1 /* 2 * Copyright © 2013 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 * 23 * Author: Jani Nikula <jani.nikula@intel.com> 24 */ 25 26 #include <linux/dmi.h> 27 #include <linux/slab.h> 28 29 #include <drm/drm_atomic_helper.h> 30 #include <drm/drm_crtc.h> 31 #include <drm/drm_edid.h> 32 #include <drm/drm_mipi_dsi.h> 33 34 #include "i915_drv.h" 35 #include "i915_reg.h" 36 #include "intel_atomic.h" 37 #include "intel_backlight.h" 38 #include "intel_connector.h" 39 #include "intel_crtc.h" 40 #include "intel_de.h" 41 #include "intel_display_types.h" 42 #include "intel_dsi.h" 43 #include "intel_dsi_vbt.h" 44 #include "intel_fifo_underrun.h" 45 #include "intel_panel.h" 46 #include "skl_scaler.h" 47 #include "vlv_dsi.h" 48 #include "vlv_dsi_pll.h" 49 #include "vlv_dsi_regs.h" 50 #include "vlv_sideband.h" 51 52 /* return pixels in terms of txbyteclkhs */ 53 static u16 txbyteclkhs(u16 pixels, int bpp, int lane_count, 54 u16 burst_mode_ratio) 55 { 56 return DIV_ROUND_UP(DIV_ROUND_UP(pixels * bpp * burst_mode_ratio, 57 8 * 100), lane_count); 58 } 59 60 /* return pixels equvalent to txbyteclkhs */ 61 static u16 pixels_from_txbyteclkhs(u16 clk_hs, int bpp, int lane_count, 62 u16 burst_mode_ratio) 63 { 64 return DIV_ROUND_UP((clk_hs * lane_count * 8 * 100), 65 (bpp * burst_mode_ratio)); 66 } 67 68 enum mipi_dsi_pixel_format pixel_format_from_register_bits(u32 fmt) 69 { 70 /* It just so happens the VBT matches register contents. */ 71 switch (fmt) { 72 case VID_MODE_FORMAT_RGB888: 73 return MIPI_DSI_FMT_RGB888; 74 case VID_MODE_FORMAT_RGB666: 75 return MIPI_DSI_FMT_RGB666; 76 case VID_MODE_FORMAT_RGB666_PACKED: 77 return MIPI_DSI_FMT_RGB666_PACKED; 78 case VID_MODE_FORMAT_RGB565: 79 return MIPI_DSI_FMT_RGB565; 80 default: 81 MISSING_CASE(fmt); 82 return MIPI_DSI_FMT_RGB666; 83 } 84 } 85 86 void vlv_dsi_wait_for_fifo_empty(struct intel_dsi *intel_dsi, enum port port) 87 { 88 struct drm_encoder *encoder = &intel_dsi->base.base; 89 struct drm_device *dev = encoder->dev; 90 struct drm_i915_private *dev_priv = to_i915(dev); 91 u32 mask; 92 93 mask = LP_CTRL_FIFO_EMPTY | HS_CTRL_FIFO_EMPTY | 94 LP_DATA_FIFO_EMPTY | HS_DATA_FIFO_EMPTY; 95 96 if (intel_de_wait_for_set(dev_priv, MIPI_GEN_FIFO_STAT(port), 97 mask, 100)) 98 drm_err(&dev_priv->drm, "DPI FIFOs are not empty\n"); 99 } 100 101 static void write_data(struct drm_i915_private *dev_priv, 102 i915_reg_t reg, 103 const u8 *data, u32 len) 104 { 105 u32 i, j; 106 107 for (i = 0; i < len; i += 4) { 108 u32 val = 0; 109 110 for (j = 0; j < min_t(u32, len - i, 4); j++) 111 val |= *data++ << 8 * j; 112 113 intel_de_write(dev_priv, reg, val); 114 } 115 } 116 117 static void read_data(struct drm_i915_private *dev_priv, 118 i915_reg_t reg, 119 u8 *data, u32 len) 120 { 121 u32 i, j; 122 123 for (i = 0; i < len; i += 4) { 124 u32 val = intel_de_read(dev_priv, reg); 125 126 for (j = 0; j < min_t(u32, len - i, 4); j++) 127 *data++ = val >> 8 * j; 128 } 129 } 130 131 static ssize_t intel_dsi_host_transfer(struct mipi_dsi_host *host, 132 const struct mipi_dsi_msg *msg) 133 { 134 struct intel_dsi_host *intel_dsi_host = to_intel_dsi_host(host); 135 struct drm_device *dev = intel_dsi_host->intel_dsi->base.base.dev; 136 struct drm_i915_private *dev_priv = to_i915(dev); 137 enum port port = intel_dsi_host->port; 138 struct mipi_dsi_packet packet; 139 ssize_t ret; 140 const u8 *header; 141 i915_reg_t data_reg, ctrl_reg; 142 u32 data_mask, ctrl_mask; 143 144 ret = mipi_dsi_create_packet(&packet, msg); 145 if (ret < 0) 146 return ret; 147 148 header = packet.header; 149 150 if (msg->flags & MIPI_DSI_MSG_USE_LPM) { 151 data_reg = MIPI_LP_GEN_DATA(port); 152 data_mask = LP_DATA_FIFO_FULL; 153 ctrl_reg = MIPI_LP_GEN_CTRL(port); 154 ctrl_mask = LP_CTRL_FIFO_FULL; 155 } else { 156 data_reg = MIPI_HS_GEN_DATA(port); 157 data_mask = HS_DATA_FIFO_FULL; 158 ctrl_reg = MIPI_HS_GEN_CTRL(port); 159 ctrl_mask = HS_CTRL_FIFO_FULL; 160 } 161 162 /* note: this is never true for reads */ 163 if (packet.payload_length) { 164 if (intel_de_wait_for_clear(dev_priv, MIPI_GEN_FIFO_STAT(port), 165 data_mask, 50)) 166 drm_err(&dev_priv->drm, 167 "Timeout waiting for HS/LP DATA FIFO !full\n"); 168 169 write_data(dev_priv, data_reg, packet.payload, 170 packet.payload_length); 171 } 172 173 if (msg->rx_len) { 174 intel_de_write(dev_priv, MIPI_INTR_STAT(port), 175 GEN_READ_DATA_AVAIL); 176 } 177 178 if (intel_de_wait_for_clear(dev_priv, MIPI_GEN_FIFO_STAT(port), 179 ctrl_mask, 50)) { 180 drm_err(&dev_priv->drm, 181 "Timeout waiting for HS/LP CTRL FIFO !full\n"); 182 } 183 184 intel_de_write(dev_priv, ctrl_reg, 185 header[2] << 16 | header[1] << 8 | header[0]); 186 187 /* ->rx_len is set only for reads */ 188 if (msg->rx_len) { 189 data_mask = GEN_READ_DATA_AVAIL; 190 if (intel_de_wait_for_set(dev_priv, MIPI_INTR_STAT(port), 191 data_mask, 50)) 192 drm_err(&dev_priv->drm, 193 "Timeout waiting for read data.\n"); 194 195 read_data(dev_priv, data_reg, msg->rx_buf, msg->rx_len); 196 } 197 198 /* XXX: fix for reads and writes */ 199 return 4 + packet.payload_length; 200 } 201 202 static int intel_dsi_host_attach(struct mipi_dsi_host *host, 203 struct mipi_dsi_device *dsi) 204 { 205 return 0; 206 } 207 208 static int intel_dsi_host_detach(struct mipi_dsi_host *host, 209 struct mipi_dsi_device *dsi) 210 { 211 return 0; 212 } 213 214 static const struct mipi_dsi_host_ops intel_dsi_host_ops = { 215 .attach = intel_dsi_host_attach, 216 .detach = intel_dsi_host_detach, 217 .transfer = intel_dsi_host_transfer, 218 }; 219 220 /* 221 * send a video mode command 222 * 223 * XXX: commands with data in MIPI_DPI_DATA? 224 */ 225 static int dpi_send_cmd(struct intel_dsi *intel_dsi, u32 cmd, bool hs, 226 enum port port) 227 { 228 struct drm_encoder *encoder = &intel_dsi->base.base; 229 struct drm_device *dev = encoder->dev; 230 struct drm_i915_private *dev_priv = to_i915(dev); 231 u32 mask; 232 233 /* XXX: pipe, hs */ 234 if (hs) 235 cmd &= ~DPI_LP_MODE; 236 else 237 cmd |= DPI_LP_MODE; 238 239 /* clear bit */ 240 intel_de_write(dev_priv, MIPI_INTR_STAT(port), SPL_PKT_SENT_INTERRUPT); 241 242 /* XXX: old code skips write if control unchanged */ 243 if (cmd == intel_de_read(dev_priv, MIPI_DPI_CONTROL(port))) 244 drm_dbg_kms(&dev_priv->drm, 245 "Same special packet %02x twice in a row.\n", cmd); 246 247 intel_de_write(dev_priv, MIPI_DPI_CONTROL(port), cmd); 248 249 mask = SPL_PKT_SENT_INTERRUPT; 250 if (intel_de_wait_for_set(dev_priv, MIPI_INTR_STAT(port), mask, 100)) 251 drm_err(&dev_priv->drm, 252 "Video mode command 0x%08x send failed.\n", cmd); 253 254 return 0; 255 } 256 257 static void band_gap_reset(struct drm_i915_private *dev_priv) 258 { 259 vlv_flisdsi_get(dev_priv); 260 261 vlv_flisdsi_write(dev_priv, 0x08, 0x0001); 262 vlv_flisdsi_write(dev_priv, 0x0F, 0x0005); 263 vlv_flisdsi_write(dev_priv, 0x0F, 0x0025); 264 udelay(150); 265 vlv_flisdsi_write(dev_priv, 0x0F, 0x0000); 266 vlv_flisdsi_write(dev_priv, 0x08, 0x0000); 267 268 vlv_flisdsi_put(dev_priv); 269 } 270 271 static int intel_dsi_compute_config(struct intel_encoder *encoder, 272 struct intel_crtc_state *pipe_config, 273 struct drm_connector_state *conn_state) 274 { 275 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 276 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 277 struct intel_connector *intel_connector = intel_dsi->attached_connector; 278 struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode; 279 int ret; 280 281 drm_dbg_kms(&dev_priv->drm, "\n"); 282 pipe_config->sink_format = INTEL_OUTPUT_FORMAT_RGB; 283 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; 284 285 ret = intel_panel_compute_config(intel_connector, adjusted_mode); 286 if (ret) 287 return ret; 288 289 ret = intel_panel_fitting(pipe_config, conn_state); 290 if (ret) 291 return ret; 292 293 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN) 294 return -EINVAL; 295 296 /* DSI uses short packets for sync events, so clear mode flags for DSI */ 297 adjusted_mode->flags = 0; 298 299 if (intel_dsi->pixel_format == MIPI_DSI_FMT_RGB888) 300 pipe_config->pipe_bpp = 24; 301 else 302 pipe_config->pipe_bpp = 18; 303 304 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) { 305 /* Enable Frame time stamp based scanline reporting */ 306 pipe_config->mode_flags |= 307 I915_MODE_FLAG_GET_SCANLINE_FROM_TIMESTAMP; 308 309 /* Dual link goes to DSI transcoder A. */ 310 if (intel_dsi->ports == BIT(PORT_C)) 311 pipe_config->cpu_transcoder = TRANSCODER_DSI_C; 312 else 313 pipe_config->cpu_transcoder = TRANSCODER_DSI_A; 314 315 ret = bxt_dsi_pll_compute(encoder, pipe_config); 316 if (ret) 317 return -EINVAL; 318 } else { 319 ret = vlv_dsi_pll_compute(encoder, pipe_config); 320 if (ret) 321 return -EINVAL; 322 } 323 324 pipe_config->clock_set = true; 325 326 return 0; 327 } 328 329 static bool glk_dsi_enable_io(struct intel_encoder *encoder) 330 { 331 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 332 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 333 enum port port; 334 bool cold_boot = false; 335 336 /* Set the MIPI mode 337 * If MIPI_Mode is off, then writing to LP_Wake bit is not reflecting. 338 * Power ON MIPI IO first and then write into IO reset and LP wake bits 339 */ 340 for_each_dsi_port(port, intel_dsi->ports) 341 intel_de_rmw(dev_priv, MIPI_CTRL(port), 0, GLK_MIPIIO_ENABLE); 342 343 /* Put the IO into reset */ 344 intel_de_rmw(dev_priv, MIPI_CTRL(PORT_A), GLK_MIPIIO_RESET_RELEASED, 0); 345 346 /* Program LP Wake */ 347 for_each_dsi_port(port, intel_dsi->ports) { 348 u32 tmp = intel_de_read(dev_priv, MIPI_DEVICE_READY(port)); 349 intel_de_rmw(dev_priv, MIPI_CTRL(port), 350 GLK_LP_WAKE, (tmp & DEVICE_READY) ? GLK_LP_WAKE : 0); 351 } 352 353 /* Wait for Pwr ACK */ 354 for_each_dsi_port(port, intel_dsi->ports) { 355 if (intel_de_wait_for_set(dev_priv, MIPI_CTRL(port), 356 GLK_MIPIIO_PORT_POWERED, 20)) 357 drm_err(&dev_priv->drm, "MIPIO port is powergated\n"); 358 } 359 360 /* Check for cold boot scenario */ 361 for_each_dsi_port(port, intel_dsi->ports) { 362 cold_boot |= 363 !(intel_de_read(dev_priv, MIPI_DEVICE_READY(port)) & DEVICE_READY); 364 } 365 366 return cold_boot; 367 } 368 369 static void glk_dsi_device_ready(struct intel_encoder *encoder) 370 { 371 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 372 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 373 enum port port; 374 375 /* Wait for MIPI PHY status bit to set */ 376 for_each_dsi_port(port, intel_dsi->ports) { 377 if (intel_de_wait_for_set(dev_priv, MIPI_CTRL(port), 378 GLK_PHY_STATUS_PORT_READY, 20)) 379 drm_err(&dev_priv->drm, "PHY is not ON\n"); 380 } 381 382 /* Get IO out of reset */ 383 intel_de_rmw(dev_priv, MIPI_CTRL(PORT_A), 0, GLK_MIPIIO_RESET_RELEASED); 384 385 /* Get IO out of Low power state*/ 386 for_each_dsi_port(port, intel_dsi->ports) { 387 if (!(intel_de_read(dev_priv, MIPI_DEVICE_READY(port)) & DEVICE_READY)) { 388 intel_de_rmw(dev_priv, MIPI_DEVICE_READY(port), 389 ULPS_STATE_MASK, DEVICE_READY); 390 usleep_range(10, 15); 391 } else { 392 /* Enter ULPS */ 393 intel_de_rmw(dev_priv, MIPI_DEVICE_READY(port), 394 ULPS_STATE_MASK, ULPS_STATE_ENTER | DEVICE_READY); 395 396 /* Wait for ULPS active */ 397 if (intel_de_wait_for_clear(dev_priv, MIPI_CTRL(port), 398 GLK_ULPS_NOT_ACTIVE, 20)) 399 drm_err(&dev_priv->drm, "ULPS not active\n"); 400 401 /* Exit ULPS */ 402 intel_de_rmw(dev_priv, MIPI_DEVICE_READY(port), 403 ULPS_STATE_MASK, ULPS_STATE_EXIT | DEVICE_READY); 404 405 /* Enter Normal Mode */ 406 intel_de_rmw(dev_priv, MIPI_DEVICE_READY(port), 407 ULPS_STATE_MASK, 408 ULPS_STATE_NORMAL_OPERATION | DEVICE_READY); 409 410 intel_de_rmw(dev_priv, MIPI_CTRL(port), GLK_LP_WAKE, 0); 411 } 412 } 413 414 /* Wait for Stop state */ 415 for_each_dsi_port(port, intel_dsi->ports) { 416 if (intel_de_wait_for_set(dev_priv, MIPI_CTRL(port), 417 GLK_DATA_LANE_STOP_STATE, 20)) 418 drm_err(&dev_priv->drm, 419 "Date lane not in STOP state\n"); 420 } 421 422 /* Wait for AFE LATCH */ 423 for_each_dsi_port(port, intel_dsi->ports) { 424 if (intel_de_wait_for_set(dev_priv, BXT_MIPI_PORT_CTRL(port), 425 AFE_LATCHOUT, 20)) 426 drm_err(&dev_priv->drm, 427 "D-PHY not entering LP-11 state\n"); 428 } 429 } 430 431 static void bxt_dsi_device_ready(struct intel_encoder *encoder) 432 { 433 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 434 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 435 enum port port; 436 u32 val; 437 438 drm_dbg_kms(&dev_priv->drm, "\n"); 439 440 /* Enable MIPI PHY transparent latch */ 441 for_each_dsi_port(port, intel_dsi->ports) { 442 intel_de_rmw(dev_priv, BXT_MIPI_PORT_CTRL(port), 0, LP_OUTPUT_HOLD); 443 usleep_range(2000, 2500); 444 } 445 446 /* Clear ULPS and set device ready */ 447 for_each_dsi_port(port, intel_dsi->ports) { 448 val = intel_de_read(dev_priv, MIPI_DEVICE_READY(port)); 449 val &= ~ULPS_STATE_MASK; 450 intel_de_write(dev_priv, MIPI_DEVICE_READY(port), val); 451 usleep_range(2000, 2500); 452 val |= DEVICE_READY; 453 intel_de_write(dev_priv, MIPI_DEVICE_READY(port), val); 454 } 455 } 456 457 static void vlv_dsi_device_ready(struct intel_encoder *encoder) 458 { 459 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 460 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 461 enum port port; 462 463 drm_dbg_kms(&dev_priv->drm, "\n"); 464 465 vlv_flisdsi_get(dev_priv); 466 /* program rcomp for compliance, reduce from 50 ohms to 45 ohms 467 * needed everytime after power gate */ 468 vlv_flisdsi_write(dev_priv, 0x04, 0x0004); 469 vlv_flisdsi_put(dev_priv); 470 471 /* bandgap reset is needed after everytime we do power gate */ 472 band_gap_reset(dev_priv); 473 474 for_each_dsi_port(port, intel_dsi->ports) { 475 476 intel_de_write(dev_priv, MIPI_DEVICE_READY(port), 477 ULPS_STATE_ENTER); 478 usleep_range(2500, 3000); 479 480 /* Enable MIPI PHY transparent latch 481 * Common bit for both MIPI Port A & MIPI Port C 482 * No similar bit in MIPI Port C reg 483 */ 484 intel_de_rmw(dev_priv, MIPI_PORT_CTRL(PORT_A), 0, LP_OUTPUT_HOLD); 485 usleep_range(1000, 1500); 486 487 intel_de_write(dev_priv, MIPI_DEVICE_READY(port), 488 ULPS_STATE_EXIT); 489 usleep_range(2500, 3000); 490 491 intel_de_write(dev_priv, MIPI_DEVICE_READY(port), 492 DEVICE_READY); 493 usleep_range(2500, 3000); 494 } 495 } 496 497 static void intel_dsi_device_ready(struct intel_encoder *encoder) 498 { 499 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 500 501 if (IS_GEMINILAKE(dev_priv)) 502 glk_dsi_device_ready(encoder); 503 else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) 504 bxt_dsi_device_ready(encoder); 505 else 506 vlv_dsi_device_ready(encoder); 507 } 508 509 static void glk_dsi_enter_low_power_mode(struct intel_encoder *encoder) 510 { 511 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 512 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 513 enum port port; 514 515 /* Enter ULPS */ 516 for_each_dsi_port(port, intel_dsi->ports) 517 intel_de_rmw(dev_priv, MIPI_DEVICE_READY(port), 518 ULPS_STATE_MASK, ULPS_STATE_ENTER | DEVICE_READY); 519 520 /* Wait for MIPI PHY status bit to unset */ 521 for_each_dsi_port(port, intel_dsi->ports) { 522 if (intel_de_wait_for_clear(dev_priv, MIPI_CTRL(port), 523 GLK_PHY_STATUS_PORT_READY, 20)) 524 drm_err(&dev_priv->drm, "PHY is not turning OFF\n"); 525 } 526 527 /* Wait for Pwr ACK bit to unset */ 528 for_each_dsi_port(port, intel_dsi->ports) { 529 if (intel_de_wait_for_clear(dev_priv, MIPI_CTRL(port), 530 GLK_MIPIIO_PORT_POWERED, 20)) 531 drm_err(&dev_priv->drm, 532 "MIPI IO Port is not powergated\n"); 533 } 534 } 535 536 static void glk_dsi_disable_mipi_io(struct intel_encoder *encoder) 537 { 538 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 539 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 540 enum port port; 541 542 /* Put the IO into reset */ 543 intel_de_rmw(dev_priv, MIPI_CTRL(PORT_A), GLK_MIPIIO_RESET_RELEASED, 0); 544 545 /* Wait for MIPI PHY status bit to unset */ 546 for_each_dsi_port(port, intel_dsi->ports) { 547 if (intel_de_wait_for_clear(dev_priv, MIPI_CTRL(port), 548 GLK_PHY_STATUS_PORT_READY, 20)) 549 drm_err(&dev_priv->drm, "PHY is not turning OFF\n"); 550 } 551 552 /* Clear MIPI mode */ 553 for_each_dsi_port(port, intel_dsi->ports) 554 intel_de_rmw(dev_priv, MIPI_CTRL(port), GLK_MIPIIO_ENABLE, 0); 555 } 556 557 static void glk_dsi_clear_device_ready(struct intel_encoder *encoder) 558 { 559 glk_dsi_enter_low_power_mode(encoder); 560 glk_dsi_disable_mipi_io(encoder); 561 } 562 563 static i915_reg_t port_ctrl_reg(struct drm_i915_private *i915, enum port port) 564 { 565 return IS_GEMINILAKE(i915) || IS_BROXTON(i915) ? 566 BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(port); 567 } 568 569 static void vlv_dsi_clear_device_ready(struct intel_encoder *encoder) 570 { 571 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 572 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 573 enum port port; 574 575 drm_dbg_kms(&dev_priv->drm, "\n"); 576 for_each_dsi_port(port, intel_dsi->ports) { 577 /* Common bit for both MIPI Port A & MIPI Port C on VLV/CHV */ 578 i915_reg_t port_ctrl = IS_BROXTON(dev_priv) ? 579 BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(PORT_A); 580 581 intel_de_write(dev_priv, MIPI_DEVICE_READY(port), 582 DEVICE_READY | ULPS_STATE_ENTER); 583 usleep_range(2000, 2500); 584 585 intel_de_write(dev_priv, MIPI_DEVICE_READY(port), 586 DEVICE_READY | ULPS_STATE_EXIT); 587 usleep_range(2000, 2500); 588 589 intel_de_write(dev_priv, MIPI_DEVICE_READY(port), 590 DEVICE_READY | ULPS_STATE_ENTER); 591 usleep_range(2000, 2500); 592 593 /* 594 * On VLV/CHV, wait till Clock lanes are in LP-00 state for MIPI 595 * Port A only. MIPI Port C has no similar bit for checking. 596 */ 597 if ((IS_BROXTON(dev_priv) || port == PORT_A) && 598 intel_de_wait_for_clear(dev_priv, port_ctrl, 599 AFE_LATCHOUT, 30)) 600 drm_err(&dev_priv->drm, "DSI LP not going Low\n"); 601 602 /* Disable MIPI PHY transparent latch */ 603 intel_de_rmw(dev_priv, port_ctrl, LP_OUTPUT_HOLD, 0); 604 usleep_range(1000, 1500); 605 606 intel_de_write(dev_priv, MIPI_DEVICE_READY(port), 0x00); 607 usleep_range(2000, 2500); 608 } 609 } 610 611 static void intel_dsi_port_enable(struct intel_encoder *encoder, 612 const struct intel_crtc_state *crtc_state) 613 { 614 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 615 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 616 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 617 enum port port; 618 619 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) { 620 u32 temp = intel_dsi->pixel_overlap; 621 622 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) { 623 for_each_dsi_port(port, intel_dsi->ports) 624 intel_de_rmw(dev_priv, MIPI_CTRL(port), 625 BXT_PIXEL_OVERLAP_CNT_MASK, 626 temp << BXT_PIXEL_OVERLAP_CNT_SHIFT); 627 } else { 628 intel_de_rmw(dev_priv, VLV_CHICKEN_3, 629 PIXEL_OVERLAP_CNT_MASK, 630 temp << PIXEL_OVERLAP_CNT_SHIFT); 631 } 632 } 633 634 for_each_dsi_port(port, intel_dsi->ports) { 635 i915_reg_t port_ctrl = port_ctrl_reg(dev_priv, port); 636 u32 temp; 637 638 temp = intel_de_read(dev_priv, port_ctrl); 639 640 temp &= ~LANE_CONFIGURATION_MASK; 641 temp &= ~DUAL_LINK_MODE_MASK; 642 643 if (intel_dsi->ports == (BIT(PORT_A) | BIT(PORT_C))) { 644 temp |= (intel_dsi->dual_link - 1) 645 << DUAL_LINK_MODE_SHIFT; 646 if (IS_BROXTON(dev_priv)) 647 temp |= LANE_CONFIGURATION_DUAL_LINK_A; 648 else 649 temp |= crtc->pipe ? 650 LANE_CONFIGURATION_DUAL_LINK_B : 651 LANE_CONFIGURATION_DUAL_LINK_A; 652 } 653 654 if (intel_dsi->pixel_format != MIPI_DSI_FMT_RGB888) 655 temp |= DITHERING_ENABLE; 656 657 /* assert ip_tg_enable signal */ 658 intel_de_write(dev_priv, port_ctrl, temp | DPI_ENABLE); 659 intel_de_posting_read(dev_priv, port_ctrl); 660 } 661 } 662 663 static void intel_dsi_port_disable(struct intel_encoder *encoder) 664 { 665 struct drm_device *dev = encoder->base.dev; 666 struct drm_i915_private *dev_priv = to_i915(dev); 667 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 668 enum port port; 669 670 for_each_dsi_port(port, intel_dsi->ports) { 671 i915_reg_t port_ctrl = port_ctrl_reg(dev_priv, port); 672 673 /* de-assert ip_tg_enable signal */ 674 intel_de_rmw(dev_priv, port_ctrl, DPI_ENABLE, 0); 675 intel_de_posting_read(dev_priv, port_ctrl); 676 } 677 } 678 static void intel_dsi_prepare(struct intel_encoder *intel_encoder, 679 const struct intel_crtc_state *pipe_config); 680 static void intel_dsi_unprepare(struct intel_encoder *encoder); 681 682 /* 683 * Panel enable/disable sequences from the VBT spec. 684 * 685 * Note the spec has AssertReset / DeassertReset swapped from their 686 * usual naming. We use the normal names to avoid confusion (so below 687 * they are swapped compared to the spec). 688 * 689 * Steps starting with MIPI refer to VBT sequences, note that for v2 690 * VBTs several steps which have a VBT in v2 are expected to be handled 691 * directly by the driver, by directly driving gpios for example. 692 * 693 * v2 video mode seq v3 video mode seq command mode seq 694 * - power on - MIPIPanelPowerOn - power on 695 * - wait t1+t2 - wait t1+t2 696 * - MIPIDeassertResetPin - MIPIDeassertResetPin - MIPIDeassertResetPin 697 * - io lines to lp-11 - io lines to lp-11 - io lines to lp-11 698 * - MIPISendInitialDcsCmds - MIPISendInitialDcsCmds - MIPISendInitialDcsCmds 699 * - MIPITearOn 700 * - MIPIDisplayOn 701 * - turn on DPI - turn on DPI - set pipe to dsr mode 702 * - MIPIDisplayOn - MIPIDisplayOn 703 * - wait t5 - wait t5 704 * - backlight on - MIPIBacklightOn - backlight on 705 * ... ... ... issue mem cmds ... 706 * - backlight off - MIPIBacklightOff - backlight off 707 * - wait t6 - wait t6 708 * - MIPIDisplayOff 709 * - turn off DPI - turn off DPI - disable pipe dsr mode 710 * - MIPITearOff 711 * - MIPIDisplayOff - MIPIDisplayOff 712 * - io lines to lp-00 - io lines to lp-00 - io lines to lp-00 713 * - MIPIAssertResetPin - MIPIAssertResetPin - MIPIAssertResetPin 714 * - wait t3 - wait t3 715 * - power off - MIPIPanelPowerOff - power off 716 * - wait t4 - wait t4 717 */ 718 719 /* 720 * DSI port enable has to be done before pipe and plane enable, so we do it in 721 * the pre_enable hook instead of the enable hook. 722 */ 723 static void intel_dsi_pre_enable(struct intel_atomic_state *state, 724 struct intel_encoder *encoder, 725 const struct intel_crtc_state *pipe_config, 726 const struct drm_connector_state *conn_state) 727 { 728 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 729 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 730 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 731 enum pipe pipe = crtc->pipe; 732 enum port port; 733 bool glk_cold_boot = false; 734 735 drm_dbg_kms(&dev_priv->drm, "\n"); 736 737 intel_dsi_wait_panel_power_cycle(intel_dsi); 738 739 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); 740 741 /* 742 * The BIOS may leave the PLL in a wonky state where it doesn't 743 * lock. It needs to be fully powered down to fix it. 744 */ 745 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) { 746 bxt_dsi_pll_disable(encoder); 747 bxt_dsi_pll_enable(encoder, pipe_config); 748 } else { 749 vlv_dsi_pll_disable(encoder); 750 vlv_dsi_pll_enable(encoder, pipe_config); 751 } 752 753 if (IS_BROXTON(dev_priv)) { 754 /* Add MIPI IO reset programming for modeset */ 755 intel_de_rmw(dev_priv, BXT_P_CR_GT_DISP_PWRON, 0, MIPIO_RST_CTRL); 756 757 /* Power up DSI regulator */ 758 intel_de_write(dev_priv, BXT_P_DSI_REGULATOR_CFG, STAP_SELECT); 759 intel_de_write(dev_priv, BXT_P_DSI_REGULATOR_TX_CTRL, 0); 760 } 761 762 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { 763 /* Disable DPOunit clock gating, can stall pipe */ 764 intel_de_rmw(dev_priv, DSPCLK_GATE_D(dev_priv), 765 0, DPOUNIT_CLOCK_GATE_DISABLE); 766 } 767 768 if (!IS_GEMINILAKE(dev_priv)) 769 intel_dsi_prepare(encoder, pipe_config); 770 771 /* Give the panel time to power-on and then deassert its reset */ 772 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_POWER_ON); 773 msleep(intel_dsi->panel_on_delay); 774 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DEASSERT_RESET); 775 776 if (IS_GEMINILAKE(dev_priv)) { 777 glk_cold_boot = glk_dsi_enable_io(encoder); 778 779 /* Prepare port in cold boot(s3/s4) scenario */ 780 if (glk_cold_boot) 781 intel_dsi_prepare(encoder, pipe_config); 782 } 783 784 /* Put device in ready state (LP-11) */ 785 intel_dsi_device_ready(encoder); 786 787 /* Prepare port in normal boot scenario */ 788 if (IS_GEMINILAKE(dev_priv) && !glk_cold_boot) 789 intel_dsi_prepare(encoder, pipe_config); 790 791 /* Send initialization commands in LP mode */ 792 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_INIT_OTP); 793 794 /* 795 * Enable port in pre-enable phase itself because as per hw team 796 * recommendation, port should be enabled before plane & pipe 797 */ 798 if (is_cmd_mode(intel_dsi)) { 799 for_each_dsi_port(port, intel_dsi->ports) 800 intel_de_write(dev_priv, 801 MIPI_MAX_RETURN_PKT_SIZE(port), 8 * 4); 802 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_TEAR_ON); 803 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DISPLAY_ON); 804 } else { 805 msleep(20); /* XXX */ 806 for_each_dsi_port(port, intel_dsi->ports) 807 dpi_send_cmd(intel_dsi, TURN_ON, false, port); 808 msleep(100); 809 810 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DISPLAY_ON); 811 812 intel_dsi_port_enable(encoder, pipe_config); 813 } 814 815 intel_backlight_enable(pipe_config, conn_state); 816 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_BACKLIGHT_ON); 817 } 818 819 static void bxt_dsi_enable(struct intel_atomic_state *state, 820 struct intel_encoder *encoder, 821 const struct intel_crtc_state *crtc_state, 822 const struct drm_connector_state *conn_state) 823 { 824 intel_crtc_vblank_on(crtc_state); 825 } 826 827 /* 828 * DSI port disable has to be done after pipe and plane disable, so we do it in 829 * the post_disable hook. 830 */ 831 static void intel_dsi_disable(struct intel_atomic_state *state, 832 struct intel_encoder *encoder, 833 const struct intel_crtc_state *old_crtc_state, 834 const struct drm_connector_state *old_conn_state) 835 { 836 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 837 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 838 enum port port; 839 840 drm_dbg_kms(&i915->drm, "\n"); 841 842 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_BACKLIGHT_OFF); 843 intel_backlight_disable(old_conn_state); 844 845 /* 846 * According to the spec we should send SHUTDOWN before 847 * MIPI_SEQ_DISPLAY_OFF only for v3+ VBTs, but field testing 848 * has shown that the v3 sequence works for v2 VBTs too 849 */ 850 if (is_vid_mode(intel_dsi)) { 851 /* Send Shutdown command to the panel in LP mode */ 852 for_each_dsi_port(port, intel_dsi->ports) 853 dpi_send_cmd(intel_dsi, SHUTDOWN, false, port); 854 msleep(10); 855 } 856 } 857 858 static void intel_dsi_clear_device_ready(struct intel_encoder *encoder) 859 { 860 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 861 862 if (IS_GEMINILAKE(dev_priv)) 863 glk_dsi_clear_device_ready(encoder); 864 else 865 vlv_dsi_clear_device_ready(encoder); 866 } 867 868 static void intel_dsi_post_disable(struct intel_atomic_state *state, 869 struct intel_encoder *encoder, 870 const struct intel_crtc_state *old_crtc_state, 871 const struct drm_connector_state *old_conn_state) 872 { 873 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 874 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 875 enum port port; 876 877 drm_dbg_kms(&dev_priv->drm, "\n"); 878 879 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) { 880 intel_crtc_vblank_off(old_crtc_state); 881 882 skl_scaler_disable(old_crtc_state); 883 } 884 885 if (is_vid_mode(intel_dsi)) { 886 for_each_dsi_port(port, intel_dsi->ports) 887 vlv_dsi_wait_for_fifo_empty(intel_dsi, port); 888 889 intel_dsi_port_disable(encoder); 890 usleep_range(2000, 5000); 891 } 892 893 intel_dsi_unprepare(encoder); 894 895 /* 896 * if disable packets are sent before sending shutdown packet then in 897 * some next enable sequence send turn on packet error is observed 898 */ 899 if (is_cmd_mode(intel_dsi)) 900 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_TEAR_OFF); 901 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DISPLAY_OFF); 902 903 /* Transition to LP-00 */ 904 intel_dsi_clear_device_ready(encoder); 905 906 if (IS_BROXTON(dev_priv)) { 907 /* Power down DSI regulator to save power */ 908 intel_de_write(dev_priv, BXT_P_DSI_REGULATOR_CFG, STAP_SELECT); 909 intel_de_write(dev_priv, BXT_P_DSI_REGULATOR_TX_CTRL, 910 HS_IO_CTRL_SELECT); 911 912 /* Add MIPI IO reset programming for modeset */ 913 intel_de_rmw(dev_priv, BXT_P_CR_GT_DISP_PWRON, MIPIO_RST_CTRL, 0); 914 } 915 916 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) { 917 bxt_dsi_pll_disable(encoder); 918 } else { 919 vlv_dsi_pll_disable(encoder); 920 921 intel_de_rmw(dev_priv, DSPCLK_GATE_D(dev_priv), 922 DPOUNIT_CLOCK_GATE_DISABLE, 0); 923 } 924 925 /* Assert reset */ 926 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_ASSERT_RESET); 927 928 msleep(intel_dsi->panel_off_delay); 929 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_POWER_OFF); 930 931 intel_dsi->panel_power_off_time = ktime_get_boottime(); 932 } 933 934 static bool intel_dsi_get_hw_state(struct intel_encoder *encoder, 935 enum pipe *pipe) 936 { 937 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 938 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 939 intel_wakeref_t wakeref; 940 enum port port; 941 bool active = false; 942 943 drm_dbg_kms(&dev_priv->drm, "\n"); 944 945 wakeref = intel_display_power_get_if_enabled(dev_priv, 946 encoder->power_domain); 947 if (!wakeref) 948 return false; 949 950 /* 951 * On Broxton the PLL needs to be enabled with a valid divider 952 * configuration, otherwise accessing DSI registers will hang the 953 * machine. See BSpec North Display Engine registers/MIPI[BXT]. 954 */ 955 if ((IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) && 956 !bxt_dsi_pll_is_enabled(dev_priv)) 957 goto out_put_power; 958 959 /* XXX: this only works for one DSI output */ 960 for_each_dsi_port(port, intel_dsi->ports) { 961 i915_reg_t port_ctrl = port_ctrl_reg(dev_priv, port); 962 bool enabled = intel_de_read(dev_priv, port_ctrl) & DPI_ENABLE; 963 964 /* 965 * Due to some hardware limitations on VLV/CHV, the DPI enable 966 * bit in port C control register does not get set. As a 967 * workaround, check pipe B conf instead. 968 */ 969 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && 970 port == PORT_C) 971 enabled = intel_de_read(dev_priv, TRANSCONF(PIPE_B)) & TRANSCONF_ENABLE; 972 973 /* Try command mode if video mode not enabled */ 974 if (!enabled) { 975 u32 tmp = intel_de_read(dev_priv, 976 MIPI_DSI_FUNC_PRG(port)); 977 enabled = tmp & CMD_MODE_DATA_WIDTH_MASK; 978 } 979 980 if (!enabled) 981 continue; 982 983 if (!(intel_de_read(dev_priv, MIPI_DEVICE_READY(port)) & DEVICE_READY)) 984 continue; 985 986 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) { 987 u32 tmp = intel_de_read(dev_priv, MIPI_CTRL(port)); 988 tmp &= BXT_PIPE_SELECT_MASK; 989 tmp >>= BXT_PIPE_SELECT_SHIFT; 990 991 if (drm_WARN_ON(&dev_priv->drm, tmp > PIPE_C)) 992 continue; 993 994 *pipe = tmp; 995 } else { 996 *pipe = port == PORT_A ? PIPE_A : PIPE_B; 997 } 998 999 active = true; 1000 break; 1001 } 1002 1003 out_put_power: 1004 intel_display_power_put(dev_priv, encoder->power_domain, wakeref); 1005 1006 return active; 1007 } 1008 1009 static void bxt_dsi_get_pipe_config(struct intel_encoder *encoder, 1010 struct intel_crtc_state *pipe_config) 1011 { 1012 struct drm_device *dev = encoder->base.dev; 1013 struct drm_i915_private *dev_priv = to_i915(dev); 1014 struct drm_display_mode *adjusted_mode = 1015 &pipe_config->hw.adjusted_mode; 1016 struct drm_display_mode *adjusted_mode_sw; 1017 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 1018 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1019 unsigned int lane_count = intel_dsi->lane_count; 1020 unsigned int bpp, fmt; 1021 enum port port; 1022 u16 hactive, hfp, hsync, hbp, vfp, vsync; 1023 u16 hfp_sw, hsync_sw, hbp_sw; 1024 u16 crtc_htotal_sw, crtc_hsync_start_sw, crtc_hsync_end_sw, 1025 crtc_hblank_start_sw, crtc_hblank_end_sw; 1026 1027 /* FIXME: hw readout should not depend on SW state */ 1028 adjusted_mode_sw = &crtc->config->hw.adjusted_mode; 1029 1030 /* 1031 * Atleast one port is active as encoder->get_config called only if 1032 * encoder->get_hw_state() returns true. 1033 */ 1034 for_each_dsi_port(port, intel_dsi->ports) { 1035 if (intel_de_read(dev_priv, BXT_MIPI_PORT_CTRL(port)) & DPI_ENABLE) 1036 break; 1037 } 1038 1039 fmt = intel_de_read(dev_priv, MIPI_DSI_FUNC_PRG(port)) & VID_MODE_FORMAT_MASK; 1040 bpp = mipi_dsi_pixel_format_to_bpp( 1041 pixel_format_from_register_bits(fmt)); 1042 1043 pipe_config->pipe_bpp = bdw_get_pipe_misc_bpp(crtc); 1044 1045 /* Enable Frame time stamo based scanline reporting */ 1046 pipe_config->mode_flags |= 1047 I915_MODE_FLAG_GET_SCANLINE_FROM_TIMESTAMP; 1048 1049 /* In terms of pixels */ 1050 adjusted_mode->crtc_hdisplay = 1051 intel_de_read(dev_priv, 1052 BXT_MIPI_TRANS_HACTIVE(port)); 1053 adjusted_mode->crtc_vdisplay = 1054 intel_de_read(dev_priv, 1055 BXT_MIPI_TRANS_VACTIVE(port)); 1056 adjusted_mode->crtc_vtotal = 1057 intel_de_read(dev_priv, 1058 BXT_MIPI_TRANS_VTOTAL(port)); 1059 1060 hactive = adjusted_mode->crtc_hdisplay; 1061 hfp = intel_de_read(dev_priv, MIPI_HFP_COUNT(port)); 1062 1063 /* 1064 * Meaningful for video mode non-burst sync pulse mode only, 1065 * can be zero for non-burst sync events and burst modes 1066 */ 1067 hsync = intel_de_read(dev_priv, MIPI_HSYNC_PADDING_COUNT(port)); 1068 hbp = intel_de_read(dev_priv, MIPI_HBP_COUNT(port)); 1069 1070 /* harizontal values are in terms of high speed byte clock */ 1071 hfp = pixels_from_txbyteclkhs(hfp, bpp, lane_count, 1072 intel_dsi->burst_mode_ratio); 1073 hsync = pixels_from_txbyteclkhs(hsync, bpp, lane_count, 1074 intel_dsi->burst_mode_ratio); 1075 hbp = pixels_from_txbyteclkhs(hbp, bpp, lane_count, 1076 intel_dsi->burst_mode_ratio); 1077 1078 if (intel_dsi->dual_link) { 1079 hfp *= 2; 1080 hsync *= 2; 1081 hbp *= 2; 1082 } 1083 1084 /* vertical values are in terms of lines */ 1085 vfp = intel_de_read(dev_priv, MIPI_VFP_COUNT(port)); 1086 vsync = intel_de_read(dev_priv, MIPI_VSYNC_PADDING_COUNT(port)); 1087 1088 adjusted_mode->crtc_htotal = hactive + hfp + hsync + hbp; 1089 adjusted_mode->crtc_hsync_start = hfp + adjusted_mode->crtc_hdisplay; 1090 adjusted_mode->crtc_hsync_end = hsync + adjusted_mode->crtc_hsync_start; 1091 adjusted_mode->crtc_hblank_start = adjusted_mode->crtc_hdisplay; 1092 adjusted_mode->crtc_hblank_end = adjusted_mode->crtc_htotal; 1093 1094 adjusted_mode->crtc_vsync_start = vfp + adjusted_mode->crtc_vdisplay; 1095 adjusted_mode->crtc_vsync_end = vsync + adjusted_mode->crtc_vsync_start; 1096 adjusted_mode->crtc_vblank_start = adjusted_mode->crtc_vdisplay; 1097 adjusted_mode->crtc_vblank_end = adjusted_mode->crtc_vtotal; 1098 1099 /* 1100 * In BXT DSI there is no regs programmed with few horizontal timings 1101 * in Pixels but txbyteclkhs.. So retrieval process adds some 1102 * ROUND_UP ERRORS in the process of PIXELS<==>txbyteclkhs. 1103 * Actually here for the given adjusted_mode, we are calculating the 1104 * value programmed to the port and then back to the horizontal timing 1105 * param in pixels. This is the expected value, including roundup errors 1106 * And if that is same as retrieved value from port, then 1107 * (HW state) adjusted_mode's horizontal timings are corrected to 1108 * match with SW state to nullify the errors. 1109 */ 1110 /* Calculating the value programmed to the Port register */ 1111 hfp_sw = adjusted_mode_sw->crtc_hsync_start - 1112 adjusted_mode_sw->crtc_hdisplay; 1113 hsync_sw = adjusted_mode_sw->crtc_hsync_end - 1114 adjusted_mode_sw->crtc_hsync_start; 1115 hbp_sw = adjusted_mode_sw->crtc_htotal - 1116 adjusted_mode_sw->crtc_hsync_end; 1117 1118 if (intel_dsi->dual_link) { 1119 hfp_sw /= 2; 1120 hsync_sw /= 2; 1121 hbp_sw /= 2; 1122 } 1123 1124 hfp_sw = txbyteclkhs(hfp_sw, bpp, lane_count, 1125 intel_dsi->burst_mode_ratio); 1126 hsync_sw = txbyteclkhs(hsync_sw, bpp, lane_count, 1127 intel_dsi->burst_mode_ratio); 1128 hbp_sw = txbyteclkhs(hbp_sw, bpp, lane_count, 1129 intel_dsi->burst_mode_ratio); 1130 1131 /* Reverse calculating the adjusted mode parameters from port reg vals*/ 1132 hfp_sw = pixels_from_txbyteclkhs(hfp_sw, bpp, lane_count, 1133 intel_dsi->burst_mode_ratio); 1134 hsync_sw = pixels_from_txbyteclkhs(hsync_sw, bpp, lane_count, 1135 intel_dsi->burst_mode_ratio); 1136 hbp_sw = pixels_from_txbyteclkhs(hbp_sw, bpp, lane_count, 1137 intel_dsi->burst_mode_ratio); 1138 1139 if (intel_dsi->dual_link) { 1140 hfp_sw *= 2; 1141 hsync_sw *= 2; 1142 hbp_sw *= 2; 1143 } 1144 1145 crtc_htotal_sw = adjusted_mode_sw->crtc_hdisplay + hfp_sw + 1146 hsync_sw + hbp_sw; 1147 crtc_hsync_start_sw = hfp_sw + adjusted_mode_sw->crtc_hdisplay; 1148 crtc_hsync_end_sw = hsync_sw + crtc_hsync_start_sw; 1149 crtc_hblank_start_sw = adjusted_mode_sw->crtc_hdisplay; 1150 crtc_hblank_end_sw = crtc_htotal_sw; 1151 1152 if (adjusted_mode->crtc_htotal == crtc_htotal_sw) 1153 adjusted_mode->crtc_htotal = adjusted_mode_sw->crtc_htotal; 1154 1155 if (adjusted_mode->crtc_hsync_start == crtc_hsync_start_sw) 1156 adjusted_mode->crtc_hsync_start = 1157 adjusted_mode_sw->crtc_hsync_start; 1158 1159 if (adjusted_mode->crtc_hsync_end == crtc_hsync_end_sw) 1160 adjusted_mode->crtc_hsync_end = 1161 adjusted_mode_sw->crtc_hsync_end; 1162 1163 if (adjusted_mode->crtc_hblank_start == crtc_hblank_start_sw) 1164 adjusted_mode->crtc_hblank_start = 1165 adjusted_mode_sw->crtc_hblank_start; 1166 1167 if (adjusted_mode->crtc_hblank_end == crtc_hblank_end_sw) 1168 adjusted_mode->crtc_hblank_end = 1169 adjusted_mode_sw->crtc_hblank_end; 1170 } 1171 1172 static void intel_dsi_get_config(struct intel_encoder *encoder, 1173 struct intel_crtc_state *pipe_config) 1174 { 1175 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1176 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1177 u32 pclk; 1178 1179 drm_dbg_kms(&dev_priv->drm, "\n"); 1180 1181 pipe_config->output_types |= BIT(INTEL_OUTPUT_DSI); 1182 1183 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) { 1184 bxt_dsi_get_pipe_config(encoder, pipe_config); 1185 pclk = bxt_dsi_get_pclk(encoder, pipe_config); 1186 } else { 1187 pclk = vlv_dsi_get_pclk(encoder, pipe_config); 1188 } 1189 1190 pipe_config->port_clock = pclk; 1191 1192 /* FIXME definitely not right for burst/cmd mode/pixel overlap */ 1193 pipe_config->hw.adjusted_mode.crtc_clock = pclk; 1194 if (intel_dsi->dual_link) 1195 pipe_config->hw.adjusted_mode.crtc_clock *= 2; 1196 } 1197 1198 /* return txclkesc cycles in terms of divider and duration in us */ 1199 static u16 txclkesc(u32 divider, unsigned int us) 1200 { 1201 switch (divider) { 1202 case ESCAPE_CLOCK_DIVIDER_1: 1203 default: 1204 return 20 * us; 1205 case ESCAPE_CLOCK_DIVIDER_2: 1206 return 10 * us; 1207 case ESCAPE_CLOCK_DIVIDER_4: 1208 return 5 * us; 1209 } 1210 } 1211 1212 static void set_dsi_timings(struct drm_encoder *encoder, 1213 const struct drm_display_mode *adjusted_mode) 1214 { 1215 struct drm_device *dev = encoder->dev; 1216 struct drm_i915_private *dev_priv = to_i915(dev); 1217 struct intel_dsi *intel_dsi = enc_to_intel_dsi(to_intel_encoder(encoder)); 1218 enum port port; 1219 unsigned int bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format); 1220 unsigned int lane_count = intel_dsi->lane_count; 1221 1222 u16 hactive, hfp, hsync, hbp, vfp, vsync, vbp; 1223 1224 hactive = adjusted_mode->crtc_hdisplay; 1225 hfp = adjusted_mode->crtc_hsync_start - adjusted_mode->crtc_hdisplay; 1226 hsync = adjusted_mode->crtc_hsync_end - adjusted_mode->crtc_hsync_start; 1227 hbp = adjusted_mode->crtc_htotal - adjusted_mode->crtc_hsync_end; 1228 1229 if (intel_dsi->dual_link) { 1230 hactive /= 2; 1231 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) 1232 hactive += intel_dsi->pixel_overlap; 1233 hfp /= 2; 1234 hsync /= 2; 1235 hbp /= 2; 1236 } 1237 1238 vfp = adjusted_mode->crtc_vsync_start - adjusted_mode->crtc_vdisplay; 1239 vsync = adjusted_mode->crtc_vsync_end - adjusted_mode->crtc_vsync_start; 1240 vbp = adjusted_mode->crtc_vtotal - adjusted_mode->crtc_vsync_end; 1241 1242 /* horizontal values are in terms of high speed byte clock */ 1243 hactive = txbyteclkhs(hactive, bpp, lane_count, 1244 intel_dsi->burst_mode_ratio); 1245 hfp = txbyteclkhs(hfp, bpp, lane_count, intel_dsi->burst_mode_ratio); 1246 hsync = txbyteclkhs(hsync, bpp, lane_count, 1247 intel_dsi->burst_mode_ratio); 1248 hbp = txbyteclkhs(hbp, bpp, lane_count, intel_dsi->burst_mode_ratio); 1249 1250 for_each_dsi_port(port, intel_dsi->ports) { 1251 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) { 1252 /* 1253 * Program hdisplay and vdisplay on MIPI transcoder. 1254 * This is different from calculated hactive and 1255 * vactive, as they are calculated per channel basis, 1256 * whereas these values should be based on resolution. 1257 */ 1258 intel_de_write(dev_priv, BXT_MIPI_TRANS_HACTIVE(port), 1259 adjusted_mode->crtc_hdisplay); 1260 intel_de_write(dev_priv, BXT_MIPI_TRANS_VACTIVE(port), 1261 adjusted_mode->crtc_vdisplay); 1262 intel_de_write(dev_priv, BXT_MIPI_TRANS_VTOTAL(port), 1263 adjusted_mode->crtc_vtotal); 1264 } 1265 1266 intel_de_write(dev_priv, MIPI_HACTIVE_AREA_COUNT(port), 1267 hactive); 1268 intel_de_write(dev_priv, MIPI_HFP_COUNT(port), hfp); 1269 1270 /* meaningful for video mode non-burst sync pulse mode only, 1271 * can be zero for non-burst sync events and burst modes */ 1272 intel_de_write(dev_priv, MIPI_HSYNC_PADDING_COUNT(port), 1273 hsync); 1274 intel_de_write(dev_priv, MIPI_HBP_COUNT(port), hbp); 1275 1276 /* vertical values are in terms of lines */ 1277 intel_de_write(dev_priv, MIPI_VFP_COUNT(port), vfp); 1278 intel_de_write(dev_priv, MIPI_VSYNC_PADDING_COUNT(port), 1279 vsync); 1280 intel_de_write(dev_priv, MIPI_VBP_COUNT(port), vbp); 1281 } 1282 } 1283 1284 static u32 pixel_format_to_reg(enum mipi_dsi_pixel_format fmt) 1285 { 1286 switch (fmt) { 1287 case MIPI_DSI_FMT_RGB888: 1288 return VID_MODE_FORMAT_RGB888; 1289 case MIPI_DSI_FMT_RGB666: 1290 return VID_MODE_FORMAT_RGB666; 1291 case MIPI_DSI_FMT_RGB666_PACKED: 1292 return VID_MODE_FORMAT_RGB666_PACKED; 1293 case MIPI_DSI_FMT_RGB565: 1294 return VID_MODE_FORMAT_RGB565; 1295 default: 1296 MISSING_CASE(fmt); 1297 return VID_MODE_FORMAT_RGB666; 1298 } 1299 } 1300 1301 static void intel_dsi_prepare(struct intel_encoder *intel_encoder, 1302 const struct intel_crtc_state *pipe_config) 1303 { 1304 struct drm_encoder *encoder = &intel_encoder->base; 1305 struct drm_device *dev = encoder->dev; 1306 struct drm_i915_private *dev_priv = to_i915(dev); 1307 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 1308 struct intel_dsi *intel_dsi = enc_to_intel_dsi(to_intel_encoder(encoder)); 1309 const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode; 1310 enum port port; 1311 unsigned int bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format); 1312 u32 val, tmp; 1313 u16 mode_hdisplay; 1314 1315 drm_dbg_kms(&dev_priv->drm, "pipe %c\n", pipe_name(crtc->pipe)); 1316 1317 mode_hdisplay = adjusted_mode->crtc_hdisplay; 1318 1319 if (intel_dsi->dual_link) { 1320 mode_hdisplay /= 2; 1321 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) 1322 mode_hdisplay += intel_dsi->pixel_overlap; 1323 } 1324 1325 for_each_dsi_port(port, intel_dsi->ports) { 1326 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { 1327 /* 1328 * escape clock divider, 20MHz, shared for A and C. 1329 * device ready must be off when doing this! txclkesc? 1330 */ 1331 tmp = intel_de_read(dev_priv, MIPI_CTRL(PORT_A)); 1332 tmp &= ~ESCAPE_CLOCK_DIVIDER_MASK; 1333 intel_de_write(dev_priv, MIPI_CTRL(PORT_A), 1334 tmp | ESCAPE_CLOCK_DIVIDER_1); 1335 1336 /* read request priority is per pipe */ 1337 tmp = intel_de_read(dev_priv, MIPI_CTRL(port)); 1338 tmp &= ~READ_REQUEST_PRIORITY_MASK; 1339 intel_de_write(dev_priv, MIPI_CTRL(port), 1340 tmp | READ_REQUEST_PRIORITY_HIGH); 1341 } else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) { 1342 enum pipe pipe = crtc->pipe; 1343 1344 intel_de_rmw(dev_priv, MIPI_CTRL(port), 1345 BXT_PIPE_SELECT_MASK, BXT_PIPE_SELECT(pipe)); 1346 } 1347 1348 /* XXX: why here, why like this? handling in irq handler?! */ 1349 intel_de_write(dev_priv, MIPI_INTR_STAT(port), 0xffffffff); 1350 intel_de_write(dev_priv, MIPI_INTR_EN(port), 0xffffffff); 1351 1352 intel_de_write(dev_priv, MIPI_DPHY_PARAM(port), 1353 intel_dsi->dphy_reg); 1354 1355 intel_de_write(dev_priv, MIPI_DPI_RESOLUTION(port), 1356 adjusted_mode->crtc_vdisplay << VERTICAL_ADDRESS_SHIFT | mode_hdisplay << HORIZONTAL_ADDRESS_SHIFT); 1357 } 1358 1359 set_dsi_timings(encoder, adjusted_mode); 1360 1361 val = intel_dsi->lane_count << DATA_LANES_PRG_REG_SHIFT; 1362 if (is_cmd_mode(intel_dsi)) { 1363 val |= intel_dsi->channel << CMD_MODE_CHANNEL_NUMBER_SHIFT; 1364 val |= CMD_MODE_DATA_WIDTH_8_BIT; /* XXX */ 1365 } else { 1366 val |= intel_dsi->channel << VID_MODE_CHANNEL_NUMBER_SHIFT; 1367 val |= pixel_format_to_reg(intel_dsi->pixel_format); 1368 } 1369 1370 tmp = 0; 1371 if (intel_dsi->eotp_pkt == 0) 1372 tmp |= EOT_DISABLE; 1373 if (intel_dsi->clock_stop) 1374 tmp |= CLOCKSTOP; 1375 1376 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) { 1377 tmp |= BXT_DPHY_DEFEATURE_EN; 1378 if (!is_cmd_mode(intel_dsi)) 1379 tmp |= BXT_DEFEATURE_DPI_FIFO_CTR; 1380 } 1381 1382 for_each_dsi_port(port, intel_dsi->ports) { 1383 intel_de_write(dev_priv, MIPI_DSI_FUNC_PRG(port), val); 1384 1385 /* timeouts for recovery. one frame IIUC. if counter expires, 1386 * EOT and stop state. */ 1387 1388 /* 1389 * In burst mode, value greater than one DPI line Time in byte 1390 * clock (txbyteclkhs) To timeout this timer 1+ of the above 1391 * said value is recommended. 1392 * 1393 * In non-burst mode, Value greater than one DPI frame time in 1394 * byte clock(txbyteclkhs) To timeout this timer 1+ of the above 1395 * said value is recommended. 1396 * 1397 * In DBI only mode, value greater than one DBI frame time in 1398 * byte clock(txbyteclkhs) To timeout this timer 1+ of the above 1399 * said value is recommended. 1400 */ 1401 1402 if (is_vid_mode(intel_dsi) && 1403 intel_dsi->video_mode == BURST_MODE) { 1404 intel_de_write(dev_priv, MIPI_HS_TX_TIMEOUT(port), 1405 txbyteclkhs(adjusted_mode->crtc_htotal, bpp, intel_dsi->lane_count, intel_dsi->burst_mode_ratio) + 1); 1406 } else { 1407 intel_de_write(dev_priv, MIPI_HS_TX_TIMEOUT(port), 1408 txbyteclkhs(adjusted_mode->crtc_vtotal * adjusted_mode->crtc_htotal, bpp, intel_dsi->lane_count, intel_dsi->burst_mode_ratio) + 1); 1409 } 1410 intel_de_write(dev_priv, MIPI_LP_RX_TIMEOUT(port), 1411 intel_dsi->lp_rx_timeout); 1412 intel_de_write(dev_priv, MIPI_TURN_AROUND_TIMEOUT(port), 1413 intel_dsi->turn_arnd_val); 1414 intel_de_write(dev_priv, MIPI_DEVICE_RESET_TIMER(port), 1415 intel_dsi->rst_timer_val); 1416 1417 /* dphy stuff */ 1418 1419 /* in terms of low power clock */ 1420 intel_de_write(dev_priv, MIPI_INIT_COUNT(port), 1421 txclkesc(intel_dsi->escape_clk_div, 100)); 1422 1423 if ((IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) && 1424 !intel_dsi->dual_link) { 1425 /* 1426 * BXT spec says write MIPI_INIT_COUNT for 1427 * both the ports, even if only one is 1428 * getting used. So write the other port 1429 * if not in dual link mode. 1430 */ 1431 intel_de_write(dev_priv, 1432 MIPI_INIT_COUNT(port == PORT_A ? PORT_C : PORT_A), 1433 intel_dsi->init_count); 1434 } 1435 1436 /* recovery disables */ 1437 intel_de_write(dev_priv, MIPI_EOT_DISABLE(port), tmp); 1438 1439 /* in terms of low power clock */ 1440 intel_de_write(dev_priv, MIPI_INIT_COUNT(port), 1441 intel_dsi->init_count); 1442 1443 /* in terms of txbyteclkhs. actual high to low switch + 1444 * MIPI_STOP_STATE_STALL * MIPI_LP_BYTECLK. 1445 * 1446 * XXX: write MIPI_STOP_STATE_STALL? 1447 */ 1448 intel_de_write(dev_priv, MIPI_HIGH_LOW_SWITCH_COUNT(port), 1449 intel_dsi->hs_to_lp_count); 1450 1451 /* XXX: low power clock equivalence in terms of byte clock. 1452 * the number of byte clocks occupied in one low power clock. 1453 * based on txbyteclkhs and txclkesc. 1454 * txclkesc time / txbyteclk time * (105 + MIPI_STOP_STATE_STALL 1455 * ) / 105.??? 1456 */ 1457 intel_de_write(dev_priv, MIPI_LP_BYTECLK(port), 1458 intel_dsi->lp_byte_clk); 1459 1460 if (IS_GEMINILAKE(dev_priv)) { 1461 intel_de_write(dev_priv, MIPI_TLPX_TIME_COUNT(port), 1462 intel_dsi->lp_byte_clk); 1463 /* Shadow of DPHY reg */ 1464 intel_de_write(dev_priv, MIPI_CLK_LANE_TIMING(port), 1465 intel_dsi->dphy_reg); 1466 } 1467 1468 /* the bw essential for transmitting 16 long packets containing 1469 * 252 bytes meant for dcs write memory command is programmed in 1470 * this register in terms of byte clocks. based on dsi transfer 1471 * rate and the number of lanes configured the time taken to 1472 * transmit 16 long packets in a dsi stream varies. */ 1473 intel_de_write(dev_priv, MIPI_DBI_BW_CTRL(port), 1474 intel_dsi->bw_timer); 1475 1476 intel_de_write(dev_priv, MIPI_CLK_LANE_SWITCH_TIME_CNT(port), 1477 intel_dsi->clk_lp_to_hs_count << LP_HS_SSW_CNT_SHIFT | intel_dsi->clk_hs_to_lp_count << HS_LP_PWR_SW_CNT_SHIFT); 1478 1479 if (is_vid_mode(intel_dsi)) { 1480 u32 fmt = intel_dsi->video_frmt_cfg_bits | IP_TG_CONFIG; 1481 1482 /* 1483 * Some panels might have resolution which is not a 1484 * multiple of 64 like 1366 x 768. Enable RANDOM 1485 * resolution support for such panels by default. 1486 */ 1487 fmt |= RANDOM_DPI_DISPLAY_RESOLUTION; 1488 1489 switch (intel_dsi->video_mode) { 1490 default: 1491 MISSING_CASE(intel_dsi->video_mode); 1492 fallthrough; 1493 case NON_BURST_SYNC_EVENTS: 1494 fmt |= VIDEO_MODE_NON_BURST_WITH_SYNC_EVENTS; 1495 break; 1496 case NON_BURST_SYNC_PULSE: 1497 fmt |= VIDEO_MODE_NON_BURST_WITH_SYNC_PULSE; 1498 break; 1499 case BURST_MODE: 1500 fmt |= VIDEO_MODE_BURST; 1501 break; 1502 } 1503 1504 intel_de_write(dev_priv, MIPI_VIDEO_MODE_FORMAT(port), fmt); 1505 } 1506 } 1507 } 1508 1509 static void intel_dsi_unprepare(struct intel_encoder *encoder) 1510 { 1511 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1512 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1513 enum port port; 1514 1515 if (IS_GEMINILAKE(dev_priv)) 1516 return; 1517 1518 for_each_dsi_port(port, intel_dsi->ports) { 1519 /* Panel commands can be sent when clock is in LP11 */ 1520 intel_de_write(dev_priv, MIPI_DEVICE_READY(port), 0x0); 1521 1522 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) 1523 bxt_dsi_reset_clocks(encoder, port); 1524 else 1525 vlv_dsi_reset_clocks(encoder, port); 1526 intel_de_write(dev_priv, MIPI_EOT_DISABLE(port), CLOCKSTOP); 1527 1528 intel_de_rmw(dev_priv, MIPI_DSI_FUNC_PRG(port), VID_MODE_FORMAT_MASK, 0); 1529 1530 intel_de_write(dev_priv, MIPI_DEVICE_READY(port), 0x1); 1531 } 1532 } 1533 1534 static const struct drm_encoder_funcs intel_dsi_funcs = { 1535 .destroy = intel_encoder_destroy, 1536 }; 1537 1538 static enum drm_mode_status vlv_dsi_mode_valid(struct drm_connector *connector, 1539 struct drm_display_mode *mode) 1540 { 1541 struct drm_i915_private *i915 = to_i915(connector->dev); 1542 1543 if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) { 1544 enum drm_mode_status status; 1545 1546 status = intel_cpu_transcoder_mode_valid(i915, mode); 1547 if (status != MODE_OK) 1548 return status; 1549 } 1550 1551 return intel_dsi_mode_valid(connector, mode); 1552 } 1553 1554 static const struct drm_connector_helper_funcs intel_dsi_connector_helper_funcs = { 1555 .get_modes = intel_dsi_get_modes, 1556 .mode_valid = vlv_dsi_mode_valid, 1557 .atomic_check = intel_digital_connector_atomic_check, 1558 }; 1559 1560 static const struct drm_connector_funcs intel_dsi_connector_funcs = { 1561 .detect = intel_panel_detect, 1562 .late_register = intel_connector_register, 1563 .early_unregister = intel_connector_unregister, 1564 .destroy = intel_connector_destroy, 1565 .fill_modes = drm_helper_probe_single_connector_modes, 1566 .atomic_get_property = intel_digital_connector_atomic_get_property, 1567 .atomic_set_property = intel_digital_connector_atomic_set_property, 1568 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 1569 .atomic_duplicate_state = intel_digital_connector_duplicate_state, 1570 }; 1571 1572 static void vlv_dsi_add_properties(struct intel_connector *connector) 1573 { 1574 const struct drm_display_mode *fixed_mode = 1575 intel_panel_preferred_fixed_mode(connector); 1576 1577 intel_attach_scaling_mode_property(&connector->base); 1578 1579 drm_connector_set_panel_orientation_with_quirk(&connector->base, 1580 intel_dsi_get_panel_orientation(connector), 1581 fixed_mode->hdisplay, 1582 fixed_mode->vdisplay); 1583 } 1584 1585 #define NS_KHZ_RATIO 1000000 1586 1587 #define PREPARE_CNT_MAX 0x3F 1588 #define EXIT_ZERO_CNT_MAX 0x3F 1589 #define CLK_ZERO_CNT_MAX 0xFF 1590 #define TRAIL_CNT_MAX 0x1F 1591 1592 static void vlv_dphy_param_init(struct intel_dsi *intel_dsi) 1593 { 1594 struct drm_device *dev = intel_dsi->base.base.dev; 1595 struct drm_i915_private *dev_priv = to_i915(dev); 1596 struct intel_connector *connector = intel_dsi->attached_connector; 1597 struct mipi_config *mipi_config = connector->panel.vbt.dsi.config; 1598 u32 tlpx_ns, extra_byte_count, tlpx_ui; 1599 u32 ui_num, ui_den; 1600 u32 prepare_cnt, exit_zero_cnt, clk_zero_cnt, trail_cnt; 1601 u32 ths_prepare_ns, tclk_trail_ns; 1602 u32 tclk_prepare_clkzero, ths_prepare_hszero; 1603 u32 lp_to_hs_switch, hs_to_lp_switch; 1604 u32 mul; 1605 1606 tlpx_ns = intel_dsi_tlpx_ns(intel_dsi); 1607 1608 switch (intel_dsi->lane_count) { 1609 case 1: 1610 case 2: 1611 extra_byte_count = 2; 1612 break; 1613 case 3: 1614 extra_byte_count = 4; 1615 break; 1616 case 4: 1617 default: 1618 extra_byte_count = 3; 1619 break; 1620 } 1621 1622 /* in Kbps */ 1623 ui_num = NS_KHZ_RATIO; 1624 ui_den = intel_dsi_bitrate(intel_dsi); 1625 1626 tclk_prepare_clkzero = mipi_config->tclk_prepare_clkzero; 1627 ths_prepare_hszero = mipi_config->ths_prepare_hszero; 1628 1629 /* 1630 * B060 1631 * LP byte clock = TLPX/ (8UI) 1632 */ 1633 intel_dsi->lp_byte_clk = DIV_ROUND_UP(tlpx_ns * ui_den, 8 * ui_num); 1634 1635 /* DDR clock period = 2 * UI 1636 * UI(sec) = 1/(bitrate * 10^3) (bitrate is in KHZ) 1637 * UI(nsec) = 10^6 / bitrate 1638 * DDR clock period (nsec) = 2 * UI = (2 * 10^6)/ bitrate 1639 * DDR clock count = ns_value / DDR clock period 1640 * 1641 * For GEMINILAKE dphy_param_reg will be programmed in terms of 1642 * HS byte clock count for other platform in HS ddr clock count 1643 */ 1644 mul = IS_GEMINILAKE(dev_priv) ? 8 : 2; 1645 ths_prepare_ns = max(mipi_config->ths_prepare, 1646 mipi_config->tclk_prepare); 1647 1648 /* prepare count */ 1649 prepare_cnt = DIV_ROUND_UP(ths_prepare_ns * ui_den, ui_num * mul); 1650 1651 if (prepare_cnt > PREPARE_CNT_MAX) { 1652 drm_dbg_kms(&dev_priv->drm, "prepare count too high %u\n", 1653 prepare_cnt); 1654 prepare_cnt = PREPARE_CNT_MAX; 1655 } 1656 1657 /* exit zero count */ 1658 exit_zero_cnt = DIV_ROUND_UP( 1659 (ths_prepare_hszero - ths_prepare_ns) * ui_den, 1660 ui_num * mul 1661 ); 1662 1663 /* 1664 * Exit zero is unified val ths_zero and ths_exit 1665 * minimum value for ths_exit = 110ns 1666 * min (exit_zero_cnt * 2) = 110/UI 1667 * exit_zero_cnt = 55/UI 1668 */ 1669 if (exit_zero_cnt < (55 * ui_den / ui_num) && (55 * ui_den) % ui_num) 1670 exit_zero_cnt += 1; 1671 1672 if (exit_zero_cnt > EXIT_ZERO_CNT_MAX) { 1673 drm_dbg_kms(&dev_priv->drm, "exit zero count too high %u\n", 1674 exit_zero_cnt); 1675 exit_zero_cnt = EXIT_ZERO_CNT_MAX; 1676 } 1677 1678 /* clk zero count */ 1679 clk_zero_cnt = DIV_ROUND_UP( 1680 (tclk_prepare_clkzero - ths_prepare_ns) 1681 * ui_den, ui_num * mul); 1682 1683 if (clk_zero_cnt > CLK_ZERO_CNT_MAX) { 1684 drm_dbg_kms(&dev_priv->drm, "clock zero count too high %u\n", 1685 clk_zero_cnt); 1686 clk_zero_cnt = CLK_ZERO_CNT_MAX; 1687 } 1688 1689 /* trail count */ 1690 tclk_trail_ns = max(mipi_config->tclk_trail, mipi_config->ths_trail); 1691 trail_cnt = DIV_ROUND_UP(tclk_trail_ns * ui_den, ui_num * mul); 1692 1693 if (trail_cnt > TRAIL_CNT_MAX) { 1694 drm_dbg_kms(&dev_priv->drm, "trail count too high %u\n", 1695 trail_cnt); 1696 trail_cnt = TRAIL_CNT_MAX; 1697 } 1698 1699 /* B080 */ 1700 intel_dsi->dphy_reg = exit_zero_cnt << 24 | trail_cnt << 16 | 1701 clk_zero_cnt << 8 | prepare_cnt; 1702 1703 /* 1704 * LP to HS switch count = 4TLPX + PREP_COUNT * mul + EXIT_ZERO_COUNT * 1705 * mul + 10UI + Extra Byte Count 1706 * 1707 * HS to LP switch count = THS-TRAIL + 2TLPX + Extra Byte Count 1708 * Extra Byte Count is calculated according to number of lanes. 1709 * High Low Switch Count is the Max of LP to HS and 1710 * HS to LP switch count 1711 * 1712 */ 1713 tlpx_ui = DIV_ROUND_UP(tlpx_ns * ui_den, ui_num); 1714 1715 /* B044 */ 1716 /* FIXME: 1717 * The comment above does not match with the code */ 1718 lp_to_hs_switch = DIV_ROUND_UP(4 * tlpx_ui + prepare_cnt * mul + 1719 exit_zero_cnt * mul + 10, 8); 1720 1721 hs_to_lp_switch = DIV_ROUND_UP(mipi_config->ths_trail + 2 * tlpx_ui, 8); 1722 1723 intel_dsi->hs_to_lp_count = max(lp_to_hs_switch, hs_to_lp_switch); 1724 intel_dsi->hs_to_lp_count += extra_byte_count; 1725 1726 /* B088 */ 1727 /* LP -> HS for clock lanes 1728 * LP clk sync + LP11 + LP01 + tclk_prepare + tclk_zero + 1729 * extra byte count 1730 * 2TPLX + 1TLPX + 1 TPLX(in ns) + prepare_cnt * 2 + clk_zero_cnt * 1731 * 2(in UI) + extra byte count 1732 * In byteclks = (4TLPX + prepare_cnt * 2 + clk_zero_cnt *2 (in UI)) / 1733 * 8 + extra byte count 1734 */ 1735 intel_dsi->clk_lp_to_hs_count = 1736 DIV_ROUND_UP( 1737 4 * tlpx_ui + prepare_cnt * 2 + 1738 clk_zero_cnt * 2, 1739 8); 1740 1741 intel_dsi->clk_lp_to_hs_count += extra_byte_count; 1742 1743 /* HS->LP for Clock Lanes 1744 * Low Power clock synchronisations + 1Tx byteclk + tclk_trail + 1745 * Extra byte count 1746 * 2TLPX + 8UI + (trail_count*2)(in UI) + Extra byte count 1747 * In byteclks = (2*TLpx(in UI) + trail_count*2 +8)(in UI)/8 + 1748 * Extra byte count 1749 */ 1750 intel_dsi->clk_hs_to_lp_count = 1751 DIV_ROUND_UP(2 * tlpx_ui + trail_cnt * 2 + 8, 1752 8); 1753 intel_dsi->clk_hs_to_lp_count += extra_byte_count; 1754 1755 intel_dsi_log_params(intel_dsi); 1756 } 1757 1758 typedef void (*vlv_dsi_dmi_quirk_func)(struct intel_dsi *intel_dsi); 1759 1760 /* 1761 * Vtotal is wrong on the Asus TF103C leading to the last line of the display 1762 * being shown as the first line. The factory installed Android has a hardcoded 1763 * modeline, causing it to not suffer from this BIOS bug. 1764 * 1765 * Original mode: "1280x800": 60 67700 1280 1312 1328 1376 800 808 812 820 0x8 0xa 1766 * Fixed mode: "1280x800": 60 67700 1280 1312 1328 1376 800 808 812 816 0x8 0xa 1767 * 1768 * https://gitlab.freedesktop.org/drm/intel/-/issues/9381 1769 */ 1770 static void vlv_dsi_asus_tf103c_mode_fixup(struct intel_dsi *intel_dsi) 1771 { 1772 /* Cast away the const as we want to fixup the mode */ 1773 struct drm_display_mode *fixed_mode = (struct drm_display_mode *) 1774 intel_panel_preferred_fixed_mode(intel_dsi->attached_connector); 1775 1776 if (fixed_mode->vtotal == 820) 1777 fixed_mode->vtotal -= 4; 1778 } 1779 1780 /* 1781 * On the Lenovo Yoga Tablet 2 830 / 1050 there are 2 problems: 1782 * 1. The I2C MIPI sequence elements reference bus 3. ACPI has I2C1 - I2C7 1783 * which under Linux become bus 0 - 6. And the MIPI sequence reference 1784 * to bus 3 is indented for I2C3 which is bus 2 under Linux. 1785 * 1786 * Note mipi_exec_i2c() cannot just subtract 1 from the bus 1787 * given in the I2C MIPI sequence element. Since on other 1788 * devices the I2C bus-numbers used in the MIPI sequences do 1789 * actually start at 0. 1790 * 1791 * 2. width_/height_mm contain a bogus 192mm x 120mm size. This is 1792 * especially a problem on the 8" 830 version which uses a 10:16 1793 * portrait screen where as the bogus size is 16:10. 1794 * 1795 * https://gitlab.freedesktop.org/drm/intel/-/issues/9379 1796 */ 1797 static void vlv_dsi_lenovo_yoga_tab2_size_fixup(struct intel_dsi *intel_dsi) 1798 { 1799 const struct drm_display_mode *fixed_mode = 1800 intel_panel_preferred_fixed_mode(intel_dsi->attached_connector); 1801 struct drm_display_info *info = &intel_dsi->attached_connector->base.display_info; 1802 1803 intel_dsi->i2c_bus_num = 2; 1804 1805 /* 1806 * The 10" 1050 uses a 1920x1200 landscape screen, where as the 8" 830 1807 * uses a 1200x1920 portrait screen. 1808 */ 1809 if (fixed_mode->hdisplay == 1920) { 1810 info->width_mm = 216; 1811 info->height_mm = 135; 1812 } else { 1813 info->width_mm = 107; 1814 info->height_mm = 171; 1815 } 1816 } 1817 1818 /* 1819 * On the Lenovo Yoga Tab 3 Pro YT3-X90F there are 2 problems: 1820 * 1. i2c_acpi_find_adapter() picks the wrong adapter causing mipi_exec_i2c() 1821 * to not work. Fix this by setting i2c_bus_num. 1822 * 2. There is no backlight off MIPI sequence, causing the backlight to stay on. 1823 * Add a backlight off sequence mirroring the existing backlight on sequence. 1824 * 1825 * https://gitlab.freedesktop.org/drm/intel/-/issues/9380 1826 */ 1827 static void vlv_dsi_lenovo_yoga_tab3_backlight_fixup(struct intel_dsi *intel_dsi) 1828 { 1829 static const u8 backlight_off_sequence[16] = { 1830 /* Header Seq-id 7, length after header 11 bytes */ 1831 0x07, 0x0b, 0x00, 0x00, 0x00, 1832 /* MIPI_SEQ_ELEM_I2C bus 0 addr 0x2c reg 0x00 data-len 1 data 0x00 */ 1833 0x04, 0x08, 0x00, 0x00, 0x00, 0x2c, 0x00, 0x00, 0x01, 0x00, 1834 /* MIPI_SEQ_ELEM_END */ 1835 0x00 1836 }; 1837 struct intel_connector *connector = intel_dsi->attached_connector; 1838 1839 intel_dsi->i2c_bus_num = 0; 1840 connector->panel.vbt.dsi.sequence[MIPI_SEQ_BACKLIGHT_OFF] = backlight_off_sequence; 1841 } 1842 1843 static const struct dmi_system_id vlv_dsi_dmi_quirk_table[] = { 1844 { 1845 /* Asus Transformer Pad TF103C */ 1846 .matches = { 1847 DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK COMPUTER INC."), 1848 DMI_MATCH(DMI_PRODUCT_NAME, "TF103C"), 1849 }, 1850 .driver_data = (void *)vlv_dsi_asus_tf103c_mode_fixup, 1851 }, 1852 { 1853 /* 1854 * Lenovo Yoga Tablet 2 830F/L or 1050F/L (The 8" and 10" 1855 * Lenovo Yoga Tablet 2 use the same mainboard) 1856 */ 1857 .matches = { 1858 DMI_MATCH(DMI_SYS_VENDOR, "Intel Corp."), 1859 DMI_MATCH(DMI_PRODUCT_NAME, "VALLEYVIEW C0 PLATFORM"), 1860 DMI_MATCH(DMI_BOARD_NAME, "BYT-T FFD8"), 1861 /* Partial match on beginning of BIOS version */ 1862 DMI_MATCH(DMI_BIOS_VERSION, "BLADE_21"), 1863 }, 1864 .driver_data = (void *)vlv_dsi_lenovo_yoga_tab2_size_fixup, 1865 }, 1866 { 1867 /* Lenovo Yoga Tab 3 Pro YT3-X90F */ 1868 .matches = { 1869 DMI_MATCH(DMI_SYS_VENDOR, "Intel Corporation"), 1870 DMI_MATCH(DMI_PRODUCT_NAME, "CHERRYVIEW D1 PLATFORM"), 1871 DMI_MATCH(DMI_PRODUCT_VERSION, "Blade3-10A-001"), 1872 }, 1873 .driver_data = (void *)vlv_dsi_lenovo_yoga_tab3_backlight_fixup, 1874 }, 1875 { } 1876 }; 1877 1878 void vlv_dsi_init(struct drm_i915_private *dev_priv) 1879 { 1880 struct intel_dsi *intel_dsi; 1881 struct intel_encoder *intel_encoder; 1882 struct drm_encoder *encoder; 1883 struct intel_connector *intel_connector; 1884 struct drm_connector *connector; 1885 struct drm_display_mode *current_mode; 1886 const struct dmi_system_id *dmi_id; 1887 enum port port; 1888 enum pipe pipe; 1889 1890 drm_dbg_kms(&dev_priv->drm, "\n"); 1891 1892 /* There is no detection method for MIPI so rely on VBT */ 1893 if (!intel_bios_is_dsi_present(dev_priv, &port)) 1894 return; 1895 1896 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) 1897 dev_priv->display.dsi.mmio_base = BXT_MIPI_BASE; 1898 else 1899 dev_priv->display.dsi.mmio_base = VLV_MIPI_BASE; 1900 1901 intel_dsi = kzalloc(sizeof(*intel_dsi), GFP_KERNEL); 1902 if (!intel_dsi) 1903 return; 1904 1905 intel_connector = intel_connector_alloc(); 1906 if (!intel_connector) { 1907 kfree(intel_dsi); 1908 return; 1909 } 1910 1911 intel_encoder = &intel_dsi->base; 1912 encoder = &intel_encoder->base; 1913 intel_dsi->attached_connector = intel_connector; 1914 1915 connector = &intel_connector->base; 1916 1917 drm_encoder_init(&dev_priv->drm, encoder, &intel_dsi_funcs, DRM_MODE_ENCODER_DSI, 1918 "DSI %c", port_name(port)); 1919 1920 intel_encoder->compute_config = intel_dsi_compute_config; 1921 intel_encoder->pre_enable = intel_dsi_pre_enable; 1922 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) 1923 intel_encoder->enable = bxt_dsi_enable; 1924 intel_encoder->disable = intel_dsi_disable; 1925 intel_encoder->post_disable = intel_dsi_post_disable; 1926 intel_encoder->get_hw_state = intel_dsi_get_hw_state; 1927 intel_encoder->get_config = intel_dsi_get_config; 1928 intel_encoder->update_pipe = intel_backlight_update; 1929 intel_encoder->shutdown = intel_dsi_shutdown; 1930 1931 intel_connector->get_hw_state = intel_connector_get_hw_state; 1932 1933 intel_encoder->port = port; 1934 intel_encoder->type = INTEL_OUTPUT_DSI; 1935 intel_encoder->power_domain = POWER_DOMAIN_PORT_DSI; 1936 intel_encoder->cloneable = 0; 1937 1938 /* 1939 * On BYT/CHV, pipe A maps to MIPI DSI port A, pipe B maps to MIPI DSI 1940 * port C. BXT isn't limited like this. 1941 */ 1942 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) 1943 intel_encoder->pipe_mask = ~0; 1944 else if (port == PORT_A) 1945 intel_encoder->pipe_mask = BIT(PIPE_A); 1946 else 1947 intel_encoder->pipe_mask = BIT(PIPE_B); 1948 1949 intel_dsi->panel_power_off_time = ktime_get_boottime(); 1950 1951 intel_bios_init_panel_late(dev_priv, &intel_connector->panel, NULL, NULL); 1952 1953 if (intel_connector->panel.vbt.dsi.config->dual_link) 1954 intel_dsi->ports = BIT(PORT_A) | BIT(PORT_C); 1955 else 1956 intel_dsi->ports = BIT(port); 1957 1958 if (drm_WARN_ON(&dev_priv->drm, intel_connector->panel.vbt.dsi.bl_ports & ~intel_dsi->ports)) 1959 intel_connector->panel.vbt.dsi.bl_ports &= intel_dsi->ports; 1960 1961 if (drm_WARN_ON(&dev_priv->drm, intel_connector->panel.vbt.dsi.cabc_ports & ~intel_dsi->ports)) 1962 intel_connector->panel.vbt.dsi.cabc_ports &= intel_dsi->ports; 1963 1964 /* Create a DSI host (and a device) for each port. */ 1965 for_each_dsi_port(port, intel_dsi->ports) { 1966 struct intel_dsi_host *host; 1967 1968 host = intel_dsi_host_init(intel_dsi, &intel_dsi_host_ops, 1969 port); 1970 if (!host) 1971 goto err; 1972 1973 intel_dsi->dsi_hosts[port] = host; 1974 } 1975 1976 if (!intel_dsi_vbt_init(intel_dsi, MIPI_DSI_GENERIC_PANEL_ID)) { 1977 drm_dbg_kms(&dev_priv->drm, "no device found\n"); 1978 goto err; 1979 } 1980 1981 /* Use clock read-back from current hw-state for fastboot */ 1982 current_mode = intel_encoder_current_mode(intel_encoder); 1983 if (current_mode) { 1984 drm_dbg_kms(&dev_priv->drm, "Calculated pclk %d GOP %d\n", 1985 intel_dsi->pclk, current_mode->clock); 1986 if (intel_fuzzy_clock_check(intel_dsi->pclk, 1987 current_mode->clock)) { 1988 drm_dbg_kms(&dev_priv->drm, "Using GOP pclk\n"); 1989 intel_dsi->pclk = current_mode->clock; 1990 } 1991 1992 kfree(current_mode); 1993 } 1994 1995 vlv_dphy_param_init(intel_dsi); 1996 1997 intel_dsi_vbt_gpio_init(intel_dsi, 1998 intel_dsi_get_hw_state(intel_encoder, &pipe)); 1999 2000 drm_connector_init(&dev_priv->drm, connector, &intel_dsi_connector_funcs, 2001 DRM_MODE_CONNECTOR_DSI); 2002 2003 drm_connector_helper_add(connector, &intel_dsi_connector_helper_funcs); 2004 2005 connector->display_info.subpixel_order = SubPixelHorizontalRGB; /*XXX*/ 2006 2007 intel_connector_attach_encoder(intel_connector, intel_encoder); 2008 2009 mutex_lock(&dev_priv->drm.mode_config.mutex); 2010 intel_panel_add_vbt_lfp_fixed_mode(intel_connector); 2011 mutex_unlock(&dev_priv->drm.mode_config.mutex); 2012 2013 if (!intel_panel_preferred_fixed_mode(intel_connector)) { 2014 drm_dbg_kms(&dev_priv->drm, "no fixed mode\n"); 2015 goto err_cleanup_connector; 2016 } 2017 2018 dmi_id = dmi_first_match(vlv_dsi_dmi_quirk_table); 2019 if (dmi_id) { 2020 vlv_dsi_dmi_quirk_func quirk_func = 2021 (vlv_dsi_dmi_quirk_func)dmi_id->driver_data; 2022 2023 quirk_func(intel_dsi); 2024 } 2025 2026 intel_panel_init(intel_connector, NULL); 2027 2028 intel_backlight_setup(intel_connector, INVALID_PIPE); 2029 2030 vlv_dsi_add_properties(intel_connector); 2031 2032 return; 2033 2034 err_cleanup_connector: 2035 drm_connector_cleanup(&intel_connector->base); 2036 err: 2037 drm_encoder_cleanup(&intel_encoder->base); 2038 kfree(intel_dsi); 2039 kfree(intel_connector); 2040 } 2041