1 /* SPDX-License-Identifier: MIT */ 2 /* 3 * Copyright © 2022 Intel Corporation 4 */ 5 6 #ifndef __SKL_WATERMARK_H__ 7 #define __SKL_WATERMARK_H__ 8 9 #include <linux/types.h> 10 11 #include "intel_display_limits.h" 12 #include "intel_global_state.h" 13 #include "intel_wm_types.h" 14 15 struct drm_i915_private; 16 struct intel_atomic_state; 17 struct intel_bw_state; 18 struct intel_crtc; 19 struct intel_crtc_state; 20 struct intel_plane; 21 22 u8 intel_enabled_dbuf_slices_mask(struct drm_i915_private *i915); 23 24 void intel_sagv_pre_plane_update(struct intel_atomic_state *state); 25 void intel_sagv_post_plane_update(struct intel_atomic_state *state); 26 bool intel_can_enable_sagv(struct drm_i915_private *i915, 27 const struct intel_bw_state *bw_state); 28 29 u32 skl_ddb_dbuf_slice_mask(struct drm_i915_private *i915, 30 const struct skl_ddb_entry *entry); 31 32 void skl_write_plane_wm(struct intel_plane *plane, 33 const struct intel_crtc_state *crtc_state); 34 void skl_write_cursor_wm(struct intel_plane *plane, 35 const struct intel_crtc_state *crtc_state); 36 37 bool skl_ddb_allocation_overlaps(const struct skl_ddb_entry *ddb, 38 const struct skl_ddb_entry *entries, 39 int num_entries, int ignore_idx); 40 41 void intel_wm_state_verify(struct intel_crtc *crtc, 42 struct intel_crtc_state *new_crtc_state); 43 44 void skl_watermark_ipc_init(struct drm_i915_private *i915); 45 void skl_watermark_ipc_update(struct drm_i915_private *i915); 46 bool skl_watermark_ipc_enabled(struct drm_i915_private *i915); 47 void skl_watermark_debugfs_register(struct drm_i915_private *i915); 48 49 unsigned int skl_watermark_max_latency(struct drm_i915_private *i915); 50 51 void skl_wm_init(struct drm_i915_private *i915); 52 53 struct intel_dbuf_state { 54 struct intel_global_state base; 55 56 struct skl_ddb_entry ddb[I915_MAX_PIPES]; 57 unsigned int weight[I915_MAX_PIPES]; 58 u8 slices[I915_MAX_PIPES]; 59 u8 enabled_slices; 60 u8 active_pipes; 61 bool joined_mbus; 62 }; 63 64 struct intel_dbuf_state * 65 intel_atomic_get_dbuf_state(struct intel_atomic_state *state); 66 67 #define to_intel_dbuf_state(x) container_of((x), struct intel_dbuf_state, base) 68 #define intel_atomic_get_old_dbuf_state(state) \ 69 to_intel_dbuf_state(intel_atomic_get_old_global_obj_state(state, &to_i915(state->base.dev)->display.dbuf.obj)) 70 #define intel_atomic_get_new_dbuf_state(state) \ 71 to_intel_dbuf_state(intel_atomic_get_new_global_obj_state(state, &to_i915(state->base.dev)->display.dbuf.obj)) 72 73 int intel_dbuf_init(struct drm_i915_private *i915); 74 void intel_dbuf_pre_plane_update(struct intel_atomic_state *state); 75 void intel_dbuf_post_plane_update(struct intel_atomic_state *state); 76 void intel_mbus_dbox_update(struct intel_atomic_state *state); 77 78 #endif /* __SKL_WATERMARK_H__ */ 79 80