1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2020 Intel Corporation 4 */ 5 6 #include <drm/drm_atomic_helper.h> 7 #include <drm/drm_blend.h> 8 #include <drm/drm_damage_helper.h> 9 #include <drm/drm_fourcc.h> 10 11 #include "i915_drv.h" 12 #include "i915_reg.h" 13 #include "intel_atomic_plane.h" 14 #include "intel_bo.h" 15 #include "intel_de.h" 16 #include "intel_display_irq.h" 17 #include "intel_display_types.h" 18 #include "intel_dpt.h" 19 #include "intel_fb.h" 20 #include "intel_fbc.h" 21 #include "intel_frontbuffer.h" 22 #include "intel_psr.h" 23 #include "intel_psr_regs.h" 24 #include "skl_scaler.h" 25 #include "skl_universal_plane.h" 26 #include "skl_universal_plane_regs.h" 27 #include "skl_watermark.h" 28 #include "pxp/intel_pxp.h" 29 30 static const u32 skl_plane_formats[] = { 31 DRM_FORMAT_C8, 32 DRM_FORMAT_RGB565, 33 DRM_FORMAT_XRGB8888, 34 DRM_FORMAT_XBGR8888, 35 DRM_FORMAT_ARGB8888, 36 DRM_FORMAT_ABGR8888, 37 DRM_FORMAT_XRGB2101010, 38 DRM_FORMAT_XBGR2101010, 39 DRM_FORMAT_XRGB16161616F, 40 DRM_FORMAT_XBGR16161616F, 41 DRM_FORMAT_YUYV, 42 DRM_FORMAT_YVYU, 43 DRM_FORMAT_UYVY, 44 DRM_FORMAT_VYUY, 45 DRM_FORMAT_XYUV8888, 46 }; 47 48 static const u32 skl_planar_formats[] = { 49 DRM_FORMAT_C8, 50 DRM_FORMAT_RGB565, 51 DRM_FORMAT_XRGB8888, 52 DRM_FORMAT_XBGR8888, 53 DRM_FORMAT_ARGB8888, 54 DRM_FORMAT_ABGR8888, 55 DRM_FORMAT_XRGB2101010, 56 DRM_FORMAT_XBGR2101010, 57 DRM_FORMAT_XRGB16161616F, 58 DRM_FORMAT_XBGR16161616F, 59 DRM_FORMAT_YUYV, 60 DRM_FORMAT_YVYU, 61 DRM_FORMAT_UYVY, 62 DRM_FORMAT_VYUY, 63 DRM_FORMAT_NV12, 64 DRM_FORMAT_XYUV8888, 65 }; 66 67 static const u32 glk_planar_formats[] = { 68 DRM_FORMAT_C8, 69 DRM_FORMAT_RGB565, 70 DRM_FORMAT_XRGB8888, 71 DRM_FORMAT_XBGR8888, 72 DRM_FORMAT_ARGB8888, 73 DRM_FORMAT_ABGR8888, 74 DRM_FORMAT_XRGB2101010, 75 DRM_FORMAT_XBGR2101010, 76 DRM_FORMAT_XRGB16161616F, 77 DRM_FORMAT_XBGR16161616F, 78 DRM_FORMAT_YUYV, 79 DRM_FORMAT_YVYU, 80 DRM_FORMAT_UYVY, 81 DRM_FORMAT_VYUY, 82 DRM_FORMAT_NV12, 83 DRM_FORMAT_XYUV8888, 84 DRM_FORMAT_P010, 85 DRM_FORMAT_P012, 86 DRM_FORMAT_P016, 87 }; 88 89 static const u32 icl_sdr_y_plane_formats[] = { 90 DRM_FORMAT_C8, 91 DRM_FORMAT_RGB565, 92 DRM_FORMAT_XRGB8888, 93 DRM_FORMAT_XBGR8888, 94 DRM_FORMAT_ARGB8888, 95 DRM_FORMAT_ABGR8888, 96 DRM_FORMAT_XRGB2101010, 97 DRM_FORMAT_XBGR2101010, 98 DRM_FORMAT_ARGB2101010, 99 DRM_FORMAT_ABGR2101010, 100 DRM_FORMAT_YUYV, 101 DRM_FORMAT_YVYU, 102 DRM_FORMAT_UYVY, 103 DRM_FORMAT_VYUY, 104 DRM_FORMAT_Y210, 105 DRM_FORMAT_Y212, 106 DRM_FORMAT_Y216, 107 DRM_FORMAT_XYUV8888, 108 DRM_FORMAT_XVYU2101010, 109 DRM_FORMAT_XVYU12_16161616, 110 DRM_FORMAT_XVYU16161616, 111 }; 112 113 static const u32 icl_sdr_uv_plane_formats[] = { 114 DRM_FORMAT_C8, 115 DRM_FORMAT_RGB565, 116 DRM_FORMAT_XRGB8888, 117 DRM_FORMAT_XBGR8888, 118 DRM_FORMAT_ARGB8888, 119 DRM_FORMAT_ABGR8888, 120 DRM_FORMAT_XRGB2101010, 121 DRM_FORMAT_XBGR2101010, 122 DRM_FORMAT_ARGB2101010, 123 DRM_FORMAT_ABGR2101010, 124 DRM_FORMAT_YUYV, 125 DRM_FORMAT_YVYU, 126 DRM_FORMAT_UYVY, 127 DRM_FORMAT_VYUY, 128 DRM_FORMAT_NV12, 129 DRM_FORMAT_P010, 130 DRM_FORMAT_P012, 131 DRM_FORMAT_P016, 132 DRM_FORMAT_Y210, 133 DRM_FORMAT_Y212, 134 DRM_FORMAT_Y216, 135 DRM_FORMAT_XYUV8888, 136 DRM_FORMAT_XVYU2101010, 137 DRM_FORMAT_XVYU12_16161616, 138 DRM_FORMAT_XVYU16161616, 139 }; 140 141 static const u32 icl_hdr_plane_formats[] = { 142 DRM_FORMAT_C8, 143 DRM_FORMAT_RGB565, 144 DRM_FORMAT_XRGB8888, 145 DRM_FORMAT_XBGR8888, 146 DRM_FORMAT_ARGB8888, 147 DRM_FORMAT_ABGR8888, 148 DRM_FORMAT_XRGB2101010, 149 DRM_FORMAT_XBGR2101010, 150 DRM_FORMAT_ARGB2101010, 151 DRM_FORMAT_ABGR2101010, 152 DRM_FORMAT_XRGB16161616F, 153 DRM_FORMAT_XBGR16161616F, 154 DRM_FORMAT_ARGB16161616F, 155 DRM_FORMAT_ABGR16161616F, 156 DRM_FORMAT_YUYV, 157 DRM_FORMAT_YVYU, 158 DRM_FORMAT_UYVY, 159 DRM_FORMAT_VYUY, 160 DRM_FORMAT_NV12, 161 DRM_FORMAT_P010, 162 DRM_FORMAT_P012, 163 DRM_FORMAT_P016, 164 DRM_FORMAT_Y210, 165 DRM_FORMAT_Y212, 166 DRM_FORMAT_Y216, 167 DRM_FORMAT_XYUV8888, 168 DRM_FORMAT_XVYU2101010, 169 DRM_FORMAT_XVYU12_16161616, 170 DRM_FORMAT_XVYU16161616, 171 }; 172 173 int skl_format_to_fourcc(int format, bool rgb_order, bool alpha) 174 { 175 switch (format) { 176 case PLANE_CTL_FORMAT_RGB_565: 177 return DRM_FORMAT_RGB565; 178 case PLANE_CTL_FORMAT_NV12: 179 return DRM_FORMAT_NV12; 180 case PLANE_CTL_FORMAT_XYUV: 181 return DRM_FORMAT_XYUV8888; 182 case PLANE_CTL_FORMAT_P010: 183 return DRM_FORMAT_P010; 184 case PLANE_CTL_FORMAT_P012: 185 return DRM_FORMAT_P012; 186 case PLANE_CTL_FORMAT_P016: 187 return DRM_FORMAT_P016; 188 case PLANE_CTL_FORMAT_Y210: 189 return DRM_FORMAT_Y210; 190 case PLANE_CTL_FORMAT_Y212: 191 return DRM_FORMAT_Y212; 192 case PLANE_CTL_FORMAT_Y216: 193 return DRM_FORMAT_Y216; 194 case PLANE_CTL_FORMAT_Y410: 195 return DRM_FORMAT_XVYU2101010; 196 case PLANE_CTL_FORMAT_Y412: 197 return DRM_FORMAT_XVYU12_16161616; 198 case PLANE_CTL_FORMAT_Y416: 199 return DRM_FORMAT_XVYU16161616; 200 default: 201 case PLANE_CTL_FORMAT_XRGB_8888: 202 if (rgb_order) { 203 if (alpha) 204 return DRM_FORMAT_ABGR8888; 205 else 206 return DRM_FORMAT_XBGR8888; 207 } else { 208 if (alpha) 209 return DRM_FORMAT_ARGB8888; 210 else 211 return DRM_FORMAT_XRGB8888; 212 } 213 case PLANE_CTL_FORMAT_XRGB_2101010: 214 if (rgb_order) { 215 if (alpha) 216 return DRM_FORMAT_ABGR2101010; 217 else 218 return DRM_FORMAT_XBGR2101010; 219 } else { 220 if (alpha) 221 return DRM_FORMAT_ARGB2101010; 222 else 223 return DRM_FORMAT_XRGB2101010; 224 } 225 case PLANE_CTL_FORMAT_XRGB_16161616F: 226 if (rgb_order) { 227 if (alpha) 228 return DRM_FORMAT_ABGR16161616F; 229 else 230 return DRM_FORMAT_XBGR16161616F; 231 } else { 232 if (alpha) 233 return DRM_FORMAT_ARGB16161616F; 234 else 235 return DRM_FORMAT_XRGB16161616F; 236 } 237 } 238 } 239 240 static u8 icl_nv12_y_plane_mask(struct drm_i915_private *i915) 241 { 242 struct intel_display *display = &i915->display; 243 244 if (DISPLAY_VER(display) >= 13 || HAS_D12_PLANE_MINIMIZATION(display)) 245 return BIT(PLANE_4) | BIT(PLANE_5); 246 else 247 return BIT(PLANE_6) | BIT(PLANE_7); 248 } 249 250 bool icl_is_nv12_y_plane(struct drm_i915_private *dev_priv, 251 enum plane_id plane_id) 252 { 253 return DISPLAY_VER(dev_priv) >= 11 && 254 icl_nv12_y_plane_mask(dev_priv) & BIT(plane_id); 255 } 256 257 u8 icl_hdr_plane_mask(void) 258 { 259 return BIT(PLANE_1) | BIT(PLANE_2) | BIT(PLANE_3); 260 } 261 262 bool icl_is_hdr_plane(struct drm_i915_private *dev_priv, enum plane_id plane_id) 263 { 264 return DISPLAY_VER(dev_priv) >= 11 && 265 icl_hdr_plane_mask() & BIT(plane_id); 266 } 267 268 static int icl_plane_min_cdclk(const struct intel_crtc_state *crtc_state, 269 const struct intel_plane_state *plane_state) 270 { 271 unsigned int pixel_rate = intel_plane_pixel_rate(crtc_state, plane_state); 272 273 /* two pixels per clock */ 274 return DIV_ROUND_UP(pixel_rate, 2); 275 } 276 277 static void 278 glk_plane_ratio(const struct intel_plane_state *plane_state, 279 unsigned int *num, unsigned int *den) 280 { 281 const struct drm_framebuffer *fb = plane_state->hw.fb; 282 283 if (fb->format->cpp[0] == 8) { 284 *num = 10; 285 *den = 8; 286 } else { 287 *num = 1; 288 *den = 1; 289 } 290 } 291 292 static int glk_plane_min_cdclk(const struct intel_crtc_state *crtc_state, 293 const struct intel_plane_state *plane_state) 294 { 295 unsigned int pixel_rate = intel_plane_pixel_rate(crtc_state, plane_state); 296 unsigned int num, den; 297 298 glk_plane_ratio(plane_state, &num, &den); 299 300 /* two pixels per clock */ 301 return DIV_ROUND_UP(pixel_rate * num, 2 * den); 302 } 303 304 static void 305 skl_plane_ratio(const struct intel_plane_state *plane_state, 306 unsigned int *num, unsigned int *den) 307 { 308 const struct drm_framebuffer *fb = plane_state->hw.fb; 309 310 if (fb->format->cpp[0] == 8) { 311 *num = 9; 312 *den = 8; 313 } else { 314 *num = 1; 315 *den = 1; 316 } 317 } 318 319 static int skl_plane_min_cdclk(const struct intel_crtc_state *crtc_state, 320 const struct intel_plane_state *plane_state) 321 { 322 unsigned int pixel_rate = intel_plane_pixel_rate(crtc_state, plane_state); 323 unsigned int num, den; 324 325 skl_plane_ratio(plane_state, &num, &den); 326 327 return DIV_ROUND_UP(pixel_rate * num, den); 328 } 329 330 static int skl_plane_max_width(const struct drm_framebuffer *fb, 331 int color_plane, 332 unsigned int rotation) 333 { 334 int cpp = fb->format->cpp[color_plane]; 335 336 switch (fb->modifier) { 337 case DRM_FORMAT_MOD_LINEAR: 338 case I915_FORMAT_MOD_X_TILED: 339 /* 340 * Validated limit is 4k, but has 5k should 341 * work apart from the following features: 342 * - Ytile (already limited to 4k) 343 * - FP16 (already limited to 4k) 344 * - render compression (already limited to 4k) 345 * - KVMR sprite and cursor (don't care) 346 * - horizontal panning (TODO verify this) 347 * - pipe and plane scaling (TODO verify this) 348 */ 349 if (cpp == 8) 350 return 4096; 351 else 352 return 5120; 353 case I915_FORMAT_MOD_Y_TILED_CCS: 354 case I915_FORMAT_MOD_Yf_TILED_CCS: 355 /* FIXME AUX plane? */ 356 case I915_FORMAT_MOD_Y_TILED: 357 case I915_FORMAT_MOD_Yf_TILED: 358 if (cpp == 8) 359 return 2048; 360 else 361 return 4096; 362 default: 363 MISSING_CASE(fb->modifier); 364 return 2048; 365 } 366 } 367 368 static int glk_plane_max_width(const struct drm_framebuffer *fb, 369 int color_plane, 370 unsigned int rotation) 371 { 372 int cpp = fb->format->cpp[color_plane]; 373 374 switch (fb->modifier) { 375 case DRM_FORMAT_MOD_LINEAR: 376 case I915_FORMAT_MOD_X_TILED: 377 if (cpp == 8) 378 return 4096; 379 else 380 return 5120; 381 case I915_FORMAT_MOD_Y_TILED_CCS: 382 case I915_FORMAT_MOD_Yf_TILED_CCS: 383 /* FIXME AUX plane? */ 384 case I915_FORMAT_MOD_Y_TILED: 385 case I915_FORMAT_MOD_Yf_TILED: 386 if (cpp == 8) 387 return 2048; 388 else 389 return 5120; 390 default: 391 MISSING_CASE(fb->modifier); 392 return 2048; 393 } 394 } 395 396 static int icl_plane_min_width(const struct drm_framebuffer *fb, 397 int color_plane, 398 unsigned int rotation) 399 { 400 /* Wa_14011264657, Wa_14011050563: gen11+ */ 401 switch (fb->format->format) { 402 case DRM_FORMAT_C8: 403 return 18; 404 case DRM_FORMAT_RGB565: 405 return 10; 406 case DRM_FORMAT_XRGB8888: 407 case DRM_FORMAT_XBGR8888: 408 case DRM_FORMAT_ARGB8888: 409 case DRM_FORMAT_ABGR8888: 410 case DRM_FORMAT_XRGB2101010: 411 case DRM_FORMAT_XBGR2101010: 412 case DRM_FORMAT_ARGB2101010: 413 case DRM_FORMAT_ABGR2101010: 414 case DRM_FORMAT_XVYU2101010: 415 case DRM_FORMAT_Y212: 416 case DRM_FORMAT_Y216: 417 return 6; 418 case DRM_FORMAT_NV12: 419 return 20; 420 case DRM_FORMAT_P010: 421 case DRM_FORMAT_P012: 422 case DRM_FORMAT_P016: 423 return 12; 424 case DRM_FORMAT_XRGB16161616F: 425 case DRM_FORMAT_XBGR16161616F: 426 case DRM_FORMAT_ARGB16161616F: 427 case DRM_FORMAT_ABGR16161616F: 428 case DRM_FORMAT_XVYU12_16161616: 429 case DRM_FORMAT_XVYU16161616: 430 return 4; 431 default: 432 return 1; 433 } 434 } 435 436 static int xe3_plane_max_width(const struct drm_framebuffer *fb, 437 int color_plane, 438 unsigned int rotation) 439 { 440 if (intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier)) 441 return 4096; 442 else 443 return 6144; 444 } 445 446 static int icl_hdr_plane_max_width(const struct drm_framebuffer *fb, 447 int color_plane, 448 unsigned int rotation) 449 { 450 if (intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier)) 451 return 4096; 452 else 453 return 5120; 454 } 455 456 static int icl_sdr_plane_max_width(const struct drm_framebuffer *fb, 457 int color_plane, 458 unsigned int rotation) 459 { 460 return 5120; 461 } 462 463 static int skl_plane_max_height(const struct drm_framebuffer *fb, 464 int color_plane, 465 unsigned int rotation) 466 { 467 return 4096; 468 } 469 470 static int icl_plane_max_height(const struct drm_framebuffer *fb, 471 int color_plane, 472 unsigned int rotation) 473 { 474 return 4320; 475 } 476 477 static unsigned int 478 plane_max_stride(struct intel_plane *plane, 479 u32 pixel_format, u64 modifier, 480 unsigned int rotation, 481 unsigned int max_pixels, 482 unsigned int max_bytes) 483 { 484 const struct drm_format_info *info = drm_format_info(pixel_format); 485 int cpp = info->cpp[0]; 486 487 if (drm_rotation_90_or_270(rotation)) 488 return min(max_pixels, max_bytes / cpp); 489 else 490 return min(max_pixels * cpp, max_bytes); 491 } 492 493 static unsigned int 494 adl_plane_max_stride(struct intel_plane *plane, 495 u32 pixel_format, u64 modifier, 496 unsigned int rotation) 497 { 498 unsigned int max_pixels = 65536; /* PLANE_OFFSET limit */ 499 unsigned int max_bytes = 128 * 1024; 500 501 return plane_max_stride(plane, pixel_format, 502 modifier, rotation, 503 max_pixels, max_bytes); 504 } 505 506 static unsigned int 507 skl_plane_max_stride(struct intel_plane *plane, 508 u32 pixel_format, u64 modifier, 509 unsigned int rotation) 510 { 511 unsigned int max_pixels = 8192; /* PLANE_OFFSET limit */ 512 unsigned int max_bytes = 32 * 1024; 513 514 return plane_max_stride(plane, pixel_format, 515 modifier, rotation, 516 max_pixels, max_bytes); 517 } 518 519 static bool tgl_plane_can_async_flip(u64 modifier) 520 { 521 switch (modifier) { 522 case DRM_FORMAT_MOD_LINEAR: 523 case I915_FORMAT_MOD_X_TILED: 524 case I915_FORMAT_MOD_Y_TILED: 525 case I915_FORMAT_MOD_4_TILED: 526 case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS: 527 case I915_FORMAT_MOD_4_TILED_MTL_RC_CCS: 528 case I915_FORMAT_MOD_4_TILED_DG2_RC_CCS: 529 case I915_FORMAT_MOD_4_TILED_BMG_CCS: 530 case I915_FORMAT_MOD_4_TILED_LNL_CCS: 531 return true; 532 case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS: 533 case I915_FORMAT_MOD_4_TILED_MTL_MC_CCS: 534 case I915_FORMAT_MOD_4_TILED_DG2_MC_CCS: 535 case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC: 536 case I915_FORMAT_MOD_4_TILED_MTL_RC_CCS_CC: 537 case I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC: 538 return false; 539 default: 540 return false; 541 } 542 } 543 544 static bool icl_plane_can_async_flip(u64 modifier) 545 { 546 switch (modifier) { 547 case DRM_FORMAT_MOD_LINEAR: 548 /* 549 * FIXME: Async on Linear buffer is supported on ICL 550 * but with additional alignment and fbc restrictions 551 * need to be taken care of. 552 */ 553 return false; 554 case I915_FORMAT_MOD_X_TILED: 555 case I915_FORMAT_MOD_Y_TILED: 556 case I915_FORMAT_MOD_Yf_TILED: 557 case I915_FORMAT_MOD_Y_TILED_CCS: 558 case I915_FORMAT_MOD_Yf_TILED_CCS: 559 return true; 560 default: 561 return false; 562 } 563 } 564 565 static bool skl_plane_can_async_flip(u64 modifier) 566 { 567 switch (modifier) { 568 case DRM_FORMAT_MOD_LINEAR: 569 return false; 570 case I915_FORMAT_MOD_X_TILED: 571 case I915_FORMAT_MOD_Y_TILED: 572 case I915_FORMAT_MOD_Yf_TILED: 573 return true; 574 case I915_FORMAT_MOD_Y_TILED_CCS: 575 case I915_FORMAT_MOD_Yf_TILED_CCS: 576 /* 577 * Display WA #0731: skl 578 * WaDisableRCWithAsyncFlip: skl 579 * "When render decompression is enabled, hardware 580 * internally converts the Async flips to Sync flips." 581 * 582 * Display WA #1159: glk 583 * "Async flip with render compression may result in 584 * intermittent underrun corruption." 585 */ 586 return false; 587 default: 588 return false; 589 } 590 } 591 592 static u32 tgl_plane_min_alignment(struct intel_plane *plane, 593 const struct drm_framebuffer *fb, 594 int color_plane) 595 { 596 struct drm_i915_private *i915 = to_i915(plane->base.dev); 597 /* PLANE_SURF GGTT -> DPT alignment */ 598 int mult = intel_fb_uses_dpt(fb) ? 512 : 1; 599 600 /* AUX_DIST needs only 4K alignment */ 601 if (intel_fb_is_ccs_aux_plane(fb, color_plane)) 602 return mult * 4 * 1024; 603 604 /* 605 * FIXME ADL sees GGTT/DMAR faults with async 606 * flips unless we align to 16k at least. 607 * Figure out what's going on here... 608 */ 609 if (IS_ALDERLAKE_P(i915) && 610 intel_plane_can_async_flip(plane, fb->modifier)) 611 return mult * 16 * 1024; 612 613 switch (fb->modifier) { 614 case DRM_FORMAT_MOD_LINEAR: 615 case I915_FORMAT_MOD_X_TILED: 616 case I915_FORMAT_MOD_Y_TILED: 617 case I915_FORMAT_MOD_4_TILED: 618 return mult * 4 * 1024; 619 case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS: 620 case I915_FORMAT_MOD_4_TILED_MTL_RC_CCS: 621 case I915_FORMAT_MOD_4_TILED_DG2_RC_CCS: 622 case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS: 623 case I915_FORMAT_MOD_4_TILED_MTL_MC_CCS: 624 case I915_FORMAT_MOD_4_TILED_DG2_MC_CCS: 625 case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC: 626 case I915_FORMAT_MOD_4_TILED_MTL_RC_CCS_CC: 627 case I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC: 628 case I915_FORMAT_MOD_4_TILED_BMG_CCS: 629 case I915_FORMAT_MOD_4_TILED_LNL_CCS: 630 /* 631 * Align to at least 4x1 main surface 632 * tiles (16K) to match 64B of AUX. 633 */ 634 return max(mult * 4 * 1024, 16 * 1024); 635 default: 636 MISSING_CASE(fb->modifier); 637 return 0; 638 } 639 } 640 641 static u32 skl_plane_min_alignment(struct intel_plane *plane, 642 const struct drm_framebuffer *fb, 643 int color_plane) 644 { 645 /* 646 * AUX_DIST needs only 4K alignment, 647 * as does ICL UV PLANE_SURF. 648 */ 649 if (color_plane != 0) 650 return 4 * 1024; 651 652 switch (fb->modifier) { 653 case DRM_FORMAT_MOD_LINEAR: 654 case I915_FORMAT_MOD_X_TILED: 655 return 256 * 1024; 656 case I915_FORMAT_MOD_Y_TILED_CCS: 657 case I915_FORMAT_MOD_Yf_TILED_CCS: 658 case I915_FORMAT_MOD_Y_TILED: 659 case I915_FORMAT_MOD_Yf_TILED: 660 return 1 * 1024 * 1024; 661 default: 662 MISSING_CASE(fb->modifier); 663 return 0; 664 } 665 } 666 667 /* Preoffset values for YUV to RGB Conversion */ 668 #define PREOFF_YUV_TO_RGB_HI 0x1800 669 #define PREOFF_YUV_TO_RGB_ME 0x0000 670 #define PREOFF_YUV_TO_RGB_LO 0x1800 671 672 #define ROFF(x) (((x) & 0xffff) << 16) 673 #define GOFF(x) (((x) & 0xffff) << 0) 674 #define BOFF(x) (((x) & 0xffff) << 16) 675 676 /* 677 * Programs the input color space conversion stage for ICL HDR planes. 678 * Note that it is assumed that this stage always happens after YUV 679 * range correction. Thus, the input to this stage is assumed to be 680 * in full-range YCbCr. 681 */ 682 static void 683 icl_program_input_csc(struct intel_dsb *dsb, 684 struct intel_plane *plane, 685 const struct intel_plane_state *plane_state) 686 { 687 struct intel_display *display = to_intel_display(plane->base.dev); 688 enum pipe pipe = plane->pipe; 689 enum plane_id plane_id = plane->id; 690 691 static const u16 input_csc_matrix[][9] = { 692 /* 693 * BT.601 full range YCbCr -> full range RGB 694 * The matrix required is : 695 * [1.000, 0.000, 1.371, 696 * 1.000, -0.336, -0.698, 697 * 1.000, 1.732, 0.0000] 698 */ 699 [DRM_COLOR_YCBCR_BT601] = { 700 0x7AF8, 0x7800, 0x0, 701 0x8B28, 0x7800, 0x9AC0, 702 0x0, 0x7800, 0x7DD8, 703 }, 704 /* 705 * BT.709 full range YCbCr -> full range RGB 706 * The matrix required is : 707 * [1.000, 0.000, 1.574, 708 * 1.000, -0.187, -0.468, 709 * 1.000, 1.855, 0.0000] 710 */ 711 [DRM_COLOR_YCBCR_BT709] = { 712 0x7C98, 0x7800, 0x0, 713 0x9EF8, 0x7800, 0xAC00, 714 0x0, 0x7800, 0x7ED8, 715 }, 716 /* 717 * BT.2020 full range YCbCr -> full range RGB 718 * The matrix required is : 719 * [1.000, 0.000, 1.474, 720 * 1.000, -0.1645, -0.5713, 721 * 1.000, 1.8814, 0.0000] 722 */ 723 [DRM_COLOR_YCBCR_BT2020] = { 724 0x7BC8, 0x7800, 0x0, 725 0x8928, 0x7800, 0xAA88, 726 0x0, 0x7800, 0x7F10, 727 }, 728 }; 729 const u16 *csc = input_csc_matrix[plane_state->hw.color_encoding]; 730 731 intel_de_write_dsb(display, dsb, PLANE_INPUT_CSC_COEFF(pipe, plane_id, 0), 732 ROFF(csc[0]) | GOFF(csc[1])); 733 intel_de_write_dsb(display, dsb, PLANE_INPUT_CSC_COEFF(pipe, plane_id, 1), 734 BOFF(csc[2])); 735 intel_de_write_dsb(display, dsb, PLANE_INPUT_CSC_COEFF(pipe, plane_id, 2), 736 ROFF(csc[3]) | GOFF(csc[4])); 737 intel_de_write_dsb(display, dsb, PLANE_INPUT_CSC_COEFF(pipe, plane_id, 3), 738 BOFF(csc[5])); 739 intel_de_write_dsb(display, dsb, PLANE_INPUT_CSC_COEFF(pipe, plane_id, 4), 740 ROFF(csc[6]) | GOFF(csc[7])); 741 intel_de_write_dsb(display, dsb, PLANE_INPUT_CSC_COEFF(pipe, plane_id, 5), 742 BOFF(csc[8])); 743 744 intel_de_write_dsb(display, dsb, PLANE_INPUT_CSC_PREOFF(pipe, plane_id, 0), 745 PREOFF_YUV_TO_RGB_HI); 746 intel_de_write_dsb(display, dsb, PLANE_INPUT_CSC_PREOFF(pipe, plane_id, 1), 747 PREOFF_YUV_TO_RGB_ME); 748 intel_de_write_dsb(display, dsb, PLANE_INPUT_CSC_PREOFF(pipe, plane_id, 2), 749 PREOFF_YUV_TO_RGB_LO); 750 intel_de_write_dsb(display, dsb, 751 PLANE_INPUT_CSC_POSTOFF(pipe, plane_id, 0), 0x0); 752 intel_de_write_dsb(display, dsb, 753 PLANE_INPUT_CSC_POSTOFF(pipe, plane_id, 1), 0x0); 754 intel_de_write_dsb(display, dsb, 755 PLANE_INPUT_CSC_POSTOFF(pipe, plane_id, 2), 0x0); 756 } 757 758 static unsigned int skl_plane_stride_mult(const struct drm_framebuffer *fb, 759 int color_plane, unsigned int rotation) 760 { 761 /* 762 * The stride is either expressed as a multiple of 64 bytes chunks for 763 * linear buffers or in number of tiles for tiled buffers. 764 */ 765 if (is_surface_linear(fb, color_plane)) 766 return 64; 767 else if (drm_rotation_90_or_270(rotation)) 768 return intel_tile_height(fb, color_plane); 769 else 770 return intel_tile_width_bytes(fb, color_plane); 771 } 772 773 static u32 skl_plane_stride(const struct intel_plane_state *plane_state, 774 int color_plane) 775 { 776 const struct drm_framebuffer *fb = plane_state->hw.fb; 777 unsigned int rotation = plane_state->hw.rotation; 778 u32 stride = plane_state->view.color_plane[color_plane].scanout_stride; 779 780 if (color_plane >= fb->format->num_planes) 781 return 0; 782 783 return stride / skl_plane_stride_mult(fb, color_plane, rotation); 784 } 785 786 static u32 skl_plane_ddb_reg_val(const struct skl_ddb_entry *entry) 787 { 788 if (!entry->end) 789 return 0; 790 791 return PLANE_BUF_END(entry->end - 1) | 792 PLANE_BUF_START(entry->start); 793 } 794 795 static u32 xe3_plane_min_ddb_reg_val(const u16 *min_ddb, 796 const u16 *interim_ddb) 797 { 798 u32 val = 0; 799 800 if (*min_ddb) 801 val |= PLANE_MIN_DBUF_BLOCKS(*min_ddb); 802 803 if (*interim_ddb) 804 val |= PLANE_INTERIM_DBUF_BLOCKS(*interim_ddb); 805 806 val |= val ? PLANE_AUTO_MIN_DBUF_EN : 0; 807 808 return val; 809 } 810 811 static u32 skl_plane_wm_reg_val(const struct skl_wm_level *level) 812 { 813 u32 val = 0; 814 815 if (level->enable) 816 val |= PLANE_WM_EN; 817 if (level->ignore_lines) 818 val |= PLANE_WM_IGNORE_LINES; 819 if (level->auto_min_alloc_wm_enable) 820 val |= PLANE_WM_AUTO_MIN_ALLOC_EN; 821 822 val |= REG_FIELD_PREP(PLANE_WM_BLOCKS_MASK, level->blocks); 823 val |= REG_FIELD_PREP(PLANE_WM_LINES_MASK, level->lines); 824 825 return val; 826 } 827 828 static void skl_write_plane_wm(struct intel_dsb *dsb, 829 struct intel_plane *plane, 830 const struct intel_crtc_state *crtc_state) 831 { 832 struct intel_display *display = to_intel_display(plane->base.dev); 833 enum plane_id plane_id = plane->id; 834 enum pipe pipe = plane->pipe; 835 const struct skl_pipe_wm *pipe_wm = &crtc_state->wm.skl.optimal; 836 const struct skl_ddb_entry *ddb = 837 &crtc_state->wm.skl.plane_ddb[plane_id]; 838 const struct skl_ddb_entry *ddb_y = 839 &crtc_state->wm.skl.plane_ddb_y[plane_id]; 840 const u16 *min_ddb = &crtc_state->wm.skl.plane_min_ddb[plane_id]; 841 const u16 *interim_ddb = 842 &crtc_state->wm.skl.plane_interim_ddb[plane_id]; 843 int level; 844 845 for (level = 0; level < display->wm.num_levels; level++) 846 intel_de_write_dsb(display, dsb, PLANE_WM(pipe, plane_id, level), 847 skl_plane_wm_reg_val(skl_plane_wm_level(pipe_wm, plane_id, level))); 848 849 intel_de_write_dsb(display, dsb, PLANE_WM_TRANS(pipe, plane_id), 850 skl_plane_wm_reg_val(skl_plane_trans_wm(pipe_wm, plane_id))); 851 852 if (HAS_HW_SAGV_WM(display)) { 853 const struct skl_plane_wm *wm = &pipe_wm->planes[plane_id]; 854 855 intel_de_write_dsb(display, dsb, PLANE_WM_SAGV(pipe, plane_id), 856 skl_plane_wm_reg_val(&wm->sagv.wm0)); 857 intel_de_write_dsb(display, dsb, PLANE_WM_SAGV_TRANS(pipe, plane_id), 858 skl_plane_wm_reg_val(&wm->sagv.trans_wm)); 859 } 860 861 intel_de_write_dsb(display, dsb, PLANE_BUF_CFG(pipe, plane_id), 862 skl_plane_ddb_reg_val(ddb)); 863 864 if (DISPLAY_VER(display) < 11) 865 intel_de_write_dsb(display, dsb, PLANE_NV12_BUF_CFG(pipe, plane_id), 866 skl_plane_ddb_reg_val(ddb_y)); 867 868 if (DISPLAY_VER(display) >= 30) 869 intel_de_write_dsb(display, dsb, PLANE_MIN_BUF_CFG(pipe, plane_id), 870 xe3_plane_min_ddb_reg_val(min_ddb, interim_ddb)); 871 } 872 873 static void 874 skl_plane_disable_arm(struct intel_dsb *dsb, 875 struct intel_plane *plane, 876 const struct intel_crtc_state *crtc_state) 877 { 878 struct intel_display *display = to_intel_display(plane->base.dev); 879 enum plane_id plane_id = plane->id; 880 enum pipe pipe = plane->pipe; 881 882 skl_write_plane_wm(dsb, plane, crtc_state); 883 884 intel_de_write_dsb(display, dsb, PLANE_CTL(pipe, plane_id), 0); 885 intel_de_write_dsb(display, dsb, PLANE_SURF(pipe, plane_id), 0); 886 } 887 888 static void icl_plane_disable_sel_fetch_arm(struct intel_dsb *dsb, 889 struct intel_plane *plane, 890 const struct intel_crtc_state *crtc_state) 891 { 892 struct intel_display *display = to_intel_display(plane->base.dev); 893 enum pipe pipe = plane->pipe; 894 895 if (!crtc_state->enable_psr2_sel_fetch) 896 return; 897 898 intel_de_write_dsb(display, dsb, SEL_FETCH_PLANE_CTL(pipe, plane->id), 0); 899 } 900 901 static void 902 icl_plane_disable_arm(struct intel_dsb *dsb, 903 struct intel_plane *plane, 904 const struct intel_crtc_state *crtc_state) 905 { 906 struct intel_display *display = to_intel_display(plane->base.dev); 907 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 908 enum plane_id plane_id = plane->id; 909 enum pipe pipe = plane->pipe; 910 911 if (icl_is_hdr_plane(dev_priv, plane_id)) 912 intel_de_write_dsb(display, dsb, PLANE_CUS_CTL(pipe, plane_id), 0); 913 914 skl_write_plane_wm(dsb, plane, crtc_state); 915 916 icl_plane_disable_sel_fetch_arm(dsb, plane, crtc_state); 917 intel_de_write_dsb(display, dsb, PLANE_CTL(pipe, plane_id), 0); 918 intel_de_write_dsb(display, dsb, PLANE_SURF(pipe, plane_id), 0); 919 } 920 921 static bool 922 skl_plane_get_hw_state(struct intel_plane *plane, 923 enum pipe *pipe) 924 { 925 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 926 enum intel_display_power_domain power_domain; 927 enum plane_id plane_id = plane->id; 928 intel_wakeref_t wakeref; 929 bool ret; 930 931 power_domain = POWER_DOMAIN_PIPE(plane->pipe); 932 wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain); 933 if (!wakeref) 934 return false; 935 936 ret = intel_de_read(dev_priv, PLANE_CTL(plane->pipe, plane_id)) & PLANE_CTL_ENABLE; 937 938 *pipe = plane->pipe; 939 940 intel_display_power_put(dev_priv, power_domain, wakeref); 941 942 return ret; 943 } 944 945 static u32 skl_plane_ctl_format(u32 pixel_format) 946 { 947 switch (pixel_format) { 948 case DRM_FORMAT_C8: 949 return PLANE_CTL_FORMAT_INDEXED; 950 case DRM_FORMAT_RGB565: 951 return PLANE_CTL_FORMAT_RGB_565; 952 case DRM_FORMAT_XBGR8888: 953 case DRM_FORMAT_ABGR8888: 954 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX; 955 case DRM_FORMAT_XRGB8888: 956 case DRM_FORMAT_ARGB8888: 957 return PLANE_CTL_FORMAT_XRGB_8888; 958 case DRM_FORMAT_XBGR2101010: 959 case DRM_FORMAT_ABGR2101010: 960 return PLANE_CTL_FORMAT_XRGB_2101010 | PLANE_CTL_ORDER_RGBX; 961 case DRM_FORMAT_XRGB2101010: 962 case DRM_FORMAT_ARGB2101010: 963 return PLANE_CTL_FORMAT_XRGB_2101010; 964 case DRM_FORMAT_XBGR16161616F: 965 case DRM_FORMAT_ABGR16161616F: 966 return PLANE_CTL_FORMAT_XRGB_16161616F | PLANE_CTL_ORDER_RGBX; 967 case DRM_FORMAT_XRGB16161616F: 968 case DRM_FORMAT_ARGB16161616F: 969 return PLANE_CTL_FORMAT_XRGB_16161616F; 970 case DRM_FORMAT_XYUV8888: 971 return PLANE_CTL_FORMAT_XYUV; 972 case DRM_FORMAT_YUYV: 973 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_ORDER_YUYV; 974 case DRM_FORMAT_YVYU: 975 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_ORDER_YVYU; 976 case DRM_FORMAT_UYVY: 977 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_ORDER_UYVY; 978 case DRM_FORMAT_VYUY: 979 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_ORDER_VYUY; 980 case DRM_FORMAT_NV12: 981 return PLANE_CTL_FORMAT_NV12; 982 case DRM_FORMAT_P010: 983 return PLANE_CTL_FORMAT_P010; 984 case DRM_FORMAT_P012: 985 return PLANE_CTL_FORMAT_P012; 986 case DRM_FORMAT_P016: 987 return PLANE_CTL_FORMAT_P016; 988 case DRM_FORMAT_Y210: 989 return PLANE_CTL_FORMAT_Y210; 990 case DRM_FORMAT_Y212: 991 return PLANE_CTL_FORMAT_Y212; 992 case DRM_FORMAT_Y216: 993 return PLANE_CTL_FORMAT_Y216; 994 case DRM_FORMAT_XVYU2101010: 995 return PLANE_CTL_FORMAT_Y410; 996 case DRM_FORMAT_XVYU12_16161616: 997 return PLANE_CTL_FORMAT_Y412; 998 case DRM_FORMAT_XVYU16161616: 999 return PLANE_CTL_FORMAT_Y416; 1000 default: 1001 MISSING_CASE(pixel_format); 1002 } 1003 1004 return 0; 1005 } 1006 1007 static u32 skl_plane_ctl_alpha(const struct intel_plane_state *plane_state) 1008 { 1009 if (!plane_state->hw.fb->format->has_alpha) 1010 return PLANE_CTL_ALPHA_DISABLE; 1011 1012 switch (plane_state->hw.pixel_blend_mode) { 1013 case DRM_MODE_BLEND_PIXEL_NONE: 1014 return PLANE_CTL_ALPHA_DISABLE; 1015 case DRM_MODE_BLEND_PREMULTI: 1016 return PLANE_CTL_ALPHA_SW_PREMULTIPLY; 1017 case DRM_MODE_BLEND_COVERAGE: 1018 return PLANE_CTL_ALPHA_HW_PREMULTIPLY; 1019 default: 1020 MISSING_CASE(plane_state->hw.pixel_blend_mode); 1021 return PLANE_CTL_ALPHA_DISABLE; 1022 } 1023 } 1024 1025 static u32 glk_plane_color_ctl_alpha(const struct intel_plane_state *plane_state) 1026 { 1027 if (!plane_state->hw.fb->format->has_alpha) 1028 return PLANE_COLOR_ALPHA_DISABLE; 1029 1030 switch (plane_state->hw.pixel_blend_mode) { 1031 case DRM_MODE_BLEND_PIXEL_NONE: 1032 return PLANE_COLOR_ALPHA_DISABLE; 1033 case DRM_MODE_BLEND_PREMULTI: 1034 return PLANE_COLOR_ALPHA_SW_PREMULTIPLY; 1035 case DRM_MODE_BLEND_COVERAGE: 1036 return PLANE_COLOR_ALPHA_HW_PREMULTIPLY; 1037 default: 1038 MISSING_CASE(plane_state->hw.pixel_blend_mode); 1039 return PLANE_COLOR_ALPHA_DISABLE; 1040 } 1041 } 1042 1043 static u32 skl_plane_ctl_tiling(u64 fb_modifier) 1044 { 1045 switch (fb_modifier) { 1046 case DRM_FORMAT_MOD_LINEAR: 1047 break; 1048 case I915_FORMAT_MOD_X_TILED: 1049 return PLANE_CTL_TILED_X; 1050 case I915_FORMAT_MOD_Y_TILED: 1051 return PLANE_CTL_TILED_Y; 1052 case I915_FORMAT_MOD_4_TILED: 1053 return PLANE_CTL_TILED_4; 1054 case I915_FORMAT_MOD_4_TILED_DG2_RC_CCS: 1055 return PLANE_CTL_TILED_4 | 1056 PLANE_CTL_RENDER_DECOMPRESSION_ENABLE | 1057 PLANE_CTL_CLEAR_COLOR_DISABLE; 1058 case I915_FORMAT_MOD_4_TILED_DG2_MC_CCS: 1059 return PLANE_CTL_TILED_4 | 1060 PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE | 1061 PLANE_CTL_CLEAR_COLOR_DISABLE; 1062 case I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC: 1063 return PLANE_CTL_TILED_4 | PLANE_CTL_RENDER_DECOMPRESSION_ENABLE; 1064 case I915_FORMAT_MOD_4_TILED_MTL_RC_CCS: 1065 return PLANE_CTL_TILED_4 | 1066 PLANE_CTL_RENDER_DECOMPRESSION_ENABLE | 1067 PLANE_CTL_CLEAR_COLOR_DISABLE; 1068 case I915_FORMAT_MOD_4_TILED_MTL_RC_CCS_CC: 1069 return PLANE_CTL_TILED_4 | PLANE_CTL_RENDER_DECOMPRESSION_ENABLE; 1070 case I915_FORMAT_MOD_4_TILED_MTL_MC_CCS: 1071 return PLANE_CTL_TILED_4 | PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE; 1072 case I915_FORMAT_MOD_4_TILED_BMG_CCS: 1073 case I915_FORMAT_MOD_4_TILED_LNL_CCS: 1074 return PLANE_CTL_TILED_4 | PLANE_CTL_RENDER_DECOMPRESSION_ENABLE; 1075 case I915_FORMAT_MOD_Y_TILED_CCS: 1076 case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC: 1077 return PLANE_CTL_TILED_Y | PLANE_CTL_RENDER_DECOMPRESSION_ENABLE; 1078 case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS: 1079 return PLANE_CTL_TILED_Y | 1080 PLANE_CTL_RENDER_DECOMPRESSION_ENABLE | 1081 PLANE_CTL_CLEAR_COLOR_DISABLE; 1082 case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS: 1083 return PLANE_CTL_TILED_Y | PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE; 1084 case I915_FORMAT_MOD_Yf_TILED: 1085 return PLANE_CTL_TILED_YF; 1086 case I915_FORMAT_MOD_Yf_TILED_CCS: 1087 return PLANE_CTL_TILED_YF | PLANE_CTL_RENDER_DECOMPRESSION_ENABLE; 1088 default: 1089 MISSING_CASE(fb_modifier); 1090 } 1091 1092 return 0; 1093 } 1094 1095 static u32 skl_plane_ctl_rotate(unsigned int rotate) 1096 { 1097 switch (rotate) { 1098 case DRM_MODE_ROTATE_0: 1099 break; 1100 /* 1101 * DRM_MODE_ROTATE_ is counter clockwise to stay compatible with Xrandr 1102 * while i915 HW rotation is clockwise, thats why this swapping. 1103 */ 1104 case DRM_MODE_ROTATE_90: 1105 return PLANE_CTL_ROTATE_270; 1106 case DRM_MODE_ROTATE_180: 1107 return PLANE_CTL_ROTATE_180; 1108 case DRM_MODE_ROTATE_270: 1109 return PLANE_CTL_ROTATE_90; 1110 default: 1111 MISSING_CASE(rotate); 1112 } 1113 1114 return 0; 1115 } 1116 1117 static u32 icl_plane_ctl_flip(unsigned int reflect) 1118 { 1119 switch (reflect) { 1120 case 0: 1121 break; 1122 case DRM_MODE_REFLECT_X: 1123 return PLANE_CTL_FLIP_HORIZONTAL; 1124 case DRM_MODE_REFLECT_Y: 1125 default: 1126 MISSING_CASE(reflect); 1127 } 1128 1129 return 0; 1130 } 1131 1132 static u32 adlp_plane_ctl_arb_slots(const struct intel_plane_state *plane_state) 1133 { 1134 const struct drm_framebuffer *fb = plane_state->hw.fb; 1135 1136 if (intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier)) { 1137 switch (fb->format->cpp[0]) { 1138 case 2: 1139 return PLANE_CTL_ARB_SLOTS(1); 1140 default: 1141 return PLANE_CTL_ARB_SLOTS(0); 1142 } 1143 } else { 1144 switch (fb->format->cpp[0]) { 1145 case 8: 1146 return PLANE_CTL_ARB_SLOTS(3); 1147 case 4: 1148 return PLANE_CTL_ARB_SLOTS(1); 1149 default: 1150 return PLANE_CTL_ARB_SLOTS(0); 1151 } 1152 } 1153 } 1154 1155 static u32 skl_plane_ctl_crtc(const struct intel_crtc_state *crtc_state) 1156 { 1157 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 1158 u32 plane_ctl = 0; 1159 1160 if (DISPLAY_VER(dev_priv) >= 10) 1161 return plane_ctl; 1162 1163 if (crtc_state->gamma_enable) 1164 plane_ctl |= PLANE_CTL_PIPE_GAMMA_ENABLE; 1165 1166 if (crtc_state->csc_enable) 1167 plane_ctl |= PLANE_CTL_PIPE_CSC_ENABLE; 1168 1169 return plane_ctl; 1170 } 1171 1172 static u32 skl_plane_ctl(const struct intel_crtc_state *crtc_state, 1173 const struct intel_plane_state *plane_state) 1174 { 1175 struct drm_i915_private *dev_priv = 1176 to_i915(plane_state->uapi.plane->dev); 1177 const struct drm_framebuffer *fb = plane_state->hw.fb; 1178 unsigned int rotation = plane_state->hw.rotation; 1179 const struct drm_intel_sprite_colorkey *key = &plane_state->ckey; 1180 u32 plane_ctl; 1181 1182 plane_ctl = PLANE_CTL_ENABLE; 1183 1184 if (DISPLAY_VER(dev_priv) < 10) { 1185 plane_ctl |= skl_plane_ctl_alpha(plane_state); 1186 plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE; 1187 1188 if (plane_state->hw.color_encoding == DRM_COLOR_YCBCR_BT709) 1189 plane_ctl |= PLANE_CTL_YUV_TO_RGB_CSC_FORMAT_BT709; 1190 1191 if (plane_state->hw.color_range == DRM_COLOR_YCBCR_FULL_RANGE) 1192 plane_ctl |= PLANE_CTL_YUV_RANGE_CORRECTION_DISABLE; 1193 } 1194 1195 plane_ctl |= skl_plane_ctl_format(fb->format->format); 1196 plane_ctl |= skl_plane_ctl_tiling(fb->modifier); 1197 plane_ctl |= skl_plane_ctl_rotate(rotation & DRM_MODE_ROTATE_MASK); 1198 1199 if (DISPLAY_VER(dev_priv) >= 11) 1200 plane_ctl |= icl_plane_ctl_flip(rotation & 1201 DRM_MODE_REFLECT_MASK); 1202 1203 if (key->flags & I915_SET_COLORKEY_DESTINATION) 1204 plane_ctl |= PLANE_CTL_KEY_ENABLE_DESTINATION; 1205 else if (key->flags & I915_SET_COLORKEY_SOURCE) 1206 plane_ctl |= PLANE_CTL_KEY_ENABLE_SOURCE; 1207 1208 /* Wa_22012358565:adl-p */ 1209 if (DISPLAY_VER(dev_priv) == 13) 1210 plane_ctl |= adlp_plane_ctl_arb_slots(plane_state); 1211 1212 return plane_ctl; 1213 } 1214 1215 static u32 glk_plane_color_ctl_crtc(const struct intel_crtc_state *crtc_state) 1216 { 1217 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 1218 u32 plane_color_ctl = 0; 1219 1220 if (DISPLAY_VER(dev_priv) >= 11) 1221 return plane_color_ctl; 1222 1223 if (crtc_state->gamma_enable) 1224 plane_color_ctl |= PLANE_COLOR_PIPE_GAMMA_ENABLE; 1225 1226 if (crtc_state->csc_enable) 1227 plane_color_ctl |= PLANE_COLOR_PIPE_CSC_ENABLE; 1228 1229 return plane_color_ctl; 1230 } 1231 1232 static u32 glk_plane_color_ctl(const struct intel_crtc_state *crtc_state, 1233 const struct intel_plane_state *plane_state) 1234 { 1235 struct drm_i915_private *dev_priv = 1236 to_i915(plane_state->uapi.plane->dev); 1237 const struct drm_framebuffer *fb = plane_state->hw.fb; 1238 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); 1239 u32 plane_color_ctl = 0; 1240 1241 plane_color_ctl |= PLANE_COLOR_PLANE_GAMMA_DISABLE; 1242 plane_color_ctl |= glk_plane_color_ctl_alpha(plane_state); 1243 1244 if (fb->format->is_yuv && !icl_is_hdr_plane(dev_priv, plane->id)) { 1245 switch (plane_state->hw.color_encoding) { 1246 case DRM_COLOR_YCBCR_BT709: 1247 plane_color_ctl |= PLANE_COLOR_CSC_MODE_YUV709_TO_RGB709; 1248 break; 1249 case DRM_COLOR_YCBCR_BT2020: 1250 plane_color_ctl |= 1251 PLANE_COLOR_CSC_MODE_YUV2020_TO_RGB2020; 1252 break; 1253 default: 1254 plane_color_ctl |= 1255 PLANE_COLOR_CSC_MODE_YUV601_TO_RGB601; 1256 } 1257 if (plane_state->hw.color_range == DRM_COLOR_YCBCR_FULL_RANGE) 1258 plane_color_ctl |= PLANE_COLOR_YUV_RANGE_CORRECTION_DISABLE; 1259 } else if (fb->format->is_yuv) { 1260 plane_color_ctl |= PLANE_COLOR_INPUT_CSC_ENABLE; 1261 if (plane_state->hw.color_range == DRM_COLOR_YCBCR_FULL_RANGE) 1262 plane_color_ctl |= PLANE_COLOR_YUV_RANGE_CORRECTION_DISABLE; 1263 } 1264 1265 if (plane_state->force_black) 1266 plane_color_ctl |= PLANE_COLOR_PLANE_CSC_ENABLE; 1267 1268 return plane_color_ctl; 1269 } 1270 1271 static u32 skl_surf_address(const struct intel_plane_state *plane_state, 1272 int color_plane) 1273 { 1274 struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev); 1275 const struct drm_framebuffer *fb = plane_state->hw.fb; 1276 u32 offset = plane_state->view.color_plane[color_plane].offset; 1277 1278 if (intel_fb_uses_dpt(fb)) { 1279 /* 1280 * The DPT object contains only one vma, so the VMA's offset 1281 * within the DPT is always 0. 1282 */ 1283 drm_WARN_ON(&i915->drm, plane_state->dpt_vma && 1284 intel_dpt_offset(plane_state->dpt_vma)); 1285 drm_WARN_ON(&i915->drm, offset & 0x1fffff); 1286 return offset >> 9; 1287 } else { 1288 drm_WARN_ON(&i915->drm, offset & 0xfff); 1289 return offset; 1290 } 1291 } 1292 1293 static u32 skl_plane_surf(const struct intel_plane_state *plane_state, 1294 int color_plane) 1295 { 1296 u32 plane_surf; 1297 1298 plane_surf = intel_plane_ggtt_offset(plane_state) + 1299 skl_surf_address(plane_state, color_plane); 1300 1301 if (plane_state->decrypt) 1302 plane_surf |= PLANE_SURF_DECRYPT; 1303 1304 return plane_surf; 1305 } 1306 1307 u32 skl_plane_aux_dist(const struct intel_plane_state *plane_state, 1308 int color_plane) 1309 { 1310 struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev); 1311 const struct drm_framebuffer *fb = plane_state->hw.fb; 1312 int aux_plane = skl_main_to_aux_plane(fb, color_plane); 1313 u32 aux_dist; 1314 1315 if (!aux_plane) 1316 return 0; 1317 1318 aux_dist = skl_surf_address(plane_state, aux_plane) - 1319 skl_surf_address(plane_state, color_plane); 1320 1321 if (DISPLAY_VER(i915) < 12) 1322 aux_dist |= PLANE_AUX_STRIDE(skl_plane_stride(plane_state, aux_plane)); 1323 1324 return aux_dist; 1325 } 1326 1327 static u32 skl_plane_keyval(const struct intel_plane_state *plane_state) 1328 { 1329 const struct drm_intel_sprite_colorkey *key = &plane_state->ckey; 1330 1331 return key->min_value; 1332 } 1333 1334 static u32 skl_plane_keymax(const struct intel_plane_state *plane_state) 1335 { 1336 const struct drm_intel_sprite_colorkey *key = &plane_state->ckey; 1337 u8 alpha = plane_state->hw.alpha >> 8; 1338 1339 return (key->max_value & 0xffffff) | PLANE_KEYMAX_ALPHA(alpha); 1340 } 1341 1342 static u32 skl_plane_keymsk(const struct intel_plane_state *plane_state) 1343 { 1344 const struct drm_intel_sprite_colorkey *key = &plane_state->ckey; 1345 u8 alpha = plane_state->hw.alpha >> 8; 1346 u32 keymsk; 1347 1348 keymsk = key->channel_mask & 0x7ffffff; 1349 if (alpha < 0xff) 1350 keymsk |= PLANE_KEYMSK_ALPHA_ENABLE; 1351 1352 return keymsk; 1353 } 1354 1355 static void icl_plane_csc_load_black(struct intel_dsb *dsb, 1356 struct intel_plane *plane, 1357 const struct intel_crtc_state *crtc_state) 1358 { 1359 struct intel_display *display = to_intel_display(plane->base.dev); 1360 enum plane_id plane_id = plane->id; 1361 enum pipe pipe = plane->pipe; 1362 1363 intel_de_write_dsb(display, dsb, PLANE_CSC_COEFF(pipe, plane_id, 0), 0); 1364 intel_de_write_dsb(display, dsb, PLANE_CSC_COEFF(pipe, plane_id, 1), 0); 1365 1366 intel_de_write_dsb(display, dsb, PLANE_CSC_COEFF(pipe, plane_id, 2), 0); 1367 intel_de_write_dsb(display, dsb, PLANE_CSC_COEFF(pipe, plane_id, 3), 0); 1368 1369 intel_de_write_dsb(display, dsb, PLANE_CSC_COEFF(pipe, plane_id, 4), 0); 1370 intel_de_write_dsb(display, dsb, PLANE_CSC_COEFF(pipe, plane_id, 5), 0); 1371 1372 intel_de_write_dsb(display, dsb, PLANE_CSC_PREOFF(pipe, plane_id, 0), 0); 1373 intel_de_write_dsb(display, dsb, PLANE_CSC_PREOFF(pipe, plane_id, 1), 0); 1374 intel_de_write_dsb(display, dsb, PLANE_CSC_PREOFF(pipe, plane_id, 2), 0); 1375 1376 intel_de_write_dsb(display, dsb, PLANE_CSC_POSTOFF(pipe, plane_id, 0), 0); 1377 intel_de_write_dsb(display, dsb, PLANE_CSC_POSTOFF(pipe, plane_id, 1), 0); 1378 intel_de_write_dsb(display, dsb, PLANE_CSC_POSTOFF(pipe, plane_id, 2), 0); 1379 } 1380 1381 static int icl_plane_color_plane(const struct intel_plane_state *plane_state) 1382 { 1383 /* Program the UV plane on planar master */ 1384 if (plane_state->planar_linked_plane && !plane_state->planar_slave) 1385 return 1; 1386 else 1387 return 0; 1388 } 1389 1390 static void 1391 skl_plane_update_noarm(struct intel_dsb *dsb, 1392 struct intel_plane *plane, 1393 const struct intel_crtc_state *crtc_state, 1394 const struct intel_plane_state *plane_state) 1395 { 1396 struct intel_display *display = to_intel_display(plane->base.dev); 1397 enum plane_id plane_id = plane->id; 1398 enum pipe pipe = plane->pipe; 1399 u32 stride = skl_plane_stride(plane_state, 0); 1400 int crtc_x = plane_state->uapi.dst.x1; 1401 int crtc_y = plane_state->uapi.dst.y1; 1402 u32 src_w = drm_rect_width(&plane_state->uapi.src) >> 16; 1403 u32 src_h = drm_rect_height(&plane_state->uapi.src) >> 16; 1404 1405 /* The scaler will handle the output position */ 1406 if (plane_state->scaler_id >= 0) { 1407 crtc_x = 0; 1408 crtc_y = 0; 1409 } 1410 1411 intel_de_write_dsb(display, dsb, PLANE_STRIDE(pipe, plane_id), 1412 PLANE_STRIDE_(stride)); 1413 intel_de_write_dsb(display, dsb, PLANE_POS(pipe, plane_id), 1414 PLANE_POS_Y(crtc_y) | PLANE_POS_X(crtc_x)); 1415 intel_de_write_dsb(display, dsb, PLANE_SIZE(pipe, plane_id), 1416 PLANE_HEIGHT(src_h - 1) | PLANE_WIDTH(src_w - 1)); 1417 1418 skl_write_plane_wm(dsb, plane, crtc_state); 1419 } 1420 1421 static void 1422 skl_plane_update_arm(struct intel_dsb *dsb, 1423 struct intel_plane *plane, 1424 const struct intel_crtc_state *crtc_state, 1425 const struct intel_plane_state *plane_state) 1426 { 1427 struct intel_display *display = to_intel_display(plane->base.dev); 1428 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 1429 enum plane_id plane_id = plane->id; 1430 enum pipe pipe = plane->pipe; 1431 u32 x = plane_state->view.color_plane[0].x; 1432 u32 y = plane_state->view.color_plane[0].y; 1433 u32 plane_ctl, plane_color_ctl = 0; 1434 1435 plane_ctl = plane_state->ctl | 1436 skl_plane_ctl_crtc(crtc_state); 1437 1438 /* see intel_plane_atomic_calc_changes() */ 1439 if (plane->need_async_flip_toggle_wa && 1440 crtc_state->async_flip_planes & BIT(plane->id)) 1441 plane_ctl |= PLANE_CTL_ASYNC_FLIP; 1442 1443 if (DISPLAY_VER(dev_priv) >= 10) 1444 plane_color_ctl = plane_state->color_ctl | 1445 glk_plane_color_ctl_crtc(crtc_state); 1446 1447 intel_de_write_dsb(display, dsb, PLANE_KEYVAL(pipe, plane_id), 1448 skl_plane_keyval(plane_state)); 1449 intel_de_write_dsb(display, dsb, PLANE_KEYMSK(pipe, plane_id), 1450 skl_plane_keymsk(plane_state)); 1451 intel_de_write_dsb(display, dsb, PLANE_KEYMAX(pipe, plane_id), 1452 skl_plane_keymax(plane_state)); 1453 1454 intel_de_write_dsb(display, dsb, PLANE_OFFSET(pipe, plane_id), 1455 PLANE_OFFSET_Y(y) | PLANE_OFFSET_X(x)); 1456 1457 intel_de_write_dsb(display, dsb, PLANE_AUX_DIST(pipe, plane_id), 1458 skl_plane_aux_dist(plane_state, 0)); 1459 1460 intel_de_write_dsb(display, dsb, PLANE_AUX_OFFSET(pipe, plane_id), 1461 PLANE_OFFSET_Y(plane_state->view.color_plane[1].y) | 1462 PLANE_OFFSET_X(plane_state->view.color_plane[1].x)); 1463 1464 if (DISPLAY_VER(dev_priv) >= 10) 1465 intel_de_write_dsb(display, dsb, PLANE_COLOR_CTL(pipe, plane_id), 1466 plane_color_ctl); 1467 1468 /* 1469 * Enable the scaler before the plane so that we don't 1470 * get a catastrophic underrun even if the two operations 1471 * end up happening in two different frames. 1472 * 1473 * TODO: split into noarm+arm pair 1474 */ 1475 if (plane_state->scaler_id >= 0) 1476 skl_program_plane_scaler(plane, crtc_state, plane_state); 1477 1478 /* 1479 * The control register self-arms if the plane was previously 1480 * disabled. Try to make the plane enable atomic by writing 1481 * the control register just before the surface register. 1482 */ 1483 intel_de_write_dsb(display, dsb, PLANE_CTL(pipe, plane_id), 1484 plane_ctl); 1485 intel_de_write_dsb(display, dsb, PLANE_SURF(pipe, plane_id), 1486 skl_plane_surf(plane_state, 0)); 1487 } 1488 1489 static void icl_plane_update_sel_fetch_noarm(struct intel_dsb *dsb, 1490 struct intel_plane *plane, 1491 const struct intel_crtc_state *crtc_state, 1492 const struct intel_plane_state *plane_state, 1493 int color_plane) 1494 { 1495 struct intel_display *display = to_intel_display(plane->base.dev); 1496 enum pipe pipe = plane->pipe; 1497 const struct drm_rect *clip; 1498 u32 val; 1499 int x, y; 1500 1501 if (!crtc_state->enable_psr2_sel_fetch) 1502 return; 1503 1504 clip = &plane_state->psr2_sel_fetch_area; 1505 1506 if (crtc_state->enable_psr2_su_region_et) 1507 y = max(0, plane_state->uapi.dst.y1 - crtc_state->psr2_su_area.y1); 1508 else 1509 y = (clip->y1 + plane_state->uapi.dst.y1); 1510 val = y << 16; 1511 val |= plane_state->uapi.dst.x1; 1512 intel_de_write_dsb(display, dsb, SEL_FETCH_PLANE_POS(pipe, plane->id), val); 1513 1514 x = plane_state->view.color_plane[color_plane].x; 1515 1516 /* 1517 * From Bspec: UV surface Start Y Position = half of Y plane Y 1518 * start position. 1519 */ 1520 if (!color_plane) 1521 y = plane_state->view.color_plane[color_plane].y + clip->y1; 1522 else 1523 y = plane_state->view.color_plane[color_plane].y + clip->y1 / 2; 1524 1525 val = y << 16 | x; 1526 1527 intel_de_write_dsb(display, dsb, SEL_FETCH_PLANE_OFFSET(pipe, plane->id), val); 1528 1529 /* Sizes are 0 based */ 1530 val = (drm_rect_height(clip) - 1) << 16; 1531 val |= (drm_rect_width(&plane_state->uapi.src) >> 16) - 1; 1532 intel_de_write_dsb(display, dsb, SEL_FETCH_PLANE_SIZE(pipe, plane->id), val); 1533 } 1534 1535 static void 1536 icl_plane_update_noarm(struct intel_dsb *dsb, 1537 struct intel_plane *plane, 1538 const struct intel_crtc_state *crtc_state, 1539 const struct intel_plane_state *plane_state) 1540 { 1541 struct intel_display *display = to_intel_display(plane->base.dev); 1542 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 1543 enum plane_id plane_id = plane->id; 1544 enum pipe pipe = plane->pipe; 1545 int color_plane = icl_plane_color_plane(plane_state); 1546 u32 stride = skl_plane_stride(plane_state, color_plane); 1547 const struct drm_framebuffer *fb = plane_state->hw.fb; 1548 int crtc_x = plane_state->uapi.dst.x1; 1549 int crtc_y = plane_state->uapi.dst.y1; 1550 int x = plane_state->view.color_plane[color_plane].x; 1551 int y = plane_state->view.color_plane[color_plane].y; 1552 int src_w = drm_rect_width(&plane_state->uapi.src) >> 16; 1553 int src_h = drm_rect_height(&plane_state->uapi.src) >> 16; 1554 u32 plane_color_ctl; 1555 1556 plane_color_ctl = plane_state->color_ctl | 1557 glk_plane_color_ctl_crtc(crtc_state); 1558 1559 /* The scaler will handle the output position */ 1560 if (plane_state->scaler_id >= 0) { 1561 crtc_x = 0; 1562 crtc_y = 0; 1563 } 1564 1565 intel_de_write_dsb(display, dsb, PLANE_STRIDE(pipe, plane_id), 1566 PLANE_STRIDE_(stride)); 1567 intel_de_write_dsb(display, dsb, PLANE_POS(pipe, plane_id), 1568 PLANE_POS_Y(crtc_y) | PLANE_POS_X(crtc_x)); 1569 intel_de_write_dsb(display, dsb, PLANE_SIZE(pipe, plane_id), 1570 PLANE_HEIGHT(src_h - 1) | PLANE_WIDTH(src_w - 1)); 1571 1572 intel_de_write_dsb(display, dsb, PLANE_KEYVAL(pipe, plane_id), 1573 skl_plane_keyval(plane_state)); 1574 intel_de_write_dsb(display, dsb, PLANE_KEYMSK(pipe, plane_id), 1575 skl_plane_keymsk(plane_state)); 1576 intel_de_write_dsb(display, dsb, PLANE_KEYMAX(pipe, plane_id), 1577 skl_plane_keymax(plane_state)); 1578 1579 intel_de_write_dsb(display, dsb, PLANE_OFFSET(pipe, plane_id), 1580 PLANE_OFFSET_Y(y) | PLANE_OFFSET_X(x)); 1581 1582 if (intel_fb_is_rc_ccs_cc_modifier(fb->modifier)) { 1583 intel_de_write_dsb(display, dsb, PLANE_CC_VAL(pipe, plane_id, 0), 1584 lower_32_bits(plane_state->ccval)); 1585 intel_de_write_dsb(display, dsb, PLANE_CC_VAL(pipe, plane_id, 1), 1586 upper_32_bits(plane_state->ccval)); 1587 } 1588 1589 /* FLAT CCS doesn't need to program AUX_DIST */ 1590 if (!HAS_FLAT_CCS(dev_priv) && DISPLAY_VER(dev_priv) < 20) 1591 intel_de_write_dsb(display, dsb, PLANE_AUX_DIST(pipe, plane_id), 1592 skl_plane_aux_dist(plane_state, color_plane)); 1593 1594 if (icl_is_hdr_plane(dev_priv, plane_id)) 1595 intel_de_write_dsb(display, dsb, PLANE_CUS_CTL(pipe, plane_id), 1596 plane_state->cus_ctl); 1597 1598 intel_de_write_dsb(display, dsb, PLANE_COLOR_CTL(pipe, plane_id), 1599 plane_color_ctl); 1600 1601 if (fb->format->is_yuv && icl_is_hdr_plane(dev_priv, plane_id)) 1602 icl_program_input_csc(dsb, plane, plane_state); 1603 1604 skl_write_plane_wm(dsb, plane, crtc_state); 1605 1606 /* 1607 * FIXME: pxp session invalidation can hit any time even at time of commit 1608 * or after the commit, display content will be garbage. 1609 */ 1610 if (plane_state->force_black) 1611 icl_plane_csc_load_black(dsb, plane, crtc_state); 1612 1613 icl_plane_update_sel_fetch_noarm(dsb, plane, crtc_state, plane_state, color_plane); 1614 } 1615 1616 static void icl_plane_update_sel_fetch_arm(struct intel_dsb *dsb, 1617 struct intel_plane *plane, 1618 const struct intel_crtc_state *crtc_state, 1619 const struct intel_plane_state *plane_state) 1620 { 1621 struct intel_display *display = to_intel_display(plane->base.dev); 1622 enum pipe pipe = plane->pipe; 1623 1624 if (!crtc_state->enable_psr2_sel_fetch) 1625 return; 1626 1627 if (drm_rect_height(&plane_state->psr2_sel_fetch_area) > 0) 1628 intel_de_write_dsb(display, dsb, SEL_FETCH_PLANE_CTL(pipe, plane->id), 1629 SEL_FETCH_PLANE_CTL_ENABLE); 1630 else 1631 icl_plane_disable_sel_fetch_arm(dsb, plane, crtc_state); 1632 } 1633 1634 static void 1635 icl_plane_update_arm(struct intel_dsb *dsb, 1636 struct intel_plane *plane, 1637 const struct intel_crtc_state *crtc_state, 1638 const struct intel_plane_state *plane_state) 1639 { 1640 struct intel_display *display = to_intel_display(plane->base.dev); 1641 enum plane_id plane_id = plane->id; 1642 enum pipe pipe = plane->pipe; 1643 int color_plane = icl_plane_color_plane(plane_state); 1644 u32 plane_ctl; 1645 1646 plane_ctl = plane_state->ctl | 1647 skl_plane_ctl_crtc(crtc_state); 1648 1649 /* 1650 * Enable the scaler before the plane so that we don't 1651 * get a catastrophic underrun even if the two operations 1652 * end up happening in two different frames. 1653 * 1654 * TODO: split into noarm+arm pair 1655 */ 1656 if (plane_state->scaler_id >= 0) 1657 skl_program_plane_scaler(plane, crtc_state, plane_state); 1658 1659 icl_plane_update_sel_fetch_arm(dsb, plane, crtc_state, plane_state); 1660 1661 /* 1662 * The control register self-arms if the plane was previously 1663 * disabled. Try to make the plane enable atomic by writing 1664 * the control register just before the surface register. 1665 */ 1666 intel_de_write_dsb(display, dsb, PLANE_CTL(pipe, plane_id), 1667 plane_ctl); 1668 intel_de_write_dsb(display, dsb, PLANE_SURF(pipe, plane_id), 1669 skl_plane_surf(plane_state, color_plane)); 1670 } 1671 1672 static void 1673 skl_plane_async_flip(struct intel_dsb *dsb, 1674 struct intel_plane *plane, 1675 const struct intel_crtc_state *crtc_state, 1676 const struct intel_plane_state *plane_state, 1677 bool async_flip) 1678 { 1679 struct intel_display *display = to_intel_display(plane->base.dev); 1680 enum plane_id plane_id = plane->id; 1681 enum pipe pipe = plane->pipe; 1682 u32 plane_ctl = plane_state->ctl, plane_surf; 1683 1684 plane_ctl |= skl_plane_ctl_crtc(crtc_state); 1685 plane_surf = skl_plane_surf(plane_state, 0); 1686 1687 if (async_flip) { 1688 if (DISPLAY_VER(display) >= 30) 1689 plane_surf |= PLANE_SURF_ASYNC_UPDATE; 1690 else 1691 plane_ctl |= PLANE_CTL_ASYNC_FLIP; 1692 } 1693 1694 intel_de_write_dsb(display, dsb, PLANE_CTL(pipe, plane_id), 1695 plane_ctl); 1696 intel_de_write_dsb(display, dsb, PLANE_SURF(pipe, plane_id), 1697 plane_surf); 1698 } 1699 1700 static bool intel_format_is_p01x(u32 format) 1701 { 1702 switch (format) { 1703 case DRM_FORMAT_P010: 1704 case DRM_FORMAT_P012: 1705 case DRM_FORMAT_P016: 1706 return true; 1707 default: 1708 return false; 1709 } 1710 } 1711 1712 static int skl_plane_check_fb(const struct intel_crtc_state *crtc_state, 1713 const struct intel_plane_state *plane_state) 1714 { 1715 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); 1716 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 1717 const struct drm_framebuffer *fb = plane_state->hw.fb; 1718 unsigned int rotation = plane_state->hw.rotation; 1719 1720 if (!fb) 1721 return 0; 1722 1723 if (rotation & ~(DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180) && 1724 intel_fb_is_ccs_modifier(fb->modifier)) { 1725 drm_dbg_kms(&dev_priv->drm, 1726 "RC support only with 0/180 degree rotation (%x)\n", 1727 rotation); 1728 return -EINVAL; 1729 } 1730 1731 if (rotation & DRM_MODE_REFLECT_X && 1732 fb->modifier == DRM_FORMAT_MOD_LINEAR) { 1733 drm_dbg_kms(&dev_priv->drm, 1734 "horizontal flip is not supported with linear surface formats\n"); 1735 return -EINVAL; 1736 } 1737 1738 /* 1739 * Display20 onward tile4 hflip is not supported 1740 */ 1741 if (rotation & DRM_MODE_REFLECT_X && 1742 intel_fb_is_tile4_modifier(fb->modifier) && 1743 DISPLAY_VER(dev_priv) >= 20) { 1744 drm_dbg_kms(&dev_priv->drm, 1745 "horizontal flip is not supported with tile4 surface formats\n"); 1746 return -EINVAL; 1747 } 1748 1749 if (drm_rotation_90_or_270(rotation)) { 1750 if (!intel_fb_supports_90_270_rotation(to_intel_framebuffer(fb))) { 1751 drm_dbg_kms(&dev_priv->drm, 1752 "Y/Yf tiling required for 90/270!\n"); 1753 return -EINVAL; 1754 } 1755 1756 /* 1757 * 90/270 is not allowed with RGB64 16:16:16:16 and 1758 * Indexed 8-bit. RGB 16-bit 5:6:5 is allowed gen11 onwards. 1759 */ 1760 switch (fb->format->format) { 1761 case DRM_FORMAT_RGB565: 1762 if (DISPLAY_VER(dev_priv) >= 11) 1763 break; 1764 fallthrough; 1765 case DRM_FORMAT_C8: 1766 case DRM_FORMAT_XRGB16161616F: 1767 case DRM_FORMAT_XBGR16161616F: 1768 case DRM_FORMAT_ARGB16161616F: 1769 case DRM_FORMAT_ABGR16161616F: 1770 case DRM_FORMAT_Y210: 1771 case DRM_FORMAT_Y212: 1772 case DRM_FORMAT_Y216: 1773 case DRM_FORMAT_XVYU12_16161616: 1774 case DRM_FORMAT_XVYU16161616: 1775 drm_dbg_kms(&dev_priv->drm, 1776 "Unsupported pixel format %p4cc for 90/270!\n", 1777 &fb->format->format); 1778 return -EINVAL; 1779 default: 1780 break; 1781 } 1782 } 1783 1784 /* Y-tiling is not supported in IF-ID Interlace mode */ 1785 if (crtc_state->hw.enable && 1786 crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE && 1787 fb->modifier != DRM_FORMAT_MOD_LINEAR && 1788 fb->modifier != I915_FORMAT_MOD_X_TILED) { 1789 drm_dbg_kms(&dev_priv->drm, 1790 "Y/Yf tiling not supported in IF-ID mode\n"); 1791 return -EINVAL; 1792 } 1793 1794 /* Wa_1606054188:tgl,adl-s */ 1795 if ((IS_ALDERLAKE_S(dev_priv) || IS_TIGERLAKE(dev_priv)) && 1796 plane_state->ckey.flags & I915_SET_COLORKEY_SOURCE && 1797 intel_format_is_p01x(fb->format->format)) { 1798 drm_dbg_kms(&dev_priv->drm, 1799 "Source color keying not supported with P01x formats\n"); 1800 return -EINVAL; 1801 } 1802 1803 return 0; 1804 } 1805 1806 static int skl_plane_check_dst_coordinates(const struct intel_crtc_state *crtc_state, 1807 const struct intel_plane_state *plane_state) 1808 { 1809 struct drm_i915_private *dev_priv = 1810 to_i915(plane_state->uapi.plane->dev); 1811 int crtc_x = plane_state->uapi.dst.x1; 1812 int crtc_w = drm_rect_width(&plane_state->uapi.dst); 1813 int pipe_src_w = drm_rect_width(&crtc_state->pipe_src); 1814 1815 /* 1816 * Display WA #1175: glk 1817 * Planes other than the cursor may cause FIFO underflow and display 1818 * corruption if starting less than 4 pixels from the right edge of 1819 * the screen. 1820 * Besides the above WA fix the similar problem, where planes other 1821 * than the cursor ending less than 4 pixels from the left edge of the 1822 * screen may cause FIFO underflow and display corruption. 1823 */ 1824 if (DISPLAY_VER(dev_priv) == 10 && 1825 (crtc_x + crtc_w < 4 || crtc_x > pipe_src_w - 4)) { 1826 drm_dbg_kms(&dev_priv->drm, 1827 "requested plane X %s position %d invalid (valid range %d-%d)\n", 1828 crtc_x + crtc_w < 4 ? "end" : "start", 1829 crtc_x + crtc_w < 4 ? crtc_x + crtc_w : crtc_x, 1830 4, pipe_src_w - 4); 1831 return -ERANGE; 1832 } 1833 1834 return 0; 1835 } 1836 1837 static int skl_plane_check_nv12_rotation(const struct intel_plane_state *plane_state) 1838 { 1839 struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev); 1840 const struct drm_framebuffer *fb = plane_state->hw.fb; 1841 unsigned int rotation = plane_state->hw.rotation; 1842 int src_w = drm_rect_width(&plane_state->uapi.src) >> 16; 1843 1844 /* Display WA #1106 */ 1845 if (intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier) && 1846 src_w & 3 && 1847 (rotation == DRM_MODE_ROTATE_270 || 1848 rotation == (DRM_MODE_REFLECT_X | DRM_MODE_ROTATE_90))) { 1849 drm_dbg_kms(&i915->drm, "src width must be multiple of 4 for rotated planar YUV\n"); 1850 return -EINVAL; 1851 } 1852 1853 return 0; 1854 } 1855 1856 static int skl_plane_max_scale(struct drm_i915_private *dev_priv, 1857 const struct drm_framebuffer *fb) 1858 { 1859 /* 1860 * We don't yet know the final source width nor 1861 * whether we can use the HQ scaler mode. Assume 1862 * the best case. 1863 * FIXME need to properly check this later. 1864 */ 1865 if (DISPLAY_VER(dev_priv) >= 10 || 1866 !intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier)) 1867 return 0x30000 - 1; 1868 else 1869 return 0x20000 - 1; 1870 } 1871 1872 static int intel_plane_min_width(struct intel_plane *plane, 1873 const struct drm_framebuffer *fb, 1874 int color_plane, 1875 unsigned int rotation) 1876 { 1877 if (plane->min_width) 1878 return plane->min_width(fb, color_plane, rotation); 1879 else 1880 return 1; 1881 } 1882 1883 static int intel_plane_max_width(struct intel_plane *plane, 1884 const struct drm_framebuffer *fb, 1885 int color_plane, 1886 unsigned int rotation) 1887 { 1888 if (plane->max_width) 1889 return plane->max_width(fb, color_plane, rotation); 1890 else 1891 return INT_MAX; 1892 } 1893 1894 static int intel_plane_max_height(struct intel_plane *plane, 1895 const struct drm_framebuffer *fb, 1896 int color_plane, 1897 unsigned int rotation) 1898 { 1899 if (plane->max_height) 1900 return plane->max_height(fb, color_plane, rotation); 1901 else 1902 return INT_MAX; 1903 } 1904 1905 static bool 1906 skl_check_main_ccs_coordinates(struct intel_plane_state *plane_state, 1907 int main_x, int main_y, u32 main_offset, 1908 int ccs_plane) 1909 { 1910 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); 1911 const struct drm_framebuffer *fb = plane_state->hw.fb; 1912 int aux_x = plane_state->view.color_plane[ccs_plane].x; 1913 int aux_y = plane_state->view.color_plane[ccs_plane].y; 1914 u32 aux_offset = plane_state->view.color_plane[ccs_plane].offset; 1915 unsigned int alignment = plane->min_alignment(plane, fb, ccs_plane); 1916 int hsub; 1917 int vsub; 1918 1919 intel_fb_plane_get_subsampling(&hsub, &vsub, fb, ccs_plane); 1920 while (aux_offset >= main_offset && aux_y <= main_y) { 1921 int x, y; 1922 1923 if (aux_x == main_x && aux_y == main_y) 1924 break; 1925 1926 if (aux_offset == 0) 1927 break; 1928 1929 x = aux_x / hsub; 1930 y = aux_y / vsub; 1931 aux_offset = intel_plane_adjust_aligned_offset(&x, &y, 1932 plane_state, 1933 ccs_plane, 1934 aux_offset, 1935 aux_offset - alignment); 1936 aux_x = x * hsub + aux_x % hsub; 1937 aux_y = y * vsub + aux_y % vsub; 1938 } 1939 1940 if (aux_x != main_x || aux_y != main_y) 1941 return false; 1942 1943 plane_state->view.color_plane[ccs_plane].offset = aux_offset; 1944 plane_state->view.color_plane[ccs_plane].x = aux_x; 1945 plane_state->view.color_plane[ccs_plane].y = aux_y; 1946 1947 return true; 1948 } 1949 1950 1951 int skl_calc_main_surface_offset(const struct intel_plane_state *plane_state, 1952 int *x, int *y, u32 *offset) 1953 { 1954 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); 1955 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 1956 const struct drm_framebuffer *fb = plane_state->hw.fb; 1957 int aux_plane = skl_main_to_aux_plane(fb, 0); 1958 u32 aux_offset = plane_state->view.color_plane[aux_plane].offset; 1959 unsigned int alignment = plane->min_alignment(plane, fb, 0); 1960 int w = drm_rect_width(&plane_state->uapi.src) >> 16; 1961 1962 intel_add_fb_offsets(x, y, plane_state, 0); 1963 *offset = intel_plane_compute_aligned_offset(x, y, plane_state, 0); 1964 if (drm_WARN_ON(&dev_priv->drm, alignment && !is_power_of_2(alignment))) 1965 return -EINVAL; 1966 1967 /* 1968 * AUX surface offset is specified as the distance from the 1969 * main surface offset, and it must be non-negative. Make 1970 * sure that is what we will get. 1971 */ 1972 if (aux_plane && *offset > aux_offset) 1973 *offset = intel_plane_adjust_aligned_offset(x, y, plane_state, 0, 1974 *offset, 1975 aux_offset & ~(alignment - 1)); 1976 1977 /* 1978 * When using an X-tiled surface, the plane blows up 1979 * if the x offset + width exceed the stride. 1980 * 1981 * TODO: linear and Y-tiled seem fine, Yf untested, 1982 */ 1983 if (fb->modifier == I915_FORMAT_MOD_X_TILED) { 1984 int cpp = fb->format->cpp[0]; 1985 1986 while ((*x + w) * cpp > plane_state->view.color_plane[0].mapping_stride) { 1987 if (*offset == 0) { 1988 drm_dbg_kms(&dev_priv->drm, 1989 "Unable to find suitable display surface offset due to X-tiling\n"); 1990 return -EINVAL; 1991 } 1992 1993 *offset = intel_plane_adjust_aligned_offset(x, y, plane_state, 0, 1994 *offset, 1995 *offset - alignment); 1996 } 1997 } 1998 1999 return 0; 2000 } 2001 2002 static int skl_check_main_surface(struct intel_plane_state *plane_state) 2003 { 2004 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); 2005 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 2006 const struct drm_framebuffer *fb = plane_state->hw.fb; 2007 unsigned int rotation = plane_state->hw.rotation; 2008 int x = plane_state->uapi.src.x1 >> 16; 2009 int y = plane_state->uapi.src.y1 >> 16; 2010 int w = drm_rect_width(&plane_state->uapi.src) >> 16; 2011 int h = drm_rect_height(&plane_state->uapi.src) >> 16; 2012 int min_width = intel_plane_min_width(plane, fb, 0, rotation); 2013 int max_width = intel_plane_max_width(plane, fb, 0, rotation); 2014 int max_height = intel_plane_max_height(plane, fb, 0, rotation); 2015 unsigned int alignment = plane->min_alignment(plane, fb, 0); 2016 int aux_plane = skl_main_to_aux_plane(fb, 0); 2017 u32 offset; 2018 int ret; 2019 2020 if (w > max_width || w < min_width || h > max_height || h < 1) { 2021 drm_dbg_kms(&dev_priv->drm, 2022 "requested Y/RGB source size %dx%d outside limits (min: %dx1 max: %dx%d)\n", 2023 w, h, min_width, max_width, max_height); 2024 return -EINVAL; 2025 } 2026 2027 ret = skl_calc_main_surface_offset(plane_state, &x, &y, &offset); 2028 if (ret) 2029 return ret; 2030 2031 /* 2032 * CCS AUX surface doesn't have its own x/y offsets, we must make sure 2033 * they match with the main surface x/y offsets. On DG2 2034 * there's no aux plane on fb so skip this checking. 2035 */ 2036 if (intel_fb_is_ccs_modifier(fb->modifier) && aux_plane) { 2037 while (!skl_check_main_ccs_coordinates(plane_state, x, y, 2038 offset, aux_plane)) { 2039 if (offset == 0) 2040 break; 2041 2042 offset = intel_plane_adjust_aligned_offset(&x, &y, plane_state, 0, 2043 offset, offset - alignment); 2044 } 2045 2046 if (x != plane_state->view.color_plane[aux_plane].x || 2047 y != plane_state->view.color_plane[aux_plane].y) { 2048 drm_dbg_kms(&dev_priv->drm, 2049 "Unable to find suitable display surface offset due to CCS\n"); 2050 return -EINVAL; 2051 } 2052 } 2053 2054 if (DISPLAY_VER(dev_priv) >= 13) 2055 drm_WARN_ON(&dev_priv->drm, x > 65535 || y > 65535); 2056 else 2057 drm_WARN_ON(&dev_priv->drm, x > 8191 || y > 8191); 2058 2059 plane_state->view.color_plane[0].offset = offset; 2060 plane_state->view.color_plane[0].x = x; 2061 plane_state->view.color_plane[0].y = y; 2062 2063 /* 2064 * Put the final coordinates back so that the src 2065 * coordinate checks will see the right values. 2066 */ 2067 drm_rect_translate_to(&plane_state->uapi.src, 2068 x << 16, y << 16); 2069 2070 return 0; 2071 } 2072 2073 static int skl_check_nv12_aux_surface(struct intel_plane_state *plane_state) 2074 { 2075 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); 2076 struct drm_i915_private *i915 = to_i915(plane->base.dev); 2077 const struct drm_framebuffer *fb = plane_state->hw.fb; 2078 unsigned int rotation = plane_state->hw.rotation; 2079 int uv_plane = 1; 2080 int ccs_plane = intel_fb_is_ccs_modifier(fb->modifier) ? 2081 skl_main_to_aux_plane(fb, uv_plane) : 0; 2082 int max_width = intel_plane_max_width(plane, fb, uv_plane, rotation); 2083 int max_height = intel_plane_max_height(plane, fb, uv_plane, rotation); 2084 int x = plane_state->uapi.src.x1 >> 17; 2085 int y = plane_state->uapi.src.y1 >> 17; 2086 int w = drm_rect_width(&plane_state->uapi.src) >> 17; 2087 int h = drm_rect_height(&plane_state->uapi.src) >> 17; 2088 u32 offset; 2089 2090 /* FIXME not quite sure how/if these apply to the chroma plane */ 2091 if (w > max_width || h > max_height) { 2092 drm_dbg_kms(&i915->drm, 2093 "CbCr source size %dx%d too big (limit %dx%d)\n", 2094 w, h, max_width, max_height); 2095 return -EINVAL; 2096 } 2097 2098 intel_add_fb_offsets(&x, &y, plane_state, uv_plane); 2099 offset = intel_plane_compute_aligned_offset(&x, &y, 2100 plane_state, uv_plane); 2101 2102 if (ccs_plane) { 2103 u32 aux_offset = plane_state->view.color_plane[ccs_plane].offset; 2104 unsigned int alignment = plane->min_alignment(plane, fb, uv_plane); 2105 2106 if (offset > aux_offset) 2107 offset = intel_plane_adjust_aligned_offset(&x, &y, 2108 plane_state, 2109 uv_plane, 2110 offset, 2111 aux_offset & ~(alignment - 1)); 2112 2113 while (!skl_check_main_ccs_coordinates(plane_state, x, y, 2114 offset, ccs_plane)) { 2115 if (offset == 0) 2116 break; 2117 2118 offset = intel_plane_adjust_aligned_offset(&x, &y, 2119 plane_state, 2120 uv_plane, 2121 offset, offset - alignment); 2122 } 2123 2124 if (x != plane_state->view.color_plane[ccs_plane].x || 2125 y != plane_state->view.color_plane[ccs_plane].y) { 2126 drm_dbg_kms(&i915->drm, 2127 "Unable to find suitable display surface offset due to CCS\n"); 2128 return -EINVAL; 2129 } 2130 } 2131 2132 if (DISPLAY_VER(i915) >= 13) 2133 drm_WARN_ON(&i915->drm, x > 65535 || y > 65535); 2134 else 2135 drm_WARN_ON(&i915->drm, x > 8191 || y > 8191); 2136 2137 plane_state->view.color_plane[uv_plane].offset = offset; 2138 plane_state->view.color_plane[uv_plane].x = x; 2139 plane_state->view.color_plane[uv_plane].y = y; 2140 2141 return 0; 2142 } 2143 2144 static int skl_check_ccs_aux_surface(struct intel_plane_state *plane_state) 2145 { 2146 const struct drm_framebuffer *fb = plane_state->hw.fb; 2147 int src_x = plane_state->uapi.src.x1 >> 16; 2148 int src_y = plane_state->uapi.src.y1 >> 16; 2149 u32 offset; 2150 int ccs_plane; 2151 2152 for (ccs_plane = 0; ccs_plane < fb->format->num_planes; ccs_plane++) { 2153 int main_hsub, main_vsub; 2154 int hsub, vsub; 2155 int x, y; 2156 2157 if (!intel_fb_is_ccs_aux_plane(fb, ccs_plane)) 2158 continue; 2159 2160 intel_fb_plane_get_subsampling(&main_hsub, &main_vsub, fb, 2161 skl_ccs_to_main_plane(fb, ccs_plane)); 2162 intel_fb_plane_get_subsampling(&hsub, &vsub, fb, ccs_plane); 2163 2164 hsub *= main_hsub; 2165 vsub *= main_vsub; 2166 x = src_x / hsub; 2167 y = src_y / vsub; 2168 2169 intel_add_fb_offsets(&x, &y, plane_state, ccs_plane); 2170 2171 offset = intel_plane_compute_aligned_offset(&x, &y, 2172 plane_state, 2173 ccs_plane); 2174 2175 plane_state->view.color_plane[ccs_plane].offset = offset; 2176 plane_state->view.color_plane[ccs_plane].x = (x * hsub + src_x % hsub) / main_hsub; 2177 plane_state->view.color_plane[ccs_plane].y = (y * vsub + src_y % vsub) / main_vsub; 2178 } 2179 2180 return 0; 2181 } 2182 2183 static int skl_check_plane_surface(struct intel_plane_state *plane_state) 2184 { 2185 const struct drm_framebuffer *fb = plane_state->hw.fb; 2186 int ret; 2187 2188 ret = intel_plane_compute_gtt(plane_state); 2189 if (ret) 2190 return ret; 2191 2192 if (!plane_state->uapi.visible) 2193 return 0; 2194 2195 /* 2196 * Handle the AUX surface first since the main surface setup depends on 2197 * it. 2198 */ 2199 if (intel_fb_is_ccs_modifier(fb->modifier)) { 2200 ret = skl_check_ccs_aux_surface(plane_state); 2201 if (ret) 2202 return ret; 2203 } 2204 2205 if (intel_format_info_is_yuv_semiplanar(fb->format, 2206 fb->modifier)) { 2207 ret = skl_check_nv12_aux_surface(plane_state); 2208 if (ret) 2209 return ret; 2210 } 2211 2212 ret = skl_check_main_surface(plane_state); 2213 if (ret) 2214 return ret; 2215 2216 return 0; 2217 } 2218 2219 static bool skl_fb_scalable(const struct drm_framebuffer *fb) 2220 { 2221 if (!fb) 2222 return false; 2223 2224 switch (fb->format->format) { 2225 case DRM_FORMAT_C8: 2226 return false; 2227 case DRM_FORMAT_XRGB16161616F: 2228 case DRM_FORMAT_ARGB16161616F: 2229 case DRM_FORMAT_XBGR16161616F: 2230 case DRM_FORMAT_ABGR16161616F: 2231 return DISPLAY_VER(to_i915(fb->dev)) >= 11; 2232 default: 2233 return true; 2234 } 2235 } 2236 2237 static void check_protection(struct intel_plane_state *plane_state) 2238 { 2239 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); 2240 struct drm_i915_private *i915 = to_i915(plane->base.dev); 2241 const struct drm_framebuffer *fb = plane_state->hw.fb; 2242 struct drm_gem_object *obj = intel_fb_bo(fb); 2243 2244 if (DISPLAY_VER(i915) < 11) 2245 return; 2246 2247 plane_state->decrypt = intel_pxp_key_check(i915->pxp, obj, false) == 0; 2248 plane_state->force_black = intel_bo_is_protected(obj) && 2249 !plane_state->decrypt; 2250 } 2251 2252 static int skl_plane_check(struct intel_crtc_state *crtc_state, 2253 struct intel_plane_state *plane_state) 2254 { 2255 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); 2256 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 2257 const struct drm_framebuffer *fb = plane_state->hw.fb; 2258 int min_scale = DRM_PLANE_NO_SCALING; 2259 int max_scale = DRM_PLANE_NO_SCALING; 2260 int ret; 2261 2262 ret = skl_plane_check_fb(crtc_state, plane_state); 2263 if (ret) 2264 return ret; 2265 2266 /* use scaler when colorkey is not required */ 2267 if (!plane_state->ckey.flags && skl_fb_scalable(fb)) { 2268 min_scale = 1; 2269 max_scale = skl_plane_max_scale(dev_priv, fb); 2270 } 2271 2272 ret = intel_atomic_plane_check_clipping(plane_state, crtc_state, 2273 min_scale, max_scale, true); 2274 if (ret) 2275 return ret; 2276 2277 ret = skl_check_plane_surface(plane_state); 2278 if (ret) 2279 return ret; 2280 2281 if (!plane_state->uapi.visible) 2282 return 0; 2283 2284 ret = skl_plane_check_dst_coordinates(crtc_state, plane_state); 2285 if (ret) 2286 return ret; 2287 2288 ret = intel_plane_check_src_coordinates(plane_state); 2289 if (ret) 2290 return ret; 2291 2292 ret = skl_plane_check_nv12_rotation(plane_state); 2293 if (ret) 2294 return ret; 2295 2296 check_protection(plane_state); 2297 2298 /* HW only has 8 bits pixel precision, disable plane if invisible */ 2299 if (!(plane_state->hw.alpha >> 8)) 2300 plane_state->uapi.visible = false; 2301 2302 plane_state->ctl = skl_plane_ctl(crtc_state, plane_state); 2303 2304 if (DISPLAY_VER(dev_priv) >= 10) 2305 plane_state->color_ctl = glk_plane_color_ctl(crtc_state, 2306 plane_state); 2307 2308 if (intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier) && 2309 icl_is_hdr_plane(dev_priv, plane->id)) 2310 /* Enable and use MPEG-2 chroma siting */ 2311 plane_state->cus_ctl = PLANE_CUS_ENABLE | 2312 PLANE_CUS_HPHASE_0 | 2313 PLANE_CUS_VPHASE_SIGN_NEGATIVE | PLANE_CUS_VPHASE_0_25; 2314 else 2315 plane_state->cus_ctl = 0; 2316 2317 return 0; 2318 } 2319 2320 static enum intel_fbc_id skl_fbc_id_for_pipe(enum pipe pipe) 2321 { 2322 return pipe - PIPE_A + INTEL_FBC_A; 2323 } 2324 2325 static bool skl_plane_has_fbc(struct drm_i915_private *i915, 2326 enum intel_fbc_id fbc_id, enum plane_id plane_id) 2327 { 2328 if ((DISPLAY_RUNTIME_INFO(i915)->fbc_mask & BIT(fbc_id)) == 0) 2329 return false; 2330 2331 if (DISPLAY_VER(i915) >= 20) 2332 return icl_is_hdr_plane(i915, plane_id); 2333 else 2334 return plane_id == PLANE_1; 2335 } 2336 2337 static struct intel_fbc *skl_plane_fbc(struct drm_i915_private *dev_priv, 2338 enum pipe pipe, enum plane_id plane_id) 2339 { 2340 enum intel_fbc_id fbc_id = skl_fbc_id_for_pipe(pipe); 2341 2342 if (skl_plane_has_fbc(dev_priv, fbc_id, plane_id)) 2343 return dev_priv->display.fbc[fbc_id]; 2344 else 2345 return NULL; 2346 } 2347 2348 static bool skl_plane_has_planar(struct drm_i915_private *dev_priv, 2349 enum pipe pipe, enum plane_id plane_id) 2350 { 2351 /* Display WA #0870: skl, bxt */ 2352 if (IS_SKYLAKE(dev_priv) || IS_BROXTON(dev_priv)) 2353 return false; 2354 2355 if (DISPLAY_VER(dev_priv) == 9 && pipe == PIPE_C) 2356 return false; 2357 2358 if (plane_id != PLANE_1 && plane_id != PLANE_2) 2359 return false; 2360 2361 return true; 2362 } 2363 2364 static const u32 *skl_get_plane_formats(struct drm_i915_private *dev_priv, 2365 enum pipe pipe, enum plane_id plane_id, 2366 int *num_formats) 2367 { 2368 if (skl_plane_has_planar(dev_priv, pipe, plane_id)) { 2369 *num_formats = ARRAY_SIZE(skl_planar_formats); 2370 return skl_planar_formats; 2371 } else { 2372 *num_formats = ARRAY_SIZE(skl_plane_formats); 2373 return skl_plane_formats; 2374 } 2375 } 2376 2377 static const u32 *glk_get_plane_formats(struct drm_i915_private *dev_priv, 2378 enum pipe pipe, enum plane_id plane_id, 2379 int *num_formats) 2380 { 2381 if (skl_plane_has_planar(dev_priv, pipe, plane_id)) { 2382 *num_formats = ARRAY_SIZE(glk_planar_formats); 2383 return glk_planar_formats; 2384 } else { 2385 *num_formats = ARRAY_SIZE(skl_plane_formats); 2386 return skl_plane_formats; 2387 } 2388 } 2389 2390 static const u32 *icl_get_plane_formats(struct drm_i915_private *dev_priv, 2391 enum pipe pipe, enum plane_id plane_id, 2392 int *num_formats) 2393 { 2394 if (icl_is_hdr_plane(dev_priv, plane_id)) { 2395 *num_formats = ARRAY_SIZE(icl_hdr_plane_formats); 2396 return icl_hdr_plane_formats; 2397 } else if (icl_is_nv12_y_plane(dev_priv, plane_id)) { 2398 *num_formats = ARRAY_SIZE(icl_sdr_y_plane_formats); 2399 return icl_sdr_y_plane_formats; 2400 } else { 2401 *num_formats = ARRAY_SIZE(icl_sdr_uv_plane_formats); 2402 return icl_sdr_uv_plane_formats; 2403 } 2404 } 2405 2406 static bool skl_plane_format_mod_supported(struct drm_plane *_plane, 2407 u32 format, u64 modifier) 2408 { 2409 struct intel_plane *plane = to_intel_plane(_plane); 2410 2411 if (!intel_fb_plane_supports_modifier(plane, modifier)) 2412 return false; 2413 2414 switch (format) { 2415 case DRM_FORMAT_XRGB8888: 2416 case DRM_FORMAT_XBGR8888: 2417 case DRM_FORMAT_ARGB8888: 2418 case DRM_FORMAT_ABGR8888: 2419 if (intel_fb_is_ccs_modifier(modifier)) 2420 return true; 2421 fallthrough; 2422 case DRM_FORMAT_RGB565: 2423 case DRM_FORMAT_XRGB2101010: 2424 case DRM_FORMAT_XBGR2101010: 2425 case DRM_FORMAT_ARGB2101010: 2426 case DRM_FORMAT_ABGR2101010: 2427 case DRM_FORMAT_YUYV: 2428 case DRM_FORMAT_YVYU: 2429 case DRM_FORMAT_UYVY: 2430 case DRM_FORMAT_VYUY: 2431 case DRM_FORMAT_NV12: 2432 case DRM_FORMAT_XYUV8888: 2433 case DRM_FORMAT_P010: 2434 case DRM_FORMAT_P012: 2435 case DRM_FORMAT_P016: 2436 case DRM_FORMAT_XVYU2101010: 2437 if (modifier == I915_FORMAT_MOD_Yf_TILED) 2438 return true; 2439 fallthrough; 2440 case DRM_FORMAT_C8: 2441 case DRM_FORMAT_XBGR16161616F: 2442 case DRM_FORMAT_ABGR16161616F: 2443 case DRM_FORMAT_XRGB16161616F: 2444 case DRM_FORMAT_ARGB16161616F: 2445 case DRM_FORMAT_Y210: 2446 case DRM_FORMAT_Y212: 2447 case DRM_FORMAT_Y216: 2448 case DRM_FORMAT_XVYU12_16161616: 2449 case DRM_FORMAT_XVYU16161616: 2450 if (modifier == DRM_FORMAT_MOD_LINEAR || 2451 modifier == I915_FORMAT_MOD_X_TILED || 2452 modifier == I915_FORMAT_MOD_Y_TILED) 2453 return true; 2454 fallthrough; 2455 default: 2456 return false; 2457 } 2458 } 2459 2460 static bool icl_plane_format_mod_supported(struct drm_plane *_plane, 2461 u32 format, u64 modifier) 2462 { 2463 struct intel_plane *plane = to_intel_plane(_plane); 2464 2465 if (!intel_fb_plane_supports_modifier(plane, modifier)) 2466 return false; 2467 2468 switch (format) { 2469 case DRM_FORMAT_XRGB8888: 2470 case DRM_FORMAT_XBGR8888: 2471 case DRM_FORMAT_ARGB8888: 2472 case DRM_FORMAT_ABGR8888: 2473 case DRM_FORMAT_XRGB2101010: 2474 case DRM_FORMAT_XBGR2101010: 2475 case DRM_FORMAT_ARGB2101010: 2476 case DRM_FORMAT_ABGR2101010: 2477 if (intel_fb_is_ccs_modifier(modifier)) 2478 return true; 2479 fallthrough; 2480 case DRM_FORMAT_RGB565: 2481 case DRM_FORMAT_YUYV: 2482 case DRM_FORMAT_YVYU: 2483 case DRM_FORMAT_UYVY: 2484 case DRM_FORMAT_VYUY: 2485 case DRM_FORMAT_NV12: 2486 case DRM_FORMAT_XYUV8888: 2487 case DRM_FORMAT_P010: 2488 case DRM_FORMAT_P012: 2489 case DRM_FORMAT_P016: 2490 case DRM_FORMAT_XVYU2101010: 2491 if (modifier == I915_FORMAT_MOD_Yf_TILED) 2492 return true; 2493 fallthrough; 2494 case DRM_FORMAT_C8: 2495 case DRM_FORMAT_XBGR16161616F: 2496 case DRM_FORMAT_ABGR16161616F: 2497 case DRM_FORMAT_XRGB16161616F: 2498 case DRM_FORMAT_ARGB16161616F: 2499 case DRM_FORMAT_Y210: 2500 case DRM_FORMAT_Y212: 2501 case DRM_FORMAT_Y216: 2502 case DRM_FORMAT_XVYU12_16161616: 2503 case DRM_FORMAT_XVYU16161616: 2504 if (modifier == DRM_FORMAT_MOD_LINEAR || 2505 modifier == I915_FORMAT_MOD_X_TILED || 2506 modifier == I915_FORMAT_MOD_Y_TILED) 2507 return true; 2508 fallthrough; 2509 default: 2510 return false; 2511 } 2512 } 2513 2514 static bool tgl_plane_format_mod_supported(struct drm_plane *_plane, 2515 u32 format, u64 modifier) 2516 { 2517 struct intel_plane *plane = to_intel_plane(_plane); 2518 2519 if (!intel_fb_plane_supports_modifier(plane, modifier)) 2520 return false; 2521 2522 switch (format) { 2523 case DRM_FORMAT_XRGB8888: 2524 case DRM_FORMAT_XBGR8888: 2525 case DRM_FORMAT_ARGB8888: 2526 case DRM_FORMAT_ABGR8888: 2527 case DRM_FORMAT_XRGB2101010: 2528 case DRM_FORMAT_XBGR2101010: 2529 case DRM_FORMAT_ARGB2101010: 2530 case DRM_FORMAT_ABGR2101010: 2531 case DRM_FORMAT_XBGR16161616F: 2532 case DRM_FORMAT_ABGR16161616F: 2533 case DRM_FORMAT_XRGB16161616F: 2534 case DRM_FORMAT_ARGB16161616F: 2535 if (intel_fb_is_ccs_modifier(modifier)) 2536 return true; 2537 fallthrough; 2538 case DRM_FORMAT_YUYV: 2539 case DRM_FORMAT_YVYU: 2540 case DRM_FORMAT_UYVY: 2541 case DRM_FORMAT_VYUY: 2542 case DRM_FORMAT_NV12: 2543 case DRM_FORMAT_XYUV8888: 2544 case DRM_FORMAT_P010: 2545 case DRM_FORMAT_P012: 2546 case DRM_FORMAT_P016: 2547 if (intel_fb_is_mc_ccs_modifier(modifier)) 2548 return true; 2549 fallthrough; 2550 case DRM_FORMAT_RGB565: 2551 case DRM_FORMAT_XVYU2101010: 2552 case DRM_FORMAT_C8: 2553 case DRM_FORMAT_Y210: 2554 case DRM_FORMAT_Y212: 2555 case DRM_FORMAT_Y216: 2556 case DRM_FORMAT_XVYU12_16161616: 2557 case DRM_FORMAT_XVYU16161616: 2558 if (!intel_fb_is_ccs_modifier(modifier)) 2559 return true; 2560 fallthrough; 2561 default: 2562 return false; 2563 } 2564 } 2565 2566 static const struct drm_plane_funcs skl_plane_funcs = { 2567 .update_plane = drm_atomic_helper_update_plane, 2568 .disable_plane = drm_atomic_helper_disable_plane, 2569 .destroy = intel_plane_destroy, 2570 .atomic_duplicate_state = intel_plane_duplicate_state, 2571 .atomic_destroy_state = intel_plane_destroy_state, 2572 .format_mod_supported = skl_plane_format_mod_supported, 2573 }; 2574 2575 static const struct drm_plane_funcs icl_plane_funcs = { 2576 .update_plane = drm_atomic_helper_update_plane, 2577 .disable_plane = drm_atomic_helper_disable_plane, 2578 .destroy = intel_plane_destroy, 2579 .atomic_duplicate_state = intel_plane_duplicate_state, 2580 .atomic_destroy_state = intel_plane_destroy_state, 2581 .format_mod_supported = icl_plane_format_mod_supported, 2582 }; 2583 2584 static const struct drm_plane_funcs tgl_plane_funcs = { 2585 .update_plane = drm_atomic_helper_update_plane, 2586 .disable_plane = drm_atomic_helper_disable_plane, 2587 .destroy = intel_plane_destroy, 2588 .atomic_duplicate_state = intel_plane_duplicate_state, 2589 .atomic_destroy_state = intel_plane_destroy_state, 2590 .format_mod_supported = tgl_plane_format_mod_supported, 2591 }; 2592 2593 static void 2594 skl_plane_enable_flip_done(struct intel_plane *plane) 2595 { 2596 struct drm_i915_private *i915 = to_i915(plane->base.dev); 2597 enum pipe pipe = plane->pipe; 2598 2599 spin_lock_irq(&i915->irq_lock); 2600 bdw_enable_pipe_irq(i915, pipe, GEN9_PIPE_PLANE_FLIP_DONE(plane->id)); 2601 spin_unlock_irq(&i915->irq_lock); 2602 } 2603 2604 static void 2605 skl_plane_disable_flip_done(struct intel_plane *plane) 2606 { 2607 struct drm_i915_private *i915 = to_i915(plane->base.dev); 2608 enum pipe pipe = plane->pipe; 2609 2610 spin_lock_irq(&i915->irq_lock); 2611 bdw_disable_pipe_irq(i915, pipe, GEN9_PIPE_PLANE_FLIP_DONE(plane->id)); 2612 spin_unlock_irq(&i915->irq_lock); 2613 } 2614 2615 static bool skl_plane_has_rc_ccs(struct drm_i915_private *i915, 2616 enum pipe pipe, enum plane_id plane_id) 2617 { 2618 return pipe != PIPE_C && 2619 (plane_id == PLANE_1 || plane_id == PLANE_2); 2620 } 2621 2622 static u8 skl_plane_caps(struct drm_i915_private *i915, 2623 enum pipe pipe, enum plane_id plane_id) 2624 { 2625 u8 caps = INTEL_PLANE_CAP_TILING_X | 2626 INTEL_PLANE_CAP_TILING_Y | 2627 INTEL_PLANE_CAP_TILING_Yf; 2628 2629 if (skl_plane_has_rc_ccs(i915, pipe, plane_id)) 2630 caps |= INTEL_PLANE_CAP_CCS_RC; 2631 2632 return caps; 2633 } 2634 2635 static bool glk_plane_has_rc_ccs(struct drm_i915_private *i915, 2636 enum pipe pipe) 2637 { 2638 return pipe != PIPE_C; 2639 } 2640 2641 static u8 glk_plane_caps(struct drm_i915_private *i915, 2642 enum pipe pipe, enum plane_id plane_id) 2643 { 2644 u8 caps = INTEL_PLANE_CAP_TILING_X | 2645 INTEL_PLANE_CAP_TILING_Y | 2646 INTEL_PLANE_CAP_TILING_Yf; 2647 2648 if (glk_plane_has_rc_ccs(i915, pipe)) 2649 caps |= INTEL_PLANE_CAP_CCS_RC; 2650 2651 return caps; 2652 } 2653 2654 static u8 icl_plane_caps(struct drm_i915_private *i915, 2655 enum pipe pipe, enum plane_id plane_id) 2656 { 2657 return INTEL_PLANE_CAP_TILING_X | 2658 INTEL_PLANE_CAP_TILING_Y | 2659 INTEL_PLANE_CAP_TILING_Yf | 2660 INTEL_PLANE_CAP_CCS_RC; 2661 } 2662 2663 static bool tgl_plane_has_mc_ccs(struct drm_i915_private *i915, 2664 enum plane_id plane_id) 2665 { 2666 /* Wa_14010477008 */ 2667 if (IS_DG1(i915) || IS_ROCKETLAKE(i915) || 2668 (IS_TIGERLAKE(i915) && IS_DISPLAY_STEP(i915, STEP_A0, STEP_D0))) 2669 return false; 2670 2671 return plane_id < PLANE_6; 2672 } 2673 2674 static u8 tgl_plane_caps(struct drm_i915_private *i915, 2675 enum pipe pipe, enum plane_id plane_id) 2676 { 2677 struct intel_display *display = &i915->display; 2678 u8 caps = INTEL_PLANE_CAP_TILING_X | 2679 INTEL_PLANE_CAP_CCS_RC | 2680 INTEL_PLANE_CAP_CCS_RC_CC; 2681 2682 if (HAS_4TILE(display)) 2683 caps |= INTEL_PLANE_CAP_TILING_4; 2684 else 2685 caps |= INTEL_PLANE_CAP_TILING_Y; 2686 2687 if (tgl_plane_has_mc_ccs(i915, plane_id)) 2688 caps |= INTEL_PLANE_CAP_CCS_MC; 2689 2690 if (DISPLAY_VER(display) >= 14 && display->platform.dgfx) 2691 caps |= INTEL_PLANE_CAP_NEED64K_PHYS; 2692 2693 return caps; 2694 } 2695 2696 struct intel_plane * 2697 skl_universal_plane_create(struct drm_i915_private *dev_priv, 2698 enum pipe pipe, enum plane_id plane_id) 2699 { 2700 const struct drm_plane_funcs *plane_funcs; 2701 struct intel_plane *plane; 2702 enum drm_plane_type plane_type; 2703 unsigned int supported_rotations; 2704 unsigned int supported_csc; 2705 const u64 *modifiers; 2706 const u32 *formats; 2707 int num_formats; 2708 int ret; 2709 u8 caps; 2710 2711 plane = intel_plane_alloc(); 2712 if (IS_ERR(plane)) 2713 return plane; 2714 2715 plane->pipe = pipe; 2716 plane->id = plane_id; 2717 plane->frontbuffer_bit = INTEL_FRONTBUFFER(pipe, plane_id); 2718 2719 intel_fbc_add_plane(skl_plane_fbc(dev_priv, pipe, plane_id), plane); 2720 2721 if (DISPLAY_VER(dev_priv) >= 30) { 2722 plane->max_width = xe3_plane_max_width; 2723 plane->max_height = icl_plane_max_height; 2724 plane->min_cdclk = icl_plane_min_cdclk; 2725 } else if (DISPLAY_VER(dev_priv) >= 11) { 2726 plane->min_width = icl_plane_min_width; 2727 if (icl_is_hdr_plane(dev_priv, plane_id)) 2728 plane->max_width = icl_hdr_plane_max_width; 2729 else 2730 plane->max_width = icl_sdr_plane_max_width; 2731 plane->max_height = icl_plane_max_height; 2732 plane->min_cdclk = icl_plane_min_cdclk; 2733 } else if (DISPLAY_VER(dev_priv) >= 10) { 2734 plane->max_width = glk_plane_max_width; 2735 plane->max_height = skl_plane_max_height; 2736 plane->min_cdclk = glk_plane_min_cdclk; 2737 } else { 2738 plane->max_width = skl_plane_max_width; 2739 plane->max_height = skl_plane_max_height; 2740 plane->min_cdclk = skl_plane_min_cdclk; 2741 } 2742 2743 if (DISPLAY_VER(dev_priv) >= 13) 2744 plane->max_stride = adl_plane_max_stride; 2745 else 2746 plane->max_stride = skl_plane_max_stride; 2747 2748 if (DISPLAY_VER(dev_priv) >= 12) 2749 plane->min_alignment = tgl_plane_min_alignment; 2750 else 2751 plane->min_alignment = skl_plane_min_alignment; 2752 2753 if (DISPLAY_VER(dev_priv) >= 11) { 2754 plane->update_noarm = icl_plane_update_noarm; 2755 plane->update_arm = icl_plane_update_arm; 2756 plane->disable_arm = icl_plane_disable_arm; 2757 } else { 2758 plane->update_noarm = skl_plane_update_noarm; 2759 plane->update_arm = skl_plane_update_arm; 2760 plane->disable_arm = skl_plane_disable_arm; 2761 } 2762 plane->get_hw_state = skl_plane_get_hw_state; 2763 plane->check_plane = skl_plane_check; 2764 2765 if (HAS_ASYNC_FLIPS(dev_priv) && plane_id == PLANE_1) { 2766 plane->need_async_flip_toggle_wa = IS_DISPLAY_VER(dev_priv, 9, 10); 2767 plane->async_flip = skl_plane_async_flip; 2768 plane->enable_flip_done = skl_plane_enable_flip_done; 2769 plane->disable_flip_done = skl_plane_disable_flip_done; 2770 2771 if (DISPLAY_VER(dev_priv) >= 12) 2772 plane->can_async_flip = tgl_plane_can_async_flip; 2773 else if (DISPLAY_VER(dev_priv) == 11) 2774 plane->can_async_flip = icl_plane_can_async_flip; 2775 else 2776 plane->can_async_flip = skl_plane_can_async_flip; 2777 } 2778 2779 if (DISPLAY_VER(dev_priv) >= 11) 2780 formats = icl_get_plane_formats(dev_priv, pipe, 2781 plane_id, &num_formats); 2782 else if (DISPLAY_VER(dev_priv) >= 10) 2783 formats = glk_get_plane_formats(dev_priv, pipe, 2784 plane_id, &num_formats); 2785 else 2786 formats = skl_get_plane_formats(dev_priv, pipe, 2787 plane_id, &num_formats); 2788 2789 if (DISPLAY_VER(dev_priv) >= 12) 2790 plane_funcs = &tgl_plane_funcs; 2791 else if (DISPLAY_VER(dev_priv) == 11) 2792 plane_funcs = &icl_plane_funcs; 2793 else 2794 plane_funcs = &skl_plane_funcs; 2795 2796 if (plane_id == PLANE_1) 2797 plane_type = DRM_PLANE_TYPE_PRIMARY; 2798 else 2799 plane_type = DRM_PLANE_TYPE_OVERLAY; 2800 2801 if (DISPLAY_VER(dev_priv) >= 12) 2802 caps = tgl_plane_caps(dev_priv, pipe, plane_id); 2803 else if (DISPLAY_VER(dev_priv) == 11) 2804 caps = icl_plane_caps(dev_priv, pipe, plane_id); 2805 else if (DISPLAY_VER(dev_priv) == 10) 2806 caps = glk_plane_caps(dev_priv, pipe, plane_id); 2807 else 2808 caps = skl_plane_caps(dev_priv, pipe, plane_id); 2809 2810 /* FIXME: xe has problems with AUX */ 2811 if (!IS_ENABLED(I915) && !HAS_FLAT_CCS(dev_priv)) 2812 caps &= ~(INTEL_PLANE_CAP_CCS_RC | 2813 INTEL_PLANE_CAP_CCS_RC_CC | 2814 INTEL_PLANE_CAP_CCS_MC); 2815 2816 modifiers = intel_fb_plane_get_modifiers(dev_priv, caps); 2817 2818 ret = drm_universal_plane_init(&dev_priv->drm, &plane->base, 2819 0, plane_funcs, 2820 formats, num_formats, modifiers, 2821 plane_type, 2822 "plane %d%c", plane_id + 1, 2823 pipe_name(pipe)); 2824 2825 kfree(modifiers); 2826 2827 if (ret) 2828 goto fail; 2829 2830 if (DISPLAY_VER(dev_priv) >= 13) 2831 supported_rotations = DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180; 2832 else 2833 supported_rotations = 2834 DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_90 | 2835 DRM_MODE_ROTATE_180 | DRM_MODE_ROTATE_270; 2836 2837 if (DISPLAY_VER(dev_priv) >= 11) 2838 supported_rotations |= DRM_MODE_REFLECT_X; 2839 2840 drm_plane_create_rotation_property(&plane->base, 2841 DRM_MODE_ROTATE_0, 2842 supported_rotations); 2843 2844 supported_csc = BIT(DRM_COLOR_YCBCR_BT601) | BIT(DRM_COLOR_YCBCR_BT709); 2845 2846 if (DISPLAY_VER(dev_priv) >= 10) 2847 supported_csc |= BIT(DRM_COLOR_YCBCR_BT2020); 2848 2849 drm_plane_create_color_properties(&plane->base, 2850 supported_csc, 2851 BIT(DRM_COLOR_YCBCR_LIMITED_RANGE) | 2852 BIT(DRM_COLOR_YCBCR_FULL_RANGE), 2853 DRM_COLOR_YCBCR_BT709, 2854 DRM_COLOR_YCBCR_LIMITED_RANGE); 2855 2856 drm_plane_create_alpha_property(&plane->base); 2857 drm_plane_create_blend_mode_property(&plane->base, 2858 BIT(DRM_MODE_BLEND_PIXEL_NONE) | 2859 BIT(DRM_MODE_BLEND_PREMULTI) | 2860 BIT(DRM_MODE_BLEND_COVERAGE)); 2861 2862 drm_plane_create_zpos_immutable_property(&plane->base, plane_id); 2863 2864 if (DISPLAY_VER(dev_priv) >= 12) 2865 drm_plane_enable_fb_damage_clips(&plane->base); 2866 2867 if (DISPLAY_VER(dev_priv) >= 11) 2868 drm_plane_create_scaling_filter_property(&plane->base, 2869 BIT(DRM_SCALING_FILTER_DEFAULT) | 2870 BIT(DRM_SCALING_FILTER_NEAREST_NEIGHBOR)); 2871 2872 intel_plane_helper_add(plane); 2873 2874 return plane; 2875 2876 fail: 2877 intel_plane_free(plane); 2878 2879 return ERR_PTR(ret); 2880 } 2881 2882 void 2883 skl_get_initial_plane_config(struct intel_crtc *crtc, 2884 struct intel_initial_plane_config *plane_config) 2885 { 2886 struct intel_display *display = to_intel_display(crtc); 2887 struct intel_crtc_state *crtc_state = to_intel_crtc_state(crtc->base.state); 2888 struct drm_device *dev = crtc->base.dev; 2889 struct drm_i915_private *dev_priv = to_i915(dev); 2890 struct intel_plane *plane = to_intel_plane(crtc->base.primary); 2891 enum plane_id plane_id = plane->id; 2892 enum pipe pipe; 2893 u32 val, base, offset, stride_mult, tiling, alpha; 2894 int fourcc, pixel_format; 2895 unsigned int aligned_height; 2896 struct drm_framebuffer *fb; 2897 struct intel_framebuffer *intel_fb; 2898 static_assert(PLANE_CTL_TILED_YF == PLANE_CTL_TILED_4); 2899 2900 if (!plane->get_hw_state(plane, &pipe)) 2901 return; 2902 2903 drm_WARN_ON(dev, pipe != crtc->pipe); 2904 2905 if (crtc_state->joiner_pipes) { 2906 drm_dbg_kms(&dev_priv->drm, 2907 "Unsupported joiner configuration for initial FB\n"); 2908 return; 2909 } 2910 2911 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); 2912 if (!intel_fb) { 2913 drm_dbg_kms(&dev_priv->drm, "failed to alloc fb\n"); 2914 return; 2915 } 2916 2917 fb = &intel_fb->base; 2918 2919 fb->dev = dev; 2920 2921 val = intel_de_read(dev_priv, PLANE_CTL(pipe, plane_id)); 2922 2923 if (DISPLAY_VER(dev_priv) >= 11) 2924 pixel_format = val & PLANE_CTL_FORMAT_MASK_ICL; 2925 else 2926 pixel_format = val & PLANE_CTL_FORMAT_MASK_SKL; 2927 2928 if (DISPLAY_VER(dev_priv) >= 10) { 2929 u32 color_ctl; 2930 2931 color_ctl = intel_de_read(dev_priv, PLANE_COLOR_CTL(pipe, plane_id)); 2932 alpha = REG_FIELD_GET(PLANE_COLOR_ALPHA_MASK, color_ctl); 2933 } else { 2934 alpha = REG_FIELD_GET(PLANE_CTL_ALPHA_MASK, val); 2935 } 2936 2937 fourcc = skl_format_to_fourcc(pixel_format, 2938 val & PLANE_CTL_ORDER_RGBX, alpha); 2939 fb->format = drm_format_info(fourcc); 2940 2941 tiling = val & PLANE_CTL_TILED_MASK; 2942 switch (tiling) { 2943 case PLANE_CTL_TILED_LINEAR: 2944 fb->modifier = DRM_FORMAT_MOD_LINEAR; 2945 break; 2946 case PLANE_CTL_TILED_X: 2947 plane_config->tiling = I915_TILING_X; 2948 fb->modifier = I915_FORMAT_MOD_X_TILED; 2949 break; 2950 case PLANE_CTL_TILED_Y: 2951 plane_config->tiling = I915_TILING_Y; 2952 if (val & PLANE_CTL_RENDER_DECOMPRESSION_ENABLE) 2953 if (DISPLAY_VER(dev_priv) >= 14) 2954 fb->modifier = I915_FORMAT_MOD_4_TILED_MTL_RC_CCS; 2955 else if (DISPLAY_VER(dev_priv) >= 12) 2956 fb->modifier = I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS; 2957 else 2958 fb->modifier = I915_FORMAT_MOD_Y_TILED_CCS; 2959 else if (val & PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE) 2960 if (DISPLAY_VER(dev_priv) >= 14) 2961 fb->modifier = I915_FORMAT_MOD_4_TILED_MTL_MC_CCS; 2962 else 2963 fb->modifier = I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS; 2964 else 2965 fb->modifier = I915_FORMAT_MOD_Y_TILED; 2966 break; 2967 case PLANE_CTL_TILED_YF: /* aka PLANE_CTL_TILED_4 on XE_LPD+ */ 2968 if (HAS_4TILE(display)) { 2969 u32 rc_mask = PLANE_CTL_RENDER_DECOMPRESSION_ENABLE | 2970 PLANE_CTL_CLEAR_COLOR_DISABLE; 2971 2972 if ((val & rc_mask) == rc_mask) 2973 fb->modifier = I915_FORMAT_MOD_4_TILED_DG2_RC_CCS; 2974 else if (val & PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE) 2975 fb->modifier = I915_FORMAT_MOD_4_TILED_DG2_MC_CCS; 2976 else if (val & PLANE_CTL_RENDER_DECOMPRESSION_ENABLE) 2977 fb->modifier = I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC; 2978 else 2979 fb->modifier = I915_FORMAT_MOD_4_TILED; 2980 } else { 2981 if (val & PLANE_CTL_RENDER_DECOMPRESSION_ENABLE) 2982 fb->modifier = I915_FORMAT_MOD_Yf_TILED_CCS; 2983 else 2984 fb->modifier = I915_FORMAT_MOD_Yf_TILED; 2985 } 2986 break; 2987 default: 2988 MISSING_CASE(tiling); 2989 goto error; 2990 } 2991 2992 if (!dev_priv->display.params.enable_dpt && 2993 intel_fb_modifier_uses_dpt(dev_priv, fb->modifier)) { 2994 drm_dbg_kms(&dev_priv->drm, "DPT disabled, skipping initial FB\n"); 2995 goto error; 2996 } 2997 2998 /* 2999 * DRM_MODE_ROTATE_ is counter clockwise to stay compatible with Xrandr 3000 * while i915 HW rotation is clockwise, thats why this swapping. 3001 */ 3002 switch (val & PLANE_CTL_ROTATE_MASK) { 3003 case PLANE_CTL_ROTATE_0: 3004 plane_config->rotation = DRM_MODE_ROTATE_0; 3005 break; 3006 case PLANE_CTL_ROTATE_90: 3007 plane_config->rotation = DRM_MODE_ROTATE_270; 3008 break; 3009 case PLANE_CTL_ROTATE_180: 3010 plane_config->rotation = DRM_MODE_ROTATE_180; 3011 break; 3012 case PLANE_CTL_ROTATE_270: 3013 plane_config->rotation = DRM_MODE_ROTATE_90; 3014 break; 3015 } 3016 3017 if (DISPLAY_VER(dev_priv) >= 11 && val & PLANE_CTL_FLIP_HORIZONTAL) 3018 plane_config->rotation |= DRM_MODE_REFLECT_X; 3019 3020 /* 90/270 degree rotation would require extra work */ 3021 if (drm_rotation_90_or_270(plane_config->rotation)) 3022 goto error; 3023 3024 base = intel_de_read(dev_priv, PLANE_SURF(pipe, plane_id)) & PLANE_SURF_ADDR_MASK; 3025 plane_config->base = base; 3026 3027 offset = intel_de_read(dev_priv, PLANE_OFFSET(pipe, plane_id)); 3028 drm_WARN_ON(&dev_priv->drm, offset != 0); 3029 3030 val = intel_de_read(dev_priv, PLANE_SIZE(pipe, plane_id)); 3031 fb->height = REG_FIELD_GET(PLANE_HEIGHT_MASK, val) + 1; 3032 fb->width = REG_FIELD_GET(PLANE_WIDTH_MASK, val) + 1; 3033 3034 val = intel_de_read(dev_priv, PLANE_STRIDE(pipe, plane_id)); 3035 stride_mult = skl_plane_stride_mult(fb, 0, DRM_MODE_ROTATE_0); 3036 3037 fb->pitches[0] = REG_FIELD_GET(PLANE_STRIDE__MASK, val) * stride_mult; 3038 3039 aligned_height = intel_fb_align_height(fb, 0, fb->height); 3040 3041 plane_config->size = fb->pitches[0] * aligned_height; 3042 3043 drm_dbg_kms(&dev_priv->drm, 3044 "%s/%s with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", 3045 crtc->base.name, plane->base.name, fb->width, fb->height, 3046 fb->format->cpp[0] * 8, base, fb->pitches[0], 3047 plane_config->size); 3048 3049 plane_config->fb = intel_fb; 3050 return; 3051 3052 error: 3053 kfree(intel_fb); 3054 } 3055 3056 bool skl_fixup_initial_plane_config(struct intel_crtc *crtc, 3057 const struct intel_initial_plane_config *plane_config) 3058 { 3059 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 3060 struct intel_plane *plane = to_intel_plane(crtc->base.primary); 3061 const struct intel_plane_state *plane_state = 3062 to_intel_plane_state(plane->base.state); 3063 enum plane_id plane_id = plane->id; 3064 enum pipe pipe = crtc->pipe; 3065 u32 base; 3066 3067 if (!plane_state->uapi.visible) 3068 return false; 3069 3070 base = intel_plane_ggtt_offset(plane_state); 3071 3072 /* 3073 * We may have moved the surface to a different 3074 * part of ggtt, make the plane aware of that. 3075 */ 3076 if (plane_config->base == base) 3077 return false; 3078 3079 intel_de_write(i915, PLANE_SURF(pipe, plane_id), base); 3080 3081 return true; 3082 } 3083