1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2020 Intel Corporation 4 */ 5 6 #include "i915_drv.h" 7 #include "i915_reg.h" 8 #include "intel_de.h" 9 #include "intel_display_trace.h" 10 #include "intel_display_types.h" 11 #include "intel_fb.h" 12 #include "skl_scaler.h" 13 #include "skl_universal_plane.h" 14 15 /* 16 * The hardware phase 0.0 refers to the center of the pixel. 17 * We want to start from the top/left edge which is phase 18 * -0.5. That matches how the hardware calculates the scaling 19 * factors (from top-left of the first pixel to bottom-right 20 * of the last pixel, as opposed to the pixel centers). 21 * 22 * For 4:2:0 subsampled chroma planes we obviously have to 23 * adjust that so that the chroma sample position lands in 24 * the right spot. 25 * 26 * Note that for packed YCbCr 4:2:2 formats there is no way to 27 * control chroma siting. The hardware simply replicates the 28 * chroma samples for both of the luma samples, and thus we don't 29 * actually get the expected MPEG2 chroma siting convention :( 30 * The same behaviour is observed on pre-SKL platforms as well. 31 * 32 * Theory behind the formula (note that we ignore sub-pixel 33 * source coordinates): 34 * s = source sample position 35 * d = destination sample position 36 * 37 * Downscaling 4:1: 38 * -0.5 39 * | 0.0 40 * | | 1.5 (initial phase) 41 * | | | 42 * v v v 43 * | s | s | s | s | 44 * | d | 45 * 46 * Upscaling 1:4: 47 * -0.5 48 * | -0.375 (initial phase) 49 * | | 0.0 50 * | | | 51 * v v v 52 * | s | 53 * | d | d | d | d | 54 */ 55 static u16 skl_scaler_calc_phase(int sub, int scale, bool chroma_cosited) 56 { 57 int phase = -0x8000; 58 u16 trip = 0; 59 60 if (chroma_cosited) 61 phase += (sub - 1) * 0x8000 / sub; 62 63 phase += scale / (2 * sub); 64 65 /* 66 * Hardware initial phase limited to [-0.5:1.5]. 67 * Since the max hardware scale factor is 3.0, we 68 * should never actually exceed 1.0 here. 69 */ 70 WARN_ON(phase < -0x8000 || phase > 0x18000); 71 72 if (phase < 0) 73 phase = 0x10000 + phase; 74 else 75 trip = PS_PHASE_TRIP; 76 77 return ((phase >> 2) & PS_PHASE_MASK) | trip; 78 } 79 80 static void skl_scaler_min_src_size(const struct drm_format_info *format, 81 u64 modifier, int *min_w, int *min_h) 82 { 83 if (format && intel_format_info_is_yuv_semiplanar(format, modifier)) { 84 *min_w = 16; 85 *min_h = 16; 86 } else { 87 *min_w = 8; 88 *min_h = 8; 89 } 90 } 91 92 static void skl_scaler_max_src_size(struct intel_crtc *crtc, 93 int *max_w, int *max_h) 94 { 95 struct intel_display *display = to_intel_display(crtc); 96 97 if (DISPLAY_VER(display) >= 14) { 98 *max_w = 4096; 99 *max_h = 8192; 100 } else if (DISPLAY_VER(display) >= 12) { 101 *max_w = 5120; 102 *max_h = 8192; 103 } else if (DISPLAY_VER(display) == 11) { 104 *max_w = 5120; 105 *max_h = 4096; 106 } else { 107 *max_w = 4096; 108 *max_h = 4096; 109 } 110 } 111 112 static void skl_scaler_min_dst_size(int *min_w, int *min_h) 113 { 114 *min_w = 8; 115 *min_h = 8; 116 } 117 118 static void skl_scaler_max_dst_size(struct intel_crtc *crtc, 119 int *max_w, int *max_h) 120 { 121 struct intel_display *display = to_intel_display(crtc); 122 123 if (DISPLAY_VER(display) >= 12) { 124 *max_w = 8192; 125 *max_h = 8192; 126 } else if (DISPLAY_VER(display) == 11) { 127 *max_w = 5120; 128 *max_h = 4096; 129 } else { 130 *max_w = 4096; 131 *max_h = 4096; 132 } 133 } 134 135 static int 136 skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach, 137 unsigned int scaler_user, int *scaler_id, 138 int src_w, int src_h, int dst_w, int dst_h, 139 const struct drm_format_info *format, 140 u64 modifier, bool need_scaler) 141 { 142 struct intel_display *display = to_intel_display(crtc_state); 143 struct intel_crtc_scaler_state *scaler_state = 144 &crtc_state->scaler_state; 145 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 146 const struct drm_display_mode *adjusted_mode = 147 &crtc_state->hw.adjusted_mode; 148 int pipe_src_w = drm_rect_width(&crtc_state->pipe_src); 149 int pipe_src_h = drm_rect_height(&crtc_state->pipe_src); 150 int min_src_w, min_src_h, min_dst_w, min_dst_h; 151 int max_src_w, max_src_h, max_dst_w, max_dst_h; 152 153 /* 154 * Src coordinates are already rotated by 270 degrees for 155 * the 90/270 degree plane rotation cases (to match the 156 * GTT mapping), hence no need to account for rotation here. 157 */ 158 if (src_w != dst_w || src_h != dst_h) 159 need_scaler = true; 160 161 /* 162 * Scaling/fitting not supported in IF-ID mode in GEN9+ 163 * TODO: Interlace fetch mode doesn't support YUV420 planar formats. 164 * Once NV12 is enabled, handle it here while allocating scaler 165 * for NV12. 166 */ 167 if (DISPLAY_VER(display) >= 9 && crtc_state->hw.enable && 168 need_scaler && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { 169 drm_dbg_kms(display->drm, 170 "[CRTC:%d:%s] scaling not supported with IF-ID mode\n", 171 crtc->base.base.id, crtc->base.name); 172 return -EINVAL; 173 } 174 175 /* 176 * if plane is being disabled or scaler is no more required or force detach 177 * - free scaler binded to this plane/crtc 178 * - in order to do this, update crtc->scaler_usage 179 * 180 * Here scaler state in crtc_state is set free so that 181 * scaler can be assigned to other user. Actual register 182 * update to free the scaler is done in plane/panel-fit programming. 183 * For this purpose crtc/plane_state->scaler_id isn't reset here. 184 */ 185 if (force_detach || !need_scaler) { 186 if (*scaler_id >= 0) { 187 scaler_state->scaler_users &= ~(1 << scaler_user); 188 scaler_state->scalers[*scaler_id].in_use = false; 189 190 drm_dbg_kms(display->drm, 191 "[CRTC:%d:%s] scaler_user index %u.%u: " 192 "Staged freeing scaler id %d scaler_users = 0x%x\n", 193 crtc->base.base.id, crtc->base.name, 194 crtc->pipe, scaler_user, *scaler_id, 195 scaler_state->scaler_users); 196 *scaler_id = -1; 197 } 198 return 0; 199 } 200 201 skl_scaler_min_src_size(format, modifier, &min_src_w, &min_src_h); 202 skl_scaler_max_src_size(crtc, &max_src_w, &max_src_h); 203 204 skl_scaler_min_dst_size(&min_dst_w, &min_dst_h); 205 skl_scaler_max_dst_size(crtc, &max_dst_w, &max_dst_h); 206 207 /* range checks */ 208 if (src_w < min_src_w || src_h < min_src_h || 209 dst_w < min_dst_w || dst_h < min_dst_h || 210 src_w > max_src_w || src_h > max_src_h || 211 dst_w > max_dst_w || dst_h > max_dst_h) { 212 drm_dbg_kms(display->drm, 213 "[CRTC:%d:%s] scaler_user index %u.%u: src %ux%u dst %ux%u " 214 "size is out of scaler range\n", 215 crtc->base.base.id, crtc->base.name, 216 crtc->pipe, scaler_user, src_w, src_h, 217 dst_w, dst_h); 218 return -EINVAL; 219 } 220 221 /* 222 * The pipe scaler does not use all the bits of PIPESRC, at least 223 * on the earlier platforms. So even when we're scaling a plane 224 * the *pipe* source size must not be too large. For simplicity 225 * we assume the limits match the scaler destination size limits. 226 * Might not be 100% accurate on all platforms, but good enough for 227 * now. 228 */ 229 if (pipe_src_w > max_dst_w || pipe_src_h > max_dst_h) { 230 drm_dbg_kms(display->drm, 231 "[CRTC:%d:%s] scaler_user index %u.%u: pipe src size %ux%u " 232 "is out of scaler range\n", 233 crtc->base.base.id, crtc->base.name, 234 crtc->pipe, scaler_user, pipe_src_w, pipe_src_h); 235 return -EINVAL; 236 } 237 238 /* mark this plane as a scaler user in crtc_state */ 239 scaler_state->scaler_users |= (1 << scaler_user); 240 drm_dbg_kms(display->drm, "[CRTC:%d:%s] scaler_user index %u.%u: " 241 "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n", 242 crtc->base.base.id, crtc->base.name, 243 crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h, 244 scaler_state->scaler_users); 245 246 return 0; 247 } 248 249 int skl_update_scaler_crtc(struct intel_crtc_state *crtc_state) 250 { 251 const struct drm_display_mode *pipe_mode = &crtc_state->hw.pipe_mode; 252 int width, height; 253 254 if (crtc_state->pch_pfit.enabled) { 255 width = drm_rect_width(&crtc_state->pch_pfit.dst); 256 height = drm_rect_height(&crtc_state->pch_pfit.dst); 257 } else { 258 width = pipe_mode->crtc_hdisplay; 259 height = pipe_mode->crtc_vdisplay; 260 } 261 return skl_update_scaler(crtc_state, !crtc_state->hw.active, 262 SKL_CRTC_INDEX, 263 &crtc_state->scaler_state.scaler_id, 264 drm_rect_width(&crtc_state->pipe_src), 265 drm_rect_height(&crtc_state->pipe_src), 266 width, height, NULL, 0, 267 crtc_state->pch_pfit.enabled); 268 } 269 270 /** 271 * skl_update_scaler_plane - Stages update to scaler state for a given plane. 272 * @crtc_state: crtc's scaler state 273 * @plane_state: atomic plane state to update 274 * 275 * Return 276 * 0 - scaler_usage updated successfully 277 * error - requested scaling cannot be supported or other error condition 278 */ 279 int skl_update_scaler_plane(struct intel_crtc_state *crtc_state, 280 struct intel_plane_state *plane_state) 281 { 282 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); 283 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 284 struct drm_framebuffer *fb = plane_state->hw.fb; 285 bool force_detach = !fb || !plane_state->uapi.visible; 286 bool need_scaler = false; 287 288 /* Pre-gen11 and SDR planes always need a scaler for planar formats. */ 289 if (!icl_is_hdr_plane(dev_priv, plane->id) && 290 fb && intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier)) 291 need_scaler = true; 292 293 return skl_update_scaler(crtc_state, force_detach, 294 drm_plane_index(&plane->base), 295 &plane_state->scaler_id, 296 drm_rect_width(&plane_state->uapi.src) >> 16, 297 drm_rect_height(&plane_state->uapi.src) >> 16, 298 drm_rect_width(&plane_state->uapi.dst), 299 drm_rect_height(&plane_state->uapi.dst), 300 fb ? fb->format : NULL, 301 fb ? fb->modifier : 0, 302 need_scaler); 303 } 304 305 static int intel_allocate_scaler(struct intel_crtc_scaler_state *scaler_state, 306 struct intel_crtc *crtc) 307 { 308 int i; 309 310 for (i = 0; i < crtc->num_scalers; i++) { 311 if (scaler_state->scalers[i].in_use) 312 continue; 313 314 scaler_state->scalers[i].in_use = true; 315 316 return i; 317 } 318 319 return -1; 320 } 321 322 static int intel_atomic_setup_scaler(struct intel_crtc_scaler_state *scaler_state, 323 int num_scalers_need, struct intel_crtc *crtc, 324 const char *name, int idx, 325 struct intel_plane_state *plane_state, 326 int *scaler_id) 327 { 328 struct intel_display *display = to_intel_display(crtc); 329 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 330 u32 mode; 331 332 if (*scaler_id < 0) 333 *scaler_id = intel_allocate_scaler(scaler_state, crtc); 334 335 if (drm_WARN(display->drm, *scaler_id < 0, 336 "Cannot find scaler for %s:%d\n", name, idx)) 337 return -EINVAL; 338 339 /* set scaler mode */ 340 if (plane_state && plane_state->hw.fb && 341 plane_state->hw.fb->format->is_yuv && 342 plane_state->hw.fb->format->num_planes > 1) { 343 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); 344 345 if (DISPLAY_VER(display) == 9) { 346 mode = SKL_PS_SCALER_MODE_NV12; 347 } else if (icl_is_hdr_plane(dev_priv, plane->id)) { 348 /* 349 * On gen11+'s HDR planes we only use the scaler for 350 * scaling. They have a dedicated chroma upsampler, so 351 * we don't need the scaler to upsample the UV plane. 352 */ 353 mode = PS_SCALER_MODE_NORMAL; 354 } else { 355 struct intel_plane *linked = 356 plane_state->planar_linked_plane; 357 358 mode = PS_SCALER_MODE_PLANAR; 359 360 if (linked) 361 mode |= PS_BINDING_Y_PLANE(linked->id); 362 } 363 } else if (DISPLAY_VER(display) >= 10) { 364 mode = PS_SCALER_MODE_NORMAL; 365 } else if (num_scalers_need == 1 && crtc->num_scalers > 1) { 366 /* 367 * when only 1 scaler is in use on a pipe with 2 scalers 368 * scaler 0 operates in high quality (HQ) mode. 369 * In this case use scaler 0 to take advantage of HQ mode 370 */ 371 scaler_state->scalers[*scaler_id].in_use = false; 372 *scaler_id = 0; 373 scaler_state->scalers[0].in_use = true; 374 mode = SKL_PS_SCALER_MODE_HQ; 375 } else { 376 mode = SKL_PS_SCALER_MODE_DYN; 377 } 378 379 /* 380 * FIXME: we should also check the scaler factors for pfit, so 381 * this shouldn't be tied directly to planes. 382 */ 383 if (plane_state && plane_state->hw.fb) { 384 const struct drm_framebuffer *fb = plane_state->hw.fb; 385 const struct drm_rect *src = &plane_state->uapi.src; 386 const struct drm_rect *dst = &plane_state->uapi.dst; 387 int hscale, vscale, max_vscale, max_hscale; 388 389 /* 390 * FIXME: When two scalers are needed, but only one of 391 * them needs to downscale, we should make sure that 392 * the one that needs downscaling support is assigned 393 * as the first scaler, so we don't reject downscaling 394 * unnecessarily. 395 */ 396 397 if (DISPLAY_VER(display) >= 14) { 398 /* 399 * On versions 14 and up, only the first 400 * scaler supports a vertical scaling factor 401 * of more than 1.0, while a horizontal 402 * scaling factor of 3.0 is supported. 403 */ 404 max_hscale = 0x30000 - 1; 405 if (*scaler_id == 0) 406 max_vscale = 0x30000 - 1; 407 else 408 max_vscale = 0x10000; 409 410 } else if (DISPLAY_VER(display) >= 10 || 411 !intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier)) { 412 max_hscale = 0x30000 - 1; 413 max_vscale = 0x30000 - 1; 414 } else { 415 max_hscale = 0x20000 - 1; 416 max_vscale = 0x20000 - 1; 417 } 418 419 /* 420 * FIXME: We should change the if-else block above to 421 * support HQ vs dynamic scaler properly. 422 */ 423 424 /* Check if required scaling is within limits */ 425 hscale = drm_rect_calc_hscale(src, dst, 1, max_hscale); 426 vscale = drm_rect_calc_vscale(src, dst, 1, max_vscale); 427 428 if (hscale < 0 || vscale < 0) { 429 drm_dbg_kms(display->drm, 430 "[CRTC:%d:%s] scaler %d doesn't support required plane scaling\n", 431 crtc->base.base.id, crtc->base.name, *scaler_id); 432 drm_rect_debug_print("src: ", src, true); 433 drm_rect_debug_print("dst: ", dst, false); 434 435 return -EINVAL; 436 } 437 } 438 439 drm_dbg_kms(display->drm, "[CRTC:%d:%s] attached scaler id %u.%u to %s:%d\n", 440 crtc->base.base.id, crtc->base.name, 441 crtc->pipe, *scaler_id, name, idx); 442 scaler_state->scalers[*scaler_id].mode = mode; 443 444 return 0; 445 } 446 447 static int setup_crtc_scaler(struct intel_atomic_state *state, 448 struct intel_crtc *crtc) 449 { 450 struct intel_crtc_state *crtc_state = 451 intel_atomic_get_new_crtc_state(state, crtc); 452 struct intel_crtc_scaler_state *scaler_state = 453 &crtc_state->scaler_state; 454 455 return intel_atomic_setup_scaler(scaler_state, 456 hweight32(scaler_state->scaler_users), 457 crtc, "CRTC", crtc->base.base.id, 458 NULL, &scaler_state->scaler_id); 459 } 460 461 static int setup_plane_scaler(struct intel_atomic_state *state, 462 struct intel_crtc *crtc, 463 struct intel_plane *plane) 464 { 465 struct intel_display *display = to_intel_display(state); 466 struct intel_crtc_state *crtc_state = 467 intel_atomic_get_new_crtc_state(state, crtc); 468 struct intel_crtc_scaler_state *scaler_state = 469 &crtc_state->scaler_state; 470 struct intel_plane_state *plane_state; 471 472 /* plane on different crtc cannot be a scaler user of this crtc */ 473 if (drm_WARN_ON(display->drm, plane->pipe != crtc->pipe)) 474 return 0; 475 476 plane_state = intel_atomic_get_new_plane_state(state, plane); 477 478 /* 479 * GLK+ scalers don't have a HQ mode so it 480 * isn't necessary to change between HQ and dyn mode 481 * on those platforms. 482 */ 483 if (!plane_state && DISPLAY_VER(display) >= 10) 484 return 0; 485 486 plane_state = intel_atomic_get_plane_state(state, plane); 487 if (IS_ERR(plane_state)) 488 return PTR_ERR(plane_state); 489 490 return intel_atomic_setup_scaler(scaler_state, 491 hweight32(scaler_state->scaler_users), 492 crtc, "PLANE", plane->base.base.id, 493 plane_state, &plane_state->scaler_id); 494 } 495 496 /** 497 * intel_atomic_setup_scalers() - setup scalers for crtc per staged requests 498 * @state: atomic state 499 * @crtc: crtc 500 * 501 * This function sets up scalers based on staged scaling requests for 502 * a @crtc and its planes. It is called from crtc level check path. If request 503 * is a supportable request, it attaches scalers to requested planes and crtc. 504 * 505 * This function takes into account the current scaler(s) in use by any planes 506 * not being part of this atomic state 507 * 508 * Returns: 509 * 0 - scalers were setup successfully 510 * error code - otherwise 511 */ 512 int intel_atomic_setup_scalers(struct intel_atomic_state *state, 513 struct intel_crtc *crtc) 514 { 515 struct intel_display *display = to_intel_display(crtc); 516 struct intel_crtc_state *crtc_state = 517 intel_atomic_get_new_crtc_state(state, crtc); 518 struct intel_crtc_scaler_state *scaler_state = 519 &crtc_state->scaler_state; 520 int num_scalers_need; 521 int i; 522 523 num_scalers_need = hweight32(scaler_state->scaler_users); 524 525 /* 526 * High level flow: 527 * - staged scaler requests are already in scaler_state->scaler_users 528 * - check whether staged scaling requests can be supported 529 * - add planes using scalers that aren't in current transaction 530 * - assign scalers to requested users 531 * - as part of plane commit, scalers will be committed 532 * (i.e., either attached or detached) to respective planes in hw 533 * - as part of crtc_commit, scaler will be either attached or detached 534 * to crtc in hw 535 */ 536 537 /* fail if required scalers > available scalers */ 538 if (num_scalers_need > crtc->num_scalers) { 539 drm_dbg_kms(display->drm, 540 "[CRTC:%d:%s] too many scaling requests %d > %d\n", 541 crtc->base.base.id, crtc->base.name, 542 num_scalers_need, crtc->num_scalers); 543 return -EINVAL; 544 } 545 546 /* walkthrough scaler_users bits and start assigning scalers */ 547 for (i = 0; i < sizeof(scaler_state->scaler_users) * 8; i++) { 548 int ret; 549 550 /* skip if scaler not required */ 551 if (!(scaler_state->scaler_users & (1 << i))) 552 continue; 553 554 if (i == SKL_CRTC_INDEX) { 555 ret = setup_crtc_scaler(state, crtc); 556 if (ret) 557 return ret; 558 } else { 559 struct intel_plane *plane = 560 to_intel_plane(drm_plane_from_index(display->drm, i)); 561 562 ret = setup_plane_scaler(state, crtc, plane); 563 if (ret) 564 return ret; 565 } 566 } 567 568 return 0; 569 } 570 571 static int glk_coef_tap(int i) 572 { 573 return i % 7; 574 } 575 576 static u16 glk_nearest_filter_coef(int t) 577 { 578 return t == 3 ? 0x0800 : 0x3000; 579 } 580 581 /* 582 * Theory behind setting nearest-neighbor integer scaling: 583 * 584 * 17 phase of 7 taps requires 119 coefficients in 60 dwords per set. 585 * The letter represents the filter tap (D is the center tap) and the number 586 * represents the coefficient set for a phase (0-16). 587 * 588 * +------------+------------------------+------------------------+ 589 * |Index value | Data value coeffient 1 | Data value coeffient 2 | 590 * +------------+------------------------+------------------------+ 591 * | 00h | B0 | A0 | 592 * +------------+------------------------+------------------------+ 593 * | 01h | D0 | C0 | 594 * +------------+------------------------+------------------------+ 595 * | 02h | F0 | E0 | 596 * +------------+------------------------+------------------------+ 597 * | 03h | A1 | G0 | 598 * +------------+------------------------+------------------------+ 599 * | 04h | C1 | B1 | 600 * +------------+------------------------+------------------------+ 601 * | ... | ... | ... | 602 * +------------+------------------------+------------------------+ 603 * | 38h | B16 | A16 | 604 * +------------+------------------------+------------------------+ 605 * | 39h | D16 | C16 | 606 * +------------+------------------------+------------------------+ 607 * | 3Ah | F16 | C16 | 608 * +------------+------------------------+------------------------+ 609 * | 3Bh | Reserved | G16 | 610 * +------------+------------------------+------------------------+ 611 * 612 * To enable nearest-neighbor scaling: program scaler coefficents with 613 * the center tap (Dxx) values set to 1 and all other values set to 0 as per 614 * SCALER_COEFFICIENT_FORMAT 615 * 616 */ 617 618 static void glk_program_nearest_filter_coefs(struct intel_display *display, 619 enum pipe pipe, int id, int set) 620 { 621 int i; 622 623 intel_de_write_fw(display, GLK_PS_COEF_INDEX_SET(pipe, id, set), 624 PS_COEF_INDEX_AUTO_INC); 625 626 for (i = 0; i < 17 * 7; i += 2) { 627 u32 tmp; 628 int t; 629 630 t = glk_coef_tap(i); 631 tmp = glk_nearest_filter_coef(t); 632 633 t = glk_coef_tap(i + 1); 634 tmp |= glk_nearest_filter_coef(t) << 16; 635 636 intel_de_write_fw(display, GLK_PS_COEF_DATA_SET(pipe, id, set), 637 tmp); 638 } 639 640 intel_de_write_fw(display, GLK_PS_COEF_INDEX_SET(pipe, id, set), 0); 641 } 642 643 static u32 skl_scaler_get_filter_select(enum drm_scaling_filter filter, int set) 644 { 645 if (filter == DRM_SCALING_FILTER_NEAREST_NEIGHBOR) { 646 return (PS_FILTER_PROGRAMMED | 647 PS_Y_VERT_FILTER_SELECT(set) | 648 PS_Y_HORZ_FILTER_SELECT(set) | 649 PS_UV_VERT_FILTER_SELECT(set) | 650 PS_UV_HORZ_FILTER_SELECT(set)); 651 } 652 653 return PS_FILTER_MEDIUM; 654 } 655 656 static void skl_scaler_setup_filter(struct intel_display *display, enum pipe pipe, 657 int id, int set, enum drm_scaling_filter filter) 658 { 659 switch (filter) { 660 case DRM_SCALING_FILTER_DEFAULT: 661 break; 662 case DRM_SCALING_FILTER_NEAREST_NEIGHBOR: 663 glk_program_nearest_filter_coefs(display, pipe, id, set); 664 break; 665 default: 666 MISSING_CASE(filter); 667 } 668 } 669 670 void skl_pfit_enable(const struct intel_crtc_state *crtc_state) 671 { 672 struct intel_display *display = to_intel_display(crtc_state); 673 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 674 const struct intel_crtc_scaler_state *scaler_state = 675 &crtc_state->scaler_state; 676 const struct drm_rect *dst = &crtc_state->pch_pfit.dst; 677 u16 uv_rgb_hphase, uv_rgb_vphase; 678 enum pipe pipe = crtc->pipe; 679 int width = drm_rect_width(dst); 680 int height = drm_rect_height(dst); 681 int x = dst->x1; 682 int y = dst->y1; 683 int hscale, vscale; 684 struct drm_rect src; 685 int id; 686 u32 ps_ctrl; 687 688 if (!crtc_state->pch_pfit.enabled) 689 return; 690 691 if (drm_WARN_ON(display->drm, 692 crtc_state->scaler_state.scaler_id < 0)) 693 return; 694 695 drm_rect_init(&src, 0, 0, 696 drm_rect_width(&crtc_state->pipe_src) << 16, 697 drm_rect_height(&crtc_state->pipe_src) << 16); 698 699 hscale = drm_rect_calc_hscale(&src, dst, 0, INT_MAX); 700 vscale = drm_rect_calc_vscale(&src, dst, 0, INT_MAX); 701 702 uv_rgb_hphase = skl_scaler_calc_phase(1, hscale, false); 703 uv_rgb_vphase = skl_scaler_calc_phase(1, vscale, false); 704 705 id = scaler_state->scaler_id; 706 707 ps_ctrl = PS_SCALER_EN | PS_BINDING_PIPE | scaler_state->scalers[id].mode | 708 skl_scaler_get_filter_select(crtc_state->hw.scaling_filter, 0); 709 710 trace_intel_pipe_scaler_update_arm(crtc, id, x, y, width, height); 711 712 skl_scaler_setup_filter(display, pipe, id, 0, 713 crtc_state->hw.scaling_filter); 714 715 intel_de_write_fw(display, SKL_PS_CTRL(pipe, id), ps_ctrl); 716 717 intel_de_write_fw(display, SKL_PS_VPHASE(pipe, id), 718 PS_Y_PHASE(0) | PS_UV_RGB_PHASE(uv_rgb_vphase)); 719 intel_de_write_fw(display, SKL_PS_HPHASE(pipe, id), 720 PS_Y_PHASE(0) | PS_UV_RGB_PHASE(uv_rgb_hphase)); 721 intel_de_write_fw(display, SKL_PS_WIN_POS(pipe, id), 722 PS_WIN_XPOS(x) | PS_WIN_YPOS(y)); 723 intel_de_write_fw(display, SKL_PS_WIN_SZ(pipe, id), 724 PS_WIN_XSIZE(width) | PS_WIN_YSIZE(height)); 725 } 726 727 void 728 skl_program_plane_scaler(struct intel_plane *plane, 729 const struct intel_crtc_state *crtc_state, 730 const struct intel_plane_state *plane_state) 731 { 732 struct intel_display *display = to_intel_display(plane); 733 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 734 const struct drm_framebuffer *fb = plane_state->hw.fb; 735 enum pipe pipe = plane->pipe; 736 int scaler_id = plane_state->scaler_id; 737 const struct intel_scaler *scaler = 738 &crtc_state->scaler_state.scalers[scaler_id]; 739 int crtc_x = plane_state->uapi.dst.x1; 740 int crtc_y = plane_state->uapi.dst.y1; 741 u32 crtc_w = drm_rect_width(&plane_state->uapi.dst); 742 u32 crtc_h = drm_rect_height(&plane_state->uapi.dst); 743 u16 y_hphase, uv_rgb_hphase; 744 u16 y_vphase, uv_rgb_vphase; 745 int hscale, vscale; 746 u32 ps_ctrl; 747 748 hscale = drm_rect_calc_hscale(&plane_state->uapi.src, 749 &plane_state->uapi.dst, 750 0, INT_MAX); 751 vscale = drm_rect_calc_vscale(&plane_state->uapi.src, 752 &plane_state->uapi.dst, 753 0, INT_MAX); 754 755 /* TODO: handle sub-pixel coordinates */ 756 if (intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier) && 757 !icl_is_hdr_plane(dev_priv, plane->id)) { 758 y_hphase = skl_scaler_calc_phase(1, hscale, false); 759 y_vphase = skl_scaler_calc_phase(1, vscale, false); 760 761 /* MPEG2 chroma siting convention */ 762 uv_rgb_hphase = skl_scaler_calc_phase(2, hscale, true); 763 uv_rgb_vphase = skl_scaler_calc_phase(2, vscale, false); 764 } else { 765 /* not used */ 766 y_hphase = 0; 767 y_vphase = 0; 768 769 uv_rgb_hphase = skl_scaler_calc_phase(1, hscale, false); 770 uv_rgb_vphase = skl_scaler_calc_phase(1, vscale, false); 771 } 772 773 ps_ctrl = PS_SCALER_EN | PS_BINDING_PLANE(plane->id) | scaler->mode | 774 skl_scaler_get_filter_select(plane_state->hw.scaling_filter, 0); 775 776 trace_intel_plane_scaler_update_arm(plane, scaler_id, 777 crtc_x, crtc_y, crtc_w, crtc_h); 778 779 skl_scaler_setup_filter(display, pipe, scaler_id, 0, 780 plane_state->hw.scaling_filter); 781 782 intel_de_write_fw(display, SKL_PS_CTRL(pipe, scaler_id), ps_ctrl); 783 intel_de_write_fw(display, SKL_PS_VPHASE(pipe, scaler_id), 784 PS_Y_PHASE(y_vphase) | PS_UV_RGB_PHASE(uv_rgb_vphase)); 785 intel_de_write_fw(display, SKL_PS_HPHASE(pipe, scaler_id), 786 PS_Y_PHASE(y_hphase) | PS_UV_RGB_PHASE(uv_rgb_hphase)); 787 intel_de_write_fw(display, SKL_PS_WIN_POS(pipe, scaler_id), 788 PS_WIN_XPOS(crtc_x) | PS_WIN_YPOS(crtc_y)); 789 intel_de_write_fw(display, SKL_PS_WIN_SZ(pipe, scaler_id), 790 PS_WIN_XSIZE(crtc_w) | PS_WIN_YSIZE(crtc_h)); 791 } 792 793 static void skl_detach_scaler(struct intel_crtc *crtc, int id) 794 { 795 struct intel_display *display = to_intel_display(crtc); 796 797 trace_intel_scaler_disable_arm(crtc, id); 798 799 intel_de_write_fw(display, SKL_PS_CTRL(crtc->pipe, id), 0); 800 intel_de_write_fw(display, SKL_PS_WIN_POS(crtc->pipe, id), 0); 801 intel_de_write_fw(display, SKL_PS_WIN_SZ(crtc->pipe, id), 0); 802 } 803 804 /* 805 * This function detaches (aka. unbinds) unused scalers in hardware 806 */ 807 void skl_detach_scalers(const struct intel_crtc_state *crtc_state) 808 { 809 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 810 const struct intel_crtc_scaler_state *scaler_state = 811 &crtc_state->scaler_state; 812 int i; 813 814 /* loop through and disable scalers that aren't in use */ 815 for (i = 0; i < crtc->num_scalers; i++) { 816 if (!scaler_state->scalers[i].in_use) 817 skl_detach_scaler(crtc, i); 818 } 819 } 820 821 void skl_scaler_disable(const struct intel_crtc_state *old_crtc_state) 822 { 823 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); 824 int i; 825 826 for (i = 0; i < crtc->num_scalers; i++) 827 skl_detach_scaler(crtc, i); 828 } 829 830 void skl_scaler_get_config(struct intel_crtc_state *crtc_state) 831 { 832 struct intel_display *display = to_intel_display(crtc_state); 833 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 834 struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state; 835 int id = -1; 836 int i; 837 838 /* find scaler attached to this pipe */ 839 for (i = 0; i < crtc->num_scalers; i++) { 840 u32 ctl, pos, size; 841 842 ctl = intel_de_read(display, SKL_PS_CTRL(crtc->pipe, i)); 843 if ((ctl & (PS_SCALER_EN | PS_BINDING_MASK)) != (PS_SCALER_EN | PS_BINDING_PIPE)) 844 continue; 845 846 id = i; 847 crtc_state->pch_pfit.enabled = true; 848 849 pos = intel_de_read(display, SKL_PS_WIN_POS(crtc->pipe, i)); 850 size = intel_de_read(display, SKL_PS_WIN_SZ(crtc->pipe, i)); 851 852 drm_rect_init(&crtc_state->pch_pfit.dst, 853 REG_FIELD_GET(PS_WIN_XPOS_MASK, pos), 854 REG_FIELD_GET(PS_WIN_YPOS_MASK, pos), 855 REG_FIELD_GET(PS_WIN_XSIZE_MASK, size), 856 REG_FIELD_GET(PS_WIN_YSIZE_MASK, size)); 857 858 scaler_state->scalers[i].in_use = true; 859 break; 860 } 861 862 scaler_state->scaler_id = id; 863 if (id >= 0) 864 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX); 865 else 866 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX); 867 } 868