1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2020 Intel Corporation 4 */ 5 6 #include <drm/drm_print.h> 7 8 #include "i915_utils.h" 9 #include "intel_de.h" 10 #include "intel_display_regs.h" 11 #include "intel_display_trace.h" 12 #include "intel_display_types.h" 13 #include "intel_fb.h" 14 #include "skl_scaler.h" 15 #include "skl_universal_plane.h" 16 17 /* 18 * The hardware phase 0.0 refers to the center of the pixel. 19 * We want to start from the top/left edge which is phase 20 * -0.5. That matches how the hardware calculates the scaling 21 * factors (from top-left of the first pixel to bottom-right 22 * of the last pixel, as opposed to the pixel centers). 23 * 24 * For 4:2:0 subsampled chroma planes we obviously have to 25 * adjust that so that the chroma sample position lands in 26 * the right spot. 27 * 28 * Note that for packed YCbCr 4:2:2 formats there is no way to 29 * control chroma siting. The hardware simply replicates the 30 * chroma samples for both of the luma samples, and thus we don't 31 * actually get the expected MPEG2 chroma siting convention :( 32 * The same behaviour is observed on pre-SKL platforms as well. 33 * 34 * Theory behind the formula (note that we ignore sub-pixel 35 * source coordinates): 36 * s = source sample position 37 * d = destination sample position 38 * 39 * Downscaling 4:1: 40 * -0.5 41 * | 0.0 42 * | | 1.5 (initial phase) 43 * | | | 44 * v v v 45 * | s | s | s | s | 46 * | d | 47 * 48 * Upscaling 1:4: 49 * -0.5 50 * | -0.375 (initial phase) 51 * | | 0.0 52 * | | | 53 * v v v 54 * | s | 55 * | d | d | d | d | 56 */ 57 static u16 skl_scaler_calc_phase(int sub, int scale, bool chroma_cosited) 58 { 59 int phase = -0x8000; 60 u16 trip = 0; 61 62 if (chroma_cosited) 63 phase += (sub - 1) * 0x8000 / sub; 64 65 phase += scale / (2 * sub); 66 67 /* 68 * Hardware initial phase limited to [-0.5:1.5]. 69 * Since the max hardware scale factor is 3.0, we 70 * should never actually exceed 1.0 here. 71 */ 72 WARN_ON(phase < -0x8000 || phase > 0x18000); 73 74 if (phase < 0) 75 phase = 0x10000 + phase; 76 else 77 trip = PS_PHASE_TRIP; 78 79 return ((phase >> 2) & PS_PHASE_MASK) | trip; 80 } 81 82 static void skl_scaler_min_src_size(const struct drm_format_info *format, 83 u64 modifier, int *min_w, int *min_h) 84 { 85 if (format && intel_format_info_is_yuv_semiplanar(format, modifier)) { 86 *min_w = 16; 87 *min_h = 16; 88 } else { 89 *min_w = 8; 90 *min_h = 8; 91 } 92 } 93 94 static void skl_scaler_max_src_size(struct intel_crtc *crtc, 95 int *max_w, int *max_h) 96 { 97 struct intel_display *display = to_intel_display(crtc); 98 99 if (DISPLAY_VER(display) >= 14) { 100 *max_w = 4096; 101 *max_h = 8192; 102 } else if (DISPLAY_VER(display) >= 12) { 103 *max_w = 5120; 104 *max_h = 8192; 105 } else if (DISPLAY_VER(display) == 11) { 106 *max_w = 5120; 107 *max_h = 4096; 108 } else { 109 *max_w = 4096; 110 *max_h = 4096; 111 } 112 } 113 114 static void skl_scaler_min_dst_size(int *min_w, int *min_h) 115 { 116 *min_w = 8; 117 *min_h = 8; 118 } 119 120 static void skl_scaler_max_dst_size(struct intel_crtc *crtc, 121 int *max_w, int *max_h) 122 { 123 struct intel_display *display = to_intel_display(crtc); 124 125 if (DISPLAY_VER(display) >= 12) { 126 *max_w = 8192; 127 *max_h = 8192; 128 } else if (DISPLAY_VER(display) == 11) { 129 *max_w = 5120; 130 *max_h = 4096; 131 } else { 132 *max_w = 4096; 133 *max_h = 4096; 134 } 135 } 136 137 static int 138 skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach, 139 unsigned int scaler_user, int *scaler_id, 140 int src_w, int src_h, int dst_w, int dst_h, 141 const struct drm_format_info *format, 142 u64 modifier, bool need_scaler) 143 { 144 struct intel_display *display = to_intel_display(crtc_state); 145 struct intel_crtc_scaler_state *scaler_state = 146 &crtc_state->scaler_state; 147 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 148 const struct drm_display_mode *adjusted_mode = 149 &crtc_state->hw.adjusted_mode; 150 int pipe_src_w = drm_rect_width(&crtc_state->pipe_src); 151 int pipe_src_h = drm_rect_height(&crtc_state->pipe_src); 152 int min_src_w, min_src_h, min_dst_w, min_dst_h; 153 int max_src_w, max_src_h, max_dst_w, max_dst_h; 154 155 /* 156 * Src coordinates are already rotated by 270 degrees for 157 * the 90/270 degree plane rotation cases (to match the 158 * GTT mapping), hence no need to account for rotation here. 159 */ 160 if (src_w != dst_w || src_h != dst_h) 161 need_scaler = true; 162 163 /* 164 * Scaling/fitting not supported in IF-ID mode in GEN9+ 165 * TODO: Interlace fetch mode doesn't support YUV420 planar formats. 166 * Once NV12 is enabled, handle it here while allocating scaler 167 * for NV12. 168 */ 169 if (DISPLAY_VER(display) >= 9 && crtc_state->hw.enable && 170 need_scaler && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { 171 drm_dbg_kms(display->drm, 172 "[CRTC:%d:%s] scaling not supported with IF-ID mode\n", 173 crtc->base.base.id, crtc->base.name); 174 return -EINVAL; 175 } 176 177 /* 178 * if plane is being disabled or scaler is no more required or force detach 179 * - free scaler binded to this plane/crtc 180 * - in order to do this, update crtc->scaler_usage 181 * 182 * Here scaler state in crtc_state is set free so that 183 * scaler can be assigned to other user. Actual register 184 * update to free the scaler is done in plane/panel-fit programming. 185 * For this purpose crtc/plane_state->scaler_id isn't reset here. 186 */ 187 if (force_detach || !need_scaler) { 188 if (*scaler_id >= 0) { 189 scaler_state->scaler_users &= ~(1 << scaler_user); 190 scaler_state->scalers[*scaler_id].in_use = false; 191 192 drm_dbg_kms(display->drm, 193 "[CRTC:%d:%s] scaler_user index %u.%u: " 194 "Staged freeing scaler id %d scaler_users = 0x%x\n", 195 crtc->base.base.id, crtc->base.name, 196 crtc->pipe, scaler_user, *scaler_id, 197 scaler_state->scaler_users); 198 *scaler_id = -1; 199 } 200 return 0; 201 } 202 203 skl_scaler_min_src_size(format, modifier, &min_src_w, &min_src_h); 204 skl_scaler_max_src_size(crtc, &max_src_w, &max_src_h); 205 206 skl_scaler_min_dst_size(&min_dst_w, &min_dst_h); 207 skl_scaler_max_dst_size(crtc, &max_dst_w, &max_dst_h); 208 209 /* range checks */ 210 if (src_w < min_src_w || src_h < min_src_h || 211 dst_w < min_dst_w || dst_h < min_dst_h || 212 src_w > max_src_w || src_h > max_src_h || 213 dst_w > max_dst_w || dst_h > max_dst_h) { 214 drm_dbg_kms(display->drm, 215 "[CRTC:%d:%s] scaler_user index %u.%u: src %ux%u dst %ux%u " 216 "size is out of scaler range\n", 217 crtc->base.base.id, crtc->base.name, 218 crtc->pipe, scaler_user, src_w, src_h, 219 dst_w, dst_h); 220 return -EINVAL; 221 } 222 223 /* 224 * The pipe scaler does not use all the bits of PIPESRC, at least 225 * on the earlier platforms. So even when we're scaling a plane 226 * the *pipe* source size must not be too large. For simplicity 227 * we assume the limits match the scaler destination size limits. 228 * Might not be 100% accurate on all platforms, but good enough for 229 * now. 230 */ 231 if (pipe_src_w > max_dst_w || pipe_src_h > max_dst_h) { 232 drm_dbg_kms(display->drm, 233 "[CRTC:%d:%s] scaler_user index %u.%u: pipe src size %ux%u " 234 "is out of scaler range\n", 235 crtc->base.base.id, crtc->base.name, 236 crtc->pipe, scaler_user, pipe_src_w, pipe_src_h); 237 return -EINVAL; 238 } 239 240 /* mark this plane as a scaler user in crtc_state */ 241 scaler_state->scaler_users |= (1 << scaler_user); 242 drm_dbg_kms(display->drm, "[CRTC:%d:%s] scaler_user index %u.%u: " 243 "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n", 244 crtc->base.base.id, crtc->base.name, 245 crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h, 246 scaler_state->scaler_users); 247 248 return 0; 249 } 250 251 int skl_update_scaler_crtc(struct intel_crtc_state *crtc_state) 252 { 253 const struct drm_display_mode *pipe_mode = &crtc_state->hw.pipe_mode; 254 int width, height; 255 256 if (crtc_state->pch_pfit.enabled) { 257 width = drm_rect_width(&crtc_state->pch_pfit.dst); 258 height = drm_rect_height(&crtc_state->pch_pfit.dst); 259 } else { 260 width = pipe_mode->crtc_hdisplay; 261 height = pipe_mode->crtc_vdisplay; 262 } 263 return skl_update_scaler(crtc_state, !crtc_state->hw.active, 264 SKL_CRTC_INDEX, 265 &crtc_state->scaler_state.scaler_id, 266 drm_rect_width(&crtc_state->pipe_src), 267 drm_rect_height(&crtc_state->pipe_src), 268 width, height, NULL, 0, 269 crtc_state->pch_pfit.enabled); 270 } 271 272 /** 273 * skl_update_scaler_plane - Stages update to scaler state for a given plane. 274 * @crtc_state: crtc's scaler state 275 * @plane_state: atomic plane state to update 276 * 277 * Return 278 * 0 - scaler_usage updated successfully 279 * error - requested scaling cannot be supported or other error condition 280 */ 281 int skl_update_scaler_plane(struct intel_crtc_state *crtc_state, 282 struct intel_plane_state *plane_state) 283 { 284 struct intel_display *display = to_intel_display(plane_state); 285 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); 286 struct drm_framebuffer *fb = plane_state->hw.fb; 287 bool force_detach = !fb || !plane_state->uapi.visible; 288 bool need_scaler = false; 289 290 /* Pre-gen11 and SDR planes always need a scaler for planar formats. */ 291 if (!icl_is_hdr_plane(display, plane->id) && 292 fb && intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier)) 293 need_scaler = true; 294 295 return skl_update_scaler(crtc_state, force_detach, 296 drm_plane_index(&plane->base), 297 &plane_state->scaler_id, 298 drm_rect_width(&plane_state->uapi.src) >> 16, 299 drm_rect_height(&plane_state->uapi.src) >> 16, 300 drm_rect_width(&plane_state->uapi.dst), 301 drm_rect_height(&plane_state->uapi.dst), 302 fb ? fb->format : NULL, 303 fb ? fb->modifier : 0, 304 need_scaler); 305 } 306 307 static int intel_allocate_scaler(struct intel_crtc_scaler_state *scaler_state, 308 struct intel_crtc *crtc) 309 { 310 int i; 311 312 for (i = 0; i < crtc->num_scalers; i++) { 313 if (scaler_state->scalers[i].in_use) 314 continue; 315 316 scaler_state->scalers[i].in_use = true; 317 318 return i; 319 } 320 321 return -1; 322 } 323 324 static void 325 calculate_max_scale(struct intel_crtc *crtc, 326 bool is_yuv_semiplanar, 327 int scaler_id, 328 int *max_hscale, int *max_vscale) 329 { 330 struct intel_display *display = to_intel_display(crtc); 331 332 /* 333 * FIXME: When two scalers are needed, but only one of 334 * them needs to downscale, we should make sure that 335 * the one that needs downscaling support is assigned 336 * as the first scaler, so we don't reject downscaling 337 * unnecessarily. 338 */ 339 340 if (DISPLAY_VER(display) >= 14) { 341 /* 342 * On versions 14 and up, only the first 343 * scaler supports a vertical scaling factor 344 * of more than 1.0, while a horizontal 345 * scaling factor of 3.0 is supported. 346 */ 347 *max_hscale = 0x30000 - 1; 348 349 if (scaler_id == 0) 350 *max_vscale = 0x30000 - 1; 351 else 352 *max_vscale = 0x10000; 353 } else if (DISPLAY_VER(display) >= 10 || !is_yuv_semiplanar) { 354 *max_hscale = 0x30000 - 1; 355 *max_vscale = 0x30000 - 1; 356 } else { 357 *max_hscale = 0x20000 - 1; 358 *max_vscale = 0x20000 - 1; 359 } 360 } 361 362 static int intel_atomic_setup_scaler(struct intel_crtc_state *crtc_state, 363 int num_scalers_need, struct intel_crtc *crtc, 364 const char *name, int idx, 365 struct intel_plane_state *plane_state, 366 int *scaler_id) 367 { 368 struct intel_display *display = to_intel_display(crtc); 369 struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state; 370 u32 mode; 371 int hscale = 0; 372 int vscale = 0; 373 374 if (*scaler_id < 0) 375 *scaler_id = intel_allocate_scaler(scaler_state, crtc); 376 377 if (drm_WARN(display->drm, *scaler_id < 0, 378 "Cannot find scaler for %s:%d\n", name, idx)) 379 return -EINVAL; 380 381 /* set scaler mode */ 382 if (plane_state && plane_state->hw.fb && 383 plane_state->hw.fb->format->is_yuv && 384 plane_state->hw.fb->format->num_planes > 1) { 385 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); 386 387 if (DISPLAY_VER(display) == 9) { 388 mode = SKL_PS_SCALER_MODE_NV12; 389 } else if (icl_is_hdr_plane(display, plane->id)) { 390 /* 391 * On gen11+'s HDR planes we only use the scaler for 392 * scaling. They have a dedicated chroma upsampler, so 393 * we don't need the scaler to upsample the UV plane. 394 */ 395 mode = PS_SCALER_MODE_NORMAL; 396 } else { 397 struct intel_plane *linked = 398 plane_state->planar_linked_plane; 399 400 mode = PS_SCALER_MODE_PLANAR; 401 402 if (linked) 403 mode |= PS_BINDING_Y_PLANE(linked->id); 404 } 405 } else if (DISPLAY_VER(display) >= 10) { 406 mode = PS_SCALER_MODE_NORMAL; 407 } else if (num_scalers_need == 1 && crtc->num_scalers > 1) { 408 /* 409 * when only 1 scaler is in use on a pipe with 2 scalers 410 * scaler 0 operates in high quality (HQ) mode. 411 * In this case use scaler 0 to take advantage of HQ mode 412 */ 413 scaler_state->scalers[*scaler_id].in_use = false; 414 *scaler_id = 0; 415 scaler_state->scalers[0].in_use = true; 416 mode = SKL_PS_SCALER_MODE_HQ; 417 } else { 418 mode = SKL_PS_SCALER_MODE_DYN; 419 } 420 421 if (plane_state && plane_state->hw.fb) { 422 const struct drm_framebuffer *fb = plane_state->hw.fb; 423 const struct drm_rect *src = &plane_state->uapi.src; 424 const struct drm_rect *dst = &plane_state->uapi.dst; 425 int max_hscale, max_vscale; 426 427 calculate_max_scale(crtc, 428 intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier), 429 *scaler_id, &max_hscale, &max_vscale); 430 431 /* 432 * FIXME: We should change the if-else block above to 433 * support HQ vs dynamic scaler properly. 434 */ 435 436 /* Check if required scaling is within limits */ 437 hscale = drm_rect_calc_hscale(src, dst, 1, max_hscale); 438 vscale = drm_rect_calc_vscale(src, dst, 1, max_vscale); 439 440 if (hscale < 0 || vscale < 0) { 441 drm_dbg_kms(display->drm, 442 "[CRTC:%d:%s] scaler %d doesn't support required plane scaling\n", 443 crtc->base.base.id, crtc->base.name, *scaler_id); 444 drm_rect_debug_print("src: ", src, true); 445 drm_rect_debug_print("dst: ", dst, false); 446 447 return -EINVAL; 448 } 449 } 450 451 if (crtc_state->pch_pfit.enabled) { 452 struct drm_rect src; 453 int max_hscale, max_vscale; 454 455 drm_rect_init(&src, 0, 0, 456 drm_rect_width(&crtc_state->pipe_src) << 16, 457 drm_rect_height(&crtc_state->pipe_src) << 16); 458 459 calculate_max_scale(crtc, 0, *scaler_id, 460 &max_hscale, &max_vscale); 461 462 /* 463 * When configured for Pipe YUV 420 encoding for port output, 464 * limit downscaling to less than 1.5 (source/destination) in 465 * the horizontal direction and 1.0 in the vertical direction. 466 */ 467 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) { 468 max_hscale = 0x18000 - 1; 469 max_vscale = 0x10000; 470 } 471 472 hscale = drm_rect_calc_hscale(&src, &crtc_state->pch_pfit.dst, 473 0, max_hscale); 474 vscale = drm_rect_calc_vscale(&src, &crtc_state->pch_pfit.dst, 475 0, max_vscale); 476 477 if (hscale < 0 || vscale < 0) { 478 drm_dbg_kms(display->drm, 479 "Scaler %d doesn't support required pipe scaling\n", 480 *scaler_id); 481 drm_rect_debug_print("src: ", &src, true); 482 drm_rect_debug_print("dst: ", &crtc_state->pch_pfit.dst, false); 483 484 return -EINVAL; 485 } 486 } 487 488 scaler_state->scalers[*scaler_id].hscale = hscale; 489 scaler_state->scalers[*scaler_id].vscale = vscale; 490 491 drm_dbg_kms(display->drm, "[CRTC:%d:%s] attached scaler id %u.%u to %s:%d\n", 492 crtc->base.base.id, crtc->base.name, 493 crtc->pipe, *scaler_id, name, idx); 494 scaler_state->scalers[*scaler_id].mode = mode; 495 496 return 0; 497 } 498 499 static int setup_crtc_scaler(struct intel_atomic_state *state, 500 struct intel_crtc *crtc) 501 { 502 struct intel_crtc_state *crtc_state = 503 intel_atomic_get_new_crtc_state(state, crtc); 504 struct intel_crtc_scaler_state *scaler_state = 505 &crtc_state->scaler_state; 506 507 return intel_atomic_setup_scaler(crtc_state, 508 hweight32(scaler_state->scaler_users), 509 crtc, "CRTC", crtc->base.base.id, 510 NULL, &scaler_state->scaler_id); 511 } 512 513 static int setup_plane_scaler(struct intel_atomic_state *state, 514 struct intel_crtc *crtc, 515 struct intel_plane *plane) 516 { 517 struct intel_display *display = to_intel_display(state); 518 struct intel_crtc_state *crtc_state = 519 intel_atomic_get_new_crtc_state(state, crtc); 520 struct intel_crtc_scaler_state *scaler_state = 521 &crtc_state->scaler_state; 522 struct intel_plane_state *plane_state; 523 524 /* plane on different crtc cannot be a scaler user of this crtc */ 525 if (drm_WARN_ON(display->drm, plane->pipe != crtc->pipe)) 526 return 0; 527 528 plane_state = intel_atomic_get_new_plane_state(state, plane); 529 530 /* 531 * GLK+ scalers don't have a HQ mode so it 532 * isn't necessary to change between HQ and dyn mode 533 * on those platforms. 534 */ 535 if (!plane_state && DISPLAY_VER(display) >= 10) 536 return 0; 537 538 plane_state = intel_atomic_get_plane_state(state, plane); 539 if (IS_ERR(plane_state)) 540 return PTR_ERR(plane_state); 541 542 return intel_atomic_setup_scaler(crtc_state, 543 hweight32(scaler_state->scaler_users), 544 crtc, "PLANE", plane->base.base.id, 545 plane_state, &plane_state->scaler_id); 546 } 547 548 /** 549 * intel_atomic_setup_scalers() - setup scalers for crtc per staged requests 550 * @state: atomic state 551 * @crtc: crtc 552 * 553 * This function sets up scalers based on staged scaling requests for 554 * a @crtc and its planes. It is called from crtc level check path. If request 555 * is a supportable request, it attaches scalers to requested planes and crtc. 556 * 557 * This function takes into account the current scaler(s) in use by any planes 558 * not being part of this atomic state 559 * 560 * Returns: 561 * 0 - scalers were setup successfully 562 * error code - otherwise 563 */ 564 int intel_atomic_setup_scalers(struct intel_atomic_state *state, 565 struct intel_crtc *crtc) 566 { 567 struct intel_display *display = to_intel_display(crtc); 568 struct intel_crtc_state *crtc_state = 569 intel_atomic_get_new_crtc_state(state, crtc); 570 struct intel_crtc_scaler_state *scaler_state = 571 &crtc_state->scaler_state; 572 int num_scalers_need; 573 int i; 574 575 num_scalers_need = hweight32(scaler_state->scaler_users); 576 577 /* 578 * High level flow: 579 * - staged scaler requests are already in scaler_state->scaler_users 580 * - check whether staged scaling requests can be supported 581 * - add planes using scalers that aren't in current transaction 582 * - assign scalers to requested users 583 * - as part of plane commit, scalers will be committed 584 * (i.e., either attached or detached) to respective planes in hw 585 * - as part of crtc_commit, scaler will be either attached or detached 586 * to crtc in hw 587 */ 588 589 /* fail if required scalers > available scalers */ 590 if (num_scalers_need > crtc->num_scalers) { 591 drm_dbg_kms(display->drm, 592 "[CRTC:%d:%s] too many scaling requests %d > %d\n", 593 crtc->base.base.id, crtc->base.name, 594 num_scalers_need, crtc->num_scalers); 595 return -EINVAL; 596 } 597 598 /* walkthrough scaler_users bits and start assigning scalers */ 599 for (i = 0; i < sizeof(scaler_state->scaler_users) * 8; i++) { 600 int ret; 601 602 /* skip if scaler not required */ 603 if (!(scaler_state->scaler_users & (1 << i))) 604 continue; 605 606 if (i == SKL_CRTC_INDEX) { 607 ret = setup_crtc_scaler(state, crtc); 608 if (ret) 609 return ret; 610 } else { 611 struct intel_plane *plane = 612 to_intel_plane(drm_plane_from_index(display->drm, i)); 613 614 ret = setup_plane_scaler(state, crtc, plane); 615 if (ret) 616 return ret; 617 } 618 } 619 620 return 0; 621 } 622 623 static int glk_coef_tap(int i) 624 { 625 return i % 7; 626 } 627 628 static u16 glk_nearest_filter_coef(int t) 629 { 630 return t == 3 ? 0x0800 : 0x3000; 631 } 632 633 /* 634 * Theory behind setting nearest-neighbor integer scaling: 635 * 636 * 17 phase of 7 taps requires 119 coefficients in 60 dwords per set. 637 * The letter represents the filter tap (D is the center tap) and the number 638 * represents the coefficient set for a phase (0-16). 639 * 640 * +------------+--------------------------+--------------------------+ 641 * |Index value | Data value coefficient 1 | Data value coefficient 2 | 642 * +------------+--------------------------+--------------------------+ 643 * | 00h | B0 | A0 | 644 * +------------+--------------------------+--------------------------+ 645 * | 01h | D0 | C0 | 646 * +------------+--------------------------+--------------------------+ 647 * | 02h | F0 | E0 | 648 * +------------+--------------------------+--------------------------+ 649 * | 03h | A1 | G0 | 650 * +------------+--------------------------+--------------------------+ 651 * | 04h | C1 | B1 | 652 * +------------+--------------------------+--------------------------+ 653 * | ... | ... | ... | 654 * +------------+--------------------------+--------------------------+ 655 * | 38h | B16 | A16 | 656 * +------------+--------------------------+--------------------------+ 657 * | 39h | D16 | C16 | 658 * +------------+--------------------------+--------------------------+ 659 * | 3Ah | F16 | C16 | 660 * +------------+--------------------------+--------------------------+ 661 * | 3Bh | Reserved | G16 | 662 * +------------+--------------------------+--------------------------+ 663 * 664 * To enable nearest-neighbor scaling: program scaler coefficients with 665 * the center tap (Dxx) values set to 1 and all other values set to 0 as per 666 * SCALER_COEFFICIENT_FORMAT 667 * 668 */ 669 670 static void glk_program_nearest_filter_coefs(struct intel_display *display, 671 struct intel_dsb *dsb, 672 enum pipe pipe, int id, int set) 673 { 674 int i; 675 676 intel_de_write_dsb(display, dsb, 677 GLK_PS_COEF_INDEX_SET(pipe, id, set), 678 PS_COEF_INDEX_AUTO_INC); 679 680 for (i = 0; i < 17 * 7; i += 2) { 681 u32 tmp; 682 int t; 683 684 t = glk_coef_tap(i); 685 tmp = glk_nearest_filter_coef(t); 686 687 t = glk_coef_tap(i + 1); 688 tmp |= glk_nearest_filter_coef(t) << 16; 689 690 intel_de_write_dsb(display, dsb, 691 GLK_PS_COEF_DATA_SET(pipe, id, set), tmp); 692 } 693 694 intel_de_write_dsb(display, dsb, 695 GLK_PS_COEF_INDEX_SET(pipe, id, set), 0); 696 } 697 698 static u32 skl_scaler_get_filter_select(enum drm_scaling_filter filter) 699 { 700 if (filter == DRM_SCALING_FILTER_NEAREST_NEIGHBOR) 701 return (PS_FILTER_PROGRAMMED | 702 PS_Y_VERT_FILTER_SELECT(0) | 703 PS_Y_HORZ_FILTER_SELECT(0) | 704 PS_UV_VERT_FILTER_SELECT(0) | 705 PS_UV_HORZ_FILTER_SELECT(0)); 706 707 return PS_FILTER_MEDIUM; 708 } 709 710 static void skl_scaler_setup_filter(struct intel_display *display, 711 struct intel_dsb *dsb, enum pipe pipe, 712 int id, int set, enum drm_scaling_filter filter) 713 { 714 switch (filter) { 715 case DRM_SCALING_FILTER_DEFAULT: 716 break; 717 case DRM_SCALING_FILTER_NEAREST_NEIGHBOR: 718 glk_program_nearest_filter_coefs(display, dsb, pipe, id, set); 719 break; 720 default: 721 MISSING_CASE(filter); 722 } 723 } 724 725 void skl_pfit_enable(const struct intel_crtc_state *crtc_state) 726 { 727 struct intel_display *display = to_intel_display(crtc_state); 728 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 729 const struct intel_crtc_scaler_state *scaler_state = 730 &crtc_state->scaler_state; 731 const struct drm_rect *dst = &crtc_state->pch_pfit.dst; 732 u16 uv_rgb_hphase, uv_rgb_vphase; 733 enum pipe pipe = crtc->pipe; 734 int width = drm_rect_width(dst); 735 int height = drm_rect_height(dst); 736 int x = dst->x1; 737 int y = dst->y1; 738 int hscale, vscale; 739 struct drm_rect src; 740 int id; 741 u32 ps_ctrl; 742 743 if (!crtc_state->pch_pfit.enabled) 744 return; 745 746 if (drm_WARN_ON(display->drm, 747 crtc_state->scaler_state.scaler_id < 0)) 748 return; 749 750 drm_rect_init(&src, 0, 0, 751 drm_rect_width(&crtc_state->pipe_src) << 16, 752 drm_rect_height(&crtc_state->pipe_src) << 16); 753 754 hscale = drm_rect_calc_hscale(&src, dst, 0, INT_MAX); 755 vscale = drm_rect_calc_vscale(&src, dst, 0, INT_MAX); 756 757 uv_rgb_hphase = skl_scaler_calc_phase(1, hscale, false); 758 uv_rgb_vphase = skl_scaler_calc_phase(1, vscale, false); 759 760 id = scaler_state->scaler_id; 761 762 ps_ctrl = PS_SCALER_EN | PS_BINDING_PIPE | scaler_state->scalers[id].mode | 763 skl_scaler_get_filter_select(crtc_state->hw.scaling_filter); 764 765 trace_intel_pipe_scaler_update_arm(crtc, id, x, y, width, height); 766 767 skl_scaler_setup_filter(display, NULL, pipe, id, 0, 768 crtc_state->hw.scaling_filter); 769 770 intel_de_write_fw(display, SKL_PS_CTRL(pipe, id), ps_ctrl); 771 772 intel_de_write_fw(display, SKL_PS_VPHASE(pipe, id), 773 PS_Y_PHASE(0) | PS_UV_RGB_PHASE(uv_rgb_vphase)); 774 intel_de_write_fw(display, SKL_PS_HPHASE(pipe, id), 775 PS_Y_PHASE(0) | PS_UV_RGB_PHASE(uv_rgb_hphase)); 776 intel_de_write_fw(display, SKL_PS_WIN_POS(pipe, id), 777 PS_WIN_XPOS(x) | PS_WIN_YPOS(y)); 778 intel_de_write_fw(display, SKL_PS_WIN_SZ(pipe, id), 779 PS_WIN_XSIZE(width) | PS_WIN_YSIZE(height)); 780 } 781 782 void 783 skl_program_plane_scaler(struct intel_dsb *dsb, 784 struct intel_plane *plane, 785 const struct intel_crtc_state *crtc_state, 786 const struct intel_plane_state *plane_state) 787 { 788 struct intel_display *display = to_intel_display(plane); 789 const struct drm_framebuffer *fb = plane_state->hw.fb; 790 enum pipe pipe = plane->pipe; 791 int scaler_id = plane_state->scaler_id; 792 const struct intel_scaler *scaler = 793 &crtc_state->scaler_state.scalers[scaler_id]; 794 int crtc_x = plane_state->uapi.dst.x1; 795 int crtc_y = plane_state->uapi.dst.y1; 796 u32 crtc_w = drm_rect_width(&plane_state->uapi.dst); 797 u32 crtc_h = drm_rect_height(&plane_state->uapi.dst); 798 u16 y_hphase, uv_rgb_hphase; 799 u16 y_vphase, uv_rgb_vphase; 800 int hscale, vscale; 801 u32 ps_ctrl; 802 803 hscale = drm_rect_calc_hscale(&plane_state->uapi.src, 804 &plane_state->uapi.dst, 805 0, INT_MAX); 806 vscale = drm_rect_calc_vscale(&plane_state->uapi.src, 807 &plane_state->uapi.dst, 808 0, INT_MAX); 809 810 /* TODO: handle sub-pixel coordinates */ 811 if (intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier) && 812 !icl_is_hdr_plane(display, plane->id)) { 813 y_hphase = skl_scaler_calc_phase(1, hscale, false); 814 y_vphase = skl_scaler_calc_phase(1, vscale, false); 815 816 /* MPEG2 chroma siting convention */ 817 uv_rgb_hphase = skl_scaler_calc_phase(2, hscale, true); 818 uv_rgb_vphase = skl_scaler_calc_phase(2, vscale, false); 819 } else { 820 /* not used */ 821 y_hphase = 0; 822 y_vphase = 0; 823 824 uv_rgb_hphase = skl_scaler_calc_phase(1, hscale, false); 825 uv_rgb_vphase = skl_scaler_calc_phase(1, vscale, false); 826 } 827 828 ps_ctrl = PS_SCALER_EN | PS_BINDING_PLANE(plane->id) | scaler->mode | 829 skl_scaler_get_filter_select(plane_state->hw.scaling_filter); 830 831 trace_intel_plane_scaler_update_arm(plane, scaler_id, 832 crtc_x, crtc_y, crtc_w, crtc_h); 833 834 skl_scaler_setup_filter(display, dsb, pipe, scaler_id, 0, 835 plane_state->hw.scaling_filter); 836 837 intel_de_write_dsb(display, dsb, SKL_PS_CTRL(pipe, scaler_id), 838 ps_ctrl); 839 intel_de_write_dsb(display, dsb, SKL_PS_VPHASE(pipe, scaler_id), 840 PS_Y_PHASE(y_vphase) | PS_UV_RGB_PHASE(uv_rgb_vphase)); 841 intel_de_write_dsb(display, dsb, SKL_PS_HPHASE(pipe, scaler_id), 842 PS_Y_PHASE(y_hphase) | PS_UV_RGB_PHASE(uv_rgb_hphase)); 843 intel_de_write_dsb(display, dsb, SKL_PS_WIN_POS(pipe, scaler_id), 844 PS_WIN_XPOS(crtc_x) | PS_WIN_YPOS(crtc_y)); 845 intel_de_write_dsb(display, dsb, SKL_PS_WIN_SZ(pipe, scaler_id), 846 PS_WIN_XSIZE(crtc_w) | PS_WIN_YSIZE(crtc_h)); 847 } 848 849 static void skl_detach_scaler(struct intel_dsb *dsb, 850 struct intel_crtc *crtc, int id) 851 { 852 struct intel_display *display = to_intel_display(crtc); 853 854 trace_intel_scaler_disable_arm(crtc, id); 855 856 intel_de_write_dsb(display, dsb, SKL_PS_CTRL(crtc->pipe, id), 0); 857 intel_de_write_dsb(display, dsb, SKL_PS_WIN_POS(crtc->pipe, id), 0); 858 intel_de_write_dsb(display, dsb, SKL_PS_WIN_SZ(crtc->pipe, id), 0); 859 } 860 861 /* 862 * This function detaches (aka. unbinds) unused scalers in hardware 863 */ 864 void skl_detach_scalers(struct intel_dsb *dsb, 865 const struct intel_crtc_state *crtc_state) 866 { 867 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 868 const struct intel_crtc_scaler_state *scaler_state = 869 &crtc_state->scaler_state; 870 int i; 871 872 /* loop through and disable scalers that aren't in use */ 873 for (i = 0; i < crtc->num_scalers; i++) { 874 if (!scaler_state->scalers[i].in_use) 875 skl_detach_scaler(dsb, crtc, i); 876 } 877 } 878 879 void skl_scaler_disable(const struct intel_crtc_state *old_crtc_state) 880 { 881 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); 882 int i; 883 884 for (i = 0; i < crtc->num_scalers; i++) 885 skl_detach_scaler(NULL, crtc, i); 886 } 887 888 void skl_scaler_get_config(struct intel_crtc_state *crtc_state) 889 { 890 struct intel_display *display = to_intel_display(crtc_state); 891 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 892 struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state; 893 int id = -1; 894 int i; 895 896 /* find scaler attached to this pipe */ 897 for (i = 0; i < crtc->num_scalers; i++) { 898 u32 ctl, pos, size; 899 900 ctl = intel_de_read(display, SKL_PS_CTRL(crtc->pipe, i)); 901 if ((ctl & (PS_SCALER_EN | PS_BINDING_MASK)) != (PS_SCALER_EN | PS_BINDING_PIPE)) 902 continue; 903 904 id = i; 905 crtc_state->pch_pfit.enabled = true; 906 907 pos = intel_de_read(display, SKL_PS_WIN_POS(crtc->pipe, i)); 908 size = intel_de_read(display, SKL_PS_WIN_SZ(crtc->pipe, i)); 909 910 drm_rect_init(&crtc_state->pch_pfit.dst, 911 REG_FIELD_GET(PS_WIN_XPOS_MASK, pos), 912 REG_FIELD_GET(PS_WIN_YPOS_MASK, pos), 913 REG_FIELD_GET(PS_WIN_XSIZE_MASK, size), 914 REG_FIELD_GET(PS_WIN_YSIZE_MASK, size)); 915 916 scaler_state->scalers[i].in_use = true; 917 break; 918 } 919 920 scaler_state->scaler_id = id; 921 if (id >= 0) 922 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX); 923 else 924 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX); 925 } 926