1 /* SPDX-License-Identifier: MIT */ 2 /* 3 * Copyright © 2024 Intel Corporation 4 */ 5 6 #ifndef __INTEL_VRR_REGS_H__ 7 #define __INTEL_VRR_REGS_H__ 8 9 #include "intel_display_reg_defs.h" 10 11 #define _TRANS_VRR_DCB_ADJ_FLIPLINE_CFG_A 0x604d4 12 #define _TRANS_VRR_DCB_ADJ_FLIPLINE_CFG_B 0x614d4 13 #define TRANS_VRR_DCB_ADJ_FLIPLINE_CFG(trans) _MMIO_TRANS(trans, \ 14 _TRANS_VRR_DCB_ADJ_FLIPLINE_CFG_A, \ 15 _TRANS_VRR_DCB_ADJ_FLIPLINE_CFG_B) 16 #define VRR_DCB_ADJ_FLIPLINE_CNT_MASK REG_GENMASK(31, 24) 17 #define VRR_DCB_ADJ_FLIPLINE_MASK REG_GENMASK(19, 0) 18 #define VRR_DCB_ADJ_FLIPLINE(flipline) REG_FIELD_PREP(VRR_DCB_ADJ_FLIPLINE_MASK, \ 19 (flipline)) 20 21 #define _TRANS_VRR_DCB_ADJ_FLIPLINE_CFG_LIVE_A 0x90700 22 #define _TRANS_VRR_DCB_ADJ_FLIPLINE_CFG_LIVE_B 0x98700 23 #define TRANS_VRR_DCB_ADJ_FLIPLINE_CFG_LIVE(trans) _MMIO_TRANS(trans, \ 24 _TRANS_VRR_DCB_ADJ_FLIPLINE_CFG_LIVE_A, \ 25 _TRANS_VRR_DCB_ADJ_FLIPLINE_CFG_LIVE_B) 26 27 #define _TRANS_VRR_DCB_ADJ_VMAX_CFG_A 0x604d8 28 #define _TRANS_VRR_DCB_ADJ_VMAX_CFG_B 0x614d8 29 #define TRANS_VRR_DCB_ADJ_VMAX_CFG(trans) _MMIO_TRANS(trans, \ 30 _TRANS_VRR_DCB_ADJ_VMAX_CFG_A, \ 31 _TRANS_VRR_DCB_ADJ_VMAX_CFG_B) 32 #define VRR_DCB_ADJ_VMAX_CNT_MASK REG_GENMASK(31, 24) 33 #define VRR_DCB_ADJ_VMAX_MASK REG_GENMASK(19, 0) 34 #define VRR_DCB_ADJ_VMAX(vmax) REG_FIELD_PREP(VRR_DCB_ADJ_VMAX_MASK, (vmax)) 35 36 #define _TRANS_VRR_DCB_ADJ_VMAX_CFG_LIVE_A 0x906f8 37 #define _TRANS_VRR_DCB_ADJ_VMAX_CFG_LIVE_B 0x986f8 38 #define TRANS_VRR_DCB_ADJ_VMAX_CFG_LIVE(trans) _MMIO_TRANS(trans, \ 39 _TRANS_VRR_DCB_ADJ_VMAX_CFG_LIVE_A, \ 40 _TRANS_VRR_DCB_ADJ_VMAX_CFG_LIVE_B) 41 42 #define _TRANS_VRR_DCB_FLIPLINE_A 0x60418 43 #define _TRANS_VRR_DCB_FLIPLINE_B 0x61418 44 #define TRANS_VRR_DCB_FLIPLINE(trans) _MMIO_TRANS(trans, \ 45 _TRANS_VRR_DCB_FLIPLINE_A, \ 46 _TRANS_VRR_DCB_FLIPLINE_B) 47 #define VRR_DCB_FLIPLINE_MASK REG_GENMASK(19, 0) 48 #define VRR_DCB_FLIPLINE(flipline) REG_FIELD_PREP(VRR_DCB_FLIPLINE_MASK, \ 49 (flipline)) 50 51 #define _TRANS_VRR_DCB_FLIPLINE_LIVE_A 0x906fc 52 #define _TRANS_VRR_DCB_FLIPLINE_LIVE_B 0x986fc 53 #define TRANS_VRR_DCB_FLIPLINE_LIVE(trans) _MMIO_TRANS(trans, \ 54 _TRANS_VRR_DCB_FLIPLINE_LIVE_A, \ 55 _TRANS_VRR_DCB_FLIPLINE_LIVE_B) 56 57 #define _TRANS_VRR_DCB_VMAX_A 0x60414 58 #define _TRANS_VRR_DCB_VMAX_B 0x61414 59 #define TRANS_VRR_DCB_VMAX(trans) _MMIO_TRANS(trans, \ 60 _TRANS_VRR_DCB_VMAX_A, \ 61 _TRANS_VRR_DCB_VMAX_B) 62 #define VRR_DCB_VMAX_MASK REG_GENMASK(19, 0) 63 #define VRR_DCB_VMAX(vmax) REG_FIELD_PREP(VRR_DCB_VMAX_MASK, (vmax)) 64 65 #define _TRANS_VRR_DCB_VMAX_LIVE_A 0x906f4 66 #define _TRANS_VRR_DCB_VMAX_LIVE_B 0x986f4 67 #define TRANS_VRR_DCB_VMAX_LIVE(trans) _MMIO_TRANS(trans, \ 68 _TRANS_VRR_DCB_VMAX_LIVE_A, \ 69 _TRANS_VRR_DCB_VMAX_LIVE_B) 70 71 #define _TRANS_ADAPTIVE_SYNC_DCB_CTL_A 0x604c0 72 #define _TRANS_ADAPTIVE_SYNC_DCB_CTL_B 0x614c0 73 #define TRANS_ADAPTIVE_SYNC_DCB_CTL(trans) _MMIO_TRANS(trans, \ 74 _TRANS_ADAPTIVE_SYNC_DCB_CTL_A, \ 75 _TRANS_ADAPTIVE_SYNC_DCB_CTL_B) 76 #define ADAPTIVE_SYNC_COUNTER_EN REG_BIT(31) 77 78 #define _TRANS_VRR_CTL_A 0x60420 79 #define _TRANS_VRR_CTL_B 0x61420 80 #define _TRANS_VRR_CTL_C 0x62420 81 #define _TRANS_VRR_CTL_D 0x63420 82 #define TRANS_VRR_CTL(display, trans) _MMIO_TRANS2((display), (trans), _TRANS_VRR_CTL_A) 83 #define VRR_CTL_VRR_ENABLE REG_BIT(31) 84 #define VRR_CTL_IGN_MAX_SHIFT REG_BIT(30) 85 #define VRR_CTL_FLIP_LINE_EN REG_BIT(29) 86 #define VRR_CTL_CMRR_ENABLE REG_BIT(27) 87 #define VRR_CTL_PIPELINE_FULL_MASK REG_GENMASK(10, 3) 88 #define VRR_CTL_PIPELINE_FULL(x) REG_FIELD_PREP(VRR_CTL_PIPELINE_FULL_MASK, (x)) 89 #define VRR_CTL_DCB_ADJ_ENABLE REG_BIT(28) 90 #define VRR_CTL_PIPELINE_FULL_OVERRIDE REG_BIT(0) 91 #define XELPD_VRR_CTL_VRR_GUARDBAND_MASK REG_GENMASK(15, 0) 92 #define XELPD_VRR_CTL_VRR_GUARDBAND(x) REG_FIELD_PREP(XELPD_VRR_CTL_VRR_GUARDBAND_MASK, (x)) 93 94 #define _TRANS_VRR_VMAX_A 0x60424 95 #define _TRANS_VRR_VMAX_B 0x61424 96 #define _TRANS_VRR_VMAX_C 0x62424 97 #define _TRANS_VRR_VMAX_D 0x63424 98 #define TRANS_VRR_VMAX(display, trans) _MMIO_TRANS2((display), (trans), _TRANS_VRR_VMAX_A) 99 #define VRR_VMAX_MASK REG_GENMASK(19, 0) 100 101 #define _TRANS_VRR_VMIN_A 0x60434 102 #define _TRANS_VRR_VMIN_B 0x61434 103 #define _TRANS_VRR_VMIN_C 0x62434 104 #define _TRANS_VRR_VMIN_D 0x63434 105 #define TRANS_VRR_VMIN(display, trans) _MMIO_TRANS2((display), (trans), _TRANS_VRR_VMIN_A) 106 #define VRR_VMIN_MASK REG_GENMASK(15, 0) 107 108 #define _TRANS_VRR_VMAXSHIFT_A 0x60428 109 #define _TRANS_VRR_VMAXSHIFT_B 0x61428 110 #define _TRANS_VRR_VMAXSHIFT_C 0x62428 111 #define _TRANS_VRR_VMAXSHIFT_D 0x63428 112 #define TRANS_VRR_VMAXSHIFT(display, trans) _MMIO_TRANS2((display), (trans), _TRANS_VRR_VMAXSHIFT_A) 113 #define VRR_VMAXSHIFT_DEC_MASK REG_GENMASK(29, 16) 114 #define VRR_VMAXSHIFT_DEC REG_BIT(16) 115 #define VRR_VMAXSHIFT_INC_MASK REG_GENMASK(12, 0) 116 117 #define _TRANS_VRR_STATUS_A 0x6042c 118 #define _TRANS_VRR_STATUS_B 0x6142c 119 #define _TRANS_VRR_STATUS_C 0x6242c 120 #define _TRANS_VRR_STATUS_D 0x6342c 121 #define TRANS_VRR_STATUS(display, trans) _MMIO_TRANS2((display), (trans), _TRANS_VRR_STATUS_A) 122 #define VRR_STATUS_VMAX_REACHED REG_BIT(31) 123 #define VRR_STATUS_NOFLIP_TILL_BNDR REG_BIT(30) 124 #define VRR_STATUS_FLIP_BEF_BNDR REG_BIT(29) 125 #define VRR_STATUS_NO_FLIP_FRAME REG_BIT(28) 126 #define VRR_STATUS_VRR_EN_LIVE REG_BIT(27) 127 #define VRR_STATUS_FLIPS_SERVICED REG_BIT(26) 128 #define VRR_STATUS_VBLANK_MASK REG_GENMASK(22, 20) 129 #define STATUS_FSM_IDLE REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 0) 130 #define STATUS_FSM_WAIT_TILL_FDB REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 1) 131 #define STATUS_FSM_WAIT_TILL_FS REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 2) 132 #define STATUS_FSM_WAIT_TILL_FLIP REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 3) 133 #define STATUS_FSM_PIPELINE_FILL REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 4) 134 #define STATUS_FSM_ACTIVE REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 5) 135 #define STATUS_FSM_LEGACY_VBLANK REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 6) 136 137 #define _TRANS_VRR_VTOTAL_PREV_A 0x60480 138 #define _TRANS_VRR_VTOTAL_PREV_B 0x61480 139 #define _TRANS_VRR_VTOTAL_PREV_C 0x62480 140 #define _TRANS_VRR_VTOTAL_PREV_D 0x63480 141 #define TRANS_VRR_VTOTAL_PREV(display, trans) _MMIO_TRANS2((display), (trans), _TRANS_VRR_VTOTAL_PREV_A) 142 #define VRR_VTOTAL_FLIP_BEFR_BNDR REG_BIT(31) 143 #define VRR_VTOTAL_FLIP_AFTER_BNDR REG_BIT(30) 144 #define VRR_VTOTAL_FLIP_AFTER_DBLBUF REG_BIT(29) 145 #define VRR_VTOTAL_PREV_FRAME_MASK REG_GENMASK(19, 0) 146 147 #define _TRANS_VRR_FLIPLINE_A 0x60438 148 #define _TRANS_VRR_FLIPLINE_B 0x61438 149 #define _TRANS_VRR_FLIPLINE_C 0x62438 150 #define _TRANS_VRR_FLIPLINE_D 0x63438 151 #define TRANS_VRR_FLIPLINE(display, trans) _MMIO_TRANS2((display), (trans), _TRANS_VRR_FLIPLINE_A) 152 #define VRR_FLIPLINE_MASK REG_GENMASK(19, 0) 153 154 #define _TRANS_VRR_STATUS2_A 0x6043c 155 #define _TRANS_VRR_STATUS2_B 0x6143c 156 #define _TRANS_VRR_STATUS2_C 0x6243c 157 #define _TRANS_VRR_STATUS2_D 0x6343c 158 #define TRANS_VRR_STATUS2(display, trans) _MMIO_TRANS2((display), (trans), _TRANS_VRR_STATUS2_A) 159 #define VRR_STATUS2_VERT_LN_CNT_MASK REG_GENMASK(19, 0) 160 161 #define _TRANS_PUSH_A 0x60a70 162 #define _TRANS_PUSH_B 0x61a70 163 #define _TRANS_PUSH_C 0x62a70 164 #define _TRANS_PUSH_D 0x63a70 165 #define TRANS_PUSH(display, trans) _MMIO_TRANS2((display), (trans), _TRANS_PUSH_A) 166 #define TRANS_PUSH_EN REG_BIT(31) 167 #define TRANS_PUSH_SEND REG_BIT(30) 168 169 #define _TRANS_VRR_VSYNC_A 0x60078 170 #define TRANS_VRR_VSYNC(display, trans) _MMIO_TRANS2((display), (trans), _TRANS_VRR_VSYNC_A) 171 #define VRR_VSYNC_END_MASK REG_GENMASK(28, 16) 172 #define VRR_VSYNC_END(vsync_end) REG_FIELD_PREP(VRR_VSYNC_END_MASK, (vsync_end)) 173 #define VRR_VSYNC_START_MASK REG_GENMASK(12, 0) 174 #define VRR_VSYNC_START(vsync_start) REG_FIELD_PREP(VRR_VSYNC_START_MASK, (vsync_start)) 175 176 /* Common register for HDMI EMP and DP AS SDP */ 177 #define _EMP_AS_SDP_TL_A 0x60204 178 #define EMP_AS_SDP_TL(display, trans) _MMIO_TRANS2((display), (trans), _EMP_AS_SDP_TL_A) 179 #define EMP_AS_SDP_DB_TL_MASK REG_GENMASK(12, 0) 180 #define EMP_AS_SDP_DB_TL(db_transmit_line) REG_FIELD_PREP(EMP_AS_SDP_DB_TL_MASK, (db_transmit_line)) 181 182 #define _TRANS_CMRR_M_LO_A 0x604F0 183 #define TRANS_CMRR_M_LO(display, trans) _MMIO_TRANS2((display), (trans), _TRANS_CMRR_M_LO_A) 184 185 #define _TRANS_CMRR_M_HI_A 0x604F4 186 #define TRANS_CMRR_M_HI(display, trans) _MMIO_TRANS2((display), (trans), _TRANS_CMRR_M_HI_A) 187 188 #define _TRANS_CMRR_N_LO_A 0x604F8 189 #define TRANS_CMRR_N_LO(display, trans) _MMIO_TRANS2((display), (trans), _TRANS_CMRR_N_LO_A) 190 191 #define _TRANS_CMRR_N_HI_A 0x604FC 192 #define TRANS_CMRR_N_HI(display, trans) _MMIO_TRANS2((display), (trans), _TRANS_CMRR_N_HI_A) 193 194 #endif /* __INTEL_VRR_REGS__ */ 195