1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2020 Intel Corporation 4 * 5 */ 6 7 #include "i915_drv.h" 8 #include "intel_de.h" 9 #include "intel_display_types.h" 10 #include "intel_vrr.h" 11 12 bool intel_vrr_is_capable(struct drm_connector *connector) 13 { 14 struct intel_dp *intel_dp; 15 const struct drm_display_info *info = &connector->display_info; 16 struct drm_i915_private *i915 = to_i915(connector->dev); 17 18 if (connector->connector_type != DRM_MODE_CONNECTOR_eDP && 19 connector->connector_type != DRM_MODE_CONNECTOR_DisplayPort) 20 return false; 21 22 intel_dp = intel_attached_dp(to_intel_connector(connector)); 23 /* 24 * DP Sink is capable of VRR video timings if 25 * Ignore MSA bit is set in DPCD. 26 * EDID monitor range also should be atleast 10 for reasonable 27 * Adaptive Sync or Variable Refresh Rate end user experience. 28 */ 29 return HAS_VRR(i915) && 30 drm_dp_sink_can_do_video_without_timing_msa(intel_dp->dpcd) && 31 info->monitor_range.max_vfreq - info->monitor_range.min_vfreq > 10; 32 } 33 34 void 35 intel_vrr_check_modeset(struct intel_atomic_state *state) 36 { 37 int i; 38 struct intel_crtc_state *old_crtc_state, *new_crtc_state; 39 struct intel_crtc *crtc; 40 41 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 42 new_crtc_state, i) { 43 if (new_crtc_state->uapi.vrr_enabled != 44 old_crtc_state->uapi.vrr_enabled) 45 new_crtc_state->uapi.mode_changed = true; 46 } 47 } 48 49 /* 50 * Without VRR registers get latched at: 51 * vblank_start 52 * 53 * With VRR the earliest registers can get latched is: 54 * intel_vrr_vmin_vblank_start(), which if we want to maintain 55 * the correct min vtotal is >=vblank_start+1 56 * 57 * The latest point registers can get latched is the vmax decision boundary: 58 * intel_vrr_vmax_vblank_start() 59 * 60 * Between those two points the vblank exit starts (and hence registers get 61 * latched) ASAP after a push is sent. 62 * 63 * framestart_delay is programmable 0-3. 64 */ 65 static int intel_vrr_vblank_exit_length(const struct intel_crtc_state *crtc_state) 66 { 67 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 68 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 69 70 /* The hw imposes the extra scanline before frame start */ 71 return crtc_state->vrr.pipeline_full + i915->framestart_delay + 1; 72 } 73 74 int intel_vrr_vmin_vblank_start(const struct intel_crtc_state *crtc_state) 75 { 76 /* Min vblank actually determined by flipline that is always >=vmin+1 */ 77 return crtc_state->vrr.vmin + 1 - intel_vrr_vblank_exit_length(crtc_state); 78 } 79 80 int intel_vrr_vmax_vblank_start(const struct intel_crtc_state *crtc_state) 81 { 82 return crtc_state->vrr.vmax - intel_vrr_vblank_exit_length(crtc_state); 83 } 84 85 void 86 intel_vrr_compute_config(struct intel_crtc_state *crtc_state, 87 struct drm_connector_state *conn_state) 88 { 89 struct intel_connector *connector = 90 to_intel_connector(conn_state->connector); 91 struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; 92 const struct drm_display_info *info = &connector->base.display_info; 93 int vmin, vmax; 94 95 if (!intel_vrr_is_capable(&connector->base)) 96 return; 97 98 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) 99 return; 100 101 if (!crtc_state->uapi.vrr_enabled) 102 return; 103 104 vmin = DIV_ROUND_UP(adjusted_mode->crtc_clock * 1000, 105 adjusted_mode->crtc_htotal * info->monitor_range.max_vfreq); 106 vmax = adjusted_mode->crtc_clock * 1000 / 107 (adjusted_mode->crtc_htotal * info->monitor_range.min_vfreq); 108 109 vmin = max_t(int, vmin, adjusted_mode->crtc_vtotal); 110 vmax = max_t(int, vmax, adjusted_mode->crtc_vtotal); 111 112 if (vmin >= vmax) 113 return; 114 115 /* 116 * flipline determines the min vblank length the hardware will 117 * generate, and flipline>=vmin+1, hence we reduce vmin by one 118 * to make sure we can get the actual min vblank length. 119 */ 120 crtc_state->vrr.vmin = vmin - 1; 121 crtc_state->vrr.vmax = vmax; 122 crtc_state->vrr.enable = true; 123 124 crtc_state->vrr.flipline = crtc_state->vrr.vmin + 1; 125 126 /* 127 * FIXME: s/4/framestart_delay+1/ to get consistent 128 * earliest/latest points for register latching regardless 129 * of the framestart_delay used? 130 * 131 * FIXME: this really needs the extra scanline to provide consistent 132 * behaviour for all framestart_delay values. Otherwise with 133 * framestart_delay==3 we will end up extending the min vblank by 134 * one extra line. 135 */ 136 crtc_state->vrr.pipeline_full = 137 min(255, crtc_state->vrr.vmin - adjusted_mode->crtc_vdisplay - 4 - 1); 138 139 crtc_state->mode_flags |= I915_MODE_FLAG_VRR; 140 } 141 142 void intel_vrr_enable(struct intel_encoder *encoder, 143 const struct intel_crtc_state *crtc_state) 144 { 145 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 146 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 147 u32 trans_vrr_ctl; 148 149 if (!crtc_state->vrr.enable) 150 return; 151 152 trans_vrr_ctl = VRR_CTL_VRR_ENABLE | 153 VRR_CTL_IGN_MAX_SHIFT | VRR_CTL_FLIP_LINE_EN | 154 VRR_CTL_PIPELINE_FULL(crtc_state->vrr.pipeline_full) | 155 VRR_CTL_PIPELINE_FULL_OVERRIDE; 156 157 intel_de_write(dev_priv, TRANS_VRR_VMIN(cpu_transcoder), crtc_state->vrr.vmin - 1); 158 intel_de_write(dev_priv, TRANS_VRR_VMAX(cpu_transcoder), crtc_state->vrr.vmax - 1); 159 intel_de_write(dev_priv, TRANS_VRR_CTL(cpu_transcoder), trans_vrr_ctl); 160 intel_de_write(dev_priv, TRANS_VRR_FLIPLINE(cpu_transcoder), crtc_state->vrr.flipline - 1); 161 intel_de_write(dev_priv, TRANS_PUSH(cpu_transcoder), TRANS_PUSH_EN); 162 } 163 164 void intel_vrr_send_push(const struct intel_crtc_state *crtc_state) 165 { 166 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 167 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 168 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 169 170 if (!crtc_state->vrr.enable) 171 return; 172 173 intel_de_write(dev_priv, TRANS_PUSH(cpu_transcoder), 174 TRANS_PUSH_EN | TRANS_PUSH_SEND); 175 } 176 177 void intel_vrr_disable(const struct intel_crtc_state *old_crtc_state) 178 { 179 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); 180 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 181 enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder; 182 183 if (!old_crtc_state->vrr.enable) 184 return; 185 186 intel_de_write(dev_priv, TRANS_VRR_CTL(cpu_transcoder), 0); 187 intel_de_write(dev_priv, TRANS_PUSH(cpu_transcoder), 0); 188 } 189 190 void intel_vrr_get_config(struct intel_crtc *crtc, 191 struct intel_crtc_state *crtc_state) 192 { 193 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 194 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 195 u32 trans_vrr_ctl; 196 197 trans_vrr_ctl = intel_de_read(dev_priv, TRANS_VRR_CTL(cpu_transcoder)); 198 crtc_state->vrr.enable = trans_vrr_ctl & VRR_CTL_VRR_ENABLE; 199 if (!crtc_state->vrr.enable) 200 return; 201 202 if (trans_vrr_ctl & VRR_CTL_PIPELINE_FULL_OVERRIDE) 203 crtc_state->vrr.pipeline_full = REG_FIELD_GET(VRR_CTL_PIPELINE_FULL_MASK, trans_vrr_ctl); 204 if (trans_vrr_ctl & VRR_CTL_FLIP_LINE_EN) 205 crtc_state->vrr.flipline = intel_de_read(dev_priv, TRANS_VRR_FLIPLINE(cpu_transcoder)) + 1; 206 crtc_state->vrr.vmax = intel_de_read(dev_priv, TRANS_VRR_VMAX(cpu_transcoder)) + 1; 207 crtc_state->vrr.vmin = intel_de_read(dev_priv, TRANS_VRR_VMIN(cpu_transcoder)) + 1; 208 209 crtc_state->mode_flags |= I915_MODE_FLAG_VRR; 210 } 211