1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2019 Intel Corporation 4 */ 5 6 #include <linux/delay.h> 7 #include <linux/pci.h> 8 #include <linux/vgaarb.h> 9 10 #include <drm/drm_device.h> 11 #include <drm/drm_print.h> 12 #include <drm/intel/i915_drm.h> 13 #include <video/vga.h> 14 15 #include "intel_de.h" 16 #include "intel_display.h" 17 #include "intel_display_types.h" 18 #include "intel_vga.h" 19 #include "intel_vga_regs.h" 20 21 static unsigned int intel_gmch_ctrl_reg(struct intel_display *display) 22 { 23 return DISPLAY_VER(display) >= 6 ? SNB_GMCH_CTRL : I830_GMCH_CTRL; 24 } 25 26 static bool intel_vga_decode_is_enabled(struct intel_display *display) 27 { 28 struct pci_dev *pdev = to_pci_dev(display->drm->dev); 29 u16 gmch_ctrl = 0; 30 31 if (pci_bus_read_config_word(pdev->bus, PCI_DEVFN(0, 0), 32 intel_gmch_ctrl_reg(display), &gmch_ctrl)) 33 return false; 34 35 return !(gmch_ctrl & INTEL_GMCH_VGA_DISABLE); 36 } 37 38 static i915_reg_t intel_vga_cntrl_reg(struct intel_display *display) 39 { 40 if (display->platform.valleyview || display->platform.cherryview) 41 return VLV_VGACNTRL; 42 else if (DISPLAY_VER(display) >= 5) 43 return CPU_VGACNTRL; 44 else 45 return VGACNTRL; 46 } 47 48 static bool has_vga_pipe_sel(struct intel_display *display) 49 { 50 if (display->platform.i845g || 51 display->platform.i865g) 52 return false; 53 54 if (display->platform.valleyview || 55 display->platform.cherryview) 56 return true; 57 58 return DISPLAY_VER(display) < 7; 59 } 60 61 static bool has_vga_mmio_access(struct intel_display *display) 62 { 63 /* WaEnableVGAAccessThroughIOPort:ctg+ */ 64 return DISPLAY_VER(display) < 5 && !display->platform.g4x; 65 } 66 67 static bool intel_pci_has_vga_io_decode(struct pci_dev *pdev) 68 { 69 u16 cmd = 0; 70 71 pci_read_config_word(pdev, PCI_COMMAND, &cmd); 72 if ((cmd & PCI_COMMAND_IO) == 0) 73 return false; 74 75 pdev = pdev->bus->self; 76 while (pdev) { 77 u16 ctl = 0; 78 79 pci_read_config_word(pdev, PCI_BRIDGE_CONTROL, &ctl); 80 if ((ctl & PCI_BRIDGE_CTL_VGA) == 0) 81 return false; 82 83 pdev = pdev->bus->self; 84 } 85 86 return true; 87 } 88 89 static bool intel_pci_set_io_decode(struct pci_dev *pdev, bool enable) 90 { 91 u16 old = 0, cmd; 92 93 pci_read_config_word(pdev, PCI_COMMAND, &old); 94 cmd = old & ~PCI_COMMAND_IO; 95 if (enable) 96 cmd |= PCI_COMMAND_IO; 97 pci_write_config_word(pdev, PCI_COMMAND, cmd); 98 99 return old & PCI_COMMAND_IO; 100 } 101 102 static bool intel_pci_bridge_set_vga(struct pci_dev *pdev, bool enable) 103 { 104 u16 old = 0, ctl; 105 106 pci_read_config_word(pdev->bus->self, PCI_BRIDGE_CONTROL, &old); 107 ctl = old & ~PCI_BRIDGE_CTL_VGA; 108 if (enable) 109 ctl |= PCI_BRIDGE_CTL_VGA; 110 pci_write_config_word(pdev->bus->self, PCI_BRIDGE_CONTROL, ctl); 111 112 return old & PCI_BRIDGE_CTL_VGA; 113 } 114 115 static int intel_vga_get(struct intel_display *display, bool mmio, 116 bool *old_io_decode) 117 { 118 struct pci_dev *pdev = to_pci_dev(display->drm->dev); 119 int err; 120 121 if (mmio) { 122 *old_io_decode = false; 123 return 0; 124 } 125 126 /* 127 * Bypass the VGA arbiter on the iGPU and just enable 128 * IO decode by hand. This avoids clobbering the VGA 129 * routing for an external GPU when it's the current 130 * VGA device, and thus prevents the all 0xff/white 131 * readout from VGA memory when taking over from vgacon. 132 * 133 * The iGPU has the highest VGA decode priority so it will 134 * grab any VGA IO access when IO decode is enabled, regardless 135 * of how any other VGA routing bits are configured. 136 */ 137 if (display->platform.dgfx) { 138 err = vga_get_uninterruptible(pdev, VGA_RSRC_LEGACY_IO); 139 if (err) 140 return err; 141 } 142 143 *old_io_decode = intel_pci_set_io_decode(pdev, true); 144 145 return 0; 146 } 147 148 static void intel_vga_put(struct intel_display *display, bool io_decode, bool mmio) 149 { 150 struct pci_dev *pdev = to_pci_dev(display->drm->dev); 151 152 if (mmio) 153 return; 154 155 /* see intel_vga_get() */ 156 intel_pci_set_io_decode(pdev, io_decode); 157 158 if (display->platform.dgfx) 159 vga_put(pdev, VGA_RSRC_LEGACY_IO); 160 } 161 162 u8 intel_vga_read(struct intel_display *display, u16 reg, bool mmio) 163 { 164 if (mmio) 165 return intel_de_read8(display, _MMIO(reg)); 166 else 167 return inb(reg); 168 } 169 170 static void intel_vga_write(struct intel_display *display, u16 reg, u8 val, bool mmio) 171 { 172 if (mmio) 173 intel_de_write8(display, _MMIO(reg), val); 174 else 175 outb(val, reg); 176 } 177 178 /* Disable the VGA plane that we never use */ 179 void intel_vga_disable(struct intel_display *display) 180 { 181 struct pci_dev *pdev = to_pci_dev(display->drm->dev); 182 i915_reg_t vga_reg = intel_vga_cntrl_reg(display); 183 bool mmio = has_vga_mmio_access(display); 184 bool io_decode; 185 u8 msr, sr1; 186 u32 tmp; 187 int err; 188 189 if (!intel_vga_decode_is_enabled(display)) { 190 drm_dbg_kms(display->drm, "VGA decode is disabled\n"); 191 192 /* 193 * On older hardware VGA_DISP_DISABLE defaults to 0, but 194 * it *must* be set or else the pipe will be completely 195 * stuck (at least on g4x). 196 */ 197 goto reset_vgacntr; 198 } 199 200 tmp = intel_de_read(display, vga_reg); 201 202 if ((tmp & VGA_DISP_DISABLE) == 0) { 203 enum pipe pipe; 204 205 if (display->platform.cherryview) 206 pipe = REG_FIELD_GET(VGA_PIPE_SEL_MASK_CHV, tmp); 207 else if (has_vga_pipe_sel(display)) 208 pipe = REG_FIELD_GET(VGA_PIPE_SEL_MASK, tmp); 209 else 210 pipe = PIPE_A; 211 212 drm_dbg_kms(display->drm, "Disabling VGA plane on pipe %c\n", 213 pipe_name(pipe)); 214 } else { 215 drm_dbg_kms(display->drm, "VGA plane is disabled\n"); 216 217 /* 218 * Unfortunately at least some BIOSes (eg. HSW Lenovo 219 * ThinkCentre E73) set up the VGA registers even when 220 * in UEFI mode with the VGA plane disabled. So we need to 221 * always clean up the mess for iGPUs. For discrete GPUs we 222 * don't really care about the state of the VGA registers 223 * since all VGA accesses can be blocked via the bridge. 224 */ 225 if (display->platform.dgfx) 226 goto reset_vgacntr; 227 } 228 229 /* 230 * This should not fail, because the vga_get() family of functions 231 * will only report errors for dGPUs that are unreachable via the 232 * bridge, and cannot be made reachable either. We shouldn't even 233 * get here for this case, but if we do, we assume that the bridge 234 * will also refuse future requests to forward VGA accesses. 235 */ 236 err = intel_vga_get(display, mmio, &io_decode); 237 if (err) 238 goto reset_vgacntr; 239 240 drm_WARN_ON(display->drm, !mmio && !intel_pci_has_vga_io_decode(pdev)); 241 242 intel_vga_write(display, VGA_SEQ_I, 0x01, mmio); 243 sr1 = intel_vga_read(display, VGA_SEQ_D, mmio); 244 sr1 |= VGA_SR01_SCREEN_OFF; 245 intel_vga_write(display, VGA_SEQ_D, sr1, mmio); 246 247 msr = intel_vga_read(display, VGA_MIS_R, mmio); 248 /* 249 * Always disable VGA memory decode for iGPU so that 250 * intel_vga_set_decode() doesn't need to access VGA registers. 251 * VGA_MIS_ENB_MEM_ACCESS=0 is also the reset value. 252 */ 253 msr &= ~VGA_MIS_ENB_MEM_ACCESS; 254 /* 255 * VGA_MIS_COLOR controls both GPU level and display engine level 256 * MDA vs. CGA decode logic. But when the register gets reset 257 * (reset value has VGA_MIS_COLOR=0) by the power well, only the 258 * display engine level decode logic gets notified. 259 * 260 * Switch to MDA mode to make sure the GPU level decode logic will 261 * be in sync with the display engine level decode logic after the 262 * power well has been reset. Otherwise the GPU will claim CGA 263 * register accesses but the display engine will not, causing 264 * RMbus NoClaim errors. 265 */ 266 msr &= ~VGA_MIS_COLOR; 267 intel_vga_write(display, VGA_MIS_W, msr, mmio); 268 269 intel_vga_put(display, io_decode, mmio); 270 271 /* 272 * Inform the arbiter about VGA memory decode being disabled so 273 * that it doesn't disable all memory decode for the iGPU when 274 * targeting another GPU. 275 */ 276 if (!display->platform.dgfx) 277 vga_set_legacy_decoding(pdev, VGA_RSRC_LEGACY_IO); 278 279 udelay(300); 280 281 reset_vgacntr: 282 intel_de_write(display, vga_reg, VGA_DISP_DISABLE); 283 intel_de_posting_read(display, vga_reg); 284 } 285 286 static unsigned int intel_vga_set_decode(struct pci_dev *pdev, bool enable_decode) 287 { 288 struct intel_display *display = to_intel_display(pdev); 289 unsigned int decodes = VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM; 290 291 drm_dbg_kms(display->drm, "%s VGA decode due to VGA arbitration\n", 292 str_enable_disable(enable_decode)); 293 294 /* 295 * Can't use GMCH_CTRL INTEL_GMCH_VGA_DISABLE to disable VGA 296 * decode on ILK+ since the register is locked. Instead 297 * intel_disable_vga() will disable VGA memory decode for the 298 * iGPU, and here we just need to take care of the IO decode. 299 * For discrete GPUs we rely on the bridge VGA control. 300 * 301 * We can't disable IO decode already in intel_vga_disable() 302 * because at least some laptops (eg. CTG Dell Latitude E5400) 303 * will hang during reboot/shutfown with IO decode disabled. 304 */ 305 if (display->platform.dgfx) { 306 if (!enable_decode) 307 intel_pci_bridge_set_vga(pdev, false); 308 else 309 decodes |= VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM; 310 } else { 311 if (!enable_decode) 312 intel_pci_set_io_decode(pdev, false); 313 else 314 decodes |= VGA_RSRC_LEGACY_IO; 315 } 316 317 return decodes; 318 } 319 320 void intel_vga_register(struct intel_display *display) 321 { 322 323 struct pci_dev *pdev = to_pci_dev(display->drm->dev); 324 int ret; 325 326 /* 327 * If we have > 1 VGA cards, then we need to arbitrate access to the 328 * common VGA resources. 329 * 330 * If we are a secondary display controller (!PCI_DISPLAY_CLASS_VGA), 331 * then we do not take part in VGA arbitration and the 332 * vga_client_register() fails with -ENODEV. 333 */ 334 ret = vga_client_register(pdev, intel_vga_set_decode); 335 drm_WARN_ON(display->drm, ret && ret != -ENODEV); 336 } 337 338 void intel_vga_unregister(struct intel_display *display) 339 { 340 struct pci_dev *pdev = to_pci_dev(display->drm->dev); 341 342 vga_client_unregister(pdev); 343 } 344