1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2018 Intel Corporation 4 * 5 * Author: Gaurav K Singh <gaurav.k.singh@intel.com> 6 * Manasi Navare <manasi.d.navare@intel.com> 7 */ 8 #include <linux/limits.h> 9 10 #include <drm/display/drm_dsc_helper.h> 11 12 #include "i915_drv.h" 13 #include "i915_reg.h" 14 #include "intel_crtc.h" 15 #include "intel_de.h" 16 #include "intel_display_types.h" 17 #include "intel_dsi.h" 18 #include "intel_qp_tables.h" 19 #include "intel_vdsc.h" 20 #include "intel_vdsc_regs.h" 21 22 bool intel_dsc_source_support(const struct intel_crtc_state *crtc_state) 23 { 24 const struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 25 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 26 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 27 28 if (!HAS_DSC(i915)) 29 return false; 30 31 if (DISPLAY_VER(i915) == 11 && cpu_transcoder == TRANSCODER_A) 32 return false; 33 34 return true; 35 } 36 37 static bool is_pipe_dsc(struct intel_crtc *crtc, enum transcoder cpu_transcoder) 38 { 39 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 40 41 if (DISPLAY_VER(i915) >= 12) 42 return true; 43 44 if (cpu_transcoder == TRANSCODER_EDP || 45 cpu_transcoder == TRANSCODER_DSI_0 || 46 cpu_transcoder == TRANSCODER_DSI_1) 47 return false; 48 49 /* There's no pipe A DSC engine on ICL */ 50 drm_WARN_ON(&i915->drm, crtc->pipe == PIPE_A); 51 52 return true; 53 } 54 55 static void 56 intel_vdsc_set_min_max_qp(struct drm_dsc_config *vdsc_cfg, int buf, 57 int bpp) 58 { 59 int bpc = vdsc_cfg->bits_per_component; 60 61 /* Read range_minqp and range_max_qp from qp tables */ 62 vdsc_cfg->rc_range_params[buf].range_min_qp = 63 intel_lookup_range_min_qp(bpc, buf, bpp, vdsc_cfg->native_420); 64 vdsc_cfg->rc_range_params[buf].range_max_qp = 65 intel_lookup_range_max_qp(bpc, buf, bpp, vdsc_cfg->native_420); 66 } 67 68 /* 69 * We are using the method provided in DSC 1.2a C-Model in codec_main.c 70 * Above method use a common formula to derive values for any combination of DSC 71 * variables. The formula approach may yield slight differences in the derived PPS 72 * parameters from the original parameter sets. These differences are not consequential 73 * to the coding performance because all parameter sets have been shown to produce 74 * visually lossless quality (provides the same PPS values as 75 * DSCParameterValuesVESA V1-2 spreadsheet). 76 */ 77 static void 78 calculate_rc_params(struct drm_dsc_config *vdsc_cfg) 79 { 80 int bpc = vdsc_cfg->bits_per_component; 81 int bpp = vdsc_cfg->bits_per_pixel >> 4; 82 int qp_bpc_modifier = (bpc - 8) * 2; 83 int uncompressed_bpg_rate; 84 int first_line_bpg_offset; 85 u32 res, buf_i, bpp_i; 86 87 if (vdsc_cfg->slice_height >= 8) 88 first_line_bpg_offset = 89 12 + (9 * min(34, vdsc_cfg->slice_height - 8)) / 100; 90 else 91 first_line_bpg_offset = 2 * (vdsc_cfg->slice_height - 1); 92 93 uncompressed_bpg_rate = (3 * bpc + (vdsc_cfg->convert_rgb ? 0 : 2)) * 3; 94 vdsc_cfg->first_line_bpg_offset = clamp(first_line_bpg_offset, 0, 95 uncompressed_bpg_rate - 3 * bpp); 96 97 /* 98 * According to DSC 1.2 spec in Section 4.1 if native_420 is set: 99 * -second_line_bpg_offset is 12 in general and equal to 2*(slice_height-1) if slice 100 * height < 8. 101 * -second_line_offset_adj is 512 as shown by emperical values to yield best chroma 102 * preservation in second line. 103 * -nsl_bpg_offset is calculated as second_line_offset/slice_height -1 then rounded 104 * up to 16 fractional bits, we left shift second line offset by 11 to preserve 11 105 * fractional bits. 106 */ 107 if (vdsc_cfg->native_420) { 108 if (vdsc_cfg->slice_height >= 8) 109 vdsc_cfg->second_line_bpg_offset = 12; 110 else 111 vdsc_cfg->second_line_bpg_offset = 112 2 * (vdsc_cfg->slice_height - 1); 113 114 vdsc_cfg->second_line_offset_adj = 512; 115 vdsc_cfg->nsl_bpg_offset = DIV_ROUND_UP(vdsc_cfg->second_line_bpg_offset << 11, 116 vdsc_cfg->slice_height - 1); 117 } 118 119 /* Our hw supports only 444 modes as of today */ 120 if (bpp >= 12) 121 vdsc_cfg->initial_offset = 2048; 122 else if (bpp >= 10) 123 vdsc_cfg->initial_offset = 5632 - DIV_ROUND_UP(((bpp - 10) * 3584), 2); 124 else if (bpp >= 8) 125 vdsc_cfg->initial_offset = 6144 - DIV_ROUND_UP(((bpp - 8) * 512), 2); 126 else 127 vdsc_cfg->initial_offset = 6144; 128 129 /* initial_xmit_delay = rc_model_size/2/compression_bpp */ 130 vdsc_cfg->initial_xmit_delay = DIV_ROUND_UP(DSC_RC_MODEL_SIZE_CONST, 2 * bpp); 131 132 vdsc_cfg->flatness_min_qp = 3 + qp_bpc_modifier; 133 vdsc_cfg->flatness_max_qp = 12 + qp_bpc_modifier; 134 135 vdsc_cfg->rc_quant_incr_limit0 = 11 + qp_bpc_modifier; 136 vdsc_cfg->rc_quant_incr_limit1 = 11 + qp_bpc_modifier; 137 138 if (vdsc_cfg->native_420) { 139 static const s8 ofs_und4[] = { 140 2, 0, 0, -2, -4, -6, -8, -8, -8, -10, -10, -12, -12, -12, -12 141 }; 142 static const s8 ofs_und5[] = { 143 2, 0, 0, -2, -4, -6, -8, -8, -8, -10, -10, -10, -12, -12, -12 144 }; 145 static const s8 ofs_und6[] = { 146 2, 0, 0, -2, -4, -6, -8, -8, -8, -10, -10, -10, -12, -12, -12 147 }; 148 static const s8 ofs_und8[] = { 149 10, 8, 6, 4, 2, 0, -2, -4, -6, -8, -10, -10, -12, -12, -12 150 }; 151 152 bpp_i = bpp - 8; 153 for (buf_i = 0; buf_i < DSC_NUM_BUF_RANGES; buf_i++) { 154 u8 range_bpg_offset; 155 156 intel_vdsc_set_min_max_qp(vdsc_cfg, buf_i, bpp_i); 157 158 /* Calculate range_bpg_offset */ 159 if (bpp <= 8) { 160 range_bpg_offset = ofs_und4[buf_i]; 161 } else if (bpp <= 10) { 162 res = DIV_ROUND_UP(((bpp - 8) * 163 (ofs_und5[buf_i] - ofs_und4[buf_i])), 2); 164 range_bpg_offset = ofs_und4[buf_i] + res; 165 } else if (bpp <= 12) { 166 res = DIV_ROUND_UP(((bpp - 10) * 167 (ofs_und6[buf_i] - ofs_und5[buf_i])), 2); 168 range_bpg_offset = ofs_und5[buf_i] + res; 169 } else if (bpp <= 16) { 170 res = DIV_ROUND_UP(((bpp - 12) * 171 (ofs_und8[buf_i] - ofs_und6[buf_i])), 4); 172 range_bpg_offset = ofs_und6[buf_i] + res; 173 } else { 174 range_bpg_offset = ofs_und8[buf_i]; 175 } 176 177 vdsc_cfg->rc_range_params[buf_i].range_bpg_offset = 178 range_bpg_offset & DSC_RANGE_BPG_OFFSET_MASK; 179 } 180 } else { 181 static const s8 ofs_und6[] = { 182 0, -2, -2, -4, -6, -6, -8, -8, -8, -10, -10, -12, -12, -12, -12 183 }; 184 static const s8 ofs_und8[] = { 185 2, 0, 0, -2, -4, -6, -8, -8, -8, -10, -10, -10, -12, -12, -12 186 }; 187 static const s8 ofs_und12[] = { 188 2, 0, 0, -2, -4, -6, -8, -8, -8, -10, -10, -10, -12, -12, -12 189 }; 190 static const s8 ofs_und15[] = { 191 10, 8, 6, 4, 2, 0, -2, -4, -6, -8, -10, -10, -12, -12, -12 192 }; 193 194 bpp_i = (2 * (bpp - 6)); 195 for (buf_i = 0; buf_i < DSC_NUM_BUF_RANGES; buf_i++) { 196 u8 range_bpg_offset; 197 198 intel_vdsc_set_min_max_qp(vdsc_cfg, buf_i, bpp_i); 199 200 /* Calculate range_bpg_offset */ 201 if (bpp <= 6) { 202 range_bpg_offset = ofs_und6[buf_i]; 203 } else if (bpp <= 8) { 204 res = DIV_ROUND_UP(((bpp - 6) * 205 (ofs_und8[buf_i] - ofs_und6[buf_i])), 2); 206 range_bpg_offset = ofs_und6[buf_i] + res; 207 } else if (bpp <= 12) { 208 range_bpg_offset = ofs_und8[buf_i]; 209 } else if (bpp <= 15) { 210 res = DIV_ROUND_UP(((bpp - 12) * 211 (ofs_und15[buf_i] - ofs_und12[buf_i])), 3); 212 range_bpg_offset = ofs_und12[buf_i] + res; 213 } else { 214 range_bpg_offset = ofs_und15[buf_i]; 215 } 216 217 vdsc_cfg->rc_range_params[buf_i].range_bpg_offset = 218 range_bpg_offset & DSC_RANGE_BPG_OFFSET_MASK; 219 } 220 } 221 } 222 223 static int intel_dsc_slice_dimensions_valid(struct intel_crtc_state *pipe_config, 224 struct drm_dsc_config *vdsc_cfg) 225 { 226 if (pipe_config->output_format == INTEL_OUTPUT_FORMAT_RGB || 227 pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR444) { 228 if (vdsc_cfg->slice_height > 4095) 229 return -EINVAL; 230 if (vdsc_cfg->slice_height * vdsc_cfg->slice_width < 15000) 231 return -EINVAL; 232 } else if (pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) { 233 if (vdsc_cfg->slice_width % 2) 234 return -EINVAL; 235 if (vdsc_cfg->slice_height % 2) 236 return -EINVAL; 237 if (vdsc_cfg->slice_height > 4094) 238 return -EINVAL; 239 if (vdsc_cfg->slice_height * vdsc_cfg->slice_width < 30000) 240 return -EINVAL; 241 } 242 243 return 0; 244 } 245 246 int intel_dsc_compute_params(struct intel_crtc_state *pipe_config) 247 { 248 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 249 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 250 struct drm_dsc_config *vdsc_cfg = &pipe_config->dsc.config; 251 u16 compressed_bpp = pipe_config->dsc.compressed_bpp; 252 int err; 253 int ret; 254 255 vdsc_cfg->pic_width = pipe_config->hw.adjusted_mode.crtc_hdisplay; 256 vdsc_cfg->slice_width = DIV_ROUND_UP(vdsc_cfg->pic_width, 257 pipe_config->dsc.slice_count); 258 259 err = intel_dsc_slice_dimensions_valid(pipe_config, vdsc_cfg); 260 261 if (err) { 262 drm_dbg_kms(&dev_priv->drm, "Slice dimension requirements not met\n"); 263 return err; 264 } 265 266 /* 267 * According to DSC 1.2 specs if colorspace is YCbCr then convert_rgb is 0 268 * else 1 269 */ 270 vdsc_cfg->convert_rgb = pipe_config->output_format != INTEL_OUTPUT_FORMAT_YCBCR420 && 271 pipe_config->output_format != INTEL_OUTPUT_FORMAT_YCBCR444; 272 273 if (DISPLAY_VER(dev_priv) >= 14 && 274 pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) 275 vdsc_cfg->native_420 = true; 276 /* We do not support YcBCr422 as of now */ 277 vdsc_cfg->native_422 = false; 278 vdsc_cfg->simple_422 = false; 279 /* Gen 11 does not support VBR */ 280 vdsc_cfg->vbr_enable = false; 281 282 /* Gen 11 only supports integral values of bpp */ 283 vdsc_cfg->bits_per_pixel = compressed_bpp << 4; 284 285 /* 286 * According to DSC 1.2 specs in Section 4.1 if native_420 is set 287 * we need to double the current bpp. 288 */ 289 if (vdsc_cfg->native_420) 290 vdsc_cfg->bits_per_pixel <<= 1; 291 292 vdsc_cfg->bits_per_component = pipe_config->pipe_bpp / 3; 293 294 drm_dsc_set_rc_buf_thresh(vdsc_cfg); 295 296 /* 297 * From XE_LPD onwards we supports compression bpps in steps of 1 298 * upto uncompressed bpp-1, hence add calculations for all the rc 299 * parameters 300 */ 301 if (DISPLAY_VER(dev_priv) >= 13) { 302 calculate_rc_params(vdsc_cfg); 303 } else { 304 if ((compressed_bpp == 8 || 305 compressed_bpp == 12) && 306 (vdsc_cfg->bits_per_component == 8 || 307 vdsc_cfg->bits_per_component == 10 || 308 vdsc_cfg->bits_per_component == 12)) 309 ret = drm_dsc_setup_rc_params(vdsc_cfg, DRM_DSC_1_1_PRE_SCR); 310 else 311 ret = drm_dsc_setup_rc_params(vdsc_cfg, DRM_DSC_1_2_444); 312 313 if (ret) 314 return ret; 315 } 316 317 /* 318 * BitsPerComponent value determines mux_word_size: 319 * When BitsPerComponent is less than or 10bpc, muxWordSize will be equal to 320 * 48 bits otherwise 64 321 */ 322 if (vdsc_cfg->bits_per_component <= 10) 323 vdsc_cfg->mux_word_size = DSC_MUX_WORD_SIZE_8_10_BPC; 324 else 325 vdsc_cfg->mux_word_size = DSC_MUX_WORD_SIZE_12_BPC; 326 327 /* InitialScaleValue is a 6 bit value with 3 fractional bits (U3.3) */ 328 vdsc_cfg->initial_scale_value = (vdsc_cfg->rc_model_size << 3) / 329 (vdsc_cfg->rc_model_size - vdsc_cfg->initial_offset); 330 331 return 0; 332 } 333 334 enum intel_display_power_domain 335 intel_dsc_power_domain(struct intel_crtc *crtc, enum transcoder cpu_transcoder) 336 { 337 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 338 enum pipe pipe = crtc->pipe; 339 340 /* 341 * VDSC/joining uses a separate power well, PW2, and requires 342 * POWER_DOMAIN_TRANSCODER_VDSC_PW2 power domain in two cases: 343 * 344 * - ICL eDP/DSI transcoder 345 * - Display version 12 (except RKL) pipe A 346 * 347 * For any other pipe, VDSC/joining uses the power well associated with 348 * the pipe in use. Hence another reference on the pipe power domain 349 * will suffice. (Except no VDSC/joining on ICL pipe A.) 350 */ 351 if (DISPLAY_VER(i915) == 12 && !IS_ROCKETLAKE(i915) && pipe == PIPE_A) 352 return POWER_DOMAIN_TRANSCODER_VDSC_PW2; 353 else if (is_pipe_dsc(crtc, cpu_transcoder)) 354 return POWER_DOMAIN_PIPE(pipe); 355 else 356 return POWER_DOMAIN_TRANSCODER_VDSC_PW2; 357 } 358 359 static int intel_dsc_get_vdsc_per_pipe(const struct intel_crtc_state *crtc_state) 360 { 361 return crtc_state->dsc.dsc_split ? 2 : 1; 362 } 363 364 int intel_dsc_get_num_vdsc_instances(const struct intel_crtc_state *crtc_state) 365 { 366 int num_vdsc_instances = intel_dsc_get_vdsc_per_pipe(crtc_state); 367 368 if (crtc_state->bigjoiner_pipes) 369 num_vdsc_instances *= 2; 370 371 return num_vdsc_instances; 372 } 373 374 static void intel_dsc_get_pps_reg(const struct intel_crtc_state *crtc_state, int pps, 375 i915_reg_t *dsc_reg, int dsc_reg_num) 376 { 377 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 378 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 379 enum pipe pipe = crtc->pipe; 380 bool pipe_dsc; 381 382 pipe_dsc = is_pipe_dsc(crtc, cpu_transcoder); 383 384 if (dsc_reg_num >= 3) 385 MISSING_CASE(dsc_reg_num); 386 if (dsc_reg_num >= 2) 387 dsc_reg[1] = pipe_dsc ? ICL_DSC1_PPS(pipe, pps) : DSCC_PPS(pps); 388 if (dsc_reg_num >= 1) 389 dsc_reg[0] = pipe_dsc ? ICL_DSC0_PPS(pipe, pps) : DSCA_PPS(pps); 390 } 391 392 static void intel_dsc_pps_write(const struct intel_crtc_state *crtc_state, 393 int pps, u32 pps_val) 394 { 395 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 396 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 397 i915_reg_t dsc_reg[2]; 398 int i, vdsc_per_pipe, dsc_reg_num; 399 400 vdsc_per_pipe = intel_dsc_get_vdsc_per_pipe(crtc_state); 401 dsc_reg_num = min_t(int, ARRAY_SIZE(dsc_reg), vdsc_per_pipe); 402 403 drm_WARN_ON_ONCE(&i915->drm, dsc_reg_num < vdsc_per_pipe); 404 405 intel_dsc_get_pps_reg(crtc_state, pps, dsc_reg, dsc_reg_num); 406 407 for (i = 0; i < dsc_reg_num; i++) 408 intel_de_write(i915, dsc_reg[i], pps_val); 409 } 410 411 static void intel_dsc_pps_configure(const struct intel_crtc_state *crtc_state) 412 { 413 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 414 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 415 const struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config; 416 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 417 enum pipe pipe = crtc->pipe; 418 u32 pps_val; 419 u32 rc_buf_thresh_dword[4]; 420 u32 rc_range_params_dword[8]; 421 int i = 0; 422 int num_vdsc_instances = intel_dsc_get_num_vdsc_instances(crtc_state); 423 int vdsc_instances_per_pipe = intel_dsc_get_vdsc_per_pipe(crtc_state); 424 425 /* PPS 0 */ 426 pps_val = DSC_PPS0_VER_MAJOR(1) | 427 DSC_PPS0_VER_MINOR(vdsc_cfg->dsc_version_minor) | 428 DSC_PPS0_BPC(vdsc_cfg->bits_per_component) | 429 DSC_PPS0_LINE_BUF_DEPTH(vdsc_cfg->line_buf_depth); 430 if (vdsc_cfg->dsc_version_minor == 2) { 431 pps_val |= DSC_PPS0_ALT_ICH_SEL; 432 if (vdsc_cfg->native_420) 433 pps_val |= DSC_PPS0_NATIVE_420_ENABLE; 434 if (vdsc_cfg->native_422) 435 pps_val |= DSC_PPS0_NATIVE_422_ENABLE; 436 } 437 if (vdsc_cfg->block_pred_enable) 438 pps_val |= DSC_PPS0_BLOCK_PREDICTION; 439 if (vdsc_cfg->convert_rgb) 440 pps_val |= DSC_PPS0_COLOR_SPACE_CONVERSION; 441 if (vdsc_cfg->simple_422) 442 pps_val |= DSC_PPS0_422_ENABLE; 443 if (vdsc_cfg->vbr_enable) 444 pps_val |= DSC_PPS0_VBR_ENABLE; 445 drm_dbg_kms(&dev_priv->drm, "PPS0 = 0x%08x\n", pps_val); 446 intel_dsc_pps_write(crtc_state, 0, pps_val); 447 448 /* PPS 1 */ 449 pps_val = DSC_PPS1_BPP(vdsc_cfg->bits_per_pixel); 450 drm_dbg_kms(&dev_priv->drm, "PPS1 = 0x%08x\n", pps_val); 451 intel_dsc_pps_write(crtc_state, 1, pps_val); 452 453 /* PPS 2 */ 454 pps_val = DSC_PPS2_PIC_HEIGHT(vdsc_cfg->pic_height) | 455 DSC_PPS2_PIC_WIDTH(vdsc_cfg->pic_width / num_vdsc_instances); 456 drm_dbg_kms(&dev_priv->drm, "PPS2 = 0x%08x\n", pps_val); 457 intel_dsc_pps_write(crtc_state, 2, pps_val); 458 459 /* PPS 3 */ 460 pps_val = DSC_PPS3_SLICE_HEIGHT(vdsc_cfg->slice_height) | 461 DSC_PPS3_SLICE_WIDTH(vdsc_cfg->slice_width); 462 drm_dbg_kms(&dev_priv->drm, "PPS3 = 0x%08x\n", pps_val); 463 intel_dsc_pps_write(crtc_state, 3, pps_val); 464 465 /* PPS 4 */ 466 pps_val = DSC_PPS4_INITIAL_XMIT_DELAY(vdsc_cfg->initial_xmit_delay) | 467 DSC_PPS4_INITIAL_DEC_DELAY(vdsc_cfg->initial_dec_delay); 468 drm_dbg_kms(&dev_priv->drm, "PPS4 = 0x%08x\n", pps_val); 469 intel_dsc_pps_write(crtc_state, 4, pps_val); 470 471 /* PPS 5 */ 472 pps_val = DSC_PPS5_SCALE_INC_INT(vdsc_cfg->scale_increment_interval) | 473 DSC_PPS5_SCALE_DEC_INT(vdsc_cfg->scale_decrement_interval); 474 drm_dbg_kms(&dev_priv->drm, "PPS5 = 0x%08x\n", pps_val); 475 intel_dsc_pps_write(crtc_state, 5, pps_val); 476 477 /* PPS 6 */ 478 pps_val = DSC_PPS6_INITIAL_SCALE_VALUE(vdsc_cfg->initial_scale_value) | 479 DSC_PPS6_FIRST_LINE_BPG_OFFSET(vdsc_cfg->first_line_bpg_offset) | 480 DSC_PPS6_FLATNESS_MIN_QP(vdsc_cfg->flatness_min_qp) | 481 DSC_PPS6_FLATNESS_MAX_QP(vdsc_cfg->flatness_max_qp); 482 drm_dbg_kms(&dev_priv->drm, "PPS6 = 0x%08x\n", pps_val); 483 intel_dsc_pps_write(crtc_state, 6, pps_val); 484 485 /* PPS 7 */ 486 pps_val = DSC_PPS7_SLICE_BPG_OFFSET(vdsc_cfg->slice_bpg_offset) | 487 DSC_PPS7_NFL_BPG_OFFSET(vdsc_cfg->nfl_bpg_offset); 488 drm_dbg_kms(&dev_priv->drm, "PPS7 = 0x%08x\n", pps_val); 489 intel_dsc_pps_write(crtc_state, 7, pps_val); 490 491 /* PPS 8 */ 492 pps_val = DSC_PPS8_FINAL_OFFSET(vdsc_cfg->final_offset) | 493 DSC_PPS8_INITIAL_OFFSET(vdsc_cfg->initial_offset); 494 drm_dbg_kms(&dev_priv->drm, "PPS8 = 0x%08x\n", pps_val); 495 intel_dsc_pps_write(crtc_state, 8, pps_val); 496 497 /* PPS 9 */ 498 pps_val = DSC_PPS9_RC_MODEL_SIZE(vdsc_cfg->rc_model_size) | 499 DSC_PPS9_RC_EDGE_FACTOR(DSC_RC_EDGE_FACTOR_CONST); 500 drm_dbg_kms(&dev_priv->drm, "PPS9 = 0x%08x\n", pps_val); 501 intel_dsc_pps_write(crtc_state, 9, pps_val); 502 503 /* PPS 10 */ 504 pps_val = DSC_PPS10_RC_QUANT_INC_LIMIT0(vdsc_cfg->rc_quant_incr_limit0) | 505 DSC_PPS10_RC_QUANT_INC_LIMIT1(vdsc_cfg->rc_quant_incr_limit1) | 506 DSC_PPS10_RC_TARGET_OFF_HIGH(DSC_RC_TGT_OFFSET_HI_CONST) | 507 DSC_PPS10_RC_TARGET_OFF_LOW(DSC_RC_TGT_OFFSET_LO_CONST); 508 drm_dbg_kms(&dev_priv->drm, "PPS10 = 0x%08x\n", pps_val); 509 intel_dsc_pps_write(crtc_state, 10, pps_val); 510 511 /* PPS 16 */ 512 pps_val = DSC_PPS16_SLICE_CHUNK_SIZE(vdsc_cfg->slice_chunk_size) | 513 DSC_PPS16_SLICE_PER_LINE((vdsc_cfg->pic_width / num_vdsc_instances) / 514 vdsc_cfg->slice_width) | 515 DSC_PPS16_SLICE_ROW_PER_FRAME(vdsc_cfg->pic_height / 516 vdsc_cfg->slice_height); 517 drm_dbg_kms(&dev_priv->drm, "PPS16 = 0x%08x\n", pps_val); 518 intel_dsc_pps_write(crtc_state, 16, pps_val); 519 520 if (DISPLAY_VER(dev_priv) >= 14) { 521 /* PPS 17 */ 522 pps_val = DSC_PPS17_SL_BPG_OFFSET(vdsc_cfg->second_line_bpg_offset); 523 drm_dbg_kms(&dev_priv->drm, "PPS17 = 0x%08x\n", pps_val); 524 intel_dsc_pps_write(crtc_state, 17, pps_val); 525 526 /* PPS 18 */ 527 pps_val = DSC_PPS18_NSL_BPG_OFFSET(vdsc_cfg->nsl_bpg_offset) | 528 DSC_PPS18_SL_OFFSET_ADJ(vdsc_cfg->second_line_offset_adj); 529 drm_dbg_kms(&dev_priv->drm, "PPS18 = 0x%08x\n", pps_val); 530 intel_dsc_pps_write(crtc_state, 18, pps_val); 531 } 532 533 /* Populate the RC_BUF_THRESH registers */ 534 memset(rc_buf_thresh_dword, 0, sizeof(rc_buf_thresh_dword)); 535 for (i = 0; i < DSC_NUM_BUF_RANGES - 1; i++) { 536 rc_buf_thresh_dword[i / 4] |= 537 (u32)(vdsc_cfg->rc_buf_thresh[i] << 538 BITS_PER_BYTE * (i % 4)); 539 drm_dbg_kms(&dev_priv->drm, "RC_BUF_THRESH_%d = 0x%08x\n", i, 540 rc_buf_thresh_dword[i / 4]); 541 } 542 if (!is_pipe_dsc(crtc, cpu_transcoder)) { 543 intel_de_write(dev_priv, DSCA_RC_BUF_THRESH_0, 544 rc_buf_thresh_dword[0]); 545 intel_de_write(dev_priv, DSCA_RC_BUF_THRESH_0_UDW, 546 rc_buf_thresh_dword[1]); 547 intel_de_write(dev_priv, DSCA_RC_BUF_THRESH_1, 548 rc_buf_thresh_dword[2]); 549 intel_de_write(dev_priv, DSCA_RC_BUF_THRESH_1_UDW, 550 rc_buf_thresh_dword[3]); 551 if (vdsc_instances_per_pipe > 1) { 552 intel_de_write(dev_priv, DSCC_RC_BUF_THRESH_0, 553 rc_buf_thresh_dword[0]); 554 intel_de_write(dev_priv, DSCC_RC_BUF_THRESH_0_UDW, 555 rc_buf_thresh_dword[1]); 556 intel_de_write(dev_priv, DSCC_RC_BUF_THRESH_1, 557 rc_buf_thresh_dword[2]); 558 intel_de_write(dev_priv, DSCC_RC_BUF_THRESH_1_UDW, 559 rc_buf_thresh_dword[3]); 560 } 561 } else { 562 intel_de_write(dev_priv, ICL_DSC0_RC_BUF_THRESH_0(pipe), 563 rc_buf_thresh_dword[0]); 564 intel_de_write(dev_priv, ICL_DSC0_RC_BUF_THRESH_0_UDW(pipe), 565 rc_buf_thresh_dword[1]); 566 intel_de_write(dev_priv, ICL_DSC0_RC_BUF_THRESH_1(pipe), 567 rc_buf_thresh_dword[2]); 568 intel_de_write(dev_priv, ICL_DSC0_RC_BUF_THRESH_1_UDW(pipe), 569 rc_buf_thresh_dword[3]); 570 if (vdsc_instances_per_pipe > 1) { 571 intel_de_write(dev_priv, 572 ICL_DSC1_RC_BUF_THRESH_0(pipe), 573 rc_buf_thresh_dword[0]); 574 intel_de_write(dev_priv, 575 ICL_DSC1_RC_BUF_THRESH_0_UDW(pipe), 576 rc_buf_thresh_dword[1]); 577 intel_de_write(dev_priv, 578 ICL_DSC1_RC_BUF_THRESH_1(pipe), 579 rc_buf_thresh_dword[2]); 580 intel_de_write(dev_priv, 581 ICL_DSC1_RC_BUF_THRESH_1_UDW(pipe), 582 rc_buf_thresh_dword[3]); 583 } 584 } 585 586 /* Populate the RC_RANGE_PARAMETERS registers */ 587 memset(rc_range_params_dword, 0, sizeof(rc_range_params_dword)); 588 for (i = 0; i < DSC_NUM_BUF_RANGES; i++) { 589 rc_range_params_dword[i / 2] |= 590 (u32)(((vdsc_cfg->rc_range_params[i].range_bpg_offset << 591 RC_BPG_OFFSET_SHIFT) | 592 (vdsc_cfg->rc_range_params[i].range_max_qp << 593 RC_MAX_QP_SHIFT) | 594 (vdsc_cfg->rc_range_params[i].range_min_qp << 595 RC_MIN_QP_SHIFT)) << 16 * (i % 2)); 596 drm_dbg_kms(&dev_priv->drm, "RC_RANGE_PARAM_%d = 0x%08x\n", i, 597 rc_range_params_dword[i / 2]); 598 } 599 if (!is_pipe_dsc(crtc, cpu_transcoder)) { 600 intel_de_write(dev_priv, DSCA_RC_RANGE_PARAMETERS_0, 601 rc_range_params_dword[0]); 602 intel_de_write(dev_priv, DSCA_RC_RANGE_PARAMETERS_0_UDW, 603 rc_range_params_dword[1]); 604 intel_de_write(dev_priv, DSCA_RC_RANGE_PARAMETERS_1, 605 rc_range_params_dword[2]); 606 intel_de_write(dev_priv, DSCA_RC_RANGE_PARAMETERS_1_UDW, 607 rc_range_params_dword[3]); 608 intel_de_write(dev_priv, DSCA_RC_RANGE_PARAMETERS_2, 609 rc_range_params_dword[4]); 610 intel_de_write(dev_priv, DSCA_RC_RANGE_PARAMETERS_2_UDW, 611 rc_range_params_dword[5]); 612 intel_de_write(dev_priv, DSCA_RC_RANGE_PARAMETERS_3, 613 rc_range_params_dword[6]); 614 intel_de_write(dev_priv, DSCA_RC_RANGE_PARAMETERS_3_UDW, 615 rc_range_params_dword[7]); 616 if (vdsc_instances_per_pipe > 1) { 617 intel_de_write(dev_priv, DSCC_RC_RANGE_PARAMETERS_0, 618 rc_range_params_dword[0]); 619 intel_de_write(dev_priv, 620 DSCC_RC_RANGE_PARAMETERS_0_UDW, 621 rc_range_params_dword[1]); 622 intel_de_write(dev_priv, DSCC_RC_RANGE_PARAMETERS_1, 623 rc_range_params_dword[2]); 624 intel_de_write(dev_priv, 625 DSCC_RC_RANGE_PARAMETERS_1_UDW, 626 rc_range_params_dword[3]); 627 intel_de_write(dev_priv, DSCC_RC_RANGE_PARAMETERS_2, 628 rc_range_params_dword[4]); 629 intel_de_write(dev_priv, 630 DSCC_RC_RANGE_PARAMETERS_2_UDW, 631 rc_range_params_dword[5]); 632 intel_de_write(dev_priv, DSCC_RC_RANGE_PARAMETERS_3, 633 rc_range_params_dword[6]); 634 intel_de_write(dev_priv, 635 DSCC_RC_RANGE_PARAMETERS_3_UDW, 636 rc_range_params_dword[7]); 637 } 638 } else { 639 intel_de_write(dev_priv, ICL_DSC0_RC_RANGE_PARAMETERS_0(pipe), 640 rc_range_params_dword[0]); 641 intel_de_write(dev_priv, 642 ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW(pipe), 643 rc_range_params_dword[1]); 644 intel_de_write(dev_priv, ICL_DSC0_RC_RANGE_PARAMETERS_1(pipe), 645 rc_range_params_dword[2]); 646 intel_de_write(dev_priv, 647 ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW(pipe), 648 rc_range_params_dword[3]); 649 intel_de_write(dev_priv, ICL_DSC0_RC_RANGE_PARAMETERS_2(pipe), 650 rc_range_params_dword[4]); 651 intel_de_write(dev_priv, 652 ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW(pipe), 653 rc_range_params_dword[5]); 654 intel_de_write(dev_priv, ICL_DSC0_RC_RANGE_PARAMETERS_3(pipe), 655 rc_range_params_dword[6]); 656 intel_de_write(dev_priv, 657 ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW(pipe), 658 rc_range_params_dword[7]); 659 if (vdsc_instances_per_pipe > 1) { 660 intel_de_write(dev_priv, 661 ICL_DSC1_RC_RANGE_PARAMETERS_0(pipe), 662 rc_range_params_dword[0]); 663 intel_de_write(dev_priv, 664 ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW(pipe), 665 rc_range_params_dword[1]); 666 intel_de_write(dev_priv, 667 ICL_DSC1_RC_RANGE_PARAMETERS_1(pipe), 668 rc_range_params_dword[2]); 669 intel_de_write(dev_priv, 670 ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW(pipe), 671 rc_range_params_dword[3]); 672 intel_de_write(dev_priv, 673 ICL_DSC1_RC_RANGE_PARAMETERS_2(pipe), 674 rc_range_params_dword[4]); 675 intel_de_write(dev_priv, 676 ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW(pipe), 677 rc_range_params_dword[5]); 678 intel_de_write(dev_priv, 679 ICL_DSC1_RC_RANGE_PARAMETERS_3(pipe), 680 rc_range_params_dword[6]); 681 intel_de_write(dev_priv, 682 ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW(pipe), 683 rc_range_params_dword[7]); 684 } 685 } 686 } 687 688 void intel_dsc_dsi_pps_write(struct intel_encoder *encoder, 689 const struct intel_crtc_state *crtc_state) 690 { 691 const struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config; 692 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 693 struct mipi_dsi_device *dsi; 694 struct drm_dsc_picture_parameter_set pps; 695 enum port port; 696 697 if (!crtc_state->dsc.compression_enable) 698 return; 699 700 drm_dsc_pps_payload_pack(&pps, vdsc_cfg); 701 702 for_each_dsi_port(port, intel_dsi->ports) { 703 dsi = intel_dsi->dsi_hosts[port]->device; 704 705 mipi_dsi_picture_parameter_set(dsi, &pps); 706 mipi_dsi_compression_mode(dsi, true); 707 } 708 } 709 710 void intel_dsc_dp_pps_write(struct intel_encoder *encoder, 711 const struct intel_crtc_state *crtc_state) 712 { 713 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 714 const struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config; 715 struct drm_dsc_pps_infoframe dp_dsc_pps_sdp; 716 717 if (!crtc_state->dsc.compression_enable) 718 return; 719 720 /* Prepare DP SDP PPS header as per DP 1.4 spec, Table 2-123 */ 721 drm_dsc_dp_pps_header_init(&dp_dsc_pps_sdp.pps_header); 722 723 /* Fill the PPS payload bytes as per DSC spec 1.2 Table 4-1 */ 724 drm_dsc_pps_payload_pack(&dp_dsc_pps_sdp.pps_payload, vdsc_cfg); 725 726 dig_port->write_infoframe(encoder, crtc_state, 727 DP_SDP_PPS, &dp_dsc_pps_sdp, 728 sizeof(dp_dsc_pps_sdp)); 729 } 730 731 static i915_reg_t dss_ctl1_reg(struct intel_crtc *crtc, enum transcoder cpu_transcoder) 732 { 733 return is_pipe_dsc(crtc, cpu_transcoder) ? 734 ICL_PIPE_DSS_CTL1(crtc->pipe) : DSS_CTL1; 735 } 736 737 static i915_reg_t dss_ctl2_reg(struct intel_crtc *crtc, enum transcoder cpu_transcoder) 738 { 739 return is_pipe_dsc(crtc, cpu_transcoder) ? 740 ICL_PIPE_DSS_CTL2(crtc->pipe) : DSS_CTL2; 741 } 742 743 void intel_uncompressed_joiner_enable(const struct intel_crtc_state *crtc_state) 744 { 745 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 746 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 747 u32 dss_ctl1_val = 0; 748 749 if (crtc_state->bigjoiner_pipes && !crtc_state->dsc.compression_enable) { 750 if (intel_crtc_is_bigjoiner_slave(crtc_state)) 751 dss_ctl1_val |= UNCOMPRESSED_JOINER_SLAVE; 752 else 753 dss_ctl1_val |= UNCOMPRESSED_JOINER_MASTER; 754 755 intel_de_write(dev_priv, dss_ctl1_reg(crtc, crtc_state->cpu_transcoder), dss_ctl1_val); 756 } 757 } 758 759 void intel_dsc_enable(const struct intel_crtc_state *crtc_state) 760 { 761 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 762 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 763 u32 dss_ctl1_val = 0; 764 u32 dss_ctl2_val = 0; 765 int vdsc_instances_per_pipe = intel_dsc_get_vdsc_per_pipe(crtc_state); 766 767 if (!crtc_state->dsc.compression_enable) 768 return; 769 770 intel_dsc_pps_configure(crtc_state); 771 772 dss_ctl2_val |= LEFT_BRANCH_VDSC_ENABLE; 773 if (vdsc_instances_per_pipe > 1) { 774 dss_ctl2_val |= RIGHT_BRANCH_VDSC_ENABLE; 775 dss_ctl1_val |= JOINER_ENABLE; 776 } 777 if (crtc_state->bigjoiner_pipes) { 778 dss_ctl1_val |= BIG_JOINER_ENABLE; 779 if (!intel_crtc_is_bigjoiner_slave(crtc_state)) 780 dss_ctl1_val |= MASTER_BIG_JOINER_ENABLE; 781 } 782 intel_de_write(dev_priv, dss_ctl1_reg(crtc, crtc_state->cpu_transcoder), dss_ctl1_val); 783 intel_de_write(dev_priv, dss_ctl2_reg(crtc, crtc_state->cpu_transcoder), dss_ctl2_val); 784 } 785 786 void intel_dsc_disable(const struct intel_crtc_state *old_crtc_state) 787 { 788 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); 789 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 790 791 /* Disable only if either of them is enabled */ 792 if (old_crtc_state->dsc.compression_enable || 793 old_crtc_state->bigjoiner_pipes) { 794 intel_de_write(dev_priv, dss_ctl1_reg(crtc, old_crtc_state->cpu_transcoder), 0); 795 intel_de_write(dev_priv, dss_ctl2_reg(crtc, old_crtc_state->cpu_transcoder), 0); 796 } 797 } 798 799 static u32 intel_dsc_pps_read(struct intel_crtc_state *crtc_state, int pps, 800 bool *check_equal) 801 { 802 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 803 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 804 i915_reg_t dsc_reg[2]; 805 int i, vdsc_per_pipe, dsc_reg_num; 806 u32 val = 0; 807 808 vdsc_per_pipe = intel_dsc_get_vdsc_per_pipe(crtc_state); 809 dsc_reg_num = min_t(int, ARRAY_SIZE(dsc_reg), vdsc_per_pipe); 810 811 drm_WARN_ON_ONCE(&i915->drm, dsc_reg_num < vdsc_per_pipe); 812 813 intel_dsc_get_pps_reg(crtc_state, pps, dsc_reg, dsc_reg_num); 814 815 if (check_equal) 816 *check_equal = true; 817 818 for (i = 0; i < dsc_reg_num; i++) { 819 u32 tmp; 820 821 tmp = intel_de_read(i915, dsc_reg[i]); 822 823 if (i == 0) { 824 val = tmp; 825 } else if (check_equal && tmp != val) { 826 *check_equal = false; 827 break; 828 } else if (!check_equal) { 829 break; 830 } 831 } 832 833 return val; 834 } 835 836 static u32 intel_dsc_pps_read_and_verify(struct intel_crtc_state *crtc_state, int pps) 837 { 838 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 839 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 840 u32 val; 841 bool all_equal; 842 843 val = intel_dsc_pps_read(crtc_state, pps, &all_equal); 844 drm_WARN_ON(&i915->drm, !all_equal); 845 846 return val; 847 } 848 849 static void intel_dsc_get_pps_config(struct intel_crtc_state *crtc_state) 850 { 851 struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config; 852 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 853 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 854 int num_vdsc_instances = intel_dsc_get_num_vdsc_instances(crtc_state); 855 u32 pps_temp; 856 857 /* PPS 0 */ 858 pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 0); 859 860 vdsc_cfg->bits_per_component = REG_FIELD_GET(DSC_PPS0_BPC_MASK, pps_temp); 861 vdsc_cfg->line_buf_depth = REG_FIELD_GET(DSC_PPS0_LINE_BUF_DEPTH_MASK, pps_temp); 862 vdsc_cfg->block_pred_enable = pps_temp & DSC_PPS0_BLOCK_PREDICTION; 863 vdsc_cfg->convert_rgb = pps_temp & DSC_PPS0_COLOR_SPACE_CONVERSION; 864 vdsc_cfg->simple_422 = pps_temp & DSC_PPS0_422_ENABLE; 865 vdsc_cfg->native_422 = pps_temp & DSC_PPS0_NATIVE_422_ENABLE; 866 vdsc_cfg->native_420 = pps_temp & DSC_PPS0_NATIVE_420_ENABLE; 867 vdsc_cfg->vbr_enable = pps_temp & DSC_PPS0_VBR_ENABLE; 868 869 /* PPS 1 */ 870 pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 1); 871 872 vdsc_cfg->bits_per_pixel = REG_FIELD_GET(DSC_PPS1_BPP_MASK, pps_temp); 873 874 if (vdsc_cfg->native_420) 875 vdsc_cfg->bits_per_pixel >>= 1; 876 877 crtc_state->dsc.compressed_bpp = vdsc_cfg->bits_per_pixel >> 4; 878 879 /* PPS 2 */ 880 pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 2); 881 882 vdsc_cfg->pic_width = REG_FIELD_GET(DSC_PPS2_PIC_WIDTH_MASK, pps_temp) * num_vdsc_instances; 883 vdsc_cfg->pic_height = REG_FIELD_GET(DSC_PPS2_PIC_HEIGHT_MASK, pps_temp); 884 885 /* PPS 3 */ 886 pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 3); 887 888 vdsc_cfg->slice_width = REG_FIELD_GET(DSC_PPS3_SLICE_WIDTH_MASK, pps_temp); 889 vdsc_cfg->slice_height = REG_FIELD_GET(DSC_PPS3_SLICE_HEIGHT_MASK, pps_temp); 890 891 /* PPS 4 */ 892 pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 4); 893 894 vdsc_cfg->initial_dec_delay = REG_FIELD_GET(DSC_PPS4_INITIAL_DEC_DELAY_MASK, pps_temp); 895 vdsc_cfg->initial_xmit_delay = REG_FIELD_GET(DSC_PPS4_INITIAL_XMIT_DELAY_MASK, pps_temp); 896 897 /* PPS 5 */ 898 pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 5); 899 900 vdsc_cfg->scale_decrement_interval = REG_FIELD_GET(DSC_PPS5_SCALE_DEC_INT_MASK, pps_temp); 901 vdsc_cfg->scale_increment_interval = REG_FIELD_GET(DSC_PPS5_SCALE_INC_INT_MASK, pps_temp); 902 903 /* PPS 6 */ 904 pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 6); 905 906 vdsc_cfg->initial_scale_value = REG_FIELD_GET(DSC_PPS6_INITIAL_SCALE_VALUE_MASK, pps_temp); 907 vdsc_cfg->first_line_bpg_offset = REG_FIELD_GET(DSC_PPS6_FIRST_LINE_BPG_OFFSET_MASK, pps_temp); 908 vdsc_cfg->flatness_min_qp = REG_FIELD_GET(DSC_PPS6_FLATNESS_MIN_QP_MASK, pps_temp); 909 vdsc_cfg->flatness_max_qp = REG_FIELD_GET(DSC_PPS6_FLATNESS_MAX_QP_MASK, pps_temp); 910 911 /* PPS 7 */ 912 pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 7); 913 914 vdsc_cfg->nfl_bpg_offset = REG_FIELD_GET(DSC_PPS7_NFL_BPG_OFFSET_MASK, pps_temp); 915 vdsc_cfg->slice_bpg_offset = REG_FIELD_GET(DSC_PPS7_SLICE_BPG_OFFSET_MASK, pps_temp); 916 917 /* PPS 8 */ 918 pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 8); 919 920 vdsc_cfg->initial_offset = REG_FIELD_GET(DSC_PPS8_INITIAL_OFFSET_MASK, pps_temp); 921 vdsc_cfg->final_offset = REG_FIELD_GET(DSC_PPS8_FINAL_OFFSET_MASK, pps_temp); 922 923 /* PPS 9 */ 924 pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 9); 925 926 vdsc_cfg->rc_model_size = REG_FIELD_GET(DSC_PPS9_RC_MODEL_SIZE_MASK, pps_temp); 927 928 /* PPS 10 */ 929 pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 10); 930 931 vdsc_cfg->rc_quant_incr_limit0 = REG_FIELD_GET(DSC_PPS10_RC_QUANT_INC_LIMIT0_MASK, pps_temp); 932 vdsc_cfg->rc_quant_incr_limit1 = REG_FIELD_GET(DSC_PPS10_RC_QUANT_INC_LIMIT1_MASK, pps_temp); 933 934 /* PPS 16 */ 935 pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 16); 936 937 vdsc_cfg->slice_chunk_size = REG_FIELD_GET(DSC_PPS16_SLICE_CHUNK_SIZE_MASK, pps_temp); 938 939 if (DISPLAY_VER(i915) >= 14) { 940 /* PPS 17 */ 941 pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 17); 942 943 vdsc_cfg->second_line_bpg_offset = REG_FIELD_GET(DSC_PPS17_SL_BPG_OFFSET_MASK, pps_temp); 944 945 /* PPS 18 */ 946 pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 18); 947 948 vdsc_cfg->nsl_bpg_offset = REG_FIELD_GET(DSC_PPS18_NSL_BPG_OFFSET_MASK, pps_temp); 949 vdsc_cfg->second_line_offset_adj = REG_FIELD_GET(DSC_PPS18_SL_OFFSET_ADJ_MASK, pps_temp); 950 } 951 } 952 953 void intel_dsc_get_config(struct intel_crtc_state *crtc_state) 954 { 955 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 956 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 957 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 958 enum intel_display_power_domain power_domain; 959 intel_wakeref_t wakeref; 960 u32 dss_ctl1, dss_ctl2; 961 962 if (!intel_dsc_source_support(crtc_state)) 963 return; 964 965 power_domain = intel_dsc_power_domain(crtc, cpu_transcoder); 966 967 wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain); 968 if (!wakeref) 969 return; 970 971 dss_ctl1 = intel_de_read(dev_priv, dss_ctl1_reg(crtc, cpu_transcoder)); 972 dss_ctl2 = intel_de_read(dev_priv, dss_ctl2_reg(crtc, cpu_transcoder)); 973 974 crtc_state->dsc.compression_enable = dss_ctl2 & LEFT_BRANCH_VDSC_ENABLE; 975 if (!crtc_state->dsc.compression_enable) 976 goto out; 977 978 crtc_state->dsc.dsc_split = (dss_ctl2 & RIGHT_BRANCH_VDSC_ENABLE) && 979 (dss_ctl1 & JOINER_ENABLE); 980 981 intel_dsc_get_pps_config(crtc_state); 982 out: 983 intel_display_power_put(dev_priv, power_domain, wakeref); 984 } 985