1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2018 Intel Corporation 4 * 5 * Author: Gaurav K Singh <gaurav.k.singh@intel.com> 6 * Manasi Navare <manasi.d.navare@intel.com> 7 */ 8 #include <linux/limits.h> 9 10 #include "i915_drv.h" 11 #include "intel_crtc.h" 12 #include "intel_de.h" 13 #include "intel_display_types.h" 14 #include "intel_dsi.h" 15 #include "intel_qp_tables.h" 16 #include "intel_vdsc.h" 17 18 enum ROW_INDEX_BPP { 19 ROW_INDEX_6BPP = 0, 20 ROW_INDEX_8BPP, 21 ROW_INDEX_10BPP, 22 ROW_INDEX_12BPP, 23 ROW_INDEX_15BPP, 24 MAX_ROW_INDEX 25 }; 26 27 enum COLUMN_INDEX_BPC { 28 COLUMN_INDEX_8BPC = 0, 29 COLUMN_INDEX_10BPC, 30 COLUMN_INDEX_12BPC, 31 COLUMN_INDEX_14BPC, 32 COLUMN_INDEX_16BPC, 33 MAX_COLUMN_INDEX 34 }; 35 36 /* From DSC_v1.11 spec, rc_parameter_Set syntax element typically constant */ 37 static const u16 rc_buf_thresh[] = { 38 896, 1792, 2688, 3584, 4480, 5376, 6272, 6720, 7168, 7616, 39 7744, 7872, 8000, 8064 40 }; 41 42 struct rc_parameters { 43 u16 initial_xmit_delay; 44 u8 first_line_bpg_offset; 45 u16 initial_offset; 46 u8 flatness_min_qp; 47 u8 flatness_max_qp; 48 u8 rc_quant_incr_limit0; 49 u8 rc_quant_incr_limit1; 50 struct drm_dsc_rc_range_parameters rc_range_params[DSC_NUM_BUF_RANGES]; 51 }; 52 53 /* 54 * Selected Rate Control Related Parameter Recommended Values 55 * from DSC_v1.11 spec & C Model release: DSC_model_20161212 56 */ 57 static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = { 58 { 59 /* 6BPP/8BPC */ 60 { 768, 15, 6144, 3, 13, 11, 11, { 61 { 0, 4, 0 }, { 1, 6, -2 }, { 3, 8, -2 }, { 4, 8, -4 }, 62 { 5, 9, -6 }, { 5, 9, -6 }, { 6, 9, -6 }, { 6, 10, -8 }, 63 { 7, 11, -8 }, { 8, 12, -10 }, { 9, 12, -10 }, { 10, 12, -12 }, 64 { 10, 12, -12 }, { 11, 12, -12 }, { 13, 14, -12 } 65 } 66 }, 67 /* 6BPP/10BPC */ 68 { 768, 15, 6144, 7, 17, 15, 15, { 69 { 0, 8, 0 }, { 3, 10, -2 }, { 7, 12, -2 }, { 8, 12, -4 }, 70 { 9, 13, -6 }, { 9, 13, -6 }, { 10, 13, -6 }, { 10, 14, -8 }, 71 { 11, 15, -8 }, { 12, 16, -10 }, { 13, 16, -10 }, 72 { 14, 16, -12 }, { 14, 16, -12 }, { 15, 16, -12 }, 73 { 17, 18, -12 } 74 } 75 }, 76 /* 6BPP/12BPC */ 77 { 768, 15, 6144, 11, 21, 19, 19, { 78 { 0, 12, 0 }, { 5, 14, -2 }, { 11, 16, -2 }, { 12, 16, -4 }, 79 { 13, 17, -6 }, { 13, 17, -6 }, { 14, 17, -6 }, { 14, 18, -8 }, 80 { 15, 19, -8 }, { 16, 20, -10 }, { 17, 20, -10 }, 81 { 18, 20, -12 }, { 18, 20, -12 }, { 19, 20, -12 }, 82 { 21, 22, -12 } 83 } 84 }, 85 /* 6BPP/14BPC */ 86 { 768, 15, 6144, 15, 25, 23, 27, { 87 { 0, 16, 0 }, { 7, 18, -2 }, { 15, 20, -2 }, { 16, 20, -4 }, 88 { 17, 21, -6 }, { 17, 21, -6 }, { 18, 21, -6 }, { 18, 22, -8 }, 89 { 19, 23, -8 }, { 20, 24, -10 }, { 21, 24, -10 }, 90 { 22, 24, -12 }, { 22, 24, -12 }, { 23, 24, -12 }, 91 { 25, 26, -12 } 92 } 93 }, 94 /* 6BPP/16BPC */ 95 { 768, 15, 6144, 19, 29, 27, 27, { 96 { 0, 20, 0 }, { 9, 22, -2 }, { 19, 24, -2 }, { 20, 24, -4 }, 97 { 21, 25, -6 }, { 21, 25, -6 }, { 22, 25, -6 }, { 22, 26, -8 }, 98 { 23, 27, -8 }, { 24, 28, -10 }, { 25, 28, -10 }, 99 { 26, 28, -12 }, { 26, 28, -12 }, { 27, 28, -12 }, 100 { 29, 30, -12 } 101 } 102 }, 103 }, 104 { 105 /* 8BPP/8BPC */ 106 { 512, 12, 6144, 3, 12, 11, 11, { 107 { 0, 4, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 }, 108 { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 }, 109 { 3, 9, -8 }, { 3, 10, -10 }, { 5, 11, -10 }, { 5, 12, -12 }, 110 { 5, 13, -12 }, { 7, 13, -12 }, { 13, 15, -12 } 111 } 112 }, 113 /* 8BPP/10BPC */ 114 { 512, 12, 6144, 7, 16, 15, 15, { 115 { 0, 4, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 5, 10, -2 }, 116 { 7, 11, -4 }, { 7, 11, -6 }, { 7, 11, -8 }, { 7, 12, -8 }, 117 { 7, 13, -8 }, { 7, 14, -10 }, { 9, 15, -10 }, { 9, 16, -12 }, 118 { 9, 17, -12 }, { 11, 17, -12 }, { 17, 19, -12 } 119 } 120 }, 121 /* 8BPP/12BPC */ 122 { 512, 12, 6144, 11, 20, 19, 19, { 123 { 0, 12, 2 }, { 4, 12, 0 }, { 9, 13, 0 }, { 9, 14, -2 }, 124 { 11, 15, -4 }, { 11, 15, -6 }, { 11, 15, -8 }, { 11, 16, -8 }, 125 { 11, 17, -8 }, { 11, 18, -10 }, { 13, 19, -10 }, 126 { 13, 20, -12 }, { 13, 21, -12 }, { 15, 21, -12 }, 127 { 21, 23, -12 } 128 } 129 }, 130 /* 8BPP/14BPC */ 131 { 512, 12, 6144, 15, 24, 23, 23, { 132 { 0, 12, 0 }, { 5, 13, 0 }, { 11, 15, 0 }, { 12, 17, -2 }, 133 { 15, 19, -4 }, { 15, 19, -6 }, { 15, 19, -8 }, { 15, 20, -8 }, 134 { 15, 21, -8 }, { 15, 22, -10 }, { 17, 22, -10 }, 135 { 17, 23, -12 }, { 17, 23, -12 }, { 21, 24, -12 }, 136 { 24, 25, -12 } 137 } 138 }, 139 /* 8BPP/16BPC */ 140 { 512, 12, 6144, 19, 28, 27, 27, { 141 { 0, 12, 2 }, { 6, 14, 0 }, { 13, 17, 0 }, { 15, 20, -2 }, 142 { 19, 23, -4 }, { 19, 23, -6 }, { 19, 23, -8 }, { 19, 24, -8 }, 143 { 19, 25, -8 }, { 19, 26, -10 }, { 21, 26, -10 }, 144 { 21, 27, -12 }, { 21, 27, -12 }, { 25, 28, -12 }, 145 { 28, 29, -12 } 146 } 147 }, 148 }, 149 { 150 /* 10BPP/8BPC */ 151 { 410, 15, 5632, 3, 12, 11, 11, { 152 { 0, 3, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 2, 6, -2 }, 153 { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 }, 154 { 3, 9, -8 }, { 3, 9, -10 }, { 5, 10, -10 }, { 5, 10, -10 }, 155 { 5, 11, -12 }, { 7, 11, -12 }, { 11, 12, -12 } 156 } 157 }, 158 /* 10BPP/10BPC */ 159 { 410, 15, 5632, 7, 16, 15, 15, { 160 { 0, 7, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 6, 10, -2 }, 161 { 7, 11, -4 }, { 7, 11, -6 }, { 7, 11, -8 }, { 7, 12, -8 }, 162 { 7, 13, -8 }, { 7, 13, -10 }, { 9, 14, -10 }, { 9, 14, -10 }, 163 { 9, 15, -12 }, { 11, 15, -12 }, { 15, 16, -12 } 164 } 165 }, 166 /* 10BPP/12BPC */ 167 { 410, 15, 5632, 11, 20, 19, 19, { 168 { 0, 11, 2 }, { 4, 12, 0 }, { 9, 13, 0 }, { 10, 14, -2 }, 169 { 11, 15, -4 }, { 11, 15, -6 }, { 11, 15, -8 }, { 11, 16, -8 }, 170 { 11, 17, -8 }, { 11, 17, -10 }, { 13, 18, -10 }, 171 { 13, 18, -10 }, { 13, 19, -12 }, { 15, 19, -12 }, 172 { 19, 20, -12 } 173 } 174 }, 175 /* 10BPP/14BPC */ 176 { 410, 15, 5632, 15, 24, 23, 23, { 177 { 0, 11, 2 }, { 5, 13, 0 }, { 11, 15, 0 }, { 13, 18, -2 }, 178 { 15, 19, -4 }, { 15, 19, -6 }, { 15, 19, -8 }, { 15, 20, -8 }, 179 { 15, 21, -8 }, { 15, 21, -10 }, { 17, 22, -10 }, 180 { 17, 22, -10 }, { 17, 23, -12 }, { 19, 23, -12 }, 181 { 23, 24, -12 } 182 } 183 }, 184 /* 10BPP/16BPC */ 185 { 410, 15, 5632, 19, 28, 27, 27, { 186 { 0, 11, 2 }, { 6, 14, 0 }, { 13, 17, 0 }, { 16, 20, -2 }, 187 { 19, 23, -4 }, { 19, 23, -6 }, { 19, 23, -8 }, { 19, 24, -8 }, 188 { 19, 25, -8 }, { 19, 25, -10 }, { 21, 26, -10 }, 189 { 21, 26, -10 }, { 21, 27, -12 }, { 23, 27, -12 }, 190 { 27, 28, -12 } 191 } 192 }, 193 }, 194 { 195 /* 12BPP/8BPC */ 196 { 341, 15, 2048, 3, 12, 11, 11, { 197 { 0, 2, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 }, 198 { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 }, 199 { 3, 9, -8 }, { 3, 10, -10 }, { 5, 11, -10 }, 200 { 5, 12, -12 }, { 5, 13, -12 }, { 7, 13, -12 }, { 13, 15, -12 } 201 } 202 }, 203 /* 12BPP/10BPC */ 204 { 341, 15, 2048, 7, 16, 15, 15, { 205 { 0, 2, 2 }, { 2, 5, 0 }, { 3, 7, 0 }, { 4, 8, -2 }, 206 { 6, 9, -4 }, { 7, 10, -6 }, { 7, 11, -8 }, { 7, 12, -8 }, 207 { 7, 13, -8 }, { 7, 14, -10 }, { 9, 15, -10 }, { 9, 16, -12 }, 208 { 9, 17, -12 }, { 11, 17, -12 }, { 17, 19, -12 } 209 } 210 }, 211 /* 12BPP/12BPC */ 212 { 341, 15, 2048, 11, 20, 19, 19, { 213 { 0, 6, 2 }, { 4, 9, 0 }, { 7, 11, 0 }, { 8, 12, -2 }, 214 { 10, 13, -4 }, { 11, 14, -6 }, { 11, 15, -8 }, { 11, 16, -8 }, 215 { 11, 17, -8 }, { 11, 18, -10 }, { 13, 19, -10 }, 216 { 13, 20, -12 }, { 13, 21, -12 }, { 15, 21, -12 }, 217 { 21, 23, -12 } 218 } 219 }, 220 /* 12BPP/14BPC */ 221 { 341, 15, 2048, 15, 24, 23, 23, { 222 { 0, 6, 2 }, { 7, 10, 0 }, { 9, 13, 0 }, { 11, 16, -2 }, 223 { 14, 17, -4 }, { 15, 18, -6 }, { 15, 19, -8 }, { 15, 20, -8 }, 224 { 15, 20, -8 }, { 15, 21, -10 }, { 17, 21, -10 }, 225 { 17, 21, -12 }, { 17, 21, -12 }, { 19, 22, -12 }, 226 { 22, 23, -12 } 227 } 228 }, 229 /* 12BPP/16BPC */ 230 { 341, 15, 2048, 19, 28, 27, 27, { 231 { 0, 6, 2 }, { 6, 11, 0 }, { 11, 15, 0 }, { 14, 18, -2 }, 232 { 18, 21, -4 }, { 19, 22, -6 }, { 19, 23, -8 }, { 19, 24, -8 }, 233 { 19, 24, -8 }, { 19, 25, -10 }, { 21, 25, -10 }, 234 { 21, 25, -12 }, { 21, 25, -12 }, { 23, 26, -12 }, 235 { 26, 27, -12 } 236 } 237 }, 238 }, 239 { 240 /* 15BPP/8BPC */ 241 { 273, 15, 2048, 3, 12, 11, 11, { 242 { 0, 0, 10 }, { 0, 1, 8 }, { 0, 1, 6 }, { 0, 2, 4 }, 243 { 1, 2, 2 }, { 1, 3, 0 }, { 1, 3, -2 }, { 2, 4, -4 }, 244 { 2, 5, -6 }, { 3, 5, -8 }, { 4, 6, -10 }, { 4, 7, -10 }, 245 { 5, 7, -12 }, { 7, 8, -12 }, { 8, 9, -12 } 246 } 247 }, 248 /* 15BPP/10BPC */ 249 { 273, 15, 2048, 7, 16, 15, 15, { 250 { 0, 2, 10 }, { 2, 5, 8 }, { 3, 5, 6 }, { 4, 6, 4 }, 251 { 5, 6, 2 }, { 5, 7, 0 }, { 5, 7, -2 }, { 6, 8, -4 }, 252 { 6, 9, -6 }, { 7, 9, -8 }, { 8, 10, -10 }, { 8, 11, -10 }, 253 { 9, 11, -12 }, { 11, 12, -12 }, { 12, 13, -12 } 254 } 255 }, 256 /* 15BPP/12BPC */ 257 { 273, 15, 2048, 11, 20, 19, 19, { 258 { 0, 4, 10 }, { 2, 7, 8 }, { 4, 9, 6 }, { 6, 11, 4 }, 259 { 9, 11, 2 }, { 9, 11, 0 }, { 9, 12, -2 }, { 10, 12, -4 }, 260 { 11, 13, -6 }, { 11, 13, -8 }, { 12, 14, -10 }, 261 { 13, 15, -10 }, { 13, 15, -12 }, { 15, 16, -12 }, 262 { 16, 17, -12 } 263 } 264 }, 265 /* 15BPP/14BPC */ 266 { 273, 15, 2048, 15, 24, 23, 23, { 267 { 0, 4, 10 }, { 3, 8, 8 }, { 6, 11, 6 }, { 9, 14, 4 }, 268 { 13, 15, 2 }, { 13, 15, 0 }, { 13, 16, -2 }, { 14, 16, -4 }, 269 { 15, 17, -6 }, { 15, 17, -8 }, { 16, 18, -10 }, 270 { 17, 19, -10 }, { 17, 19, -12 }, { 19, 20, -12 }, 271 { 20, 21, -12 } 272 } 273 }, 274 /* 15BPP/16BPC */ 275 { 273, 15, 2048, 19, 28, 27, 27, { 276 { 0, 4, 10 }, { 4, 9, 8 }, { 8, 13, 6 }, { 12, 17, 4 }, 277 { 17, 19, 2 }, { 17, 20, 0 }, { 17, 20, -2 }, { 18, 20, -4 }, 278 { 19, 21, -6 }, { 19, 21, -8 }, { 20, 22, -10 }, 279 { 21, 23, -10 }, { 21, 23, -12 }, { 23, 24, -12 }, 280 { 24, 25, -12 } 281 } 282 } 283 } 284 285 }; 286 287 static int get_row_index_for_rc_params(u16 compressed_bpp) 288 { 289 switch (compressed_bpp) { 290 case 6: 291 return ROW_INDEX_6BPP; 292 case 8: 293 return ROW_INDEX_8BPP; 294 case 10: 295 return ROW_INDEX_10BPP; 296 case 12: 297 return ROW_INDEX_12BPP; 298 case 15: 299 return ROW_INDEX_15BPP; 300 default: 301 return -EINVAL; 302 } 303 } 304 305 static int get_column_index_for_rc_params(u8 bits_per_component) 306 { 307 switch (bits_per_component) { 308 case 8: 309 return COLUMN_INDEX_8BPC; 310 case 10: 311 return COLUMN_INDEX_10BPC; 312 case 12: 313 return COLUMN_INDEX_12BPC; 314 case 14: 315 return COLUMN_INDEX_14BPC; 316 case 16: 317 return COLUMN_INDEX_16BPC; 318 default: 319 return -EINVAL; 320 } 321 } 322 323 static const struct rc_parameters *get_rc_params(u16 compressed_bpp, 324 u8 bits_per_component) 325 { 326 int row_index, column_index; 327 328 row_index = get_row_index_for_rc_params(compressed_bpp); 329 if (row_index < 0) 330 return NULL; 331 332 column_index = get_column_index_for_rc_params(bits_per_component); 333 if (column_index < 0) 334 return NULL; 335 336 return &rc_parameters[row_index][column_index]; 337 } 338 339 bool intel_dsc_source_support(const struct intel_crtc_state *crtc_state) 340 { 341 const struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 342 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 343 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 344 345 if (!INTEL_INFO(i915)->display.has_dsc) 346 return false; 347 348 if (DISPLAY_VER(i915) >= 12) 349 return true; 350 351 if (DISPLAY_VER(i915) >= 11 && cpu_transcoder != TRANSCODER_A) 352 return true; 353 354 return false; 355 } 356 357 static bool is_pipe_dsc(struct intel_crtc *crtc, enum transcoder cpu_transcoder) 358 { 359 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 360 361 if (DISPLAY_VER(i915) >= 12) 362 return true; 363 364 if (cpu_transcoder == TRANSCODER_EDP || 365 cpu_transcoder == TRANSCODER_DSI_0 || 366 cpu_transcoder == TRANSCODER_DSI_1) 367 return false; 368 369 /* There's no pipe A DSC engine on ICL */ 370 drm_WARN_ON(&i915->drm, crtc->pipe == PIPE_A); 371 372 return true; 373 } 374 375 static void 376 calculate_rc_params(struct rc_parameters *rc, 377 struct drm_dsc_config *vdsc_cfg) 378 { 379 int bpc = vdsc_cfg->bits_per_component; 380 int bpp = vdsc_cfg->bits_per_pixel >> 4; 381 int ofs_und6[] = { 0, -2, -2, -4, -6, -6, -8, -8, -8, -10, -10, -12, -12, -12, -12 }; 382 int ofs_und8[] = { 2, 0, 0, -2, -4, -6, -8, -8, -8, -10, -10, -10, -12, -12, -12 }; 383 int ofs_und12[] = { 2, 0, 0, -2, -4, -6, -8, -8, -8, -10, -10, -10, -12, -12, -12 }; 384 int ofs_und15[] = { 10, 8, 6, 4, 2, 0, -2, -4, -6, -8, -10, -10, -12, -12, -12 }; 385 int qp_bpc_modifier = (bpc - 8) * 2; 386 u32 res, buf_i, bpp_i; 387 388 if (vdsc_cfg->slice_height >= 8) 389 rc->first_line_bpg_offset = 390 12 + DIV_ROUND_UP((9 * min(34, vdsc_cfg->slice_height - 8)), 100); 391 else 392 rc->first_line_bpg_offset = 2 * (vdsc_cfg->slice_height - 1); 393 394 /* Our hw supports only 444 modes as of today */ 395 if (bpp >= 12) 396 rc->initial_offset = 2048; 397 else if (bpp >= 10) 398 rc->initial_offset = 5632 - DIV_ROUND_UP(((bpp - 10) * 3584), 2); 399 else if (bpp >= 8) 400 rc->initial_offset = 6144 - DIV_ROUND_UP(((bpp - 8) * 512), 2); 401 else 402 rc->initial_offset = 6144; 403 404 /* initial_xmit_delay = rc_model_size/2/compression_bpp */ 405 rc->initial_xmit_delay = DIV_ROUND_UP(DSC_RC_MODEL_SIZE_CONST, 2 * bpp); 406 407 rc->flatness_min_qp = 3 + qp_bpc_modifier; 408 rc->flatness_max_qp = 12 + qp_bpc_modifier; 409 410 rc->rc_quant_incr_limit0 = 11 + qp_bpc_modifier; 411 rc->rc_quant_incr_limit1 = 11 + qp_bpc_modifier; 412 413 bpp_i = (2 * (bpp - 6)); 414 for (buf_i = 0; buf_i < DSC_NUM_BUF_RANGES; buf_i++) { 415 /* Read range_minqp and range_max_qp from qp tables */ 416 rc->rc_range_params[buf_i].range_min_qp = 417 intel_lookup_range_min_qp(bpc, buf_i, bpp_i); 418 rc->rc_range_params[buf_i].range_max_qp = 419 intel_lookup_range_max_qp(bpc, buf_i, bpp_i); 420 421 /* Calculate range_bgp_offset */ 422 if (bpp <= 6) { 423 rc->rc_range_params[buf_i].range_bpg_offset = ofs_und6[buf_i]; 424 } else if (bpp <= 8) { 425 res = DIV_ROUND_UP(((bpp - 6) * (ofs_und8[buf_i] - ofs_und6[buf_i])), 2); 426 rc->rc_range_params[buf_i].range_bpg_offset = 427 ofs_und6[buf_i] + res; 428 } else if (bpp <= 12) { 429 rc->rc_range_params[buf_i].range_bpg_offset = 430 ofs_und8[buf_i]; 431 } else if (bpp <= 15) { 432 res = DIV_ROUND_UP(((bpp - 12) * (ofs_und15[buf_i] - ofs_und12[buf_i])), 3); 433 rc->rc_range_params[buf_i].range_bpg_offset = 434 ofs_und12[buf_i] + res; 435 } else { 436 rc->rc_range_params[buf_i].range_bpg_offset = 437 ofs_und15[buf_i]; 438 } 439 } 440 } 441 442 int intel_dsc_compute_params(struct intel_crtc_state *pipe_config) 443 { 444 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 445 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 446 struct drm_dsc_config *vdsc_cfg = &pipe_config->dsc.config; 447 u16 compressed_bpp = pipe_config->dsc.compressed_bpp; 448 const struct rc_parameters *rc_params; 449 struct rc_parameters *rc = NULL; 450 u8 i = 0; 451 452 vdsc_cfg->pic_width = pipe_config->hw.adjusted_mode.crtc_hdisplay; 453 vdsc_cfg->pic_height = pipe_config->hw.adjusted_mode.crtc_vdisplay; 454 vdsc_cfg->slice_width = DIV_ROUND_UP(vdsc_cfg->pic_width, 455 pipe_config->dsc.slice_count); 456 457 /* Gen 11 does not support YCbCr */ 458 vdsc_cfg->simple_422 = false; 459 /* Gen 11 does not support VBR */ 460 vdsc_cfg->vbr_enable = false; 461 462 /* Gen 11 only supports integral values of bpp */ 463 vdsc_cfg->bits_per_pixel = compressed_bpp << 4; 464 vdsc_cfg->bits_per_component = pipe_config->pipe_bpp / 3; 465 466 for (i = 0; i < DSC_NUM_BUF_RANGES - 1; i++) { 467 /* 468 * six 0s are appended to the lsb of each threshold value 469 * internally in h/w. 470 * Only 8 bits are allowed for programming RcBufThreshold 471 */ 472 vdsc_cfg->rc_buf_thresh[i] = rc_buf_thresh[i] >> 6; 473 } 474 475 /* 476 * For 6bpp, RC Buffer threshold 12 and 13 need a different value 477 * as per C Model 478 */ 479 if (compressed_bpp == 6) { 480 vdsc_cfg->rc_buf_thresh[12] = 0x7C; 481 vdsc_cfg->rc_buf_thresh[13] = 0x7D; 482 } 483 484 /* 485 * From XE_LPD onwards we supports compression bpps in steps of 1 486 * upto uncompressed bpp-1, hence add calculations for all the rc 487 * parameters 488 */ 489 if (DISPLAY_VER(dev_priv) >= 13) { 490 rc = kmalloc(sizeof(*rc), GFP_KERNEL); 491 if (!rc) 492 return -ENOMEM; 493 494 calculate_rc_params(rc, vdsc_cfg); 495 rc_params = rc; 496 } else { 497 rc_params = get_rc_params(compressed_bpp, 498 vdsc_cfg->bits_per_component); 499 if (!rc_params) 500 return -EINVAL; 501 } 502 503 vdsc_cfg->first_line_bpg_offset = rc_params->first_line_bpg_offset; 504 vdsc_cfg->initial_xmit_delay = rc_params->initial_xmit_delay; 505 vdsc_cfg->initial_offset = rc_params->initial_offset; 506 vdsc_cfg->flatness_min_qp = rc_params->flatness_min_qp; 507 vdsc_cfg->flatness_max_qp = rc_params->flatness_max_qp; 508 vdsc_cfg->rc_quant_incr_limit0 = rc_params->rc_quant_incr_limit0; 509 vdsc_cfg->rc_quant_incr_limit1 = rc_params->rc_quant_incr_limit1; 510 511 for (i = 0; i < DSC_NUM_BUF_RANGES; i++) { 512 vdsc_cfg->rc_range_params[i].range_min_qp = 513 rc_params->rc_range_params[i].range_min_qp; 514 vdsc_cfg->rc_range_params[i].range_max_qp = 515 rc_params->rc_range_params[i].range_max_qp; 516 /* 517 * Range BPG Offset uses 2's complement and is only a 6 bits. So 518 * mask it to get only 6 bits. 519 */ 520 vdsc_cfg->rc_range_params[i].range_bpg_offset = 521 rc_params->rc_range_params[i].range_bpg_offset & 522 DSC_RANGE_BPG_OFFSET_MASK; 523 } 524 525 /* 526 * BitsPerComponent value determines mux_word_size: 527 * When BitsPerComponent is less than or 10bpc, muxWordSize will be equal to 528 * 48 bits otherwise 64 529 */ 530 if (vdsc_cfg->bits_per_component <= 10) 531 vdsc_cfg->mux_word_size = DSC_MUX_WORD_SIZE_8_10_BPC; 532 else 533 vdsc_cfg->mux_word_size = DSC_MUX_WORD_SIZE_12_BPC; 534 535 /* InitialScaleValue is a 6 bit value with 3 fractional bits (U3.3) */ 536 vdsc_cfg->initial_scale_value = (vdsc_cfg->rc_model_size << 3) / 537 (vdsc_cfg->rc_model_size - vdsc_cfg->initial_offset); 538 539 kfree(rc); 540 541 return 0; 542 } 543 544 enum intel_display_power_domain 545 intel_dsc_power_domain(struct intel_crtc *crtc, enum transcoder cpu_transcoder) 546 { 547 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 548 enum pipe pipe = crtc->pipe; 549 550 /* 551 * VDSC/joining uses a separate power well, PW2, and requires 552 * POWER_DOMAIN_TRANSCODER_VDSC_PW2 power domain in two cases: 553 * 554 * - ICL eDP/DSI transcoder 555 * - Display version 12 (except RKL) pipe A 556 * 557 * For any other pipe, VDSC/joining uses the power well associated with 558 * the pipe in use. Hence another reference on the pipe power domain 559 * will suffice. (Except no VDSC/joining on ICL pipe A.) 560 */ 561 if (DISPLAY_VER(i915) == 12 && !IS_ROCKETLAKE(i915) && pipe == PIPE_A) 562 return POWER_DOMAIN_TRANSCODER_VDSC_PW2; 563 else if (is_pipe_dsc(crtc, cpu_transcoder)) 564 return POWER_DOMAIN_PIPE(pipe); 565 else 566 return POWER_DOMAIN_TRANSCODER_VDSC_PW2; 567 } 568 569 static void intel_dsc_pps_configure(const struct intel_crtc_state *crtc_state) 570 { 571 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 572 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 573 const struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config; 574 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 575 enum pipe pipe = crtc->pipe; 576 u32 pps_val = 0; 577 u32 rc_buf_thresh_dword[4]; 578 u32 rc_range_params_dword[8]; 579 u8 num_vdsc_instances = (crtc_state->dsc.dsc_split) ? 2 : 1; 580 int i = 0; 581 582 if (crtc_state->bigjoiner) 583 num_vdsc_instances *= 2; 584 585 /* Populate PICTURE_PARAMETER_SET_0 registers */ 586 pps_val = DSC_VER_MAJ | vdsc_cfg->dsc_version_minor << 587 DSC_VER_MIN_SHIFT | 588 vdsc_cfg->bits_per_component << DSC_BPC_SHIFT | 589 vdsc_cfg->line_buf_depth << DSC_LINE_BUF_DEPTH_SHIFT; 590 if (vdsc_cfg->block_pred_enable) 591 pps_val |= DSC_BLOCK_PREDICTION; 592 if (vdsc_cfg->convert_rgb) 593 pps_val |= DSC_COLOR_SPACE_CONVERSION; 594 if (vdsc_cfg->simple_422) 595 pps_val |= DSC_422_ENABLE; 596 if (vdsc_cfg->vbr_enable) 597 pps_val |= DSC_VBR_ENABLE; 598 drm_dbg_kms(&dev_priv->drm, "PPS0 = 0x%08x\n", pps_val); 599 if (!is_pipe_dsc(crtc, cpu_transcoder)) { 600 intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_0, 601 pps_val); 602 /* 603 * If 2 VDSC instances are needed, configure PPS for second 604 * VDSC 605 */ 606 if (crtc_state->dsc.dsc_split) 607 intel_de_write(dev_priv, DSCC_PICTURE_PARAMETER_SET_0, 608 pps_val); 609 } else { 610 intel_de_write(dev_priv, 611 ICL_DSC0_PICTURE_PARAMETER_SET_0(pipe), 612 pps_val); 613 if (crtc_state->dsc.dsc_split) 614 intel_de_write(dev_priv, 615 ICL_DSC1_PICTURE_PARAMETER_SET_0(pipe), 616 pps_val); 617 } 618 619 /* Populate PICTURE_PARAMETER_SET_1 registers */ 620 pps_val = 0; 621 pps_val |= DSC_BPP(vdsc_cfg->bits_per_pixel); 622 drm_dbg_kms(&dev_priv->drm, "PPS1 = 0x%08x\n", pps_val); 623 if (!is_pipe_dsc(crtc, cpu_transcoder)) { 624 intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_1, 625 pps_val); 626 /* 627 * If 2 VDSC instances are needed, configure PPS for second 628 * VDSC 629 */ 630 if (crtc_state->dsc.dsc_split) 631 intel_de_write(dev_priv, DSCC_PICTURE_PARAMETER_SET_1, 632 pps_val); 633 } else { 634 intel_de_write(dev_priv, 635 ICL_DSC0_PICTURE_PARAMETER_SET_1(pipe), 636 pps_val); 637 if (crtc_state->dsc.dsc_split) 638 intel_de_write(dev_priv, 639 ICL_DSC1_PICTURE_PARAMETER_SET_1(pipe), 640 pps_val); 641 } 642 643 /* Populate PICTURE_PARAMETER_SET_2 registers */ 644 pps_val = 0; 645 pps_val |= DSC_PIC_HEIGHT(vdsc_cfg->pic_height) | 646 DSC_PIC_WIDTH(vdsc_cfg->pic_width / num_vdsc_instances); 647 drm_dbg_kms(&dev_priv->drm, "PPS2 = 0x%08x\n", pps_val); 648 if (!is_pipe_dsc(crtc, cpu_transcoder)) { 649 intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_2, 650 pps_val); 651 /* 652 * If 2 VDSC instances are needed, configure PPS for second 653 * VDSC 654 */ 655 if (crtc_state->dsc.dsc_split) 656 intel_de_write(dev_priv, DSCC_PICTURE_PARAMETER_SET_2, 657 pps_val); 658 } else { 659 intel_de_write(dev_priv, 660 ICL_DSC0_PICTURE_PARAMETER_SET_2(pipe), 661 pps_val); 662 if (crtc_state->dsc.dsc_split) 663 intel_de_write(dev_priv, 664 ICL_DSC1_PICTURE_PARAMETER_SET_2(pipe), 665 pps_val); 666 } 667 668 /* Populate PICTURE_PARAMETER_SET_3 registers */ 669 pps_val = 0; 670 pps_val |= DSC_SLICE_HEIGHT(vdsc_cfg->slice_height) | 671 DSC_SLICE_WIDTH(vdsc_cfg->slice_width); 672 drm_dbg_kms(&dev_priv->drm, "PPS3 = 0x%08x\n", pps_val); 673 if (!is_pipe_dsc(crtc, cpu_transcoder)) { 674 intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_3, 675 pps_val); 676 /* 677 * If 2 VDSC instances are needed, configure PPS for second 678 * VDSC 679 */ 680 if (crtc_state->dsc.dsc_split) 681 intel_de_write(dev_priv, DSCC_PICTURE_PARAMETER_SET_3, 682 pps_val); 683 } else { 684 intel_de_write(dev_priv, 685 ICL_DSC0_PICTURE_PARAMETER_SET_3(pipe), 686 pps_val); 687 if (crtc_state->dsc.dsc_split) 688 intel_de_write(dev_priv, 689 ICL_DSC1_PICTURE_PARAMETER_SET_3(pipe), 690 pps_val); 691 } 692 693 /* Populate PICTURE_PARAMETER_SET_4 registers */ 694 pps_val = 0; 695 pps_val |= DSC_INITIAL_XMIT_DELAY(vdsc_cfg->initial_xmit_delay) | 696 DSC_INITIAL_DEC_DELAY(vdsc_cfg->initial_dec_delay); 697 drm_dbg_kms(&dev_priv->drm, "PPS4 = 0x%08x\n", pps_val); 698 if (!is_pipe_dsc(crtc, cpu_transcoder)) { 699 intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_4, 700 pps_val); 701 /* 702 * If 2 VDSC instances are needed, configure PPS for second 703 * VDSC 704 */ 705 if (crtc_state->dsc.dsc_split) 706 intel_de_write(dev_priv, DSCC_PICTURE_PARAMETER_SET_4, 707 pps_val); 708 } else { 709 intel_de_write(dev_priv, 710 ICL_DSC0_PICTURE_PARAMETER_SET_4(pipe), 711 pps_val); 712 if (crtc_state->dsc.dsc_split) 713 intel_de_write(dev_priv, 714 ICL_DSC1_PICTURE_PARAMETER_SET_4(pipe), 715 pps_val); 716 } 717 718 /* Populate PICTURE_PARAMETER_SET_5 registers */ 719 pps_val = 0; 720 pps_val |= DSC_SCALE_INC_INT(vdsc_cfg->scale_increment_interval) | 721 DSC_SCALE_DEC_INT(vdsc_cfg->scale_decrement_interval); 722 drm_dbg_kms(&dev_priv->drm, "PPS5 = 0x%08x\n", pps_val); 723 if (!is_pipe_dsc(crtc, cpu_transcoder)) { 724 intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_5, 725 pps_val); 726 /* 727 * If 2 VDSC instances are needed, configure PPS for second 728 * VDSC 729 */ 730 if (crtc_state->dsc.dsc_split) 731 intel_de_write(dev_priv, DSCC_PICTURE_PARAMETER_SET_5, 732 pps_val); 733 } else { 734 intel_de_write(dev_priv, 735 ICL_DSC0_PICTURE_PARAMETER_SET_5(pipe), 736 pps_val); 737 if (crtc_state->dsc.dsc_split) 738 intel_de_write(dev_priv, 739 ICL_DSC1_PICTURE_PARAMETER_SET_5(pipe), 740 pps_val); 741 } 742 743 /* Populate PICTURE_PARAMETER_SET_6 registers */ 744 pps_val = 0; 745 pps_val |= DSC_INITIAL_SCALE_VALUE(vdsc_cfg->initial_scale_value) | 746 DSC_FIRST_LINE_BPG_OFFSET(vdsc_cfg->first_line_bpg_offset) | 747 DSC_FLATNESS_MIN_QP(vdsc_cfg->flatness_min_qp) | 748 DSC_FLATNESS_MAX_QP(vdsc_cfg->flatness_max_qp); 749 drm_dbg_kms(&dev_priv->drm, "PPS6 = 0x%08x\n", pps_val); 750 if (!is_pipe_dsc(crtc, cpu_transcoder)) { 751 intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_6, 752 pps_val); 753 /* 754 * If 2 VDSC instances are needed, configure PPS for second 755 * VDSC 756 */ 757 if (crtc_state->dsc.dsc_split) 758 intel_de_write(dev_priv, DSCC_PICTURE_PARAMETER_SET_6, 759 pps_val); 760 } else { 761 intel_de_write(dev_priv, 762 ICL_DSC0_PICTURE_PARAMETER_SET_6(pipe), 763 pps_val); 764 if (crtc_state->dsc.dsc_split) 765 intel_de_write(dev_priv, 766 ICL_DSC1_PICTURE_PARAMETER_SET_6(pipe), 767 pps_val); 768 } 769 770 /* Populate PICTURE_PARAMETER_SET_7 registers */ 771 pps_val = 0; 772 pps_val |= DSC_SLICE_BPG_OFFSET(vdsc_cfg->slice_bpg_offset) | 773 DSC_NFL_BPG_OFFSET(vdsc_cfg->nfl_bpg_offset); 774 drm_dbg_kms(&dev_priv->drm, "PPS7 = 0x%08x\n", pps_val); 775 if (!is_pipe_dsc(crtc, cpu_transcoder)) { 776 intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_7, 777 pps_val); 778 /* 779 * If 2 VDSC instances are needed, configure PPS for second 780 * VDSC 781 */ 782 if (crtc_state->dsc.dsc_split) 783 intel_de_write(dev_priv, DSCC_PICTURE_PARAMETER_SET_7, 784 pps_val); 785 } else { 786 intel_de_write(dev_priv, 787 ICL_DSC0_PICTURE_PARAMETER_SET_7(pipe), 788 pps_val); 789 if (crtc_state->dsc.dsc_split) 790 intel_de_write(dev_priv, 791 ICL_DSC1_PICTURE_PARAMETER_SET_7(pipe), 792 pps_val); 793 } 794 795 /* Populate PICTURE_PARAMETER_SET_8 registers */ 796 pps_val = 0; 797 pps_val |= DSC_FINAL_OFFSET(vdsc_cfg->final_offset) | 798 DSC_INITIAL_OFFSET(vdsc_cfg->initial_offset); 799 drm_dbg_kms(&dev_priv->drm, "PPS8 = 0x%08x\n", pps_val); 800 if (!is_pipe_dsc(crtc, cpu_transcoder)) { 801 intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_8, 802 pps_val); 803 /* 804 * If 2 VDSC instances are needed, configure PPS for second 805 * VDSC 806 */ 807 if (crtc_state->dsc.dsc_split) 808 intel_de_write(dev_priv, DSCC_PICTURE_PARAMETER_SET_8, 809 pps_val); 810 } else { 811 intel_de_write(dev_priv, 812 ICL_DSC0_PICTURE_PARAMETER_SET_8(pipe), 813 pps_val); 814 if (crtc_state->dsc.dsc_split) 815 intel_de_write(dev_priv, 816 ICL_DSC1_PICTURE_PARAMETER_SET_8(pipe), 817 pps_val); 818 } 819 820 /* Populate PICTURE_PARAMETER_SET_9 registers */ 821 pps_val = 0; 822 pps_val |= DSC_RC_MODEL_SIZE(vdsc_cfg->rc_model_size) | 823 DSC_RC_EDGE_FACTOR(DSC_RC_EDGE_FACTOR_CONST); 824 drm_dbg_kms(&dev_priv->drm, "PPS9 = 0x%08x\n", pps_val); 825 if (!is_pipe_dsc(crtc, cpu_transcoder)) { 826 intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_9, 827 pps_val); 828 /* 829 * If 2 VDSC instances are needed, configure PPS for second 830 * VDSC 831 */ 832 if (crtc_state->dsc.dsc_split) 833 intel_de_write(dev_priv, DSCC_PICTURE_PARAMETER_SET_9, 834 pps_val); 835 } else { 836 intel_de_write(dev_priv, 837 ICL_DSC0_PICTURE_PARAMETER_SET_9(pipe), 838 pps_val); 839 if (crtc_state->dsc.dsc_split) 840 intel_de_write(dev_priv, 841 ICL_DSC1_PICTURE_PARAMETER_SET_9(pipe), 842 pps_val); 843 } 844 845 /* Populate PICTURE_PARAMETER_SET_10 registers */ 846 pps_val = 0; 847 pps_val |= DSC_RC_QUANT_INC_LIMIT0(vdsc_cfg->rc_quant_incr_limit0) | 848 DSC_RC_QUANT_INC_LIMIT1(vdsc_cfg->rc_quant_incr_limit1) | 849 DSC_RC_TARGET_OFF_HIGH(DSC_RC_TGT_OFFSET_HI_CONST) | 850 DSC_RC_TARGET_OFF_LOW(DSC_RC_TGT_OFFSET_LO_CONST); 851 drm_dbg_kms(&dev_priv->drm, "PPS10 = 0x%08x\n", pps_val); 852 if (!is_pipe_dsc(crtc, cpu_transcoder)) { 853 intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_10, 854 pps_val); 855 /* 856 * If 2 VDSC instances are needed, configure PPS for second 857 * VDSC 858 */ 859 if (crtc_state->dsc.dsc_split) 860 intel_de_write(dev_priv, 861 DSCC_PICTURE_PARAMETER_SET_10, pps_val); 862 } else { 863 intel_de_write(dev_priv, 864 ICL_DSC0_PICTURE_PARAMETER_SET_10(pipe), 865 pps_val); 866 if (crtc_state->dsc.dsc_split) 867 intel_de_write(dev_priv, 868 ICL_DSC1_PICTURE_PARAMETER_SET_10(pipe), 869 pps_val); 870 } 871 872 /* Populate Picture parameter set 16 */ 873 pps_val = 0; 874 pps_val |= DSC_SLICE_CHUNK_SIZE(vdsc_cfg->slice_chunk_size) | 875 DSC_SLICE_PER_LINE((vdsc_cfg->pic_width / num_vdsc_instances) / 876 vdsc_cfg->slice_width) | 877 DSC_SLICE_ROW_PER_FRAME(vdsc_cfg->pic_height / 878 vdsc_cfg->slice_height); 879 drm_dbg_kms(&dev_priv->drm, "PPS16 = 0x%08x\n", pps_val); 880 if (!is_pipe_dsc(crtc, cpu_transcoder)) { 881 intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_16, 882 pps_val); 883 /* 884 * If 2 VDSC instances are needed, configure PPS for second 885 * VDSC 886 */ 887 if (crtc_state->dsc.dsc_split) 888 intel_de_write(dev_priv, 889 DSCC_PICTURE_PARAMETER_SET_16, pps_val); 890 } else { 891 intel_de_write(dev_priv, 892 ICL_DSC0_PICTURE_PARAMETER_SET_16(pipe), 893 pps_val); 894 if (crtc_state->dsc.dsc_split) 895 intel_de_write(dev_priv, 896 ICL_DSC1_PICTURE_PARAMETER_SET_16(pipe), 897 pps_val); 898 } 899 900 /* Populate the RC_BUF_THRESH registers */ 901 memset(rc_buf_thresh_dword, 0, sizeof(rc_buf_thresh_dword)); 902 for (i = 0; i < DSC_NUM_BUF_RANGES - 1; i++) { 903 rc_buf_thresh_dword[i / 4] |= 904 (u32)(vdsc_cfg->rc_buf_thresh[i] << 905 BITS_PER_BYTE * (i % 4)); 906 drm_dbg_kms(&dev_priv->drm, "RC_BUF_THRESH_%d = 0x%08x\n", i, 907 rc_buf_thresh_dword[i / 4]); 908 } 909 if (!is_pipe_dsc(crtc, cpu_transcoder)) { 910 intel_de_write(dev_priv, DSCA_RC_BUF_THRESH_0, 911 rc_buf_thresh_dword[0]); 912 intel_de_write(dev_priv, DSCA_RC_BUF_THRESH_0_UDW, 913 rc_buf_thresh_dword[1]); 914 intel_de_write(dev_priv, DSCA_RC_BUF_THRESH_1, 915 rc_buf_thresh_dword[2]); 916 intel_de_write(dev_priv, DSCA_RC_BUF_THRESH_1_UDW, 917 rc_buf_thresh_dword[3]); 918 if (crtc_state->dsc.dsc_split) { 919 intel_de_write(dev_priv, DSCC_RC_BUF_THRESH_0, 920 rc_buf_thresh_dword[0]); 921 intel_de_write(dev_priv, DSCC_RC_BUF_THRESH_0_UDW, 922 rc_buf_thresh_dword[1]); 923 intel_de_write(dev_priv, DSCC_RC_BUF_THRESH_1, 924 rc_buf_thresh_dword[2]); 925 intel_de_write(dev_priv, DSCC_RC_BUF_THRESH_1_UDW, 926 rc_buf_thresh_dword[3]); 927 } 928 } else { 929 intel_de_write(dev_priv, ICL_DSC0_RC_BUF_THRESH_0(pipe), 930 rc_buf_thresh_dword[0]); 931 intel_de_write(dev_priv, ICL_DSC0_RC_BUF_THRESH_0_UDW(pipe), 932 rc_buf_thresh_dword[1]); 933 intel_de_write(dev_priv, ICL_DSC0_RC_BUF_THRESH_1(pipe), 934 rc_buf_thresh_dword[2]); 935 intel_de_write(dev_priv, ICL_DSC0_RC_BUF_THRESH_1_UDW(pipe), 936 rc_buf_thresh_dword[3]); 937 if (crtc_state->dsc.dsc_split) { 938 intel_de_write(dev_priv, 939 ICL_DSC1_RC_BUF_THRESH_0(pipe), 940 rc_buf_thresh_dword[0]); 941 intel_de_write(dev_priv, 942 ICL_DSC1_RC_BUF_THRESH_0_UDW(pipe), 943 rc_buf_thresh_dword[1]); 944 intel_de_write(dev_priv, 945 ICL_DSC1_RC_BUF_THRESH_1(pipe), 946 rc_buf_thresh_dword[2]); 947 intel_de_write(dev_priv, 948 ICL_DSC1_RC_BUF_THRESH_1_UDW(pipe), 949 rc_buf_thresh_dword[3]); 950 } 951 } 952 953 /* Populate the RC_RANGE_PARAMETERS registers */ 954 memset(rc_range_params_dword, 0, sizeof(rc_range_params_dword)); 955 for (i = 0; i < DSC_NUM_BUF_RANGES; i++) { 956 rc_range_params_dword[i / 2] |= 957 (u32)(((vdsc_cfg->rc_range_params[i].range_bpg_offset << 958 RC_BPG_OFFSET_SHIFT) | 959 (vdsc_cfg->rc_range_params[i].range_max_qp << 960 RC_MAX_QP_SHIFT) | 961 (vdsc_cfg->rc_range_params[i].range_min_qp << 962 RC_MIN_QP_SHIFT)) << 16 * (i % 2)); 963 drm_dbg_kms(&dev_priv->drm, "RC_RANGE_PARAM_%d = 0x%08x\n", i, 964 rc_range_params_dword[i / 2]); 965 } 966 if (!is_pipe_dsc(crtc, cpu_transcoder)) { 967 intel_de_write(dev_priv, DSCA_RC_RANGE_PARAMETERS_0, 968 rc_range_params_dword[0]); 969 intel_de_write(dev_priv, DSCA_RC_RANGE_PARAMETERS_0_UDW, 970 rc_range_params_dword[1]); 971 intel_de_write(dev_priv, DSCA_RC_RANGE_PARAMETERS_1, 972 rc_range_params_dword[2]); 973 intel_de_write(dev_priv, DSCA_RC_RANGE_PARAMETERS_1_UDW, 974 rc_range_params_dword[3]); 975 intel_de_write(dev_priv, DSCA_RC_RANGE_PARAMETERS_2, 976 rc_range_params_dword[4]); 977 intel_de_write(dev_priv, DSCA_RC_RANGE_PARAMETERS_2_UDW, 978 rc_range_params_dword[5]); 979 intel_de_write(dev_priv, DSCA_RC_RANGE_PARAMETERS_3, 980 rc_range_params_dword[6]); 981 intel_de_write(dev_priv, DSCA_RC_RANGE_PARAMETERS_3_UDW, 982 rc_range_params_dword[7]); 983 if (crtc_state->dsc.dsc_split) { 984 intel_de_write(dev_priv, DSCC_RC_RANGE_PARAMETERS_0, 985 rc_range_params_dword[0]); 986 intel_de_write(dev_priv, 987 DSCC_RC_RANGE_PARAMETERS_0_UDW, 988 rc_range_params_dword[1]); 989 intel_de_write(dev_priv, DSCC_RC_RANGE_PARAMETERS_1, 990 rc_range_params_dword[2]); 991 intel_de_write(dev_priv, 992 DSCC_RC_RANGE_PARAMETERS_1_UDW, 993 rc_range_params_dword[3]); 994 intel_de_write(dev_priv, DSCC_RC_RANGE_PARAMETERS_2, 995 rc_range_params_dword[4]); 996 intel_de_write(dev_priv, 997 DSCC_RC_RANGE_PARAMETERS_2_UDW, 998 rc_range_params_dword[5]); 999 intel_de_write(dev_priv, DSCC_RC_RANGE_PARAMETERS_3, 1000 rc_range_params_dword[6]); 1001 intel_de_write(dev_priv, 1002 DSCC_RC_RANGE_PARAMETERS_3_UDW, 1003 rc_range_params_dword[7]); 1004 } 1005 } else { 1006 intel_de_write(dev_priv, ICL_DSC0_RC_RANGE_PARAMETERS_0(pipe), 1007 rc_range_params_dword[0]); 1008 intel_de_write(dev_priv, 1009 ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW(pipe), 1010 rc_range_params_dword[1]); 1011 intel_de_write(dev_priv, ICL_DSC0_RC_RANGE_PARAMETERS_1(pipe), 1012 rc_range_params_dword[2]); 1013 intel_de_write(dev_priv, 1014 ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW(pipe), 1015 rc_range_params_dword[3]); 1016 intel_de_write(dev_priv, ICL_DSC0_RC_RANGE_PARAMETERS_2(pipe), 1017 rc_range_params_dword[4]); 1018 intel_de_write(dev_priv, 1019 ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW(pipe), 1020 rc_range_params_dword[5]); 1021 intel_de_write(dev_priv, ICL_DSC0_RC_RANGE_PARAMETERS_3(pipe), 1022 rc_range_params_dword[6]); 1023 intel_de_write(dev_priv, 1024 ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW(pipe), 1025 rc_range_params_dword[7]); 1026 if (crtc_state->dsc.dsc_split) { 1027 intel_de_write(dev_priv, 1028 ICL_DSC1_RC_RANGE_PARAMETERS_0(pipe), 1029 rc_range_params_dword[0]); 1030 intel_de_write(dev_priv, 1031 ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW(pipe), 1032 rc_range_params_dword[1]); 1033 intel_de_write(dev_priv, 1034 ICL_DSC1_RC_RANGE_PARAMETERS_1(pipe), 1035 rc_range_params_dword[2]); 1036 intel_de_write(dev_priv, 1037 ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW(pipe), 1038 rc_range_params_dword[3]); 1039 intel_de_write(dev_priv, 1040 ICL_DSC1_RC_RANGE_PARAMETERS_2(pipe), 1041 rc_range_params_dword[4]); 1042 intel_de_write(dev_priv, 1043 ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW(pipe), 1044 rc_range_params_dword[5]); 1045 intel_de_write(dev_priv, 1046 ICL_DSC1_RC_RANGE_PARAMETERS_3(pipe), 1047 rc_range_params_dword[6]); 1048 intel_de_write(dev_priv, 1049 ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW(pipe), 1050 rc_range_params_dword[7]); 1051 } 1052 } 1053 } 1054 1055 void intel_dsc_dsi_pps_write(struct intel_encoder *encoder, 1056 const struct intel_crtc_state *crtc_state) 1057 { 1058 const struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config; 1059 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1060 struct mipi_dsi_device *dsi; 1061 struct drm_dsc_picture_parameter_set pps; 1062 enum port port; 1063 1064 if (!crtc_state->dsc.compression_enable) 1065 return; 1066 1067 drm_dsc_pps_payload_pack(&pps, vdsc_cfg); 1068 1069 for_each_dsi_port(port, intel_dsi->ports) { 1070 dsi = intel_dsi->dsi_hosts[port]->device; 1071 1072 mipi_dsi_picture_parameter_set(dsi, &pps); 1073 mipi_dsi_compression_mode(dsi, true); 1074 } 1075 } 1076 1077 void intel_dsc_dp_pps_write(struct intel_encoder *encoder, 1078 const struct intel_crtc_state *crtc_state) 1079 { 1080 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 1081 const struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config; 1082 struct drm_dsc_pps_infoframe dp_dsc_pps_sdp; 1083 1084 if (!crtc_state->dsc.compression_enable) 1085 return; 1086 1087 /* Prepare DP SDP PPS header as per DP 1.4 spec, Table 2-123 */ 1088 drm_dsc_dp_pps_header_init(&dp_dsc_pps_sdp.pps_header); 1089 1090 /* Fill the PPS payload bytes as per DSC spec 1.2 Table 4-1 */ 1091 drm_dsc_pps_payload_pack(&dp_dsc_pps_sdp.pps_payload, vdsc_cfg); 1092 1093 dig_port->write_infoframe(encoder, crtc_state, 1094 DP_SDP_PPS, &dp_dsc_pps_sdp, 1095 sizeof(dp_dsc_pps_sdp)); 1096 } 1097 1098 static i915_reg_t dss_ctl1_reg(struct intel_crtc *crtc, enum transcoder cpu_transcoder) 1099 { 1100 return is_pipe_dsc(crtc, cpu_transcoder) ? 1101 ICL_PIPE_DSS_CTL1(crtc->pipe) : DSS_CTL1; 1102 } 1103 1104 static i915_reg_t dss_ctl2_reg(struct intel_crtc *crtc, enum transcoder cpu_transcoder) 1105 { 1106 return is_pipe_dsc(crtc, cpu_transcoder) ? 1107 ICL_PIPE_DSS_CTL2(crtc->pipe) : DSS_CTL2; 1108 } 1109 1110 struct intel_crtc * 1111 intel_dsc_get_bigjoiner_secondary(const struct intel_crtc *primary_crtc) 1112 { 1113 return intel_crtc_for_pipe(to_i915(primary_crtc->base.dev), primary_crtc->pipe + 1); 1114 } 1115 1116 static struct intel_crtc * 1117 intel_dsc_get_bigjoiner_primary(const struct intel_crtc *secondary_crtc) 1118 { 1119 return intel_crtc_for_pipe(to_i915(secondary_crtc->base.dev), secondary_crtc->pipe - 1); 1120 } 1121 1122 void intel_uncompressed_joiner_enable(const struct intel_crtc_state *crtc_state) 1123 { 1124 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1125 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1126 u32 dss_ctl1_val = 0; 1127 1128 if (crtc_state->bigjoiner && !crtc_state->dsc.compression_enable) { 1129 if (crtc_state->bigjoiner_slave) 1130 dss_ctl1_val |= UNCOMPRESSED_JOINER_SLAVE; 1131 else 1132 dss_ctl1_val |= UNCOMPRESSED_JOINER_MASTER; 1133 1134 intel_de_write(dev_priv, dss_ctl1_reg(crtc, crtc_state->cpu_transcoder), dss_ctl1_val); 1135 } 1136 } 1137 1138 void intel_dsc_enable(const struct intel_crtc_state *crtc_state) 1139 { 1140 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1141 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1142 u32 dss_ctl1_val = 0; 1143 u32 dss_ctl2_val = 0; 1144 1145 if (!crtc_state->dsc.compression_enable) 1146 return; 1147 1148 intel_dsc_pps_configure(crtc_state); 1149 1150 dss_ctl2_val |= LEFT_BRANCH_VDSC_ENABLE; 1151 if (crtc_state->dsc.dsc_split) { 1152 dss_ctl2_val |= RIGHT_BRANCH_VDSC_ENABLE; 1153 dss_ctl1_val |= JOINER_ENABLE; 1154 } 1155 if (crtc_state->bigjoiner) { 1156 dss_ctl1_val |= BIG_JOINER_ENABLE; 1157 if (!crtc_state->bigjoiner_slave) 1158 dss_ctl1_val |= MASTER_BIG_JOINER_ENABLE; 1159 } 1160 intel_de_write(dev_priv, dss_ctl1_reg(crtc, crtc_state->cpu_transcoder), dss_ctl1_val); 1161 intel_de_write(dev_priv, dss_ctl2_reg(crtc, crtc_state->cpu_transcoder), dss_ctl2_val); 1162 } 1163 1164 void intel_dsc_disable(const struct intel_crtc_state *old_crtc_state) 1165 { 1166 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); 1167 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1168 1169 /* Disable only if either of them is enabled */ 1170 if (old_crtc_state->dsc.compression_enable || 1171 old_crtc_state->bigjoiner) { 1172 intel_de_write(dev_priv, dss_ctl1_reg(crtc, old_crtc_state->cpu_transcoder), 0); 1173 intel_de_write(dev_priv, dss_ctl2_reg(crtc, old_crtc_state->cpu_transcoder), 0); 1174 } 1175 } 1176 1177 void intel_uncompressed_joiner_get_config(struct intel_crtc_state *crtc_state) 1178 { 1179 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1180 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1181 u32 dss_ctl1; 1182 1183 dss_ctl1 = intel_de_read(dev_priv, dss_ctl1_reg(crtc, crtc_state->cpu_transcoder)); 1184 if (dss_ctl1 & UNCOMPRESSED_JOINER_MASTER) { 1185 crtc_state->bigjoiner = true; 1186 crtc_state->bigjoiner_linked_crtc = intel_dsc_get_bigjoiner_secondary(crtc); 1187 drm_WARN_ON(&dev_priv->drm, !crtc_state->bigjoiner_linked_crtc); 1188 } else if (dss_ctl1 & UNCOMPRESSED_JOINER_SLAVE) { 1189 crtc_state->bigjoiner = true; 1190 crtc_state->bigjoiner_slave = true; 1191 crtc_state->bigjoiner_linked_crtc = intel_dsc_get_bigjoiner_primary(crtc); 1192 drm_WARN_ON(&dev_priv->drm, !crtc_state->bigjoiner_linked_crtc); 1193 } 1194 } 1195 1196 void intel_dsc_get_config(struct intel_crtc_state *crtc_state) 1197 { 1198 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1199 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1200 struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config; 1201 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 1202 enum pipe pipe = crtc->pipe; 1203 enum intel_display_power_domain power_domain; 1204 intel_wakeref_t wakeref; 1205 u32 dss_ctl1, dss_ctl2, val; 1206 1207 if (!intel_dsc_source_support(crtc_state)) 1208 return; 1209 1210 power_domain = intel_dsc_power_domain(crtc, cpu_transcoder); 1211 1212 wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain); 1213 if (!wakeref) 1214 return; 1215 1216 dss_ctl1 = intel_de_read(dev_priv, dss_ctl1_reg(crtc, cpu_transcoder)); 1217 dss_ctl2 = intel_de_read(dev_priv, dss_ctl2_reg(crtc, cpu_transcoder)); 1218 1219 crtc_state->dsc.compression_enable = dss_ctl2 & LEFT_BRANCH_VDSC_ENABLE; 1220 if (!crtc_state->dsc.compression_enable) 1221 goto out; 1222 1223 crtc_state->dsc.dsc_split = (dss_ctl2 & RIGHT_BRANCH_VDSC_ENABLE) && 1224 (dss_ctl1 & JOINER_ENABLE); 1225 1226 if (dss_ctl1 & BIG_JOINER_ENABLE) { 1227 crtc_state->bigjoiner = true; 1228 1229 if (!(dss_ctl1 & MASTER_BIG_JOINER_ENABLE)) { 1230 crtc_state->bigjoiner_slave = true; 1231 crtc_state->bigjoiner_linked_crtc = intel_dsc_get_bigjoiner_primary(crtc); 1232 } else { 1233 crtc_state->bigjoiner_linked_crtc = intel_dsc_get_bigjoiner_secondary(crtc); 1234 } 1235 drm_WARN_ON(&dev_priv->drm, !crtc_state->bigjoiner_linked_crtc); 1236 } 1237 1238 /* FIXME: add more state readout as needed */ 1239 1240 /* PPS1 */ 1241 if (!is_pipe_dsc(crtc, cpu_transcoder)) 1242 val = intel_de_read(dev_priv, DSCA_PICTURE_PARAMETER_SET_1); 1243 else 1244 val = intel_de_read(dev_priv, 1245 ICL_DSC0_PICTURE_PARAMETER_SET_1(pipe)); 1246 vdsc_cfg->bits_per_pixel = val; 1247 crtc_state->dsc.compressed_bpp = vdsc_cfg->bits_per_pixel >> 4; 1248 out: 1249 intel_display_power_put(dev_priv, power_domain, wakeref); 1250 } 1251