1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2018 Intel Corporation 4 * 5 * Author: Gaurav K Singh <gaurav.k.singh@intel.com> 6 * Manasi Navare <manasi.d.navare@intel.com> 7 */ 8 9 #include "i915_drv.h" 10 #include "intel_de.h" 11 #include "intel_display_types.h" 12 #include "intel_dsi.h" 13 #include "intel_vdsc.h" 14 15 enum ROW_INDEX_BPP { 16 ROW_INDEX_6BPP = 0, 17 ROW_INDEX_8BPP, 18 ROW_INDEX_10BPP, 19 ROW_INDEX_12BPP, 20 ROW_INDEX_15BPP, 21 MAX_ROW_INDEX 22 }; 23 24 enum COLUMN_INDEX_BPC { 25 COLUMN_INDEX_8BPC = 0, 26 COLUMN_INDEX_10BPC, 27 COLUMN_INDEX_12BPC, 28 COLUMN_INDEX_14BPC, 29 COLUMN_INDEX_16BPC, 30 MAX_COLUMN_INDEX 31 }; 32 33 /* From DSC_v1.11 spec, rc_parameter_Set syntax element typically constant */ 34 static const u16 rc_buf_thresh[] = { 35 896, 1792, 2688, 3584, 4480, 5376, 6272, 6720, 7168, 7616, 36 7744, 7872, 8000, 8064 37 }; 38 39 struct rc_parameters { 40 u16 initial_xmit_delay; 41 u8 first_line_bpg_offset; 42 u16 initial_offset; 43 u8 flatness_min_qp; 44 u8 flatness_max_qp; 45 u8 rc_quant_incr_limit0; 46 u8 rc_quant_incr_limit1; 47 struct drm_dsc_rc_range_parameters rc_range_params[DSC_NUM_BUF_RANGES]; 48 }; 49 50 /* 51 * Selected Rate Control Related Parameter Recommended Values 52 * from DSC_v1.11 spec & C Model release: DSC_model_20161212 53 */ 54 static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = { 55 { 56 /* 6BPP/8BPC */ 57 { 768, 15, 6144, 3, 13, 11, 11, { 58 { 0, 4, 0 }, { 1, 6, -2 }, { 3, 8, -2 }, { 4, 8, -4 }, 59 { 5, 9, -6 }, { 5, 9, -6 }, { 6, 9, -6 }, { 6, 10, -8 }, 60 { 7, 11, -8 }, { 8, 12, -10 }, { 9, 12, -10 }, { 10, 12, -12 }, 61 { 10, 12, -12 }, { 11, 12, -12 }, { 13, 14, -12 } 62 } 63 }, 64 /* 6BPP/10BPC */ 65 { 768, 15, 6144, 7, 17, 15, 15, { 66 { 0, 8, 0 }, { 3, 10, -2 }, { 7, 12, -2 }, { 8, 12, -4 }, 67 { 9, 13, -6 }, { 9, 13, -6 }, { 10, 13, -6 }, { 10, 14, -8 }, 68 { 11, 15, -8 }, { 12, 16, -10 }, { 13, 16, -10 }, 69 { 14, 16, -12 }, { 14, 16, -12 }, { 15, 16, -12 }, 70 { 17, 18, -12 } 71 } 72 }, 73 /* 6BPP/12BPC */ 74 { 768, 15, 6144, 11, 21, 19, 19, { 75 { 0, 12, 0 }, { 5, 14, -2 }, { 11, 16, -2 }, { 12, 16, -4 }, 76 { 13, 17, -6 }, { 13, 17, -6 }, { 14, 17, -6 }, { 14, 18, -8 }, 77 { 15, 19, -8 }, { 16, 20, -10 }, { 17, 20, -10 }, 78 { 18, 20, -12 }, { 18, 20, -12 }, { 19, 20, -12 }, 79 { 21, 22, -12 } 80 } 81 }, 82 /* 6BPP/14BPC */ 83 { 768, 15, 6144, 15, 25, 23, 27, { 84 { 0, 16, 0 }, { 7, 18, -2 }, { 15, 20, -2 }, { 16, 20, -4 }, 85 { 17, 21, -6 }, { 17, 21, -6 }, { 18, 21, -6 }, { 18, 22, -8 }, 86 { 19, 23, -8 }, { 20, 24, -10 }, { 21, 24, -10 }, 87 { 22, 24, -12 }, { 22, 24, -12 }, { 23, 24, -12 }, 88 { 25, 26, -12 } 89 } 90 }, 91 /* 6BPP/16BPC */ 92 { 768, 15, 6144, 19, 29, 27, 27, { 93 { 0, 20, 0 }, { 9, 22, -2 }, { 19, 24, -2 }, { 20, 24, -4 }, 94 { 21, 25, -6 }, { 21, 25, -6 }, { 22, 25, -6 }, { 22, 26, -8 }, 95 { 23, 27, -8 }, { 24, 28, -10 }, { 25, 28, -10 }, 96 { 26, 28, -12 }, { 26, 28, -12 }, { 27, 28, -12 }, 97 { 29, 30, -12 } 98 } 99 }, 100 }, 101 { 102 /* 8BPP/8BPC */ 103 { 512, 12, 6144, 3, 12, 11, 11, { 104 { 0, 4, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 }, 105 { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 }, 106 { 3, 9, -8 }, { 3, 10, -10 }, { 5, 11, -10 }, { 5, 12, -12 }, 107 { 5, 13, -12 }, { 7, 13, -12 }, { 13, 15, -12 } 108 } 109 }, 110 /* 8BPP/10BPC */ 111 { 512, 12, 6144, 7, 16, 15, 15, { 112 { 0, 4, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 5, 10, -2 }, 113 { 7, 11, -4 }, { 7, 11, -6 }, { 7, 11, -8 }, { 7, 12, -8 }, 114 { 7, 13, -8 }, { 7, 14, -10 }, { 9, 15, -10 }, { 9, 16, -12 }, 115 { 9, 17, -12 }, { 11, 17, -12 }, { 17, 19, -12 } 116 } 117 }, 118 /* 8BPP/12BPC */ 119 { 512, 12, 6144, 11, 20, 19, 19, { 120 { 0, 12, 2 }, { 4, 12, 0 }, { 9, 13, 0 }, { 9, 14, -2 }, 121 { 11, 15, -4 }, { 11, 15, -6 }, { 11, 15, -8 }, { 11, 16, -8 }, 122 { 11, 17, -8 }, { 11, 18, -10 }, { 13, 19, -10 }, 123 { 13, 20, -12 }, { 13, 21, -12 }, { 15, 21, -12 }, 124 { 21, 23, -12 } 125 } 126 }, 127 /* 8BPP/14BPC */ 128 { 512, 12, 6144, 15, 24, 23, 23, { 129 { 0, 12, 0 }, { 5, 13, 0 }, { 11, 15, 0 }, { 12, 17, -2 }, 130 { 15, 19, -4 }, { 15, 19, -6 }, { 15, 19, -8 }, { 15, 20, -8 }, 131 { 15, 21, -8 }, { 15, 22, -10 }, { 17, 22, -10 }, 132 { 17, 23, -12 }, { 17, 23, -12 }, { 21, 24, -12 }, 133 { 24, 25, -12 } 134 } 135 }, 136 /* 8BPP/16BPC */ 137 { 512, 12, 6144, 19, 28, 27, 27, { 138 { 0, 12, 2 }, { 6, 14, 0 }, { 13, 17, 0 }, { 15, 20, -2 }, 139 { 19, 23, -4 }, { 19, 23, -6 }, { 19, 23, -8 }, { 19, 24, -8 }, 140 { 19, 25, -8 }, { 19, 26, -10 }, { 21, 26, -10 }, 141 { 21, 27, -12 }, { 21, 27, -12 }, { 25, 28, -12 }, 142 { 28, 29, -12 } 143 } 144 }, 145 }, 146 { 147 /* 10BPP/8BPC */ 148 { 410, 15, 5632, 3, 12, 11, 11, { 149 { 0, 3, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 2, 6, -2 }, 150 { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 }, 151 { 3, 9, -8 }, { 3, 9, -10 }, { 5, 10, -10 }, { 5, 10, -10 }, 152 { 5, 11, -12 }, { 7, 11, -12 }, { 11, 12, -12 } 153 } 154 }, 155 /* 10BPP/10BPC */ 156 { 410, 15, 5632, 7, 16, 15, 15, { 157 { 0, 7, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 6, 10, -2 }, 158 { 7, 11, -4 }, { 7, 11, -6 }, { 7, 11, -8 }, { 7, 12, -8 }, 159 { 7, 13, -8 }, { 7, 13, -10 }, { 9, 14, -10 }, { 9, 14, -10 }, 160 { 9, 15, -12 }, { 11, 15, -12 }, { 15, 16, -12 } 161 } 162 }, 163 /* 10BPP/12BPC */ 164 { 410, 15, 5632, 11, 20, 19, 19, { 165 { 0, 11, 2 }, { 4, 12, 0 }, { 9, 13, 0 }, { 10, 14, -2 }, 166 { 11, 15, -4 }, { 11, 15, -6 }, { 11, 15, -8 }, { 11, 16, -8 }, 167 { 11, 17, -8 }, { 11, 17, -10 }, { 13, 18, -10 }, 168 { 13, 18, -10 }, { 13, 19, -12 }, { 15, 19, -12 }, 169 { 19, 20, -12 } 170 } 171 }, 172 /* 10BPP/14BPC */ 173 { 410, 15, 5632, 15, 24, 23, 23, { 174 { 0, 11, 2 }, { 5, 13, 0 }, { 11, 15, 0 }, { 13, 18, -2 }, 175 { 15, 19, -4 }, { 15, 19, -6 }, { 15, 19, -8 }, { 15, 20, -8 }, 176 { 15, 21, -8 }, { 15, 21, -10 }, { 17, 22, -10 }, 177 { 17, 22, -10 }, { 17, 23, -12 }, { 19, 23, -12 }, 178 { 23, 24, -12 } 179 } 180 }, 181 /* 10BPP/16BPC */ 182 { 410, 15, 5632, 19, 28, 27, 27, { 183 { 0, 11, 2 }, { 6, 14, 0 }, { 13, 17, 0 }, { 16, 20, -2 }, 184 { 19, 23, -4 }, { 19, 23, -6 }, { 19, 23, -8 }, { 19, 24, -8 }, 185 { 19, 25, -8 }, { 19, 25, -10 }, { 21, 26, -10 }, 186 { 21, 26, -10 }, { 21, 27, -12 }, { 23, 27, -12 }, 187 { 27, 28, -12 } 188 } 189 }, 190 }, 191 { 192 /* 12BPP/8BPC */ 193 { 341, 15, 2048, 3, 12, 11, 11, { 194 { 0, 2, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 }, 195 { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 }, 196 { 3, 9, -8 }, { 3, 10, -10 }, { 5, 11, -10 }, 197 { 5, 12, -12 }, { 5, 13, -12 }, { 7, 13, -12 }, { 13, 15, -12 } 198 } 199 }, 200 /* 12BPP/10BPC */ 201 { 341, 15, 2048, 7, 16, 15, 15, { 202 { 0, 2, 2 }, { 2, 5, 0 }, { 3, 7, 0 }, { 4, 8, -2 }, 203 { 6, 9, -4 }, { 7, 10, -6 }, { 7, 11, -8 }, { 7, 12, -8 }, 204 { 7, 13, -8 }, { 7, 14, -10 }, { 9, 15, -10 }, { 9, 16, -12 }, 205 { 9, 17, -12 }, { 11, 17, -12 }, { 17, 19, -12 } 206 } 207 }, 208 /* 12BPP/12BPC */ 209 { 341, 15, 2048, 11, 20, 19, 19, { 210 { 0, 6, 2 }, { 4, 9, 0 }, { 7, 11, 0 }, { 8, 12, -2 }, 211 { 10, 13, -4 }, { 11, 14, -6 }, { 11, 15, -8 }, { 11, 16, -8 }, 212 { 11, 17, -8 }, { 11, 18, -10 }, { 13, 19, -10 }, 213 { 13, 20, -12 }, { 13, 21, -12 }, { 15, 21, -12 }, 214 { 21, 23, -12 } 215 } 216 }, 217 /* 12BPP/14BPC */ 218 { 341, 15, 2048, 15, 24, 23, 23, { 219 { 0, 6, 2 }, { 7, 10, 0 }, { 9, 13, 0 }, { 11, 16, -2 }, 220 { 14, 17, -4 }, { 15, 18, -6 }, { 15, 19, -8 }, { 15, 20, -8 }, 221 { 15, 20, -8 }, { 15, 21, -10 }, { 17, 21, -10 }, 222 { 17, 21, -12 }, { 17, 21, -12 }, { 19, 22, -12 }, 223 { 22, 23, -12 } 224 } 225 }, 226 /* 12BPP/16BPC */ 227 { 341, 15, 2048, 19, 28, 27, 27, { 228 { 0, 6, 2 }, { 6, 11, 0 }, { 11, 15, 0 }, { 14, 18, -2 }, 229 { 18, 21, -4 }, { 19, 22, -6 }, { 19, 23, -8 }, { 19, 24, -8 }, 230 { 19, 24, -8 }, { 19, 25, -10 }, { 21, 25, -10 }, 231 { 21, 25, -12 }, { 21, 25, -12 }, { 23, 26, -12 }, 232 { 26, 27, -12 } 233 } 234 }, 235 }, 236 { 237 /* 15BPP/8BPC */ 238 { 273, 15, 2048, 3, 12, 11, 11, { 239 { 0, 0, 10 }, { 0, 1, 8 }, { 0, 1, 6 }, { 0, 2, 4 }, 240 { 1, 2, 2 }, { 1, 3, 0 }, { 1, 3, -2 }, { 2, 4, -4 }, 241 { 2, 5, -6 }, { 3, 5, -8 }, { 4, 6, -10 }, { 4, 7, -10 }, 242 { 5, 7, -12 }, { 7, 8, -12 }, { 8, 9, -12 } 243 } 244 }, 245 /* 15BPP/10BPC */ 246 { 273, 15, 2048, 7, 16, 15, 15, { 247 { 0, 2, 10 }, { 2, 5, 8 }, { 3, 5, 6 }, { 4, 6, 4 }, 248 { 5, 6, 2 }, { 5, 7, 0 }, { 5, 7, -2 }, { 6, 8, -4 }, 249 { 6, 9, -6 }, { 7, 9, -8 }, { 8, 10, -10 }, { 8, 11, -10 }, 250 { 9, 11, -12 }, { 11, 12, -12 }, { 12, 13, -12 } 251 } 252 }, 253 /* 15BPP/12BPC */ 254 { 273, 15, 2048, 11, 20, 19, 19, { 255 { 0, 4, 10 }, { 2, 7, 8 }, { 4, 9, 6 }, { 6, 11, 4 }, 256 { 9, 11, 2 }, { 9, 11, 0 }, { 9, 12, -2 }, { 10, 12, -4 }, 257 { 11, 13, -6 }, { 11, 13, -8 }, { 12, 14, -10 }, 258 { 13, 15, -10 }, { 13, 15, -12 }, { 15, 16, -12 }, 259 { 16, 17, -12 } 260 } 261 }, 262 /* 15BPP/14BPC */ 263 { 273, 15, 2048, 15, 24, 23, 23, { 264 { 0, 4, 10 }, { 3, 8, 8 }, { 6, 11, 6 }, { 9, 14, 4 }, 265 { 13, 15, 2 }, { 13, 15, 0 }, { 13, 16, -2 }, { 14, 16, -4 }, 266 { 15, 17, -6 }, { 15, 17, -8 }, { 16, 18, -10 }, 267 { 17, 19, -10 }, { 17, 19, -12 }, { 19, 20, -12 }, 268 { 20, 21, -12 } 269 } 270 }, 271 /* 15BPP/16BPC */ 272 { 273, 15, 2048, 19, 28, 27, 27, { 273 { 0, 4, 10 }, { 4, 9, 8 }, { 8, 13, 6 }, { 12, 17, 4 }, 274 { 17, 19, 2 }, { 17, 20, 0 }, { 17, 20, -2 }, { 18, 20, -4 }, 275 { 19, 21, -6 }, { 19, 21, -8 }, { 20, 22, -10 }, 276 { 21, 23, -10 }, { 21, 23, -12 }, { 23, 24, -12 }, 277 { 24, 25, -12 } 278 } 279 } 280 } 281 282 }; 283 284 static int get_row_index_for_rc_params(u16 compressed_bpp) 285 { 286 switch (compressed_bpp) { 287 case 6: 288 return ROW_INDEX_6BPP; 289 case 8: 290 return ROW_INDEX_8BPP; 291 case 10: 292 return ROW_INDEX_10BPP; 293 case 12: 294 return ROW_INDEX_12BPP; 295 case 15: 296 return ROW_INDEX_15BPP; 297 default: 298 return -EINVAL; 299 } 300 } 301 302 static int get_column_index_for_rc_params(u8 bits_per_component) 303 { 304 switch (bits_per_component) { 305 case 8: 306 return COLUMN_INDEX_8BPC; 307 case 10: 308 return COLUMN_INDEX_10BPC; 309 case 12: 310 return COLUMN_INDEX_12BPC; 311 case 14: 312 return COLUMN_INDEX_14BPC; 313 case 16: 314 return COLUMN_INDEX_16BPC; 315 default: 316 return -EINVAL; 317 } 318 } 319 320 static const struct rc_parameters *get_rc_params(u16 compressed_bpp, 321 u8 bits_per_component) 322 { 323 int row_index, column_index; 324 325 row_index = get_row_index_for_rc_params(compressed_bpp); 326 if (row_index < 0) 327 return NULL; 328 329 column_index = get_column_index_for_rc_params(bits_per_component); 330 if (column_index < 0) 331 return NULL; 332 333 return &rc_parameters[row_index][column_index]; 334 } 335 336 bool intel_dsc_source_support(const struct intel_crtc_state *crtc_state) 337 { 338 const struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 339 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 340 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 341 enum pipe pipe = crtc->pipe; 342 343 if (!INTEL_INFO(i915)->display.has_dsc) 344 return false; 345 346 /* On TGL, DSC is supported on all Pipes */ 347 if (DISPLAY_VER(i915) >= 12) 348 return true; 349 350 if ((DISPLAY_VER(i915) >= 11 || IS_CANNONLAKE(i915)) && (pipe != PIPE_A || (cpu_transcoder == TRANSCODER_EDP || cpu_transcoder == TRANSCODER_DSI_0 || cpu_transcoder == TRANSCODER_DSI_1))) 351 return true; 352 353 return false; 354 } 355 356 static bool is_pipe_dsc(const struct intel_crtc_state *crtc_state) 357 { 358 const struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 359 const struct drm_i915_private *i915 = to_i915(crtc->base.dev); 360 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 361 362 if (DISPLAY_VER(i915) >= 12) 363 return true; 364 365 if (cpu_transcoder == TRANSCODER_EDP || 366 cpu_transcoder == TRANSCODER_DSI_0 || 367 cpu_transcoder == TRANSCODER_DSI_1) 368 return false; 369 370 /* There's no pipe A DSC engine on ICL */ 371 drm_WARN_ON(&i915->drm, crtc->pipe == PIPE_A); 372 373 return true; 374 } 375 376 int intel_dsc_compute_params(struct intel_encoder *encoder, 377 struct intel_crtc_state *pipe_config) 378 { 379 struct drm_dsc_config *vdsc_cfg = &pipe_config->dsc.config; 380 u16 compressed_bpp = pipe_config->dsc.compressed_bpp; 381 const struct rc_parameters *rc_params; 382 u8 i = 0; 383 384 vdsc_cfg->pic_width = pipe_config->hw.adjusted_mode.crtc_hdisplay; 385 vdsc_cfg->pic_height = pipe_config->hw.adjusted_mode.crtc_vdisplay; 386 vdsc_cfg->slice_width = DIV_ROUND_UP(vdsc_cfg->pic_width, 387 pipe_config->dsc.slice_count); 388 389 /* Gen 11 does not support YCbCr */ 390 vdsc_cfg->simple_422 = false; 391 /* Gen 11 does not support VBR */ 392 vdsc_cfg->vbr_enable = false; 393 394 /* Gen 11 only supports integral values of bpp */ 395 vdsc_cfg->bits_per_pixel = compressed_bpp << 4; 396 vdsc_cfg->bits_per_component = pipe_config->pipe_bpp / 3; 397 398 for (i = 0; i < DSC_NUM_BUF_RANGES - 1; i++) { 399 /* 400 * six 0s are appended to the lsb of each threshold value 401 * internally in h/w. 402 * Only 8 bits are allowed for programming RcBufThreshold 403 */ 404 vdsc_cfg->rc_buf_thresh[i] = rc_buf_thresh[i] >> 6; 405 } 406 407 /* 408 * For 6bpp, RC Buffer threshold 12 and 13 need a different value 409 * as per C Model 410 */ 411 if (compressed_bpp == 6) { 412 vdsc_cfg->rc_buf_thresh[12] = 0x7C; 413 vdsc_cfg->rc_buf_thresh[13] = 0x7D; 414 } 415 416 rc_params = get_rc_params(compressed_bpp, vdsc_cfg->bits_per_component); 417 if (!rc_params) 418 return -EINVAL; 419 420 vdsc_cfg->first_line_bpg_offset = rc_params->first_line_bpg_offset; 421 vdsc_cfg->initial_xmit_delay = rc_params->initial_xmit_delay; 422 vdsc_cfg->initial_offset = rc_params->initial_offset; 423 vdsc_cfg->flatness_min_qp = rc_params->flatness_min_qp; 424 vdsc_cfg->flatness_max_qp = rc_params->flatness_max_qp; 425 vdsc_cfg->rc_quant_incr_limit0 = rc_params->rc_quant_incr_limit0; 426 vdsc_cfg->rc_quant_incr_limit1 = rc_params->rc_quant_incr_limit1; 427 428 for (i = 0; i < DSC_NUM_BUF_RANGES; i++) { 429 vdsc_cfg->rc_range_params[i].range_min_qp = 430 rc_params->rc_range_params[i].range_min_qp; 431 vdsc_cfg->rc_range_params[i].range_max_qp = 432 rc_params->rc_range_params[i].range_max_qp; 433 /* 434 * Range BPG Offset uses 2's complement and is only a 6 bits. So 435 * mask it to get only 6 bits. 436 */ 437 vdsc_cfg->rc_range_params[i].range_bpg_offset = 438 rc_params->rc_range_params[i].range_bpg_offset & 439 DSC_RANGE_BPG_OFFSET_MASK; 440 } 441 442 /* 443 * BitsPerComponent value determines mux_word_size: 444 * When BitsPerComponent is 12bpc, muxWordSize will be equal to 64 bits 445 * When BitsPerComponent is 8 or 10bpc, muxWordSize will be equal to 446 * 48 bits 447 */ 448 if (vdsc_cfg->bits_per_component == 8 || 449 vdsc_cfg->bits_per_component == 10) 450 vdsc_cfg->mux_word_size = DSC_MUX_WORD_SIZE_8_10_BPC; 451 else if (vdsc_cfg->bits_per_component == 12) 452 vdsc_cfg->mux_word_size = DSC_MUX_WORD_SIZE_12_BPC; 453 454 /* InitialScaleValue is a 6 bit value with 3 fractional bits (U3.3) */ 455 vdsc_cfg->initial_scale_value = (vdsc_cfg->rc_model_size << 3) / 456 (vdsc_cfg->rc_model_size - vdsc_cfg->initial_offset); 457 458 return 0; 459 } 460 461 enum intel_display_power_domain 462 intel_dsc_power_domain(const struct intel_crtc_state *crtc_state) 463 { 464 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 465 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 466 enum pipe pipe = crtc->pipe; 467 468 /* 469 * VDSC/joining uses a separate power well, PW2, and requires 470 * POWER_DOMAIN_TRANSCODER_VDSC_PW2 power domain in two cases: 471 * 472 * - ICL eDP/DSI transcoder 473 * - Display version 12 (except RKL) pipe A 474 * 475 * For any other pipe, VDSC/joining uses the power well associated with 476 * the pipe in use. Hence another reference on the pipe power domain 477 * will suffice. (Except no VDSC/joining on ICL pipe A.) 478 */ 479 if (DISPLAY_VER(i915) == 12 && !IS_ROCKETLAKE(i915) && pipe == PIPE_A) 480 return POWER_DOMAIN_TRANSCODER_VDSC_PW2; 481 else if (is_pipe_dsc(crtc_state)) 482 return POWER_DOMAIN_PIPE(pipe); 483 else 484 return POWER_DOMAIN_TRANSCODER_VDSC_PW2; 485 } 486 487 static void intel_dsc_pps_configure(const struct intel_crtc_state *crtc_state) 488 { 489 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 490 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 491 const struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config; 492 enum pipe pipe = crtc->pipe; 493 u32 pps_val = 0; 494 u32 rc_buf_thresh_dword[4]; 495 u32 rc_range_params_dword[8]; 496 u8 num_vdsc_instances = (crtc_state->dsc.dsc_split) ? 2 : 1; 497 int i = 0; 498 499 if (crtc_state->bigjoiner) 500 num_vdsc_instances *= 2; 501 502 /* Populate PICTURE_PARAMETER_SET_0 registers */ 503 pps_val = DSC_VER_MAJ | vdsc_cfg->dsc_version_minor << 504 DSC_VER_MIN_SHIFT | 505 vdsc_cfg->bits_per_component << DSC_BPC_SHIFT | 506 vdsc_cfg->line_buf_depth << DSC_LINE_BUF_DEPTH_SHIFT; 507 if (vdsc_cfg->block_pred_enable) 508 pps_val |= DSC_BLOCK_PREDICTION; 509 if (vdsc_cfg->convert_rgb) 510 pps_val |= DSC_COLOR_SPACE_CONVERSION; 511 if (vdsc_cfg->simple_422) 512 pps_val |= DSC_422_ENABLE; 513 if (vdsc_cfg->vbr_enable) 514 pps_val |= DSC_VBR_ENABLE; 515 drm_info(&dev_priv->drm, "PPS0 = 0x%08x\n", pps_val); 516 if (!is_pipe_dsc(crtc_state)) { 517 intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_0, 518 pps_val); 519 /* 520 * If 2 VDSC instances are needed, configure PPS for second 521 * VDSC 522 */ 523 if (crtc_state->dsc.dsc_split) 524 intel_de_write(dev_priv, DSCC_PICTURE_PARAMETER_SET_0, 525 pps_val); 526 } else { 527 intel_de_write(dev_priv, 528 ICL_DSC0_PICTURE_PARAMETER_SET_0(pipe), 529 pps_val); 530 if (crtc_state->dsc.dsc_split) 531 intel_de_write(dev_priv, 532 ICL_DSC1_PICTURE_PARAMETER_SET_0(pipe), 533 pps_val); 534 } 535 536 /* Populate PICTURE_PARAMETER_SET_1 registers */ 537 pps_val = 0; 538 pps_val |= DSC_BPP(vdsc_cfg->bits_per_pixel); 539 drm_info(&dev_priv->drm, "PPS1 = 0x%08x\n", pps_val); 540 if (!is_pipe_dsc(crtc_state)) { 541 intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_1, 542 pps_val); 543 /* 544 * If 2 VDSC instances are needed, configure PPS for second 545 * VDSC 546 */ 547 if (crtc_state->dsc.dsc_split) 548 intel_de_write(dev_priv, DSCC_PICTURE_PARAMETER_SET_1, 549 pps_val); 550 } else { 551 intel_de_write(dev_priv, 552 ICL_DSC0_PICTURE_PARAMETER_SET_1(pipe), 553 pps_val); 554 if (crtc_state->dsc.dsc_split) 555 intel_de_write(dev_priv, 556 ICL_DSC1_PICTURE_PARAMETER_SET_1(pipe), 557 pps_val); 558 } 559 560 /* Populate PICTURE_PARAMETER_SET_2 registers */ 561 pps_val = 0; 562 pps_val |= DSC_PIC_HEIGHT(vdsc_cfg->pic_height) | 563 DSC_PIC_WIDTH(vdsc_cfg->pic_width / num_vdsc_instances); 564 drm_info(&dev_priv->drm, "PPS2 = 0x%08x\n", pps_val); 565 if (!is_pipe_dsc(crtc_state)) { 566 intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_2, 567 pps_val); 568 /* 569 * If 2 VDSC instances are needed, configure PPS for second 570 * VDSC 571 */ 572 if (crtc_state->dsc.dsc_split) 573 intel_de_write(dev_priv, DSCC_PICTURE_PARAMETER_SET_2, 574 pps_val); 575 } else { 576 intel_de_write(dev_priv, 577 ICL_DSC0_PICTURE_PARAMETER_SET_2(pipe), 578 pps_val); 579 if (crtc_state->dsc.dsc_split) 580 intel_de_write(dev_priv, 581 ICL_DSC1_PICTURE_PARAMETER_SET_2(pipe), 582 pps_val); 583 } 584 585 /* Populate PICTURE_PARAMETER_SET_3 registers */ 586 pps_val = 0; 587 pps_val |= DSC_SLICE_HEIGHT(vdsc_cfg->slice_height) | 588 DSC_SLICE_WIDTH(vdsc_cfg->slice_width); 589 drm_info(&dev_priv->drm, "PPS3 = 0x%08x\n", pps_val); 590 if (!is_pipe_dsc(crtc_state)) { 591 intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_3, 592 pps_val); 593 /* 594 * If 2 VDSC instances are needed, configure PPS for second 595 * VDSC 596 */ 597 if (crtc_state->dsc.dsc_split) 598 intel_de_write(dev_priv, DSCC_PICTURE_PARAMETER_SET_3, 599 pps_val); 600 } else { 601 intel_de_write(dev_priv, 602 ICL_DSC0_PICTURE_PARAMETER_SET_3(pipe), 603 pps_val); 604 if (crtc_state->dsc.dsc_split) 605 intel_de_write(dev_priv, 606 ICL_DSC1_PICTURE_PARAMETER_SET_3(pipe), 607 pps_val); 608 } 609 610 /* Populate PICTURE_PARAMETER_SET_4 registers */ 611 pps_val = 0; 612 pps_val |= DSC_INITIAL_XMIT_DELAY(vdsc_cfg->initial_xmit_delay) | 613 DSC_INITIAL_DEC_DELAY(vdsc_cfg->initial_dec_delay); 614 drm_info(&dev_priv->drm, "PPS4 = 0x%08x\n", pps_val); 615 if (!is_pipe_dsc(crtc_state)) { 616 intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_4, 617 pps_val); 618 /* 619 * If 2 VDSC instances are needed, configure PPS for second 620 * VDSC 621 */ 622 if (crtc_state->dsc.dsc_split) 623 intel_de_write(dev_priv, DSCC_PICTURE_PARAMETER_SET_4, 624 pps_val); 625 } else { 626 intel_de_write(dev_priv, 627 ICL_DSC0_PICTURE_PARAMETER_SET_4(pipe), 628 pps_val); 629 if (crtc_state->dsc.dsc_split) 630 intel_de_write(dev_priv, 631 ICL_DSC1_PICTURE_PARAMETER_SET_4(pipe), 632 pps_val); 633 } 634 635 /* Populate PICTURE_PARAMETER_SET_5 registers */ 636 pps_val = 0; 637 pps_val |= DSC_SCALE_INC_INT(vdsc_cfg->scale_increment_interval) | 638 DSC_SCALE_DEC_INT(vdsc_cfg->scale_decrement_interval); 639 drm_info(&dev_priv->drm, "PPS5 = 0x%08x\n", pps_val); 640 if (!is_pipe_dsc(crtc_state)) { 641 intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_5, 642 pps_val); 643 /* 644 * If 2 VDSC instances are needed, configure PPS for second 645 * VDSC 646 */ 647 if (crtc_state->dsc.dsc_split) 648 intel_de_write(dev_priv, DSCC_PICTURE_PARAMETER_SET_5, 649 pps_val); 650 } else { 651 intel_de_write(dev_priv, 652 ICL_DSC0_PICTURE_PARAMETER_SET_5(pipe), 653 pps_val); 654 if (crtc_state->dsc.dsc_split) 655 intel_de_write(dev_priv, 656 ICL_DSC1_PICTURE_PARAMETER_SET_5(pipe), 657 pps_val); 658 } 659 660 /* Populate PICTURE_PARAMETER_SET_6 registers */ 661 pps_val = 0; 662 pps_val |= DSC_INITIAL_SCALE_VALUE(vdsc_cfg->initial_scale_value) | 663 DSC_FIRST_LINE_BPG_OFFSET(vdsc_cfg->first_line_bpg_offset) | 664 DSC_FLATNESS_MIN_QP(vdsc_cfg->flatness_min_qp) | 665 DSC_FLATNESS_MAX_QP(vdsc_cfg->flatness_max_qp); 666 drm_info(&dev_priv->drm, "PPS6 = 0x%08x\n", pps_val); 667 if (!is_pipe_dsc(crtc_state)) { 668 intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_6, 669 pps_val); 670 /* 671 * If 2 VDSC instances are needed, configure PPS for second 672 * VDSC 673 */ 674 if (crtc_state->dsc.dsc_split) 675 intel_de_write(dev_priv, DSCC_PICTURE_PARAMETER_SET_6, 676 pps_val); 677 } else { 678 intel_de_write(dev_priv, 679 ICL_DSC0_PICTURE_PARAMETER_SET_6(pipe), 680 pps_val); 681 if (crtc_state->dsc.dsc_split) 682 intel_de_write(dev_priv, 683 ICL_DSC1_PICTURE_PARAMETER_SET_6(pipe), 684 pps_val); 685 } 686 687 /* Populate PICTURE_PARAMETER_SET_7 registers */ 688 pps_val = 0; 689 pps_val |= DSC_SLICE_BPG_OFFSET(vdsc_cfg->slice_bpg_offset) | 690 DSC_NFL_BPG_OFFSET(vdsc_cfg->nfl_bpg_offset); 691 drm_info(&dev_priv->drm, "PPS7 = 0x%08x\n", pps_val); 692 if (!is_pipe_dsc(crtc_state)) { 693 intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_7, 694 pps_val); 695 /* 696 * If 2 VDSC instances are needed, configure PPS for second 697 * VDSC 698 */ 699 if (crtc_state->dsc.dsc_split) 700 intel_de_write(dev_priv, DSCC_PICTURE_PARAMETER_SET_7, 701 pps_val); 702 } else { 703 intel_de_write(dev_priv, 704 ICL_DSC0_PICTURE_PARAMETER_SET_7(pipe), 705 pps_val); 706 if (crtc_state->dsc.dsc_split) 707 intel_de_write(dev_priv, 708 ICL_DSC1_PICTURE_PARAMETER_SET_7(pipe), 709 pps_val); 710 } 711 712 /* Populate PICTURE_PARAMETER_SET_8 registers */ 713 pps_val = 0; 714 pps_val |= DSC_FINAL_OFFSET(vdsc_cfg->final_offset) | 715 DSC_INITIAL_OFFSET(vdsc_cfg->initial_offset); 716 drm_info(&dev_priv->drm, "PPS8 = 0x%08x\n", pps_val); 717 if (!is_pipe_dsc(crtc_state)) { 718 intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_8, 719 pps_val); 720 /* 721 * If 2 VDSC instances are needed, configure PPS for second 722 * VDSC 723 */ 724 if (crtc_state->dsc.dsc_split) 725 intel_de_write(dev_priv, DSCC_PICTURE_PARAMETER_SET_8, 726 pps_val); 727 } else { 728 intel_de_write(dev_priv, 729 ICL_DSC0_PICTURE_PARAMETER_SET_8(pipe), 730 pps_val); 731 if (crtc_state->dsc.dsc_split) 732 intel_de_write(dev_priv, 733 ICL_DSC1_PICTURE_PARAMETER_SET_8(pipe), 734 pps_val); 735 } 736 737 /* Populate PICTURE_PARAMETER_SET_9 registers */ 738 pps_val = 0; 739 pps_val |= DSC_RC_MODEL_SIZE(vdsc_cfg->rc_model_size) | 740 DSC_RC_EDGE_FACTOR(DSC_RC_EDGE_FACTOR_CONST); 741 drm_info(&dev_priv->drm, "PPS9 = 0x%08x\n", pps_val); 742 if (!is_pipe_dsc(crtc_state)) { 743 intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_9, 744 pps_val); 745 /* 746 * If 2 VDSC instances are needed, configure PPS for second 747 * VDSC 748 */ 749 if (crtc_state->dsc.dsc_split) 750 intel_de_write(dev_priv, DSCC_PICTURE_PARAMETER_SET_9, 751 pps_val); 752 } else { 753 intel_de_write(dev_priv, 754 ICL_DSC0_PICTURE_PARAMETER_SET_9(pipe), 755 pps_val); 756 if (crtc_state->dsc.dsc_split) 757 intel_de_write(dev_priv, 758 ICL_DSC1_PICTURE_PARAMETER_SET_9(pipe), 759 pps_val); 760 } 761 762 /* Populate PICTURE_PARAMETER_SET_10 registers */ 763 pps_val = 0; 764 pps_val |= DSC_RC_QUANT_INC_LIMIT0(vdsc_cfg->rc_quant_incr_limit0) | 765 DSC_RC_QUANT_INC_LIMIT1(vdsc_cfg->rc_quant_incr_limit1) | 766 DSC_RC_TARGET_OFF_HIGH(DSC_RC_TGT_OFFSET_HI_CONST) | 767 DSC_RC_TARGET_OFF_LOW(DSC_RC_TGT_OFFSET_LO_CONST); 768 drm_info(&dev_priv->drm, "PPS10 = 0x%08x\n", pps_val); 769 if (!is_pipe_dsc(crtc_state)) { 770 intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_10, 771 pps_val); 772 /* 773 * If 2 VDSC instances are needed, configure PPS for second 774 * VDSC 775 */ 776 if (crtc_state->dsc.dsc_split) 777 intel_de_write(dev_priv, 778 DSCC_PICTURE_PARAMETER_SET_10, pps_val); 779 } else { 780 intel_de_write(dev_priv, 781 ICL_DSC0_PICTURE_PARAMETER_SET_10(pipe), 782 pps_val); 783 if (crtc_state->dsc.dsc_split) 784 intel_de_write(dev_priv, 785 ICL_DSC1_PICTURE_PARAMETER_SET_10(pipe), 786 pps_val); 787 } 788 789 /* Populate Picture parameter set 16 */ 790 pps_val = 0; 791 pps_val |= DSC_SLICE_CHUNK_SIZE(vdsc_cfg->slice_chunk_size) | 792 DSC_SLICE_PER_LINE((vdsc_cfg->pic_width / num_vdsc_instances) / 793 vdsc_cfg->slice_width) | 794 DSC_SLICE_ROW_PER_FRAME(vdsc_cfg->pic_height / 795 vdsc_cfg->slice_height); 796 drm_info(&dev_priv->drm, "PPS16 = 0x%08x\n", pps_val); 797 if (!is_pipe_dsc(crtc_state)) { 798 intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_16, 799 pps_val); 800 /* 801 * If 2 VDSC instances are needed, configure PPS for second 802 * VDSC 803 */ 804 if (crtc_state->dsc.dsc_split) 805 intel_de_write(dev_priv, 806 DSCC_PICTURE_PARAMETER_SET_16, pps_val); 807 } else { 808 intel_de_write(dev_priv, 809 ICL_DSC0_PICTURE_PARAMETER_SET_16(pipe), 810 pps_val); 811 if (crtc_state->dsc.dsc_split) 812 intel_de_write(dev_priv, 813 ICL_DSC1_PICTURE_PARAMETER_SET_16(pipe), 814 pps_val); 815 } 816 817 /* Populate the RC_BUF_THRESH registers */ 818 memset(rc_buf_thresh_dword, 0, sizeof(rc_buf_thresh_dword)); 819 for (i = 0; i < DSC_NUM_BUF_RANGES - 1; i++) { 820 rc_buf_thresh_dword[i / 4] |= 821 (u32)(vdsc_cfg->rc_buf_thresh[i] << 822 BITS_PER_BYTE * (i % 4)); 823 drm_info(&dev_priv->drm, " RC_BUF_THRESH%d = 0x%08x\n", i, 824 rc_buf_thresh_dword[i / 4]); 825 } 826 if (!is_pipe_dsc(crtc_state)) { 827 intel_de_write(dev_priv, DSCA_RC_BUF_THRESH_0, 828 rc_buf_thresh_dword[0]); 829 intel_de_write(dev_priv, DSCA_RC_BUF_THRESH_0_UDW, 830 rc_buf_thresh_dword[1]); 831 intel_de_write(dev_priv, DSCA_RC_BUF_THRESH_1, 832 rc_buf_thresh_dword[2]); 833 intel_de_write(dev_priv, DSCA_RC_BUF_THRESH_1_UDW, 834 rc_buf_thresh_dword[3]); 835 if (crtc_state->dsc.dsc_split) { 836 intel_de_write(dev_priv, DSCC_RC_BUF_THRESH_0, 837 rc_buf_thresh_dword[0]); 838 intel_de_write(dev_priv, DSCC_RC_BUF_THRESH_0_UDW, 839 rc_buf_thresh_dword[1]); 840 intel_de_write(dev_priv, DSCC_RC_BUF_THRESH_1, 841 rc_buf_thresh_dword[2]); 842 intel_de_write(dev_priv, DSCC_RC_BUF_THRESH_1_UDW, 843 rc_buf_thresh_dword[3]); 844 } 845 } else { 846 intel_de_write(dev_priv, ICL_DSC0_RC_BUF_THRESH_0(pipe), 847 rc_buf_thresh_dword[0]); 848 intel_de_write(dev_priv, ICL_DSC0_RC_BUF_THRESH_0_UDW(pipe), 849 rc_buf_thresh_dword[1]); 850 intel_de_write(dev_priv, ICL_DSC0_RC_BUF_THRESH_1(pipe), 851 rc_buf_thresh_dword[2]); 852 intel_de_write(dev_priv, ICL_DSC0_RC_BUF_THRESH_1_UDW(pipe), 853 rc_buf_thresh_dword[3]); 854 if (crtc_state->dsc.dsc_split) { 855 intel_de_write(dev_priv, 856 ICL_DSC1_RC_BUF_THRESH_0(pipe), 857 rc_buf_thresh_dword[0]); 858 intel_de_write(dev_priv, 859 ICL_DSC1_RC_BUF_THRESH_0_UDW(pipe), 860 rc_buf_thresh_dword[1]); 861 intel_de_write(dev_priv, 862 ICL_DSC1_RC_BUF_THRESH_1(pipe), 863 rc_buf_thresh_dword[2]); 864 intel_de_write(dev_priv, 865 ICL_DSC1_RC_BUF_THRESH_1_UDW(pipe), 866 rc_buf_thresh_dword[3]); 867 } 868 } 869 870 /* Populate the RC_RANGE_PARAMETERS registers */ 871 memset(rc_range_params_dword, 0, sizeof(rc_range_params_dword)); 872 for (i = 0; i < DSC_NUM_BUF_RANGES; i++) { 873 rc_range_params_dword[i / 2] |= 874 (u32)(((vdsc_cfg->rc_range_params[i].range_bpg_offset << 875 RC_BPG_OFFSET_SHIFT) | 876 (vdsc_cfg->rc_range_params[i].range_max_qp << 877 RC_MAX_QP_SHIFT) | 878 (vdsc_cfg->rc_range_params[i].range_min_qp << 879 RC_MIN_QP_SHIFT)) << 16 * (i % 2)); 880 drm_info(&dev_priv->drm, " RC_RANGE_PARAM_%d = 0x%08x\n", i, 881 rc_range_params_dword[i / 2]); 882 } 883 if (!is_pipe_dsc(crtc_state)) { 884 intel_de_write(dev_priv, DSCA_RC_RANGE_PARAMETERS_0, 885 rc_range_params_dword[0]); 886 intel_de_write(dev_priv, DSCA_RC_RANGE_PARAMETERS_0_UDW, 887 rc_range_params_dword[1]); 888 intel_de_write(dev_priv, DSCA_RC_RANGE_PARAMETERS_1, 889 rc_range_params_dword[2]); 890 intel_de_write(dev_priv, DSCA_RC_RANGE_PARAMETERS_1_UDW, 891 rc_range_params_dword[3]); 892 intel_de_write(dev_priv, DSCA_RC_RANGE_PARAMETERS_2, 893 rc_range_params_dword[4]); 894 intel_de_write(dev_priv, DSCA_RC_RANGE_PARAMETERS_2_UDW, 895 rc_range_params_dword[5]); 896 intel_de_write(dev_priv, DSCA_RC_RANGE_PARAMETERS_3, 897 rc_range_params_dword[6]); 898 intel_de_write(dev_priv, DSCA_RC_RANGE_PARAMETERS_3_UDW, 899 rc_range_params_dword[7]); 900 if (crtc_state->dsc.dsc_split) { 901 intel_de_write(dev_priv, DSCC_RC_RANGE_PARAMETERS_0, 902 rc_range_params_dword[0]); 903 intel_de_write(dev_priv, 904 DSCC_RC_RANGE_PARAMETERS_0_UDW, 905 rc_range_params_dword[1]); 906 intel_de_write(dev_priv, DSCC_RC_RANGE_PARAMETERS_1, 907 rc_range_params_dword[2]); 908 intel_de_write(dev_priv, 909 DSCC_RC_RANGE_PARAMETERS_1_UDW, 910 rc_range_params_dword[3]); 911 intel_de_write(dev_priv, DSCC_RC_RANGE_PARAMETERS_2, 912 rc_range_params_dword[4]); 913 intel_de_write(dev_priv, 914 DSCC_RC_RANGE_PARAMETERS_2_UDW, 915 rc_range_params_dword[5]); 916 intel_de_write(dev_priv, DSCC_RC_RANGE_PARAMETERS_3, 917 rc_range_params_dword[6]); 918 intel_de_write(dev_priv, 919 DSCC_RC_RANGE_PARAMETERS_3_UDW, 920 rc_range_params_dword[7]); 921 } 922 } else { 923 intel_de_write(dev_priv, ICL_DSC0_RC_RANGE_PARAMETERS_0(pipe), 924 rc_range_params_dword[0]); 925 intel_de_write(dev_priv, 926 ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW(pipe), 927 rc_range_params_dword[1]); 928 intel_de_write(dev_priv, ICL_DSC0_RC_RANGE_PARAMETERS_1(pipe), 929 rc_range_params_dword[2]); 930 intel_de_write(dev_priv, 931 ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW(pipe), 932 rc_range_params_dword[3]); 933 intel_de_write(dev_priv, ICL_DSC0_RC_RANGE_PARAMETERS_2(pipe), 934 rc_range_params_dword[4]); 935 intel_de_write(dev_priv, 936 ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW(pipe), 937 rc_range_params_dword[5]); 938 intel_de_write(dev_priv, ICL_DSC0_RC_RANGE_PARAMETERS_3(pipe), 939 rc_range_params_dword[6]); 940 intel_de_write(dev_priv, 941 ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW(pipe), 942 rc_range_params_dword[7]); 943 if (crtc_state->dsc.dsc_split) { 944 intel_de_write(dev_priv, 945 ICL_DSC1_RC_RANGE_PARAMETERS_0(pipe), 946 rc_range_params_dword[0]); 947 intel_de_write(dev_priv, 948 ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW(pipe), 949 rc_range_params_dword[1]); 950 intel_de_write(dev_priv, 951 ICL_DSC1_RC_RANGE_PARAMETERS_1(pipe), 952 rc_range_params_dword[2]); 953 intel_de_write(dev_priv, 954 ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW(pipe), 955 rc_range_params_dword[3]); 956 intel_de_write(dev_priv, 957 ICL_DSC1_RC_RANGE_PARAMETERS_2(pipe), 958 rc_range_params_dword[4]); 959 intel_de_write(dev_priv, 960 ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW(pipe), 961 rc_range_params_dword[5]); 962 intel_de_write(dev_priv, 963 ICL_DSC1_RC_RANGE_PARAMETERS_3(pipe), 964 rc_range_params_dword[6]); 965 intel_de_write(dev_priv, 966 ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW(pipe), 967 rc_range_params_dword[7]); 968 } 969 } 970 } 971 972 static void intel_dsc_dsi_pps_write(struct intel_encoder *encoder, 973 const struct intel_crtc_state *crtc_state) 974 { 975 const struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config; 976 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 977 struct mipi_dsi_device *dsi; 978 struct drm_dsc_picture_parameter_set pps; 979 enum port port; 980 981 drm_dsc_pps_payload_pack(&pps, vdsc_cfg); 982 983 for_each_dsi_port(port, intel_dsi->ports) { 984 dsi = intel_dsi->dsi_hosts[port]->device; 985 986 mipi_dsi_picture_parameter_set(dsi, &pps); 987 mipi_dsi_compression_mode(dsi, true); 988 } 989 } 990 991 static void intel_dsc_dp_pps_write(struct intel_encoder *encoder, 992 const struct intel_crtc_state *crtc_state) 993 { 994 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 995 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 996 const struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config; 997 struct drm_dsc_pps_infoframe dp_dsc_pps_sdp; 998 999 /* Prepare DP SDP PPS header as per DP 1.4 spec, Table 2-123 */ 1000 drm_dsc_dp_pps_header_init(&dp_dsc_pps_sdp.pps_header); 1001 1002 /* Fill the PPS payload bytes as per DSC spec 1.2 Table 4-1 */ 1003 drm_dsc_pps_payload_pack(&dp_dsc_pps_sdp.pps_payload, vdsc_cfg); 1004 1005 dig_port->write_infoframe(encoder, crtc_state, 1006 DP_SDP_PPS, &dp_dsc_pps_sdp, 1007 sizeof(dp_dsc_pps_sdp)); 1008 } 1009 1010 static i915_reg_t dss_ctl1_reg(const struct intel_crtc_state *crtc_state) 1011 { 1012 enum pipe pipe = to_intel_crtc(crtc_state->uapi.crtc)->pipe; 1013 1014 return is_pipe_dsc(crtc_state) ? ICL_PIPE_DSS_CTL1(pipe) : DSS_CTL1; 1015 } 1016 1017 static i915_reg_t dss_ctl2_reg(const struct intel_crtc_state *crtc_state) 1018 { 1019 enum pipe pipe = to_intel_crtc(crtc_state->uapi.crtc)->pipe; 1020 1021 return is_pipe_dsc(crtc_state) ? ICL_PIPE_DSS_CTL2(pipe) : DSS_CTL2; 1022 } 1023 1024 void intel_uncompressed_joiner_enable(const struct intel_crtc_state *crtc_state) 1025 { 1026 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1027 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1028 u32 dss_ctl1_val = 0; 1029 1030 if (crtc_state->bigjoiner && !crtc_state->dsc.compression_enable) { 1031 if (crtc_state->bigjoiner_slave) 1032 dss_ctl1_val |= UNCOMPRESSED_JOINER_SLAVE; 1033 else 1034 dss_ctl1_val |= UNCOMPRESSED_JOINER_MASTER; 1035 1036 intel_de_write(dev_priv, dss_ctl1_reg(crtc_state), dss_ctl1_val); 1037 } 1038 } 1039 1040 void intel_dsc_enable(struct intel_encoder *encoder, 1041 const struct intel_crtc_state *crtc_state) 1042 { 1043 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1044 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1045 u32 dss_ctl1_val = 0; 1046 u32 dss_ctl2_val = 0; 1047 1048 if (!crtc_state->dsc.compression_enable) 1049 return; 1050 1051 intel_dsc_pps_configure(crtc_state); 1052 1053 if (!crtc_state->bigjoiner_slave) { 1054 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI)) 1055 intel_dsc_dsi_pps_write(encoder, crtc_state); 1056 else 1057 intel_dsc_dp_pps_write(encoder, crtc_state); 1058 } 1059 1060 dss_ctl2_val |= LEFT_BRANCH_VDSC_ENABLE; 1061 if (crtc_state->dsc.dsc_split) { 1062 dss_ctl2_val |= RIGHT_BRANCH_VDSC_ENABLE; 1063 dss_ctl1_val |= JOINER_ENABLE; 1064 } 1065 if (crtc_state->bigjoiner) { 1066 dss_ctl1_val |= BIG_JOINER_ENABLE; 1067 if (!crtc_state->bigjoiner_slave) 1068 dss_ctl1_val |= MASTER_BIG_JOINER_ENABLE; 1069 } 1070 intel_de_write(dev_priv, dss_ctl1_reg(crtc_state), dss_ctl1_val); 1071 intel_de_write(dev_priv, dss_ctl2_reg(crtc_state), dss_ctl2_val); 1072 } 1073 1074 void intel_dsc_disable(const struct intel_crtc_state *old_crtc_state) 1075 { 1076 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); 1077 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1078 1079 if (!(old_crtc_state->dsc.compression_enable && 1080 old_crtc_state->bigjoiner)) 1081 return; 1082 1083 intel_de_write(dev_priv, dss_ctl1_reg(old_crtc_state), 0); 1084 intel_de_write(dev_priv, dss_ctl2_reg(old_crtc_state), 0); 1085 } 1086 1087 void intel_uncompressed_joiner_get_config(struct intel_crtc_state *crtc_state) 1088 { 1089 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1090 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1091 u32 dss_ctl1; 1092 1093 dss_ctl1 = intel_de_read(dev_priv, dss_ctl1_reg(crtc_state)); 1094 if (dss_ctl1 & UNCOMPRESSED_JOINER_MASTER) { 1095 crtc_state->bigjoiner = true; 1096 if (!WARN_ON(INTEL_NUM_PIPES(dev_priv) == crtc->pipe + 1)) 1097 crtc_state->bigjoiner_linked_crtc = 1098 intel_get_crtc_for_pipe(dev_priv, crtc->pipe + 1); 1099 } else if (dss_ctl1 & UNCOMPRESSED_JOINER_SLAVE) { 1100 crtc_state->bigjoiner = true; 1101 crtc_state->bigjoiner_slave = true; 1102 if (!WARN_ON(crtc->pipe == PIPE_A)) 1103 crtc_state->bigjoiner_linked_crtc = 1104 intel_get_crtc_for_pipe(dev_priv, crtc->pipe - 1); 1105 } 1106 } 1107 1108 void intel_dsc_get_config(struct intel_crtc_state *crtc_state) 1109 { 1110 struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config; 1111 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1112 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1113 enum pipe pipe = crtc->pipe; 1114 enum intel_display_power_domain power_domain; 1115 intel_wakeref_t wakeref; 1116 u32 dss_ctl1, dss_ctl2, val; 1117 1118 if (!intel_dsc_source_support(crtc_state)) 1119 return; 1120 1121 power_domain = intel_dsc_power_domain(crtc_state); 1122 1123 wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain); 1124 if (!wakeref) 1125 return; 1126 1127 dss_ctl1 = intel_de_read(dev_priv, dss_ctl1_reg(crtc_state)); 1128 dss_ctl2 = intel_de_read(dev_priv, dss_ctl2_reg(crtc_state)); 1129 1130 crtc_state->dsc.compression_enable = dss_ctl2 & LEFT_BRANCH_VDSC_ENABLE; 1131 if (!crtc_state->dsc.compression_enable) 1132 goto out; 1133 1134 crtc_state->dsc.dsc_split = (dss_ctl2 & RIGHT_BRANCH_VDSC_ENABLE) && 1135 (dss_ctl1 & JOINER_ENABLE); 1136 1137 if (dss_ctl1 & BIG_JOINER_ENABLE) { 1138 crtc_state->bigjoiner = true; 1139 1140 if (!(dss_ctl1 & MASTER_BIG_JOINER_ENABLE)) { 1141 crtc_state->bigjoiner_slave = true; 1142 if (!WARN_ON(crtc->pipe == PIPE_A)) 1143 crtc_state->bigjoiner_linked_crtc = 1144 intel_get_crtc_for_pipe(dev_priv, crtc->pipe - 1); 1145 } else { 1146 if (!WARN_ON(INTEL_NUM_PIPES(dev_priv) == crtc->pipe + 1)) 1147 crtc_state->bigjoiner_linked_crtc = 1148 intel_get_crtc_for_pipe(dev_priv, crtc->pipe + 1); 1149 } 1150 } 1151 1152 /* FIXME: add more state readout as needed */ 1153 1154 /* PPS1 */ 1155 if (!is_pipe_dsc(crtc_state)) 1156 val = intel_de_read(dev_priv, DSCA_PICTURE_PARAMETER_SET_1); 1157 else 1158 val = intel_de_read(dev_priv, 1159 ICL_DSC0_PICTURE_PARAMETER_SET_1(pipe)); 1160 vdsc_cfg->bits_per_pixel = val; 1161 crtc_state->dsc.compressed_bpp = vdsc_cfg->bits_per_pixel >> 4; 1162 out: 1163 intel_display_power_put(dev_priv, power_domain, wakeref); 1164 } 1165