1 /* 2 * Copyright © 2006-2016 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 * SOFTWARE. 22 * 23 * Authors: 24 * Eric Anholt <eric@anholt.net> 25 * 26 */ 27 28 /* 29 * This information is private to VBT parsing in intel_bios.c. 30 * 31 * Please do NOT include anywhere else. 32 */ 33 #ifndef _INTEL_BIOS_PRIVATE 34 #error "intel_vbt_defs.h is private to intel_bios.c" 35 #endif 36 37 #ifndef _INTEL_VBT_DEFS_H_ 38 #define _INTEL_VBT_DEFS_H_ 39 40 #include "intel_bios.h" 41 42 /** 43 * struct vbt_header - VBT Header structure 44 * @signature: VBT signature, always starts with "$VBT" 45 * @version: Version of this structure 46 * @header_size: Size of this structure 47 * @vbt_size: Size of VBT (VBT Header, BDB Header and data blocks) 48 * @vbt_checksum: Checksum 49 * @reserved0: Reserved 50 * @bdb_offset: Offset of &struct bdb_header from beginning of VBT 51 * @aim_offset: Offsets of add-in data blocks from beginning of VBT 52 */ 53 struct vbt_header { 54 u8 signature[20]; 55 u16 version; 56 u16 header_size; 57 u16 vbt_size; 58 u8 vbt_checksum; 59 u8 reserved0; 60 u32 bdb_offset; 61 u32 aim_offset[4]; 62 } __packed; 63 64 /** 65 * struct bdb_header - BDB Header structure 66 * @signature: BDB signature "BIOS_DATA_BLOCK" 67 * @version: Version of the data block definitions 68 * @header_size: Size of this structure 69 * @bdb_size: Size of BDB (BDB Header and data blocks) 70 */ 71 struct bdb_header { 72 u8 signature[16]; 73 u16 version; 74 u16 header_size; 75 u16 bdb_size; 76 } __packed; 77 78 /* 79 * There are several types of BIOS data blocks (BDBs), each block has 80 * an ID and size in the first 3 bytes (ID in first, size in next 2). 81 * Known types are listed below. 82 */ 83 enum bdb_block_id { 84 BDB_GENERAL_FEATURES = 1, 85 BDB_GENERAL_DEFINITIONS = 2, 86 BDB_OLD_TOGGLE_LIST = 3, 87 BDB_MODE_SUPPORT_LIST = 4, 88 BDB_GENERIC_MODE_TABLE = 5, 89 BDB_EXT_MMIO_REGS = 6, 90 BDB_SWF_IO = 7, 91 BDB_SWF_MMIO = 8, 92 BDB_PSR = 9, 93 BDB_MODE_REMOVAL_TABLE = 10, 94 BDB_CHILD_DEVICE_TABLE = 11, 95 BDB_DRIVER_FEATURES = 12, 96 BDB_DRIVER_PERSISTENCE = 13, 97 BDB_EXT_TABLE_PTRS = 14, 98 BDB_DOT_CLOCK_OVERRIDE = 15, 99 BDB_DISPLAY_SELECT = 16, 100 BDB_DRIVER_ROTATION = 18, 101 BDB_DISPLAY_REMOVE = 19, 102 BDB_OEM_CUSTOM = 20, 103 BDB_EFP_LIST = 21, /* workarounds for VGA hsync/vsync */ 104 BDB_SDVO_LVDS_OPTIONS = 22, 105 BDB_SDVO_PANEL_DTDS = 23, 106 BDB_SDVO_LVDS_PNP_IDS = 24, 107 BDB_SDVO_LVDS_POWER_SEQ = 25, 108 BDB_TV_OPTIONS = 26, 109 BDB_EDP = 27, 110 BDB_LVDS_OPTIONS = 40, 111 BDB_LVDS_LFP_DATA_PTRS = 41, 112 BDB_LVDS_LFP_DATA = 42, 113 BDB_LVDS_BACKLIGHT = 43, 114 BDB_LFP_POWER = 44, 115 BDB_MIPI_CONFIG = 52, 116 BDB_MIPI_SEQUENCE = 53, 117 BDB_COMPRESSION_PARAMETERS = 56, 118 BDB_GENERIC_DTD = 58, 119 BDB_SKIP = 254, /* VBIOS private block, ignore */ 120 }; 121 122 /* 123 * Block 1 - General Bit Definitions 124 */ 125 126 struct bdb_general_features { 127 /* bits 1 */ 128 u8 panel_fitting:2; 129 u8 flexaim:1; 130 u8 msg_enable:1; 131 u8 clear_screen:3; 132 u8 color_flip:1; 133 134 /* bits 2 */ 135 u8 download_ext_vbt:1; 136 u8 enable_ssc:1; 137 u8 ssc_freq:1; 138 u8 enable_lfp_on_override:1; 139 u8 disable_ssc_ddt:1; 140 u8 underscan_vga_timings:1; 141 u8 display_clock_mode:1; 142 u8 vbios_hotplug_support:1; 143 144 /* bits 3 */ 145 u8 disable_smooth_vision:1; 146 u8 single_dvi:1; 147 u8 rotate_180:1; /* 181 */ 148 u8 fdi_rx_polarity_inverted:1; 149 u8 vbios_extended_mode:1; /* 160 */ 150 u8 copy_ilfp_dtd_to_sdvo_lvds_dtd:1; /* 160 */ 151 u8 panel_best_fit_timing:1; /* 160 */ 152 u8 ignore_strap_state:1; /* 160 */ 153 154 /* bits 4 */ 155 u8 legacy_monitor_detect; 156 157 /* bits 5 */ 158 u8 int_crt_support:1; 159 u8 int_tv_support:1; 160 u8 int_efp_support:1; 161 u8 dp_ssc_enable:1; /* PCH attached eDP supports SSC */ 162 u8 dp_ssc_freq:1; /* SSC freq for PCH attached eDP */ 163 u8 dp_ssc_dongle_supported:1; 164 u8 rsvd11:2; /* finish byte */ 165 } __packed; 166 167 /* 168 * Block 2 - General Bytes Definition 169 */ 170 171 /* pre-915 */ 172 #define GPIO_PIN_DVI_LVDS 0x03 /* "DVI/LVDS DDC GPIO pins" */ 173 #define GPIO_PIN_ADD_I2C 0x05 /* "ADDCARD I2C GPIO pins" */ 174 #define GPIO_PIN_ADD_DDC 0x04 /* "ADDCARD DDC GPIO pins" */ 175 #define GPIO_PIN_ADD_DDC_I2C 0x06 /* "ADDCARD DDC/I2C GPIO pins" */ 176 177 /* Pre 915 */ 178 #define DEVICE_TYPE_NONE 0x00 179 #define DEVICE_TYPE_CRT 0x01 180 #define DEVICE_TYPE_TV 0x09 181 #define DEVICE_TYPE_EFP 0x12 182 #define DEVICE_TYPE_LFP 0x22 183 /* On 915+ */ 184 #define DEVICE_TYPE_CRT_DPMS 0x6001 185 #define DEVICE_TYPE_CRT_DPMS_HOTPLUG 0x4001 186 #define DEVICE_TYPE_TV_COMPOSITE 0x0209 187 #define DEVICE_TYPE_TV_MACROVISION 0x0289 188 #define DEVICE_TYPE_TV_RF_COMPOSITE 0x020c 189 #define DEVICE_TYPE_TV_SVIDEO_COMPOSITE 0x0609 190 #define DEVICE_TYPE_TV_SCART 0x0209 191 #define DEVICE_TYPE_TV_CODEC_HOTPLUG_PWR 0x6009 192 #define DEVICE_TYPE_EFP_HOTPLUG_PWR 0x6012 193 #define DEVICE_TYPE_EFP_DVI_HOTPLUG_PWR 0x6052 194 #define DEVICE_TYPE_EFP_DVI_I 0x6053 195 #define DEVICE_TYPE_EFP_DVI_D_DUAL 0x6152 196 #define DEVICE_TYPE_EFP_DVI_D_HDCP 0x60d2 197 #define DEVICE_TYPE_OPENLDI_HOTPLUG_PWR 0x6062 198 #define DEVICE_TYPE_OPENLDI_DUALPIX 0x6162 199 #define DEVICE_TYPE_LFP_PANELLINK 0x5012 200 #define DEVICE_TYPE_LFP_CMOS_PWR 0x5042 201 #define DEVICE_TYPE_LFP_LVDS_PWR 0x5062 202 #define DEVICE_TYPE_LFP_LVDS_DUAL 0x5162 203 #define DEVICE_TYPE_LFP_LVDS_DUAL_HDCP 0x51e2 204 205 /* Add the device class for LFP, TV, HDMI */ 206 #define DEVICE_TYPE_INT_LFP 0x1022 207 #define DEVICE_TYPE_INT_TV 0x1009 208 #define DEVICE_TYPE_HDMI 0x60D2 209 #define DEVICE_TYPE_DP 0x68C6 210 #define DEVICE_TYPE_DP_DUAL_MODE 0x60D6 211 #define DEVICE_TYPE_eDP 0x78C6 212 213 #define DEVICE_TYPE_CLASS_EXTENSION (1 << 15) 214 #define DEVICE_TYPE_POWER_MANAGEMENT (1 << 14) 215 #define DEVICE_TYPE_HOTPLUG_SIGNALING (1 << 13) 216 #define DEVICE_TYPE_INTERNAL_CONNECTOR (1 << 12) 217 #define DEVICE_TYPE_NOT_HDMI_OUTPUT (1 << 11) 218 #define DEVICE_TYPE_MIPI_OUTPUT (1 << 10) 219 #define DEVICE_TYPE_COMPOSITE_OUTPUT (1 << 9) 220 #define DEVICE_TYPE_DUAL_CHANNEL (1 << 8) 221 #define DEVICE_TYPE_HIGH_SPEED_LINK (1 << 6) 222 #define DEVICE_TYPE_LVDS_SIGNALING (1 << 5) 223 #define DEVICE_TYPE_TMDS_DVI_SIGNALING (1 << 4) 224 #define DEVICE_TYPE_VIDEO_SIGNALING (1 << 3) 225 #define DEVICE_TYPE_DISPLAYPORT_OUTPUT (1 << 2) 226 #define DEVICE_TYPE_DIGITAL_OUTPUT (1 << 1) 227 #define DEVICE_TYPE_ANALOG_OUTPUT (1 << 0) 228 229 /* 230 * Bits we care about when checking for DEVICE_TYPE_eDP. Depending on the 231 * system, the other bits may or may not be set for eDP outputs. 232 */ 233 #define DEVICE_TYPE_eDP_BITS \ 234 (DEVICE_TYPE_INTERNAL_CONNECTOR | \ 235 DEVICE_TYPE_MIPI_OUTPUT | \ 236 DEVICE_TYPE_COMPOSITE_OUTPUT | \ 237 DEVICE_TYPE_DUAL_CHANNEL | \ 238 DEVICE_TYPE_LVDS_SIGNALING | \ 239 DEVICE_TYPE_TMDS_DVI_SIGNALING | \ 240 DEVICE_TYPE_VIDEO_SIGNALING | \ 241 DEVICE_TYPE_DISPLAYPORT_OUTPUT | \ 242 DEVICE_TYPE_ANALOG_OUTPUT) 243 244 #define DEVICE_TYPE_DP_DUAL_MODE_BITS \ 245 (DEVICE_TYPE_INTERNAL_CONNECTOR | \ 246 DEVICE_TYPE_MIPI_OUTPUT | \ 247 DEVICE_TYPE_COMPOSITE_OUTPUT | \ 248 DEVICE_TYPE_LVDS_SIGNALING | \ 249 DEVICE_TYPE_TMDS_DVI_SIGNALING | \ 250 DEVICE_TYPE_VIDEO_SIGNALING | \ 251 DEVICE_TYPE_DISPLAYPORT_OUTPUT | \ 252 DEVICE_TYPE_DIGITAL_OUTPUT | \ 253 DEVICE_TYPE_ANALOG_OUTPUT) 254 255 #define DEVICE_CFG_NONE 0x00 256 #define DEVICE_CFG_12BIT_DVOB 0x01 257 #define DEVICE_CFG_12BIT_DVOC 0x02 258 #define DEVICE_CFG_24BIT_DVOBC 0x09 259 #define DEVICE_CFG_24BIT_DVOCB 0x0a 260 #define DEVICE_CFG_DUAL_DVOB 0x11 261 #define DEVICE_CFG_DUAL_DVOC 0x12 262 #define DEVICE_CFG_DUAL_DVOBC 0x13 263 #define DEVICE_CFG_DUAL_LINK_DVOBC 0x19 264 #define DEVICE_CFG_DUAL_LINK_DVOCB 0x1a 265 266 #define DEVICE_WIRE_NONE 0x00 267 #define DEVICE_WIRE_DVOB 0x01 268 #define DEVICE_WIRE_DVOC 0x02 269 #define DEVICE_WIRE_DVOBC 0x03 270 #define DEVICE_WIRE_DVOBB 0x05 271 #define DEVICE_WIRE_DVOCC 0x06 272 #define DEVICE_WIRE_DVOB_MASTER 0x0d 273 #define DEVICE_WIRE_DVOC_MASTER 0x0e 274 275 /* dvo_port pre BDB 155 */ 276 #define DEVICE_PORT_DVOA 0x00 /* none on 845+ */ 277 #define DEVICE_PORT_DVOB 0x01 278 #define DEVICE_PORT_DVOC 0x02 279 280 /* dvo_port BDB 155+ */ 281 #define DVO_PORT_HDMIA 0 282 #define DVO_PORT_HDMIB 1 283 #define DVO_PORT_HDMIC 2 284 #define DVO_PORT_HDMID 3 285 #define DVO_PORT_LVDS 4 286 #define DVO_PORT_TV 5 287 #define DVO_PORT_CRT 6 288 #define DVO_PORT_DPB 7 289 #define DVO_PORT_DPC 8 290 #define DVO_PORT_DPD 9 291 #define DVO_PORT_DPA 10 292 #define DVO_PORT_DPE 11 /* 193 */ 293 #define DVO_PORT_HDMIE 12 /* 193 */ 294 #define DVO_PORT_DPF 13 /* N/A */ 295 #define DVO_PORT_HDMIF 14 /* N/A */ 296 #define DVO_PORT_DPG 15 /* 217 */ 297 #define DVO_PORT_HDMIG 16 /* 217 */ 298 #define DVO_PORT_DPH 17 /* 217 */ 299 #define DVO_PORT_HDMIH 18 /* 217 */ 300 #define DVO_PORT_DPI 19 /* 217 */ 301 #define DVO_PORT_HDMII 20 /* 217 */ 302 #define DVO_PORT_MIPIA 21 /* 171 */ 303 #define DVO_PORT_MIPIB 22 /* 171 */ 304 #define DVO_PORT_MIPIC 23 /* 171 */ 305 #define DVO_PORT_MIPID 24 /* 171 */ 306 307 #define HDMI_MAX_DATA_RATE_PLATFORM 0 /* 204 */ 308 #define HDMI_MAX_DATA_RATE_297 1 /* 204 */ 309 #define HDMI_MAX_DATA_RATE_165 2 /* 204 */ 310 311 #define LEGACY_CHILD_DEVICE_CONFIG_SIZE 33 312 313 /* DDC Bus DDI Type 155+ */ 314 enum vbt_gmbus_ddi { 315 DDC_BUS_DDI_B = 0x1, 316 DDC_BUS_DDI_C, 317 DDC_BUS_DDI_D, 318 DDC_BUS_DDI_F, 319 ICL_DDC_BUS_DDI_A = 0x1, 320 ICL_DDC_BUS_DDI_B, 321 TGL_DDC_BUS_DDI_C, 322 RKL_DDC_BUS_DDI_D = 0x3, 323 RKL_DDC_BUS_DDI_E, 324 ICL_DDC_BUS_PORT_1 = 0x4, 325 ICL_DDC_BUS_PORT_2, 326 ICL_DDC_BUS_PORT_3, 327 ICL_DDC_BUS_PORT_4, 328 TGL_DDC_BUS_PORT_5, 329 TGL_DDC_BUS_PORT_6, 330 }; 331 332 #define DP_AUX_A 0x40 333 #define DP_AUX_B 0x10 334 #define DP_AUX_C 0x20 335 #define DP_AUX_D 0x30 336 #define DP_AUX_E 0x50 337 #define DP_AUX_F 0x60 338 #define DP_AUX_G 0x70 339 #define DP_AUX_H 0x80 340 #define DP_AUX_I 0x90 341 342 #define VBT_DP_MAX_LINK_RATE_HBR3 0 343 #define VBT_DP_MAX_LINK_RATE_HBR2 1 344 #define VBT_DP_MAX_LINK_RATE_HBR 2 345 #define VBT_DP_MAX_LINK_RATE_LBR 3 346 347 /* 348 * The child device config, aka the display device data structure, provides a 349 * description of a port and its configuration on the platform. 350 * 351 * The child device config size has been increased, and fields have been added 352 * and their meaning has changed over time. Care must be taken when accessing 353 * basically any of the fields to ensure the correct interpretation for the BDB 354 * version in question. 355 * 356 * When we copy the child device configs to dev_priv->vbt.child_dev, we reserve 357 * space for the full structure below, and initialize the tail not actually 358 * present in VBT to zeros. Accessing those fields is fine, as long as the 359 * default zero is taken into account, again according to the BDB version. 360 * 361 * BDB versions 155 and below are considered legacy, and version 155 seems to be 362 * a baseline for some of the VBT documentation. When adding new fields, please 363 * include the BDB version when the field was added, if it's above that. 364 */ 365 struct child_device_config { 366 u16 handle; 367 u16 device_type; /* See DEVICE_TYPE_* above */ 368 369 union { 370 u8 device_id[10]; /* ascii string */ 371 struct { 372 u8 i2c_speed; 373 u8 dp_onboard_redriver; /* 158 */ 374 u8 dp_ondock_redriver; /* 158 */ 375 u8 hdmi_level_shifter_value:5; /* 169 */ 376 u8 hdmi_max_data_rate:3; /* 204 */ 377 u16 dtd_buf_ptr; /* 161 */ 378 u8 edidless_efp:1; /* 161 */ 379 u8 compression_enable:1; /* 198 */ 380 u8 compression_method_cps:1; /* 198 */ 381 u8 ganged_edp:1; /* 202 */ 382 u8 reserved0:4; 383 u8 compression_structure_index:4; /* 198 */ 384 u8 reserved1:4; 385 u8 slave_port; /* 202 */ 386 u8 reserved2; 387 } __packed; 388 } __packed; 389 390 u16 addin_offset; 391 u8 dvo_port; /* See DEVICE_PORT_* and DVO_PORT_* above */ 392 u8 i2c_pin; 393 u8 slave_addr; 394 u8 ddc_pin; 395 u16 edid_ptr; 396 u8 dvo_cfg; /* See DEVICE_CFG_* above */ 397 398 union { 399 struct { 400 u8 dvo2_port; 401 u8 i2c2_pin; 402 u8 slave2_addr; 403 u8 ddc2_pin; 404 } __packed; 405 struct { 406 u8 efp_routed:1; /* 158 */ 407 u8 lane_reversal:1; /* 184 */ 408 u8 lspcon:1; /* 192 */ 409 u8 iboost:1; /* 196 */ 410 u8 hpd_invert:1; /* 196 */ 411 u8 use_vbt_vswing:1; /* 218 */ 412 u8 flag_reserved:2; 413 u8 hdmi_support:1; /* 158 */ 414 u8 dp_support:1; /* 158 */ 415 u8 tmds_support:1; /* 158 */ 416 u8 support_reserved:5; 417 u8 aux_channel; 418 u8 dongle_detect; 419 } __packed; 420 } __packed; 421 422 u8 pipe_cap:2; 423 u8 sdvo_stall:1; /* 158 */ 424 u8 hpd_status:2; 425 u8 integrated_encoder:1; 426 u8 capabilities_reserved:2; 427 u8 dvo_wiring; /* See DEVICE_WIRE_* above */ 428 429 union { 430 u8 dvo2_wiring; 431 u8 mipi_bridge_type; /* 171 */ 432 } __packed; 433 434 u16 extended_type; 435 u8 dvo_function; 436 u8 dp_usb_type_c:1; /* 195 */ 437 u8 tbt:1; /* 209 */ 438 u8 flags2_reserved:2; /* 195 */ 439 u8 dp_port_trace_length:4; /* 209 */ 440 u8 dp_gpio_index; /* 195 */ 441 u16 dp_gpio_pin_num; /* 195 */ 442 u8 dp_iboost_level:4; /* 196 */ 443 u8 hdmi_iboost_level:4; /* 196 */ 444 u8 dp_max_link_rate:2; /* 216 CNL+ */ 445 u8 dp_max_link_rate_reserved:6; /* 216 */ 446 } __packed; 447 448 struct bdb_general_definitions { 449 /* DDC GPIO */ 450 u8 crt_ddc_gmbus_pin; 451 452 /* DPMS bits */ 453 u8 dpms_acpi:1; 454 u8 skip_boot_crt_detect:1; 455 u8 dpms_aim:1; 456 u8 rsvd1:5; /* finish byte */ 457 458 /* boot device bits */ 459 u8 boot_display[2]; 460 u8 child_dev_size; 461 462 /* 463 * Device info: 464 * If TV is present, it'll be at devices[0]. 465 * LVDS will be next, either devices[0] or [1], if present. 466 * On some platforms the number of device is 6. But could be as few as 467 * 4 if both TV and LVDS are missing. 468 * And the device num is related with the size of general definition 469 * block. It is obtained by using the following formula: 470 * number = (block_size - sizeof(bdb_general_definitions))/ 471 * defs->child_dev_size; 472 */ 473 u8 devices[]; 474 } __packed; 475 476 /* 477 * Block 9 - SRD Feature Block 478 */ 479 480 struct psr_table { 481 /* Feature bits */ 482 u8 full_link:1; 483 u8 require_aux_to_wakeup:1; 484 u8 feature_bits_rsvd:6; 485 486 /* Wait times */ 487 u8 idle_frames:4; 488 u8 lines_to_wait:3; 489 u8 wait_times_rsvd:1; 490 491 /* TP wake up time in multiple of 100 */ 492 u16 tp1_wakeup_time; 493 u16 tp2_tp3_wakeup_time; 494 } __packed; 495 496 struct bdb_psr { 497 struct psr_table psr_table[16]; 498 499 /* PSR2 TP2/TP3 wakeup time for 16 panels */ 500 u32 psr2_tp2_tp3_wakeup_time; 501 } __packed; 502 503 /* 504 * Block 12 - Driver Features Data Block 505 */ 506 507 #define BDB_DRIVER_FEATURE_NO_LVDS 0 508 #define BDB_DRIVER_FEATURE_INT_LVDS 1 509 #define BDB_DRIVER_FEATURE_SDVO_LVDS 2 510 #define BDB_DRIVER_FEATURE_INT_SDVO_LVDS 3 511 512 struct bdb_driver_features { 513 u8 boot_dev_algorithm:1; 514 u8 block_display_switch:1; 515 u8 allow_display_switch:1; 516 u8 hotplug_dvo:1; 517 u8 dual_view_zoom:1; 518 u8 int15h_hook:1; 519 u8 sprite_in_clone:1; 520 u8 primary_lfp_id:1; 521 522 u16 boot_mode_x; 523 u16 boot_mode_y; 524 u8 boot_mode_bpp; 525 u8 boot_mode_refresh; 526 527 u16 enable_lfp_primary:1; 528 u16 selective_mode_pruning:1; 529 u16 dual_frequency:1; 530 u16 render_clock_freq:1; /* 0: high freq; 1: low freq */ 531 u16 nt_clone_support:1; 532 u16 power_scheme_ui:1; /* 0: CUI; 1: 3rd party */ 533 u16 sprite_display_assign:1; /* 0: secondary; 1: primary */ 534 u16 cui_aspect_scaling:1; 535 u16 preserve_aspect_ratio:1; 536 u16 sdvo_device_power_down:1; 537 u16 crt_hotplug:1; 538 u16 lvds_config:2; 539 u16 tv_hotplug:1; 540 u16 hdmi_config:2; 541 542 u8 static_display:1; 543 u8 reserved2:7; 544 u16 legacy_crt_max_x; 545 u16 legacy_crt_max_y; 546 u8 legacy_crt_max_refresh; 547 548 u8 hdmi_termination; 549 u8 custom_vbt_version; 550 /* Driver features data block */ 551 u16 rmpm_enabled:1; 552 u16 s2ddt_enabled:1; 553 u16 dpst_enabled:1; 554 u16 bltclt_enabled:1; 555 u16 adb_enabled:1; 556 u16 drrs_enabled:1; 557 u16 grs_enabled:1; 558 u16 gpmt_enabled:1; 559 u16 tbt_enabled:1; 560 u16 psr_enabled:1; 561 u16 ips_enabled:1; 562 u16 reserved3:4; 563 u16 pc_feature_valid:1; 564 } __packed; 565 566 /* 567 * Block 22 - SDVO LVDS General Options 568 */ 569 570 struct bdb_sdvo_lvds_options { 571 u8 panel_backlight; 572 u8 h40_set_panel_type; 573 u8 panel_type; 574 u8 ssc_clk_freq; 575 u16 als_low_trip; 576 u16 als_high_trip; 577 u8 sclalarcoeff_tab_row_num; 578 u8 sclalarcoeff_tab_row_size; 579 u8 coefficient[8]; 580 u8 panel_misc_bits_1; 581 u8 panel_misc_bits_2; 582 u8 panel_misc_bits_3; 583 u8 panel_misc_bits_4; 584 } __packed; 585 586 /* 587 * Block 23 - SDVO LVDS Panel DTDs 588 */ 589 590 struct lvds_dvo_timing { 591 u16 clock; /**< In 10khz */ 592 u8 hactive_lo; 593 u8 hblank_lo; 594 u8 hblank_hi:4; 595 u8 hactive_hi:4; 596 u8 vactive_lo; 597 u8 vblank_lo; 598 u8 vblank_hi:4; 599 u8 vactive_hi:4; 600 u8 hsync_off_lo; 601 u8 hsync_pulse_width_lo; 602 u8 vsync_pulse_width_lo:4; 603 u8 vsync_off_lo:4; 604 u8 vsync_pulse_width_hi:2; 605 u8 vsync_off_hi:2; 606 u8 hsync_pulse_width_hi:2; 607 u8 hsync_off_hi:2; 608 u8 himage_lo; 609 u8 vimage_lo; 610 u8 vimage_hi:4; 611 u8 himage_hi:4; 612 u8 h_border; 613 u8 v_border; 614 u8 rsvd1:3; 615 u8 digital:2; 616 u8 vsync_positive:1; 617 u8 hsync_positive:1; 618 u8 non_interlaced:1; 619 } __packed; 620 621 struct bdb_sdvo_panel_dtds { 622 struct lvds_dvo_timing dtds[4]; 623 } __packed; 624 625 /* 626 * Block 27 - eDP VBT Block 627 */ 628 629 #define EDP_18BPP 0 630 #define EDP_24BPP 1 631 #define EDP_30BPP 2 632 #define EDP_RATE_1_62 0 633 #define EDP_RATE_2_7 1 634 #define EDP_LANE_1 0 635 #define EDP_LANE_2 1 636 #define EDP_LANE_4 3 637 #define EDP_PREEMPHASIS_NONE 0 638 #define EDP_PREEMPHASIS_3_5dB 1 639 #define EDP_PREEMPHASIS_6dB 2 640 #define EDP_PREEMPHASIS_9_5dB 3 641 #define EDP_VSWING_0_4V 0 642 #define EDP_VSWING_0_6V 1 643 #define EDP_VSWING_0_8V 2 644 #define EDP_VSWING_1_2V 3 645 646 647 struct edp_fast_link_params { 648 u8 rate:4; 649 u8 lanes:4; 650 u8 preemphasis:4; 651 u8 vswing:4; 652 } __packed; 653 654 struct edp_pwm_delays { 655 u16 pwm_on_to_backlight_enable; 656 u16 backlight_disable_to_pwm_off; 657 } __packed; 658 659 struct edp_full_link_params { 660 u8 preemphasis:4; 661 u8 vswing:4; 662 } __packed; 663 664 struct bdb_edp { 665 struct edp_power_seq power_seqs[16]; 666 u32 color_depth; 667 struct edp_fast_link_params fast_link_params[16]; 668 u32 sdrrs_msa_timing_delay; 669 670 /* ith bit indicates enabled/disabled for (i+1)th panel */ 671 u16 edp_s3d_feature; /* 162 */ 672 u16 edp_t3_optimization; /* 165 */ 673 u64 edp_vswing_preemph; /* 173 */ 674 u16 fast_link_training; /* 182 */ 675 u16 dpcd_600h_write_required; /* 185 */ 676 struct edp_pwm_delays pwm_delays[16]; /* 186 */ 677 u16 full_link_params_provided; /* 199 */ 678 struct edp_full_link_params full_link_params[16]; /* 199 */ 679 } __packed; 680 681 /* 682 * Block 40 - LFP Data Block 683 */ 684 685 /* Mask for DRRS / Panel Channel / SSC / BLT control bits extraction */ 686 #define MODE_MASK 0x3 687 688 struct bdb_lvds_options { 689 u8 panel_type; 690 u8 panel_type2; /* 212 */ 691 /* LVDS capabilities, stored in a dword */ 692 u8 pfit_mode:2; 693 u8 pfit_text_mode_enhanced:1; 694 u8 pfit_gfx_mode_enhanced:1; 695 u8 pfit_ratio_auto:1; 696 u8 pixel_dither:1; 697 u8 lvds_edid:1; 698 u8 rsvd2:1; 699 u8 rsvd4; 700 /* LVDS Panel channel bits stored here */ 701 u32 lvds_panel_channel_bits; 702 /* LVDS SSC (Spread Spectrum Clock) bits stored here. */ 703 u16 ssc_bits; 704 u16 ssc_freq; 705 u16 ssc_ddt; 706 /* Panel color depth defined here */ 707 u16 panel_color_depth; 708 /* LVDS panel type bits stored here */ 709 u32 dps_panel_type_bits; 710 /* LVDS backlight control type bits stored here */ 711 u32 blt_control_type_bits; 712 713 u16 lcdvcc_s0_enable; /* 200 */ 714 u32 rotation; /* 228 */ 715 } __packed; 716 717 /* 718 * Block 41 - LFP Data Table Pointers 719 */ 720 721 /* LFP pointer table contains entries to the struct below */ 722 struct lvds_lfp_data_ptr { 723 u16 fp_timing_offset; /* offsets are from start of bdb */ 724 u8 fp_table_size; 725 u16 dvo_timing_offset; 726 u8 dvo_table_size; 727 u16 panel_pnp_id_offset; 728 u8 pnp_table_size; 729 } __packed; 730 731 struct bdb_lvds_lfp_data_ptrs { 732 u8 lvds_entries; /* followed by one or more lvds_data_ptr structs */ 733 struct lvds_lfp_data_ptr ptr[16]; 734 } __packed; 735 736 /* 737 * Block 42 - LFP Data Tables 738 */ 739 740 /* LFP data has 3 blocks per entry */ 741 struct lvds_fp_timing { 742 u16 x_res; 743 u16 y_res; 744 u32 lvds_reg; 745 u32 lvds_reg_val; 746 u32 pp_on_reg; 747 u32 pp_on_reg_val; 748 u32 pp_off_reg; 749 u32 pp_off_reg_val; 750 u32 pp_cycle_reg; 751 u32 pp_cycle_reg_val; 752 u32 pfit_reg; 753 u32 pfit_reg_val; 754 u16 terminator; 755 } __packed; 756 757 struct lvds_pnp_id { 758 u16 mfg_name; 759 u16 product_code; 760 u32 serial; 761 u8 mfg_week; 762 u8 mfg_year; 763 } __packed; 764 765 struct lvds_lfp_data_entry { 766 struct lvds_fp_timing fp_timing; 767 struct lvds_dvo_timing dvo_timing; 768 struct lvds_pnp_id pnp_id; 769 } __packed; 770 771 struct bdb_lvds_lfp_data { 772 struct lvds_lfp_data_entry data[16]; 773 } __packed; 774 775 /* 776 * Block 43 - LFP Backlight Control Data Block 777 */ 778 779 #define BDB_BACKLIGHT_TYPE_NONE 0 780 #define BDB_BACKLIGHT_TYPE_PWM 2 781 782 struct lfp_backlight_data_entry { 783 u8 type:2; 784 u8 active_low_pwm:1; 785 u8 obsolete1:5; 786 u16 pwm_freq_hz; 787 u8 min_brightness; /* Obsolete from 234+ */ 788 u8 obsolete2; 789 u8 obsolete3; 790 } __packed; 791 792 struct lfp_backlight_control_method { 793 u8 type:4; 794 u8 controller:4; 795 } __packed; 796 797 struct lfp_brightness_level { 798 u16 level; 799 u16 reserved; 800 } __packed; 801 802 struct bdb_lfp_backlight_data { 803 u8 entry_size; 804 struct lfp_backlight_data_entry data[16]; 805 u8 level[16]; /* Obsolete from 234+ */ 806 struct lfp_backlight_control_method backlight_control[16]; 807 struct lfp_brightness_level brightness_level[16]; /* 234+ */ 808 struct lfp_brightness_level brightness_min_level[16]; /* 234+ */ 809 u8 brightness_precision_bits[16]; /* 236+ */ 810 } __packed; 811 812 /* 813 * Block 44 - LFP Power Conservation Features Block 814 */ 815 816 struct als_data_entry { 817 u16 backlight_adjust; 818 u16 lux; 819 } __packed; 820 821 struct agressiveness_profile_entry { 822 u8 dpst_agressiveness : 4; 823 u8 lace_agressiveness : 4; 824 } __packed; 825 826 struct bdb_lfp_power { 827 u8 lfp_feature_bits; 828 struct als_data_entry als[5]; 829 u8 lace_aggressiveness_profile; 830 u16 dpst; 831 u16 psr; 832 u16 drrs; 833 u16 lace_support; 834 u16 adt; 835 u16 dmrrs; 836 u16 adb; 837 u16 lace_enabled_status; 838 struct agressiveness_profile_entry aggressivenes[16]; 839 u16 hobl; /* 232+ */ 840 u16 vrr_feature_enabled; /* 233+ */ 841 } __packed; 842 843 /* 844 * Block 52 - MIPI Configuration Block 845 */ 846 847 #define MAX_MIPI_CONFIGURATIONS 6 848 849 struct bdb_mipi_config { 850 struct mipi_config config[MAX_MIPI_CONFIGURATIONS]; 851 struct mipi_pps_data pps[MAX_MIPI_CONFIGURATIONS]; 852 } __packed; 853 854 /* 855 * Block 53 - MIPI Sequence Block 856 */ 857 858 struct bdb_mipi_sequence { 859 u8 version; 860 u8 data[]; /* up to 6 variable length blocks */ 861 } __packed; 862 863 /* 864 * Block 56 - Compression Parameters 865 */ 866 867 #define VBT_RC_BUFFER_BLOCK_SIZE_1KB 0 868 #define VBT_RC_BUFFER_BLOCK_SIZE_4KB 1 869 #define VBT_RC_BUFFER_BLOCK_SIZE_16KB 2 870 #define VBT_RC_BUFFER_BLOCK_SIZE_64KB 3 871 872 #define VBT_DSC_LINE_BUFFER_DEPTH(vbt_value) ((vbt_value) + 8) /* bits */ 873 #define VBT_DSC_MAX_BPP(vbt_value) (6 + (vbt_value) * 2) 874 875 struct dsc_compression_parameters_entry { 876 u8 version_major:4; 877 u8 version_minor:4; 878 879 u8 rc_buffer_block_size:2; 880 u8 reserved1:6; 881 882 /* 883 * Buffer size in bytes: 884 * 885 * 4 ^ rc_buffer_block_size * 1024 * (rc_buffer_size + 1) bytes 886 */ 887 u8 rc_buffer_size; 888 u32 slices_per_line; 889 890 u8 line_buffer_depth:4; 891 u8 reserved2:4; 892 893 /* Flag Bits 1 */ 894 u8 block_prediction_enable:1; 895 u8 reserved3:7; 896 897 u8 max_bpp; /* mapping */ 898 899 /* Color depth capabilities */ 900 u8 reserved4:1; 901 u8 support_8bpc:1; 902 u8 support_10bpc:1; 903 u8 support_12bpc:1; 904 u8 reserved5:4; 905 906 u16 slice_height; 907 } __packed; 908 909 struct bdb_compression_parameters { 910 u16 entry_size; 911 struct dsc_compression_parameters_entry data[16]; 912 } __packed; 913 914 /* 915 * Block 58 - Generic DTD Block 916 */ 917 918 struct generic_dtd_entry { 919 u32 pixel_clock; 920 u16 hactive; 921 u16 hblank; 922 u16 hfront_porch; 923 u16 hsync; 924 u16 vactive; 925 u16 vblank; 926 u16 vfront_porch; 927 u16 vsync; 928 u16 width_mm; 929 u16 height_mm; 930 931 /* Flags */ 932 u8 rsvd_flags:6; 933 u8 vsync_positive_polarity:1; 934 u8 hsync_positive_polarity:1; 935 936 u8 rsvd[3]; 937 } __packed; 938 939 struct bdb_generic_dtd { 940 u16 gdtd_size; 941 struct generic_dtd_entry dtd[]; /* up to 24 DTD's */ 942 } __packed; 943 944 #endif /* _INTEL_VBT_DEFS_H_ */ 945