1 /* 2 * Copyright © 2006-2008 Intel Corporation 3 * Jesse Barnes <jesse.barnes@intel.com> 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 22 * DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: 25 * Eric Anholt <eric@anholt.net> 26 * 27 */ 28 29 /** @file 30 * Integrated TV-out support for the 915GM and 945GM. 31 */ 32 33 #include <drm/drm_atomic_helper.h> 34 #include <drm/drm_crtc.h> 35 #include <drm/drm_edid.h> 36 #include <drm/drm_print.h> 37 #include <drm/drm_probe_helper.h> 38 39 #include "intel_connector.h" 40 #include "intel_crtc.h" 41 #include "intel_de.h" 42 #include "intel_display_driver.h" 43 #include "intel_display_irq.h" 44 #include "intel_display_regs.h" 45 #include "intel_display_types.h" 46 #include "intel_dpll.h" 47 #include "intel_hotplug.h" 48 #include "intel_load_detect.h" 49 #include "intel_tv.h" 50 #include "intel_tv_regs.h" 51 52 enum tv_margin { 53 TV_MARGIN_LEFT, TV_MARGIN_TOP, 54 TV_MARGIN_RIGHT, TV_MARGIN_BOTTOM 55 }; 56 57 struct intel_tv { 58 struct intel_encoder base; 59 60 int type; 61 }; 62 63 struct video_levels { 64 u16 blank, black; 65 u8 burst; 66 }; 67 68 struct color_conversion { 69 u16 ry, gy, by, ay; 70 u16 ru, gu, bu, au; 71 u16 rv, gv, bv, av; 72 }; 73 74 static const u32 filter_table[] = { 75 0xB1403000, 0x2E203500, 0x35002E20, 0x3000B140, 76 0x35A0B160, 0x2DC02E80, 0xB1403480, 0xB1603000, 77 0x2EA03640, 0x34002D80, 0x3000B120, 0x36E0B160, 78 0x2D202EF0, 0xB1203380, 0xB1603000, 0x2F303780, 79 0x33002CC0, 0x3000B100, 0x3820B160, 0x2C802F50, 80 0xB10032A0, 0xB1603000, 0x2F9038C0, 0x32202C20, 81 0x3000B0E0, 0x3980B160, 0x2BC02FC0, 0xB0E031C0, 82 0xB1603000, 0x2FF03A20, 0x31602B60, 0xB020B0C0, 83 0x3AE0B160, 0x2B001810, 0xB0C03120, 0xB140B020, 84 0x18283BA0, 0x30C02A80, 0xB020B0A0, 0x3C60B140, 85 0x2A201838, 0xB0A03080, 0xB120B020, 0x18383D20, 86 0x304029C0, 0xB040B080, 0x3DE0B100, 0x29601848, 87 0xB0803000, 0xB100B040, 0x18483EC0, 0xB0402900, 88 0xB040B060, 0x3F80B0C0, 0x28801858, 0xB060B080, 89 0xB0A0B060, 0x18602820, 0xB0A02820, 0x0000B060, 90 0xB1403000, 0x2E203500, 0x35002E20, 0x3000B140, 91 0x35A0B160, 0x2DC02E80, 0xB1403480, 0xB1603000, 92 0x2EA03640, 0x34002D80, 0x3000B120, 0x36E0B160, 93 0x2D202EF0, 0xB1203380, 0xB1603000, 0x2F303780, 94 0x33002CC0, 0x3000B100, 0x3820B160, 0x2C802F50, 95 0xB10032A0, 0xB1603000, 0x2F9038C0, 0x32202C20, 96 0x3000B0E0, 0x3980B160, 0x2BC02FC0, 0xB0E031C0, 97 0xB1603000, 0x2FF03A20, 0x31602B60, 0xB020B0C0, 98 0x3AE0B160, 0x2B001810, 0xB0C03120, 0xB140B020, 99 0x18283BA0, 0x30C02A80, 0xB020B0A0, 0x3C60B140, 100 0x2A201838, 0xB0A03080, 0xB120B020, 0x18383D20, 101 0x304029C0, 0xB040B080, 0x3DE0B100, 0x29601848, 102 0xB0803000, 0xB100B040, 0x18483EC0, 0xB0402900, 103 0xB040B060, 0x3F80B0C0, 0x28801858, 0xB060B080, 104 0xB0A0B060, 0x18602820, 0xB0A02820, 0x0000B060, 105 0x36403000, 0x2D002CC0, 0x30003640, 0x2D0036C0, 106 0x35C02CC0, 0x37403000, 0x2C802D40, 0x30003540, 107 0x2D8037C0, 0x34C02C40, 0x38403000, 0x2BC02E00, 108 0x30003440, 0x2E2038C0, 0x34002B80, 0x39803000, 109 0x2B402E40, 0x30003380, 0x2E603A00, 0x33402B00, 110 0x3A803040, 0x2A802EA0, 0x30403300, 0x2EC03B40, 111 0x32802A40, 0x3C003040, 0x2A002EC0, 0x30803240, 112 0x2EC03C80, 0x320029C0, 0x3D403080, 0x29402F00, 113 0x308031C0, 0x2F203DC0, 0x31802900, 0x3E8030C0, 114 0x28802F40, 0x30C03140, 0x2F203F40, 0x31402840, 115 0x28003100, 0x28002F00, 0x00003100, 0x36403000, 116 0x2D002CC0, 0x30003640, 0x2D0036C0, 117 0x35C02CC0, 0x37403000, 0x2C802D40, 0x30003540, 118 0x2D8037C0, 0x34C02C40, 0x38403000, 0x2BC02E00, 119 0x30003440, 0x2E2038C0, 0x34002B80, 0x39803000, 120 0x2B402E40, 0x30003380, 0x2E603A00, 0x33402B00, 121 0x3A803040, 0x2A802EA0, 0x30403300, 0x2EC03B40, 122 0x32802A40, 0x3C003040, 0x2A002EC0, 0x30803240, 123 0x2EC03C80, 0x320029C0, 0x3D403080, 0x29402F00, 124 0x308031C0, 0x2F203DC0, 0x31802900, 0x3E8030C0, 125 0x28802F40, 0x30C03140, 0x2F203F40, 0x31402840, 126 0x28003100, 0x28002F00, 0x00003100, 127 }; 128 129 /* 130 * Color conversion values have 3 separate fixed point formats: 131 * 132 * 10 bit fields (ay, au) 133 * 1.9 fixed point (b.bbbbbbbbb) 134 * 11 bit fields (ry, by, ru, gu, gv) 135 * exp.mantissa (ee.mmmmmmmmm) 136 * ee = 00 = 10^-1 (0.mmmmmmmmm) 137 * ee = 01 = 10^-2 (0.0mmmmmmmmm) 138 * ee = 10 = 10^-3 (0.00mmmmmmmmm) 139 * ee = 11 = 10^-4 (0.000mmmmmmmmm) 140 * 12 bit fields (gy, rv, bu) 141 * exp.mantissa (eee.mmmmmmmmm) 142 * eee = 000 = 10^-1 (0.mmmmmmmmm) 143 * eee = 001 = 10^-2 (0.0mmmmmmmmm) 144 * eee = 010 = 10^-3 (0.00mmmmmmmmm) 145 * eee = 011 = 10^-4 (0.000mmmmmmmmm) 146 * eee = 100 = reserved 147 * eee = 101 = reserved 148 * eee = 110 = reserved 149 * eee = 111 = 10^0 (m.mmmmmmmm) (only usable for 1.0 representation) 150 * 151 * Saturation and contrast are 8 bits, with their own representation: 152 * 8 bit field (saturation, contrast) 153 * exp.mantissa (ee.mmmmmm) 154 * ee = 00 = 10^-1 (0.mmmmmm) 155 * ee = 01 = 10^0 (m.mmmmm) 156 * ee = 10 = 10^1 (mm.mmmm) 157 * ee = 11 = 10^2 (mmm.mmm) 158 * 159 * Simple conversion function: 160 * 161 * static u32 162 * float_to_csc_11(float f) 163 * { 164 * u32 exp; 165 * u32 mant; 166 * u32 ret; 167 * 168 * if (f < 0) 169 * f = -f; 170 * 171 * if (f >= 1) { 172 * exp = 0x7; 173 * mant = 1 << 8; 174 * } else { 175 * for (exp = 0; exp < 3 && f < 0.5; exp++) 176 * f *= 2.0; 177 * mant = (f * (1 << 9) + 0.5); 178 * if (mant >= (1 << 9)) 179 * mant = (1 << 9) - 1; 180 * } 181 * ret = (exp << 9) | mant; 182 * return ret; 183 * } 184 */ 185 186 /* 187 * Behold, magic numbers! If we plant them they might grow a big 188 * s-video cable to the sky... or something. 189 * 190 * Pre-converted to appropriate hex value. 191 */ 192 193 /* 194 * PAL & NTSC values for composite & s-video connections 195 */ 196 static const struct color_conversion ntsc_m_csc_composite = { 197 .ry = 0x0332, .gy = 0x012d, .by = 0x07d3, .ay = 0x0104, 198 .ru = 0x0733, .gu = 0x052d, .bu = 0x05c7, .au = 0x0200, 199 .rv = 0x0340, .gv = 0x030c, .bv = 0x06d0, .av = 0x0200, 200 }; 201 202 static const struct video_levels ntsc_m_levels_composite = { 203 .blank = 225, .black = 267, .burst = 113, 204 }; 205 206 static const struct color_conversion ntsc_m_csc_svideo = { 207 .ry = 0x0332, .gy = 0x012d, .by = 0x07d3, .ay = 0x0133, 208 .ru = 0x076a, .gu = 0x0564, .bu = 0x030d, .au = 0x0200, 209 .rv = 0x037a, .gv = 0x033d, .bv = 0x06f6, .av = 0x0200, 210 }; 211 212 static const struct video_levels ntsc_m_levels_svideo = { 213 .blank = 266, .black = 316, .burst = 133, 214 }; 215 216 static const struct color_conversion ntsc_j_csc_composite = { 217 .ry = 0x0332, .gy = 0x012d, .by = 0x07d3, .ay = 0x0119, 218 .ru = 0x074c, .gu = 0x0546, .bu = 0x05ec, .au = 0x0200, 219 .rv = 0x035a, .gv = 0x0322, .bv = 0x06e1, .av = 0x0200, 220 }; 221 222 static const struct video_levels ntsc_j_levels_composite = { 223 .blank = 225, .black = 225, .burst = 113, 224 }; 225 226 static const struct color_conversion ntsc_j_csc_svideo = { 227 .ry = 0x0332, .gy = 0x012d, .by = 0x07d3, .ay = 0x014c, 228 .ru = 0x0788, .gu = 0x0581, .bu = 0x0322, .au = 0x0200, 229 .rv = 0x0399, .gv = 0x0356, .bv = 0x070a, .av = 0x0200, 230 }; 231 232 static const struct video_levels ntsc_j_levels_svideo = { 233 .blank = 266, .black = 266, .burst = 133, 234 }; 235 236 static const struct color_conversion pal_csc_composite = { 237 .ry = 0x0332, .gy = 0x012d, .by = 0x07d3, .ay = 0x0113, 238 .ru = 0x0745, .gu = 0x053f, .bu = 0x05e1, .au = 0x0200, 239 .rv = 0x0353, .gv = 0x031c, .bv = 0x06dc, .av = 0x0200, 240 }; 241 242 static const struct video_levels pal_levels_composite = { 243 .blank = 237, .black = 237, .burst = 118, 244 }; 245 246 static const struct color_conversion pal_csc_svideo = { 247 .ry = 0x0332, .gy = 0x012d, .by = 0x07d3, .ay = 0x0145, 248 .ru = 0x0780, .gu = 0x0579, .bu = 0x031c, .au = 0x0200, 249 .rv = 0x0390, .gv = 0x034f, .bv = 0x0705, .av = 0x0200, 250 }; 251 252 static const struct video_levels pal_levels_svideo = { 253 .blank = 280, .black = 280, .burst = 139, 254 }; 255 256 static const struct color_conversion pal_m_csc_composite = { 257 .ry = 0x0332, .gy = 0x012d, .by = 0x07d3, .ay = 0x0104, 258 .ru = 0x0733, .gu = 0x052d, .bu = 0x05c7, .au = 0x0200, 259 .rv = 0x0340, .gv = 0x030c, .bv = 0x06d0, .av = 0x0200, 260 }; 261 262 static const struct video_levels pal_m_levels_composite = { 263 .blank = 225, .black = 267, .burst = 113, 264 }; 265 266 static const struct color_conversion pal_m_csc_svideo = { 267 .ry = 0x0332, .gy = 0x012d, .by = 0x07d3, .ay = 0x0133, 268 .ru = 0x076a, .gu = 0x0564, .bu = 0x030d, .au = 0x0200, 269 .rv = 0x037a, .gv = 0x033d, .bv = 0x06f6, .av = 0x0200, 270 }; 271 272 static const struct video_levels pal_m_levels_svideo = { 273 .blank = 266, .black = 316, .burst = 133, 274 }; 275 276 static const struct color_conversion pal_n_csc_composite = { 277 .ry = 0x0332, .gy = 0x012d, .by = 0x07d3, .ay = 0x0104, 278 .ru = 0x0733, .gu = 0x052d, .bu = 0x05c7, .au = 0x0200, 279 .rv = 0x0340, .gv = 0x030c, .bv = 0x06d0, .av = 0x0200, 280 }; 281 282 static const struct video_levels pal_n_levels_composite = { 283 .blank = 225, .black = 267, .burst = 118, 284 }; 285 286 static const struct color_conversion pal_n_csc_svideo = { 287 .ry = 0x0332, .gy = 0x012d, .by = 0x07d3, .ay = 0x0133, 288 .ru = 0x076a, .gu = 0x0564, .bu = 0x030d, .au = 0x0200, 289 .rv = 0x037a, .gv = 0x033d, .bv = 0x06f6, .av = 0x0200, 290 }; 291 292 static const struct video_levels pal_n_levels_svideo = { 293 .blank = 266, .black = 316, .burst = 139, 294 }; 295 296 /* 297 * Component connections 298 */ 299 static const struct color_conversion sdtv_csc_yprpb = { 300 .ry = 0x0332, .gy = 0x012d, .by = 0x07d3, .ay = 0x0145, 301 .ru = 0x0559, .gu = 0x0353, .bu = 0x0100, .au = 0x0200, 302 .rv = 0x0100, .gv = 0x03ad, .bv = 0x074d, .av = 0x0200, 303 }; 304 305 static const struct color_conversion hdtv_csc_yprpb = { 306 .ry = 0x05b3, .gy = 0x016e, .by = 0x0728, .ay = 0x0145, 307 .ru = 0x07d5, .gu = 0x038b, .bu = 0x0100, .au = 0x0200, 308 .rv = 0x0100, .gv = 0x03d1, .bv = 0x06bc, .av = 0x0200, 309 }; 310 311 static const struct video_levels component_levels = { 312 .blank = 279, .black = 279, .burst = 0, 313 }; 314 315 316 struct tv_mode { 317 const char *name; 318 319 u32 clock; 320 u16 refresh; /* in millihertz (for precision) */ 321 u8 oversample; 322 u8 hsync_end; 323 u16 hblank_start, hblank_end, htotal; 324 bool progressive : 1, trilevel_sync : 1, component_only : 1; 325 u8 vsync_start_f1, vsync_start_f2, vsync_len; 326 bool veq_ena : 1; 327 u8 veq_start_f1, veq_start_f2, veq_len; 328 u8 vi_end_f1, vi_end_f2; 329 u16 nbr_end; 330 bool burst_ena : 1; 331 u8 hburst_start, hburst_len; 332 u8 vburst_start_f1; 333 u16 vburst_end_f1; 334 u8 vburst_start_f2; 335 u16 vburst_end_f2; 336 u8 vburst_start_f3; 337 u16 vburst_end_f3; 338 u8 vburst_start_f4; 339 u16 vburst_end_f4; 340 /* 341 * subcarrier programming 342 */ 343 u16 dda2_size, dda3_size; 344 u8 dda1_inc; 345 u16 dda2_inc, dda3_inc; 346 u32 sc_reset; 347 bool pal_burst : 1; 348 /* 349 * blank/black levels 350 */ 351 const struct video_levels *composite_levels, *svideo_levels; 352 const struct color_conversion *composite_color, *svideo_color; 353 const u32 *filter_table; 354 }; 355 356 357 /* 358 * Sub carrier DDA 359 * 360 * I think this works as follows: 361 * 362 * subcarrier freq = pixel_clock * (dda1_inc + dda2_inc / dda2_size) / 4096 363 * 364 * Presumably, when dda3 is added in, it gets to adjust the dda2_inc value 365 * 366 * So, 367 * dda1_ideal = subcarrier/pixel * 4096 368 * dda1_inc = floor (dda1_ideal) 369 * dda2 = dda1_ideal - dda1_inc 370 * 371 * then pick a ratio for dda2 that gives the closest approximation. If 372 * you can't get close enough, you can play with dda3 as well. This 373 * seems likely to happen when dda2 is small as the jumps would be larger 374 * 375 * To invert this, 376 * 377 * pixel_clock = subcarrier * 4096 / (dda1_inc + dda2_inc / dda2_size) 378 * 379 * The constants below were all computed using a 107.520MHz clock 380 */ 381 382 /* 383 * Register programming values for TV modes. 384 * 385 * These values account for -1s required. 386 */ 387 static const struct tv_mode tv_modes[] = { 388 { 389 .name = "NTSC-M", 390 .clock = 108000, 391 .refresh = 59940, 392 .oversample = 8, 393 .component_only = false, 394 /* 525 Lines, 60 Fields, 15.734KHz line, Sub-Carrier 3.580MHz */ 395 396 .hsync_end = 64, .hblank_end = 124, 397 .hblank_start = 836, .htotal = 857, 398 399 .progressive = false, .trilevel_sync = false, 400 401 .vsync_start_f1 = 6, .vsync_start_f2 = 7, 402 .vsync_len = 6, 403 404 .veq_ena = true, .veq_start_f1 = 0, 405 .veq_start_f2 = 1, .veq_len = 18, 406 407 .vi_end_f1 = 20, .vi_end_f2 = 21, 408 .nbr_end = 240, 409 410 .burst_ena = true, 411 .hburst_start = 72, .hburst_len = 34, 412 .vburst_start_f1 = 9, .vburst_end_f1 = 240, 413 .vburst_start_f2 = 10, .vburst_end_f2 = 240, 414 .vburst_start_f3 = 9, .vburst_end_f3 = 240, 415 .vburst_start_f4 = 10, .vburst_end_f4 = 240, 416 417 /* desired 3.5800000 actual 3.5800000 clock 107.52 */ 418 .dda1_inc = 135, 419 .dda2_inc = 20800, .dda2_size = 27456, 420 .dda3_inc = 0, .dda3_size = 0, 421 .sc_reset = TV_SC_RESET_EVERY_4, 422 .pal_burst = false, 423 424 .composite_levels = &ntsc_m_levels_composite, 425 .composite_color = &ntsc_m_csc_composite, 426 .svideo_levels = &ntsc_m_levels_svideo, 427 .svideo_color = &ntsc_m_csc_svideo, 428 429 .filter_table = filter_table, 430 }, 431 { 432 .name = "NTSC-443", 433 .clock = 108000, 434 .refresh = 59940, 435 .oversample = 8, 436 .component_only = false, 437 /* 525 Lines, 60 Fields, 15.734KHz line, Sub-Carrier 4.43MHz */ 438 .hsync_end = 64, .hblank_end = 124, 439 .hblank_start = 836, .htotal = 857, 440 441 .progressive = false, .trilevel_sync = false, 442 443 .vsync_start_f1 = 6, .vsync_start_f2 = 7, 444 .vsync_len = 6, 445 446 .veq_ena = true, .veq_start_f1 = 0, 447 .veq_start_f2 = 1, .veq_len = 18, 448 449 .vi_end_f1 = 20, .vi_end_f2 = 21, 450 .nbr_end = 240, 451 452 .burst_ena = true, 453 .hburst_start = 72, .hburst_len = 34, 454 .vburst_start_f1 = 9, .vburst_end_f1 = 240, 455 .vburst_start_f2 = 10, .vburst_end_f2 = 240, 456 .vburst_start_f3 = 9, .vburst_end_f3 = 240, 457 .vburst_start_f4 = 10, .vburst_end_f4 = 240, 458 459 /* desired 4.4336180 actual 4.4336180 clock 107.52 */ 460 .dda1_inc = 168, 461 .dda2_inc = 4093, .dda2_size = 27456, 462 .dda3_inc = 310, .dda3_size = 525, 463 .sc_reset = TV_SC_RESET_NEVER, 464 .pal_burst = false, 465 466 .composite_levels = &ntsc_m_levels_composite, 467 .composite_color = &ntsc_m_csc_composite, 468 .svideo_levels = &ntsc_m_levels_svideo, 469 .svideo_color = &ntsc_m_csc_svideo, 470 471 .filter_table = filter_table, 472 }, 473 { 474 .name = "NTSC-J", 475 .clock = 108000, 476 .refresh = 59940, 477 .oversample = 8, 478 .component_only = false, 479 480 /* 525 Lines, 60 Fields, 15.734KHz line, Sub-Carrier 3.580MHz */ 481 .hsync_end = 64, .hblank_end = 124, 482 .hblank_start = 836, .htotal = 857, 483 484 .progressive = false, .trilevel_sync = false, 485 486 .vsync_start_f1 = 6, .vsync_start_f2 = 7, 487 .vsync_len = 6, 488 489 .veq_ena = true, .veq_start_f1 = 0, 490 .veq_start_f2 = 1, .veq_len = 18, 491 492 .vi_end_f1 = 20, .vi_end_f2 = 21, 493 .nbr_end = 240, 494 495 .burst_ena = true, 496 .hburst_start = 72, .hburst_len = 34, 497 .vburst_start_f1 = 9, .vburst_end_f1 = 240, 498 .vburst_start_f2 = 10, .vburst_end_f2 = 240, 499 .vburst_start_f3 = 9, .vburst_end_f3 = 240, 500 .vburst_start_f4 = 10, .vburst_end_f4 = 240, 501 502 /* desired 3.5800000 actual 3.5800000 clock 107.52 */ 503 .dda1_inc = 135, 504 .dda2_inc = 20800, .dda2_size = 27456, 505 .dda3_inc = 0, .dda3_size = 0, 506 .sc_reset = TV_SC_RESET_EVERY_4, 507 .pal_burst = false, 508 509 .composite_levels = &ntsc_j_levels_composite, 510 .composite_color = &ntsc_j_csc_composite, 511 .svideo_levels = &ntsc_j_levels_svideo, 512 .svideo_color = &ntsc_j_csc_svideo, 513 514 .filter_table = filter_table, 515 }, 516 { 517 .name = "PAL-M", 518 .clock = 108000, 519 .refresh = 59940, 520 .oversample = 8, 521 .component_only = false, 522 523 /* 525 Lines, 60 Fields, 15.734KHz line, Sub-Carrier 3.580MHz */ 524 .hsync_end = 64, .hblank_end = 124, 525 .hblank_start = 836, .htotal = 857, 526 527 .progressive = false, .trilevel_sync = false, 528 529 .vsync_start_f1 = 6, .vsync_start_f2 = 7, 530 .vsync_len = 6, 531 532 .veq_ena = true, .veq_start_f1 = 0, 533 .veq_start_f2 = 1, .veq_len = 18, 534 535 .vi_end_f1 = 20, .vi_end_f2 = 21, 536 .nbr_end = 240, 537 538 .burst_ena = true, 539 .hburst_start = 72, .hburst_len = 34, 540 .vburst_start_f1 = 9, .vburst_end_f1 = 240, 541 .vburst_start_f2 = 10, .vburst_end_f2 = 240, 542 .vburst_start_f3 = 9, .vburst_end_f3 = 240, 543 .vburst_start_f4 = 10, .vburst_end_f4 = 240, 544 545 /* desired 3.5800000 actual 3.5800000 clock 107.52 */ 546 .dda1_inc = 135, 547 .dda2_inc = 16704, .dda2_size = 27456, 548 .dda3_inc = 0, .dda3_size = 0, 549 .sc_reset = TV_SC_RESET_EVERY_8, 550 .pal_burst = true, 551 552 .composite_levels = &pal_m_levels_composite, 553 .composite_color = &pal_m_csc_composite, 554 .svideo_levels = &pal_m_levels_svideo, 555 .svideo_color = &pal_m_csc_svideo, 556 557 .filter_table = filter_table, 558 }, 559 { 560 /* 625 Lines, 50 Fields, 15.625KHz line, Sub-Carrier 4.434MHz */ 561 .name = "PAL-N", 562 .clock = 108000, 563 .refresh = 50000, 564 .oversample = 8, 565 .component_only = false, 566 567 .hsync_end = 64, .hblank_end = 128, 568 .hblank_start = 844, .htotal = 863, 569 570 .progressive = false, .trilevel_sync = false, 571 572 573 .vsync_start_f1 = 6, .vsync_start_f2 = 7, 574 .vsync_len = 6, 575 576 .veq_ena = true, .veq_start_f1 = 0, 577 .veq_start_f2 = 1, .veq_len = 18, 578 579 .vi_end_f1 = 24, .vi_end_f2 = 25, 580 .nbr_end = 286, 581 582 .burst_ena = true, 583 .hburst_start = 73, .hburst_len = 34, 584 .vburst_start_f1 = 8, .vburst_end_f1 = 285, 585 .vburst_start_f2 = 8, .vburst_end_f2 = 286, 586 .vburst_start_f3 = 9, .vburst_end_f3 = 286, 587 .vburst_start_f4 = 9, .vburst_end_f4 = 285, 588 589 590 /* desired 4.4336180 actual 4.4336180 clock 107.52 */ 591 .dda1_inc = 135, 592 .dda2_inc = 23578, .dda2_size = 27648, 593 .dda3_inc = 134, .dda3_size = 625, 594 .sc_reset = TV_SC_RESET_EVERY_8, 595 .pal_burst = true, 596 597 .composite_levels = &pal_n_levels_composite, 598 .composite_color = &pal_n_csc_composite, 599 .svideo_levels = &pal_n_levels_svideo, 600 .svideo_color = &pal_n_csc_svideo, 601 602 .filter_table = filter_table, 603 }, 604 { 605 /* 625 Lines, 50 Fields, 15.625KHz line, Sub-Carrier 4.434MHz */ 606 .name = "PAL", 607 .clock = 108000, 608 .refresh = 50000, 609 .oversample = 8, 610 .component_only = false, 611 612 .hsync_end = 64, .hblank_end = 142, 613 .hblank_start = 844, .htotal = 863, 614 615 .progressive = false, .trilevel_sync = false, 616 617 .vsync_start_f1 = 5, .vsync_start_f2 = 6, 618 .vsync_len = 5, 619 620 .veq_ena = true, .veq_start_f1 = 0, 621 .veq_start_f2 = 1, .veq_len = 15, 622 623 .vi_end_f1 = 24, .vi_end_f2 = 25, 624 .nbr_end = 286, 625 626 .burst_ena = true, 627 .hburst_start = 73, .hburst_len = 32, 628 .vburst_start_f1 = 8, .vburst_end_f1 = 285, 629 .vburst_start_f2 = 8, .vburst_end_f2 = 286, 630 .vburst_start_f3 = 9, .vburst_end_f3 = 286, 631 .vburst_start_f4 = 9, .vburst_end_f4 = 285, 632 633 /* desired 4.4336180 actual 4.4336180 clock 107.52 */ 634 .dda1_inc = 168, 635 .dda2_inc = 4122, .dda2_size = 27648, 636 .dda3_inc = 67, .dda3_size = 625, 637 .sc_reset = TV_SC_RESET_EVERY_8, 638 .pal_burst = true, 639 640 .composite_levels = &pal_levels_composite, 641 .composite_color = &pal_csc_composite, 642 .svideo_levels = &pal_levels_svideo, 643 .svideo_color = &pal_csc_svideo, 644 645 .filter_table = filter_table, 646 }, 647 { 648 .name = "480p", 649 .clock = 108000, 650 .refresh = 59940, 651 .oversample = 4, 652 .component_only = true, 653 654 .hsync_end = 64, .hblank_end = 122, 655 .hblank_start = 842, .htotal = 857, 656 657 .progressive = true, .trilevel_sync = false, 658 659 .vsync_start_f1 = 12, .vsync_start_f2 = 12, 660 .vsync_len = 12, 661 662 .veq_ena = false, 663 664 .vi_end_f1 = 44, .vi_end_f2 = 44, 665 .nbr_end = 479, 666 667 .burst_ena = false, 668 669 .filter_table = filter_table, 670 }, 671 { 672 .name = "576p", 673 .clock = 108000, 674 .refresh = 50000, 675 .oversample = 4, 676 .component_only = true, 677 678 .hsync_end = 64, .hblank_end = 139, 679 .hblank_start = 859, .htotal = 863, 680 681 .progressive = true, .trilevel_sync = false, 682 683 .vsync_start_f1 = 10, .vsync_start_f2 = 10, 684 .vsync_len = 10, 685 686 .veq_ena = false, 687 688 .vi_end_f1 = 48, .vi_end_f2 = 48, 689 .nbr_end = 575, 690 691 .burst_ena = false, 692 693 .filter_table = filter_table, 694 }, 695 { 696 .name = "720p@60Hz", 697 .clock = 148500, 698 .refresh = 60000, 699 .oversample = 2, 700 .component_only = true, 701 702 .hsync_end = 80, .hblank_end = 300, 703 .hblank_start = 1580, .htotal = 1649, 704 705 .progressive = true, .trilevel_sync = true, 706 707 .vsync_start_f1 = 10, .vsync_start_f2 = 10, 708 .vsync_len = 10, 709 710 .veq_ena = false, 711 712 .vi_end_f1 = 29, .vi_end_f2 = 29, 713 .nbr_end = 719, 714 715 .burst_ena = false, 716 717 .filter_table = filter_table, 718 }, 719 { 720 .name = "720p@50Hz", 721 .clock = 148500, 722 .refresh = 50000, 723 .oversample = 2, 724 .component_only = true, 725 726 .hsync_end = 80, .hblank_end = 300, 727 .hblank_start = 1580, .htotal = 1979, 728 729 .progressive = true, .trilevel_sync = true, 730 731 .vsync_start_f1 = 10, .vsync_start_f2 = 10, 732 .vsync_len = 10, 733 734 .veq_ena = false, 735 736 .vi_end_f1 = 29, .vi_end_f2 = 29, 737 .nbr_end = 719, 738 739 .burst_ena = false, 740 741 .filter_table = filter_table, 742 }, 743 { 744 .name = "1080i@50Hz", 745 .clock = 148500, 746 .refresh = 50000, 747 .oversample = 2, 748 .component_only = true, 749 750 .hsync_end = 88, .hblank_end = 235, 751 .hblank_start = 2155, .htotal = 2639, 752 753 .progressive = false, .trilevel_sync = true, 754 755 .vsync_start_f1 = 4, .vsync_start_f2 = 5, 756 .vsync_len = 10, 757 758 .veq_ena = true, .veq_start_f1 = 4, 759 .veq_start_f2 = 4, .veq_len = 10, 760 761 762 .vi_end_f1 = 21, .vi_end_f2 = 22, 763 .nbr_end = 539, 764 765 .burst_ena = false, 766 767 .filter_table = filter_table, 768 }, 769 { 770 .name = "1080i@60Hz", 771 .clock = 148500, 772 .refresh = 60000, 773 .oversample = 2, 774 .component_only = true, 775 776 .hsync_end = 88, .hblank_end = 235, 777 .hblank_start = 2155, .htotal = 2199, 778 779 .progressive = false, .trilevel_sync = true, 780 781 .vsync_start_f1 = 4, .vsync_start_f2 = 5, 782 .vsync_len = 10, 783 784 .veq_ena = true, .veq_start_f1 = 4, 785 .veq_start_f2 = 4, .veq_len = 10, 786 787 788 .vi_end_f1 = 21, .vi_end_f2 = 22, 789 .nbr_end = 539, 790 791 .burst_ena = false, 792 793 .filter_table = filter_table, 794 }, 795 796 { 797 .name = "1080p@30Hz", 798 .clock = 148500, 799 .refresh = 30000, 800 .oversample = 2, 801 .component_only = true, 802 803 .hsync_end = 88, .hblank_end = 235, 804 .hblank_start = 2155, .htotal = 2199, 805 806 .progressive = true, .trilevel_sync = true, 807 808 .vsync_start_f1 = 8, .vsync_start_f2 = 8, 809 .vsync_len = 10, 810 811 .veq_ena = false, .veq_start_f1 = 0, 812 .veq_start_f2 = 0, .veq_len = 0, 813 814 .vi_end_f1 = 44, .vi_end_f2 = 44, 815 .nbr_end = 1079, 816 817 .burst_ena = false, 818 819 .filter_table = filter_table, 820 }, 821 822 { 823 .name = "1080p@50Hz", 824 .clock = 148500, 825 .refresh = 50000, 826 .oversample = 1, 827 .component_only = true, 828 829 .hsync_end = 88, .hblank_end = 235, 830 .hblank_start = 2155, .htotal = 2639, 831 832 .progressive = true, .trilevel_sync = true, 833 834 .vsync_start_f1 = 8, .vsync_start_f2 = 8, 835 .vsync_len = 10, 836 837 .veq_ena = false, .veq_start_f1 = 0, 838 .veq_start_f2 = 0, .veq_len = 0, 839 840 .vi_end_f1 = 44, .vi_end_f2 = 44, 841 .nbr_end = 1079, 842 843 .burst_ena = false, 844 845 .filter_table = filter_table, 846 }, 847 848 { 849 .name = "1080p@60Hz", 850 .clock = 148500, 851 .refresh = 60000, 852 .oversample = 1, 853 .component_only = true, 854 855 .hsync_end = 88, .hblank_end = 235, 856 .hblank_start = 2155, .htotal = 2199, 857 858 .progressive = true, .trilevel_sync = true, 859 860 .vsync_start_f1 = 8, .vsync_start_f2 = 8, 861 .vsync_len = 10, 862 863 .veq_ena = false, .veq_start_f1 = 0, 864 .veq_start_f2 = 0, .veq_len = 0, 865 866 .vi_end_f1 = 44, .vi_end_f2 = 44, 867 .nbr_end = 1079, 868 869 .burst_ena = false, 870 871 .filter_table = filter_table, 872 }, 873 }; 874 875 struct intel_tv_connector_state { 876 struct drm_connector_state base; 877 878 /* 879 * May need to override the user margins for 880 * gen3 >1024 wide source vertical centering. 881 */ 882 struct { 883 u16 top, bottom; 884 } margins; 885 886 bool bypass_vfilter; 887 }; 888 889 #define to_intel_tv_connector_state(conn_state) \ 890 container_of_const((conn_state), struct intel_tv_connector_state, base) 891 892 static struct drm_connector_state * 893 intel_tv_connector_duplicate_state(struct drm_connector *connector) 894 { 895 struct intel_tv_connector_state *state; 896 897 state = kmemdup(connector->state, sizeof(*state), GFP_KERNEL); 898 if (!state) 899 return NULL; 900 901 __drm_atomic_helper_connector_duplicate_state(connector, &state->base); 902 return &state->base; 903 } 904 905 static struct intel_tv *enc_to_tv(struct intel_encoder *encoder) 906 { 907 return container_of(encoder, struct intel_tv, base); 908 } 909 910 static struct intel_tv *intel_attached_tv(struct intel_connector *connector) 911 { 912 return enc_to_tv(intel_attached_encoder(connector)); 913 } 914 915 static bool 916 intel_tv_get_hw_state(struct intel_encoder *encoder, enum pipe *pipe) 917 { 918 struct intel_display *display = to_intel_display(encoder); 919 u32 tmp = intel_de_read(display, TV_CTL); 920 921 *pipe = (tmp & TV_ENC_PIPE_SEL_MASK) >> TV_ENC_PIPE_SEL_SHIFT; 922 923 return tmp & TV_ENC_ENABLE; 924 } 925 926 static void 927 intel_enable_tv(struct intel_atomic_state *state, 928 struct intel_encoder *encoder, 929 const struct intel_crtc_state *pipe_config, 930 const struct drm_connector_state *conn_state) 931 { 932 struct intel_display *display = to_intel_display(encoder); 933 934 /* Prevents vblank waits from timing out in intel_tv_detect_type() */ 935 intel_crtc_wait_for_next_vblank(to_intel_crtc(pipe_config->uapi.crtc)); 936 937 intel_de_rmw(display, TV_CTL, 0, TV_ENC_ENABLE); 938 } 939 940 static void 941 intel_disable_tv(struct intel_atomic_state *state, 942 struct intel_encoder *encoder, 943 const struct intel_crtc_state *old_crtc_state, 944 const struct drm_connector_state *old_conn_state) 945 { 946 struct intel_display *display = to_intel_display(encoder); 947 948 intel_de_rmw(display, TV_CTL, TV_ENC_ENABLE, 0); 949 } 950 951 static const struct tv_mode *intel_tv_mode_find(const struct drm_connector_state *conn_state) 952 { 953 int format = conn_state->tv.legacy_mode; 954 955 return &tv_modes[format]; 956 } 957 958 static enum drm_mode_status 959 intel_tv_mode_valid(struct drm_connector *connector, 960 const struct drm_display_mode *mode) 961 { 962 struct intel_display *display = to_intel_display(connector->dev); 963 const struct tv_mode *tv_mode = intel_tv_mode_find(connector->state); 964 int max_dotclk = display->cdclk.max_dotclk_freq; 965 enum drm_mode_status status; 966 967 status = intel_cpu_transcoder_mode_valid(display, mode); 968 if (status != MODE_OK) 969 return status; 970 971 if (mode->clock > max_dotclk) 972 return MODE_CLOCK_HIGH; 973 974 /* Ensure TV refresh is close to desired refresh */ 975 if (abs(tv_mode->refresh - drm_mode_vrefresh(mode) * 1000) >= 1000) 976 return MODE_CLOCK_RANGE; 977 978 return MODE_OK; 979 } 980 981 static int 982 intel_tv_mode_vdisplay(const struct tv_mode *tv_mode) 983 { 984 if (tv_mode->progressive) 985 return tv_mode->nbr_end + 1; 986 else 987 return 2 * (tv_mode->nbr_end + 1); 988 } 989 990 static void 991 intel_tv_mode_to_mode(struct drm_display_mode *mode, 992 const struct tv_mode *tv_mode, 993 int clock) 994 { 995 mode->clock = clock / (tv_mode->oversample >> !tv_mode->progressive); 996 997 /* 998 * tv_mode horizontal timings: 999 * 1000 * hsync_end 1001 * | hblank_end 1002 * | | hblank_start 1003 * | | | htotal 1004 * | _______ | 1005 * ____/ \___ 1006 * \__/ \ 1007 */ 1008 mode->hdisplay = 1009 tv_mode->hblank_start - tv_mode->hblank_end; 1010 mode->hsync_start = mode->hdisplay + 1011 tv_mode->htotal - tv_mode->hblank_start; 1012 mode->hsync_end = mode->hsync_start + 1013 tv_mode->hsync_end; 1014 mode->htotal = tv_mode->htotal + 1; 1015 1016 /* 1017 * tv_mode vertical timings: 1018 * 1019 * vsync_start 1020 * | vsync_end 1021 * | | vi_end nbr_end 1022 * | | | | 1023 * | | _______ 1024 * \__ ____/ \ 1025 * \__/ 1026 */ 1027 mode->vdisplay = intel_tv_mode_vdisplay(tv_mode); 1028 if (tv_mode->progressive) { 1029 mode->vsync_start = mode->vdisplay + 1030 tv_mode->vsync_start_f1 + 1; 1031 mode->vsync_end = mode->vsync_start + 1032 tv_mode->vsync_len; 1033 mode->vtotal = mode->vdisplay + 1034 tv_mode->vi_end_f1 + 1; 1035 } else { 1036 mode->vsync_start = mode->vdisplay + 1037 tv_mode->vsync_start_f1 + 1 + 1038 tv_mode->vsync_start_f2 + 1; 1039 mode->vsync_end = mode->vsync_start + 1040 2 * tv_mode->vsync_len; 1041 mode->vtotal = mode->vdisplay + 1042 tv_mode->vi_end_f1 + 1 + 1043 tv_mode->vi_end_f2 + 1; 1044 } 1045 1046 /* TV has it's own notion of sync and other mode flags, so clear them. */ 1047 mode->flags = 0; 1048 1049 snprintf(mode->name, sizeof(mode->name), 1050 "%dx%d%c (%s)", 1051 mode->hdisplay, mode->vdisplay, 1052 tv_mode->progressive ? 'p' : 'i', 1053 tv_mode->name); 1054 } 1055 1056 static void intel_tv_scale_mode_horiz(struct drm_display_mode *mode, 1057 int hdisplay, int left_margin, 1058 int right_margin) 1059 { 1060 int hsync_start = mode->hsync_start - mode->hdisplay + right_margin; 1061 int hsync_end = mode->hsync_end - mode->hdisplay + right_margin; 1062 int new_htotal = mode->htotal * hdisplay / 1063 (mode->hdisplay - left_margin - right_margin); 1064 1065 mode->clock = mode->clock * new_htotal / mode->htotal; 1066 1067 mode->hdisplay = hdisplay; 1068 mode->hsync_start = hdisplay + hsync_start * new_htotal / mode->htotal; 1069 mode->hsync_end = hdisplay + hsync_end * new_htotal / mode->htotal; 1070 mode->htotal = new_htotal; 1071 } 1072 1073 static void intel_tv_scale_mode_vert(struct drm_display_mode *mode, 1074 int vdisplay, int top_margin, 1075 int bottom_margin) 1076 { 1077 int vsync_start = mode->vsync_start - mode->vdisplay + bottom_margin; 1078 int vsync_end = mode->vsync_end - mode->vdisplay + bottom_margin; 1079 int new_vtotal = mode->vtotal * vdisplay / 1080 (mode->vdisplay - top_margin - bottom_margin); 1081 1082 mode->clock = mode->clock * new_vtotal / mode->vtotal; 1083 1084 mode->vdisplay = vdisplay; 1085 mode->vsync_start = vdisplay + vsync_start * new_vtotal / mode->vtotal; 1086 mode->vsync_end = vdisplay + vsync_end * new_vtotal / mode->vtotal; 1087 mode->vtotal = new_vtotal; 1088 } 1089 1090 static void 1091 intel_tv_get_config(struct intel_encoder *encoder, 1092 struct intel_crtc_state *pipe_config) 1093 { 1094 struct intel_display *display = to_intel_display(encoder); 1095 struct drm_display_mode *adjusted_mode = 1096 &pipe_config->hw.adjusted_mode; 1097 struct drm_display_mode mode = {}; 1098 u32 tv_ctl, hctl1, hctl3, vctl1, vctl2, tmp; 1099 struct tv_mode tv_mode = {}; 1100 int hdisplay = adjusted_mode->crtc_hdisplay; 1101 int vdisplay = adjusted_mode->crtc_vdisplay; 1102 int xsize, ysize, xpos, ypos; 1103 1104 pipe_config->output_types |= BIT(INTEL_OUTPUT_TVOUT); 1105 1106 tv_ctl = intel_de_read(display, TV_CTL); 1107 hctl1 = intel_de_read(display, TV_H_CTL_1); 1108 hctl3 = intel_de_read(display, TV_H_CTL_3); 1109 vctl1 = intel_de_read(display, TV_V_CTL_1); 1110 vctl2 = intel_de_read(display, TV_V_CTL_2); 1111 1112 tv_mode.htotal = (hctl1 & TV_HTOTAL_MASK) >> TV_HTOTAL_SHIFT; 1113 tv_mode.hsync_end = (hctl1 & TV_HSYNC_END_MASK) >> TV_HSYNC_END_SHIFT; 1114 1115 tv_mode.hblank_start = (hctl3 & TV_HBLANK_START_MASK) >> TV_HBLANK_START_SHIFT; 1116 tv_mode.hblank_end = (hctl3 & TV_HSYNC_END_MASK) >> TV_HBLANK_END_SHIFT; 1117 1118 tv_mode.nbr_end = (vctl1 & TV_NBR_END_MASK) >> TV_NBR_END_SHIFT; 1119 tv_mode.vi_end_f1 = (vctl1 & TV_VI_END_F1_MASK) >> TV_VI_END_F1_SHIFT; 1120 tv_mode.vi_end_f2 = (vctl1 & TV_VI_END_F2_MASK) >> TV_VI_END_F2_SHIFT; 1121 1122 tv_mode.vsync_len = (vctl2 & TV_VSYNC_LEN_MASK) >> TV_VSYNC_LEN_SHIFT; 1123 tv_mode.vsync_start_f1 = (vctl2 & TV_VSYNC_START_F1_MASK) >> TV_VSYNC_START_F1_SHIFT; 1124 tv_mode.vsync_start_f2 = (vctl2 & TV_VSYNC_START_F2_MASK) >> TV_VSYNC_START_F2_SHIFT; 1125 1126 tv_mode.clock = pipe_config->port_clock; 1127 1128 tv_mode.progressive = tv_ctl & TV_PROGRESSIVE; 1129 1130 switch (tv_ctl & TV_OVERSAMPLE_MASK) { 1131 case TV_OVERSAMPLE_8X: 1132 tv_mode.oversample = 8; 1133 break; 1134 case TV_OVERSAMPLE_4X: 1135 tv_mode.oversample = 4; 1136 break; 1137 case TV_OVERSAMPLE_2X: 1138 tv_mode.oversample = 2; 1139 break; 1140 default: 1141 tv_mode.oversample = 1; 1142 break; 1143 } 1144 1145 tmp = intel_de_read(display, TV_WIN_POS); 1146 xpos = tmp >> 16; 1147 ypos = tmp & 0xffff; 1148 1149 tmp = intel_de_read(display, TV_WIN_SIZE); 1150 xsize = tmp >> 16; 1151 ysize = tmp & 0xffff; 1152 1153 intel_tv_mode_to_mode(&mode, &tv_mode, pipe_config->port_clock); 1154 1155 drm_dbg_kms(display->drm, "TV mode: " DRM_MODE_FMT "\n", 1156 DRM_MODE_ARG(&mode)); 1157 1158 intel_tv_scale_mode_horiz(&mode, hdisplay, 1159 xpos, mode.hdisplay - xsize - xpos); 1160 intel_tv_scale_mode_vert(&mode, vdisplay, 1161 ypos, mode.vdisplay - ysize - ypos); 1162 1163 adjusted_mode->crtc_clock = mode.clock; 1164 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) 1165 adjusted_mode->crtc_clock /= 2; 1166 1167 /* pixel counter doesn't work on i965gm TV output */ 1168 if (display->platform.i965gm) 1169 pipe_config->mode_flags |= 1170 I915_MODE_FLAG_USE_SCANLINE_COUNTER; 1171 } 1172 1173 static bool intel_tv_source_too_wide(struct intel_display *display, 1174 int hdisplay) 1175 { 1176 return DISPLAY_VER(display) == 3 && hdisplay > 1024; 1177 } 1178 1179 static bool intel_tv_vert_scaling(const struct drm_display_mode *tv_mode, 1180 const struct drm_connector_state *conn_state, 1181 int vdisplay) 1182 { 1183 return tv_mode->crtc_vdisplay - 1184 conn_state->tv.margins.top - 1185 conn_state->tv.margins.bottom != 1186 vdisplay; 1187 } 1188 1189 static int 1190 intel_tv_compute_config(struct intel_atomic_state *state, 1191 struct intel_encoder *encoder, 1192 struct intel_crtc_state *pipe_config, 1193 struct drm_connector_state *conn_state) 1194 { 1195 struct intel_display *display = to_intel_display(encoder); 1196 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 1197 struct intel_tv_connector_state *tv_conn_state = 1198 to_intel_tv_connector_state(conn_state); 1199 const struct tv_mode *tv_mode = intel_tv_mode_find(conn_state); 1200 struct drm_display_mode *adjusted_mode = 1201 &pipe_config->hw.adjusted_mode; 1202 int hdisplay = adjusted_mode->crtc_hdisplay; 1203 int vdisplay = adjusted_mode->crtc_vdisplay; 1204 int ret; 1205 1206 if (!tv_mode) 1207 return -EINVAL; 1208 1209 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN) 1210 return -EINVAL; 1211 1212 pipe_config->sink_format = INTEL_OUTPUT_FORMAT_RGB; 1213 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; 1214 1215 drm_dbg_kms(display->drm, "forcing bpc to 8 for TV\n"); 1216 pipe_config->pipe_bpp = 8*3; 1217 1218 pipe_config->port_clock = tv_mode->clock; 1219 1220 ret = intel_dpll_crtc_compute_clock(state, crtc); 1221 if (ret) 1222 return ret; 1223 1224 pipe_config->clock_set = true; 1225 1226 intel_tv_mode_to_mode(adjusted_mode, tv_mode, pipe_config->port_clock); 1227 drm_mode_set_crtcinfo(adjusted_mode, 0); 1228 1229 if (intel_tv_source_too_wide(display, hdisplay) || 1230 !intel_tv_vert_scaling(adjusted_mode, conn_state, vdisplay)) { 1231 int extra, top, bottom; 1232 1233 extra = adjusted_mode->crtc_vdisplay - vdisplay; 1234 1235 if (extra < 0) { 1236 drm_dbg_kms(display->drm, 1237 "No vertical scaling for >1024 pixel wide modes\n"); 1238 return -EINVAL; 1239 } 1240 1241 /* Need to turn off the vertical filter and center the image */ 1242 1243 /* Attempt to maintain the relative sizes of the margins */ 1244 top = conn_state->tv.margins.top; 1245 bottom = conn_state->tv.margins.bottom; 1246 1247 if (top + bottom) 1248 top = extra * top / (top + bottom); 1249 else 1250 top = extra / 2; 1251 bottom = extra - top; 1252 1253 tv_conn_state->margins.top = top; 1254 tv_conn_state->margins.bottom = bottom; 1255 1256 tv_conn_state->bypass_vfilter = true; 1257 1258 if (!tv_mode->progressive) { 1259 adjusted_mode->clock /= 2; 1260 adjusted_mode->crtc_clock /= 2; 1261 adjusted_mode->flags |= DRM_MODE_FLAG_INTERLACE; 1262 } 1263 } else { 1264 tv_conn_state->margins.top = conn_state->tv.margins.top; 1265 tv_conn_state->margins.bottom = conn_state->tv.margins.bottom; 1266 1267 tv_conn_state->bypass_vfilter = false; 1268 } 1269 1270 drm_dbg_kms(display->drm, "TV mode: " DRM_MODE_FMT "\n", 1271 DRM_MODE_ARG(adjusted_mode)); 1272 1273 /* 1274 * The pipe scanline counter behaviour looks as follows when 1275 * using the TV encoder: 1276 * 1277 * time -> 1278 * 1279 * dsl=vtotal-1 | | 1280 * || || 1281 * ___| | ___| | 1282 * / | / | 1283 * / | / | 1284 * dsl=0 ___/ |_____/ | 1285 * | | | | | | 1286 * ^ ^ ^ ^ ^ 1287 * | | | | pipe vblank/first part of tv vblank 1288 * | | | bottom margin 1289 * | | active 1290 * | top margin 1291 * remainder of tv vblank 1292 * 1293 * When the TV encoder is used the pipe wants to run faster 1294 * than expected rate. During the active portion the TV 1295 * encoder stalls the pipe every few lines to keep it in 1296 * check. When the TV encoder reaches the bottom margin the 1297 * pipe simply stops. Once we reach the TV vblank the pipe is 1298 * no longer stalled and it runs at the max rate (apparently 1299 * oversample clock on gen3, cdclk on gen4). Once the pipe 1300 * reaches the pipe vtotal the pipe stops for the remainder 1301 * of the TV vblank/top margin. The pipe starts up again when 1302 * the TV encoder exits the top margin. 1303 * 1304 * To avoid huge hassles for vblank timestamping we scale 1305 * the pipe timings as if the pipe always runs at the average 1306 * rate it maintains during the active period. This also 1307 * gives us a reasonable guesstimate as to the pixel rate. 1308 * Due to the variation in the actual pipe speed the scanline 1309 * counter will give us slightly erroneous results during the 1310 * TV vblank/margins. But since vtotal was selected such that 1311 * it matches the average rate of the pipe during the active 1312 * portion the error shouldn't cause any serious grief to 1313 * vblank timestamps. 1314 * 1315 * For posterity here is the empirically derived formula 1316 * that gives us the maximum length of the pipe vblank 1317 * we can use without causing display corruption. Following 1318 * this would allow us to have a ticking scanline counter 1319 * everywhere except during the bottom margin (there the 1320 * pipe always stops). Ie. this would eliminate the second 1321 * flat portion of the above graph. However this would also 1322 * complicate vblank timestamping as the pipe vtotal would 1323 * no longer match the average rate the pipe runs at during 1324 * the active portion. Hence following this formula seems 1325 * more trouble that it's worth. 1326 * 1327 * if (DISPLAY_VER(dev_priv) == 4) { 1328 * num = cdclk * (tv_mode->oversample >> !tv_mode->progressive); 1329 * den = tv_mode->clock; 1330 * } else { 1331 * num = tv_mode->oversample >> !tv_mode->progressive; 1332 * den = 1; 1333 * } 1334 * max_pipe_vblank_len ~= 1335 * (num * tv_htotal * (tv_vblank_len + top_margin)) / 1336 * (den * pipe_htotal); 1337 */ 1338 intel_tv_scale_mode_horiz(adjusted_mode, hdisplay, 1339 conn_state->tv.margins.left, 1340 conn_state->tv.margins.right); 1341 intel_tv_scale_mode_vert(adjusted_mode, vdisplay, 1342 tv_conn_state->margins.top, 1343 tv_conn_state->margins.bottom); 1344 drm_mode_set_crtcinfo(adjusted_mode, 0); 1345 adjusted_mode->name[0] = '\0'; 1346 1347 /* pixel counter doesn't work on i965gm TV output */ 1348 if (display->platform.i965gm) 1349 pipe_config->mode_flags |= 1350 I915_MODE_FLAG_USE_SCANLINE_COUNTER; 1351 1352 return 0; 1353 } 1354 1355 static void 1356 set_tv_mode_timings(struct intel_display *display, 1357 const struct tv_mode *tv_mode, 1358 bool burst_ena) 1359 { 1360 u32 hctl1, hctl2, hctl3; 1361 u32 vctl1, vctl2, vctl3, vctl4, vctl5, vctl6, vctl7; 1362 1363 hctl1 = (tv_mode->hsync_end << TV_HSYNC_END_SHIFT) | 1364 (tv_mode->htotal << TV_HTOTAL_SHIFT); 1365 1366 hctl2 = (tv_mode->hburst_start << 16) | 1367 (tv_mode->hburst_len << TV_HBURST_LEN_SHIFT); 1368 1369 if (burst_ena) 1370 hctl2 |= TV_BURST_ENA; 1371 1372 hctl3 = (tv_mode->hblank_start << TV_HBLANK_START_SHIFT) | 1373 (tv_mode->hblank_end << TV_HBLANK_END_SHIFT); 1374 1375 vctl1 = (tv_mode->nbr_end << TV_NBR_END_SHIFT) | 1376 (tv_mode->vi_end_f1 << TV_VI_END_F1_SHIFT) | 1377 (tv_mode->vi_end_f2 << TV_VI_END_F2_SHIFT); 1378 1379 vctl2 = (tv_mode->vsync_len << TV_VSYNC_LEN_SHIFT) | 1380 (tv_mode->vsync_start_f1 << TV_VSYNC_START_F1_SHIFT) | 1381 (tv_mode->vsync_start_f2 << TV_VSYNC_START_F2_SHIFT); 1382 1383 vctl3 = (tv_mode->veq_len << TV_VEQ_LEN_SHIFT) | 1384 (tv_mode->veq_start_f1 << TV_VEQ_START_F1_SHIFT) | 1385 (tv_mode->veq_start_f2 << TV_VEQ_START_F2_SHIFT); 1386 1387 if (tv_mode->veq_ena) 1388 vctl3 |= TV_EQUAL_ENA; 1389 1390 vctl4 = (tv_mode->vburst_start_f1 << TV_VBURST_START_F1_SHIFT) | 1391 (tv_mode->vburst_end_f1 << TV_VBURST_END_F1_SHIFT); 1392 1393 vctl5 = (tv_mode->vburst_start_f2 << TV_VBURST_START_F2_SHIFT) | 1394 (tv_mode->vburst_end_f2 << TV_VBURST_END_F2_SHIFT); 1395 1396 vctl6 = (tv_mode->vburst_start_f3 << TV_VBURST_START_F3_SHIFT) | 1397 (tv_mode->vburst_end_f3 << TV_VBURST_END_F3_SHIFT); 1398 1399 vctl7 = (tv_mode->vburst_start_f4 << TV_VBURST_START_F4_SHIFT) | 1400 (tv_mode->vburst_end_f4 << TV_VBURST_END_F4_SHIFT); 1401 1402 intel_de_write(display, TV_H_CTL_1, hctl1); 1403 intel_de_write(display, TV_H_CTL_2, hctl2); 1404 intel_de_write(display, TV_H_CTL_3, hctl3); 1405 intel_de_write(display, TV_V_CTL_1, vctl1); 1406 intel_de_write(display, TV_V_CTL_2, vctl2); 1407 intel_de_write(display, TV_V_CTL_3, vctl3); 1408 intel_de_write(display, TV_V_CTL_4, vctl4); 1409 intel_de_write(display, TV_V_CTL_5, vctl5); 1410 intel_de_write(display, TV_V_CTL_6, vctl6); 1411 intel_de_write(display, TV_V_CTL_7, vctl7); 1412 } 1413 1414 static void set_color_conversion(struct intel_display *display, 1415 const struct color_conversion *color_conversion) 1416 { 1417 intel_de_write(display, TV_CSC_Y, 1418 (color_conversion->ry << 16) | color_conversion->gy); 1419 intel_de_write(display, TV_CSC_Y2, 1420 (color_conversion->by << 16) | color_conversion->ay); 1421 intel_de_write(display, TV_CSC_U, 1422 (color_conversion->ru << 16) | color_conversion->gu); 1423 intel_de_write(display, TV_CSC_U2, 1424 (color_conversion->bu << 16) | color_conversion->au); 1425 intel_de_write(display, TV_CSC_V, 1426 (color_conversion->rv << 16) | color_conversion->gv); 1427 intel_de_write(display, TV_CSC_V2, 1428 (color_conversion->bv << 16) | color_conversion->av); 1429 } 1430 1431 static void intel_tv_pre_enable(struct intel_atomic_state *state, 1432 struct intel_encoder *encoder, 1433 const struct intel_crtc_state *pipe_config, 1434 const struct drm_connector_state *conn_state) 1435 { 1436 struct intel_display *display = to_intel_display(encoder); 1437 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 1438 struct intel_tv *intel_tv = enc_to_tv(encoder); 1439 const struct intel_tv_connector_state *tv_conn_state = 1440 to_intel_tv_connector_state(conn_state); 1441 const struct tv_mode *tv_mode = intel_tv_mode_find(conn_state); 1442 u32 tv_ctl, tv_filter_ctl; 1443 u32 scctl1, scctl2, scctl3; 1444 int i, j; 1445 const struct video_levels *video_levels; 1446 const struct color_conversion *color_conversion; 1447 bool burst_ena; 1448 int xpos, ypos; 1449 unsigned int xsize, ysize; 1450 1451 tv_ctl = intel_de_read(display, TV_CTL); 1452 tv_ctl &= TV_CTL_SAVE; 1453 1454 switch (intel_tv->type) { 1455 default: 1456 case DRM_MODE_CONNECTOR_Unknown: 1457 case DRM_MODE_CONNECTOR_Composite: 1458 tv_ctl |= TV_ENC_OUTPUT_COMPOSITE; 1459 video_levels = tv_mode->composite_levels; 1460 color_conversion = tv_mode->composite_color; 1461 burst_ena = tv_mode->burst_ena; 1462 break; 1463 case DRM_MODE_CONNECTOR_Component: 1464 tv_ctl |= TV_ENC_OUTPUT_COMPONENT; 1465 video_levels = &component_levels; 1466 if (tv_mode->burst_ena) 1467 color_conversion = &sdtv_csc_yprpb; 1468 else 1469 color_conversion = &hdtv_csc_yprpb; 1470 burst_ena = false; 1471 break; 1472 case DRM_MODE_CONNECTOR_SVIDEO: 1473 tv_ctl |= TV_ENC_OUTPUT_SVIDEO; 1474 video_levels = tv_mode->svideo_levels; 1475 color_conversion = tv_mode->svideo_color; 1476 burst_ena = tv_mode->burst_ena; 1477 break; 1478 } 1479 1480 tv_ctl |= TV_ENC_PIPE_SEL(crtc->pipe); 1481 1482 switch (tv_mode->oversample) { 1483 case 8: 1484 tv_ctl |= TV_OVERSAMPLE_8X; 1485 break; 1486 case 4: 1487 tv_ctl |= TV_OVERSAMPLE_4X; 1488 break; 1489 case 2: 1490 tv_ctl |= TV_OVERSAMPLE_2X; 1491 break; 1492 default: 1493 tv_ctl |= TV_OVERSAMPLE_NONE; 1494 break; 1495 } 1496 1497 if (tv_mode->progressive) 1498 tv_ctl |= TV_PROGRESSIVE; 1499 if (tv_mode->trilevel_sync) 1500 tv_ctl |= TV_TRILEVEL_SYNC; 1501 if (tv_mode->pal_burst) 1502 tv_ctl |= TV_PAL_BURST; 1503 1504 scctl1 = 0; 1505 if (tv_mode->dda1_inc) 1506 scctl1 |= TV_SC_DDA1_EN; 1507 if (tv_mode->dda2_inc) 1508 scctl1 |= TV_SC_DDA2_EN; 1509 if (tv_mode->dda3_inc) 1510 scctl1 |= TV_SC_DDA3_EN; 1511 scctl1 |= tv_mode->sc_reset; 1512 if (video_levels) 1513 scctl1 |= video_levels->burst << TV_BURST_LEVEL_SHIFT; 1514 scctl1 |= tv_mode->dda1_inc << TV_SCDDA1_INC_SHIFT; 1515 1516 scctl2 = tv_mode->dda2_size << TV_SCDDA2_SIZE_SHIFT | 1517 tv_mode->dda2_inc << TV_SCDDA2_INC_SHIFT; 1518 1519 scctl3 = tv_mode->dda3_size << TV_SCDDA3_SIZE_SHIFT | 1520 tv_mode->dda3_inc << TV_SCDDA3_INC_SHIFT; 1521 1522 /* Enable two fixes for the chips that need them. */ 1523 if (display->platform.i915gm) 1524 tv_ctl |= TV_ENC_C0_FIX | TV_ENC_SDP_FIX; 1525 1526 set_tv_mode_timings(display, tv_mode, burst_ena); 1527 1528 intel_de_write(display, TV_SC_CTL_1, scctl1); 1529 intel_de_write(display, TV_SC_CTL_2, scctl2); 1530 intel_de_write(display, TV_SC_CTL_3, scctl3); 1531 1532 set_color_conversion(display, color_conversion); 1533 1534 if (DISPLAY_VER(display) >= 4) 1535 intel_de_write(display, TV_CLR_KNOBS, 0x00404000); 1536 else 1537 intel_de_write(display, TV_CLR_KNOBS, 0x00606000); 1538 1539 if (video_levels) 1540 intel_de_write(display, TV_CLR_LEVEL, 1541 ((video_levels->black << TV_BLACK_LEVEL_SHIFT) | (video_levels->blank << TV_BLANK_LEVEL_SHIFT))); 1542 1543 assert_transcoder_disabled(display, pipe_config->cpu_transcoder); 1544 1545 /* Filter ctl must be set before TV_WIN_SIZE */ 1546 tv_filter_ctl = TV_AUTO_SCALE; 1547 if (tv_conn_state->bypass_vfilter) 1548 tv_filter_ctl |= TV_V_FILTER_BYPASS; 1549 intel_de_write(display, TV_FILTER_CTL_1, tv_filter_ctl); 1550 1551 xsize = tv_mode->hblank_start - tv_mode->hblank_end; 1552 ysize = intel_tv_mode_vdisplay(tv_mode); 1553 1554 xpos = conn_state->tv.margins.left; 1555 ypos = tv_conn_state->margins.top; 1556 xsize -= (conn_state->tv.margins.left + 1557 conn_state->tv.margins.right); 1558 ysize -= (tv_conn_state->margins.top + 1559 tv_conn_state->margins.bottom); 1560 intel_de_write(display, TV_WIN_POS, (xpos << 16) | ypos); 1561 intel_de_write(display, TV_WIN_SIZE, (xsize << 16) | ysize); 1562 1563 j = 0; 1564 for (i = 0; i < 60; i++) 1565 intel_de_write(display, TV_H_LUMA(i), 1566 tv_mode->filter_table[j++]); 1567 for (i = 0; i < 60; i++) 1568 intel_de_write(display, TV_H_CHROMA(i), 1569 tv_mode->filter_table[j++]); 1570 for (i = 0; i < 43; i++) 1571 intel_de_write(display, TV_V_LUMA(i), 1572 tv_mode->filter_table[j++]); 1573 for (i = 0; i < 43; i++) 1574 intel_de_write(display, TV_V_CHROMA(i), 1575 tv_mode->filter_table[j++]); 1576 intel_de_write(display, TV_DAC, 1577 intel_de_read(display, TV_DAC) & TV_DAC_SAVE); 1578 intel_de_write(display, TV_CTL, tv_ctl); 1579 } 1580 1581 static int 1582 intel_tv_detect_type(struct intel_tv *intel_tv, 1583 struct drm_connector *connector) 1584 { 1585 struct intel_display *display = to_intel_display(connector->dev); 1586 struct intel_crtc *crtc = to_intel_crtc(connector->state->crtc); 1587 u32 tv_ctl, save_tv_ctl; 1588 u32 tv_dac, save_tv_dac; 1589 int type; 1590 1591 /* Disable TV interrupts around load detect or we'll recurse */ 1592 if (connector->polled & DRM_CONNECTOR_POLL_HPD) { 1593 spin_lock_irq(&display->irq.lock); 1594 i915_disable_pipestat(display, 0, 1595 PIPE_HOTPLUG_INTERRUPT_STATUS | 1596 PIPE_HOTPLUG_TV_INTERRUPT_STATUS); 1597 spin_unlock_irq(&display->irq.lock); 1598 } 1599 1600 save_tv_dac = tv_dac = intel_de_read(display, TV_DAC); 1601 save_tv_ctl = tv_ctl = intel_de_read(display, TV_CTL); 1602 1603 /* Poll for TV detection */ 1604 tv_ctl &= ~(TV_ENC_ENABLE | TV_ENC_PIPE_SEL_MASK | TV_TEST_MODE_MASK); 1605 tv_ctl |= TV_TEST_MODE_MONITOR_DETECT; 1606 tv_ctl |= TV_ENC_PIPE_SEL(crtc->pipe); 1607 1608 tv_dac &= ~(TVDAC_SENSE_MASK | DAC_A_MASK | DAC_B_MASK | DAC_C_MASK); 1609 tv_dac |= (TVDAC_STATE_CHG_EN | 1610 TVDAC_A_SENSE_CTL | 1611 TVDAC_B_SENSE_CTL | 1612 TVDAC_C_SENSE_CTL | 1613 DAC_CTL_OVERRIDE | 1614 DAC_A_0_7_V | 1615 DAC_B_0_7_V | 1616 DAC_C_0_7_V); 1617 1618 1619 /* 1620 * The TV sense state should be cleared to zero on cantiga platform. Otherwise 1621 * the TV is misdetected. This is hardware requirement. 1622 */ 1623 if (display->platform.gm45) 1624 tv_dac &= ~(TVDAC_STATE_CHG_EN | TVDAC_A_SENSE_CTL | 1625 TVDAC_B_SENSE_CTL | TVDAC_C_SENSE_CTL); 1626 1627 intel_de_write(display, TV_CTL, tv_ctl); 1628 intel_de_write(display, TV_DAC, tv_dac); 1629 intel_de_posting_read(display, TV_DAC); 1630 1631 intel_crtc_wait_for_next_vblank(crtc); 1632 1633 type = -1; 1634 tv_dac = intel_de_read(display, TV_DAC); 1635 drm_dbg_kms(display->drm, "TV detected: %x, %x\n", tv_ctl, tv_dac); 1636 /* 1637 * A B C 1638 * 0 1 1 Composite 1639 * 1 0 X svideo 1640 * 0 0 0 Component 1641 */ 1642 if ((tv_dac & TVDAC_SENSE_MASK) == (TVDAC_B_SENSE | TVDAC_C_SENSE)) { 1643 drm_dbg_kms(display->drm, 1644 "Detected Composite TV connection\n"); 1645 type = DRM_MODE_CONNECTOR_Composite; 1646 } else if ((tv_dac & (TVDAC_A_SENSE|TVDAC_B_SENSE)) == TVDAC_A_SENSE) { 1647 drm_dbg_kms(display->drm, 1648 "Detected S-Video TV connection\n"); 1649 type = DRM_MODE_CONNECTOR_SVIDEO; 1650 } else if ((tv_dac & TVDAC_SENSE_MASK) == 0) { 1651 drm_dbg_kms(display->drm, 1652 "Detected Component TV connection\n"); 1653 type = DRM_MODE_CONNECTOR_Component; 1654 } else { 1655 drm_dbg_kms(display->drm, "Unrecognised TV connection\n"); 1656 type = -1; 1657 } 1658 1659 intel_de_write(display, TV_DAC, save_tv_dac & ~TVDAC_STATE_CHG_EN); 1660 intel_de_write(display, TV_CTL, save_tv_ctl); 1661 intel_de_posting_read(display, TV_CTL); 1662 1663 /* For unknown reasons the hw barfs if we don't do this vblank wait. */ 1664 intel_crtc_wait_for_next_vblank(crtc); 1665 1666 /* Restore interrupt config */ 1667 if (connector->polled & DRM_CONNECTOR_POLL_HPD) { 1668 spin_lock_irq(&display->irq.lock); 1669 i915_enable_pipestat(display, 0, 1670 PIPE_HOTPLUG_INTERRUPT_STATUS | 1671 PIPE_HOTPLUG_TV_INTERRUPT_STATUS); 1672 spin_unlock_irq(&display->irq.lock); 1673 } 1674 1675 return type; 1676 } 1677 1678 /* 1679 * Here we set accurate tv format according to connector type 1680 * i.e Component TV should not be assigned by NTSC or PAL 1681 */ 1682 static void intel_tv_find_better_format(struct drm_connector *connector) 1683 { 1684 struct intel_tv *intel_tv = intel_attached_tv(to_intel_connector(connector)); 1685 const struct tv_mode *tv_mode = intel_tv_mode_find(connector->state); 1686 int i; 1687 1688 /* Component supports everything so we can keep the current mode */ 1689 if (intel_tv->type == DRM_MODE_CONNECTOR_Component) 1690 return; 1691 1692 /* If the current mode is fine don't change it */ 1693 if (!tv_mode->component_only) 1694 return; 1695 1696 for (i = 0; i < ARRAY_SIZE(tv_modes); i++) { 1697 tv_mode = &tv_modes[i]; 1698 1699 if (!tv_mode->component_only) 1700 break; 1701 } 1702 1703 connector->state->tv.legacy_mode = i; 1704 } 1705 1706 static int 1707 intel_tv_detect(struct drm_connector *connector, 1708 struct drm_modeset_acquire_ctx *ctx, 1709 bool force) 1710 { 1711 struct intel_display *display = to_intel_display(connector->dev); 1712 struct intel_tv *intel_tv = intel_attached_tv(to_intel_connector(connector)); 1713 enum drm_connector_status status; 1714 int type; 1715 1716 drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s] force=%d\n", 1717 connector->base.id, connector->name, force); 1718 1719 if (!intel_display_device_enabled(display)) 1720 return connector_status_disconnected; 1721 1722 if (!intel_display_driver_check_access(display)) 1723 return connector->status; 1724 1725 if (force) { 1726 struct drm_atomic_commit *state; 1727 1728 state = intel_load_detect_get_pipe(connector, ctx); 1729 if (IS_ERR(state)) 1730 return PTR_ERR(state); 1731 1732 if (state) { 1733 type = intel_tv_detect_type(intel_tv, connector); 1734 intel_load_detect_release_pipe(connector, state, ctx); 1735 status = type < 0 ? 1736 connector_status_disconnected : 1737 connector_status_connected; 1738 } else { 1739 status = connector_status_unknown; 1740 } 1741 1742 if (status == connector_status_connected) { 1743 intel_tv->type = type; 1744 intel_tv_find_better_format(connector); 1745 } 1746 1747 return status; 1748 } else 1749 return connector->status; 1750 } 1751 1752 static const struct input_res { 1753 u16 w, h; 1754 } input_res_table[] = { 1755 { 640, 480 }, 1756 { 800, 600 }, 1757 { 1024, 768 }, 1758 { 1280, 1024 }, 1759 { 848, 480 }, 1760 { 1280, 720 }, 1761 { 1920, 1080 }, 1762 }; 1763 1764 /* Choose preferred mode according to line number of TV format */ 1765 static bool 1766 intel_tv_is_preferred_mode(const struct drm_display_mode *mode, 1767 const struct tv_mode *tv_mode) 1768 { 1769 int vdisplay = intel_tv_mode_vdisplay(tv_mode); 1770 1771 /* prefer 480 line modes for all SD TV modes */ 1772 if (vdisplay <= 576) 1773 vdisplay = 480; 1774 1775 return vdisplay == mode->vdisplay; 1776 } 1777 1778 static void 1779 intel_tv_set_mode_type(struct drm_display_mode *mode, 1780 const struct tv_mode *tv_mode) 1781 { 1782 mode->type = DRM_MODE_TYPE_DRIVER; 1783 1784 if (intel_tv_is_preferred_mode(mode, tv_mode)) 1785 mode->type |= DRM_MODE_TYPE_PREFERRED; 1786 } 1787 1788 static int 1789 intel_tv_get_modes(struct drm_connector *connector) 1790 { 1791 struct intel_display *display = to_intel_display(connector->dev); 1792 const struct tv_mode *tv_mode = intel_tv_mode_find(connector->state); 1793 int i, count = 0; 1794 1795 for (i = 0; i < ARRAY_SIZE(input_res_table); i++) { 1796 const struct input_res *input = &input_res_table[i]; 1797 struct drm_display_mode *mode; 1798 1799 if (input->w > 1024 && 1800 !tv_mode->progressive && 1801 !tv_mode->component_only) 1802 continue; 1803 1804 /* no vertical scaling with wide sources on gen3 */ 1805 if (DISPLAY_VER(display) == 3 && input->w > 1024 && 1806 input->h > intel_tv_mode_vdisplay(tv_mode)) 1807 continue; 1808 1809 mode = drm_mode_create(connector->dev); 1810 if (!mode) 1811 continue; 1812 1813 /* 1814 * We take the TV mode and scale it to look 1815 * like it had the expected h/vdisplay. This 1816 * provides the most information to userspace 1817 * about the actual timings of the mode. We 1818 * do ignore the margins though. 1819 */ 1820 intel_tv_mode_to_mode(mode, tv_mode, tv_mode->clock); 1821 if (count == 0) { 1822 drm_dbg_kms(display->drm, 1823 "TV mode: " DRM_MODE_FMT "\n", 1824 DRM_MODE_ARG(mode)); 1825 } 1826 intel_tv_scale_mode_horiz(mode, input->w, 0, 0); 1827 intel_tv_scale_mode_vert(mode, input->h, 0, 0); 1828 intel_tv_set_mode_type(mode, tv_mode); 1829 1830 drm_mode_set_name(mode); 1831 1832 drm_mode_probed_add(connector, mode); 1833 count++; 1834 } 1835 1836 return count; 1837 } 1838 1839 static const struct drm_connector_funcs intel_tv_connector_funcs = { 1840 .late_register = intel_connector_register, 1841 .early_unregister = intel_connector_unregister, 1842 .destroy = intel_connector_destroy, 1843 .fill_modes = drm_helper_probe_single_connector_modes, 1844 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 1845 .atomic_duplicate_state = intel_tv_connector_duplicate_state, 1846 }; 1847 1848 static int intel_tv_atomic_check(struct drm_connector *connector, 1849 struct drm_atomic_commit *state) 1850 { 1851 struct drm_connector_state *new_state; 1852 struct drm_crtc_state *new_crtc_state; 1853 struct drm_connector_state *old_state; 1854 1855 new_state = drm_atomic_get_new_connector_state(state, connector); 1856 if (!new_state->crtc) 1857 return 0; 1858 1859 old_state = drm_atomic_get_old_connector_state(state, connector); 1860 new_crtc_state = drm_atomic_get_new_crtc_state(state, new_state->crtc); 1861 1862 if (old_state->tv.legacy_mode != new_state->tv.legacy_mode || 1863 old_state->tv.margins.left != new_state->tv.margins.left || 1864 old_state->tv.margins.right != new_state->tv.margins.right || 1865 old_state->tv.margins.top != new_state->tv.margins.top || 1866 old_state->tv.margins.bottom != new_state->tv.margins.bottom) { 1867 /* Force a modeset. */ 1868 1869 new_crtc_state->connectors_changed = true; 1870 } 1871 1872 return 0; 1873 } 1874 1875 static const struct drm_connector_helper_funcs intel_tv_connector_helper_funcs = { 1876 .detect_ctx = intel_tv_detect, 1877 .mode_valid = intel_tv_mode_valid, 1878 .get_modes = intel_tv_get_modes, 1879 .atomic_check = intel_tv_atomic_check, 1880 }; 1881 1882 static const struct drm_encoder_funcs intel_tv_enc_funcs = { 1883 .destroy = intel_encoder_destroy, 1884 }; 1885 1886 static void intel_tv_add_properties(struct drm_connector *connector) 1887 { 1888 struct intel_display *display = to_intel_display(connector->dev); 1889 struct drm_connector_state *conn_state = connector->state; 1890 const char *tv_format_names[ARRAY_SIZE(tv_modes)]; 1891 int i; 1892 1893 /* BIOS margin values */ 1894 conn_state->tv.margins.left = 54; 1895 conn_state->tv.margins.top = 36; 1896 conn_state->tv.margins.right = 46; 1897 conn_state->tv.margins.bottom = 37; 1898 1899 conn_state->tv.legacy_mode = 0; 1900 1901 /* Create TV properties then attach current values */ 1902 for (i = 0; i < ARRAY_SIZE(tv_modes); i++) { 1903 /* 1080p50/1080p60 not supported on gen3 */ 1904 if (DISPLAY_VER(display) == 3 && tv_modes[i].oversample == 1) 1905 break; 1906 1907 tv_format_names[i] = tv_modes[i].name; 1908 } 1909 drm_mode_create_tv_properties_legacy(display->drm, i, tv_format_names); 1910 1911 drm_object_attach_property(&connector->base, 1912 display->drm->mode_config.legacy_tv_mode_property, 1913 conn_state->tv.legacy_mode); 1914 drm_object_attach_property(&connector->base, 1915 display->drm->mode_config.tv_left_margin_property, 1916 conn_state->tv.margins.left); 1917 drm_object_attach_property(&connector->base, 1918 display->drm->mode_config.tv_top_margin_property, 1919 conn_state->tv.margins.top); 1920 drm_object_attach_property(&connector->base, 1921 display->drm->mode_config.tv_right_margin_property, 1922 conn_state->tv.margins.right); 1923 drm_object_attach_property(&connector->base, 1924 display->drm->mode_config.tv_bottom_margin_property, 1925 conn_state->tv.margins.bottom); 1926 } 1927 1928 void 1929 intel_tv_init(struct intel_display *display) 1930 { 1931 struct drm_connector *connector; 1932 struct intel_tv *intel_tv; 1933 struct intel_encoder *intel_encoder; 1934 struct intel_connector *intel_connector; 1935 u32 tv_dac_on, tv_dac_off, save_tv_dac; 1936 1937 if ((intel_de_read(display, TV_CTL) & TV_FUSE_STATE_MASK) == TV_FUSE_STATE_DISABLED) 1938 return; 1939 1940 if (!intel_bios_is_tv_present(display)) { 1941 drm_dbg_kms(display->drm, "Integrated TV is not present.\n"); 1942 return; 1943 } 1944 1945 /* 1946 * Sanity check the TV output by checking to see if the 1947 * DAC register holds a value 1948 */ 1949 save_tv_dac = intel_de_read(display, TV_DAC); 1950 1951 intel_de_write(display, TV_DAC, save_tv_dac | TVDAC_STATE_CHG_EN); 1952 tv_dac_on = intel_de_read(display, TV_DAC); 1953 1954 intel_de_write(display, TV_DAC, save_tv_dac & ~TVDAC_STATE_CHG_EN); 1955 tv_dac_off = intel_de_read(display, TV_DAC); 1956 1957 intel_de_write(display, TV_DAC, save_tv_dac); 1958 1959 /* 1960 * If the register does not hold the state change enable 1961 * bit, (either as a 0 or a 1), assume it doesn't really 1962 * exist 1963 */ 1964 if ((tv_dac_on & TVDAC_STATE_CHG_EN) == 0 || 1965 (tv_dac_off & TVDAC_STATE_CHG_EN) != 0) 1966 return; 1967 1968 intel_tv = kzalloc_obj(*intel_tv); 1969 if (!intel_tv) { 1970 return; 1971 } 1972 1973 intel_connector = intel_connector_alloc(); 1974 if (!intel_connector) { 1975 kfree(intel_tv); 1976 return; 1977 } 1978 1979 intel_encoder = &intel_tv->base; 1980 connector = &intel_connector->base; 1981 1982 /* 1983 * The documentation, for the older chipsets at least, recommend 1984 * using a polling method rather than hotplug detection for TVs. 1985 * This is because in order to perform the hotplug detection, the PLLs 1986 * for the TV must be kept alive increasing power drain and starving 1987 * bandwidth from other encoders. Notably for instance, it causes 1988 * pipe underruns on Crestline when this encoder is supposedly idle. 1989 * 1990 * More recent chipsets favour HDMI rather than integrated S-Video. 1991 */ 1992 intel_connector->polled = DRM_CONNECTOR_POLL_CONNECT; 1993 intel_connector->base.polled = intel_connector->polled; 1994 1995 drm_connector_init(display->drm, connector, &intel_tv_connector_funcs, 1996 DRM_MODE_CONNECTOR_SVIDEO); 1997 1998 drm_encoder_init(display->drm, &intel_encoder->base, 1999 &intel_tv_enc_funcs, 2000 DRM_MODE_ENCODER_TVDAC, "TV"); 2001 2002 intel_encoder->compute_config = intel_tv_compute_config; 2003 intel_encoder->get_config = intel_tv_get_config; 2004 intel_encoder->pre_enable = intel_tv_pre_enable; 2005 intel_encoder->enable = intel_enable_tv; 2006 intel_encoder->disable = intel_disable_tv; 2007 intel_encoder->get_hw_state = intel_tv_get_hw_state; 2008 intel_connector->get_hw_state = intel_connector_get_hw_state; 2009 2010 intel_connector_attach_encoder(intel_connector, intel_encoder); 2011 2012 intel_encoder->type = INTEL_OUTPUT_TVOUT; 2013 intel_encoder->power_domain = POWER_DOMAIN_PORT_OTHER; 2014 intel_encoder->port = PORT_NONE; 2015 intel_encoder->pipe_mask = ~0; 2016 intel_encoder->cloneable = 0; 2017 intel_tv->type = DRM_MODE_CONNECTOR_Unknown; 2018 2019 drm_connector_helper_add(connector, &intel_tv_connector_helper_funcs); 2020 2021 intel_tv_add_properties(connector); 2022 } 2023