1 /* 2 * Copyright © 2006-2008 Intel Corporation 3 * Jesse Barnes <jesse.barnes@intel.com> 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 22 * DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: 25 * Eric Anholt <eric@anholt.net> 26 * 27 */ 28 29 /** @file 30 * Integrated TV-out support for the 915GM and 945GM. 31 */ 32 33 #include <drm/drm_atomic_helper.h> 34 #include <drm/drm_crtc.h> 35 #include <drm/drm_edid.h> 36 #include <drm/i915_drm.h> 37 38 #include "i915_drv.h" 39 #include "intel_connector.h" 40 #include "intel_display_types.h" 41 #include "intel_hotplug.h" 42 #include "intel_tv.h" 43 44 enum tv_margin { 45 TV_MARGIN_LEFT, TV_MARGIN_TOP, 46 TV_MARGIN_RIGHT, TV_MARGIN_BOTTOM 47 }; 48 49 struct intel_tv { 50 struct intel_encoder base; 51 52 int type; 53 }; 54 55 struct video_levels { 56 u16 blank, black; 57 u8 burst; 58 }; 59 60 struct color_conversion { 61 u16 ry, gy, by, ay; 62 u16 ru, gu, bu, au; 63 u16 rv, gv, bv, av; 64 }; 65 66 static const u32 filter_table[] = { 67 0xB1403000, 0x2E203500, 0x35002E20, 0x3000B140, 68 0x35A0B160, 0x2DC02E80, 0xB1403480, 0xB1603000, 69 0x2EA03640, 0x34002D80, 0x3000B120, 0x36E0B160, 70 0x2D202EF0, 0xB1203380, 0xB1603000, 0x2F303780, 71 0x33002CC0, 0x3000B100, 0x3820B160, 0x2C802F50, 72 0xB10032A0, 0xB1603000, 0x2F9038C0, 0x32202C20, 73 0x3000B0E0, 0x3980B160, 0x2BC02FC0, 0xB0E031C0, 74 0xB1603000, 0x2FF03A20, 0x31602B60, 0xB020B0C0, 75 0x3AE0B160, 0x2B001810, 0xB0C03120, 0xB140B020, 76 0x18283BA0, 0x30C02A80, 0xB020B0A0, 0x3C60B140, 77 0x2A201838, 0xB0A03080, 0xB120B020, 0x18383D20, 78 0x304029C0, 0xB040B080, 0x3DE0B100, 0x29601848, 79 0xB0803000, 0xB100B040, 0x18483EC0, 0xB0402900, 80 0xB040B060, 0x3F80B0C0, 0x28801858, 0xB060B080, 81 0xB0A0B060, 0x18602820, 0xB0A02820, 0x0000B060, 82 0xB1403000, 0x2E203500, 0x35002E20, 0x3000B140, 83 0x35A0B160, 0x2DC02E80, 0xB1403480, 0xB1603000, 84 0x2EA03640, 0x34002D80, 0x3000B120, 0x36E0B160, 85 0x2D202EF0, 0xB1203380, 0xB1603000, 0x2F303780, 86 0x33002CC0, 0x3000B100, 0x3820B160, 0x2C802F50, 87 0xB10032A0, 0xB1603000, 0x2F9038C0, 0x32202C20, 88 0x3000B0E0, 0x3980B160, 0x2BC02FC0, 0xB0E031C0, 89 0xB1603000, 0x2FF03A20, 0x31602B60, 0xB020B0C0, 90 0x3AE0B160, 0x2B001810, 0xB0C03120, 0xB140B020, 91 0x18283BA0, 0x30C02A80, 0xB020B0A0, 0x3C60B140, 92 0x2A201838, 0xB0A03080, 0xB120B020, 0x18383D20, 93 0x304029C0, 0xB040B080, 0x3DE0B100, 0x29601848, 94 0xB0803000, 0xB100B040, 0x18483EC0, 0xB0402900, 95 0xB040B060, 0x3F80B0C0, 0x28801858, 0xB060B080, 96 0xB0A0B060, 0x18602820, 0xB0A02820, 0x0000B060, 97 0x36403000, 0x2D002CC0, 0x30003640, 0x2D0036C0, 98 0x35C02CC0, 0x37403000, 0x2C802D40, 0x30003540, 99 0x2D8037C0, 0x34C02C40, 0x38403000, 0x2BC02E00, 100 0x30003440, 0x2E2038C0, 0x34002B80, 0x39803000, 101 0x2B402E40, 0x30003380, 0x2E603A00, 0x33402B00, 102 0x3A803040, 0x2A802EA0, 0x30403300, 0x2EC03B40, 103 0x32802A40, 0x3C003040, 0x2A002EC0, 0x30803240, 104 0x2EC03C80, 0x320029C0, 0x3D403080, 0x29402F00, 105 0x308031C0, 0x2F203DC0, 0x31802900, 0x3E8030C0, 106 0x28802F40, 0x30C03140, 0x2F203F40, 0x31402840, 107 0x28003100, 0x28002F00, 0x00003100, 0x36403000, 108 0x2D002CC0, 0x30003640, 0x2D0036C0, 109 0x35C02CC0, 0x37403000, 0x2C802D40, 0x30003540, 110 0x2D8037C0, 0x34C02C40, 0x38403000, 0x2BC02E00, 111 0x30003440, 0x2E2038C0, 0x34002B80, 0x39803000, 112 0x2B402E40, 0x30003380, 0x2E603A00, 0x33402B00, 113 0x3A803040, 0x2A802EA0, 0x30403300, 0x2EC03B40, 114 0x32802A40, 0x3C003040, 0x2A002EC0, 0x30803240, 115 0x2EC03C80, 0x320029C0, 0x3D403080, 0x29402F00, 116 0x308031C0, 0x2F203DC0, 0x31802900, 0x3E8030C0, 117 0x28802F40, 0x30C03140, 0x2F203F40, 0x31402840, 118 0x28003100, 0x28002F00, 0x00003100, 119 }; 120 121 /* 122 * Color conversion values have 3 separate fixed point formats: 123 * 124 * 10 bit fields (ay, au) 125 * 1.9 fixed point (b.bbbbbbbbb) 126 * 11 bit fields (ry, by, ru, gu, gv) 127 * exp.mantissa (ee.mmmmmmmmm) 128 * ee = 00 = 10^-1 (0.mmmmmmmmm) 129 * ee = 01 = 10^-2 (0.0mmmmmmmmm) 130 * ee = 10 = 10^-3 (0.00mmmmmmmmm) 131 * ee = 11 = 10^-4 (0.000mmmmmmmmm) 132 * 12 bit fields (gy, rv, bu) 133 * exp.mantissa (eee.mmmmmmmmm) 134 * eee = 000 = 10^-1 (0.mmmmmmmmm) 135 * eee = 001 = 10^-2 (0.0mmmmmmmmm) 136 * eee = 010 = 10^-3 (0.00mmmmmmmmm) 137 * eee = 011 = 10^-4 (0.000mmmmmmmmm) 138 * eee = 100 = reserved 139 * eee = 101 = reserved 140 * eee = 110 = reserved 141 * eee = 111 = 10^0 (m.mmmmmmmm) (only usable for 1.0 representation) 142 * 143 * Saturation and contrast are 8 bits, with their own representation: 144 * 8 bit field (saturation, contrast) 145 * exp.mantissa (ee.mmmmmm) 146 * ee = 00 = 10^-1 (0.mmmmmm) 147 * ee = 01 = 10^0 (m.mmmmm) 148 * ee = 10 = 10^1 (mm.mmmm) 149 * ee = 11 = 10^2 (mmm.mmm) 150 * 151 * Simple conversion function: 152 * 153 * static u32 154 * float_to_csc_11(float f) 155 * { 156 * u32 exp; 157 * u32 mant; 158 * u32 ret; 159 * 160 * if (f < 0) 161 * f = -f; 162 * 163 * if (f >= 1) { 164 * exp = 0x7; 165 * mant = 1 << 8; 166 * } else { 167 * for (exp = 0; exp < 3 && f < 0.5; exp++) 168 * f *= 2.0; 169 * mant = (f * (1 << 9) + 0.5); 170 * if (mant >= (1 << 9)) 171 * mant = (1 << 9) - 1; 172 * } 173 * ret = (exp << 9) | mant; 174 * return ret; 175 * } 176 */ 177 178 /* 179 * Behold, magic numbers! If we plant them they might grow a big 180 * s-video cable to the sky... or something. 181 * 182 * Pre-converted to appropriate hex value. 183 */ 184 185 /* 186 * PAL & NTSC values for composite & s-video connections 187 */ 188 static const struct color_conversion ntsc_m_csc_composite = { 189 .ry = 0x0332, .gy = 0x012d, .by = 0x07d3, .ay = 0x0104, 190 .ru = 0x0733, .gu = 0x052d, .bu = 0x05c7, .au = 0x0200, 191 .rv = 0x0340, .gv = 0x030c, .bv = 0x06d0, .av = 0x0200, 192 }; 193 194 static const struct video_levels ntsc_m_levels_composite = { 195 .blank = 225, .black = 267, .burst = 113, 196 }; 197 198 static const struct color_conversion ntsc_m_csc_svideo = { 199 .ry = 0x0332, .gy = 0x012d, .by = 0x07d3, .ay = 0x0133, 200 .ru = 0x076a, .gu = 0x0564, .bu = 0x030d, .au = 0x0200, 201 .rv = 0x037a, .gv = 0x033d, .bv = 0x06f6, .av = 0x0200, 202 }; 203 204 static const struct video_levels ntsc_m_levels_svideo = { 205 .blank = 266, .black = 316, .burst = 133, 206 }; 207 208 static const struct color_conversion ntsc_j_csc_composite = { 209 .ry = 0x0332, .gy = 0x012d, .by = 0x07d3, .ay = 0x0119, 210 .ru = 0x074c, .gu = 0x0546, .bu = 0x05ec, .au = 0x0200, 211 .rv = 0x035a, .gv = 0x0322, .bv = 0x06e1, .av = 0x0200, 212 }; 213 214 static const struct video_levels ntsc_j_levels_composite = { 215 .blank = 225, .black = 225, .burst = 113, 216 }; 217 218 static const struct color_conversion ntsc_j_csc_svideo = { 219 .ry = 0x0332, .gy = 0x012d, .by = 0x07d3, .ay = 0x014c, 220 .ru = 0x0788, .gu = 0x0581, .bu = 0x0322, .au = 0x0200, 221 .rv = 0x0399, .gv = 0x0356, .bv = 0x070a, .av = 0x0200, 222 }; 223 224 static const struct video_levels ntsc_j_levels_svideo = { 225 .blank = 266, .black = 266, .burst = 133, 226 }; 227 228 static const struct color_conversion pal_csc_composite = { 229 .ry = 0x0332, .gy = 0x012d, .by = 0x07d3, .ay = 0x0113, 230 .ru = 0x0745, .gu = 0x053f, .bu = 0x05e1, .au = 0x0200, 231 .rv = 0x0353, .gv = 0x031c, .bv = 0x06dc, .av = 0x0200, 232 }; 233 234 static const struct video_levels pal_levels_composite = { 235 .blank = 237, .black = 237, .burst = 118, 236 }; 237 238 static const struct color_conversion pal_csc_svideo = { 239 .ry = 0x0332, .gy = 0x012d, .by = 0x07d3, .ay = 0x0145, 240 .ru = 0x0780, .gu = 0x0579, .bu = 0x031c, .au = 0x0200, 241 .rv = 0x0390, .gv = 0x034f, .bv = 0x0705, .av = 0x0200, 242 }; 243 244 static const struct video_levels pal_levels_svideo = { 245 .blank = 280, .black = 280, .burst = 139, 246 }; 247 248 static const struct color_conversion pal_m_csc_composite = { 249 .ry = 0x0332, .gy = 0x012d, .by = 0x07d3, .ay = 0x0104, 250 .ru = 0x0733, .gu = 0x052d, .bu = 0x05c7, .au = 0x0200, 251 .rv = 0x0340, .gv = 0x030c, .bv = 0x06d0, .av = 0x0200, 252 }; 253 254 static const struct video_levels pal_m_levels_composite = { 255 .blank = 225, .black = 267, .burst = 113, 256 }; 257 258 static const struct color_conversion pal_m_csc_svideo = { 259 .ry = 0x0332, .gy = 0x012d, .by = 0x07d3, .ay = 0x0133, 260 .ru = 0x076a, .gu = 0x0564, .bu = 0x030d, .au = 0x0200, 261 .rv = 0x037a, .gv = 0x033d, .bv = 0x06f6, .av = 0x0200, 262 }; 263 264 static const struct video_levels pal_m_levels_svideo = { 265 .blank = 266, .black = 316, .burst = 133, 266 }; 267 268 static const struct color_conversion pal_n_csc_composite = { 269 .ry = 0x0332, .gy = 0x012d, .by = 0x07d3, .ay = 0x0104, 270 .ru = 0x0733, .gu = 0x052d, .bu = 0x05c7, .au = 0x0200, 271 .rv = 0x0340, .gv = 0x030c, .bv = 0x06d0, .av = 0x0200, 272 }; 273 274 static const struct video_levels pal_n_levels_composite = { 275 .blank = 225, .black = 267, .burst = 118, 276 }; 277 278 static const struct color_conversion pal_n_csc_svideo = { 279 .ry = 0x0332, .gy = 0x012d, .by = 0x07d3, .ay = 0x0133, 280 .ru = 0x076a, .gu = 0x0564, .bu = 0x030d, .au = 0x0200, 281 .rv = 0x037a, .gv = 0x033d, .bv = 0x06f6, .av = 0x0200, 282 }; 283 284 static const struct video_levels pal_n_levels_svideo = { 285 .blank = 266, .black = 316, .burst = 139, 286 }; 287 288 /* 289 * Component connections 290 */ 291 static const struct color_conversion sdtv_csc_yprpb = { 292 .ry = 0x0332, .gy = 0x012d, .by = 0x07d3, .ay = 0x0145, 293 .ru = 0x0559, .gu = 0x0353, .bu = 0x0100, .au = 0x0200, 294 .rv = 0x0100, .gv = 0x03ad, .bv = 0x074d, .av = 0x0200, 295 }; 296 297 static const struct color_conversion hdtv_csc_yprpb = { 298 .ry = 0x05b3, .gy = 0x016e, .by = 0x0728, .ay = 0x0145, 299 .ru = 0x07d5, .gu = 0x038b, .bu = 0x0100, .au = 0x0200, 300 .rv = 0x0100, .gv = 0x03d1, .bv = 0x06bc, .av = 0x0200, 301 }; 302 303 static const struct video_levels component_levels = { 304 .blank = 279, .black = 279, .burst = 0, 305 }; 306 307 308 struct tv_mode { 309 const char *name; 310 311 u32 clock; 312 u16 refresh; /* in millihertz (for precision) */ 313 u8 oversample; 314 u8 hsync_end; 315 u16 hblank_start, hblank_end, htotal; 316 bool progressive : 1, trilevel_sync : 1, component_only : 1; 317 u8 vsync_start_f1, vsync_start_f2, vsync_len; 318 bool veq_ena : 1; 319 u8 veq_start_f1, veq_start_f2, veq_len; 320 u8 vi_end_f1, vi_end_f2; 321 u16 nbr_end; 322 bool burst_ena : 1; 323 u8 hburst_start, hburst_len; 324 u8 vburst_start_f1; 325 u16 vburst_end_f1; 326 u8 vburst_start_f2; 327 u16 vburst_end_f2; 328 u8 vburst_start_f3; 329 u16 vburst_end_f3; 330 u8 vburst_start_f4; 331 u16 vburst_end_f4; 332 /* 333 * subcarrier programming 334 */ 335 u16 dda2_size, dda3_size; 336 u8 dda1_inc; 337 u16 dda2_inc, dda3_inc; 338 u32 sc_reset; 339 bool pal_burst : 1; 340 /* 341 * blank/black levels 342 */ 343 const struct video_levels *composite_levels, *svideo_levels; 344 const struct color_conversion *composite_color, *svideo_color; 345 const u32 *filter_table; 346 }; 347 348 349 /* 350 * Sub carrier DDA 351 * 352 * I think this works as follows: 353 * 354 * subcarrier freq = pixel_clock * (dda1_inc + dda2_inc / dda2_size) / 4096 355 * 356 * Presumably, when dda3 is added in, it gets to adjust the dda2_inc value 357 * 358 * So, 359 * dda1_ideal = subcarrier/pixel * 4096 360 * dda1_inc = floor (dda1_ideal) 361 * dda2 = dda1_ideal - dda1_inc 362 * 363 * then pick a ratio for dda2 that gives the closest approximation. If 364 * you can't get close enough, you can play with dda3 as well. This 365 * seems likely to happen when dda2 is small as the jumps would be larger 366 * 367 * To invert this, 368 * 369 * pixel_clock = subcarrier * 4096 / (dda1_inc + dda2_inc / dda2_size) 370 * 371 * The constants below were all computed using a 107.520MHz clock 372 */ 373 374 /* 375 * Register programming values for TV modes. 376 * 377 * These values account for -1s required. 378 */ 379 static const struct tv_mode tv_modes[] = { 380 { 381 .name = "NTSC-M", 382 .clock = 108000, 383 .refresh = 59940, 384 .oversample = 8, 385 .component_only = false, 386 /* 525 Lines, 60 Fields, 15.734KHz line, Sub-Carrier 3.580MHz */ 387 388 .hsync_end = 64, .hblank_end = 124, 389 .hblank_start = 836, .htotal = 857, 390 391 .progressive = false, .trilevel_sync = false, 392 393 .vsync_start_f1 = 6, .vsync_start_f2 = 7, 394 .vsync_len = 6, 395 396 .veq_ena = true, .veq_start_f1 = 0, 397 .veq_start_f2 = 1, .veq_len = 18, 398 399 .vi_end_f1 = 20, .vi_end_f2 = 21, 400 .nbr_end = 240, 401 402 .burst_ena = true, 403 .hburst_start = 72, .hburst_len = 34, 404 .vburst_start_f1 = 9, .vburst_end_f1 = 240, 405 .vburst_start_f2 = 10, .vburst_end_f2 = 240, 406 .vburst_start_f3 = 9, .vburst_end_f3 = 240, 407 .vburst_start_f4 = 10, .vburst_end_f4 = 240, 408 409 /* desired 3.5800000 actual 3.5800000 clock 107.52 */ 410 .dda1_inc = 135, 411 .dda2_inc = 20800, .dda2_size = 27456, 412 .dda3_inc = 0, .dda3_size = 0, 413 .sc_reset = TV_SC_RESET_EVERY_4, 414 .pal_burst = false, 415 416 .composite_levels = &ntsc_m_levels_composite, 417 .composite_color = &ntsc_m_csc_composite, 418 .svideo_levels = &ntsc_m_levels_svideo, 419 .svideo_color = &ntsc_m_csc_svideo, 420 421 .filter_table = filter_table, 422 }, 423 { 424 .name = "NTSC-443", 425 .clock = 108000, 426 .refresh = 59940, 427 .oversample = 8, 428 .component_only = false, 429 /* 525 Lines, 60 Fields, 15.734KHz line, Sub-Carrier 4.43MHz */ 430 .hsync_end = 64, .hblank_end = 124, 431 .hblank_start = 836, .htotal = 857, 432 433 .progressive = false, .trilevel_sync = false, 434 435 .vsync_start_f1 = 6, .vsync_start_f2 = 7, 436 .vsync_len = 6, 437 438 .veq_ena = true, .veq_start_f1 = 0, 439 .veq_start_f2 = 1, .veq_len = 18, 440 441 .vi_end_f1 = 20, .vi_end_f2 = 21, 442 .nbr_end = 240, 443 444 .burst_ena = true, 445 .hburst_start = 72, .hburst_len = 34, 446 .vburst_start_f1 = 9, .vburst_end_f1 = 240, 447 .vburst_start_f2 = 10, .vburst_end_f2 = 240, 448 .vburst_start_f3 = 9, .vburst_end_f3 = 240, 449 .vburst_start_f4 = 10, .vburst_end_f4 = 240, 450 451 /* desired 4.4336180 actual 4.4336180 clock 107.52 */ 452 .dda1_inc = 168, 453 .dda2_inc = 4093, .dda2_size = 27456, 454 .dda3_inc = 310, .dda3_size = 525, 455 .sc_reset = TV_SC_RESET_NEVER, 456 .pal_burst = false, 457 458 .composite_levels = &ntsc_m_levels_composite, 459 .composite_color = &ntsc_m_csc_composite, 460 .svideo_levels = &ntsc_m_levels_svideo, 461 .svideo_color = &ntsc_m_csc_svideo, 462 463 .filter_table = filter_table, 464 }, 465 { 466 .name = "NTSC-J", 467 .clock = 108000, 468 .refresh = 59940, 469 .oversample = 8, 470 .component_only = false, 471 472 /* 525 Lines, 60 Fields, 15.734KHz line, Sub-Carrier 3.580MHz */ 473 .hsync_end = 64, .hblank_end = 124, 474 .hblank_start = 836, .htotal = 857, 475 476 .progressive = false, .trilevel_sync = false, 477 478 .vsync_start_f1 = 6, .vsync_start_f2 = 7, 479 .vsync_len = 6, 480 481 .veq_ena = true, .veq_start_f1 = 0, 482 .veq_start_f2 = 1, .veq_len = 18, 483 484 .vi_end_f1 = 20, .vi_end_f2 = 21, 485 .nbr_end = 240, 486 487 .burst_ena = true, 488 .hburst_start = 72, .hburst_len = 34, 489 .vburst_start_f1 = 9, .vburst_end_f1 = 240, 490 .vburst_start_f2 = 10, .vburst_end_f2 = 240, 491 .vburst_start_f3 = 9, .vburst_end_f3 = 240, 492 .vburst_start_f4 = 10, .vburst_end_f4 = 240, 493 494 /* desired 3.5800000 actual 3.5800000 clock 107.52 */ 495 .dda1_inc = 135, 496 .dda2_inc = 20800, .dda2_size = 27456, 497 .dda3_inc = 0, .dda3_size = 0, 498 .sc_reset = TV_SC_RESET_EVERY_4, 499 .pal_burst = false, 500 501 .composite_levels = &ntsc_j_levels_composite, 502 .composite_color = &ntsc_j_csc_composite, 503 .svideo_levels = &ntsc_j_levels_svideo, 504 .svideo_color = &ntsc_j_csc_svideo, 505 506 .filter_table = filter_table, 507 }, 508 { 509 .name = "PAL-M", 510 .clock = 108000, 511 .refresh = 59940, 512 .oversample = 8, 513 .component_only = false, 514 515 /* 525 Lines, 60 Fields, 15.734KHz line, Sub-Carrier 3.580MHz */ 516 .hsync_end = 64, .hblank_end = 124, 517 .hblank_start = 836, .htotal = 857, 518 519 .progressive = false, .trilevel_sync = false, 520 521 .vsync_start_f1 = 6, .vsync_start_f2 = 7, 522 .vsync_len = 6, 523 524 .veq_ena = true, .veq_start_f1 = 0, 525 .veq_start_f2 = 1, .veq_len = 18, 526 527 .vi_end_f1 = 20, .vi_end_f2 = 21, 528 .nbr_end = 240, 529 530 .burst_ena = true, 531 .hburst_start = 72, .hburst_len = 34, 532 .vburst_start_f1 = 9, .vburst_end_f1 = 240, 533 .vburst_start_f2 = 10, .vburst_end_f2 = 240, 534 .vburst_start_f3 = 9, .vburst_end_f3 = 240, 535 .vburst_start_f4 = 10, .vburst_end_f4 = 240, 536 537 /* desired 3.5800000 actual 3.5800000 clock 107.52 */ 538 .dda1_inc = 135, 539 .dda2_inc = 16704, .dda2_size = 27456, 540 .dda3_inc = 0, .dda3_size = 0, 541 .sc_reset = TV_SC_RESET_EVERY_8, 542 .pal_burst = true, 543 544 .composite_levels = &pal_m_levels_composite, 545 .composite_color = &pal_m_csc_composite, 546 .svideo_levels = &pal_m_levels_svideo, 547 .svideo_color = &pal_m_csc_svideo, 548 549 .filter_table = filter_table, 550 }, 551 { 552 /* 625 Lines, 50 Fields, 15.625KHz line, Sub-Carrier 4.434MHz */ 553 .name = "PAL-N", 554 .clock = 108000, 555 .refresh = 50000, 556 .oversample = 8, 557 .component_only = false, 558 559 .hsync_end = 64, .hblank_end = 128, 560 .hblank_start = 844, .htotal = 863, 561 562 .progressive = false, .trilevel_sync = false, 563 564 565 .vsync_start_f1 = 6, .vsync_start_f2 = 7, 566 .vsync_len = 6, 567 568 .veq_ena = true, .veq_start_f1 = 0, 569 .veq_start_f2 = 1, .veq_len = 18, 570 571 .vi_end_f1 = 24, .vi_end_f2 = 25, 572 .nbr_end = 286, 573 574 .burst_ena = true, 575 .hburst_start = 73, .hburst_len = 34, 576 .vburst_start_f1 = 8, .vburst_end_f1 = 285, 577 .vburst_start_f2 = 8, .vburst_end_f2 = 286, 578 .vburst_start_f3 = 9, .vburst_end_f3 = 286, 579 .vburst_start_f4 = 9, .vburst_end_f4 = 285, 580 581 582 /* desired 4.4336180 actual 4.4336180 clock 107.52 */ 583 .dda1_inc = 135, 584 .dda2_inc = 23578, .dda2_size = 27648, 585 .dda3_inc = 134, .dda3_size = 625, 586 .sc_reset = TV_SC_RESET_EVERY_8, 587 .pal_burst = true, 588 589 .composite_levels = &pal_n_levels_composite, 590 .composite_color = &pal_n_csc_composite, 591 .svideo_levels = &pal_n_levels_svideo, 592 .svideo_color = &pal_n_csc_svideo, 593 594 .filter_table = filter_table, 595 }, 596 { 597 /* 625 Lines, 50 Fields, 15.625KHz line, Sub-Carrier 4.434MHz */ 598 .name = "PAL", 599 .clock = 108000, 600 .refresh = 50000, 601 .oversample = 8, 602 .component_only = false, 603 604 .hsync_end = 64, .hblank_end = 142, 605 .hblank_start = 844, .htotal = 863, 606 607 .progressive = false, .trilevel_sync = false, 608 609 .vsync_start_f1 = 5, .vsync_start_f2 = 6, 610 .vsync_len = 5, 611 612 .veq_ena = true, .veq_start_f1 = 0, 613 .veq_start_f2 = 1, .veq_len = 15, 614 615 .vi_end_f1 = 24, .vi_end_f2 = 25, 616 .nbr_end = 286, 617 618 .burst_ena = true, 619 .hburst_start = 73, .hburst_len = 32, 620 .vburst_start_f1 = 8, .vburst_end_f1 = 285, 621 .vburst_start_f2 = 8, .vburst_end_f2 = 286, 622 .vburst_start_f3 = 9, .vburst_end_f3 = 286, 623 .vburst_start_f4 = 9, .vburst_end_f4 = 285, 624 625 /* desired 4.4336180 actual 4.4336180 clock 107.52 */ 626 .dda1_inc = 168, 627 .dda2_inc = 4122, .dda2_size = 27648, 628 .dda3_inc = 67, .dda3_size = 625, 629 .sc_reset = TV_SC_RESET_EVERY_8, 630 .pal_burst = true, 631 632 .composite_levels = &pal_levels_composite, 633 .composite_color = &pal_csc_composite, 634 .svideo_levels = &pal_levels_svideo, 635 .svideo_color = &pal_csc_svideo, 636 637 .filter_table = filter_table, 638 }, 639 { 640 .name = "480p", 641 .clock = 108000, 642 .refresh = 59940, 643 .oversample = 4, 644 .component_only = true, 645 646 .hsync_end = 64, .hblank_end = 122, 647 .hblank_start = 842, .htotal = 857, 648 649 .progressive = true, .trilevel_sync = false, 650 651 .vsync_start_f1 = 12, .vsync_start_f2 = 12, 652 .vsync_len = 12, 653 654 .veq_ena = false, 655 656 .vi_end_f1 = 44, .vi_end_f2 = 44, 657 .nbr_end = 479, 658 659 .burst_ena = false, 660 661 .filter_table = filter_table, 662 }, 663 { 664 .name = "576p", 665 .clock = 108000, 666 .refresh = 50000, 667 .oversample = 4, 668 .component_only = true, 669 670 .hsync_end = 64, .hblank_end = 139, 671 .hblank_start = 859, .htotal = 863, 672 673 .progressive = true, .trilevel_sync = false, 674 675 .vsync_start_f1 = 10, .vsync_start_f2 = 10, 676 .vsync_len = 10, 677 678 .veq_ena = false, 679 680 .vi_end_f1 = 48, .vi_end_f2 = 48, 681 .nbr_end = 575, 682 683 .burst_ena = false, 684 685 .filter_table = filter_table, 686 }, 687 { 688 .name = "720p@60Hz", 689 .clock = 148500, 690 .refresh = 60000, 691 .oversample = 2, 692 .component_only = true, 693 694 .hsync_end = 80, .hblank_end = 300, 695 .hblank_start = 1580, .htotal = 1649, 696 697 .progressive = true, .trilevel_sync = true, 698 699 .vsync_start_f1 = 10, .vsync_start_f2 = 10, 700 .vsync_len = 10, 701 702 .veq_ena = false, 703 704 .vi_end_f1 = 29, .vi_end_f2 = 29, 705 .nbr_end = 719, 706 707 .burst_ena = false, 708 709 .filter_table = filter_table, 710 }, 711 { 712 .name = "720p@50Hz", 713 .clock = 148500, 714 .refresh = 50000, 715 .oversample = 2, 716 .component_only = true, 717 718 .hsync_end = 80, .hblank_end = 300, 719 .hblank_start = 1580, .htotal = 1979, 720 721 .progressive = true, .trilevel_sync = true, 722 723 .vsync_start_f1 = 10, .vsync_start_f2 = 10, 724 .vsync_len = 10, 725 726 .veq_ena = false, 727 728 .vi_end_f1 = 29, .vi_end_f2 = 29, 729 .nbr_end = 719, 730 731 .burst_ena = false, 732 733 .filter_table = filter_table, 734 }, 735 { 736 .name = "1080i@50Hz", 737 .clock = 148500, 738 .refresh = 50000, 739 .oversample = 2, 740 .component_only = true, 741 742 .hsync_end = 88, .hblank_end = 235, 743 .hblank_start = 2155, .htotal = 2639, 744 745 .progressive = false, .trilevel_sync = true, 746 747 .vsync_start_f1 = 4, .vsync_start_f2 = 5, 748 .vsync_len = 10, 749 750 .veq_ena = true, .veq_start_f1 = 4, 751 .veq_start_f2 = 4, .veq_len = 10, 752 753 754 .vi_end_f1 = 21, .vi_end_f2 = 22, 755 .nbr_end = 539, 756 757 .burst_ena = false, 758 759 .filter_table = filter_table, 760 }, 761 { 762 .name = "1080i@60Hz", 763 .clock = 148500, 764 .refresh = 60000, 765 .oversample = 2, 766 .component_only = true, 767 768 .hsync_end = 88, .hblank_end = 235, 769 .hblank_start = 2155, .htotal = 2199, 770 771 .progressive = false, .trilevel_sync = true, 772 773 .vsync_start_f1 = 4, .vsync_start_f2 = 5, 774 .vsync_len = 10, 775 776 .veq_ena = true, .veq_start_f1 = 4, 777 .veq_start_f2 = 4, .veq_len = 10, 778 779 780 .vi_end_f1 = 21, .vi_end_f2 = 22, 781 .nbr_end = 539, 782 783 .burst_ena = false, 784 785 .filter_table = filter_table, 786 }, 787 788 { 789 .name = "1080p@30Hz", 790 .clock = 148500, 791 .refresh = 30000, 792 .oversample = 2, 793 .component_only = true, 794 795 .hsync_end = 88, .hblank_end = 235, 796 .hblank_start = 2155, .htotal = 2199, 797 798 .progressive = true, .trilevel_sync = true, 799 800 .vsync_start_f1 = 8, .vsync_start_f2 = 8, 801 .vsync_len = 10, 802 803 .veq_ena = false, .veq_start_f1 = 0, 804 .veq_start_f2 = 0, .veq_len = 0, 805 806 .vi_end_f1 = 44, .vi_end_f2 = 44, 807 .nbr_end = 1079, 808 809 .burst_ena = false, 810 811 .filter_table = filter_table, 812 }, 813 814 { 815 .name = "1080p@50Hz", 816 .clock = 148500, 817 .refresh = 50000, 818 .oversample = 1, 819 .component_only = true, 820 821 .hsync_end = 88, .hblank_end = 235, 822 .hblank_start = 2155, .htotal = 2639, 823 824 .progressive = true, .trilevel_sync = true, 825 826 .vsync_start_f1 = 8, .vsync_start_f2 = 8, 827 .vsync_len = 10, 828 829 .veq_ena = false, .veq_start_f1 = 0, 830 .veq_start_f2 = 0, .veq_len = 0, 831 832 .vi_end_f1 = 44, .vi_end_f2 = 44, 833 .nbr_end = 1079, 834 835 .burst_ena = false, 836 837 .filter_table = filter_table, 838 }, 839 840 { 841 .name = "1080p@60Hz", 842 .clock = 148500, 843 .refresh = 60000, 844 .oversample = 1, 845 .component_only = true, 846 847 .hsync_end = 88, .hblank_end = 235, 848 .hblank_start = 2155, .htotal = 2199, 849 850 .progressive = true, .trilevel_sync = true, 851 852 .vsync_start_f1 = 8, .vsync_start_f2 = 8, 853 .vsync_len = 10, 854 855 .veq_ena = false, .veq_start_f1 = 0, 856 .veq_start_f2 = 0, .veq_len = 0, 857 858 .vi_end_f1 = 44, .vi_end_f2 = 44, 859 .nbr_end = 1079, 860 861 .burst_ena = false, 862 863 .filter_table = filter_table, 864 }, 865 }; 866 867 struct intel_tv_connector_state { 868 struct drm_connector_state base; 869 870 /* 871 * May need to override the user margins for 872 * gen3 >1024 wide source vertical centering. 873 */ 874 struct { 875 u16 top, bottom; 876 } margins; 877 878 bool bypass_vfilter; 879 }; 880 881 #define to_intel_tv_connector_state(x) container_of(x, struct intel_tv_connector_state, base) 882 883 static struct drm_connector_state * 884 intel_tv_connector_duplicate_state(struct drm_connector *connector) 885 { 886 struct intel_tv_connector_state *state; 887 888 state = kmemdup(connector->state, sizeof(*state), GFP_KERNEL); 889 if (!state) 890 return NULL; 891 892 __drm_atomic_helper_connector_duplicate_state(connector, &state->base); 893 return &state->base; 894 } 895 896 static struct intel_tv *enc_to_tv(struct intel_encoder *encoder) 897 { 898 return container_of(encoder, struct intel_tv, base); 899 } 900 901 static struct intel_tv *intel_attached_tv(struct intel_connector *connector) 902 { 903 return enc_to_tv(intel_attached_encoder(connector)); 904 } 905 906 static bool 907 intel_tv_get_hw_state(struct intel_encoder *encoder, enum pipe *pipe) 908 { 909 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 910 u32 tmp = intel_de_read(dev_priv, TV_CTL); 911 912 *pipe = (tmp & TV_ENC_PIPE_SEL_MASK) >> TV_ENC_PIPE_SEL_SHIFT; 913 914 return tmp & TV_ENC_ENABLE; 915 } 916 917 static void 918 intel_enable_tv(struct intel_encoder *encoder, 919 const struct intel_crtc_state *pipe_config, 920 const struct drm_connector_state *conn_state) 921 { 922 struct drm_device *dev = encoder->base.dev; 923 struct drm_i915_private *dev_priv = to_i915(dev); 924 925 /* Prevents vblank waits from timing out in intel_tv_detect_type() */ 926 intel_wait_for_vblank(dev_priv, 927 to_intel_crtc(pipe_config->uapi.crtc)->pipe); 928 929 intel_de_write(dev_priv, TV_CTL, 930 intel_de_read(dev_priv, TV_CTL) | TV_ENC_ENABLE); 931 } 932 933 static void 934 intel_disable_tv(struct intel_encoder *encoder, 935 const struct intel_crtc_state *old_crtc_state, 936 const struct drm_connector_state *old_conn_state) 937 { 938 struct drm_device *dev = encoder->base.dev; 939 struct drm_i915_private *dev_priv = to_i915(dev); 940 941 intel_de_write(dev_priv, TV_CTL, 942 intel_de_read(dev_priv, TV_CTL) & ~TV_ENC_ENABLE); 943 } 944 945 static const struct tv_mode *intel_tv_mode_find(const struct drm_connector_state *conn_state) 946 { 947 int format = conn_state->tv.mode; 948 949 return &tv_modes[format]; 950 } 951 952 static enum drm_mode_status 953 intel_tv_mode_valid(struct drm_connector *connector, 954 struct drm_display_mode *mode) 955 { 956 const struct tv_mode *tv_mode = intel_tv_mode_find(connector->state); 957 int max_dotclk = to_i915(connector->dev)->max_dotclk_freq; 958 959 if (mode->flags & DRM_MODE_FLAG_DBLSCAN) 960 return MODE_NO_DBLESCAN; 961 962 if (mode->clock > max_dotclk) 963 return MODE_CLOCK_HIGH; 964 965 /* Ensure TV refresh is close to desired refresh */ 966 if (abs(tv_mode->refresh - drm_mode_vrefresh(mode) * 1000) >= 1000) 967 return MODE_CLOCK_RANGE; 968 969 return MODE_OK; 970 } 971 972 static int 973 intel_tv_mode_vdisplay(const struct tv_mode *tv_mode) 974 { 975 if (tv_mode->progressive) 976 return tv_mode->nbr_end + 1; 977 else 978 return 2 * (tv_mode->nbr_end + 1); 979 } 980 981 static void 982 intel_tv_mode_to_mode(struct drm_display_mode *mode, 983 const struct tv_mode *tv_mode) 984 { 985 mode->clock = tv_mode->clock / 986 (tv_mode->oversample >> !tv_mode->progressive); 987 988 /* 989 * tv_mode horizontal timings: 990 * 991 * hsync_end 992 * | hblank_end 993 * | | hblank_start 994 * | | | htotal 995 * | _______ | 996 * ____/ \___ 997 * \__/ \ 998 */ 999 mode->hdisplay = 1000 tv_mode->hblank_start - tv_mode->hblank_end; 1001 mode->hsync_start = mode->hdisplay + 1002 tv_mode->htotal - tv_mode->hblank_start; 1003 mode->hsync_end = mode->hsync_start + 1004 tv_mode->hsync_end; 1005 mode->htotal = tv_mode->htotal + 1; 1006 1007 /* 1008 * tv_mode vertical timings: 1009 * 1010 * vsync_start 1011 * | vsync_end 1012 * | | vi_end nbr_end 1013 * | | | | 1014 * | | _______ 1015 * \__ ____/ \ 1016 * \__/ 1017 */ 1018 mode->vdisplay = intel_tv_mode_vdisplay(tv_mode); 1019 if (tv_mode->progressive) { 1020 mode->vsync_start = mode->vdisplay + 1021 tv_mode->vsync_start_f1 + 1; 1022 mode->vsync_end = mode->vsync_start + 1023 tv_mode->vsync_len; 1024 mode->vtotal = mode->vdisplay + 1025 tv_mode->vi_end_f1 + 1; 1026 } else { 1027 mode->vsync_start = mode->vdisplay + 1028 tv_mode->vsync_start_f1 + 1 + 1029 tv_mode->vsync_start_f2 + 1; 1030 mode->vsync_end = mode->vsync_start + 1031 2 * tv_mode->vsync_len; 1032 mode->vtotal = mode->vdisplay + 1033 tv_mode->vi_end_f1 + 1 + 1034 tv_mode->vi_end_f2 + 1; 1035 } 1036 1037 /* TV has it's own notion of sync and other mode flags, so clear them. */ 1038 mode->flags = 0; 1039 1040 mode->vrefresh = 0; 1041 mode->vrefresh = drm_mode_vrefresh(mode); 1042 1043 snprintf(mode->name, sizeof(mode->name), 1044 "%dx%d%c (%s)", 1045 mode->hdisplay, mode->vdisplay, 1046 tv_mode->progressive ? 'p' : 'i', 1047 tv_mode->name); 1048 } 1049 1050 static void intel_tv_scale_mode_horiz(struct drm_display_mode *mode, 1051 int hdisplay, int left_margin, 1052 int right_margin) 1053 { 1054 int hsync_start = mode->hsync_start - mode->hdisplay + right_margin; 1055 int hsync_end = mode->hsync_end - mode->hdisplay + right_margin; 1056 int new_htotal = mode->htotal * hdisplay / 1057 (mode->hdisplay - left_margin - right_margin); 1058 1059 mode->clock = mode->clock * new_htotal / mode->htotal; 1060 1061 mode->hdisplay = hdisplay; 1062 mode->hsync_start = hdisplay + hsync_start * new_htotal / mode->htotal; 1063 mode->hsync_end = hdisplay + hsync_end * new_htotal / mode->htotal; 1064 mode->htotal = new_htotal; 1065 } 1066 1067 static void intel_tv_scale_mode_vert(struct drm_display_mode *mode, 1068 int vdisplay, int top_margin, 1069 int bottom_margin) 1070 { 1071 int vsync_start = mode->vsync_start - mode->vdisplay + bottom_margin; 1072 int vsync_end = mode->vsync_end - mode->vdisplay + bottom_margin; 1073 int new_vtotal = mode->vtotal * vdisplay / 1074 (mode->vdisplay - top_margin - bottom_margin); 1075 1076 mode->clock = mode->clock * new_vtotal / mode->vtotal; 1077 1078 mode->vdisplay = vdisplay; 1079 mode->vsync_start = vdisplay + vsync_start * new_vtotal / mode->vtotal; 1080 mode->vsync_end = vdisplay + vsync_end * new_vtotal / mode->vtotal; 1081 mode->vtotal = new_vtotal; 1082 } 1083 1084 static void 1085 intel_tv_get_config(struct intel_encoder *encoder, 1086 struct intel_crtc_state *pipe_config) 1087 { 1088 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1089 struct drm_display_mode *adjusted_mode = 1090 &pipe_config->hw.adjusted_mode; 1091 struct drm_display_mode mode = {}; 1092 u32 tv_ctl, hctl1, hctl3, vctl1, vctl2, tmp; 1093 struct tv_mode tv_mode = {}; 1094 int hdisplay = adjusted_mode->crtc_hdisplay; 1095 int vdisplay = adjusted_mode->crtc_vdisplay; 1096 int xsize, ysize, xpos, ypos; 1097 1098 pipe_config->output_types |= BIT(INTEL_OUTPUT_TVOUT); 1099 1100 tv_ctl = intel_de_read(dev_priv, TV_CTL); 1101 hctl1 = intel_de_read(dev_priv, TV_H_CTL_1); 1102 hctl3 = intel_de_read(dev_priv, TV_H_CTL_3); 1103 vctl1 = intel_de_read(dev_priv, TV_V_CTL_1); 1104 vctl2 = intel_de_read(dev_priv, TV_V_CTL_2); 1105 1106 tv_mode.htotal = (hctl1 & TV_HTOTAL_MASK) >> TV_HTOTAL_SHIFT; 1107 tv_mode.hsync_end = (hctl1 & TV_HSYNC_END_MASK) >> TV_HSYNC_END_SHIFT; 1108 1109 tv_mode.hblank_start = (hctl3 & TV_HBLANK_START_MASK) >> TV_HBLANK_START_SHIFT; 1110 tv_mode.hblank_end = (hctl3 & TV_HSYNC_END_MASK) >> TV_HBLANK_END_SHIFT; 1111 1112 tv_mode.nbr_end = (vctl1 & TV_NBR_END_MASK) >> TV_NBR_END_SHIFT; 1113 tv_mode.vi_end_f1 = (vctl1 & TV_VI_END_F1_MASK) >> TV_VI_END_F1_SHIFT; 1114 tv_mode.vi_end_f2 = (vctl1 & TV_VI_END_F2_MASK) >> TV_VI_END_F2_SHIFT; 1115 1116 tv_mode.vsync_len = (vctl2 & TV_VSYNC_LEN_MASK) >> TV_VSYNC_LEN_SHIFT; 1117 tv_mode.vsync_start_f1 = (vctl2 & TV_VSYNC_START_F1_MASK) >> TV_VSYNC_START_F1_SHIFT; 1118 tv_mode.vsync_start_f2 = (vctl2 & TV_VSYNC_START_F2_MASK) >> TV_VSYNC_START_F2_SHIFT; 1119 1120 tv_mode.clock = pipe_config->port_clock; 1121 1122 tv_mode.progressive = tv_ctl & TV_PROGRESSIVE; 1123 1124 switch (tv_ctl & TV_OVERSAMPLE_MASK) { 1125 case TV_OVERSAMPLE_8X: 1126 tv_mode.oversample = 8; 1127 break; 1128 case TV_OVERSAMPLE_4X: 1129 tv_mode.oversample = 4; 1130 break; 1131 case TV_OVERSAMPLE_2X: 1132 tv_mode.oversample = 2; 1133 break; 1134 default: 1135 tv_mode.oversample = 1; 1136 break; 1137 } 1138 1139 tmp = intel_de_read(dev_priv, TV_WIN_POS); 1140 xpos = tmp >> 16; 1141 ypos = tmp & 0xffff; 1142 1143 tmp = intel_de_read(dev_priv, TV_WIN_SIZE); 1144 xsize = tmp >> 16; 1145 ysize = tmp & 0xffff; 1146 1147 intel_tv_mode_to_mode(&mode, &tv_mode); 1148 1149 drm_dbg_kms(&dev_priv->drm, "TV mode:\n"); 1150 drm_mode_debug_printmodeline(&mode); 1151 1152 intel_tv_scale_mode_horiz(&mode, hdisplay, 1153 xpos, mode.hdisplay - xsize - xpos); 1154 intel_tv_scale_mode_vert(&mode, vdisplay, 1155 ypos, mode.vdisplay - ysize - ypos); 1156 1157 adjusted_mode->crtc_clock = mode.clock; 1158 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) 1159 adjusted_mode->crtc_clock /= 2; 1160 1161 /* pixel counter doesn't work on i965gm TV output */ 1162 if (IS_I965GM(dev_priv)) 1163 adjusted_mode->private_flags |= 1164 I915_MODE_FLAG_USE_SCANLINE_COUNTER; 1165 } 1166 1167 static bool intel_tv_source_too_wide(struct drm_i915_private *dev_priv, 1168 int hdisplay) 1169 { 1170 return IS_GEN(dev_priv, 3) && hdisplay > 1024; 1171 } 1172 1173 static bool intel_tv_vert_scaling(const struct drm_display_mode *tv_mode, 1174 const struct drm_connector_state *conn_state, 1175 int vdisplay) 1176 { 1177 return tv_mode->crtc_vdisplay - 1178 conn_state->tv.margins.top - 1179 conn_state->tv.margins.bottom != 1180 vdisplay; 1181 } 1182 1183 static int 1184 intel_tv_compute_config(struct intel_encoder *encoder, 1185 struct intel_crtc_state *pipe_config, 1186 struct drm_connector_state *conn_state) 1187 { 1188 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1189 struct intel_tv_connector_state *tv_conn_state = 1190 to_intel_tv_connector_state(conn_state); 1191 const struct tv_mode *tv_mode = intel_tv_mode_find(conn_state); 1192 struct drm_display_mode *adjusted_mode = 1193 &pipe_config->hw.adjusted_mode; 1194 int hdisplay = adjusted_mode->crtc_hdisplay; 1195 int vdisplay = adjusted_mode->crtc_vdisplay; 1196 1197 if (!tv_mode) 1198 return -EINVAL; 1199 1200 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN) 1201 return -EINVAL; 1202 1203 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; 1204 1205 drm_dbg_kms(&dev_priv->drm, "forcing bpc to 8 for TV\n"); 1206 pipe_config->pipe_bpp = 8*3; 1207 1208 pipe_config->port_clock = tv_mode->clock; 1209 1210 intel_tv_mode_to_mode(adjusted_mode, tv_mode); 1211 drm_mode_set_crtcinfo(adjusted_mode, 0); 1212 1213 if (intel_tv_source_too_wide(dev_priv, hdisplay) || 1214 !intel_tv_vert_scaling(adjusted_mode, conn_state, vdisplay)) { 1215 int extra, top, bottom; 1216 1217 extra = adjusted_mode->crtc_vdisplay - vdisplay; 1218 1219 if (extra < 0) { 1220 drm_dbg_kms(&dev_priv->drm, 1221 "No vertical scaling for >1024 pixel wide modes\n"); 1222 return -EINVAL; 1223 } 1224 1225 /* Need to turn off the vertical filter and center the image */ 1226 1227 /* Attempt to maintain the relative sizes of the margins */ 1228 top = conn_state->tv.margins.top; 1229 bottom = conn_state->tv.margins.bottom; 1230 1231 if (top + bottom) 1232 top = extra * top / (top + bottom); 1233 else 1234 top = extra / 2; 1235 bottom = extra - top; 1236 1237 tv_conn_state->margins.top = top; 1238 tv_conn_state->margins.bottom = bottom; 1239 1240 tv_conn_state->bypass_vfilter = true; 1241 1242 if (!tv_mode->progressive) { 1243 adjusted_mode->clock /= 2; 1244 adjusted_mode->crtc_clock /= 2; 1245 adjusted_mode->flags |= DRM_MODE_FLAG_INTERLACE; 1246 } 1247 } else { 1248 tv_conn_state->margins.top = conn_state->tv.margins.top; 1249 tv_conn_state->margins.bottom = conn_state->tv.margins.bottom; 1250 1251 tv_conn_state->bypass_vfilter = false; 1252 } 1253 1254 drm_dbg_kms(&dev_priv->drm, "TV mode:\n"); 1255 drm_mode_debug_printmodeline(adjusted_mode); 1256 1257 /* 1258 * The pipe scanline counter behaviour looks as follows when 1259 * using the TV encoder: 1260 * 1261 * time -> 1262 * 1263 * dsl=vtotal-1 | | 1264 * || || 1265 * ___| | ___| | 1266 * / | / | 1267 * / | / | 1268 * dsl=0 ___/ |_____/ | 1269 * | | | | | | 1270 * ^ ^ ^ ^ ^ 1271 * | | | | pipe vblank/first part of tv vblank 1272 * | | | bottom margin 1273 * | | active 1274 * | top margin 1275 * remainder of tv vblank 1276 * 1277 * When the TV encoder is used the pipe wants to run faster 1278 * than expected rate. During the active portion the TV 1279 * encoder stalls the pipe every few lines to keep it in 1280 * check. When the TV encoder reaches the bottom margin the 1281 * pipe simply stops. Once we reach the TV vblank the pipe is 1282 * no longer stalled and it runs at the max rate (apparently 1283 * oversample clock on gen3, cdclk on gen4). Once the pipe 1284 * reaches the pipe vtotal the pipe stops for the remainder 1285 * of the TV vblank/top margin. The pipe starts up again when 1286 * the TV encoder exits the top margin. 1287 * 1288 * To avoid huge hassles for vblank timestamping we scale 1289 * the pipe timings as if the pipe always runs at the average 1290 * rate it maintains during the active period. This also 1291 * gives us a reasonable guesstimate as to the pixel rate. 1292 * Due to the variation in the actual pipe speed the scanline 1293 * counter will give us slightly erroneous results during the 1294 * TV vblank/margins. But since vtotal was selected such that 1295 * it matches the average rate of the pipe during the active 1296 * portion the error shouldn't cause any serious grief to 1297 * vblank timestamps. 1298 * 1299 * For posterity here is the empirically derived formula 1300 * that gives us the maximum length of the pipe vblank 1301 * we can use without causing display corruption. Following 1302 * this would allow us to have a ticking scanline counter 1303 * everywhere except during the bottom margin (there the 1304 * pipe always stops). Ie. this would eliminate the second 1305 * flat portion of the above graph. However this would also 1306 * complicate vblank timestamping as the pipe vtotal would 1307 * no longer match the average rate the pipe runs at during 1308 * the active portion. Hence following this formula seems 1309 * more trouble that it's worth. 1310 * 1311 * if (IS_GEN(dev_priv, 4)) { 1312 * num = cdclk * (tv_mode->oversample >> !tv_mode->progressive); 1313 * den = tv_mode->clock; 1314 * } else { 1315 * num = tv_mode->oversample >> !tv_mode->progressive; 1316 * den = 1; 1317 * } 1318 * max_pipe_vblank_len ~= 1319 * (num * tv_htotal * (tv_vblank_len + top_margin)) / 1320 * (den * pipe_htotal); 1321 */ 1322 intel_tv_scale_mode_horiz(adjusted_mode, hdisplay, 1323 conn_state->tv.margins.left, 1324 conn_state->tv.margins.right); 1325 intel_tv_scale_mode_vert(adjusted_mode, vdisplay, 1326 tv_conn_state->margins.top, 1327 tv_conn_state->margins.bottom); 1328 drm_mode_set_crtcinfo(adjusted_mode, 0); 1329 adjusted_mode->name[0] = '\0'; 1330 1331 /* pixel counter doesn't work on i965gm TV output */ 1332 if (IS_I965GM(dev_priv)) 1333 adjusted_mode->private_flags |= 1334 I915_MODE_FLAG_USE_SCANLINE_COUNTER; 1335 1336 return 0; 1337 } 1338 1339 static void 1340 set_tv_mode_timings(struct drm_i915_private *dev_priv, 1341 const struct tv_mode *tv_mode, 1342 bool burst_ena) 1343 { 1344 u32 hctl1, hctl2, hctl3; 1345 u32 vctl1, vctl2, vctl3, vctl4, vctl5, vctl6, vctl7; 1346 1347 hctl1 = (tv_mode->hsync_end << TV_HSYNC_END_SHIFT) | 1348 (tv_mode->htotal << TV_HTOTAL_SHIFT); 1349 1350 hctl2 = (tv_mode->hburst_start << 16) | 1351 (tv_mode->hburst_len << TV_HBURST_LEN_SHIFT); 1352 1353 if (burst_ena) 1354 hctl2 |= TV_BURST_ENA; 1355 1356 hctl3 = (tv_mode->hblank_start << TV_HBLANK_START_SHIFT) | 1357 (tv_mode->hblank_end << TV_HBLANK_END_SHIFT); 1358 1359 vctl1 = (tv_mode->nbr_end << TV_NBR_END_SHIFT) | 1360 (tv_mode->vi_end_f1 << TV_VI_END_F1_SHIFT) | 1361 (tv_mode->vi_end_f2 << TV_VI_END_F2_SHIFT); 1362 1363 vctl2 = (tv_mode->vsync_len << TV_VSYNC_LEN_SHIFT) | 1364 (tv_mode->vsync_start_f1 << TV_VSYNC_START_F1_SHIFT) | 1365 (tv_mode->vsync_start_f2 << TV_VSYNC_START_F2_SHIFT); 1366 1367 vctl3 = (tv_mode->veq_len << TV_VEQ_LEN_SHIFT) | 1368 (tv_mode->veq_start_f1 << TV_VEQ_START_F1_SHIFT) | 1369 (tv_mode->veq_start_f2 << TV_VEQ_START_F2_SHIFT); 1370 1371 if (tv_mode->veq_ena) 1372 vctl3 |= TV_EQUAL_ENA; 1373 1374 vctl4 = (tv_mode->vburst_start_f1 << TV_VBURST_START_F1_SHIFT) | 1375 (tv_mode->vburst_end_f1 << TV_VBURST_END_F1_SHIFT); 1376 1377 vctl5 = (tv_mode->vburst_start_f2 << TV_VBURST_START_F2_SHIFT) | 1378 (tv_mode->vburst_end_f2 << TV_VBURST_END_F2_SHIFT); 1379 1380 vctl6 = (tv_mode->vburst_start_f3 << TV_VBURST_START_F3_SHIFT) | 1381 (tv_mode->vburst_end_f3 << TV_VBURST_END_F3_SHIFT); 1382 1383 vctl7 = (tv_mode->vburst_start_f4 << TV_VBURST_START_F4_SHIFT) | 1384 (tv_mode->vburst_end_f4 << TV_VBURST_END_F4_SHIFT); 1385 1386 intel_de_write(dev_priv, TV_H_CTL_1, hctl1); 1387 intel_de_write(dev_priv, TV_H_CTL_2, hctl2); 1388 intel_de_write(dev_priv, TV_H_CTL_3, hctl3); 1389 intel_de_write(dev_priv, TV_V_CTL_1, vctl1); 1390 intel_de_write(dev_priv, TV_V_CTL_2, vctl2); 1391 intel_de_write(dev_priv, TV_V_CTL_3, vctl3); 1392 intel_de_write(dev_priv, TV_V_CTL_4, vctl4); 1393 intel_de_write(dev_priv, TV_V_CTL_5, vctl5); 1394 intel_de_write(dev_priv, TV_V_CTL_6, vctl6); 1395 intel_de_write(dev_priv, TV_V_CTL_7, vctl7); 1396 } 1397 1398 static void set_color_conversion(struct drm_i915_private *dev_priv, 1399 const struct color_conversion *color_conversion) 1400 { 1401 if (!color_conversion) 1402 return; 1403 1404 intel_de_write(dev_priv, TV_CSC_Y, 1405 (color_conversion->ry << 16) | color_conversion->gy); 1406 intel_de_write(dev_priv, TV_CSC_Y2, 1407 (color_conversion->by << 16) | color_conversion->ay); 1408 intel_de_write(dev_priv, TV_CSC_U, 1409 (color_conversion->ru << 16) | color_conversion->gu); 1410 intel_de_write(dev_priv, TV_CSC_U2, 1411 (color_conversion->bu << 16) | color_conversion->au); 1412 intel_de_write(dev_priv, TV_CSC_V, 1413 (color_conversion->rv << 16) | color_conversion->gv); 1414 intel_de_write(dev_priv, TV_CSC_V2, 1415 (color_conversion->bv << 16) | color_conversion->av); 1416 } 1417 1418 static void intel_tv_pre_enable(struct intel_encoder *encoder, 1419 const struct intel_crtc_state *pipe_config, 1420 const struct drm_connector_state *conn_state) 1421 { 1422 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1423 struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->uapi.crtc); 1424 struct intel_tv *intel_tv = enc_to_tv(encoder); 1425 const struct intel_tv_connector_state *tv_conn_state = 1426 to_intel_tv_connector_state(conn_state); 1427 const struct tv_mode *tv_mode = intel_tv_mode_find(conn_state); 1428 u32 tv_ctl, tv_filter_ctl; 1429 u32 scctl1, scctl2, scctl3; 1430 int i, j; 1431 const struct video_levels *video_levels; 1432 const struct color_conversion *color_conversion; 1433 bool burst_ena; 1434 int xpos, ypos; 1435 unsigned int xsize, ysize; 1436 1437 if (!tv_mode) 1438 return; /* can't happen (mode_prepare prevents this) */ 1439 1440 tv_ctl = intel_de_read(dev_priv, TV_CTL); 1441 tv_ctl &= TV_CTL_SAVE; 1442 1443 switch (intel_tv->type) { 1444 default: 1445 case DRM_MODE_CONNECTOR_Unknown: 1446 case DRM_MODE_CONNECTOR_Composite: 1447 tv_ctl |= TV_ENC_OUTPUT_COMPOSITE; 1448 video_levels = tv_mode->composite_levels; 1449 color_conversion = tv_mode->composite_color; 1450 burst_ena = tv_mode->burst_ena; 1451 break; 1452 case DRM_MODE_CONNECTOR_Component: 1453 tv_ctl |= TV_ENC_OUTPUT_COMPONENT; 1454 video_levels = &component_levels; 1455 if (tv_mode->burst_ena) 1456 color_conversion = &sdtv_csc_yprpb; 1457 else 1458 color_conversion = &hdtv_csc_yprpb; 1459 burst_ena = false; 1460 break; 1461 case DRM_MODE_CONNECTOR_SVIDEO: 1462 tv_ctl |= TV_ENC_OUTPUT_SVIDEO; 1463 video_levels = tv_mode->svideo_levels; 1464 color_conversion = tv_mode->svideo_color; 1465 burst_ena = tv_mode->burst_ena; 1466 break; 1467 } 1468 1469 tv_ctl |= TV_ENC_PIPE_SEL(intel_crtc->pipe); 1470 1471 switch (tv_mode->oversample) { 1472 case 8: 1473 tv_ctl |= TV_OVERSAMPLE_8X; 1474 break; 1475 case 4: 1476 tv_ctl |= TV_OVERSAMPLE_4X; 1477 break; 1478 case 2: 1479 tv_ctl |= TV_OVERSAMPLE_2X; 1480 break; 1481 default: 1482 tv_ctl |= TV_OVERSAMPLE_NONE; 1483 break; 1484 } 1485 1486 if (tv_mode->progressive) 1487 tv_ctl |= TV_PROGRESSIVE; 1488 if (tv_mode->trilevel_sync) 1489 tv_ctl |= TV_TRILEVEL_SYNC; 1490 if (tv_mode->pal_burst) 1491 tv_ctl |= TV_PAL_BURST; 1492 1493 scctl1 = 0; 1494 if (tv_mode->dda1_inc) 1495 scctl1 |= TV_SC_DDA1_EN; 1496 if (tv_mode->dda2_inc) 1497 scctl1 |= TV_SC_DDA2_EN; 1498 if (tv_mode->dda3_inc) 1499 scctl1 |= TV_SC_DDA3_EN; 1500 scctl1 |= tv_mode->sc_reset; 1501 if (video_levels) 1502 scctl1 |= video_levels->burst << TV_BURST_LEVEL_SHIFT; 1503 scctl1 |= tv_mode->dda1_inc << TV_SCDDA1_INC_SHIFT; 1504 1505 scctl2 = tv_mode->dda2_size << TV_SCDDA2_SIZE_SHIFT | 1506 tv_mode->dda2_inc << TV_SCDDA2_INC_SHIFT; 1507 1508 scctl3 = tv_mode->dda3_size << TV_SCDDA3_SIZE_SHIFT | 1509 tv_mode->dda3_inc << TV_SCDDA3_INC_SHIFT; 1510 1511 /* Enable two fixes for the chips that need them. */ 1512 if (IS_I915GM(dev_priv)) 1513 tv_ctl |= TV_ENC_C0_FIX | TV_ENC_SDP_FIX; 1514 1515 set_tv_mode_timings(dev_priv, tv_mode, burst_ena); 1516 1517 intel_de_write(dev_priv, TV_SC_CTL_1, scctl1); 1518 intel_de_write(dev_priv, TV_SC_CTL_2, scctl2); 1519 intel_de_write(dev_priv, TV_SC_CTL_3, scctl3); 1520 1521 set_color_conversion(dev_priv, color_conversion); 1522 1523 if (INTEL_GEN(dev_priv) >= 4) 1524 intel_de_write(dev_priv, TV_CLR_KNOBS, 0x00404000); 1525 else 1526 intel_de_write(dev_priv, TV_CLR_KNOBS, 0x00606000); 1527 1528 if (video_levels) 1529 intel_de_write(dev_priv, TV_CLR_LEVEL, 1530 ((video_levels->black << TV_BLACK_LEVEL_SHIFT) | (video_levels->blank << TV_BLANK_LEVEL_SHIFT))); 1531 1532 assert_pipe_disabled(dev_priv, pipe_config->cpu_transcoder); 1533 1534 /* Filter ctl must be set before TV_WIN_SIZE */ 1535 tv_filter_ctl = TV_AUTO_SCALE; 1536 if (tv_conn_state->bypass_vfilter) 1537 tv_filter_ctl |= TV_V_FILTER_BYPASS; 1538 intel_de_write(dev_priv, TV_FILTER_CTL_1, tv_filter_ctl); 1539 1540 xsize = tv_mode->hblank_start - tv_mode->hblank_end; 1541 ysize = intel_tv_mode_vdisplay(tv_mode); 1542 1543 xpos = conn_state->tv.margins.left; 1544 ypos = tv_conn_state->margins.top; 1545 xsize -= (conn_state->tv.margins.left + 1546 conn_state->tv.margins.right); 1547 ysize -= (tv_conn_state->margins.top + 1548 tv_conn_state->margins.bottom); 1549 intel_de_write(dev_priv, TV_WIN_POS, (xpos << 16) | ypos); 1550 intel_de_write(dev_priv, TV_WIN_SIZE, (xsize << 16) | ysize); 1551 1552 j = 0; 1553 for (i = 0; i < 60; i++) 1554 intel_de_write(dev_priv, TV_H_LUMA(i), 1555 tv_mode->filter_table[j++]); 1556 for (i = 0; i < 60; i++) 1557 intel_de_write(dev_priv, TV_H_CHROMA(i), 1558 tv_mode->filter_table[j++]); 1559 for (i = 0; i < 43; i++) 1560 intel_de_write(dev_priv, TV_V_LUMA(i), 1561 tv_mode->filter_table[j++]); 1562 for (i = 0; i < 43; i++) 1563 intel_de_write(dev_priv, TV_V_CHROMA(i), 1564 tv_mode->filter_table[j++]); 1565 intel_de_write(dev_priv, TV_DAC, 1566 intel_de_read(dev_priv, TV_DAC) & TV_DAC_SAVE); 1567 intel_de_write(dev_priv, TV_CTL, tv_ctl); 1568 } 1569 1570 static int 1571 intel_tv_detect_type(struct intel_tv *intel_tv, 1572 struct drm_connector *connector) 1573 { 1574 struct drm_crtc *crtc = connector->state->crtc; 1575 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 1576 struct drm_device *dev = connector->dev; 1577 struct drm_i915_private *dev_priv = to_i915(dev); 1578 u32 tv_ctl, save_tv_ctl; 1579 u32 tv_dac, save_tv_dac; 1580 int type; 1581 1582 /* Disable TV interrupts around load detect or we'll recurse */ 1583 if (connector->polled & DRM_CONNECTOR_POLL_HPD) { 1584 spin_lock_irq(&dev_priv->irq_lock); 1585 i915_disable_pipestat(dev_priv, 0, 1586 PIPE_HOTPLUG_INTERRUPT_STATUS | 1587 PIPE_HOTPLUG_TV_INTERRUPT_STATUS); 1588 spin_unlock_irq(&dev_priv->irq_lock); 1589 } 1590 1591 save_tv_dac = tv_dac = intel_de_read(dev_priv, TV_DAC); 1592 save_tv_ctl = tv_ctl = intel_de_read(dev_priv, TV_CTL); 1593 1594 /* Poll for TV detection */ 1595 tv_ctl &= ~(TV_ENC_ENABLE | TV_ENC_PIPE_SEL_MASK | TV_TEST_MODE_MASK); 1596 tv_ctl |= TV_TEST_MODE_MONITOR_DETECT; 1597 tv_ctl |= TV_ENC_PIPE_SEL(intel_crtc->pipe); 1598 1599 tv_dac &= ~(TVDAC_SENSE_MASK | DAC_A_MASK | DAC_B_MASK | DAC_C_MASK); 1600 tv_dac |= (TVDAC_STATE_CHG_EN | 1601 TVDAC_A_SENSE_CTL | 1602 TVDAC_B_SENSE_CTL | 1603 TVDAC_C_SENSE_CTL | 1604 DAC_CTL_OVERRIDE | 1605 DAC_A_0_7_V | 1606 DAC_B_0_7_V | 1607 DAC_C_0_7_V); 1608 1609 1610 /* 1611 * The TV sense state should be cleared to zero on cantiga platform. Otherwise 1612 * the TV is misdetected. This is hardware requirement. 1613 */ 1614 if (IS_GM45(dev_priv)) 1615 tv_dac &= ~(TVDAC_STATE_CHG_EN | TVDAC_A_SENSE_CTL | 1616 TVDAC_B_SENSE_CTL | TVDAC_C_SENSE_CTL); 1617 1618 intel_de_write(dev_priv, TV_CTL, tv_ctl); 1619 intel_de_write(dev_priv, TV_DAC, tv_dac); 1620 intel_de_posting_read(dev_priv, TV_DAC); 1621 1622 intel_wait_for_vblank(dev_priv, intel_crtc->pipe); 1623 1624 type = -1; 1625 tv_dac = intel_de_read(dev_priv, TV_DAC); 1626 drm_dbg_kms(&dev_priv->drm, "TV detected: %x, %x\n", tv_ctl, tv_dac); 1627 /* 1628 * A B C 1629 * 0 1 1 Composite 1630 * 1 0 X svideo 1631 * 0 0 0 Component 1632 */ 1633 if ((tv_dac & TVDAC_SENSE_MASK) == (TVDAC_B_SENSE | TVDAC_C_SENSE)) { 1634 drm_dbg_kms(&dev_priv->drm, 1635 "Detected Composite TV connection\n"); 1636 type = DRM_MODE_CONNECTOR_Composite; 1637 } else if ((tv_dac & (TVDAC_A_SENSE|TVDAC_B_SENSE)) == TVDAC_A_SENSE) { 1638 drm_dbg_kms(&dev_priv->drm, 1639 "Detected S-Video TV connection\n"); 1640 type = DRM_MODE_CONNECTOR_SVIDEO; 1641 } else if ((tv_dac & TVDAC_SENSE_MASK) == 0) { 1642 drm_dbg_kms(&dev_priv->drm, 1643 "Detected Component TV connection\n"); 1644 type = DRM_MODE_CONNECTOR_Component; 1645 } else { 1646 drm_dbg_kms(&dev_priv->drm, "Unrecognised TV connection\n"); 1647 type = -1; 1648 } 1649 1650 intel_de_write(dev_priv, TV_DAC, save_tv_dac & ~TVDAC_STATE_CHG_EN); 1651 intel_de_write(dev_priv, TV_CTL, save_tv_ctl); 1652 intel_de_posting_read(dev_priv, TV_CTL); 1653 1654 /* For unknown reasons the hw barfs if we don't do this vblank wait. */ 1655 intel_wait_for_vblank(dev_priv, intel_crtc->pipe); 1656 1657 /* Restore interrupt config */ 1658 if (connector->polled & DRM_CONNECTOR_POLL_HPD) { 1659 spin_lock_irq(&dev_priv->irq_lock); 1660 i915_enable_pipestat(dev_priv, 0, 1661 PIPE_HOTPLUG_INTERRUPT_STATUS | 1662 PIPE_HOTPLUG_TV_INTERRUPT_STATUS); 1663 spin_unlock_irq(&dev_priv->irq_lock); 1664 } 1665 1666 return type; 1667 } 1668 1669 /* 1670 * Here we set accurate tv format according to connector type 1671 * i.e Component TV should not be assigned by NTSC or PAL 1672 */ 1673 static void intel_tv_find_better_format(struct drm_connector *connector) 1674 { 1675 struct intel_tv *intel_tv = intel_attached_tv(to_intel_connector(connector)); 1676 const struct tv_mode *tv_mode = intel_tv_mode_find(connector->state); 1677 int i; 1678 1679 /* Component supports everything so we can keep the current mode */ 1680 if (intel_tv->type == DRM_MODE_CONNECTOR_Component) 1681 return; 1682 1683 /* If the current mode is fine don't change it */ 1684 if (!tv_mode->component_only) 1685 return; 1686 1687 for (i = 0; i < ARRAY_SIZE(tv_modes); i++) { 1688 tv_mode = &tv_modes[i]; 1689 1690 if (!tv_mode->component_only) 1691 break; 1692 } 1693 1694 connector->state->tv.mode = i; 1695 } 1696 1697 static int 1698 intel_tv_detect(struct drm_connector *connector, 1699 struct drm_modeset_acquire_ctx *ctx, 1700 bool force) 1701 { 1702 struct intel_tv *intel_tv = intel_attached_tv(to_intel_connector(connector)); 1703 enum drm_connector_status status; 1704 int type; 1705 1706 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] force=%d\n", 1707 connector->base.id, connector->name, 1708 force); 1709 1710 if (force) { 1711 struct intel_load_detect_pipe tmp; 1712 int ret; 1713 1714 ret = intel_get_load_detect_pipe(connector, &tmp, ctx); 1715 if (ret < 0) 1716 return ret; 1717 1718 if (ret > 0) { 1719 type = intel_tv_detect_type(intel_tv, connector); 1720 intel_release_load_detect_pipe(connector, &tmp, ctx); 1721 status = type < 0 ? 1722 connector_status_disconnected : 1723 connector_status_connected; 1724 } else 1725 status = connector_status_unknown; 1726 1727 if (status == connector_status_connected) { 1728 intel_tv->type = type; 1729 intel_tv_find_better_format(connector); 1730 } 1731 1732 return status; 1733 } else 1734 return connector->status; 1735 } 1736 1737 static const struct input_res { 1738 u16 w, h; 1739 } input_res_table[] = { 1740 { 640, 480 }, 1741 { 800, 600 }, 1742 { 1024, 768 }, 1743 { 1280, 1024 }, 1744 { 848, 480 }, 1745 { 1280, 720 }, 1746 { 1920, 1080 }, 1747 }; 1748 1749 /* Choose preferred mode according to line number of TV format */ 1750 static bool 1751 intel_tv_is_preferred_mode(const struct drm_display_mode *mode, 1752 const struct tv_mode *tv_mode) 1753 { 1754 int vdisplay = intel_tv_mode_vdisplay(tv_mode); 1755 1756 /* prefer 480 line modes for all SD TV modes */ 1757 if (vdisplay <= 576) 1758 vdisplay = 480; 1759 1760 return vdisplay == mode->vdisplay; 1761 } 1762 1763 static void 1764 intel_tv_set_mode_type(struct drm_display_mode *mode, 1765 const struct tv_mode *tv_mode) 1766 { 1767 mode->type = DRM_MODE_TYPE_DRIVER; 1768 1769 if (intel_tv_is_preferred_mode(mode, tv_mode)) 1770 mode->type |= DRM_MODE_TYPE_PREFERRED; 1771 } 1772 1773 static int 1774 intel_tv_get_modes(struct drm_connector *connector) 1775 { 1776 struct drm_i915_private *dev_priv = to_i915(connector->dev); 1777 const struct tv_mode *tv_mode = intel_tv_mode_find(connector->state); 1778 int i, count = 0; 1779 1780 for (i = 0; i < ARRAY_SIZE(input_res_table); i++) { 1781 const struct input_res *input = &input_res_table[i]; 1782 struct drm_display_mode *mode; 1783 1784 if (input->w > 1024 && 1785 !tv_mode->progressive && 1786 !tv_mode->component_only) 1787 continue; 1788 1789 /* no vertical scaling with wide sources on gen3 */ 1790 if (IS_GEN(dev_priv, 3) && input->w > 1024 && 1791 input->h > intel_tv_mode_vdisplay(tv_mode)) 1792 continue; 1793 1794 mode = drm_mode_create(connector->dev); 1795 if (!mode) 1796 continue; 1797 1798 /* 1799 * We take the TV mode and scale it to look 1800 * like it had the expected h/vdisplay. This 1801 * provides the most information to userspace 1802 * about the actual timings of the mode. We 1803 * do ignore the margins though. 1804 */ 1805 intel_tv_mode_to_mode(mode, tv_mode); 1806 if (count == 0) { 1807 drm_dbg_kms(&dev_priv->drm, "TV mode:\n"); 1808 drm_mode_debug_printmodeline(mode); 1809 } 1810 intel_tv_scale_mode_horiz(mode, input->w, 0, 0); 1811 intel_tv_scale_mode_vert(mode, input->h, 0, 0); 1812 intel_tv_set_mode_type(mode, tv_mode); 1813 1814 drm_mode_set_name(mode); 1815 1816 drm_mode_probed_add(connector, mode); 1817 count++; 1818 } 1819 1820 return count; 1821 } 1822 1823 static const struct drm_connector_funcs intel_tv_connector_funcs = { 1824 .late_register = intel_connector_register, 1825 .early_unregister = intel_connector_unregister, 1826 .destroy = intel_connector_destroy, 1827 .fill_modes = drm_helper_probe_single_connector_modes, 1828 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 1829 .atomic_duplicate_state = intel_tv_connector_duplicate_state, 1830 }; 1831 1832 static int intel_tv_atomic_check(struct drm_connector *connector, 1833 struct drm_atomic_state *state) 1834 { 1835 struct drm_connector_state *new_state; 1836 struct drm_crtc_state *new_crtc_state; 1837 struct drm_connector_state *old_state; 1838 1839 new_state = drm_atomic_get_new_connector_state(state, connector); 1840 if (!new_state->crtc) 1841 return 0; 1842 1843 old_state = drm_atomic_get_old_connector_state(state, connector); 1844 new_crtc_state = drm_atomic_get_new_crtc_state(state, new_state->crtc); 1845 1846 if (old_state->tv.mode != new_state->tv.mode || 1847 old_state->tv.margins.left != new_state->tv.margins.left || 1848 old_state->tv.margins.right != new_state->tv.margins.right || 1849 old_state->tv.margins.top != new_state->tv.margins.top || 1850 old_state->tv.margins.bottom != new_state->tv.margins.bottom) { 1851 /* Force a modeset. */ 1852 1853 new_crtc_state->connectors_changed = true; 1854 } 1855 1856 return 0; 1857 } 1858 1859 static const struct drm_connector_helper_funcs intel_tv_connector_helper_funcs = { 1860 .detect_ctx = intel_tv_detect, 1861 .mode_valid = intel_tv_mode_valid, 1862 .get_modes = intel_tv_get_modes, 1863 .atomic_check = intel_tv_atomic_check, 1864 }; 1865 1866 static const struct drm_encoder_funcs intel_tv_enc_funcs = { 1867 .destroy = intel_encoder_destroy, 1868 }; 1869 1870 void 1871 intel_tv_init(struct drm_i915_private *dev_priv) 1872 { 1873 struct drm_device *dev = &dev_priv->drm; 1874 struct drm_connector *connector; 1875 struct intel_tv *intel_tv; 1876 struct intel_encoder *intel_encoder; 1877 struct intel_connector *intel_connector; 1878 u32 tv_dac_on, tv_dac_off, save_tv_dac; 1879 const char *tv_format_names[ARRAY_SIZE(tv_modes)]; 1880 int i, initial_mode = 0; 1881 struct drm_connector_state *state; 1882 1883 if ((intel_de_read(dev_priv, TV_CTL) & TV_FUSE_STATE_MASK) == TV_FUSE_STATE_DISABLED) 1884 return; 1885 1886 if (!intel_bios_is_tv_present(dev_priv)) { 1887 drm_dbg_kms(&dev_priv->drm, "Integrated TV is not present.\n"); 1888 return; 1889 } 1890 1891 /* 1892 * Sanity check the TV output by checking to see if the 1893 * DAC register holds a value 1894 */ 1895 save_tv_dac = intel_de_read(dev_priv, TV_DAC); 1896 1897 intel_de_write(dev_priv, TV_DAC, save_tv_dac | TVDAC_STATE_CHG_EN); 1898 tv_dac_on = intel_de_read(dev_priv, TV_DAC); 1899 1900 intel_de_write(dev_priv, TV_DAC, save_tv_dac & ~TVDAC_STATE_CHG_EN); 1901 tv_dac_off = intel_de_read(dev_priv, TV_DAC); 1902 1903 intel_de_write(dev_priv, TV_DAC, save_tv_dac); 1904 1905 /* 1906 * If the register does not hold the state change enable 1907 * bit, (either as a 0 or a 1), assume it doesn't really 1908 * exist 1909 */ 1910 if ((tv_dac_on & TVDAC_STATE_CHG_EN) == 0 || 1911 (tv_dac_off & TVDAC_STATE_CHG_EN) != 0) 1912 return; 1913 1914 intel_tv = kzalloc(sizeof(*intel_tv), GFP_KERNEL); 1915 if (!intel_tv) { 1916 return; 1917 } 1918 1919 intel_connector = intel_connector_alloc(); 1920 if (!intel_connector) { 1921 kfree(intel_tv); 1922 return; 1923 } 1924 1925 intel_encoder = &intel_tv->base; 1926 connector = &intel_connector->base; 1927 state = connector->state; 1928 1929 /* 1930 * The documentation, for the older chipsets at least, recommend 1931 * using a polling method rather than hotplug detection for TVs. 1932 * This is because in order to perform the hotplug detection, the PLLs 1933 * for the TV must be kept alive increasing power drain and starving 1934 * bandwidth from other encoders. Notably for instance, it causes 1935 * pipe underruns on Crestline when this encoder is supposedly idle. 1936 * 1937 * More recent chipsets favour HDMI rather than integrated S-Video. 1938 */ 1939 intel_connector->polled = DRM_CONNECTOR_POLL_CONNECT; 1940 1941 drm_connector_init(dev, connector, &intel_tv_connector_funcs, 1942 DRM_MODE_CONNECTOR_SVIDEO); 1943 1944 drm_encoder_init(dev, &intel_encoder->base, &intel_tv_enc_funcs, 1945 DRM_MODE_ENCODER_TVDAC, "TV"); 1946 1947 intel_encoder->compute_config = intel_tv_compute_config; 1948 intel_encoder->get_config = intel_tv_get_config; 1949 intel_encoder->pre_enable = intel_tv_pre_enable; 1950 intel_encoder->enable = intel_enable_tv; 1951 intel_encoder->disable = intel_disable_tv; 1952 intel_encoder->get_hw_state = intel_tv_get_hw_state; 1953 intel_connector->get_hw_state = intel_connector_get_hw_state; 1954 1955 intel_connector_attach_encoder(intel_connector, intel_encoder); 1956 1957 intel_encoder->type = INTEL_OUTPUT_TVOUT; 1958 intel_encoder->power_domain = POWER_DOMAIN_PORT_OTHER; 1959 intel_encoder->port = PORT_NONE; 1960 intel_encoder->pipe_mask = ~0; 1961 intel_encoder->cloneable = 0; 1962 intel_tv->type = DRM_MODE_CONNECTOR_Unknown; 1963 1964 /* BIOS margin values */ 1965 state->tv.margins.left = 54; 1966 state->tv.margins.top = 36; 1967 state->tv.margins.right = 46; 1968 state->tv.margins.bottom = 37; 1969 1970 state->tv.mode = initial_mode; 1971 1972 drm_connector_helper_add(connector, &intel_tv_connector_helper_funcs); 1973 connector->interlace_allowed = false; 1974 connector->doublescan_allowed = false; 1975 1976 /* Create TV properties then attach current values */ 1977 for (i = 0; i < ARRAY_SIZE(tv_modes); i++) { 1978 /* 1080p50/1080p60 not supported on gen3 */ 1979 if (IS_GEN(dev_priv, 3) && 1980 tv_modes[i].oversample == 1) 1981 break; 1982 1983 tv_format_names[i] = tv_modes[i].name; 1984 } 1985 drm_mode_create_tv_properties(dev, i, tv_format_names); 1986 1987 drm_object_attach_property(&connector->base, dev->mode_config.tv_mode_property, 1988 state->tv.mode); 1989 drm_object_attach_property(&connector->base, 1990 dev->mode_config.tv_left_margin_property, 1991 state->tv.margins.left); 1992 drm_object_attach_property(&connector->base, 1993 dev->mode_config.tv_top_margin_property, 1994 state->tv.margins.top); 1995 drm_object_attach_property(&connector->base, 1996 dev->mode_config.tv_right_margin_property, 1997 state->tv.margins.right); 1998 drm_object_attach_property(&connector->base, 1999 dev->mode_config.tv_bottom_margin_property, 2000 state->tv.margins.bottom); 2001 } 2002