1 /* SPDX-License-Identifier: MIT */ 2 /* 3 * Copyright © 2019 Intel Corporation 4 */ 5 6 #ifndef __INTEL_TC_H__ 7 #define __INTEL_TC_H__ 8 9 #include <linux/types.h> 10 11 struct drm_printer; 12 struct intel_crtc_state; 13 struct intel_digital_port; 14 struct intel_encoder; 15 16 /* 17 * The following enum values must stay fixed, as they match the corresponding 18 * pin assignment fields in the PORT_TX_DFLEXPA1 and TCSS_DDI_STATUS registers. 19 */ 20 enum intel_tc_pin_assignment { /* Lanes (a) Signal/ Cable Notes */ 21 /* DP USB Rate (b) type */ 22 INTEL_TC_PIN_ASSIGNMENT_NONE = 0, /* 4 - - - (c) */ 23 INTEL_TC_PIN_ASSIGNMENT_A, /* 2/4 0 GEN2 TC->TC (d,e) */ 24 INTEL_TC_PIN_ASSIGNMENT_B, /* 1/2 1 GEN2 TC->TC (d,f,g) */ 25 INTEL_TC_PIN_ASSIGNMENT_C, /* 4 0 DP2 TC->TC (h) */ 26 INTEL_TC_PIN_ASSIGNMENT_D, /* 2 1 DP2 TC->TC (h,g) */ 27 INTEL_TC_PIN_ASSIGNMENT_E, /* 4 0 DP2 TC->DP */ 28 INTEL_TC_PIN_ASSIGNMENT_F, /* 2 1 GEN1/DP1 TC->DP (d,g,i) */ 29 /* 30 * (a) - DP unidirectional lanes, each lane using 1 differential signal 31 * pair. 32 * - USB SuperSpeed bidirectional lane, using 2 differential (TX and 33 * RX) signal pairs. 34 * - USB 2.0 (HighSpeed) unidirectional lane, using 1 differential 35 * signal pair. Not indicated, this lane is always present on pin 36 * assignments A-D and never present on pin assignments E/F. 37 * (b) - GEN1: USB 3.1 GEN1 bit rate (5 Gbps) and signaling. This 38 * is used for transferring only a USB stream. 39 * - GEN2: USB 3.1 GEN2 bit rate (10 Gbps) and signaling. This 40 * allows transferring an HBR3 (8.1 Gbps) DP stream. 41 * - DP1: Display Port signaling defined by the DP v1.3 Standard, 42 * with a maximum bit rate of HBR3. 43 * - DP2: Display Port signaling defined by the DP v2.1 Standard, 44 * with a maximum bit rate defined by the DP Alt Mode 45 * v2.1a Standard depending on the cable type as follows: 46 * - Passive (Full-Featured) USB 3.2 GEN1 47 * TC->TC cables (CC3G1-X) : UHBR10 48 * - Passive (Full-Featured) USB 3.2/4 GEN2 and 49 * Thunderbolt Alt Mode GEN2 50 * TC->TC cables (CC3G2-X) all : UHBR10 51 * DP54 logo : UHBR13.5 52 * - Passive (Full-Featured) USB4 GEN3+ and 53 * Thunderbolt Alt Mode GEN3+ 54 * TC->TC cables (CC4G3-X) all : UHBR13.5 55 * DP80 logo : UHBR20 56 * - Active Re-Timed or 57 * Active Linear Re-driven (LRD) 58 * USB3.2 GEN1/2 and USB4 GEN2+ 59 * TC->TC cables all : HBR3 60 * with DP_BR CTS : UHBR10 61 * DP54 logo : UHBR13.5 62 * DP80 logo : UHBR20 63 * - Passive/Active Re-Timed or 64 * Active Linear Re-driven (LRD) 65 * TC->DP cables with DP_BR CTS/DP8K logo : HBR3 66 * with DP_BR CTS : UHBR10 67 * DP54 logo : UHBR13.5 68 * DP80 logo : UHBR20 69 * (c) Used in TBT-alt/legacy modes and on LNL+ after the sink 70 * disconnected in DP-alt mode. 71 * (d) Only defined by the DP Alt Standard v1.0a, deprecated by v1.0b, 72 * only supported on ICL. 73 * (e) GEN2 passive 1 m cable: 4 DP lanes, GEN2 active cable: 2 DP lanes. 74 * (f) GEN2 passive 1 m cable: 2 DP lanes, GEN2 active cable: 1 DP lane. 75 * (g) These pin assignments are also referred to as (USB/DP) 76 * multifunction or Multifunction Display Port (MFD) modes. 77 * (h) Also used where one end of the cable is a captive connector, 78 * attached to a DP->HDMI/DVI/VGA converter. 79 * (i) The DP end of the cable is a captive connector attached to a 80 * (DP/USB) multifunction dock as defined by the DockPort v1.0a 81 * specification. 82 */ 83 }; 84 85 bool intel_tc_port_in_tbt_alt_mode(struct intel_digital_port *dig_port); 86 bool intel_tc_port_in_dp_alt_mode(struct intel_digital_port *dig_port); 87 bool intel_tc_port_in_legacy_mode(struct intel_digital_port *dig_port); 88 bool intel_tc_port_handles_hpd_glitches(struct intel_digital_port *dig_port); 89 90 bool intel_tc_port_connected(struct intel_encoder *encoder); 91 92 enum intel_tc_pin_assignment 93 intel_tc_port_get_pin_assignment(struct intel_digital_port *dig_port); 94 int intel_tc_port_max_lane_count(struct intel_digital_port *dig_port); 95 void intel_tc_port_set_fia_lane_count(struct intel_digital_port *dig_port, 96 int required_lanes); 97 98 void intel_tc_port_init_mode(struct intel_digital_port *dig_port); 99 void intel_tc_port_sanitize_mode(struct intel_digital_port *dig_port, 100 const struct intel_crtc_state *crtc_state); 101 void intel_tc_port_lock(struct intel_digital_port *dig_port); 102 void intel_tc_port_unlock(struct intel_digital_port *dig_port); 103 void intel_tc_port_suspend(struct intel_digital_port *dig_port); 104 void intel_tc_port_get_link(struct intel_digital_port *dig_port, 105 int required_lanes); 106 void intel_tc_port_put_link(struct intel_digital_port *dig_port); 107 bool intel_tc_port_ref_held(struct intel_digital_port *dig_port); 108 bool intel_tc_port_link_needs_reset(struct intel_digital_port *dig_port); 109 bool intel_tc_port_link_reset(struct intel_digital_port *dig_port); 110 void intel_tc_port_link_cancel_reset_work(struct intel_digital_port *dig_port); 111 112 int intel_tc_port_init(struct intel_digital_port *dig_port, bool is_legacy); 113 void intel_tc_port_cleanup(struct intel_digital_port *dig_port); 114 115 bool intel_tc_cold_requires_aux_pw(struct intel_digital_port *dig_port); 116 117 void intel_tc_info(struct drm_printer *p, struct intel_digital_port *dig_port); 118 119 #endif /* __INTEL_TC_H__ */ 120