1 /* 2 * Copyright © 2011 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 * SOFTWARE. 22 * 23 * Authors: 24 * Jesse Barnes <jbarnes@virtuousgeek.org> 25 * 26 * New plane/sprite handling. 27 * 28 * The older chips had a separate interface for programming plane related 29 * registers; newer ones are much simpler and we can use the new DRM plane 30 * support. 31 */ 32 33 #include <linux/string_helpers.h> 34 35 #include <drm/drm_atomic_helper.h> 36 #include <drm/drm_blend.h> 37 #include <drm/drm_color_mgmt.h> 38 #include <drm/drm_fourcc.h> 39 #include <drm/drm_rect.h> 40 41 #include "i915_drv.h" 42 #include "i9xx_plane.h" 43 #include "intel_atomic_plane.h" 44 #include "intel_de.h" 45 #include "intel_display_types.h" 46 #include "intel_fb.h" 47 #include "intel_frontbuffer.h" 48 #include "intel_sprite.h" 49 #include "intel_sprite_regs.h" 50 51 static char sprite_name(struct drm_i915_private *i915, enum pipe pipe, int sprite) 52 { 53 return pipe * DISPLAY_RUNTIME_INFO(i915)->num_sprites[pipe] + sprite + 'A'; 54 } 55 56 static void i9xx_plane_linear_gamma(u16 gamma[8]) 57 { 58 /* The points are not evenly spaced. */ 59 static const u8 in[8] = { 0, 1, 2, 4, 8, 16, 24, 32 }; 60 int i; 61 62 for (i = 0; i < 8; i++) 63 gamma[i] = (in[i] << 8) / 32; 64 } 65 66 static void 67 chv_sprite_update_csc(const struct intel_plane_state *plane_state) 68 { 69 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); 70 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 71 const struct drm_framebuffer *fb = plane_state->hw.fb; 72 enum plane_id plane_id = plane->id; 73 /* 74 * |r| | c0 c1 c2 | |cr| 75 * |g| = | c3 c4 c5 | x |y | 76 * |b| | c6 c7 c8 | |cb| 77 * 78 * Coefficients are s3.12. 79 * 80 * Cb and Cr apparently come in as signed already, and 81 * we always get full range data in on account of CLRC0/1. 82 */ 83 static const s16 csc_matrix[][9] = { 84 /* BT.601 full range YCbCr -> full range RGB */ 85 [DRM_COLOR_YCBCR_BT601] = { 86 5743, 4096, 0, 87 -2925, 4096, -1410, 88 0, 4096, 7258, 89 }, 90 /* BT.709 full range YCbCr -> full range RGB */ 91 [DRM_COLOR_YCBCR_BT709] = { 92 6450, 4096, 0, 93 -1917, 4096, -767, 94 0, 4096, 7601, 95 }, 96 }; 97 const s16 *csc = csc_matrix[plane_state->hw.color_encoding]; 98 99 /* Seems RGB data bypasses the CSC always */ 100 if (!fb->format->is_yuv) 101 return; 102 103 intel_de_write_fw(dev_priv, SPCSCYGOFF(plane_id), 104 SPCSC_OOFF(0) | SPCSC_IOFF(0)); 105 intel_de_write_fw(dev_priv, SPCSCCBOFF(plane_id), 106 SPCSC_OOFF(0) | SPCSC_IOFF(0)); 107 intel_de_write_fw(dev_priv, SPCSCCROFF(plane_id), 108 SPCSC_OOFF(0) | SPCSC_IOFF(0)); 109 110 intel_de_write_fw(dev_priv, SPCSCC01(plane_id), 111 SPCSC_C1(csc[1]) | SPCSC_C0(csc[0])); 112 intel_de_write_fw(dev_priv, SPCSCC23(plane_id), 113 SPCSC_C1(csc[3]) | SPCSC_C0(csc[2])); 114 intel_de_write_fw(dev_priv, SPCSCC45(plane_id), 115 SPCSC_C1(csc[5]) | SPCSC_C0(csc[4])); 116 intel_de_write_fw(dev_priv, SPCSCC67(plane_id), 117 SPCSC_C1(csc[7]) | SPCSC_C0(csc[6])); 118 intel_de_write_fw(dev_priv, SPCSCC8(plane_id), SPCSC_C0(csc[8])); 119 120 intel_de_write_fw(dev_priv, SPCSCYGICLAMP(plane_id), 121 SPCSC_IMAX(1023) | SPCSC_IMIN(0)); 122 intel_de_write_fw(dev_priv, SPCSCCBICLAMP(plane_id), 123 SPCSC_IMAX(512) | SPCSC_IMIN(-512)); 124 intel_de_write_fw(dev_priv, SPCSCCRICLAMP(plane_id), 125 SPCSC_IMAX(512) | SPCSC_IMIN(-512)); 126 127 intel_de_write_fw(dev_priv, SPCSCYGOCLAMP(plane_id), 128 SPCSC_OMAX(1023) | SPCSC_OMIN(0)); 129 intel_de_write_fw(dev_priv, SPCSCCBOCLAMP(plane_id), 130 SPCSC_OMAX(1023) | SPCSC_OMIN(0)); 131 intel_de_write_fw(dev_priv, SPCSCCROCLAMP(plane_id), 132 SPCSC_OMAX(1023) | SPCSC_OMIN(0)); 133 } 134 135 #define SIN_0 0 136 #define COS_0 1 137 138 static void 139 vlv_sprite_update_clrc(const struct intel_plane_state *plane_state) 140 { 141 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); 142 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 143 const struct drm_framebuffer *fb = plane_state->hw.fb; 144 enum pipe pipe = plane->pipe; 145 enum plane_id plane_id = plane->id; 146 int contrast, brightness, sh_scale, sh_sin, sh_cos; 147 148 if (fb->format->is_yuv && 149 plane_state->hw.color_range == DRM_COLOR_YCBCR_LIMITED_RANGE) { 150 /* 151 * Expand limited range to full range: 152 * Contrast is applied first and is used to expand Y range. 153 * Brightness is applied second and is used to remove the 154 * offset from Y. Saturation/hue is used to expand CbCr range. 155 */ 156 contrast = DIV_ROUND_CLOSEST(255 << 6, 235 - 16); 157 brightness = -DIV_ROUND_CLOSEST(16 * 255, 235 - 16); 158 sh_scale = DIV_ROUND_CLOSEST(128 << 7, 240 - 128); 159 sh_sin = SIN_0 * sh_scale; 160 sh_cos = COS_0 * sh_scale; 161 } else { 162 /* Pass-through everything. */ 163 contrast = 1 << 6; 164 brightness = 0; 165 sh_scale = 1 << 7; 166 sh_sin = SIN_0 * sh_scale; 167 sh_cos = COS_0 * sh_scale; 168 } 169 170 /* FIXME these register are single buffered :( */ 171 intel_de_write_fw(dev_priv, SPCLRC0(pipe, plane_id), 172 SP_CONTRAST(contrast) | SP_BRIGHTNESS(brightness)); 173 intel_de_write_fw(dev_priv, SPCLRC1(pipe, plane_id), 174 SP_SH_SIN(sh_sin) | SP_SH_COS(sh_cos)); 175 } 176 177 static void 178 vlv_plane_ratio(const struct intel_crtc_state *crtc_state, 179 const struct intel_plane_state *plane_state, 180 unsigned int *num, unsigned int *den) 181 { 182 u8 active_planes = crtc_state->active_planes & ~BIT(PLANE_CURSOR); 183 const struct drm_framebuffer *fb = plane_state->hw.fb; 184 unsigned int cpp = fb->format->cpp[0]; 185 186 /* 187 * VLV bspec only considers cases where all three planes are 188 * enabled, and cases where the primary and one sprite is enabled. 189 * Let's assume the case with just two sprites enabled also 190 * maps to the latter case. 191 */ 192 if (hweight8(active_planes) == 3) { 193 switch (cpp) { 194 case 8: 195 *num = 11; 196 *den = 8; 197 break; 198 case 4: 199 *num = 18; 200 *den = 16; 201 break; 202 default: 203 *num = 1; 204 *den = 1; 205 break; 206 } 207 } else if (hweight8(active_planes) == 2) { 208 switch (cpp) { 209 case 8: 210 *num = 10; 211 *den = 8; 212 break; 213 case 4: 214 *num = 17; 215 *den = 16; 216 break; 217 default: 218 *num = 1; 219 *den = 1; 220 break; 221 } 222 } else { 223 switch (cpp) { 224 case 8: 225 *num = 10; 226 *den = 8; 227 break; 228 default: 229 *num = 1; 230 *den = 1; 231 break; 232 } 233 } 234 } 235 236 int vlv_plane_min_cdclk(const struct intel_crtc_state *crtc_state, 237 const struct intel_plane_state *plane_state) 238 { 239 unsigned int pixel_rate; 240 unsigned int num, den; 241 242 /* 243 * Note that crtc_state->pixel_rate accounts for both 244 * horizontal and vertical panel fitter downscaling factors. 245 * Pre-HSW bspec tells us to only consider the horizontal 246 * downscaling factor here. We ignore that and just consider 247 * both for simplicity. 248 */ 249 pixel_rate = crtc_state->pixel_rate; 250 251 vlv_plane_ratio(crtc_state, plane_state, &num, &den); 252 253 return DIV_ROUND_UP(pixel_rate * num, den); 254 } 255 256 static unsigned int vlv_sprite_min_alignment(struct intel_plane *plane, 257 const struct drm_framebuffer *fb, 258 int color_plane) 259 { 260 switch (fb->modifier) { 261 case I915_FORMAT_MOD_X_TILED: 262 return 4 * 1024; 263 case DRM_FORMAT_MOD_LINEAR: 264 return 128 * 1024; 265 default: 266 MISSING_CASE(fb->modifier); 267 return 0; 268 } 269 } 270 271 static u32 vlv_sprite_ctl_crtc(const struct intel_crtc_state *crtc_state) 272 { 273 u32 sprctl = 0; 274 275 if (crtc_state->gamma_enable) 276 sprctl |= SP_PIPE_GAMMA_ENABLE; 277 278 return sprctl; 279 } 280 281 static u32 vlv_sprite_ctl(const struct intel_crtc_state *crtc_state, 282 const struct intel_plane_state *plane_state) 283 { 284 const struct drm_framebuffer *fb = plane_state->hw.fb; 285 unsigned int rotation = plane_state->hw.rotation; 286 const struct drm_intel_sprite_colorkey *key = &plane_state->ckey; 287 u32 sprctl; 288 289 sprctl = SP_ENABLE; 290 291 switch (fb->format->format) { 292 case DRM_FORMAT_YUYV: 293 sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_YUYV; 294 break; 295 case DRM_FORMAT_YVYU: 296 sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_YVYU; 297 break; 298 case DRM_FORMAT_UYVY: 299 sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_UYVY; 300 break; 301 case DRM_FORMAT_VYUY: 302 sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_VYUY; 303 break; 304 case DRM_FORMAT_C8: 305 sprctl |= SP_FORMAT_8BPP; 306 break; 307 case DRM_FORMAT_RGB565: 308 sprctl |= SP_FORMAT_BGR565; 309 break; 310 case DRM_FORMAT_XRGB8888: 311 sprctl |= SP_FORMAT_BGRX8888; 312 break; 313 case DRM_FORMAT_ARGB8888: 314 sprctl |= SP_FORMAT_BGRA8888; 315 break; 316 case DRM_FORMAT_XBGR2101010: 317 sprctl |= SP_FORMAT_RGBX1010102; 318 break; 319 case DRM_FORMAT_ABGR2101010: 320 sprctl |= SP_FORMAT_RGBA1010102; 321 break; 322 case DRM_FORMAT_XRGB2101010: 323 sprctl |= SP_FORMAT_BGRX1010102; 324 break; 325 case DRM_FORMAT_ARGB2101010: 326 sprctl |= SP_FORMAT_BGRA1010102; 327 break; 328 case DRM_FORMAT_XBGR8888: 329 sprctl |= SP_FORMAT_RGBX8888; 330 break; 331 case DRM_FORMAT_ABGR8888: 332 sprctl |= SP_FORMAT_RGBA8888; 333 break; 334 default: 335 MISSING_CASE(fb->format->format); 336 return 0; 337 } 338 339 if (plane_state->hw.color_encoding == DRM_COLOR_YCBCR_BT709) 340 sprctl |= SP_YUV_FORMAT_BT709; 341 342 if (fb->modifier == I915_FORMAT_MOD_X_TILED) 343 sprctl |= SP_TILED; 344 345 if (rotation & DRM_MODE_ROTATE_180) 346 sprctl |= SP_ROTATE_180; 347 348 if (rotation & DRM_MODE_REFLECT_X) 349 sprctl |= SP_MIRROR; 350 351 if (key->flags & I915_SET_COLORKEY_SOURCE) 352 sprctl |= SP_SOURCE_KEY; 353 354 return sprctl; 355 } 356 357 static void vlv_sprite_update_gamma(const struct intel_plane_state *plane_state) 358 { 359 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); 360 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 361 const struct drm_framebuffer *fb = plane_state->hw.fb; 362 enum pipe pipe = plane->pipe; 363 enum plane_id plane_id = plane->id; 364 u16 gamma[8]; 365 int i; 366 367 /* Seems RGB data bypasses the gamma always */ 368 if (!fb->format->is_yuv) 369 return; 370 371 i9xx_plane_linear_gamma(gamma); 372 373 /* FIXME these register are single buffered :( */ 374 /* The two end points are implicit (0.0 and 1.0) */ 375 for (i = 1; i < 8 - 1; i++) 376 intel_de_write_fw(dev_priv, SPGAMC(pipe, plane_id, i - 1), 377 gamma[i] << 16 | gamma[i] << 8 | gamma[i]); 378 } 379 380 static void 381 vlv_sprite_update_noarm(struct intel_plane *plane, 382 const struct intel_crtc_state *crtc_state, 383 const struct intel_plane_state *plane_state) 384 { 385 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 386 enum pipe pipe = plane->pipe; 387 enum plane_id plane_id = plane->id; 388 int crtc_x = plane_state->uapi.dst.x1; 389 int crtc_y = plane_state->uapi.dst.y1; 390 u32 crtc_w = drm_rect_width(&plane_state->uapi.dst); 391 u32 crtc_h = drm_rect_height(&plane_state->uapi.dst); 392 393 intel_de_write_fw(dev_priv, SPSTRIDE(pipe, plane_id), 394 plane_state->view.color_plane[0].mapping_stride); 395 intel_de_write_fw(dev_priv, SPPOS(pipe, plane_id), 396 SP_POS_Y(crtc_y) | SP_POS_X(crtc_x)); 397 intel_de_write_fw(dev_priv, SPSIZE(pipe, plane_id), 398 SP_HEIGHT(crtc_h - 1) | SP_WIDTH(crtc_w - 1)); 399 } 400 401 static void 402 vlv_sprite_update_arm(struct intel_plane *plane, 403 const struct intel_crtc_state *crtc_state, 404 const struct intel_plane_state *plane_state) 405 { 406 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 407 enum pipe pipe = plane->pipe; 408 enum plane_id plane_id = plane->id; 409 const struct drm_intel_sprite_colorkey *key = &plane_state->ckey; 410 u32 sprsurf_offset = plane_state->view.color_plane[0].offset; 411 u32 x = plane_state->view.color_plane[0].x; 412 u32 y = plane_state->view.color_plane[0].y; 413 u32 sprctl, linear_offset; 414 415 sprctl = plane_state->ctl | vlv_sprite_ctl_crtc(crtc_state); 416 417 linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0); 418 419 if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) 420 chv_sprite_update_csc(plane_state); 421 422 if (key->flags) { 423 intel_de_write_fw(dev_priv, SPKEYMINVAL(pipe, plane_id), 424 key->min_value); 425 intel_de_write_fw(dev_priv, SPKEYMSK(pipe, plane_id), 426 key->channel_mask); 427 intel_de_write_fw(dev_priv, SPKEYMAXVAL(pipe, plane_id), 428 key->max_value); 429 } 430 431 intel_de_write_fw(dev_priv, SPCONSTALPHA(pipe, plane_id), 0); 432 433 intel_de_write_fw(dev_priv, SPLINOFF(pipe, plane_id), linear_offset); 434 intel_de_write_fw(dev_priv, SPTILEOFF(pipe, plane_id), 435 SP_OFFSET_Y(y) | SP_OFFSET_X(x)); 436 437 /* 438 * The control register self-arms if the plane was previously 439 * disabled. Try to make the plane enable atomic by writing 440 * the control register just before the surface register. 441 */ 442 intel_de_write_fw(dev_priv, SPCNTR(pipe, plane_id), sprctl); 443 intel_de_write_fw(dev_priv, SPSURF(pipe, plane_id), 444 intel_plane_ggtt_offset(plane_state) + sprsurf_offset); 445 446 vlv_sprite_update_clrc(plane_state); 447 vlv_sprite_update_gamma(plane_state); 448 } 449 450 static void 451 vlv_sprite_disable_arm(struct intel_plane *plane, 452 const struct intel_crtc_state *crtc_state) 453 { 454 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 455 enum pipe pipe = plane->pipe; 456 enum plane_id plane_id = plane->id; 457 458 intel_de_write_fw(dev_priv, SPCNTR(pipe, plane_id), 0); 459 intel_de_write_fw(dev_priv, SPSURF(pipe, plane_id), 0); 460 } 461 462 static bool 463 vlv_sprite_get_hw_state(struct intel_plane *plane, 464 enum pipe *pipe) 465 { 466 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 467 enum intel_display_power_domain power_domain; 468 enum plane_id plane_id = plane->id; 469 intel_wakeref_t wakeref; 470 bool ret; 471 472 power_domain = POWER_DOMAIN_PIPE(plane->pipe); 473 wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain); 474 if (!wakeref) 475 return false; 476 477 ret = intel_de_read(dev_priv, SPCNTR(plane->pipe, plane_id)) & SP_ENABLE; 478 479 *pipe = plane->pipe; 480 481 intel_display_power_put(dev_priv, power_domain, wakeref); 482 483 return ret; 484 } 485 486 static void ivb_plane_ratio(const struct intel_crtc_state *crtc_state, 487 const struct intel_plane_state *plane_state, 488 unsigned int *num, unsigned int *den) 489 { 490 u8 active_planes = crtc_state->active_planes & ~BIT(PLANE_CURSOR); 491 const struct drm_framebuffer *fb = plane_state->hw.fb; 492 unsigned int cpp = fb->format->cpp[0]; 493 494 if (hweight8(active_planes) == 2) { 495 switch (cpp) { 496 case 8: 497 *num = 10; 498 *den = 8; 499 break; 500 case 4: 501 *num = 17; 502 *den = 16; 503 break; 504 default: 505 *num = 1; 506 *den = 1; 507 break; 508 } 509 } else { 510 switch (cpp) { 511 case 8: 512 *num = 9; 513 *den = 8; 514 break; 515 default: 516 *num = 1; 517 *den = 1; 518 break; 519 } 520 } 521 } 522 523 static void ivb_plane_ratio_scaling(const struct intel_crtc_state *crtc_state, 524 const struct intel_plane_state *plane_state, 525 unsigned int *num, unsigned int *den) 526 { 527 const struct drm_framebuffer *fb = plane_state->hw.fb; 528 unsigned int cpp = fb->format->cpp[0]; 529 530 switch (cpp) { 531 case 8: 532 *num = 12; 533 *den = 8; 534 break; 535 case 4: 536 *num = 19; 537 *den = 16; 538 break; 539 case 2: 540 *num = 33; 541 *den = 32; 542 break; 543 default: 544 *num = 1; 545 *den = 1; 546 break; 547 } 548 } 549 550 int ivb_plane_min_cdclk(const struct intel_crtc_state *crtc_state, 551 const struct intel_plane_state *plane_state) 552 { 553 unsigned int pixel_rate; 554 unsigned int num, den; 555 556 /* 557 * Note that crtc_state->pixel_rate accounts for both 558 * horizontal and vertical panel fitter downscaling factors. 559 * Pre-HSW bspec tells us to only consider the horizontal 560 * downscaling factor here. We ignore that and just consider 561 * both for simplicity. 562 */ 563 pixel_rate = crtc_state->pixel_rate; 564 565 ivb_plane_ratio(crtc_state, plane_state, &num, &den); 566 567 return DIV_ROUND_UP(pixel_rate * num, den); 568 } 569 570 static int ivb_sprite_min_cdclk(const struct intel_crtc_state *crtc_state, 571 const struct intel_plane_state *plane_state) 572 { 573 unsigned int src_w, dst_w, pixel_rate; 574 unsigned int num, den; 575 576 /* 577 * Note that crtc_state->pixel_rate accounts for both 578 * horizontal and vertical panel fitter downscaling factors. 579 * Pre-HSW bspec tells us to only consider the horizontal 580 * downscaling factor here. We ignore that and just consider 581 * both for simplicity. 582 */ 583 pixel_rate = crtc_state->pixel_rate; 584 585 src_w = drm_rect_width(&plane_state->uapi.src) >> 16; 586 dst_w = drm_rect_width(&plane_state->uapi.dst); 587 588 if (src_w != dst_w) 589 ivb_plane_ratio_scaling(crtc_state, plane_state, &num, &den); 590 else 591 ivb_plane_ratio(crtc_state, plane_state, &num, &den); 592 593 /* Horizontal downscaling limits the maximum pixel rate */ 594 dst_w = min(src_w, dst_w); 595 596 return DIV_ROUND_UP_ULL(mul_u32_u32(pixel_rate, num * src_w), 597 den * dst_w); 598 } 599 600 static void hsw_plane_ratio(const struct intel_crtc_state *crtc_state, 601 const struct intel_plane_state *plane_state, 602 unsigned int *num, unsigned int *den) 603 { 604 u8 active_planes = crtc_state->active_planes & ~BIT(PLANE_CURSOR); 605 const struct drm_framebuffer *fb = plane_state->hw.fb; 606 unsigned int cpp = fb->format->cpp[0]; 607 608 if (hweight8(active_planes) == 2) { 609 switch (cpp) { 610 case 8: 611 *num = 10; 612 *den = 8; 613 break; 614 default: 615 *num = 1; 616 *den = 1; 617 break; 618 } 619 } else { 620 switch (cpp) { 621 case 8: 622 *num = 9; 623 *den = 8; 624 break; 625 default: 626 *num = 1; 627 *den = 1; 628 break; 629 } 630 } 631 } 632 633 int hsw_plane_min_cdclk(const struct intel_crtc_state *crtc_state, 634 const struct intel_plane_state *plane_state) 635 { 636 unsigned int pixel_rate = crtc_state->pixel_rate; 637 unsigned int num, den; 638 639 hsw_plane_ratio(crtc_state, plane_state, &num, &den); 640 641 return DIV_ROUND_UP(pixel_rate * num, den); 642 } 643 644 static u32 ivb_sprite_ctl_crtc(const struct intel_crtc_state *crtc_state) 645 { 646 u32 sprctl = 0; 647 648 if (crtc_state->gamma_enable) 649 sprctl |= SPRITE_PIPE_GAMMA_ENABLE; 650 651 if (crtc_state->csc_enable) 652 sprctl |= SPRITE_PIPE_CSC_ENABLE; 653 654 return sprctl; 655 } 656 657 static bool ivb_need_sprite_gamma(const struct intel_plane_state *plane_state) 658 { 659 struct drm_i915_private *dev_priv = 660 to_i915(plane_state->uapi.plane->dev); 661 const struct drm_framebuffer *fb = plane_state->hw.fb; 662 663 return fb->format->cpp[0] == 8 && 664 (IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv)); 665 } 666 667 static u32 ivb_sprite_ctl(const struct intel_crtc_state *crtc_state, 668 const struct intel_plane_state *plane_state) 669 { 670 struct drm_i915_private *dev_priv = 671 to_i915(plane_state->uapi.plane->dev); 672 const struct drm_framebuffer *fb = plane_state->hw.fb; 673 unsigned int rotation = plane_state->hw.rotation; 674 const struct drm_intel_sprite_colorkey *key = &plane_state->ckey; 675 u32 sprctl; 676 677 sprctl = SPRITE_ENABLE; 678 679 if (IS_IVYBRIDGE(dev_priv)) 680 sprctl |= SPRITE_TRICKLE_FEED_DISABLE; 681 682 switch (fb->format->format) { 683 case DRM_FORMAT_XBGR8888: 684 sprctl |= SPRITE_FORMAT_RGBX888 | SPRITE_RGB_ORDER_RGBX; 685 break; 686 case DRM_FORMAT_XRGB8888: 687 sprctl |= SPRITE_FORMAT_RGBX888; 688 break; 689 case DRM_FORMAT_XBGR2101010: 690 sprctl |= SPRITE_FORMAT_RGBX101010 | SPRITE_RGB_ORDER_RGBX; 691 break; 692 case DRM_FORMAT_XRGB2101010: 693 sprctl |= SPRITE_FORMAT_RGBX101010; 694 break; 695 case DRM_FORMAT_XBGR16161616F: 696 sprctl |= SPRITE_FORMAT_RGBX161616 | SPRITE_RGB_ORDER_RGBX; 697 break; 698 case DRM_FORMAT_XRGB16161616F: 699 sprctl |= SPRITE_FORMAT_RGBX161616; 700 break; 701 case DRM_FORMAT_YUYV: 702 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_YUYV; 703 break; 704 case DRM_FORMAT_YVYU: 705 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_YVYU; 706 break; 707 case DRM_FORMAT_UYVY: 708 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_UYVY; 709 break; 710 case DRM_FORMAT_VYUY: 711 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_VYUY; 712 break; 713 default: 714 MISSING_CASE(fb->format->format); 715 return 0; 716 } 717 718 if (!ivb_need_sprite_gamma(plane_state)) 719 sprctl |= SPRITE_PLANE_GAMMA_DISABLE; 720 721 if (plane_state->hw.color_encoding == DRM_COLOR_YCBCR_BT709) 722 sprctl |= SPRITE_YUV_TO_RGB_CSC_FORMAT_BT709; 723 724 if (plane_state->hw.color_range == DRM_COLOR_YCBCR_FULL_RANGE) 725 sprctl |= SPRITE_YUV_RANGE_CORRECTION_DISABLE; 726 727 if (fb->modifier == I915_FORMAT_MOD_X_TILED) 728 sprctl |= SPRITE_TILED; 729 730 if (rotation & DRM_MODE_ROTATE_180) 731 sprctl |= SPRITE_ROTATE_180; 732 733 if (key->flags & I915_SET_COLORKEY_DESTINATION) 734 sprctl |= SPRITE_DEST_KEY; 735 else if (key->flags & I915_SET_COLORKEY_SOURCE) 736 sprctl |= SPRITE_SOURCE_KEY; 737 738 return sprctl; 739 } 740 741 static void ivb_sprite_linear_gamma(const struct intel_plane_state *plane_state, 742 u16 gamma[18]) 743 { 744 int scale, i; 745 746 /* 747 * WaFP16GammaEnabling:ivb,hsw 748 * "Workaround : When using the 64-bit format, the sprite output 749 * on each color channel has one quarter amplitude. It can be 750 * brought up to full amplitude by using sprite internal gamma 751 * correction, pipe gamma correction, or pipe color space 752 * conversion to multiply the sprite output by four." 753 */ 754 scale = 4; 755 756 for (i = 0; i < 16; i++) 757 gamma[i] = min((scale * i << 10) / 16, (1 << 10) - 1); 758 759 gamma[i] = min((scale * i << 10) / 16, 1 << 10); 760 i++; 761 762 gamma[i] = 3 << 10; 763 i++; 764 } 765 766 static void ivb_sprite_update_gamma(const struct intel_plane_state *plane_state) 767 { 768 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); 769 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 770 enum pipe pipe = plane->pipe; 771 u16 gamma[18]; 772 int i; 773 774 if (!ivb_need_sprite_gamma(plane_state)) 775 return; 776 777 ivb_sprite_linear_gamma(plane_state, gamma); 778 779 /* FIXME these register are single buffered :( */ 780 for (i = 0; i < 16; i++) 781 intel_de_write_fw(dev_priv, SPRGAMC(pipe, i), 782 gamma[i] << 20 | gamma[i] << 10 | gamma[i]); 783 784 intel_de_write_fw(dev_priv, SPRGAMC16(pipe, 0), gamma[i]); 785 intel_de_write_fw(dev_priv, SPRGAMC16(pipe, 1), gamma[i]); 786 intel_de_write_fw(dev_priv, SPRGAMC16(pipe, 2), gamma[i]); 787 i++; 788 789 intel_de_write_fw(dev_priv, SPRGAMC17(pipe, 0), gamma[i]); 790 intel_de_write_fw(dev_priv, SPRGAMC17(pipe, 1), gamma[i]); 791 intel_de_write_fw(dev_priv, SPRGAMC17(pipe, 2), gamma[i]); 792 i++; 793 } 794 795 static void 796 ivb_sprite_update_noarm(struct intel_plane *plane, 797 const struct intel_crtc_state *crtc_state, 798 const struct intel_plane_state *plane_state) 799 { 800 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 801 enum pipe pipe = plane->pipe; 802 int crtc_x = plane_state->uapi.dst.x1; 803 int crtc_y = plane_state->uapi.dst.y1; 804 u32 crtc_w = drm_rect_width(&plane_state->uapi.dst); 805 u32 crtc_h = drm_rect_height(&plane_state->uapi.dst); 806 u32 src_w = drm_rect_width(&plane_state->uapi.src) >> 16; 807 u32 src_h = drm_rect_height(&plane_state->uapi.src) >> 16; 808 u32 sprscale = 0; 809 810 if (crtc_w != src_w || crtc_h != src_h) 811 sprscale = SPRITE_SCALE_ENABLE | 812 SPRITE_SRC_WIDTH(src_w - 1) | 813 SPRITE_SRC_HEIGHT(src_h - 1); 814 815 intel_de_write_fw(dev_priv, SPRSTRIDE(pipe), 816 plane_state->view.color_plane[0].mapping_stride); 817 intel_de_write_fw(dev_priv, SPRPOS(pipe), 818 SPRITE_POS_Y(crtc_y) | SPRITE_POS_X(crtc_x)); 819 intel_de_write_fw(dev_priv, SPRSIZE(pipe), 820 SPRITE_HEIGHT(crtc_h - 1) | SPRITE_WIDTH(crtc_w - 1)); 821 if (IS_IVYBRIDGE(dev_priv)) 822 intel_de_write_fw(dev_priv, SPRSCALE(pipe), sprscale); 823 } 824 825 static void 826 ivb_sprite_update_arm(struct intel_plane *plane, 827 const struct intel_crtc_state *crtc_state, 828 const struct intel_plane_state *plane_state) 829 { 830 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 831 enum pipe pipe = plane->pipe; 832 const struct drm_intel_sprite_colorkey *key = &plane_state->ckey; 833 u32 sprsurf_offset = plane_state->view.color_plane[0].offset; 834 u32 x = plane_state->view.color_plane[0].x; 835 u32 y = plane_state->view.color_plane[0].y; 836 u32 sprctl, linear_offset; 837 838 sprctl = plane_state->ctl | ivb_sprite_ctl_crtc(crtc_state); 839 840 linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0); 841 842 if (key->flags) { 843 intel_de_write_fw(dev_priv, SPRKEYVAL(pipe), key->min_value); 844 intel_de_write_fw(dev_priv, SPRKEYMSK(pipe), 845 key->channel_mask); 846 intel_de_write_fw(dev_priv, SPRKEYMAX(pipe), key->max_value); 847 } 848 849 /* HSW consolidates SPRTILEOFF and SPRLINOFF into a single SPROFFSET 850 * register */ 851 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { 852 intel_de_write_fw(dev_priv, SPROFFSET(pipe), 853 SPRITE_OFFSET_Y(y) | SPRITE_OFFSET_X(x)); 854 } else { 855 intel_de_write_fw(dev_priv, SPRLINOFF(pipe), linear_offset); 856 intel_de_write_fw(dev_priv, SPRTILEOFF(pipe), 857 SPRITE_OFFSET_Y(y) | SPRITE_OFFSET_X(x)); 858 } 859 860 /* 861 * The control register self-arms if the plane was previously 862 * disabled. Try to make the plane enable atomic by writing 863 * the control register just before the surface register. 864 */ 865 intel_de_write_fw(dev_priv, SPRCTL(pipe), sprctl); 866 intel_de_write_fw(dev_priv, SPRSURF(pipe), 867 intel_plane_ggtt_offset(plane_state) + sprsurf_offset); 868 869 ivb_sprite_update_gamma(plane_state); 870 } 871 872 static void 873 ivb_sprite_disable_arm(struct intel_plane *plane, 874 const struct intel_crtc_state *crtc_state) 875 { 876 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 877 enum pipe pipe = plane->pipe; 878 879 intel_de_write_fw(dev_priv, SPRCTL(pipe), 0); 880 /* Disable the scaler */ 881 if (IS_IVYBRIDGE(dev_priv)) 882 intel_de_write_fw(dev_priv, SPRSCALE(pipe), 0); 883 intel_de_write_fw(dev_priv, SPRSURF(pipe), 0); 884 } 885 886 static bool 887 ivb_sprite_get_hw_state(struct intel_plane *plane, 888 enum pipe *pipe) 889 { 890 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 891 enum intel_display_power_domain power_domain; 892 intel_wakeref_t wakeref; 893 bool ret; 894 895 power_domain = POWER_DOMAIN_PIPE(plane->pipe); 896 wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain); 897 if (!wakeref) 898 return false; 899 900 ret = intel_de_read(dev_priv, SPRCTL(plane->pipe)) & SPRITE_ENABLE; 901 902 *pipe = plane->pipe; 903 904 intel_display_power_put(dev_priv, power_domain, wakeref); 905 906 return ret; 907 } 908 909 static int g4x_sprite_min_cdclk(const struct intel_crtc_state *crtc_state, 910 const struct intel_plane_state *plane_state) 911 { 912 const struct drm_framebuffer *fb = plane_state->hw.fb; 913 unsigned int hscale, pixel_rate; 914 unsigned int limit, decimate; 915 916 /* 917 * Note that crtc_state->pixel_rate accounts for both 918 * horizontal and vertical panel fitter downscaling factors. 919 * Pre-HSW bspec tells us to only consider the horizontal 920 * downscaling factor here. We ignore that and just consider 921 * both for simplicity. 922 */ 923 pixel_rate = crtc_state->pixel_rate; 924 925 /* Horizontal downscaling limits the maximum pixel rate */ 926 hscale = drm_rect_calc_hscale(&plane_state->uapi.src, 927 &plane_state->uapi.dst, 928 0, INT_MAX); 929 hscale = max(hscale, 0x10000u); 930 931 /* Decimation steps at 2x,4x,8x,16x */ 932 decimate = ilog2(hscale >> 16); 933 hscale >>= decimate; 934 935 /* Starting limit is 90% of cdclk */ 936 limit = 9; 937 938 /* -10% per decimation step */ 939 limit -= decimate; 940 941 /* -10% for RGB */ 942 if (!fb->format->is_yuv) 943 limit--; 944 945 /* 946 * We should also do -10% if sprite scaling is enabled 947 * on the other pipe, but we can't really check for that, 948 * so we ignore it. 949 */ 950 951 return DIV_ROUND_UP_ULL(mul_u32_u32(pixel_rate, 10 * hscale), 952 limit << 16); 953 } 954 955 static unsigned int 956 g4x_sprite_max_stride(struct intel_plane *plane, 957 u32 pixel_format, u64 modifier, 958 unsigned int rotation) 959 { 960 const struct drm_format_info *info = drm_format_info(pixel_format); 961 int cpp = info->cpp[0]; 962 963 /* Limit to 4k pixels to guarantee TILEOFF.x doesn't get too big. */ 964 if (modifier == I915_FORMAT_MOD_X_TILED) 965 return min(4096 * cpp, 16 * 1024); 966 else 967 return 16 * 1024; 968 } 969 970 static unsigned int 971 hsw_sprite_max_stride(struct intel_plane *plane, 972 u32 pixel_format, u64 modifier, 973 unsigned int rotation) 974 { 975 const struct drm_format_info *info = drm_format_info(pixel_format); 976 int cpp = info->cpp[0]; 977 978 /* Limit to 8k pixels to guarantee OFFSET.x doesn't get too big. */ 979 return min(8192 * cpp, 16 * 1024); 980 } 981 982 static unsigned int g4x_sprite_min_alignment(struct intel_plane *plane, 983 const struct drm_framebuffer *fb, 984 int color_plane) 985 { 986 return 4 * 1024; 987 } 988 989 static u32 g4x_sprite_ctl_crtc(const struct intel_crtc_state *crtc_state) 990 { 991 u32 dvscntr = 0; 992 993 if (crtc_state->gamma_enable) 994 dvscntr |= DVS_PIPE_GAMMA_ENABLE; 995 996 if (crtc_state->csc_enable) 997 dvscntr |= DVS_PIPE_CSC_ENABLE; 998 999 return dvscntr; 1000 } 1001 1002 static u32 g4x_sprite_ctl(const struct intel_crtc_state *crtc_state, 1003 const struct intel_plane_state *plane_state) 1004 { 1005 struct drm_i915_private *dev_priv = 1006 to_i915(plane_state->uapi.plane->dev); 1007 const struct drm_framebuffer *fb = plane_state->hw.fb; 1008 unsigned int rotation = plane_state->hw.rotation; 1009 const struct drm_intel_sprite_colorkey *key = &plane_state->ckey; 1010 u32 dvscntr; 1011 1012 dvscntr = DVS_ENABLE; 1013 1014 if (IS_SANDYBRIDGE(dev_priv)) 1015 dvscntr |= DVS_TRICKLE_FEED_DISABLE; 1016 1017 switch (fb->format->format) { 1018 case DRM_FORMAT_XBGR8888: 1019 dvscntr |= DVS_FORMAT_RGBX888 | DVS_RGB_ORDER_XBGR; 1020 break; 1021 case DRM_FORMAT_XRGB8888: 1022 dvscntr |= DVS_FORMAT_RGBX888; 1023 break; 1024 case DRM_FORMAT_XBGR2101010: 1025 dvscntr |= DVS_FORMAT_RGBX101010 | DVS_RGB_ORDER_XBGR; 1026 break; 1027 case DRM_FORMAT_XRGB2101010: 1028 dvscntr |= DVS_FORMAT_RGBX101010; 1029 break; 1030 case DRM_FORMAT_XBGR16161616F: 1031 dvscntr |= DVS_FORMAT_RGBX161616 | DVS_RGB_ORDER_XBGR; 1032 break; 1033 case DRM_FORMAT_XRGB16161616F: 1034 dvscntr |= DVS_FORMAT_RGBX161616; 1035 break; 1036 case DRM_FORMAT_YUYV: 1037 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_YUYV; 1038 break; 1039 case DRM_FORMAT_YVYU: 1040 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_YVYU; 1041 break; 1042 case DRM_FORMAT_UYVY: 1043 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_UYVY; 1044 break; 1045 case DRM_FORMAT_VYUY: 1046 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_VYUY; 1047 break; 1048 default: 1049 MISSING_CASE(fb->format->format); 1050 return 0; 1051 } 1052 1053 if (plane_state->hw.color_encoding == DRM_COLOR_YCBCR_BT709) 1054 dvscntr |= DVS_YUV_FORMAT_BT709; 1055 1056 if (plane_state->hw.color_range == DRM_COLOR_YCBCR_FULL_RANGE) 1057 dvscntr |= DVS_YUV_RANGE_CORRECTION_DISABLE; 1058 1059 if (fb->modifier == I915_FORMAT_MOD_X_TILED) 1060 dvscntr |= DVS_TILED; 1061 1062 if (rotation & DRM_MODE_ROTATE_180) 1063 dvscntr |= DVS_ROTATE_180; 1064 1065 if (key->flags & I915_SET_COLORKEY_DESTINATION) 1066 dvscntr |= DVS_DEST_KEY; 1067 else if (key->flags & I915_SET_COLORKEY_SOURCE) 1068 dvscntr |= DVS_SOURCE_KEY; 1069 1070 return dvscntr; 1071 } 1072 1073 static void g4x_sprite_update_gamma(const struct intel_plane_state *plane_state) 1074 { 1075 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); 1076 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 1077 const struct drm_framebuffer *fb = plane_state->hw.fb; 1078 enum pipe pipe = plane->pipe; 1079 u16 gamma[8]; 1080 int i; 1081 1082 /* Seems RGB data bypasses the gamma always */ 1083 if (!fb->format->is_yuv) 1084 return; 1085 1086 i9xx_plane_linear_gamma(gamma); 1087 1088 /* FIXME these register are single buffered :( */ 1089 /* The two end points are implicit (0.0 and 1.0) */ 1090 for (i = 1; i < 8 - 1; i++) 1091 intel_de_write_fw(dev_priv, DVSGAMC_G4X(pipe, i - 1), 1092 gamma[i] << 16 | gamma[i] << 8 | gamma[i]); 1093 } 1094 1095 static void ilk_sprite_linear_gamma(u16 gamma[17]) 1096 { 1097 int i; 1098 1099 for (i = 0; i < 17; i++) 1100 gamma[i] = (i << 10) / 16; 1101 } 1102 1103 static void ilk_sprite_update_gamma(const struct intel_plane_state *plane_state) 1104 { 1105 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); 1106 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 1107 const struct drm_framebuffer *fb = plane_state->hw.fb; 1108 enum pipe pipe = plane->pipe; 1109 u16 gamma[17]; 1110 int i; 1111 1112 /* Seems RGB data bypasses the gamma always */ 1113 if (!fb->format->is_yuv) 1114 return; 1115 1116 ilk_sprite_linear_gamma(gamma); 1117 1118 /* FIXME these register are single buffered :( */ 1119 for (i = 0; i < 16; i++) 1120 intel_de_write_fw(dev_priv, DVSGAMC_ILK(pipe, i), 1121 gamma[i] << 20 | gamma[i] << 10 | gamma[i]); 1122 1123 intel_de_write_fw(dev_priv, DVSGAMCMAX_ILK(pipe, 0), gamma[i]); 1124 intel_de_write_fw(dev_priv, DVSGAMCMAX_ILK(pipe, 1), gamma[i]); 1125 intel_de_write_fw(dev_priv, DVSGAMCMAX_ILK(pipe, 2), gamma[i]); 1126 i++; 1127 } 1128 1129 static void 1130 g4x_sprite_update_noarm(struct intel_plane *plane, 1131 const struct intel_crtc_state *crtc_state, 1132 const struct intel_plane_state *plane_state) 1133 { 1134 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 1135 enum pipe pipe = plane->pipe; 1136 int crtc_x = plane_state->uapi.dst.x1; 1137 int crtc_y = plane_state->uapi.dst.y1; 1138 u32 crtc_w = drm_rect_width(&plane_state->uapi.dst); 1139 u32 crtc_h = drm_rect_height(&plane_state->uapi.dst); 1140 u32 src_w = drm_rect_width(&plane_state->uapi.src) >> 16; 1141 u32 src_h = drm_rect_height(&plane_state->uapi.src) >> 16; 1142 u32 dvsscale = 0; 1143 1144 if (crtc_w != src_w || crtc_h != src_h) 1145 dvsscale = DVS_SCALE_ENABLE | 1146 DVS_SRC_WIDTH(src_w - 1) | 1147 DVS_SRC_HEIGHT(src_h - 1); 1148 1149 intel_de_write_fw(dev_priv, DVSSTRIDE(pipe), 1150 plane_state->view.color_plane[0].mapping_stride); 1151 intel_de_write_fw(dev_priv, DVSPOS(pipe), 1152 DVS_POS_Y(crtc_y) | DVS_POS_X(crtc_x)); 1153 intel_de_write_fw(dev_priv, DVSSIZE(pipe), 1154 DVS_HEIGHT(crtc_h - 1) | DVS_WIDTH(crtc_w - 1)); 1155 intel_de_write_fw(dev_priv, DVSSCALE(pipe), dvsscale); 1156 } 1157 1158 static void 1159 g4x_sprite_update_arm(struct intel_plane *plane, 1160 const struct intel_crtc_state *crtc_state, 1161 const struct intel_plane_state *plane_state) 1162 { 1163 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 1164 enum pipe pipe = plane->pipe; 1165 const struct drm_intel_sprite_colorkey *key = &plane_state->ckey; 1166 u32 dvssurf_offset = plane_state->view.color_plane[0].offset; 1167 u32 x = plane_state->view.color_plane[0].x; 1168 u32 y = plane_state->view.color_plane[0].y; 1169 u32 dvscntr, linear_offset; 1170 1171 dvscntr = plane_state->ctl | g4x_sprite_ctl_crtc(crtc_state); 1172 1173 linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0); 1174 1175 if (key->flags) { 1176 intel_de_write_fw(dev_priv, DVSKEYVAL(pipe), key->min_value); 1177 intel_de_write_fw(dev_priv, DVSKEYMSK(pipe), 1178 key->channel_mask); 1179 intel_de_write_fw(dev_priv, DVSKEYMAX(pipe), key->max_value); 1180 } 1181 1182 intel_de_write_fw(dev_priv, DVSLINOFF(pipe), linear_offset); 1183 intel_de_write_fw(dev_priv, DVSTILEOFF(pipe), 1184 DVS_OFFSET_Y(y) | DVS_OFFSET_X(x)); 1185 1186 /* 1187 * The control register self-arms if the plane was previously 1188 * disabled. Try to make the plane enable atomic by writing 1189 * the control register just before the surface register. 1190 */ 1191 intel_de_write_fw(dev_priv, DVSCNTR(pipe), dvscntr); 1192 intel_de_write_fw(dev_priv, DVSSURF(pipe), 1193 intel_plane_ggtt_offset(plane_state) + dvssurf_offset); 1194 1195 if (IS_G4X(dev_priv)) 1196 g4x_sprite_update_gamma(plane_state); 1197 else 1198 ilk_sprite_update_gamma(plane_state); 1199 } 1200 1201 static void 1202 g4x_sprite_disable_arm(struct intel_plane *plane, 1203 const struct intel_crtc_state *crtc_state) 1204 { 1205 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 1206 enum pipe pipe = plane->pipe; 1207 1208 intel_de_write_fw(dev_priv, DVSCNTR(pipe), 0); 1209 /* Disable the scaler */ 1210 intel_de_write_fw(dev_priv, DVSSCALE(pipe), 0); 1211 intel_de_write_fw(dev_priv, DVSSURF(pipe), 0); 1212 } 1213 1214 static bool 1215 g4x_sprite_get_hw_state(struct intel_plane *plane, 1216 enum pipe *pipe) 1217 { 1218 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 1219 enum intel_display_power_domain power_domain; 1220 intel_wakeref_t wakeref; 1221 bool ret; 1222 1223 power_domain = POWER_DOMAIN_PIPE(plane->pipe); 1224 wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain); 1225 if (!wakeref) 1226 return false; 1227 1228 ret = intel_de_read(dev_priv, DVSCNTR(plane->pipe)) & DVS_ENABLE; 1229 1230 *pipe = plane->pipe; 1231 1232 intel_display_power_put(dev_priv, power_domain, wakeref); 1233 1234 return ret; 1235 } 1236 1237 static bool g4x_fb_scalable(const struct drm_framebuffer *fb) 1238 { 1239 if (!fb) 1240 return false; 1241 1242 switch (fb->format->format) { 1243 case DRM_FORMAT_C8: 1244 case DRM_FORMAT_XRGB16161616F: 1245 case DRM_FORMAT_ARGB16161616F: 1246 case DRM_FORMAT_XBGR16161616F: 1247 case DRM_FORMAT_ABGR16161616F: 1248 return false; 1249 default: 1250 return true; 1251 } 1252 } 1253 1254 static int 1255 g4x_sprite_check_scaling(struct intel_crtc_state *crtc_state, 1256 struct intel_plane_state *plane_state) 1257 { 1258 struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev); 1259 const struct drm_framebuffer *fb = plane_state->hw.fb; 1260 const struct drm_rect *src = &plane_state->uapi.src; 1261 const struct drm_rect *dst = &plane_state->uapi.dst; 1262 int src_x, src_w, src_h, crtc_w, crtc_h; 1263 const struct drm_display_mode *adjusted_mode = 1264 &crtc_state->hw.adjusted_mode; 1265 unsigned int stride = plane_state->view.color_plane[0].mapping_stride; 1266 unsigned int cpp = fb->format->cpp[0]; 1267 unsigned int width_bytes; 1268 int min_width, min_height; 1269 1270 crtc_w = drm_rect_width(dst); 1271 crtc_h = drm_rect_height(dst); 1272 1273 src_x = src->x1 >> 16; 1274 src_w = drm_rect_width(src) >> 16; 1275 src_h = drm_rect_height(src) >> 16; 1276 1277 if (src_w == crtc_w && src_h == crtc_h) 1278 return 0; 1279 1280 min_width = 3; 1281 1282 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { 1283 if (src_h & 1) { 1284 drm_dbg_kms(&i915->drm, "Source height must be even with interlaced modes\n"); 1285 return -EINVAL; 1286 } 1287 min_height = 6; 1288 } else { 1289 min_height = 3; 1290 } 1291 1292 width_bytes = ((src_x * cpp) & 63) + src_w * cpp; 1293 1294 if (src_w < min_width || src_h < min_height || 1295 src_w > 2048 || src_h > 2048) { 1296 drm_dbg_kms(&i915->drm, "Source dimensions (%dx%d) exceed hardware limits (%dx%d - %dx%d)\n", 1297 src_w, src_h, min_width, min_height, 2048, 2048); 1298 return -EINVAL; 1299 } 1300 1301 if (width_bytes > 4096) { 1302 drm_dbg_kms(&i915->drm, "Fetch width (%d) exceeds hardware max with scaling (%u)\n", 1303 width_bytes, 4096); 1304 return -EINVAL; 1305 } 1306 1307 if (stride > 4096) { 1308 drm_dbg_kms(&i915->drm, "Stride (%u) exceeds hardware max with scaling (%u)\n", 1309 stride, 4096); 1310 return -EINVAL; 1311 } 1312 1313 return 0; 1314 } 1315 1316 static int 1317 g4x_sprite_check(struct intel_crtc_state *crtc_state, 1318 struct intel_plane_state *plane_state) 1319 { 1320 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); 1321 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 1322 int min_scale = DRM_PLANE_NO_SCALING; 1323 int max_scale = DRM_PLANE_NO_SCALING; 1324 int ret; 1325 1326 if (g4x_fb_scalable(plane_state->hw.fb)) { 1327 if (DISPLAY_VER(dev_priv) < 7) { 1328 min_scale = 1; 1329 max_scale = 16 << 16; 1330 } else if (IS_IVYBRIDGE(dev_priv)) { 1331 min_scale = 1; 1332 max_scale = 2 << 16; 1333 } 1334 } 1335 1336 ret = intel_atomic_plane_check_clipping(plane_state, crtc_state, 1337 min_scale, max_scale, true); 1338 if (ret) 1339 return ret; 1340 1341 ret = i9xx_check_plane_surface(plane_state); 1342 if (ret) 1343 return ret; 1344 1345 if (!plane_state->uapi.visible) 1346 return 0; 1347 1348 ret = intel_plane_check_src_coordinates(plane_state); 1349 if (ret) 1350 return ret; 1351 1352 ret = g4x_sprite_check_scaling(crtc_state, plane_state); 1353 if (ret) 1354 return ret; 1355 1356 if (DISPLAY_VER(dev_priv) >= 7) 1357 plane_state->ctl = ivb_sprite_ctl(crtc_state, plane_state); 1358 else 1359 plane_state->ctl = g4x_sprite_ctl(crtc_state, plane_state); 1360 1361 return 0; 1362 } 1363 1364 int chv_plane_check_rotation(const struct intel_plane_state *plane_state) 1365 { 1366 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); 1367 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 1368 unsigned int rotation = plane_state->hw.rotation; 1369 1370 /* CHV ignores the mirror bit when the rotate bit is set :( */ 1371 if (IS_CHERRYVIEW(dev_priv) && 1372 rotation & DRM_MODE_ROTATE_180 && 1373 rotation & DRM_MODE_REFLECT_X) { 1374 drm_dbg_kms(&dev_priv->drm, 1375 "Cannot rotate and reflect at the same time\n"); 1376 return -EINVAL; 1377 } 1378 1379 return 0; 1380 } 1381 1382 static int 1383 vlv_sprite_check(struct intel_crtc_state *crtc_state, 1384 struct intel_plane_state *plane_state) 1385 { 1386 int ret; 1387 1388 ret = chv_plane_check_rotation(plane_state); 1389 if (ret) 1390 return ret; 1391 1392 ret = intel_atomic_plane_check_clipping(plane_state, crtc_state, 1393 DRM_PLANE_NO_SCALING, 1394 DRM_PLANE_NO_SCALING, 1395 true); 1396 if (ret) 1397 return ret; 1398 1399 ret = i9xx_check_plane_surface(plane_state); 1400 if (ret) 1401 return ret; 1402 1403 if (!plane_state->uapi.visible) 1404 return 0; 1405 1406 ret = intel_plane_check_src_coordinates(plane_state); 1407 if (ret) 1408 return ret; 1409 1410 plane_state->ctl = vlv_sprite_ctl(crtc_state, plane_state); 1411 1412 return 0; 1413 } 1414 1415 static const u32 g4x_sprite_formats[] = { 1416 DRM_FORMAT_XRGB8888, 1417 DRM_FORMAT_YUYV, 1418 DRM_FORMAT_YVYU, 1419 DRM_FORMAT_UYVY, 1420 DRM_FORMAT_VYUY, 1421 }; 1422 1423 static const u32 snb_sprite_formats[] = { 1424 DRM_FORMAT_XRGB8888, 1425 DRM_FORMAT_XBGR8888, 1426 DRM_FORMAT_XRGB2101010, 1427 DRM_FORMAT_XBGR2101010, 1428 DRM_FORMAT_XRGB16161616F, 1429 DRM_FORMAT_XBGR16161616F, 1430 DRM_FORMAT_YUYV, 1431 DRM_FORMAT_YVYU, 1432 DRM_FORMAT_UYVY, 1433 DRM_FORMAT_VYUY, 1434 }; 1435 1436 static const u32 vlv_sprite_formats[] = { 1437 DRM_FORMAT_C8, 1438 DRM_FORMAT_RGB565, 1439 DRM_FORMAT_XRGB8888, 1440 DRM_FORMAT_XBGR8888, 1441 DRM_FORMAT_ARGB8888, 1442 DRM_FORMAT_ABGR8888, 1443 DRM_FORMAT_XBGR2101010, 1444 DRM_FORMAT_ABGR2101010, 1445 DRM_FORMAT_YUYV, 1446 DRM_FORMAT_YVYU, 1447 DRM_FORMAT_UYVY, 1448 DRM_FORMAT_VYUY, 1449 }; 1450 1451 static const u32 chv_pipe_b_sprite_formats[] = { 1452 DRM_FORMAT_C8, 1453 DRM_FORMAT_RGB565, 1454 DRM_FORMAT_XRGB8888, 1455 DRM_FORMAT_XBGR8888, 1456 DRM_FORMAT_ARGB8888, 1457 DRM_FORMAT_ABGR8888, 1458 DRM_FORMAT_XRGB2101010, 1459 DRM_FORMAT_XBGR2101010, 1460 DRM_FORMAT_ARGB2101010, 1461 DRM_FORMAT_ABGR2101010, 1462 DRM_FORMAT_YUYV, 1463 DRM_FORMAT_YVYU, 1464 DRM_FORMAT_UYVY, 1465 DRM_FORMAT_VYUY, 1466 }; 1467 1468 static bool g4x_sprite_format_mod_supported(struct drm_plane *_plane, 1469 u32 format, u64 modifier) 1470 { 1471 if (!intel_fb_plane_supports_modifier(to_intel_plane(_plane), modifier)) 1472 return false; 1473 1474 switch (format) { 1475 case DRM_FORMAT_XRGB8888: 1476 case DRM_FORMAT_YUYV: 1477 case DRM_FORMAT_YVYU: 1478 case DRM_FORMAT_UYVY: 1479 case DRM_FORMAT_VYUY: 1480 if (modifier == DRM_FORMAT_MOD_LINEAR || 1481 modifier == I915_FORMAT_MOD_X_TILED) 1482 return true; 1483 fallthrough; 1484 default: 1485 return false; 1486 } 1487 } 1488 1489 static bool snb_sprite_format_mod_supported(struct drm_plane *_plane, 1490 u32 format, u64 modifier) 1491 { 1492 if (!intel_fb_plane_supports_modifier(to_intel_plane(_plane), modifier)) 1493 return false; 1494 1495 switch (format) { 1496 case DRM_FORMAT_XRGB8888: 1497 case DRM_FORMAT_XBGR8888: 1498 case DRM_FORMAT_XRGB2101010: 1499 case DRM_FORMAT_XBGR2101010: 1500 case DRM_FORMAT_XRGB16161616F: 1501 case DRM_FORMAT_XBGR16161616F: 1502 case DRM_FORMAT_YUYV: 1503 case DRM_FORMAT_YVYU: 1504 case DRM_FORMAT_UYVY: 1505 case DRM_FORMAT_VYUY: 1506 if (modifier == DRM_FORMAT_MOD_LINEAR || 1507 modifier == I915_FORMAT_MOD_X_TILED) 1508 return true; 1509 fallthrough; 1510 default: 1511 return false; 1512 } 1513 } 1514 1515 static bool vlv_sprite_format_mod_supported(struct drm_plane *_plane, 1516 u32 format, u64 modifier) 1517 { 1518 if (!intel_fb_plane_supports_modifier(to_intel_plane(_plane), modifier)) 1519 return false; 1520 1521 switch (format) { 1522 case DRM_FORMAT_C8: 1523 case DRM_FORMAT_RGB565: 1524 case DRM_FORMAT_ABGR8888: 1525 case DRM_FORMAT_ARGB8888: 1526 case DRM_FORMAT_XBGR8888: 1527 case DRM_FORMAT_XRGB8888: 1528 case DRM_FORMAT_XBGR2101010: 1529 case DRM_FORMAT_ABGR2101010: 1530 case DRM_FORMAT_XRGB2101010: 1531 case DRM_FORMAT_ARGB2101010: 1532 case DRM_FORMAT_YUYV: 1533 case DRM_FORMAT_YVYU: 1534 case DRM_FORMAT_UYVY: 1535 case DRM_FORMAT_VYUY: 1536 if (modifier == DRM_FORMAT_MOD_LINEAR || 1537 modifier == I915_FORMAT_MOD_X_TILED) 1538 return true; 1539 fallthrough; 1540 default: 1541 return false; 1542 } 1543 } 1544 1545 static const struct drm_plane_funcs g4x_sprite_funcs = { 1546 .update_plane = drm_atomic_helper_update_plane, 1547 .disable_plane = drm_atomic_helper_disable_plane, 1548 .destroy = intel_plane_destroy, 1549 .atomic_duplicate_state = intel_plane_duplicate_state, 1550 .atomic_destroy_state = intel_plane_destroy_state, 1551 .format_mod_supported = g4x_sprite_format_mod_supported, 1552 }; 1553 1554 static const struct drm_plane_funcs snb_sprite_funcs = { 1555 .update_plane = drm_atomic_helper_update_plane, 1556 .disable_plane = drm_atomic_helper_disable_plane, 1557 .destroy = intel_plane_destroy, 1558 .atomic_duplicate_state = intel_plane_duplicate_state, 1559 .atomic_destroy_state = intel_plane_destroy_state, 1560 .format_mod_supported = snb_sprite_format_mod_supported, 1561 }; 1562 1563 static const struct drm_plane_funcs vlv_sprite_funcs = { 1564 .update_plane = drm_atomic_helper_update_plane, 1565 .disable_plane = drm_atomic_helper_disable_plane, 1566 .destroy = intel_plane_destroy, 1567 .atomic_duplicate_state = intel_plane_duplicate_state, 1568 .atomic_destroy_state = intel_plane_destroy_state, 1569 .format_mod_supported = vlv_sprite_format_mod_supported, 1570 }; 1571 1572 struct intel_plane * 1573 intel_sprite_plane_create(struct drm_i915_private *dev_priv, 1574 enum pipe pipe, int sprite) 1575 { 1576 struct intel_plane *plane; 1577 const struct drm_plane_funcs *plane_funcs; 1578 unsigned int supported_rotations; 1579 const u64 *modifiers; 1580 const u32 *formats; 1581 int num_formats; 1582 int ret, zpos; 1583 1584 plane = intel_plane_alloc(); 1585 if (IS_ERR(plane)) 1586 return plane; 1587 1588 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { 1589 plane->update_noarm = vlv_sprite_update_noarm; 1590 plane->update_arm = vlv_sprite_update_arm; 1591 plane->disable_arm = vlv_sprite_disable_arm; 1592 plane->get_hw_state = vlv_sprite_get_hw_state; 1593 plane->check_plane = vlv_sprite_check; 1594 plane->max_stride = i965_plane_max_stride; 1595 plane->min_alignment = vlv_sprite_min_alignment; 1596 plane->min_cdclk = vlv_plane_min_cdclk; 1597 1598 if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) { 1599 formats = chv_pipe_b_sprite_formats; 1600 num_formats = ARRAY_SIZE(chv_pipe_b_sprite_formats); 1601 } else { 1602 formats = vlv_sprite_formats; 1603 num_formats = ARRAY_SIZE(vlv_sprite_formats); 1604 } 1605 1606 plane_funcs = &vlv_sprite_funcs; 1607 } else if (DISPLAY_VER(dev_priv) >= 7) { 1608 plane->update_noarm = ivb_sprite_update_noarm; 1609 plane->update_arm = ivb_sprite_update_arm; 1610 plane->disable_arm = ivb_sprite_disable_arm; 1611 plane->get_hw_state = ivb_sprite_get_hw_state; 1612 plane->check_plane = g4x_sprite_check; 1613 1614 if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) { 1615 plane->max_stride = hsw_sprite_max_stride; 1616 plane->min_cdclk = hsw_plane_min_cdclk; 1617 } else { 1618 plane->max_stride = g4x_sprite_max_stride; 1619 plane->min_cdclk = ivb_sprite_min_cdclk; 1620 } 1621 1622 plane->min_alignment = g4x_sprite_min_alignment; 1623 1624 formats = snb_sprite_formats; 1625 num_formats = ARRAY_SIZE(snb_sprite_formats); 1626 1627 plane_funcs = &snb_sprite_funcs; 1628 } else { 1629 plane->update_noarm = g4x_sprite_update_noarm; 1630 plane->update_arm = g4x_sprite_update_arm; 1631 plane->disable_arm = g4x_sprite_disable_arm; 1632 plane->get_hw_state = g4x_sprite_get_hw_state; 1633 plane->check_plane = g4x_sprite_check; 1634 plane->max_stride = g4x_sprite_max_stride; 1635 plane->min_alignment = g4x_sprite_min_alignment; 1636 plane->min_cdclk = g4x_sprite_min_cdclk; 1637 1638 if (IS_SANDYBRIDGE(dev_priv)) { 1639 formats = snb_sprite_formats; 1640 num_formats = ARRAY_SIZE(snb_sprite_formats); 1641 1642 plane_funcs = &snb_sprite_funcs; 1643 } else { 1644 formats = g4x_sprite_formats; 1645 num_formats = ARRAY_SIZE(g4x_sprite_formats); 1646 1647 plane_funcs = &g4x_sprite_funcs; 1648 } 1649 } 1650 1651 if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) { 1652 supported_rotations = 1653 DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180 | 1654 DRM_MODE_REFLECT_X; 1655 } else { 1656 supported_rotations = 1657 DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180; 1658 } 1659 1660 plane->pipe = pipe; 1661 plane->id = PLANE_SPRITE0 + sprite; 1662 plane->frontbuffer_bit = INTEL_FRONTBUFFER(pipe, plane->id); 1663 1664 modifiers = intel_fb_plane_get_modifiers(dev_priv, INTEL_PLANE_CAP_TILING_X); 1665 1666 ret = drm_universal_plane_init(&dev_priv->drm, &plane->base, 1667 0, plane_funcs, 1668 formats, num_formats, modifiers, 1669 DRM_PLANE_TYPE_OVERLAY, 1670 "sprite %c", sprite_name(dev_priv, pipe, sprite)); 1671 kfree(modifiers); 1672 1673 if (ret) 1674 goto fail; 1675 1676 drm_plane_create_rotation_property(&plane->base, 1677 DRM_MODE_ROTATE_0, 1678 supported_rotations); 1679 1680 drm_plane_create_color_properties(&plane->base, 1681 BIT(DRM_COLOR_YCBCR_BT601) | 1682 BIT(DRM_COLOR_YCBCR_BT709), 1683 BIT(DRM_COLOR_YCBCR_LIMITED_RANGE) | 1684 BIT(DRM_COLOR_YCBCR_FULL_RANGE), 1685 DRM_COLOR_YCBCR_BT709, 1686 DRM_COLOR_YCBCR_LIMITED_RANGE); 1687 1688 zpos = sprite + 1; 1689 drm_plane_create_zpos_immutable_property(&plane->base, zpos); 1690 1691 intel_plane_helper_add(plane); 1692 1693 return plane; 1694 1695 fail: 1696 intel_plane_free(plane); 1697 1698 return ERR_PTR(ret); 1699 } 1700