1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2019 Intel Corporation 4 */ 5 6 #include <linux/math.h> 7 8 #include "i915_drv.h" 9 #include "i915_reg.h" 10 #include "intel_ddi.h" 11 #include "intel_ddi_buf_trans.h" 12 #include "intel_de.h" 13 #include "intel_display_types.h" 14 #include "intel_snps_phy.h" 15 #include "intel_snps_phy_regs.h" 16 17 /** 18 * DOC: Synopsis PHY support 19 * 20 * Synopsis PHYs are primarily programmed by looking up magic register values 21 * in tables rather than calculating the necessary values at runtime. 22 * 23 * Of special note is that the SNPS PHYs include a dedicated port PLL, known as 24 * an "MPLLB." The MPLLB replaces the shared DPLL functionality used on other 25 * platforms and must be programming directly during the modeset sequence 26 * since it is not handled by the shared DPLL framework as on other platforms. 27 */ 28 29 void intel_snps_phy_wait_for_calibration(struct drm_i915_private *i915) 30 { 31 enum phy phy; 32 33 for_each_phy_masked(phy, ~0) { 34 if (!intel_phy_is_snps(i915, phy)) 35 continue; 36 37 /* 38 * If calibration does not complete successfully, we'll remember 39 * which phy was affected and skip setup of the corresponding 40 * output later. 41 */ 42 if (intel_de_wait_for_clear(i915, DG2_PHY_MISC(phy), 43 DG2_PHY_DP_TX_ACK_MASK, 25)) 44 i915->display.snps.phy_failed_calibration |= BIT(phy); 45 } 46 } 47 48 void intel_snps_phy_update_psr_power_state(struct intel_encoder *encoder, 49 bool enable) 50 { 51 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 52 enum phy phy = intel_encoder_to_phy(encoder); 53 u32 val; 54 55 if (!intel_encoder_is_snps(encoder)) 56 return; 57 58 val = REG_FIELD_PREP(SNPS_PHY_TX_REQ_LN_DIS_PWR_STATE_PSR, 59 enable ? 2 : 3); 60 intel_de_rmw(i915, SNPS_PHY_TX_REQ(phy), 61 SNPS_PHY_TX_REQ_LN_DIS_PWR_STATE_PSR, val); 62 } 63 64 void intel_snps_phy_set_signal_levels(struct intel_encoder *encoder, 65 const struct intel_crtc_state *crtc_state) 66 { 67 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 68 const struct intel_ddi_buf_trans *trans; 69 enum phy phy = intel_encoder_to_phy(encoder); 70 int n_entries, ln; 71 72 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); 73 if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans)) 74 return; 75 76 for (ln = 0; ln < 4; ln++) { 77 int level = intel_ddi_level(encoder, crtc_state, ln); 78 u32 val = 0; 79 80 val |= REG_FIELD_PREP(SNPS_PHY_TX_EQ_MAIN, trans->entries[level].snps.vswing); 81 val |= REG_FIELD_PREP(SNPS_PHY_TX_EQ_PRE, trans->entries[level].snps.pre_cursor); 82 val |= REG_FIELD_PREP(SNPS_PHY_TX_EQ_POST, trans->entries[level].snps.post_cursor); 83 84 intel_de_write(dev_priv, SNPS_PHY_TX_EQ(ln, phy), val); 85 } 86 } 87 88 /* 89 * Basic DP link rates with 100 MHz reference clock. 90 */ 91 92 static const struct intel_mpllb_state dg2_dp_rbr_100 = { 93 .clock = 162000, 94 .ref_control = 95 REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3), 96 .mpllb_cp = 97 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 4) | 98 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 20) | 99 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 65) | 100 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 127), 101 .mpllb_div = 102 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) | 103 REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 2) | 104 REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) | 105 REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) | 106 REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 2), 107 .mpllb_div2 = 108 REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 2) | 109 REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 226), 110 .mpllb_fracn1 = 111 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) | 112 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) | 113 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 5), 114 .mpllb_fracn2 = 115 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 39321) | 116 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 3), 117 }; 118 119 static const struct intel_mpllb_state dg2_dp_hbr1_100 = { 120 .clock = 270000, 121 .ref_control = 122 REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3), 123 .mpllb_cp = 124 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 4) | 125 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 20) | 126 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 65) | 127 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 127), 128 .mpllb_div = 129 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) | 130 REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 1) | 131 REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) | 132 REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 3), 133 .mpllb_div2 = 134 REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 2) | 135 REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 184), 136 .mpllb_fracn1 = 137 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) | 138 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 1), 139 }; 140 141 static const struct intel_mpllb_state dg2_dp_hbr2_100 = { 142 .clock = 540000, 143 .ref_control = 144 REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3), 145 .mpllb_cp = 146 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 4) | 147 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 20) | 148 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 65) | 149 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 127), 150 .mpllb_div = 151 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) | 152 REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) | 153 REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 3), 154 .mpllb_div2 = 155 REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 2) | 156 REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 184), 157 .mpllb_fracn1 = 158 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) | 159 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 1), 160 }; 161 162 static const struct intel_mpllb_state dg2_dp_hbr3_100 = { 163 .clock = 810000, 164 .ref_control = 165 REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3), 166 .mpllb_cp = 167 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 4) | 168 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 19) | 169 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 65) | 170 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 127), 171 .mpllb_div = 172 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) | 173 REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2), 174 .mpllb_div2 = 175 REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 2) | 176 REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 292), 177 .mpllb_fracn1 = 178 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) | 179 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 1), 180 }; 181 182 static const struct intel_mpllb_state dg2_dp_uhbr10_100 = { 183 .clock = 1000000, 184 .ref_control = 185 REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3), 186 .mpllb_cp = 187 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 4) | 188 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 21) | 189 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 65) | 190 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 127), 191 .mpllb_div = 192 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) | 193 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV_CLK_EN, 1) | 194 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV_MULTIPLIER, 8) | 195 REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) | 196 REG_FIELD_PREP(SNPS_PHY_MPLLB_WORD_DIV2_EN, 1) | 197 REG_FIELD_PREP(SNPS_PHY_MPLLB_DP2_MODE, 1) | 198 REG_FIELD_PREP(SNPS_PHY_MPLLB_SHIM_DIV32_CLK_SEL, 1) | 199 REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2), 200 .mpllb_div2 = 201 REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 2) | 202 REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 368), 203 .mpllb_fracn1 = 204 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) | 205 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 1), 206 207 /* 208 * SSC will be enabled, DP UHBR has a minimum SSC requirement. 209 */ 210 .mpllb_sscen = 211 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_EN, 1) | 212 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_PEAK, 58982), 213 .mpllb_sscstep = 214 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_STEPSIZE, 76101), 215 }; 216 217 static const struct intel_mpllb_state dg2_dp_uhbr13_100 = { 218 .clock = 1350000, 219 .ref_control = 220 REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3), 221 .mpllb_cp = 222 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 5) | 223 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 45) | 224 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 65) | 225 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 127), 226 .mpllb_div = 227 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) | 228 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV_CLK_EN, 1) | 229 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV_MULTIPLIER, 8) | 230 REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) | 231 REG_FIELD_PREP(SNPS_PHY_MPLLB_WORD_DIV2_EN, 1) | 232 REG_FIELD_PREP(SNPS_PHY_MPLLB_DP2_MODE, 1) | 233 REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 3), 234 .mpllb_div2 = 235 REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 2) | 236 REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 508), 237 .mpllb_fracn1 = 238 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) | 239 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 1), 240 241 /* 242 * SSC will be enabled, DP UHBR has a minimum SSC requirement. 243 */ 244 .mpllb_sscen = 245 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_EN, 1) | 246 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_PEAK, 79626), 247 .mpllb_sscstep = 248 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_STEPSIZE, 102737), 249 }; 250 251 static const struct intel_mpllb_state * const dg2_dp_100_tables[] = { 252 &dg2_dp_rbr_100, 253 &dg2_dp_hbr1_100, 254 &dg2_dp_hbr2_100, 255 &dg2_dp_hbr3_100, 256 &dg2_dp_uhbr10_100, 257 &dg2_dp_uhbr13_100, 258 NULL, 259 }; 260 261 /* 262 * eDP link rates with 100 MHz reference clock. 263 */ 264 265 static const struct intel_mpllb_state dg2_edp_r216 = { 266 .clock = 216000, 267 .ref_control = 268 REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3), 269 .mpllb_cp = 270 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 4) | 271 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 19) | 272 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 65) | 273 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 127), 274 .mpllb_div = 275 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) | 276 REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 2) | 277 REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) | 278 REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2), 279 .mpllb_div2 = 280 REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 2) | 281 REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 312), 282 .mpllb_fracn1 = 283 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) | 284 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) | 285 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 5), 286 .mpllb_fracn2 = 287 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 52428) | 288 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 4), 289 .mpllb_sscen = 290 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_EN, 1) | 291 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_PEAK, 50961), 292 .mpllb_sscstep = 293 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_STEPSIZE, 65752), 294 }; 295 296 static const struct intel_mpllb_state dg2_edp_r243 = { 297 .clock = 243000, 298 .ref_control = 299 REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3), 300 .mpllb_cp = 301 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 4) | 302 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 20) | 303 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 65) | 304 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 127), 305 .mpllb_div = 306 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) | 307 REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 2) | 308 REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) | 309 REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2), 310 .mpllb_div2 = 311 REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 2) | 312 REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 356), 313 .mpllb_fracn1 = 314 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) | 315 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) | 316 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 5), 317 .mpllb_fracn2 = 318 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 26214) | 319 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 2), 320 .mpllb_sscen = 321 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_EN, 1) | 322 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_PEAK, 57331), 323 .mpllb_sscstep = 324 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_STEPSIZE, 73971), 325 }; 326 327 static const struct intel_mpllb_state dg2_edp_r324 = { 328 .clock = 324000, 329 .ref_control = 330 REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3), 331 .mpllb_cp = 332 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 4) | 333 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 20) | 334 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 65) | 335 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 127), 336 .mpllb_div = 337 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) | 338 REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 1) | 339 REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) | 340 REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) | 341 REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 2), 342 .mpllb_div2 = 343 REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 2) | 344 REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 226), 345 .mpllb_fracn1 = 346 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) | 347 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) | 348 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 5), 349 .mpllb_fracn2 = 350 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 39321) | 351 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 3), 352 .mpllb_sscen = 353 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_EN, 1) | 354 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_PEAK, 38221), 355 .mpllb_sscstep = 356 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_STEPSIZE, 49314), 357 }; 358 359 static const struct intel_mpllb_state dg2_edp_r432 = { 360 .clock = 432000, 361 .ref_control = 362 REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3), 363 .mpllb_cp = 364 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 4) | 365 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 19) | 366 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 65) | 367 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 127), 368 .mpllb_div = 369 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) | 370 REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 1) | 371 REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) | 372 REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2), 373 .mpllb_div2 = 374 REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 2) | 375 REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 312), 376 .mpllb_fracn1 = 377 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) | 378 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) | 379 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 5), 380 .mpllb_fracn2 = 381 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 52428) | 382 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 4), 383 .mpllb_sscen = 384 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_EN, 1) | 385 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_PEAK, 50961), 386 .mpllb_sscstep = 387 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_STEPSIZE, 65752), 388 }; 389 390 static const struct intel_mpllb_state * const dg2_edp_tables[] = { 391 &dg2_dp_rbr_100, 392 &dg2_edp_r216, 393 &dg2_edp_r243, 394 &dg2_dp_hbr1_100, 395 &dg2_edp_r324, 396 &dg2_edp_r432, 397 &dg2_dp_hbr2_100, 398 &dg2_dp_hbr3_100, 399 NULL, 400 }; 401 402 /* 403 * HDMI link rates with 100 MHz reference clock. 404 */ 405 406 static const struct intel_mpllb_state dg2_hdmi_25_175 = { 407 .clock = 25175, 408 .ref_control = 409 REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3), 410 .mpllb_cp = 411 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 5) | 412 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 15) | 413 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) | 414 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124), 415 .mpllb_div = 416 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) | 417 REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 5) | 418 REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) | 419 REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2), 420 .mpllb_div2 = 421 REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) | 422 REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 128) | 423 REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1), 424 .mpllb_fracn1 = 425 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) | 426 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) | 427 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 143), 428 .mpllb_fracn2 = 429 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 36663) | 430 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 71), 431 .mpllb_sscen = 432 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1), 433 }; 434 435 static const struct intel_mpllb_state dg2_hdmi_27_0 = { 436 .clock = 27000, 437 .ref_control = 438 REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3), 439 .mpllb_cp = 440 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 5) | 441 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 15) | 442 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) | 443 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124), 444 .mpllb_div = 445 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) | 446 REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 5) | 447 REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) | 448 REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2), 449 .mpllb_div2 = 450 REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) | 451 REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 140) | 452 REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1), 453 .mpllb_fracn1 = 454 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) | 455 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) | 456 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 5), 457 .mpllb_fracn2 = 458 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 26214) | 459 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 2), 460 .mpllb_sscen = 461 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1), 462 }; 463 464 static const struct intel_mpllb_state dg2_hdmi_74_25 = { 465 .clock = 74250, 466 .ref_control = 467 REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3), 468 .mpllb_cp = 469 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 4) | 470 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 15) | 471 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) | 472 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124), 473 .mpllb_div = 474 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) | 475 REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 3) | 476 REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) | 477 REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) | 478 REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 3), 479 .mpllb_div2 = 480 REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) | 481 REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 86) | 482 REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1), 483 .mpllb_fracn1 = 484 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) | 485 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) | 486 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 5), 487 .mpllb_fracn2 = 488 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 26214) | 489 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 2), 490 .mpllb_sscen = 491 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1), 492 }; 493 494 static const struct intel_mpllb_state dg2_hdmi_148_5 = { 495 .clock = 148500, 496 .ref_control = 497 REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3), 498 .mpllb_cp = 499 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 4) | 500 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 15) | 501 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) | 502 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124), 503 .mpllb_div = 504 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) | 505 REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 2) | 506 REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) | 507 REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) | 508 REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 3), 509 .mpllb_div2 = 510 REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) | 511 REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 86) | 512 REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1), 513 .mpllb_fracn1 = 514 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) | 515 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) | 516 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 5), 517 .mpllb_fracn2 = 518 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 26214) | 519 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 2), 520 .mpllb_sscen = 521 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1), 522 }; 523 524 /* values in the below table are calculted using the algo */ 525 static const struct intel_mpllb_state dg2_hdmi_25200 = { 526 .clock = 25200, 527 .ref_control = 528 REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3), 529 .mpllb_cp = 530 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 7) | 531 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) | 532 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) | 533 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124), 534 .mpllb_div = 535 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) | 536 REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 5) | 537 REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) | 538 REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) | 539 REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 0), 540 .mpllb_div2 = 541 REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) | 542 REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 128) | 543 REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1), 544 .mpllb_fracn1 = 545 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) | 546 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) | 547 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535), 548 .mpllb_fracn2 = 549 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 41943) | 550 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 2621), 551 .mpllb_sscen = 552 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1), 553 }; 554 555 static const struct intel_mpllb_state dg2_hdmi_27027 = { 556 .clock = 27027, 557 .ref_control = 558 REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3), 559 .mpllb_cp = 560 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) | 561 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) | 562 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) | 563 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124), 564 .mpllb_div = 565 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) | 566 REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 5) | 567 REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) | 568 REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) | 569 REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 0), 570 .mpllb_div2 = 571 REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) | 572 REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 140) | 573 REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1), 574 .mpllb_fracn1 = 575 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) | 576 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) | 577 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535), 578 .mpllb_fracn2 = 579 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 31876) | 580 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 46555), 581 .mpllb_sscen = 582 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1), 583 }; 584 585 static const struct intel_mpllb_state dg2_hdmi_28320 = { 586 .clock = 28320, 587 .ref_control = 588 REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3), 589 .mpllb_cp = 590 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) | 591 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) | 592 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) | 593 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124), 594 .mpllb_div = 595 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) | 596 REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 5) | 597 REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) | 598 REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) | 599 REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 0), 600 .mpllb_div2 = 601 REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) | 602 REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 148) | 603 REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1), 604 .mpllb_fracn1 = 605 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) | 606 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) | 607 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535), 608 .mpllb_fracn2 = 609 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 40894) | 610 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 30408), 611 .mpllb_sscen = 612 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1), 613 }; 614 615 static const struct intel_mpllb_state dg2_hdmi_30240 = { 616 .clock = 30240, 617 .ref_control = 618 REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3), 619 .mpllb_cp = 620 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) | 621 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) | 622 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) | 623 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124), 624 .mpllb_div = 625 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) | 626 REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 5) | 627 REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) | 628 REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) | 629 REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 0), 630 .mpllb_div2 = 631 REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) | 632 REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 160) | 633 REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1), 634 .mpllb_fracn1 = 635 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) | 636 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) | 637 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535), 638 .mpllb_fracn2 = 639 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 50331) | 640 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 42466), 641 .mpllb_sscen = 642 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1), 643 }; 644 645 static const struct intel_mpllb_state dg2_hdmi_31500 = { 646 .clock = 31500, 647 .ref_control = 648 REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3), 649 .mpllb_cp = 650 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 7) | 651 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) | 652 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) | 653 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124), 654 .mpllb_div = 655 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) | 656 REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 4) | 657 REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) | 658 REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) | 659 REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 3), 660 .mpllb_div2 = 661 REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) | 662 REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 68) | 663 REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1), 664 .mpllb_fracn1 = 665 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) | 666 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) | 667 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535), 668 .mpllb_fracn2 = 669 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 26214) | 670 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 26214), 671 .mpllb_sscen = 672 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1), 673 }; 674 675 static const struct intel_mpllb_state dg2_hdmi_36000 = { 676 .clock = 36000, 677 .ref_control = 678 REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3), 679 .mpllb_cp = 680 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) | 681 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) | 682 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) | 683 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124), 684 .mpllb_div = 685 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) | 686 REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 4) | 687 REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) | 688 REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) | 689 REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 3), 690 .mpllb_div2 = 691 REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) | 692 REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 82) | 693 REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1), 694 .mpllb_fracn1 = 695 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) | 696 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) | 697 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535), 698 .mpllb_fracn2 = 699 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 39321) | 700 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 39320), 701 .mpllb_sscen = 702 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1), 703 }; 704 705 static const struct intel_mpllb_state dg2_hdmi_40000 = { 706 .clock = 40000, 707 .ref_control = 708 REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3), 709 .mpllb_cp = 710 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) | 711 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) | 712 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) | 713 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124), 714 .mpllb_div = 715 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) | 716 REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 4) | 717 REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 0) | 718 REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) | 719 REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 2), 720 .mpllb_div2 = 721 REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) | 722 REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 96) | 723 REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1), 724 .mpllb_fracn1 = 725 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) | 726 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 0) | 727 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535), 728 .mpllb_fracn2 = 729 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 0) | 730 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 0), 731 .mpllb_sscen = 732 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1), 733 }; 734 735 static const struct intel_mpllb_state dg2_hdmi_49500 = { 736 .clock = 49500, 737 .ref_control = 738 REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3), 739 .mpllb_cp = 740 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) | 741 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) | 742 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) | 743 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124), 744 .mpllb_div = 745 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) | 746 REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 4) | 747 REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) | 748 REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) | 749 REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 1), 750 .mpllb_div2 = 751 REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) | 752 REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 126) | 753 REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1), 754 .mpllb_fracn1 = 755 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) | 756 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) | 757 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535), 758 .mpllb_fracn2 = 759 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 13107) | 760 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 13107), 761 .mpllb_sscen = 762 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1), 763 }; 764 765 static const struct intel_mpllb_state dg2_hdmi_50000 = { 766 .clock = 50000, 767 .ref_control = 768 REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3), 769 .mpllb_cp = 770 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) | 771 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) | 772 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) | 773 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124), 774 .mpllb_div = 775 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) | 776 REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 4) | 777 REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 0) | 778 REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) | 779 REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 1), 780 .mpllb_div2 = 781 REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) | 782 REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 128) | 783 REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1), 784 .mpllb_fracn1 = 785 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) | 786 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 0) | 787 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535), 788 .mpllb_fracn2 = 789 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 0) | 790 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 0), 791 .mpllb_sscen = 792 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1), 793 }; 794 795 static const struct intel_mpllb_state dg2_hdmi_57284 = { 796 .clock = 57284, 797 .ref_control = 798 REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3), 799 .mpllb_cp = 800 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) | 801 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) | 802 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) | 803 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124), 804 .mpllb_div = 805 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) | 806 REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 4) | 807 REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) | 808 REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) | 809 REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 0), 810 .mpllb_div2 = 811 REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) | 812 REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 150) | 813 REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1), 814 .mpllb_fracn1 = 815 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) | 816 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) | 817 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535), 818 .mpllb_fracn2 = 819 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 42886) | 820 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 49701), 821 .mpllb_sscen = 822 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1), 823 }; 824 825 static const struct intel_mpllb_state dg2_hdmi_58000 = { 826 .clock = 58000, 827 .ref_control = 828 REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3), 829 .mpllb_cp = 830 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) | 831 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) | 832 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) | 833 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124), 834 .mpllb_div = 835 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) | 836 REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 4) | 837 REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) | 838 REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) | 839 REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 0), 840 .mpllb_div2 = 841 REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) | 842 REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 152) | 843 REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1), 844 .mpllb_fracn1 = 845 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) | 846 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) | 847 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535), 848 .mpllb_fracn2 = 849 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 52428) | 850 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 52427), 851 .mpllb_sscen = 852 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1), 853 }; 854 855 static const struct intel_mpllb_state dg2_hdmi_65000 = { 856 .clock = 65000, 857 .ref_control = 858 REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3), 859 .mpllb_cp = 860 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 7) | 861 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) | 862 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) | 863 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124), 864 .mpllb_div = 865 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) | 866 REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 3) | 867 REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 0) | 868 REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) | 869 REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 3), 870 .mpllb_div2 = 871 REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) | 872 REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 72) | 873 REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1), 874 .mpllb_fracn1 = 875 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) | 876 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 0) | 877 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535), 878 .mpllb_fracn2 = 879 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 0) | 880 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 0), 881 .mpllb_sscen = 882 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1), 883 }; 884 885 static const struct intel_mpllb_state dg2_hdmi_71000 = { 886 .clock = 71000, 887 .ref_control = 888 REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3), 889 .mpllb_cp = 890 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) | 891 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) | 892 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) | 893 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124), 894 .mpllb_div = 895 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) | 896 REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 3) | 897 REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) | 898 REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) | 899 REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 3), 900 .mpllb_div2 = 901 REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) | 902 REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 80) | 903 REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1), 904 .mpllb_fracn1 = 905 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) | 906 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) | 907 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535), 908 .mpllb_fracn2 = 909 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 52428) | 910 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 52427), 911 .mpllb_sscen = 912 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1), 913 }; 914 915 static const struct intel_mpllb_state dg2_hdmi_74176 = { 916 .clock = 74176, 917 .ref_control = 918 REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3), 919 .mpllb_cp = 920 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) | 921 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) | 922 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) | 923 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124), 924 .mpllb_div = 925 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) | 926 REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 3) | 927 REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) | 928 REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) | 929 REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 3), 930 .mpllb_div2 = 931 REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) | 932 REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 86) | 933 REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1), 934 .mpllb_fracn1 = 935 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) | 936 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) | 937 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535), 938 .mpllb_fracn2 = 939 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 22334) | 940 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 43829), 941 .mpllb_sscen = 942 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1), 943 }; 944 945 static const struct intel_mpllb_state dg2_hdmi_75000 = { 946 .clock = 75000, 947 .ref_control = 948 REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3), 949 .mpllb_cp = 950 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) | 951 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) | 952 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) | 953 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124), 954 .mpllb_div = 955 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) | 956 REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 3) | 957 REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 0) | 958 REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) | 959 REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 3), 960 .mpllb_div2 = 961 REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) | 962 REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 88) | 963 REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1), 964 .mpllb_fracn1 = 965 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) | 966 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 0) | 967 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535), 968 .mpllb_fracn2 = 969 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 0) | 970 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 0), 971 .mpllb_sscen = 972 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1), 973 }; 974 975 static const struct intel_mpllb_state dg2_hdmi_78750 = { 976 .clock = 78750, 977 .ref_control = 978 REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3), 979 .mpllb_cp = 980 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) | 981 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) | 982 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) | 983 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124), 984 .mpllb_div = 985 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) | 986 REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 3) | 987 REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 0) | 988 REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) | 989 REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 2), 990 .mpllb_div2 = 991 REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) | 992 REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 94) | 993 REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1), 994 .mpllb_fracn1 = 995 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) | 996 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 0) | 997 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535), 998 .mpllb_fracn2 = 999 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 0) | 1000 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 0), 1001 .mpllb_sscen = 1002 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1), 1003 }; 1004 1005 static const struct intel_mpllb_state dg2_hdmi_85500 = { 1006 .clock = 85500, 1007 .ref_control = 1008 REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3), 1009 .mpllb_cp = 1010 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) | 1011 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) | 1012 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) | 1013 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124), 1014 .mpllb_div = 1015 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) | 1016 REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 3) | 1017 REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) | 1018 REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) | 1019 REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 2), 1020 .mpllb_div2 = 1021 REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) | 1022 REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 104) | 1023 REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1), 1024 .mpllb_fracn1 = 1025 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) | 1026 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) | 1027 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535), 1028 .mpllb_fracn2 = 1029 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 26214) | 1030 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 26214), 1031 .mpllb_sscen = 1032 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1), 1033 }; 1034 1035 static const struct intel_mpllb_state dg2_hdmi_88750 = { 1036 .clock = 88750, 1037 .ref_control = 1038 REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3), 1039 .mpllb_cp = 1040 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 7) | 1041 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 15) | 1042 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) | 1043 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124), 1044 .mpllb_div = 1045 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) | 1046 REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 3) | 1047 REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 0) | 1048 REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) | 1049 REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 1), 1050 .mpllb_div2 = 1051 REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) | 1052 REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 110) | 1053 REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1), 1054 .mpllb_fracn1 = 1055 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) | 1056 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 0) | 1057 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535), 1058 .mpllb_fracn2 = 1059 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 0) | 1060 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 0), 1061 .mpllb_sscen = 1062 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1), 1063 }; 1064 1065 static const struct intel_mpllb_state dg2_hdmi_106500 = { 1066 .clock = 106500, 1067 .ref_control = 1068 REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3), 1069 .mpllb_cp = 1070 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) | 1071 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) | 1072 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) | 1073 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124), 1074 .mpllb_div = 1075 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) | 1076 REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 3) | 1077 REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) | 1078 REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) | 1079 REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 0), 1080 .mpllb_div2 = 1081 REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) | 1082 REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 138) | 1083 REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1), 1084 .mpllb_fracn1 = 1085 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) | 1086 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) | 1087 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535), 1088 .mpllb_fracn2 = 1089 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 13107) | 1090 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 13107), 1091 .mpllb_sscen = 1092 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1), 1093 }; 1094 1095 static const struct intel_mpllb_state dg2_hdmi_108000 = { 1096 .clock = 108000, 1097 .ref_control = 1098 REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3), 1099 .mpllb_cp = 1100 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) | 1101 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) | 1102 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) | 1103 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124), 1104 .mpllb_div = 1105 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) | 1106 REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 3) | 1107 REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) | 1108 REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) | 1109 REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 0), 1110 .mpllb_div2 = 1111 REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) | 1112 REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 140) | 1113 REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1), 1114 .mpllb_fracn1 = 1115 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) | 1116 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) | 1117 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535), 1118 .mpllb_fracn2 = 1119 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 26214) | 1120 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 26214), 1121 .mpllb_sscen = 1122 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1), 1123 }; 1124 1125 static const struct intel_mpllb_state dg2_hdmi_115500 = { 1126 .clock = 115500, 1127 .ref_control = 1128 REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3), 1129 .mpllb_cp = 1130 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) | 1131 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) | 1132 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) | 1133 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124), 1134 .mpllb_div = 1135 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) | 1136 REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 3) | 1137 REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) | 1138 REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) | 1139 REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 0), 1140 .mpllb_div2 = 1141 REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) | 1142 REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 152) | 1143 REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1), 1144 .mpllb_fracn1 = 1145 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) | 1146 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) | 1147 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535), 1148 .mpllb_fracn2 = 1149 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 26214) | 1150 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 26214), 1151 .mpllb_sscen = 1152 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1), 1153 }; 1154 1155 static const struct intel_mpllb_state dg2_hdmi_119000 = { 1156 .clock = 119000, 1157 .ref_control = 1158 REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3), 1159 .mpllb_cp = 1160 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) | 1161 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) | 1162 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) | 1163 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124), 1164 .mpllb_div = 1165 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) | 1166 REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 3) | 1167 REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) | 1168 REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) | 1169 REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 0), 1170 .mpllb_div2 = 1171 REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) | 1172 REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 158) | 1173 REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1), 1174 .mpllb_fracn1 = 1175 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) | 1176 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) | 1177 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535), 1178 .mpllb_fracn2 = 1179 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 13107) | 1180 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 13107), 1181 .mpllb_sscen = 1182 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1), 1183 }; 1184 1185 static const struct intel_mpllb_state dg2_hdmi_135000 = { 1186 .clock = 135000, 1187 .ref_control = 1188 REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3), 1189 .mpllb_cp = 1190 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 7) | 1191 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 15) | 1192 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) | 1193 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124), 1194 .mpllb_div = 1195 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) | 1196 REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 2) | 1197 REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 0) | 1198 REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) | 1199 REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 3), 1200 .mpllb_div2 = 1201 REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) | 1202 REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 76) | 1203 REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1), 1204 .mpllb_fracn1 = 1205 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) | 1206 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 0) | 1207 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535), 1208 .mpllb_fracn2 = 1209 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 0) | 1210 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 0), 1211 .mpllb_sscen = 1212 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1), 1213 }; 1214 1215 static const struct intel_mpllb_state dg2_hdmi_138500 = { 1216 .clock = 138500, 1217 .ref_control = 1218 REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3), 1219 .mpllb_cp = 1220 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) | 1221 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) | 1222 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) | 1223 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124), 1224 .mpllb_div = 1225 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) | 1226 REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 2) | 1227 REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) | 1228 REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) | 1229 REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 3), 1230 .mpllb_div2 = 1231 REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) | 1232 REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 78) | 1233 REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1), 1234 .mpllb_fracn1 = 1235 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) | 1236 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) | 1237 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535), 1238 .mpllb_fracn2 = 1239 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 26214) | 1240 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 26214), 1241 .mpllb_sscen = 1242 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1), 1243 }; 1244 1245 static const struct intel_mpllb_state dg2_hdmi_147160 = { 1246 .clock = 147160, 1247 .ref_control = 1248 REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3), 1249 .mpllb_cp = 1250 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) | 1251 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) | 1252 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) | 1253 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124), 1254 .mpllb_div = 1255 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) | 1256 REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 2) | 1257 REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) | 1258 REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) | 1259 REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 3), 1260 .mpllb_div2 = 1261 REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) | 1262 REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 84) | 1263 REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1), 1264 .mpllb_fracn1 = 1265 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) | 1266 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) | 1267 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535), 1268 .mpllb_fracn2 = 1269 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 56623) | 1270 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 6815), 1271 .mpllb_sscen = 1272 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1), 1273 }; 1274 1275 static const struct intel_mpllb_state dg2_hdmi_148352 = { 1276 .clock = 148352, 1277 .ref_control = 1278 REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3), 1279 .mpllb_cp = 1280 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) | 1281 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) | 1282 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) | 1283 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124), 1284 .mpllb_div = 1285 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) | 1286 REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 2) | 1287 REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) | 1288 REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) | 1289 REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 3), 1290 .mpllb_div2 = 1291 REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) | 1292 REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 86) | 1293 REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1), 1294 .mpllb_fracn1 = 1295 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) | 1296 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) | 1297 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535), 1298 .mpllb_fracn2 = 1299 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 22334) | 1300 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 43829), 1301 .mpllb_sscen = 1302 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1), 1303 }; 1304 1305 static const struct intel_mpllb_state dg2_hdmi_154000 = { 1306 .clock = 154000, 1307 .ref_control = 1308 REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3), 1309 .mpllb_cp = 1310 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) | 1311 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 13) | 1312 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) | 1313 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124), 1314 .mpllb_div = 1315 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) | 1316 REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 2) | 1317 REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) | 1318 REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) | 1319 REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 2), 1320 .mpllb_div2 = 1321 REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) | 1322 REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 90) | 1323 REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1), 1324 .mpllb_fracn1 = 1325 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) | 1326 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) | 1327 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535), 1328 .mpllb_fracn2 = 1329 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 39321) | 1330 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 39320), 1331 .mpllb_sscen = 1332 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1), 1333 }; 1334 1335 static const struct intel_mpllb_state dg2_hdmi_162000 = { 1336 .clock = 162000, 1337 .ref_control = 1338 REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3), 1339 .mpllb_cp = 1340 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) | 1341 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) | 1342 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) | 1343 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124), 1344 .mpllb_div = 1345 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) | 1346 REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 2) | 1347 REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) | 1348 REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) | 1349 REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 2), 1350 .mpllb_div2 = 1351 REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) | 1352 REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 96) | 1353 REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1), 1354 .mpllb_fracn1 = 1355 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) | 1356 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) | 1357 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535), 1358 .mpllb_fracn2 = 1359 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 52428) | 1360 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 52427), 1361 .mpllb_sscen = 1362 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1), 1363 }; 1364 1365 static const struct intel_mpllb_state dg2_hdmi_209800 = { 1366 .clock = 209800, 1367 .ref_control = 1368 REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3), 1369 .mpllb_cp = 1370 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 7) | 1371 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) | 1372 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) | 1373 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124), 1374 .mpllb_div = 1375 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) | 1376 REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 2) | 1377 REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) | 1378 REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) | 1379 REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 0), 1380 .mpllb_div2 = 1381 REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) | 1382 REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 134) | 1383 REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1), 1384 .mpllb_fracn1 = 1385 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) | 1386 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) | 1387 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535), 1388 .mpllb_fracn2 = 1389 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 60293) | 1390 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 7864), 1391 .mpllb_sscen = 1392 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1), 1393 }; 1394 1395 static const struct intel_mpllb_state dg2_hdmi_262750 = { 1396 .clock = 262750, 1397 .ref_control = 1398 REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3), 1399 .mpllb_cp = 1400 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 7) | 1401 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) | 1402 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) | 1403 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124), 1404 .mpllb_div = 1405 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) | 1406 REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 1) | 1407 REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) | 1408 REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) | 1409 REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 3), 1410 .mpllb_div2 = 1411 REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) | 1412 REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 72) | 1413 REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1), 1414 .mpllb_fracn1 = 1415 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) | 1416 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) | 1417 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535), 1418 .mpllb_fracn2 = 1419 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 36044) | 1420 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 52427), 1421 .mpllb_sscen = 1422 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1), 1423 }; 1424 1425 static const struct intel_mpllb_state dg2_hdmi_267300 = { 1426 .clock = 267300, 1427 .ref_control = 1428 REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3), 1429 .mpllb_cp = 1430 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 7) | 1431 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) | 1432 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) | 1433 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124), 1434 .mpllb_div = 1435 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) | 1436 REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 1) | 1437 REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) | 1438 REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) | 1439 REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 3), 1440 .mpllb_div2 = 1441 REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) | 1442 REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 74) | 1443 REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1), 1444 .mpllb_fracn1 = 1445 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) | 1446 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) | 1447 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535), 1448 .mpllb_fracn2 = 1449 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 30146) | 1450 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 36699), 1451 .mpllb_sscen = 1452 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1), 1453 }; 1454 1455 static const struct intel_mpllb_state dg2_hdmi_268500 = { 1456 .clock = 268500, 1457 .ref_control = 1458 REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3), 1459 .mpllb_cp = 1460 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 7) | 1461 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) | 1462 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) | 1463 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124), 1464 .mpllb_div = 1465 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) | 1466 REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 1) | 1467 REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) | 1468 REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) | 1469 REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 3), 1470 .mpllb_div2 = 1471 REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) | 1472 REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 74) | 1473 REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1), 1474 .mpllb_fracn1 = 1475 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) | 1476 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) | 1477 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535), 1478 .mpllb_fracn2 = 1479 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 45875) | 1480 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 13107), 1481 .mpllb_sscen = 1482 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1), 1483 }; 1484 1485 static const struct intel_mpllb_state dg2_hdmi_296703 = { 1486 .clock = 296703, 1487 .ref_control = 1488 REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3), 1489 .mpllb_cp = 1490 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) | 1491 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) | 1492 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) | 1493 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124), 1494 .mpllb_div = 1495 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) | 1496 REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 1) | 1497 REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) | 1498 REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) | 1499 REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 3), 1500 .mpllb_div2 = 1501 REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) | 1502 REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 86) | 1503 REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1), 1504 .mpllb_fracn1 = 1505 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) | 1506 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) | 1507 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535), 1508 .mpllb_fracn2 = 1509 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 22321) | 1510 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 36804), 1511 .mpllb_sscen = 1512 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1), 1513 }; 1514 1515 static const struct intel_mpllb_state dg2_hdmi_241500 = { 1516 .clock = 241500, 1517 .ref_control = 1518 REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3), 1519 .mpllb_cp = 1520 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) | 1521 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) | 1522 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) | 1523 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124), 1524 .mpllb_div = 1525 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) | 1526 REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 2) | 1527 REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) | 1528 REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) | 1529 REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 0), 1530 .mpllb_div2 = 1531 REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) | 1532 REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 160) | 1533 REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1), 1534 .mpllb_fracn1 = 1535 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) | 1536 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) | 1537 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535), 1538 .mpllb_fracn2 = 1539 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 39321) | 1540 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 39320), 1541 .mpllb_sscen = 1542 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1), 1543 }; 1544 1545 static const struct intel_mpllb_state dg2_hdmi_319890 = { 1546 .clock = 319890, 1547 .ref_control = 1548 REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3), 1549 .mpllb_cp = 1550 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) | 1551 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) | 1552 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) | 1553 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124), 1554 .mpllb_div = 1555 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) | 1556 REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 1) | 1557 REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) | 1558 REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) | 1559 REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 2), 1560 .mpllb_div2 = 1561 REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) | 1562 REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 94) | 1563 REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1), 1564 .mpllb_fracn1 = 1565 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) | 1566 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) | 1567 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535), 1568 .mpllb_fracn2 = 1569 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 64094) | 1570 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 13631), 1571 .mpllb_sscen = 1572 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1), 1573 }; 1574 1575 static const struct intel_mpllb_state dg2_hdmi_497750 = { 1576 .clock = 497750, 1577 .ref_control = 1578 REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3), 1579 .mpllb_cp = 1580 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) | 1581 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 15) | 1582 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) | 1583 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124), 1584 .mpllb_div = 1585 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) | 1586 REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 1) | 1587 REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) | 1588 REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) | 1589 REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 0), 1590 .mpllb_div2 = 1591 REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) | 1592 REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 166) | 1593 REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1), 1594 .mpllb_fracn1 = 1595 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) | 1596 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) | 1597 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535), 1598 .mpllb_fracn2 = 1599 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 36044) | 1600 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 52427), 1601 .mpllb_sscen = 1602 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1), 1603 }; 1604 1605 static const struct intel_mpllb_state dg2_hdmi_592000 = { 1606 .clock = 592000, 1607 .ref_control = 1608 REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3), 1609 .mpllb_cp = 1610 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) | 1611 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) | 1612 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) | 1613 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124), 1614 .mpllb_div = 1615 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) | 1616 REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 0) | 1617 REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) | 1618 REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) | 1619 REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 3), 1620 .mpllb_div2 = 1621 REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) | 1622 REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 86) | 1623 REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1), 1624 .mpllb_fracn1 = 1625 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) | 1626 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) | 1627 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535), 1628 .mpllb_fracn2 = 1629 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 13107) | 1630 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 13107), 1631 .mpllb_sscen = 1632 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1), 1633 }; 1634 1635 static const struct intel_mpllb_state dg2_hdmi_593407 = { 1636 .clock = 593407, 1637 .ref_control = 1638 REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3), 1639 .mpllb_cp = 1640 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) | 1641 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) | 1642 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) | 1643 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124), 1644 .mpllb_div = 1645 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) | 1646 REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 0) | 1647 REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) | 1648 REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) | 1649 REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 3), 1650 .mpllb_div2 = 1651 REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) | 1652 REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 86) | 1653 REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1), 1654 .mpllb_fracn1 = 1655 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) | 1656 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) | 1657 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535), 1658 .mpllb_fracn2 = 1659 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 22328) | 1660 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 7549), 1661 .mpllb_sscen = 1662 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1), 1663 }; 1664 1665 static const struct intel_mpllb_state dg2_hdmi_297 = { 1666 .clock = 297000, 1667 .ref_control = 1668 REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3), 1669 .mpllb_cp = 1670 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) | 1671 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) | 1672 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) | 1673 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124), 1674 .mpllb_div = 1675 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) | 1676 REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 1) | 1677 REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) | 1678 REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) | 1679 REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 3), 1680 .mpllb_div2 = 1681 REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) | 1682 REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 86) | 1683 REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1), 1684 .mpllb_fracn1 = 1685 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) | 1686 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) | 1687 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535), 1688 .mpllb_fracn2 = 1689 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 26214) | 1690 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 26214), 1691 .mpllb_sscen = 1692 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1), 1693 }; 1694 1695 static const struct intel_mpllb_state dg2_hdmi_594 = { 1696 .clock = 594000, 1697 .ref_control = 1698 REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3), 1699 .mpllb_cp = 1700 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 4) | 1701 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 15) | 1702 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) | 1703 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124), 1704 .mpllb_div = 1705 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) | 1706 REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) | 1707 REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) | 1708 REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 3), 1709 .mpllb_div2 = 1710 REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) | 1711 REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 86) | 1712 REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1), 1713 .mpllb_fracn1 = 1714 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) | 1715 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) | 1716 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 5), 1717 .mpllb_fracn2 = 1718 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 26214) | 1719 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 2), 1720 .mpllb_sscen = 1721 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1), 1722 }; 1723 1724 static const struct intel_mpllb_state * const dg2_hdmi_tables[] = { 1725 &dg2_hdmi_25_175, 1726 &dg2_hdmi_27_0, 1727 &dg2_hdmi_74_25, 1728 &dg2_hdmi_148_5, 1729 &dg2_hdmi_297, 1730 &dg2_hdmi_594, 1731 &dg2_hdmi_25200, 1732 &dg2_hdmi_27027, 1733 &dg2_hdmi_28320, 1734 &dg2_hdmi_30240, 1735 &dg2_hdmi_31500, 1736 &dg2_hdmi_36000, 1737 &dg2_hdmi_40000, 1738 &dg2_hdmi_49500, 1739 &dg2_hdmi_50000, 1740 &dg2_hdmi_57284, 1741 &dg2_hdmi_58000, 1742 &dg2_hdmi_65000, 1743 &dg2_hdmi_71000, 1744 &dg2_hdmi_74176, 1745 &dg2_hdmi_75000, 1746 &dg2_hdmi_78750, 1747 &dg2_hdmi_85500, 1748 &dg2_hdmi_88750, 1749 &dg2_hdmi_106500, 1750 &dg2_hdmi_108000, 1751 &dg2_hdmi_115500, 1752 &dg2_hdmi_119000, 1753 &dg2_hdmi_135000, 1754 &dg2_hdmi_138500, 1755 &dg2_hdmi_147160, 1756 &dg2_hdmi_148352, 1757 &dg2_hdmi_154000, 1758 &dg2_hdmi_162000, 1759 &dg2_hdmi_209800, 1760 &dg2_hdmi_241500, 1761 &dg2_hdmi_262750, 1762 &dg2_hdmi_267300, 1763 &dg2_hdmi_268500, 1764 &dg2_hdmi_296703, 1765 &dg2_hdmi_319890, 1766 &dg2_hdmi_497750, 1767 &dg2_hdmi_592000, 1768 &dg2_hdmi_593407, 1769 NULL, 1770 }; 1771 1772 static const struct intel_mpllb_state * const * 1773 intel_mpllb_tables_get(struct intel_crtc_state *crtc_state, 1774 struct intel_encoder *encoder) 1775 { 1776 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) { 1777 return dg2_edp_tables; 1778 } else if (intel_crtc_has_dp_encoder(crtc_state)) { 1779 return dg2_dp_100_tables; 1780 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { 1781 return dg2_hdmi_tables; 1782 } 1783 1784 MISSING_CASE(encoder->type); 1785 return NULL; 1786 } 1787 1788 int intel_mpllb_calc_state(struct intel_crtc_state *crtc_state, 1789 struct intel_encoder *encoder) 1790 { 1791 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1792 const struct intel_mpllb_state * const *tables; 1793 int i; 1794 1795 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { 1796 if (intel_snps_phy_check_hdmi_link_rate(crtc_state->port_clock) 1797 != MODE_OK) { 1798 /* 1799 * FIXME: Can only support fixed HDMI frequencies 1800 * until we have a proper algorithm under a valid 1801 * license. 1802 */ 1803 drm_dbg_kms(&i915->drm, "Can't support HDMI link rate %d\n", 1804 crtc_state->port_clock); 1805 return -EINVAL; 1806 } 1807 } 1808 1809 tables = intel_mpllb_tables_get(crtc_state, encoder); 1810 if (!tables) 1811 return -EINVAL; 1812 1813 for (i = 0; tables[i]; i++) { 1814 if (crtc_state->port_clock == tables[i]->clock) { 1815 crtc_state->dpll_hw_state.mpllb = *tables[i]; 1816 return 0; 1817 } 1818 } 1819 1820 return -EINVAL; 1821 } 1822 1823 void intel_mpllb_enable(struct intel_encoder *encoder, 1824 const struct intel_crtc_state *crtc_state) 1825 { 1826 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1827 const struct intel_mpllb_state *pll_state = &crtc_state->dpll_hw_state.mpllb; 1828 enum phy phy = intel_encoder_to_phy(encoder); 1829 i915_reg_t enable_reg = (phy <= PHY_D ? 1830 DG2_PLL_ENABLE(phy) : MG_PLL_ENABLE(0)); 1831 1832 /* 1833 * 3. Software programs the following PLL registers for the desired 1834 * frequency. 1835 */ 1836 intel_de_write(dev_priv, SNPS_PHY_MPLLB_CP(phy), pll_state->mpllb_cp); 1837 intel_de_write(dev_priv, SNPS_PHY_MPLLB_DIV(phy), pll_state->mpllb_div); 1838 intel_de_write(dev_priv, SNPS_PHY_MPLLB_DIV2(phy), pll_state->mpllb_div2); 1839 intel_de_write(dev_priv, SNPS_PHY_MPLLB_SSCEN(phy), pll_state->mpllb_sscen); 1840 intel_de_write(dev_priv, SNPS_PHY_MPLLB_SSCSTEP(phy), pll_state->mpllb_sscstep); 1841 intel_de_write(dev_priv, SNPS_PHY_MPLLB_FRACN1(phy), pll_state->mpllb_fracn1); 1842 intel_de_write(dev_priv, SNPS_PHY_MPLLB_FRACN2(phy), pll_state->mpllb_fracn2); 1843 1844 /* 1845 * 4. If the frequency will result in a change to the voltage 1846 * requirement, follow the Display Voltage Frequency Switching - 1847 * Sequence Before Frequency Change. 1848 * 1849 * We handle this step in bxt_set_cdclk(). 1850 */ 1851 1852 /* 5. Software sets DPLL_ENABLE [PLL Enable] to "1". */ 1853 intel_de_rmw(dev_priv, enable_reg, 0, PLL_ENABLE); 1854 1855 /* 1856 * 9. Software sets SNPS_PHY_MPLLB_DIV dp_mpllb_force_en to "1". This 1857 * will keep the PLL running during the DDI lane programming and any 1858 * typeC DP cable disconnect. Do not set the force before enabling the 1859 * PLL because that will start the PLL before it has sampled the 1860 * divider values. 1861 */ 1862 intel_de_write(dev_priv, SNPS_PHY_MPLLB_DIV(phy), 1863 pll_state->mpllb_div | SNPS_PHY_MPLLB_FORCE_EN); 1864 1865 /* 1866 * 10. Software polls on register DPLL_ENABLE [PLL Lock] to confirm PLL 1867 * is locked at new settings. This register bit is sampling PHY 1868 * dp_mpllb_state interface signal. 1869 */ 1870 if (intel_de_wait_for_set(dev_priv, enable_reg, PLL_LOCK, 5)) 1871 drm_dbg_kms(&dev_priv->drm, "Port %c PLL not locked\n", phy_name(phy)); 1872 1873 /* 1874 * 11. If the frequency will result in a change to the voltage 1875 * requirement, follow the Display Voltage Frequency Switching - 1876 * Sequence After Frequency Change. 1877 * 1878 * We handle this step in bxt_set_cdclk(). 1879 */ 1880 } 1881 1882 void intel_mpllb_disable(struct intel_encoder *encoder) 1883 { 1884 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1885 enum phy phy = intel_encoder_to_phy(encoder); 1886 i915_reg_t enable_reg = (phy <= PHY_D ? 1887 DG2_PLL_ENABLE(phy) : MG_PLL_ENABLE(0)); 1888 1889 /* 1890 * 1. If the frequency will result in a change to the voltage 1891 * requirement, follow the Display Voltage Frequency Switching - 1892 * Sequence Before Frequency Change. 1893 * 1894 * We handle this step in bxt_set_cdclk(). 1895 */ 1896 1897 /* 2. Software programs DPLL_ENABLE [PLL Enable] to "0" */ 1898 intel_de_rmw(i915, enable_reg, PLL_ENABLE, 0); 1899 1900 /* 1901 * 4. Software programs SNPS_PHY_MPLLB_DIV dp_mpllb_force_en to "0". 1902 * This will allow the PLL to stop running. 1903 */ 1904 intel_de_rmw(i915, SNPS_PHY_MPLLB_DIV(phy), SNPS_PHY_MPLLB_FORCE_EN, 0); 1905 1906 /* 1907 * 5. Software polls DPLL_ENABLE [PLL Lock] for PHY acknowledgment 1908 * (dp_txX_ack) that the new transmitter setting request is completed. 1909 */ 1910 if (intel_de_wait_for_clear(i915, enable_reg, PLL_LOCK, 5)) 1911 drm_err(&i915->drm, "Port %c PLL not locked\n", phy_name(phy)); 1912 1913 /* 1914 * 6. If the frequency will result in a change to the voltage 1915 * requirement, follow the Display Voltage Frequency Switching - 1916 * Sequence After Frequency Change. 1917 * 1918 * We handle this step in bxt_set_cdclk(). 1919 */ 1920 } 1921 1922 int intel_mpllb_calc_port_clock(struct intel_encoder *encoder, 1923 const struct intel_mpllb_state *pll_state) 1924 { 1925 unsigned int frac_quot = 0, frac_rem = 0, frac_den = 1; 1926 unsigned int multiplier, tx_clk_div, refclk; 1927 bool frac_en; 1928 1929 if (0) 1930 refclk = 38400; 1931 else 1932 refclk = 100000; 1933 1934 refclk >>= REG_FIELD_GET(SNPS_PHY_MPLLB_REF_CLK_DIV, pll_state->mpllb_div2) - 1; 1935 1936 frac_en = REG_FIELD_GET(SNPS_PHY_MPLLB_FRACN_EN, pll_state->mpllb_fracn1); 1937 1938 if (frac_en) { 1939 frac_quot = REG_FIELD_GET(SNPS_PHY_MPLLB_FRACN_QUOT, pll_state->mpllb_fracn2); 1940 frac_rem = REG_FIELD_GET(SNPS_PHY_MPLLB_FRACN_REM, pll_state->mpllb_fracn2); 1941 frac_den = REG_FIELD_GET(SNPS_PHY_MPLLB_FRACN_DEN, pll_state->mpllb_fracn1); 1942 } 1943 1944 multiplier = REG_FIELD_GET(SNPS_PHY_MPLLB_MULTIPLIER, pll_state->mpllb_div2) / 2 + 16; 1945 1946 tx_clk_div = REG_FIELD_GET(SNPS_PHY_MPLLB_TX_CLK_DIV, pll_state->mpllb_div); 1947 1948 return DIV_ROUND_CLOSEST_ULL(mul_u32_u32(refclk, (multiplier << 16) + frac_quot) + 1949 DIV_ROUND_CLOSEST(refclk * frac_rem, frac_den), 1950 10 << (tx_clk_div + 16)); 1951 } 1952 1953 void intel_mpllb_readout_hw_state(struct intel_encoder *encoder, 1954 struct intel_mpllb_state *pll_state) 1955 { 1956 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1957 enum phy phy = intel_encoder_to_phy(encoder); 1958 1959 pll_state->mpllb_cp = intel_de_read(dev_priv, SNPS_PHY_MPLLB_CP(phy)); 1960 pll_state->mpllb_div = intel_de_read(dev_priv, SNPS_PHY_MPLLB_DIV(phy)); 1961 pll_state->mpllb_div2 = intel_de_read(dev_priv, SNPS_PHY_MPLLB_DIV2(phy)); 1962 pll_state->mpllb_sscen = intel_de_read(dev_priv, SNPS_PHY_MPLLB_SSCEN(phy)); 1963 pll_state->mpllb_sscstep = intel_de_read(dev_priv, SNPS_PHY_MPLLB_SSCSTEP(phy)); 1964 pll_state->mpllb_fracn1 = intel_de_read(dev_priv, SNPS_PHY_MPLLB_FRACN1(phy)); 1965 pll_state->mpllb_fracn2 = intel_de_read(dev_priv, SNPS_PHY_MPLLB_FRACN2(phy)); 1966 1967 /* 1968 * REF_CONTROL is under firmware control and never programmed by the 1969 * driver; we read it only for sanity checking purposes. The bspec 1970 * only tells us the expected value for one field in this register, 1971 * so we'll only read out those specific bits here. 1972 */ 1973 pll_state->ref_control = intel_de_read(dev_priv, SNPS_PHY_REF_CONTROL(phy)) & 1974 SNPS_PHY_REF_CONTROL_REF_RANGE; 1975 1976 /* 1977 * MPLLB_DIV is programmed twice, once with the software-computed 1978 * state, then again with the MPLLB_FORCE_EN bit added. Drop that 1979 * extra bit during readout so that we return the actual expected 1980 * software state. 1981 */ 1982 pll_state->mpllb_div &= ~SNPS_PHY_MPLLB_FORCE_EN; 1983 } 1984 1985 int intel_snps_phy_check_hdmi_link_rate(int clock) 1986 { 1987 const struct intel_mpllb_state * const *tables = dg2_hdmi_tables; 1988 int i; 1989 1990 for (i = 0; tables[i]; i++) { 1991 if (clock == tables[i]->clock) 1992 return MODE_OK; 1993 } 1994 1995 return MODE_CLOCK_RANGE; 1996 } 1997 1998 void intel_mpllb_state_verify(struct intel_atomic_state *state, 1999 struct intel_crtc *crtc) 2000 { 2001 struct intel_display *display = to_intel_display(state); 2002 struct drm_i915_private *i915 = to_i915(state->base.dev); 2003 const struct intel_crtc_state *new_crtc_state = 2004 intel_atomic_get_new_crtc_state(state, crtc); 2005 struct intel_mpllb_state mpllb_hw_state = {}; 2006 const struct intel_mpllb_state *mpllb_sw_state = &new_crtc_state->dpll_hw_state.mpllb; 2007 struct intel_encoder *encoder; 2008 2009 if (!IS_DG2(i915)) 2010 return; 2011 2012 if (!new_crtc_state->hw.active) 2013 return; 2014 2015 /* intel_get_crtc_new_encoder() only works for modeset/fastset commits */ 2016 if (!intel_crtc_needs_modeset(new_crtc_state) && 2017 !intel_crtc_needs_fastset(new_crtc_state)) 2018 return; 2019 2020 encoder = intel_get_crtc_new_encoder(state, new_crtc_state); 2021 intel_mpllb_readout_hw_state(encoder, &mpllb_hw_state); 2022 2023 #define MPLLB_CHECK(__name) \ 2024 INTEL_DISPLAY_STATE_WARN(display, mpllb_sw_state->__name != mpllb_hw_state.__name, \ 2025 "[CRTC:%d:%s] mismatch in MPLLB: %s (expected 0x%08x, found 0x%08x)", \ 2026 crtc->base.base.id, crtc->base.name, \ 2027 __stringify(__name), \ 2028 mpllb_sw_state->__name, mpllb_hw_state.__name) 2029 2030 MPLLB_CHECK(mpllb_cp); 2031 MPLLB_CHECK(mpllb_div); 2032 MPLLB_CHECK(mpllb_div2); 2033 MPLLB_CHECK(mpllb_fracn1); 2034 MPLLB_CHECK(mpllb_fracn2); 2035 MPLLB_CHECK(mpllb_sscen); 2036 MPLLB_CHECK(mpllb_sscstep); 2037 2038 /* 2039 * ref_control is handled by the hardware/firemware and never 2040 * programmed by the software, but the proper values are supplied 2041 * in the bspec for verification purposes. 2042 */ 2043 MPLLB_CHECK(ref_control); 2044 2045 #undef MPLLB_CHECK 2046 } 2047