1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2019 Intel Corporation 4 */ 5 6 #include <linux/math.h> 7 8 #include "i915_reg.h" 9 #include "i915_utils.h" 10 #include "intel_ddi.h" 11 #include "intel_ddi_buf_trans.h" 12 #include "intel_de.h" 13 #include "intel_display_types.h" 14 #include "intel_snps_hdmi_pll.h" 15 #include "intel_snps_phy.h" 16 #include "intel_snps_phy_regs.h" 17 18 /** 19 * DOC: Synopsis PHY support 20 * 21 * Synopsis PHYs are primarily programmed by looking up magic register values 22 * in tables rather than calculating the necessary values at runtime. 23 * 24 * Of special note is that the SNPS PHYs include a dedicated port PLL, known as 25 * an "MPLLB." The MPLLB replaces the shared DPLL functionality used on other 26 * platforms and must be programming directly during the modeset sequence 27 * since it is not handled by the shared DPLL framework as on other platforms. 28 */ 29 30 void intel_snps_phy_wait_for_calibration(struct intel_display *display) 31 { 32 enum phy phy; 33 34 for_each_phy_masked(phy, ~0) { 35 if (!intel_phy_is_snps(display, phy)) 36 continue; 37 38 /* 39 * If calibration does not complete successfully, we'll remember 40 * which phy was affected and skip setup of the corresponding 41 * output later. 42 */ 43 if (intel_de_wait_for_clear(display, DG2_PHY_MISC(phy), 44 DG2_PHY_DP_TX_ACK_MASK, 25)) 45 display->snps.phy_failed_calibration |= BIT(phy); 46 } 47 } 48 49 void intel_snps_phy_update_psr_power_state(struct intel_encoder *encoder, 50 bool enable) 51 { 52 struct intel_display *display = to_intel_display(encoder); 53 enum phy phy = intel_encoder_to_phy(encoder); 54 u32 val; 55 56 if (!intel_encoder_is_snps(encoder)) 57 return; 58 59 val = REG_FIELD_PREP(SNPS_PHY_TX_REQ_LN_DIS_PWR_STATE_PSR, 60 enable ? 2 : 3); 61 intel_de_rmw(display, SNPS_PHY_TX_REQ(phy), 62 SNPS_PHY_TX_REQ_LN_DIS_PWR_STATE_PSR, val); 63 } 64 65 void intel_snps_phy_set_signal_levels(struct intel_encoder *encoder, 66 const struct intel_crtc_state *crtc_state) 67 { 68 struct intel_display *display = to_intel_display(encoder); 69 const struct intel_ddi_buf_trans *trans; 70 enum phy phy = intel_encoder_to_phy(encoder); 71 int n_entries, ln; 72 73 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); 74 if (drm_WARN_ON_ONCE(display->drm, !trans)) 75 return; 76 77 for (ln = 0; ln < 4; ln++) { 78 int level = intel_ddi_level(encoder, crtc_state, ln); 79 u32 val = 0; 80 81 val |= REG_FIELD_PREP(SNPS_PHY_TX_EQ_MAIN, trans->entries[level].snps.vswing); 82 val |= REG_FIELD_PREP(SNPS_PHY_TX_EQ_PRE, trans->entries[level].snps.pre_cursor); 83 val |= REG_FIELD_PREP(SNPS_PHY_TX_EQ_POST, trans->entries[level].snps.post_cursor); 84 85 intel_de_write(display, SNPS_PHY_TX_EQ(ln, phy), val); 86 } 87 } 88 89 /* 90 * Basic DP link rates with 100 MHz reference clock. 91 */ 92 93 static const struct intel_mpllb_state dg2_dp_rbr_100 = { 94 .clock = 162000, 95 .ref_control = 96 REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3), 97 .mpllb_cp = 98 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 4) | 99 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 20) | 100 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 65) | 101 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 127), 102 .mpllb_div = 103 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) | 104 REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 2) | 105 REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) | 106 REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) | 107 REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 2), 108 .mpllb_div2 = 109 REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 2) | 110 REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 226), 111 .mpllb_fracn1 = 112 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) | 113 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) | 114 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 5), 115 .mpllb_fracn2 = 116 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 39321) | 117 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 3), 118 }; 119 120 static const struct intel_mpllb_state dg2_dp_hbr1_100 = { 121 .clock = 270000, 122 .ref_control = 123 REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3), 124 .mpllb_cp = 125 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 4) | 126 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 20) | 127 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 65) | 128 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 127), 129 .mpllb_div = 130 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) | 131 REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 1) | 132 REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) | 133 REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 3), 134 .mpllb_div2 = 135 REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 2) | 136 REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 184), 137 .mpllb_fracn1 = 138 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) | 139 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 1), 140 }; 141 142 static const struct intel_mpllb_state dg2_dp_hbr2_100 = { 143 .clock = 540000, 144 .ref_control = 145 REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3), 146 .mpllb_cp = 147 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 4) | 148 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 20) | 149 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 65) | 150 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 127), 151 .mpllb_div = 152 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) | 153 REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) | 154 REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 3), 155 .mpllb_div2 = 156 REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 2) | 157 REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 184), 158 .mpllb_fracn1 = 159 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) | 160 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 1), 161 }; 162 163 static const struct intel_mpllb_state dg2_dp_hbr3_100 = { 164 .clock = 810000, 165 .ref_control = 166 REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3), 167 .mpllb_cp = 168 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 4) | 169 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 19) | 170 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 65) | 171 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 127), 172 .mpllb_div = 173 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) | 174 REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2), 175 .mpllb_div2 = 176 REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 2) | 177 REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 292), 178 .mpllb_fracn1 = 179 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) | 180 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 1), 181 }; 182 183 static const struct intel_mpllb_state dg2_dp_uhbr10_100 = { 184 .clock = 1000000, 185 .ref_control = 186 REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3), 187 .mpllb_cp = 188 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 4) | 189 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 21) | 190 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 65) | 191 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 127), 192 .mpllb_div = 193 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) | 194 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV_CLK_EN, 1) | 195 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV_MULTIPLIER, 8) | 196 REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) | 197 REG_FIELD_PREP(SNPS_PHY_MPLLB_WORD_DIV2_EN, 1) | 198 REG_FIELD_PREP(SNPS_PHY_MPLLB_DP2_MODE, 1) | 199 REG_FIELD_PREP(SNPS_PHY_MPLLB_SHIM_DIV32_CLK_SEL, 1) | 200 REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2), 201 .mpllb_div2 = 202 REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 2) | 203 REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 368), 204 .mpllb_fracn1 = 205 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) | 206 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 1), 207 208 /* 209 * SSC will be enabled, DP UHBR has a minimum SSC requirement. 210 */ 211 .mpllb_sscen = 212 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_EN, 1) | 213 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_PEAK, 58982), 214 .mpllb_sscstep = 215 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_STEPSIZE, 76101), 216 }; 217 218 static const struct intel_mpllb_state dg2_dp_uhbr13_100 = { 219 .clock = 1350000, 220 .ref_control = 221 REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3), 222 .mpllb_cp = 223 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 5) | 224 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 45) | 225 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 65) | 226 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 127), 227 .mpllb_div = 228 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) | 229 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV_CLK_EN, 1) | 230 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV_MULTIPLIER, 8) | 231 REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) | 232 REG_FIELD_PREP(SNPS_PHY_MPLLB_WORD_DIV2_EN, 1) | 233 REG_FIELD_PREP(SNPS_PHY_MPLLB_DP2_MODE, 1) | 234 REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 3), 235 .mpllb_div2 = 236 REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 2) | 237 REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 508), 238 .mpllb_fracn1 = 239 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) | 240 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 1), 241 242 /* 243 * SSC will be enabled, DP UHBR has a minimum SSC requirement. 244 */ 245 .mpllb_sscen = 246 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_EN, 1) | 247 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_PEAK, 79626), 248 .mpllb_sscstep = 249 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_STEPSIZE, 102737), 250 }; 251 252 static const struct intel_mpllb_state * const dg2_dp_100_tables[] = { 253 &dg2_dp_rbr_100, 254 &dg2_dp_hbr1_100, 255 &dg2_dp_hbr2_100, 256 &dg2_dp_hbr3_100, 257 &dg2_dp_uhbr10_100, 258 &dg2_dp_uhbr13_100, 259 NULL, 260 }; 261 262 /* 263 * eDP link rates with 100 MHz reference clock. 264 */ 265 266 static const struct intel_mpllb_state dg2_edp_r216 = { 267 .clock = 216000, 268 .ref_control = 269 REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3), 270 .mpllb_cp = 271 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 4) | 272 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 19) | 273 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 65) | 274 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 127), 275 .mpllb_div = 276 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) | 277 REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 2) | 278 REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) | 279 REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2), 280 .mpllb_div2 = 281 REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 2) | 282 REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 312), 283 .mpllb_fracn1 = 284 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) | 285 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) | 286 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 5), 287 .mpllb_fracn2 = 288 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 52428) | 289 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 4), 290 .mpllb_sscen = 291 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_EN, 1) | 292 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_PEAK, 50961), 293 .mpllb_sscstep = 294 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_STEPSIZE, 65752), 295 }; 296 297 static const struct intel_mpllb_state dg2_edp_r243 = { 298 .clock = 243000, 299 .ref_control = 300 REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3), 301 .mpllb_cp = 302 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 4) | 303 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 20) | 304 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 65) | 305 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 127), 306 .mpllb_div = 307 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) | 308 REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 2) | 309 REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) | 310 REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2), 311 .mpllb_div2 = 312 REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 2) | 313 REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 356), 314 .mpllb_fracn1 = 315 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) | 316 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) | 317 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 5), 318 .mpllb_fracn2 = 319 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 26214) | 320 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 2), 321 .mpllb_sscen = 322 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_EN, 1) | 323 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_PEAK, 57331), 324 .mpllb_sscstep = 325 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_STEPSIZE, 73971), 326 }; 327 328 static const struct intel_mpllb_state dg2_edp_r324 = { 329 .clock = 324000, 330 .ref_control = 331 REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3), 332 .mpllb_cp = 333 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 4) | 334 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 20) | 335 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 65) | 336 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 127), 337 .mpllb_div = 338 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) | 339 REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 1) | 340 REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) | 341 REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) | 342 REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 2), 343 .mpllb_div2 = 344 REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 2) | 345 REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 226), 346 .mpllb_fracn1 = 347 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) | 348 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) | 349 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 5), 350 .mpllb_fracn2 = 351 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 39321) | 352 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 3), 353 .mpllb_sscen = 354 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_EN, 1) | 355 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_PEAK, 38221), 356 .mpllb_sscstep = 357 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_STEPSIZE, 49314), 358 }; 359 360 static const struct intel_mpllb_state dg2_edp_r432 = { 361 .clock = 432000, 362 .ref_control = 363 REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3), 364 .mpllb_cp = 365 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 4) | 366 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 19) | 367 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 65) | 368 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 127), 369 .mpllb_div = 370 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) | 371 REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 1) | 372 REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) | 373 REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2), 374 .mpllb_div2 = 375 REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 2) | 376 REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 312), 377 .mpllb_fracn1 = 378 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) | 379 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) | 380 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 5), 381 .mpllb_fracn2 = 382 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 52428) | 383 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 4), 384 .mpllb_sscen = 385 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_EN, 1) | 386 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_PEAK, 50961), 387 .mpllb_sscstep = 388 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_STEPSIZE, 65752), 389 }; 390 391 static const struct intel_mpllb_state * const dg2_edp_tables[] = { 392 &dg2_dp_rbr_100, 393 &dg2_edp_r216, 394 &dg2_edp_r243, 395 &dg2_dp_hbr1_100, 396 &dg2_edp_r324, 397 &dg2_edp_r432, 398 &dg2_dp_hbr2_100, 399 &dg2_dp_hbr3_100, 400 NULL, 401 }; 402 403 /* 404 * HDMI link rates with 100 MHz reference clock. 405 */ 406 407 static const struct intel_mpllb_state dg2_hdmi_25_175 = { 408 .clock = 25175, 409 .ref_control = 410 REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3), 411 .mpllb_cp = 412 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 5) | 413 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 15) | 414 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) | 415 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124), 416 .mpllb_div = 417 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) | 418 REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 5) | 419 REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) | 420 REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2), 421 .mpllb_div2 = 422 REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) | 423 REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 128) | 424 REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1), 425 .mpllb_fracn1 = 426 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) | 427 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) | 428 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 143), 429 .mpllb_fracn2 = 430 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 36663) | 431 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 71), 432 .mpllb_sscen = 433 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1), 434 }; 435 436 static const struct intel_mpllb_state dg2_hdmi_27_0 = { 437 .clock = 27000, 438 .ref_control = 439 REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3), 440 .mpllb_cp = 441 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 5) | 442 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 15) | 443 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) | 444 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124), 445 .mpllb_div = 446 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) | 447 REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 5) | 448 REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) | 449 REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2), 450 .mpllb_div2 = 451 REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) | 452 REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 140) | 453 REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1), 454 .mpllb_fracn1 = 455 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) | 456 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) | 457 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 5), 458 .mpllb_fracn2 = 459 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 26214) | 460 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 2), 461 .mpllb_sscen = 462 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1), 463 }; 464 465 static const struct intel_mpllb_state dg2_hdmi_74_25 = { 466 .clock = 74250, 467 .ref_control = 468 REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3), 469 .mpllb_cp = 470 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 4) | 471 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 15) | 472 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) | 473 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124), 474 .mpllb_div = 475 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) | 476 REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 3) | 477 REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) | 478 REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) | 479 REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 3), 480 .mpllb_div2 = 481 REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) | 482 REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 86) | 483 REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1), 484 .mpllb_fracn1 = 485 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) | 486 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) | 487 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 5), 488 .mpllb_fracn2 = 489 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 26214) | 490 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 2), 491 .mpllb_sscen = 492 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1), 493 }; 494 495 static const struct intel_mpllb_state dg2_hdmi_148_5 = { 496 .clock = 148500, 497 .ref_control = 498 REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3), 499 .mpllb_cp = 500 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 4) | 501 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 15) | 502 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) | 503 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124), 504 .mpllb_div = 505 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) | 506 REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 2) | 507 REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) | 508 REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) | 509 REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 3), 510 .mpllb_div2 = 511 REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) | 512 REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 86) | 513 REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1), 514 .mpllb_fracn1 = 515 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) | 516 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) | 517 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 5), 518 .mpllb_fracn2 = 519 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 26214) | 520 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 2), 521 .mpllb_sscen = 522 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1), 523 }; 524 525 /* values in the below table are calculated using the algo */ 526 static const struct intel_mpllb_state dg2_hdmi_25200 = { 527 .clock = 25200, 528 .ref_control = 529 REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3), 530 .mpllb_cp = 531 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 7) | 532 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) | 533 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) | 534 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124), 535 .mpllb_div = 536 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) | 537 REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 5) | 538 REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) | 539 REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) | 540 REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 0), 541 .mpllb_div2 = 542 REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) | 543 REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 128) | 544 REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1), 545 .mpllb_fracn1 = 546 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) | 547 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) | 548 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535), 549 .mpllb_fracn2 = 550 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 41943) | 551 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 2621), 552 .mpllb_sscen = 553 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1), 554 }; 555 556 static const struct intel_mpllb_state dg2_hdmi_27027 = { 557 .clock = 27027, 558 .ref_control = 559 REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3), 560 .mpllb_cp = 561 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) | 562 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) | 563 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) | 564 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124), 565 .mpllb_div = 566 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) | 567 REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 5) | 568 REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) | 569 REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) | 570 REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 0), 571 .mpllb_div2 = 572 REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) | 573 REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 140) | 574 REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1), 575 .mpllb_fracn1 = 576 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) | 577 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) | 578 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535), 579 .mpllb_fracn2 = 580 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 31876) | 581 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 46555), 582 .mpllb_sscen = 583 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1), 584 }; 585 586 static const struct intel_mpllb_state dg2_hdmi_28320 = { 587 .clock = 28320, 588 .ref_control = 589 REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3), 590 .mpllb_cp = 591 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) | 592 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) | 593 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) | 594 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124), 595 .mpllb_div = 596 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) | 597 REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 5) | 598 REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) | 599 REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) | 600 REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 0), 601 .mpllb_div2 = 602 REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) | 603 REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 148) | 604 REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1), 605 .mpllb_fracn1 = 606 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) | 607 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) | 608 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535), 609 .mpllb_fracn2 = 610 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 40894) | 611 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 30408), 612 .mpllb_sscen = 613 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1), 614 }; 615 616 static const struct intel_mpllb_state dg2_hdmi_30240 = { 617 .clock = 30240, 618 .ref_control = 619 REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3), 620 .mpllb_cp = 621 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) | 622 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) | 623 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) | 624 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124), 625 .mpllb_div = 626 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) | 627 REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 5) | 628 REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) | 629 REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) | 630 REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 0), 631 .mpllb_div2 = 632 REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) | 633 REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 160) | 634 REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1), 635 .mpllb_fracn1 = 636 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) | 637 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) | 638 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535), 639 .mpllb_fracn2 = 640 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 50331) | 641 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 42466), 642 .mpllb_sscen = 643 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1), 644 }; 645 646 static const struct intel_mpllb_state dg2_hdmi_31500 = { 647 .clock = 31500, 648 .ref_control = 649 REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3), 650 .mpllb_cp = 651 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 7) | 652 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) | 653 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) | 654 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124), 655 .mpllb_div = 656 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) | 657 REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 4) | 658 REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) | 659 REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) | 660 REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 3), 661 .mpllb_div2 = 662 REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) | 663 REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 68) | 664 REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1), 665 .mpllb_fracn1 = 666 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) | 667 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) | 668 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535), 669 .mpllb_fracn2 = 670 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 26214) | 671 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 26214), 672 .mpllb_sscen = 673 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1), 674 }; 675 676 static const struct intel_mpllb_state dg2_hdmi_36000 = { 677 .clock = 36000, 678 .ref_control = 679 REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3), 680 .mpllb_cp = 681 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) | 682 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) | 683 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) | 684 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124), 685 .mpllb_div = 686 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) | 687 REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 4) | 688 REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) | 689 REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) | 690 REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 3), 691 .mpllb_div2 = 692 REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) | 693 REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 82) | 694 REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1), 695 .mpllb_fracn1 = 696 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) | 697 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) | 698 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535), 699 .mpllb_fracn2 = 700 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 39321) | 701 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 39320), 702 .mpllb_sscen = 703 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1), 704 }; 705 706 static const struct intel_mpllb_state dg2_hdmi_40000 = { 707 .clock = 40000, 708 .ref_control = 709 REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3), 710 .mpllb_cp = 711 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) | 712 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) | 713 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) | 714 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124), 715 .mpllb_div = 716 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) | 717 REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 4) | 718 REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 0) | 719 REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) | 720 REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 2), 721 .mpllb_div2 = 722 REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) | 723 REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 96) | 724 REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1), 725 .mpllb_fracn1 = 726 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) | 727 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 0) | 728 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535), 729 .mpllb_fracn2 = 730 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 0) | 731 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 0), 732 .mpllb_sscen = 733 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1), 734 }; 735 736 static const struct intel_mpllb_state dg2_hdmi_49500 = { 737 .clock = 49500, 738 .ref_control = 739 REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3), 740 .mpllb_cp = 741 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) | 742 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) | 743 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) | 744 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124), 745 .mpllb_div = 746 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) | 747 REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 4) | 748 REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) | 749 REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) | 750 REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 1), 751 .mpllb_div2 = 752 REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) | 753 REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 126) | 754 REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1), 755 .mpllb_fracn1 = 756 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) | 757 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) | 758 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535), 759 .mpllb_fracn2 = 760 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 13107) | 761 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 13107), 762 .mpllb_sscen = 763 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1), 764 }; 765 766 static const struct intel_mpllb_state dg2_hdmi_50000 = { 767 .clock = 50000, 768 .ref_control = 769 REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3), 770 .mpllb_cp = 771 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) | 772 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) | 773 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) | 774 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124), 775 .mpllb_div = 776 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) | 777 REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 4) | 778 REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 0) | 779 REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) | 780 REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 1), 781 .mpllb_div2 = 782 REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) | 783 REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 128) | 784 REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1), 785 .mpllb_fracn1 = 786 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) | 787 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 0) | 788 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535), 789 .mpllb_fracn2 = 790 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 0) | 791 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 0), 792 .mpllb_sscen = 793 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1), 794 }; 795 796 static const struct intel_mpllb_state dg2_hdmi_57284 = { 797 .clock = 57284, 798 .ref_control = 799 REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3), 800 .mpllb_cp = 801 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) | 802 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) | 803 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) | 804 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124), 805 .mpllb_div = 806 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) | 807 REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 4) | 808 REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) | 809 REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) | 810 REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 0), 811 .mpllb_div2 = 812 REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) | 813 REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 150) | 814 REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1), 815 .mpllb_fracn1 = 816 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) | 817 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) | 818 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535), 819 .mpllb_fracn2 = 820 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 42886) | 821 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 49701), 822 .mpllb_sscen = 823 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1), 824 }; 825 826 static const struct intel_mpllb_state dg2_hdmi_58000 = { 827 .clock = 58000, 828 .ref_control = 829 REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3), 830 .mpllb_cp = 831 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) | 832 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) | 833 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) | 834 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124), 835 .mpllb_div = 836 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) | 837 REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 4) | 838 REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) | 839 REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) | 840 REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 0), 841 .mpllb_div2 = 842 REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) | 843 REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 152) | 844 REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1), 845 .mpllb_fracn1 = 846 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) | 847 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) | 848 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535), 849 .mpllb_fracn2 = 850 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 52428) | 851 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 52427), 852 .mpllb_sscen = 853 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1), 854 }; 855 856 static const struct intel_mpllb_state dg2_hdmi_65000 = { 857 .clock = 65000, 858 .ref_control = 859 REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3), 860 .mpllb_cp = 861 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 7) | 862 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) | 863 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) | 864 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124), 865 .mpllb_div = 866 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) | 867 REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 3) | 868 REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 0) | 869 REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) | 870 REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 3), 871 .mpllb_div2 = 872 REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) | 873 REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 72) | 874 REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1), 875 .mpllb_fracn1 = 876 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) | 877 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 0) | 878 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535), 879 .mpllb_fracn2 = 880 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 0) | 881 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 0), 882 .mpllb_sscen = 883 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1), 884 }; 885 886 static const struct intel_mpllb_state dg2_hdmi_71000 = { 887 .clock = 71000, 888 .ref_control = 889 REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3), 890 .mpllb_cp = 891 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) | 892 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) | 893 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) | 894 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124), 895 .mpllb_div = 896 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) | 897 REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 3) | 898 REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) | 899 REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) | 900 REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 3), 901 .mpllb_div2 = 902 REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) | 903 REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 80) | 904 REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1), 905 .mpllb_fracn1 = 906 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) | 907 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) | 908 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535), 909 .mpllb_fracn2 = 910 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 52428) | 911 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 52427), 912 .mpllb_sscen = 913 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1), 914 }; 915 916 static const struct intel_mpllb_state dg2_hdmi_74176 = { 917 .clock = 74176, 918 .ref_control = 919 REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3), 920 .mpllb_cp = 921 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) | 922 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) | 923 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) | 924 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124), 925 .mpllb_div = 926 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) | 927 REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 3) | 928 REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) | 929 REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) | 930 REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 3), 931 .mpllb_div2 = 932 REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) | 933 REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 86) | 934 REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1), 935 .mpllb_fracn1 = 936 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) | 937 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) | 938 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535), 939 .mpllb_fracn2 = 940 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 22334) | 941 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 43829), 942 .mpllb_sscen = 943 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1), 944 }; 945 946 static const struct intel_mpllb_state dg2_hdmi_75000 = { 947 .clock = 75000, 948 .ref_control = 949 REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3), 950 .mpllb_cp = 951 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) | 952 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) | 953 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) | 954 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124), 955 .mpllb_div = 956 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) | 957 REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 3) | 958 REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 0) | 959 REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) | 960 REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 3), 961 .mpllb_div2 = 962 REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) | 963 REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 88) | 964 REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1), 965 .mpllb_fracn1 = 966 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) | 967 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 0) | 968 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535), 969 .mpllb_fracn2 = 970 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 0) | 971 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 0), 972 .mpllb_sscen = 973 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1), 974 }; 975 976 static const struct intel_mpllb_state dg2_hdmi_78750 = { 977 .clock = 78750, 978 .ref_control = 979 REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3), 980 .mpllb_cp = 981 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) | 982 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) | 983 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) | 984 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124), 985 .mpllb_div = 986 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) | 987 REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 3) | 988 REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 0) | 989 REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) | 990 REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 2), 991 .mpllb_div2 = 992 REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) | 993 REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 94) | 994 REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1), 995 .mpllb_fracn1 = 996 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) | 997 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 0) | 998 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535), 999 .mpllb_fracn2 = 1000 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 0) | 1001 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 0), 1002 .mpllb_sscen = 1003 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1), 1004 }; 1005 1006 static const struct intel_mpllb_state dg2_hdmi_85500 = { 1007 .clock = 85500, 1008 .ref_control = 1009 REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3), 1010 .mpllb_cp = 1011 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) | 1012 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) | 1013 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) | 1014 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124), 1015 .mpllb_div = 1016 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) | 1017 REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 3) | 1018 REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) | 1019 REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) | 1020 REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 2), 1021 .mpllb_div2 = 1022 REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) | 1023 REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 104) | 1024 REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1), 1025 .mpllb_fracn1 = 1026 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) | 1027 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) | 1028 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535), 1029 .mpllb_fracn2 = 1030 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 26214) | 1031 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 26214), 1032 .mpllb_sscen = 1033 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1), 1034 }; 1035 1036 static const struct intel_mpllb_state dg2_hdmi_88750 = { 1037 .clock = 88750, 1038 .ref_control = 1039 REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3), 1040 .mpllb_cp = 1041 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 7) | 1042 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 15) | 1043 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) | 1044 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124), 1045 .mpllb_div = 1046 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) | 1047 REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 3) | 1048 REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 0) | 1049 REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) | 1050 REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 1), 1051 .mpllb_div2 = 1052 REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) | 1053 REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 110) | 1054 REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1), 1055 .mpllb_fracn1 = 1056 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) | 1057 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 0) | 1058 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535), 1059 .mpllb_fracn2 = 1060 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 0) | 1061 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 0), 1062 .mpllb_sscen = 1063 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1), 1064 }; 1065 1066 static const struct intel_mpllb_state dg2_hdmi_106500 = { 1067 .clock = 106500, 1068 .ref_control = 1069 REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3), 1070 .mpllb_cp = 1071 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) | 1072 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) | 1073 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) | 1074 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124), 1075 .mpllb_div = 1076 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) | 1077 REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 3) | 1078 REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) | 1079 REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) | 1080 REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 0), 1081 .mpllb_div2 = 1082 REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) | 1083 REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 138) | 1084 REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1), 1085 .mpllb_fracn1 = 1086 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) | 1087 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) | 1088 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535), 1089 .mpllb_fracn2 = 1090 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 13107) | 1091 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 13107), 1092 .mpllb_sscen = 1093 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1), 1094 }; 1095 1096 static const struct intel_mpllb_state dg2_hdmi_108000 = { 1097 .clock = 108000, 1098 .ref_control = 1099 REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3), 1100 .mpllb_cp = 1101 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) | 1102 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) | 1103 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) | 1104 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124), 1105 .mpllb_div = 1106 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) | 1107 REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 3) | 1108 REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) | 1109 REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) | 1110 REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 0), 1111 .mpllb_div2 = 1112 REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) | 1113 REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 140) | 1114 REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1), 1115 .mpllb_fracn1 = 1116 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) | 1117 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) | 1118 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535), 1119 .mpllb_fracn2 = 1120 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 26214) | 1121 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 26214), 1122 .mpllb_sscen = 1123 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1), 1124 }; 1125 1126 static const struct intel_mpllb_state dg2_hdmi_115500 = { 1127 .clock = 115500, 1128 .ref_control = 1129 REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3), 1130 .mpllb_cp = 1131 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) | 1132 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) | 1133 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) | 1134 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124), 1135 .mpllb_div = 1136 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) | 1137 REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 3) | 1138 REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) | 1139 REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) | 1140 REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 0), 1141 .mpllb_div2 = 1142 REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) | 1143 REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 152) | 1144 REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1), 1145 .mpllb_fracn1 = 1146 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) | 1147 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) | 1148 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535), 1149 .mpllb_fracn2 = 1150 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 26214) | 1151 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 26214), 1152 .mpllb_sscen = 1153 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1), 1154 }; 1155 1156 static const struct intel_mpllb_state dg2_hdmi_119000 = { 1157 .clock = 119000, 1158 .ref_control = 1159 REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3), 1160 .mpllb_cp = 1161 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) | 1162 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) | 1163 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) | 1164 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124), 1165 .mpllb_div = 1166 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) | 1167 REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 3) | 1168 REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) | 1169 REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) | 1170 REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 0), 1171 .mpllb_div2 = 1172 REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) | 1173 REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 158) | 1174 REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1), 1175 .mpllb_fracn1 = 1176 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) | 1177 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) | 1178 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535), 1179 .mpllb_fracn2 = 1180 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 13107) | 1181 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 13107), 1182 .mpllb_sscen = 1183 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1), 1184 }; 1185 1186 static const struct intel_mpllb_state dg2_hdmi_135000 = { 1187 .clock = 135000, 1188 .ref_control = 1189 REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3), 1190 .mpllb_cp = 1191 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 7) | 1192 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 15) | 1193 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) | 1194 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124), 1195 .mpllb_div = 1196 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) | 1197 REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 2) | 1198 REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 0) | 1199 REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) | 1200 REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 3), 1201 .mpllb_div2 = 1202 REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) | 1203 REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 76) | 1204 REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1), 1205 .mpllb_fracn1 = 1206 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) | 1207 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 0) | 1208 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535), 1209 .mpllb_fracn2 = 1210 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 0) | 1211 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 0), 1212 .mpllb_sscen = 1213 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1), 1214 }; 1215 1216 static const struct intel_mpllb_state dg2_hdmi_138500 = { 1217 .clock = 138500, 1218 .ref_control = 1219 REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3), 1220 .mpllb_cp = 1221 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) | 1222 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) | 1223 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) | 1224 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124), 1225 .mpllb_div = 1226 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) | 1227 REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 2) | 1228 REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) | 1229 REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) | 1230 REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 3), 1231 .mpllb_div2 = 1232 REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) | 1233 REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 78) | 1234 REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1), 1235 .mpllb_fracn1 = 1236 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) | 1237 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) | 1238 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535), 1239 .mpllb_fracn2 = 1240 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 26214) | 1241 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 26214), 1242 .mpllb_sscen = 1243 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1), 1244 }; 1245 1246 static const struct intel_mpllb_state dg2_hdmi_147160 = { 1247 .clock = 147160, 1248 .ref_control = 1249 REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3), 1250 .mpllb_cp = 1251 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) | 1252 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) | 1253 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) | 1254 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124), 1255 .mpllb_div = 1256 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) | 1257 REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 2) | 1258 REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) | 1259 REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) | 1260 REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 3), 1261 .mpllb_div2 = 1262 REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) | 1263 REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 84) | 1264 REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1), 1265 .mpllb_fracn1 = 1266 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) | 1267 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) | 1268 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535), 1269 .mpllb_fracn2 = 1270 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 56623) | 1271 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 6815), 1272 .mpllb_sscen = 1273 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1), 1274 }; 1275 1276 static const struct intel_mpllb_state dg2_hdmi_148352 = { 1277 .clock = 148352, 1278 .ref_control = 1279 REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3), 1280 .mpllb_cp = 1281 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) | 1282 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) | 1283 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) | 1284 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124), 1285 .mpllb_div = 1286 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) | 1287 REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 2) | 1288 REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) | 1289 REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) | 1290 REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 3), 1291 .mpllb_div2 = 1292 REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) | 1293 REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 86) | 1294 REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1), 1295 .mpllb_fracn1 = 1296 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) | 1297 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) | 1298 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535), 1299 .mpllb_fracn2 = 1300 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 22334) | 1301 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 43829), 1302 .mpllb_sscen = 1303 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1), 1304 }; 1305 1306 static const struct intel_mpllb_state dg2_hdmi_154000 = { 1307 .clock = 154000, 1308 .ref_control = 1309 REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3), 1310 .mpllb_cp = 1311 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) | 1312 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 13) | 1313 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) | 1314 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124), 1315 .mpllb_div = 1316 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) | 1317 REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 2) | 1318 REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) | 1319 REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) | 1320 REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 2), 1321 .mpllb_div2 = 1322 REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) | 1323 REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 90) | 1324 REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1), 1325 .mpllb_fracn1 = 1326 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) | 1327 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) | 1328 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535), 1329 .mpllb_fracn2 = 1330 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 39321) | 1331 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 39320), 1332 .mpllb_sscen = 1333 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1), 1334 }; 1335 1336 static const struct intel_mpllb_state dg2_hdmi_162000 = { 1337 .clock = 162000, 1338 .ref_control = 1339 REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3), 1340 .mpllb_cp = 1341 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) | 1342 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) | 1343 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) | 1344 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124), 1345 .mpllb_div = 1346 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) | 1347 REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 2) | 1348 REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) | 1349 REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) | 1350 REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 2), 1351 .mpllb_div2 = 1352 REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) | 1353 REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 96) | 1354 REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1), 1355 .mpllb_fracn1 = 1356 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) | 1357 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) | 1358 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535), 1359 .mpllb_fracn2 = 1360 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 52428) | 1361 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 52427), 1362 .mpllb_sscen = 1363 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1), 1364 }; 1365 1366 static const struct intel_mpllb_state dg2_hdmi_209800 = { 1367 .clock = 209800, 1368 .ref_control = 1369 REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3), 1370 .mpllb_cp = 1371 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 7) | 1372 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) | 1373 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) | 1374 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124), 1375 .mpllb_div = 1376 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) | 1377 REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 2) | 1378 REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) | 1379 REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) | 1380 REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 0), 1381 .mpllb_div2 = 1382 REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) | 1383 REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 134) | 1384 REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1), 1385 .mpllb_fracn1 = 1386 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) | 1387 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) | 1388 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535), 1389 .mpllb_fracn2 = 1390 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 60293) | 1391 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 7864), 1392 .mpllb_sscen = 1393 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1), 1394 }; 1395 1396 static const struct intel_mpllb_state dg2_hdmi_262750 = { 1397 .clock = 262750, 1398 .ref_control = 1399 REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3), 1400 .mpllb_cp = 1401 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 7) | 1402 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) | 1403 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) | 1404 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124), 1405 .mpllb_div = 1406 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) | 1407 REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 1) | 1408 REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) | 1409 REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) | 1410 REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 3), 1411 .mpllb_div2 = 1412 REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) | 1413 REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 72) | 1414 REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1), 1415 .mpllb_fracn1 = 1416 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) | 1417 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) | 1418 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535), 1419 .mpllb_fracn2 = 1420 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 36044) | 1421 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 52427), 1422 .mpllb_sscen = 1423 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1), 1424 }; 1425 1426 static const struct intel_mpllb_state dg2_hdmi_267300 = { 1427 .clock = 267300, 1428 .ref_control = 1429 REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3), 1430 .mpllb_cp = 1431 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 7) | 1432 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) | 1433 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) | 1434 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124), 1435 .mpllb_div = 1436 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) | 1437 REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 1) | 1438 REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) | 1439 REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) | 1440 REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 3), 1441 .mpllb_div2 = 1442 REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) | 1443 REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 74) | 1444 REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1), 1445 .mpllb_fracn1 = 1446 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) | 1447 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) | 1448 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535), 1449 .mpllb_fracn2 = 1450 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 30146) | 1451 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 36699), 1452 .mpllb_sscen = 1453 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1), 1454 }; 1455 1456 static const struct intel_mpllb_state dg2_hdmi_268500 = { 1457 .clock = 268500, 1458 .ref_control = 1459 REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3), 1460 .mpllb_cp = 1461 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 7) | 1462 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) | 1463 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) | 1464 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124), 1465 .mpllb_div = 1466 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) | 1467 REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 1) | 1468 REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) | 1469 REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) | 1470 REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 3), 1471 .mpllb_div2 = 1472 REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) | 1473 REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 74) | 1474 REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1), 1475 .mpllb_fracn1 = 1476 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) | 1477 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) | 1478 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535), 1479 .mpllb_fracn2 = 1480 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 45875) | 1481 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 13107), 1482 .mpllb_sscen = 1483 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1), 1484 }; 1485 1486 static const struct intel_mpllb_state dg2_hdmi_296703 = { 1487 .clock = 296703, 1488 .ref_control = 1489 REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3), 1490 .mpllb_cp = 1491 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) | 1492 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) | 1493 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) | 1494 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124), 1495 .mpllb_div = 1496 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) | 1497 REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 1) | 1498 REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) | 1499 REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) | 1500 REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 3), 1501 .mpllb_div2 = 1502 REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) | 1503 REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 86) | 1504 REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1), 1505 .mpllb_fracn1 = 1506 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) | 1507 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) | 1508 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535), 1509 .mpllb_fracn2 = 1510 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 22321) | 1511 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 36804), 1512 .mpllb_sscen = 1513 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1), 1514 }; 1515 1516 static const struct intel_mpllb_state dg2_hdmi_241500 = { 1517 .clock = 241500, 1518 .ref_control = 1519 REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3), 1520 .mpllb_cp = 1521 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) | 1522 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) | 1523 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) | 1524 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124), 1525 .mpllb_div = 1526 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) | 1527 REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 2) | 1528 REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) | 1529 REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) | 1530 REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 0), 1531 .mpllb_div2 = 1532 REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) | 1533 REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 160) | 1534 REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1), 1535 .mpllb_fracn1 = 1536 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) | 1537 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) | 1538 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535), 1539 .mpllb_fracn2 = 1540 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 39321) | 1541 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 39320), 1542 .mpllb_sscen = 1543 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1), 1544 }; 1545 1546 static const struct intel_mpllb_state dg2_hdmi_319890 = { 1547 .clock = 319890, 1548 .ref_control = 1549 REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3), 1550 .mpllb_cp = 1551 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) | 1552 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) | 1553 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) | 1554 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124), 1555 .mpllb_div = 1556 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) | 1557 REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 1) | 1558 REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) | 1559 REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) | 1560 REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 2), 1561 .mpllb_div2 = 1562 REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) | 1563 REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 94) | 1564 REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1), 1565 .mpllb_fracn1 = 1566 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) | 1567 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) | 1568 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535), 1569 .mpllb_fracn2 = 1570 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 64094) | 1571 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 13631), 1572 .mpllb_sscen = 1573 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1), 1574 }; 1575 1576 static const struct intel_mpllb_state dg2_hdmi_497750 = { 1577 .clock = 497750, 1578 .ref_control = 1579 REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3), 1580 .mpllb_cp = 1581 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) | 1582 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 15) | 1583 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) | 1584 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124), 1585 .mpllb_div = 1586 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) | 1587 REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 1) | 1588 REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) | 1589 REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) | 1590 REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 0), 1591 .mpllb_div2 = 1592 REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) | 1593 REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 166) | 1594 REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1), 1595 .mpllb_fracn1 = 1596 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) | 1597 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) | 1598 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535), 1599 .mpllb_fracn2 = 1600 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 36044) | 1601 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 52427), 1602 .mpllb_sscen = 1603 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1), 1604 }; 1605 1606 static const struct intel_mpllb_state dg2_hdmi_592000 = { 1607 .clock = 592000, 1608 .ref_control = 1609 REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3), 1610 .mpllb_cp = 1611 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) | 1612 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) | 1613 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) | 1614 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124), 1615 .mpllb_div = 1616 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) | 1617 REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 0) | 1618 REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) | 1619 REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) | 1620 REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 3), 1621 .mpllb_div2 = 1622 REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) | 1623 REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 86) | 1624 REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1), 1625 .mpllb_fracn1 = 1626 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) | 1627 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) | 1628 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535), 1629 .mpllb_fracn2 = 1630 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 13107) | 1631 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 13107), 1632 .mpllb_sscen = 1633 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1), 1634 }; 1635 1636 static const struct intel_mpllb_state dg2_hdmi_593407 = { 1637 .clock = 593407, 1638 .ref_control = 1639 REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3), 1640 .mpllb_cp = 1641 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) | 1642 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) | 1643 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) | 1644 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124), 1645 .mpllb_div = 1646 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) | 1647 REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 0) | 1648 REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) | 1649 REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) | 1650 REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 3), 1651 .mpllb_div2 = 1652 REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) | 1653 REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 86) | 1654 REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1), 1655 .mpllb_fracn1 = 1656 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) | 1657 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) | 1658 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535), 1659 .mpllb_fracn2 = 1660 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 22328) | 1661 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 7549), 1662 .mpllb_sscen = 1663 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1), 1664 }; 1665 1666 static const struct intel_mpllb_state dg2_hdmi_297 = { 1667 .clock = 297000, 1668 .ref_control = 1669 REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3), 1670 .mpllb_cp = 1671 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) | 1672 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) | 1673 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) | 1674 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124), 1675 .mpllb_div = 1676 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) | 1677 REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 1) | 1678 REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) | 1679 REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) | 1680 REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 3), 1681 .mpllb_div2 = 1682 REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) | 1683 REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 86) | 1684 REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1), 1685 .mpllb_fracn1 = 1686 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) | 1687 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) | 1688 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535), 1689 .mpllb_fracn2 = 1690 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 26214) | 1691 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 26214), 1692 .mpllb_sscen = 1693 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1), 1694 }; 1695 1696 static const struct intel_mpllb_state dg2_hdmi_594 = { 1697 .clock = 594000, 1698 .ref_control = 1699 REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3), 1700 .mpllb_cp = 1701 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 4) | 1702 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 15) | 1703 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) | 1704 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124), 1705 .mpllb_div = 1706 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) | 1707 REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) | 1708 REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) | 1709 REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 3), 1710 .mpllb_div2 = 1711 REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) | 1712 REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 86) | 1713 REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1), 1714 .mpllb_fracn1 = 1715 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) | 1716 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) | 1717 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 5), 1718 .mpllb_fracn2 = 1719 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 26214) | 1720 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 2), 1721 .mpllb_sscen = 1722 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1), 1723 }; 1724 1725 static const struct intel_mpllb_state * const dg2_hdmi_tables[] = { 1726 &dg2_hdmi_25_175, 1727 &dg2_hdmi_27_0, 1728 &dg2_hdmi_74_25, 1729 &dg2_hdmi_148_5, 1730 &dg2_hdmi_297, 1731 &dg2_hdmi_594, 1732 &dg2_hdmi_25200, 1733 &dg2_hdmi_27027, 1734 &dg2_hdmi_28320, 1735 &dg2_hdmi_30240, 1736 &dg2_hdmi_31500, 1737 &dg2_hdmi_36000, 1738 &dg2_hdmi_40000, 1739 &dg2_hdmi_49500, 1740 &dg2_hdmi_50000, 1741 &dg2_hdmi_57284, 1742 &dg2_hdmi_58000, 1743 &dg2_hdmi_65000, 1744 &dg2_hdmi_71000, 1745 &dg2_hdmi_74176, 1746 &dg2_hdmi_75000, 1747 &dg2_hdmi_78750, 1748 &dg2_hdmi_85500, 1749 &dg2_hdmi_88750, 1750 &dg2_hdmi_106500, 1751 &dg2_hdmi_108000, 1752 &dg2_hdmi_115500, 1753 &dg2_hdmi_119000, 1754 &dg2_hdmi_135000, 1755 &dg2_hdmi_138500, 1756 &dg2_hdmi_147160, 1757 &dg2_hdmi_148352, 1758 &dg2_hdmi_154000, 1759 &dg2_hdmi_162000, 1760 &dg2_hdmi_209800, 1761 &dg2_hdmi_241500, 1762 &dg2_hdmi_262750, 1763 &dg2_hdmi_267300, 1764 &dg2_hdmi_268500, 1765 &dg2_hdmi_296703, 1766 &dg2_hdmi_319890, 1767 &dg2_hdmi_497750, 1768 &dg2_hdmi_592000, 1769 &dg2_hdmi_593407, 1770 NULL, 1771 }; 1772 1773 static const struct intel_mpllb_state * const * 1774 intel_mpllb_tables_get(struct intel_crtc_state *crtc_state, 1775 struct intel_encoder *encoder) 1776 { 1777 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) { 1778 return dg2_edp_tables; 1779 } else if (intel_crtc_has_dp_encoder(crtc_state)) { 1780 return dg2_dp_100_tables; 1781 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { 1782 return dg2_hdmi_tables; 1783 } 1784 1785 MISSING_CASE(encoder->type); 1786 return NULL; 1787 } 1788 1789 int intel_mpllb_calc_state(struct intel_crtc_state *crtc_state, 1790 struct intel_encoder *encoder) 1791 { 1792 const struct intel_mpllb_state * const *tables; 1793 int i; 1794 1795 tables = intel_mpllb_tables_get(crtc_state, encoder); 1796 if (!tables) 1797 return -EINVAL; 1798 1799 for (i = 0; tables[i]; i++) { 1800 if (crtc_state->port_clock == tables[i]->clock) { 1801 crtc_state->dpll_hw_state.mpllb = *tables[i]; 1802 return 0; 1803 } 1804 } 1805 1806 /* For HDMI PLLs try SNPS PHY algorithm, if there are no precomputed tables */ 1807 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { 1808 intel_snps_hdmi_pll_compute_mpllb(&crtc_state->dpll_hw_state.mpllb, 1809 crtc_state->port_clock); 1810 1811 return 0; 1812 } 1813 1814 return -EINVAL; 1815 } 1816 1817 void intel_mpllb_enable(struct intel_encoder *encoder, 1818 const struct intel_crtc_state *crtc_state) 1819 { 1820 struct intel_display *display = to_intel_display(encoder); 1821 const struct intel_mpllb_state *pll_state = &crtc_state->dpll_hw_state.mpllb; 1822 enum phy phy = intel_encoder_to_phy(encoder); 1823 i915_reg_t enable_reg = (phy <= PHY_D ? 1824 DG2_PLL_ENABLE(phy) : MG_PLL_ENABLE(0)); 1825 1826 /* 1827 * 3. Software programs the following PLL registers for the desired 1828 * frequency. 1829 */ 1830 intel_de_write(display, SNPS_PHY_MPLLB_CP(phy), pll_state->mpllb_cp); 1831 intel_de_write(display, SNPS_PHY_MPLLB_DIV(phy), pll_state->mpllb_div); 1832 intel_de_write(display, SNPS_PHY_MPLLB_DIV2(phy), pll_state->mpllb_div2); 1833 intel_de_write(display, SNPS_PHY_MPLLB_SSCEN(phy), pll_state->mpllb_sscen); 1834 intel_de_write(display, SNPS_PHY_MPLLB_SSCSTEP(phy), pll_state->mpllb_sscstep); 1835 intel_de_write(display, SNPS_PHY_MPLLB_FRACN1(phy), pll_state->mpllb_fracn1); 1836 intel_de_write(display, SNPS_PHY_MPLLB_FRACN2(phy), pll_state->mpllb_fracn2); 1837 1838 /* 1839 * 4. If the frequency will result in a change to the voltage 1840 * requirement, follow the Display Voltage Frequency Switching - 1841 * Sequence Before Frequency Change. 1842 * 1843 * We handle this step in bxt_set_cdclk(). 1844 */ 1845 1846 /* 5. Software sets DPLL_ENABLE [PLL Enable] to "1". */ 1847 intel_de_rmw(display, enable_reg, 0, PLL_ENABLE); 1848 1849 /* 1850 * 9. Software sets SNPS_PHY_MPLLB_DIV dp_mpllb_force_en to "1". This 1851 * will keep the PLL running during the DDI lane programming and any 1852 * typeC DP cable disconnect. Do not set the force before enabling the 1853 * PLL because that will start the PLL before it has sampled the 1854 * divider values. 1855 */ 1856 intel_de_write(display, SNPS_PHY_MPLLB_DIV(phy), 1857 pll_state->mpllb_div | SNPS_PHY_MPLLB_FORCE_EN); 1858 1859 /* 1860 * 10. Software polls on register DPLL_ENABLE [PLL Lock] to confirm PLL 1861 * is locked at new settings. This register bit is sampling PHY 1862 * dp_mpllb_state interface signal. 1863 */ 1864 if (intel_de_wait_for_set(display, enable_reg, PLL_LOCK, 5)) 1865 drm_dbg_kms(display->drm, "Port %c PLL not locked\n", phy_name(phy)); 1866 1867 /* 1868 * 11. If the frequency will result in a change to the voltage 1869 * requirement, follow the Display Voltage Frequency Switching - 1870 * Sequence After Frequency Change. 1871 * 1872 * We handle this step in bxt_set_cdclk(). 1873 */ 1874 } 1875 1876 void intel_mpllb_disable(struct intel_encoder *encoder) 1877 { 1878 struct intel_display *display = to_intel_display(encoder); 1879 enum phy phy = intel_encoder_to_phy(encoder); 1880 i915_reg_t enable_reg = (phy <= PHY_D ? 1881 DG2_PLL_ENABLE(phy) : MG_PLL_ENABLE(0)); 1882 1883 /* 1884 * 1. If the frequency will result in a change to the voltage 1885 * requirement, follow the Display Voltage Frequency Switching - 1886 * Sequence Before Frequency Change. 1887 * 1888 * We handle this step in bxt_set_cdclk(). 1889 */ 1890 1891 /* 2. Software programs DPLL_ENABLE [PLL Enable] to "0" */ 1892 intel_de_rmw(display, enable_reg, PLL_ENABLE, 0); 1893 1894 /* 1895 * 4. Software programs SNPS_PHY_MPLLB_DIV dp_mpllb_force_en to "0". 1896 * This will allow the PLL to stop running. 1897 */ 1898 intel_de_rmw(display, SNPS_PHY_MPLLB_DIV(phy), SNPS_PHY_MPLLB_FORCE_EN, 0); 1899 1900 /* 1901 * 5. Software polls DPLL_ENABLE [PLL Lock] for PHY acknowledgment 1902 * (dp_txX_ack) that the new transmitter setting request is completed. 1903 */ 1904 if (intel_de_wait_for_clear(display, enable_reg, PLL_LOCK, 5)) 1905 drm_err(display->drm, "Port %c PLL not locked\n", phy_name(phy)); 1906 1907 /* 1908 * 6. If the frequency will result in a change to the voltage 1909 * requirement, follow the Display Voltage Frequency Switching - 1910 * Sequence After Frequency Change. 1911 * 1912 * We handle this step in bxt_set_cdclk(). 1913 */ 1914 } 1915 1916 int intel_mpllb_calc_port_clock(struct intel_encoder *encoder, 1917 const struct intel_mpllb_state *pll_state) 1918 { 1919 unsigned int frac_quot = 0, frac_rem = 0, frac_den = 1; 1920 unsigned int multiplier, tx_clk_div, refclk; 1921 bool frac_en; 1922 1923 if (0) 1924 refclk = 38400; 1925 else 1926 refclk = 100000; 1927 1928 refclk >>= REG_FIELD_GET(SNPS_PHY_MPLLB_REF_CLK_DIV, pll_state->mpllb_div2) - 1; 1929 1930 frac_en = REG_FIELD_GET(SNPS_PHY_MPLLB_FRACN_EN, pll_state->mpllb_fracn1); 1931 1932 if (frac_en) { 1933 frac_quot = REG_FIELD_GET(SNPS_PHY_MPLLB_FRACN_QUOT, pll_state->mpllb_fracn2); 1934 frac_rem = REG_FIELD_GET(SNPS_PHY_MPLLB_FRACN_REM, pll_state->mpllb_fracn2); 1935 frac_den = REG_FIELD_GET(SNPS_PHY_MPLLB_FRACN_DEN, pll_state->mpllb_fracn1); 1936 } 1937 1938 multiplier = REG_FIELD_GET(SNPS_PHY_MPLLB_MULTIPLIER, pll_state->mpllb_div2) / 2 + 16; 1939 1940 tx_clk_div = REG_FIELD_GET(SNPS_PHY_MPLLB_TX_CLK_DIV, pll_state->mpllb_div); 1941 1942 return DIV_ROUND_CLOSEST_ULL(mul_u32_u32(refclk, (multiplier << 16) + frac_quot) + 1943 DIV_ROUND_CLOSEST(refclk * frac_rem, frac_den), 1944 10 << (tx_clk_div + 16)); 1945 } 1946 1947 void intel_mpllb_readout_hw_state(struct intel_encoder *encoder, 1948 struct intel_mpllb_state *pll_state) 1949 { 1950 struct intel_display *display = to_intel_display(encoder); 1951 enum phy phy = intel_encoder_to_phy(encoder); 1952 1953 pll_state->mpllb_cp = intel_de_read(display, SNPS_PHY_MPLLB_CP(phy)); 1954 pll_state->mpllb_div = intel_de_read(display, SNPS_PHY_MPLLB_DIV(phy)); 1955 pll_state->mpllb_div2 = intel_de_read(display, SNPS_PHY_MPLLB_DIV2(phy)); 1956 pll_state->mpllb_sscen = intel_de_read(display, SNPS_PHY_MPLLB_SSCEN(phy)); 1957 pll_state->mpllb_sscstep = intel_de_read(display, SNPS_PHY_MPLLB_SSCSTEP(phy)); 1958 pll_state->mpllb_fracn1 = intel_de_read(display, SNPS_PHY_MPLLB_FRACN1(phy)); 1959 pll_state->mpllb_fracn2 = intel_de_read(display, SNPS_PHY_MPLLB_FRACN2(phy)); 1960 1961 /* 1962 * REF_CONTROL is under firmware control and never programmed by the 1963 * driver; we read it only for sanity checking purposes. The bspec 1964 * only tells us the expected value for one field in this register, 1965 * so we'll only read out those specific bits here. 1966 */ 1967 pll_state->ref_control = intel_de_read(display, SNPS_PHY_REF_CONTROL(phy)) & 1968 SNPS_PHY_REF_CONTROL_REF_RANGE; 1969 1970 /* 1971 * MPLLB_DIV is programmed twice, once with the software-computed 1972 * state, then again with the MPLLB_FORCE_EN bit added. Drop that 1973 * extra bit during readout so that we return the actual expected 1974 * software state. 1975 */ 1976 pll_state->mpllb_div &= ~SNPS_PHY_MPLLB_FORCE_EN; 1977 } 1978 1979 void intel_mpllb_state_verify(struct intel_atomic_state *state, 1980 struct intel_crtc *crtc) 1981 { 1982 struct intel_display *display = to_intel_display(state); 1983 const struct intel_crtc_state *new_crtc_state = 1984 intel_atomic_get_new_crtc_state(state, crtc); 1985 struct intel_mpllb_state mpllb_hw_state = {}; 1986 const struct intel_mpllb_state *mpllb_sw_state = &new_crtc_state->dpll_hw_state.mpllb; 1987 struct intel_encoder *encoder; 1988 1989 if (!display->platform.dg2) 1990 return; 1991 1992 if (!new_crtc_state->hw.active) 1993 return; 1994 1995 /* intel_get_crtc_new_encoder() only works for modeset/fastset commits */ 1996 if (!intel_crtc_needs_modeset(new_crtc_state) && 1997 !intel_crtc_needs_fastset(new_crtc_state)) 1998 return; 1999 2000 encoder = intel_get_crtc_new_encoder(state, new_crtc_state); 2001 intel_mpllb_readout_hw_state(encoder, &mpllb_hw_state); 2002 2003 #define MPLLB_CHECK(__name) \ 2004 INTEL_DISPLAY_STATE_WARN(display, mpllb_sw_state->__name != mpllb_hw_state.__name, \ 2005 "[CRTC:%d:%s] mismatch in MPLLB: %s (expected 0x%08x, found 0x%08x)", \ 2006 crtc->base.base.id, crtc->base.name, \ 2007 __stringify(__name), \ 2008 mpllb_sw_state->__name, mpllb_hw_state.__name) 2009 2010 MPLLB_CHECK(mpllb_cp); 2011 MPLLB_CHECK(mpllb_div); 2012 MPLLB_CHECK(mpllb_div2); 2013 MPLLB_CHECK(mpllb_fracn1); 2014 MPLLB_CHECK(mpllb_fracn2); 2015 MPLLB_CHECK(mpllb_sscen); 2016 MPLLB_CHECK(mpllb_sscstep); 2017 2018 /* 2019 * ref_control is handled by the hardware/firemware and never 2020 * programmed by the software, but the proper values are supplied 2021 * in the bspec for verification purposes. 2022 */ 2023 MPLLB_CHECK(ref_control); 2024 2025 #undef MPLLB_CHECK 2026 } 2027