1 /* 2 * Copyright 2006 Dave Airlie <airlied@linux.ie> 3 * Copyright © 2006-2007 Intel Corporation 4 * Jesse Barnes <jesse.barnes@intel.com> 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice (including the next 14 * paragraph) shall be included in all copies or substantial portions of the 15 * Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 23 * DEALINGS IN THE SOFTWARE. 24 * 25 * Authors: 26 * Eric Anholt <eric@anholt.net> 27 */ 28 29 #include <linux/delay.h> 30 #include <linux/export.h> 31 #include <linux/i2c.h> 32 #include <linux/slab.h> 33 34 #include <drm/display/drm_hdmi_helper.h> 35 #include <drm/drm_atomic_helper.h> 36 #include <drm/drm_crtc.h> 37 #include <drm/drm_edid.h> 38 #include <drm/drm_eld.h> 39 #include <drm/drm_print.h> 40 #include <drm/drm_probe_helper.h> 41 42 #include "intel_atomic.h" 43 #include "intel_audio.h" 44 #include "intel_connector.h" 45 #include "intel_crtc.h" 46 #include "intel_de.h" 47 #include "intel_display_driver.h" 48 #include "intel_display_regs.h" 49 #include "intel_display_types.h" 50 #include "intel_fifo_underrun.h" 51 #include "intel_gmbus.h" 52 #include "intel_hdmi.h" 53 #include "intel_hotplug.h" 54 #include "intel_link_bw.h" 55 #include "intel_panel.h" 56 #include "intel_sdvo.h" 57 #include "intel_sdvo_regs.h" 58 59 #define SDVO_TMDS_MASK (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_TMDS1) 60 #define SDVO_RGB_MASK (SDVO_OUTPUT_RGB0 | SDVO_OUTPUT_RGB1) 61 #define SDVO_LVDS_MASK (SDVO_OUTPUT_LVDS0 | SDVO_OUTPUT_LVDS1) 62 #define SDVO_TV_MASK (SDVO_OUTPUT_CVBS0 | SDVO_OUTPUT_SVID0 | SDVO_OUTPUT_YPRPB0) 63 64 #define SDVO_OUTPUT_MASK (SDVO_TMDS_MASK | SDVO_RGB_MASK | SDVO_LVDS_MASK | SDVO_TV_MASK) 65 66 #define IS_TV(c) ((c)->output_flag & SDVO_TV_MASK) 67 #define IS_TMDS(c) ((c)->output_flag & SDVO_TMDS_MASK) 68 #define IS_LVDS(c) ((c)->output_flag & SDVO_LVDS_MASK) 69 #define IS_TV_OR_LVDS(c) ((c)->output_flag & (SDVO_TV_MASK | SDVO_LVDS_MASK)) 70 #define IS_DIGITAL(c) ((c)->output_flag & (SDVO_TMDS_MASK | SDVO_LVDS_MASK)) 71 72 #define HAS_DDC(c) ((c)->output_flag & (SDVO_RGB_MASK | SDVO_TMDS_MASK | \ 73 SDVO_LVDS_MASK)) 74 75 static const char * const tv_format_names[] = { 76 "NTSC_M" , "NTSC_J" , "NTSC_443", 77 "PAL_B" , "PAL_D" , "PAL_G" , 78 "PAL_H" , "PAL_I" , "PAL_M" , 79 "PAL_N" , "PAL_NC" , "PAL_60" , 80 "SECAM_B" , "SECAM_D" , "SECAM_G" , 81 "SECAM_K" , "SECAM_K1", "SECAM_L" , 82 "SECAM_60" 83 }; 84 85 #define TV_FORMAT_NUM ARRAY_SIZE(tv_format_names) 86 87 struct intel_sdvo; 88 89 struct intel_sdvo_ddc { 90 struct i2c_adapter ddc; 91 struct intel_sdvo *sdvo; 92 u8 ddc_bus; 93 }; 94 95 struct intel_sdvo { 96 struct intel_encoder base; 97 98 struct i2c_adapter *i2c; 99 u8 target_addr; 100 101 struct intel_sdvo_ddc ddc[3]; 102 103 /* Register for the SDVO device: SDVOB or SDVOC */ 104 intel_reg_t sdvo_reg; 105 106 /* 107 * Capabilities of the SDVO device returned by 108 * intel_sdvo_get_capabilities() 109 */ 110 struct intel_sdvo_caps caps; 111 112 u8 colorimetry_cap; 113 114 /* Pixel clock limitations reported by the SDVO device, in kHz */ 115 int pixel_clock_min, pixel_clock_max; 116 117 /* 118 * Hotplug activation bits for this device 119 */ 120 u16 hotplug_active; 121 122 /* 123 * the sdvo flag gets lost in round trip: dtd->adjusted_mode->dtd 124 */ 125 u8 dtd_sdvo_flags; 126 }; 127 128 struct intel_sdvo_connector { 129 struct intel_connector base; 130 131 /* Mark the type of connector */ 132 u16 output_flag; 133 134 /* This contains all current supported TV format */ 135 u8 tv_format_supported[TV_FORMAT_NUM]; 136 int format_supported_num; 137 struct drm_property *tv_format; 138 139 /* add the property for the SDVO-TV */ 140 struct drm_property *left; 141 struct drm_property *right; 142 struct drm_property *top; 143 struct drm_property *bottom; 144 struct drm_property *hpos; 145 struct drm_property *vpos; 146 struct drm_property *contrast; 147 struct drm_property *saturation; 148 struct drm_property *hue; 149 struct drm_property *sharpness; 150 struct drm_property *flicker_filter; 151 struct drm_property *flicker_filter_adaptive; 152 struct drm_property *flicker_filter_2d; 153 struct drm_property *tv_chroma_filter; 154 struct drm_property *tv_luma_filter; 155 struct drm_property *dot_crawl; 156 157 /* add the property for the SDVO-TV/LVDS */ 158 struct drm_property *brightness; 159 160 /* this is to get the range of margin.*/ 161 u32 max_hscan, max_vscan; 162 163 /** 164 * This is set if we treat the device as HDMI, instead of DVI. 165 */ 166 bool is_hdmi; 167 }; 168 169 struct intel_sdvo_connector_state { 170 /* base.base: tv.saturation/contrast/hue/brightness */ 171 struct intel_digital_connector_state base; 172 173 struct { 174 unsigned overscan_h, overscan_v, hpos, vpos, sharpness; 175 unsigned flicker_filter, flicker_filter_2d, flicker_filter_adaptive; 176 unsigned chroma_filter, luma_filter, dot_crawl; 177 } tv; 178 }; 179 180 static struct intel_sdvo *to_sdvo(struct intel_encoder *encoder) 181 { 182 return container_of(encoder, struct intel_sdvo, base); 183 } 184 185 static struct intel_sdvo *intel_attached_sdvo(struct intel_connector *connector) 186 { 187 return to_sdvo(intel_attached_encoder(connector)); 188 } 189 190 static struct intel_sdvo_connector * 191 to_intel_sdvo_connector(struct drm_connector *connector) 192 { 193 return container_of(connector, struct intel_sdvo_connector, base.base); 194 } 195 196 #define to_intel_sdvo_connector_state(conn_state) \ 197 container_of_const((conn_state), struct intel_sdvo_connector_state, base.base) 198 199 static bool 200 intel_sdvo_output_setup(struct intel_sdvo *intel_sdvo); 201 static bool 202 intel_sdvo_tv_create_property(struct intel_sdvo *intel_sdvo, 203 struct intel_sdvo_connector *intel_sdvo_connector, 204 int type); 205 static bool 206 intel_sdvo_create_enhance_property(struct intel_sdvo *intel_sdvo, 207 struct intel_sdvo_connector *intel_sdvo_connector); 208 209 /* 210 * Writes the SDVOB or SDVOC with the given value, but always writes both 211 * SDVOB and SDVOC to work around apparent hardware issues (according to 212 * comments in the BIOS). 213 */ 214 static void intel_sdvo_write_sdvox(struct intel_sdvo *intel_sdvo, u32 val) 215 { 216 struct intel_display *display = to_intel_display(&intel_sdvo->base); 217 u32 bval = val, cval = val; 218 int i; 219 220 if (HAS_PCH_SPLIT(display)) { 221 intel_de_write(display, intel_sdvo->sdvo_reg, val); 222 intel_de_posting_read(display, intel_sdvo->sdvo_reg); 223 /* 224 * HW workaround, need to write this twice for issue 225 * that may result in first write getting masked. 226 */ 227 if (HAS_PCH_IBX(display)) { 228 intel_de_write(display, intel_sdvo->sdvo_reg, val); 229 intel_de_posting_read(display, intel_sdvo->sdvo_reg); 230 } 231 return; 232 } 233 234 if (intel_sdvo->base.port == PORT_B) 235 cval = intel_de_read(display, GEN3_SDVOC); 236 else 237 bval = intel_de_read(display, GEN3_SDVOB); 238 239 /* 240 * Write the registers twice for luck. Sometimes, 241 * writing them only once doesn't appear to 'stick'. 242 * The BIOS does this too. Yay, magic 243 */ 244 for (i = 0; i < 2; i++) { 245 intel_de_write(display, GEN3_SDVOB, bval); 246 intel_de_posting_read(display, GEN3_SDVOB); 247 248 intel_de_write(display, GEN3_SDVOC, cval); 249 intel_de_posting_read(display, GEN3_SDVOC); 250 } 251 } 252 253 static bool intel_sdvo_read_byte(struct intel_sdvo *intel_sdvo, u8 addr, u8 *ch) 254 { 255 struct intel_display *display = to_intel_display(&intel_sdvo->base); 256 struct i2c_msg msgs[] = { 257 { 258 .addr = intel_sdvo->target_addr, 259 .flags = 0, 260 .len = 1, 261 .buf = &addr, 262 }, 263 { 264 .addr = intel_sdvo->target_addr, 265 .flags = I2C_M_RD, 266 .len = 1, 267 .buf = ch, 268 } 269 }; 270 int ret; 271 272 if ((ret = i2c_transfer(intel_sdvo->i2c, msgs, 2)) == 2) 273 return true; 274 275 drm_dbg_kms(display->drm, "i2c transfer returned %d\n", ret); 276 return false; 277 } 278 279 #define SDVO_CMD_NAME_ENTRY(cmd_) { .cmd = SDVO_CMD_ ## cmd_, .name = #cmd_ } 280 281 /** Mapping of command numbers to names, for debug output */ 282 static const struct { 283 u8 cmd; 284 const char *name; 285 } __packed sdvo_cmd_names[] = { 286 SDVO_CMD_NAME_ENTRY(RESET), 287 SDVO_CMD_NAME_ENTRY(GET_DEVICE_CAPS), 288 SDVO_CMD_NAME_ENTRY(GET_FIRMWARE_REV), 289 SDVO_CMD_NAME_ENTRY(GET_TRAINED_INPUTS), 290 SDVO_CMD_NAME_ENTRY(GET_ACTIVE_OUTPUTS), 291 SDVO_CMD_NAME_ENTRY(SET_ACTIVE_OUTPUTS), 292 SDVO_CMD_NAME_ENTRY(GET_IN_OUT_MAP), 293 SDVO_CMD_NAME_ENTRY(SET_IN_OUT_MAP), 294 SDVO_CMD_NAME_ENTRY(GET_ATTACHED_DISPLAYS), 295 SDVO_CMD_NAME_ENTRY(GET_HOT_PLUG_SUPPORT), 296 SDVO_CMD_NAME_ENTRY(SET_ACTIVE_HOT_PLUG), 297 SDVO_CMD_NAME_ENTRY(GET_ACTIVE_HOT_PLUG), 298 SDVO_CMD_NAME_ENTRY(GET_INTERRUPT_EVENT_SOURCE), 299 SDVO_CMD_NAME_ENTRY(SET_TARGET_INPUT), 300 SDVO_CMD_NAME_ENTRY(SET_TARGET_OUTPUT), 301 SDVO_CMD_NAME_ENTRY(GET_INPUT_TIMINGS_PART1), 302 SDVO_CMD_NAME_ENTRY(GET_INPUT_TIMINGS_PART2), 303 SDVO_CMD_NAME_ENTRY(SET_INPUT_TIMINGS_PART1), 304 SDVO_CMD_NAME_ENTRY(SET_INPUT_TIMINGS_PART2), 305 SDVO_CMD_NAME_ENTRY(SET_OUTPUT_TIMINGS_PART1), 306 SDVO_CMD_NAME_ENTRY(SET_OUTPUT_TIMINGS_PART2), 307 SDVO_CMD_NAME_ENTRY(GET_OUTPUT_TIMINGS_PART1), 308 SDVO_CMD_NAME_ENTRY(GET_OUTPUT_TIMINGS_PART2), 309 SDVO_CMD_NAME_ENTRY(CREATE_PREFERRED_INPUT_TIMING), 310 SDVO_CMD_NAME_ENTRY(GET_PREFERRED_INPUT_TIMING_PART1), 311 SDVO_CMD_NAME_ENTRY(GET_PREFERRED_INPUT_TIMING_PART2), 312 SDVO_CMD_NAME_ENTRY(GET_INPUT_PIXEL_CLOCK_RANGE), 313 SDVO_CMD_NAME_ENTRY(GET_OUTPUT_PIXEL_CLOCK_RANGE), 314 SDVO_CMD_NAME_ENTRY(GET_SUPPORTED_CLOCK_RATE_MULTS), 315 SDVO_CMD_NAME_ENTRY(GET_CLOCK_RATE_MULT), 316 SDVO_CMD_NAME_ENTRY(SET_CLOCK_RATE_MULT), 317 SDVO_CMD_NAME_ENTRY(GET_SUPPORTED_TV_FORMATS), 318 SDVO_CMD_NAME_ENTRY(GET_TV_FORMAT), 319 SDVO_CMD_NAME_ENTRY(SET_TV_FORMAT), 320 SDVO_CMD_NAME_ENTRY(GET_SUPPORTED_POWER_STATES), 321 SDVO_CMD_NAME_ENTRY(GET_POWER_STATE), 322 SDVO_CMD_NAME_ENTRY(SET_ENCODER_POWER_STATE), 323 SDVO_CMD_NAME_ENTRY(SET_DISPLAY_POWER_STATE), 324 SDVO_CMD_NAME_ENTRY(SET_CONTROL_BUS_SWITCH), 325 SDVO_CMD_NAME_ENTRY(GET_SDTV_RESOLUTION_SUPPORT), 326 SDVO_CMD_NAME_ENTRY(GET_SCALED_HDTV_RESOLUTION_SUPPORT), 327 SDVO_CMD_NAME_ENTRY(GET_SUPPORTED_ENHANCEMENTS), 328 329 /* Add the op code for SDVO enhancements */ 330 SDVO_CMD_NAME_ENTRY(GET_MAX_HPOS), 331 SDVO_CMD_NAME_ENTRY(GET_HPOS), 332 SDVO_CMD_NAME_ENTRY(SET_HPOS), 333 SDVO_CMD_NAME_ENTRY(GET_MAX_VPOS), 334 SDVO_CMD_NAME_ENTRY(GET_VPOS), 335 SDVO_CMD_NAME_ENTRY(SET_VPOS), 336 SDVO_CMD_NAME_ENTRY(GET_MAX_SATURATION), 337 SDVO_CMD_NAME_ENTRY(GET_SATURATION), 338 SDVO_CMD_NAME_ENTRY(SET_SATURATION), 339 SDVO_CMD_NAME_ENTRY(GET_MAX_HUE), 340 SDVO_CMD_NAME_ENTRY(GET_HUE), 341 SDVO_CMD_NAME_ENTRY(SET_HUE), 342 SDVO_CMD_NAME_ENTRY(GET_MAX_CONTRAST), 343 SDVO_CMD_NAME_ENTRY(GET_CONTRAST), 344 SDVO_CMD_NAME_ENTRY(SET_CONTRAST), 345 SDVO_CMD_NAME_ENTRY(GET_MAX_BRIGHTNESS), 346 SDVO_CMD_NAME_ENTRY(GET_BRIGHTNESS), 347 SDVO_CMD_NAME_ENTRY(SET_BRIGHTNESS), 348 SDVO_CMD_NAME_ENTRY(GET_MAX_OVERSCAN_H), 349 SDVO_CMD_NAME_ENTRY(GET_OVERSCAN_H), 350 SDVO_CMD_NAME_ENTRY(SET_OVERSCAN_H), 351 SDVO_CMD_NAME_ENTRY(GET_MAX_OVERSCAN_V), 352 SDVO_CMD_NAME_ENTRY(GET_OVERSCAN_V), 353 SDVO_CMD_NAME_ENTRY(SET_OVERSCAN_V), 354 SDVO_CMD_NAME_ENTRY(GET_MAX_FLICKER_FILTER), 355 SDVO_CMD_NAME_ENTRY(GET_FLICKER_FILTER), 356 SDVO_CMD_NAME_ENTRY(SET_FLICKER_FILTER), 357 SDVO_CMD_NAME_ENTRY(GET_MAX_FLICKER_FILTER_ADAPTIVE), 358 SDVO_CMD_NAME_ENTRY(GET_FLICKER_FILTER_ADAPTIVE), 359 SDVO_CMD_NAME_ENTRY(SET_FLICKER_FILTER_ADAPTIVE), 360 SDVO_CMD_NAME_ENTRY(GET_MAX_FLICKER_FILTER_2D), 361 SDVO_CMD_NAME_ENTRY(GET_FLICKER_FILTER_2D), 362 SDVO_CMD_NAME_ENTRY(SET_FLICKER_FILTER_2D), 363 SDVO_CMD_NAME_ENTRY(GET_MAX_SHARPNESS), 364 SDVO_CMD_NAME_ENTRY(GET_SHARPNESS), 365 SDVO_CMD_NAME_ENTRY(SET_SHARPNESS), 366 SDVO_CMD_NAME_ENTRY(GET_DOT_CRAWL), 367 SDVO_CMD_NAME_ENTRY(SET_DOT_CRAWL), 368 SDVO_CMD_NAME_ENTRY(GET_MAX_TV_CHROMA_FILTER), 369 SDVO_CMD_NAME_ENTRY(GET_TV_CHROMA_FILTER), 370 SDVO_CMD_NAME_ENTRY(SET_TV_CHROMA_FILTER), 371 SDVO_CMD_NAME_ENTRY(GET_MAX_TV_LUMA_FILTER), 372 SDVO_CMD_NAME_ENTRY(GET_TV_LUMA_FILTER), 373 SDVO_CMD_NAME_ENTRY(SET_TV_LUMA_FILTER), 374 375 /* HDMI op code */ 376 SDVO_CMD_NAME_ENTRY(GET_SUPP_ENCODE), 377 SDVO_CMD_NAME_ENTRY(GET_ENCODE), 378 SDVO_CMD_NAME_ENTRY(SET_ENCODE), 379 SDVO_CMD_NAME_ENTRY(SET_PIXEL_REPLI), 380 SDVO_CMD_NAME_ENTRY(GET_PIXEL_REPLI), 381 SDVO_CMD_NAME_ENTRY(GET_COLORIMETRY_CAP), 382 SDVO_CMD_NAME_ENTRY(SET_COLORIMETRY), 383 SDVO_CMD_NAME_ENTRY(GET_COLORIMETRY), 384 SDVO_CMD_NAME_ENTRY(GET_AUDIO_ENCRYPT_PREFER), 385 SDVO_CMD_NAME_ENTRY(SET_AUDIO_STAT), 386 SDVO_CMD_NAME_ENTRY(GET_AUDIO_STAT), 387 SDVO_CMD_NAME_ENTRY(GET_HBUF_INDEX), 388 SDVO_CMD_NAME_ENTRY(SET_HBUF_INDEX), 389 SDVO_CMD_NAME_ENTRY(GET_HBUF_INFO), 390 SDVO_CMD_NAME_ENTRY(GET_HBUF_AV_SPLIT), 391 SDVO_CMD_NAME_ENTRY(SET_HBUF_AV_SPLIT), 392 SDVO_CMD_NAME_ENTRY(GET_HBUF_TXRATE), 393 SDVO_CMD_NAME_ENTRY(SET_HBUF_TXRATE), 394 SDVO_CMD_NAME_ENTRY(SET_HBUF_DATA), 395 SDVO_CMD_NAME_ENTRY(GET_HBUF_DATA), 396 }; 397 398 #undef SDVO_CMD_NAME_ENTRY 399 400 static const char *sdvo_cmd_name(u8 cmd) 401 { 402 int i; 403 404 for (i = 0; i < ARRAY_SIZE(sdvo_cmd_names); i++) { 405 if (cmd == sdvo_cmd_names[i].cmd) 406 return sdvo_cmd_names[i].name; 407 } 408 409 return NULL; 410 } 411 412 #define SDVO_NAME(svdo) ((svdo)->base.port == PORT_B ? "SDVOB" : "SDVOC") 413 414 static void intel_sdvo_debug_write(struct intel_sdvo *intel_sdvo, u8 cmd, 415 const void *args, int args_len) 416 { 417 struct intel_display *display = to_intel_display(&intel_sdvo->base); 418 const char *cmd_name; 419 int i, pos = 0; 420 char buffer[64]; 421 422 #define BUF_PRINT(args...) \ 423 pos += snprintf(buffer + pos, max_t(int, sizeof(buffer) - pos, 0), args) 424 425 for (i = 0; i < args_len; i++) { 426 BUF_PRINT("%02X ", ((u8 *)args)[i]); 427 } 428 for (; i < 8; i++) { 429 BUF_PRINT(" "); 430 } 431 432 cmd_name = sdvo_cmd_name(cmd); 433 if (cmd_name) 434 BUF_PRINT("(%s)", cmd_name); 435 else 436 BUF_PRINT("(%02X)", cmd); 437 438 drm_WARN_ON(display->drm, pos >= sizeof(buffer) - 1); 439 #undef BUF_PRINT 440 441 drm_dbg_kms(display->drm, "%s: W: %02X %s\n", SDVO_NAME(intel_sdvo), 442 cmd, buffer); 443 } 444 445 static const char * const cmd_status_names[] = { 446 [SDVO_CMD_STATUS_POWER_ON] = "Power on", 447 [SDVO_CMD_STATUS_SUCCESS] = "Success", 448 [SDVO_CMD_STATUS_NOTSUPP] = "Not supported", 449 [SDVO_CMD_STATUS_INVALID_ARG] = "Invalid arg", 450 [SDVO_CMD_STATUS_PENDING] = "Pending", 451 [SDVO_CMD_STATUS_TARGET_NOT_SPECIFIED] = "Target not specified", 452 [SDVO_CMD_STATUS_SCALING_NOT_SUPP] = "Scaling not supported", 453 }; 454 455 static const char *sdvo_cmd_status(u8 status) 456 { 457 if (status < ARRAY_SIZE(cmd_status_names)) 458 return cmd_status_names[status]; 459 else 460 return NULL; 461 } 462 463 static bool __intel_sdvo_write_cmd(struct intel_sdvo *intel_sdvo, u8 cmd, 464 const void *args, int args_len, 465 bool unlocked) 466 { 467 struct intel_display *display = to_intel_display(&intel_sdvo->base); 468 u8 *buf, status; 469 struct i2c_msg *msgs; 470 int i, ret = true; 471 472 /* Would be simpler to allocate both in one go ? */ 473 buf = kzalloc(args_len * 2 + 2, GFP_KERNEL); 474 if (!buf) 475 return false; 476 477 msgs = kzalloc_objs(*msgs, args_len + 3); 478 if (!msgs) { 479 kfree(buf); 480 return false; 481 } 482 483 intel_sdvo_debug_write(intel_sdvo, cmd, args, args_len); 484 485 for (i = 0; i < args_len; i++) { 486 msgs[i].addr = intel_sdvo->target_addr; 487 msgs[i].flags = 0; 488 msgs[i].len = 2; 489 msgs[i].buf = buf + 2 *i; 490 buf[2*i + 0] = SDVO_I2C_ARG_0 - i; 491 buf[2*i + 1] = ((u8*)args)[i]; 492 } 493 msgs[i].addr = intel_sdvo->target_addr; 494 msgs[i].flags = 0; 495 msgs[i].len = 2; 496 msgs[i].buf = buf + 2*i; 497 buf[2*i + 0] = SDVO_I2C_OPCODE; 498 buf[2*i + 1] = cmd; 499 500 /* the following two are to read the response */ 501 status = SDVO_I2C_CMD_STATUS; 502 msgs[i+1].addr = intel_sdvo->target_addr; 503 msgs[i+1].flags = 0; 504 msgs[i+1].len = 1; 505 msgs[i+1].buf = &status; 506 507 msgs[i+2].addr = intel_sdvo->target_addr; 508 msgs[i+2].flags = I2C_M_RD; 509 msgs[i+2].len = 1; 510 msgs[i+2].buf = &status; 511 512 if (unlocked) 513 ret = i2c_transfer(intel_sdvo->i2c, msgs, i+3); 514 else 515 ret = __i2c_transfer(intel_sdvo->i2c, msgs, i+3); 516 if (ret < 0) { 517 drm_dbg_kms(display->drm, "I2c transfer returned %d\n", ret); 518 ret = false; 519 goto out; 520 } 521 if (ret != i+3) { 522 /* failure in I2C transfer */ 523 drm_dbg_kms(display->drm, "I2c transfer returned %d/%d\n", ret, i + 3); 524 ret = false; 525 } 526 527 out: 528 kfree(msgs); 529 kfree(buf); 530 return ret; 531 } 532 533 static bool intel_sdvo_write_cmd(struct intel_sdvo *intel_sdvo, u8 cmd, 534 const void *args, int args_len) 535 { 536 return __intel_sdvo_write_cmd(intel_sdvo, cmd, args, args_len, true); 537 } 538 539 static bool intel_sdvo_read_response(struct intel_sdvo *intel_sdvo, 540 void *response, int response_len) 541 { 542 struct intel_display *display = to_intel_display(&intel_sdvo->base); 543 const char *cmd_status; 544 u8 retry = 15; /* 5 quick checks, followed by 10 long checks */ 545 u8 status; 546 int i, pos = 0; 547 char buffer[64]; 548 549 buffer[0] = '\0'; 550 551 /* 552 * The documentation states that all commands will be 553 * processed within 15µs, and that we need only poll 554 * the status byte a maximum of 3 times in order for the 555 * command to be complete. 556 * 557 * Check 5 times in case the hardware failed to read the docs. 558 * 559 * Also beware that the first response by many devices is to 560 * reply PENDING and stall for time. TVs are notorious for 561 * requiring longer than specified to complete their replies. 562 * Originally (in the DDX long ago), the delay was only ever 15ms 563 * with an additional delay of 30ms applied for TVs added later after 564 * many experiments. To accommodate both sets of delays, we do a 565 * sequence of slow checks if the device is falling behind and fails 566 * to reply within 5*15µs. 567 */ 568 if (!intel_sdvo_read_byte(intel_sdvo, 569 SDVO_I2C_CMD_STATUS, 570 &status)) 571 goto log_fail; 572 573 while ((status == SDVO_CMD_STATUS_PENDING || 574 status == SDVO_CMD_STATUS_TARGET_NOT_SPECIFIED) && --retry) { 575 if (retry < 10) 576 msleep(15); 577 else 578 udelay(15); 579 580 if (!intel_sdvo_read_byte(intel_sdvo, 581 SDVO_I2C_CMD_STATUS, 582 &status)) 583 goto log_fail; 584 } 585 586 #define BUF_PRINT(args...) \ 587 pos += snprintf(buffer + pos, max_t(int, sizeof(buffer) - pos, 0), args) 588 589 cmd_status = sdvo_cmd_status(status); 590 if (cmd_status) 591 BUF_PRINT("(%s)", cmd_status); 592 else 593 BUF_PRINT("(??? %d)", status); 594 595 if (status != SDVO_CMD_STATUS_SUCCESS) 596 goto log_fail; 597 598 /* Read the command response */ 599 for (i = 0; i < response_len; i++) { 600 if (!intel_sdvo_read_byte(intel_sdvo, 601 SDVO_I2C_RETURN_0 + i, 602 &((u8 *)response)[i])) 603 goto log_fail; 604 BUF_PRINT(" %02X", ((u8 *)response)[i]); 605 } 606 607 drm_WARN_ON(display->drm, pos >= sizeof(buffer) - 1); 608 #undef BUF_PRINT 609 610 drm_dbg_kms(display->drm, "%s: R: %s\n", 611 SDVO_NAME(intel_sdvo), buffer); 612 return true; 613 614 log_fail: 615 drm_dbg_kms(display->drm, "%s: R: ... failed %s\n", 616 SDVO_NAME(intel_sdvo), buffer); 617 return false; 618 } 619 620 static int intel_sdvo_get_pixel_multiplier(const struct drm_display_mode *adjusted_mode) 621 { 622 if (adjusted_mode->crtc_clock >= 100000) 623 return 1; 624 else if (adjusted_mode->crtc_clock >= 50000) 625 return 2; 626 else 627 return 4; 628 } 629 630 static bool __intel_sdvo_set_control_bus_switch(struct intel_sdvo *intel_sdvo, 631 u8 ddc_bus) 632 { 633 /* This must be the immediately preceding write before the i2c xfer */ 634 return __intel_sdvo_write_cmd(intel_sdvo, 635 SDVO_CMD_SET_CONTROL_BUS_SWITCH, 636 &ddc_bus, 1, false); 637 } 638 639 static bool intel_sdvo_set_value(struct intel_sdvo *intel_sdvo, u8 cmd, const void *data, int len) 640 { 641 if (!intel_sdvo_write_cmd(intel_sdvo, cmd, data, len)) 642 return false; 643 644 return intel_sdvo_read_response(intel_sdvo, NULL, 0); 645 } 646 647 static bool 648 intel_sdvo_get_value(struct intel_sdvo *intel_sdvo, u8 cmd, void *value, int len) 649 { 650 if (!intel_sdvo_write_cmd(intel_sdvo, cmd, NULL, 0)) 651 return false; 652 653 return intel_sdvo_read_response(intel_sdvo, value, len); 654 } 655 656 static bool intel_sdvo_set_target_input(struct intel_sdvo *intel_sdvo) 657 { 658 struct intel_sdvo_set_target_input_args targets = {}; 659 return intel_sdvo_set_value(intel_sdvo, 660 SDVO_CMD_SET_TARGET_INPUT, 661 &targets, sizeof(targets)); 662 } 663 664 /* 665 * Return whether each input is trained. 666 * 667 * This function is making an assumption about the layout of the response, 668 * which should be checked against the docs. 669 */ 670 static bool intel_sdvo_get_trained_inputs(struct intel_sdvo *intel_sdvo, bool *input_1, bool *input_2) 671 { 672 struct intel_sdvo_get_trained_inputs_response response; 673 674 BUILD_BUG_ON(sizeof(response) != 1); 675 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_TRAINED_INPUTS, 676 &response, sizeof(response))) 677 return false; 678 679 *input_1 = response.input0_trained; 680 *input_2 = response.input1_trained; 681 return true; 682 } 683 684 static bool intel_sdvo_set_active_outputs(struct intel_sdvo *intel_sdvo, 685 u16 outputs) 686 { 687 return intel_sdvo_set_value(intel_sdvo, 688 SDVO_CMD_SET_ACTIVE_OUTPUTS, 689 &outputs, sizeof(outputs)); 690 } 691 692 static bool intel_sdvo_get_active_outputs(struct intel_sdvo *intel_sdvo, 693 u16 *outputs) 694 { 695 return intel_sdvo_get_value(intel_sdvo, 696 SDVO_CMD_GET_ACTIVE_OUTPUTS, 697 outputs, sizeof(*outputs)); 698 } 699 700 static bool intel_sdvo_set_encoder_power_state(struct intel_sdvo *intel_sdvo, 701 int mode) 702 { 703 u8 state = SDVO_ENCODER_STATE_ON; 704 705 switch (mode) { 706 case DRM_MODE_DPMS_ON: 707 state = SDVO_ENCODER_STATE_ON; 708 break; 709 case DRM_MODE_DPMS_STANDBY: 710 state = SDVO_ENCODER_STATE_STANDBY; 711 break; 712 case DRM_MODE_DPMS_SUSPEND: 713 state = SDVO_ENCODER_STATE_SUSPEND; 714 break; 715 case DRM_MODE_DPMS_OFF: 716 state = SDVO_ENCODER_STATE_OFF; 717 break; 718 } 719 720 return intel_sdvo_set_value(intel_sdvo, 721 SDVO_CMD_SET_ENCODER_POWER_STATE, &state, sizeof(state)); 722 } 723 724 static bool intel_sdvo_get_input_pixel_clock_range(struct intel_sdvo *intel_sdvo, 725 int *clock_min, 726 int *clock_max) 727 { 728 struct intel_sdvo_pixel_clock_range clocks; 729 730 BUILD_BUG_ON(sizeof(clocks) != 4); 731 if (!intel_sdvo_get_value(intel_sdvo, 732 SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE, 733 &clocks, sizeof(clocks))) 734 return false; 735 736 /* Convert the values from units of 10 kHz to kHz. */ 737 *clock_min = clocks.min * 10; 738 *clock_max = clocks.max * 10; 739 return true; 740 } 741 742 static bool intel_sdvo_set_target_output(struct intel_sdvo *intel_sdvo, 743 u16 outputs) 744 { 745 return intel_sdvo_set_value(intel_sdvo, 746 SDVO_CMD_SET_TARGET_OUTPUT, 747 &outputs, sizeof(outputs)); 748 } 749 750 static bool intel_sdvo_set_timing(struct intel_sdvo *intel_sdvo, u8 cmd, 751 struct intel_sdvo_dtd *dtd) 752 { 753 return intel_sdvo_set_value(intel_sdvo, cmd, &dtd->part1, sizeof(dtd->part1)) && 754 intel_sdvo_set_value(intel_sdvo, cmd + 1, &dtd->part2, sizeof(dtd->part2)); 755 } 756 757 static bool intel_sdvo_get_timing(struct intel_sdvo *intel_sdvo, u8 cmd, 758 struct intel_sdvo_dtd *dtd) 759 { 760 return intel_sdvo_get_value(intel_sdvo, cmd, &dtd->part1, sizeof(dtd->part1)) && 761 intel_sdvo_get_value(intel_sdvo, cmd + 1, &dtd->part2, sizeof(dtd->part2)); 762 } 763 764 static bool intel_sdvo_set_input_timing(struct intel_sdvo *intel_sdvo, 765 struct intel_sdvo_dtd *dtd) 766 { 767 return intel_sdvo_set_timing(intel_sdvo, 768 SDVO_CMD_SET_INPUT_TIMINGS_PART1, dtd); 769 } 770 771 static bool intel_sdvo_set_output_timing(struct intel_sdvo *intel_sdvo, 772 struct intel_sdvo_dtd *dtd) 773 { 774 return intel_sdvo_set_timing(intel_sdvo, 775 SDVO_CMD_SET_OUTPUT_TIMINGS_PART1, dtd); 776 } 777 778 static bool intel_sdvo_get_input_timing(struct intel_sdvo *intel_sdvo, 779 struct intel_sdvo_dtd *dtd) 780 { 781 return intel_sdvo_get_timing(intel_sdvo, 782 SDVO_CMD_GET_INPUT_TIMINGS_PART1, dtd); 783 } 784 785 static bool 786 intel_sdvo_create_preferred_input_timing(struct intel_sdvo *intel_sdvo, 787 struct intel_sdvo_connector *intel_sdvo_connector, 788 const struct drm_display_mode *mode) 789 { 790 struct intel_sdvo_preferred_input_timing_args args; 791 792 memset(&args, 0, sizeof(args)); 793 args.clock = mode->clock / 10; 794 args.width = mode->hdisplay; 795 args.height = mode->vdisplay; 796 args.interlace = 0; 797 798 if (IS_LVDS(intel_sdvo_connector)) { 799 const struct drm_display_mode *fixed_mode = 800 intel_panel_fixed_mode(&intel_sdvo_connector->base, mode); 801 802 if (fixed_mode->hdisplay != args.width || 803 fixed_mode->vdisplay != args.height) 804 args.scaled = 1; 805 } 806 807 return intel_sdvo_set_value(intel_sdvo, 808 SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING, 809 &args, sizeof(args)); 810 } 811 812 static bool intel_sdvo_get_preferred_input_timing(struct intel_sdvo *intel_sdvo, 813 struct intel_sdvo_dtd *dtd) 814 { 815 BUILD_BUG_ON(sizeof(dtd->part1) != 8); 816 BUILD_BUG_ON(sizeof(dtd->part2) != 8); 817 return intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1, 818 &dtd->part1, sizeof(dtd->part1)) && 819 intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2, 820 &dtd->part2, sizeof(dtd->part2)); 821 } 822 823 static bool intel_sdvo_set_clock_rate_mult(struct intel_sdvo *intel_sdvo, u8 val) 824 { 825 return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_CLOCK_RATE_MULT, &val, 1); 826 } 827 828 static void intel_sdvo_get_dtd_from_mode(struct intel_sdvo_dtd *dtd, 829 const struct drm_display_mode *mode) 830 { 831 u16 width, height; 832 u16 h_blank_len, h_sync_len, v_blank_len, v_sync_len; 833 u16 h_sync_offset, v_sync_offset; 834 int mode_clock; 835 836 memset(dtd, 0, sizeof(*dtd)); 837 838 width = mode->hdisplay; 839 height = mode->vdisplay; 840 841 /* do some mode translations */ 842 h_blank_len = mode->htotal - mode->hdisplay; 843 h_sync_len = mode->hsync_end - mode->hsync_start; 844 845 v_blank_len = mode->vtotal - mode->vdisplay; 846 v_sync_len = mode->vsync_end - mode->vsync_start; 847 848 h_sync_offset = mode->hsync_start - mode->hdisplay; 849 v_sync_offset = mode->vsync_start - mode->vdisplay; 850 851 mode_clock = mode->clock; 852 mode_clock /= 10; 853 dtd->part1.clock = mode_clock; 854 855 dtd->part1.h_active = width & 0xff; 856 dtd->part1.h_blank = h_blank_len & 0xff; 857 dtd->part1.h_high = (((width >> 8) & 0xf) << 4) | 858 ((h_blank_len >> 8) & 0xf); 859 dtd->part1.v_active = height & 0xff; 860 dtd->part1.v_blank = v_blank_len & 0xff; 861 dtd->part1.v_high = (((height >> 8) & 0xf) << 4) | 862 ((v_blank_len >> 8) & 0xf); 863 864 dtd->part2.h_sync_off = h_sync_offset & 0xff; 865 dtd->part2.h_sync_width = h_sync_len & 0xff; 866 dtd->part2.v_sync_off_width = (v_sync_offset & 0xf) << 4 | 867 (v_sync_len & 0xf); 868 dtd->part2.sync_off_width_high = ((h_sync_offset & 0x300) >> 2) | 869 ((h_sync_len & 0x300) >> 4) | ((v_sync_offset & 0x30) >> 2) | 870 ((v_sync_len & 0x30) >> 4); 871 872 dtd->part2.dtd_flags = 0x18; 873 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 874 dtd->part2.dtd_flags |= DTD_FLAG_INTERLACE; 875 if (mode->flags & DRM_MODE_FLAG_PHSYNC) 876 dtd->part2.dtd_flags |= DTD_FLAG_HSYNC_POSITIVE; 877 if (mode->flags & DRM_MODE_FLAG_PVSYNC) 878 dtd->part2.dtd_flags |= DTD_FLAG_VSYNC_POSITIVE; 879 880 dtd->part2.v_sync_off_high = v_sync_offset & 0xc0; 881 } 882 883 static void intel_sdvo_get_mode_from_dtd(struct drm_display_mode *pmode, 884 const struct intel_sdvo_dtd *dtd) 885 { 886 struct drm_display_mode mode = {}; 887 888 mode.hdisplay = dtd->part1.h_active; 889 mode.hdisplay += ((dtd->part1.h_high >> 4) & 0x0f) << 8; 890 mode.hsync_start = mode.hdisplay + dtd->part2.h_sync_off; 891 mode.hsync_start += (dtd->part2.sync_off_width_high & 0xc0) << 2; 892 mode.hsync_end = mode.hsync_start + dtd->part2.h_sync_width; 893 mode.hsync_end += (dtd->part2.sync_off_width_high & 0x30) << 4; 894 mode.htotal = mode.hdisplay + dtd->part1.h_blank; 895 mode.htotal += (dtd->part1.h_high & 0xf) << 8; 896 897 mode.vdisplay = dtd->part1.v_active; 898 mode.vdisplay += ((dtd->part1.v_high >> 4) & 0x0f) << 8; 899 mode.vsync_start = mode.vdisplay; 900 mode.vsync_start += (dtd->part2.v_sync_off_width >> 4) & 0xf; 901 mode.vsync_start += (dtd->part2.sync_off_width_high & 0x0c) << 2; 902 mode.vsync_start += dtd->part2.v_sync_off_high & 0xc0; 903 mode.vsync_end = mode.vsync_start + 904 (dtd->part2.v_sync_off_width & 0xf); 905 mode.vsync_end += (dtd->part2.sync_off_width_high & 0x3) << 4; 906 mode.vtotal = mode.vdisplay + dtd->part1.v_blank; 907 mode.vtotal += (dtd->part1.v_high & 0xf) << 8; 908 909 mode.clock = dtd->part1.clock * 10; 910 911 if (dtd->part2.dtd_flags & DTD_FLAG_INTERLACE) 912 mode.flags |= DRM_MODE_FLAG_INTERLACE; 913 if (dtd->part2.dtd_flags & DTD_FLAG_HSYNC_POSITIVE) 914 mode.flags |= DRM_MODE_FLAG_PHSYNC; 915 else 916 mode.flags |= DRM_MODE_FLAG_NHSYNC; 917 if (dtd->part2.dtd_flags & DTD_FLAG_VSYNC_POSITIVE) 918 mode.flags |= DRM_MODE_FLAG_PVSYNC; 919 else 920 mode.flags |= DRM_MODE_FLAG_NVSYNC; 921 922 drm_mode_set_crtcinfo(&mode, 0); 923 924 drm_mode_copy(pmode, &mode); 925 } 926 927 static bool intel_sdvo_check_supp_encode(struct intel_sdvo *intel_sdvo) 928 { 929 struct intel_sdvo_encode encode; 930 931 BUILD_BUG_ON(sizeof(encode) != 2); 932 return intel_sdvo_get_value(intel_sdvo, 933 SDVO_CMD_GET_SUPP_ENCODE, 934 &encode, sizeof(encode)); 935 } 936 937 static bool intel_sdvo_set_encode(struct intel_sdvo *intel_sdvo, 938 u8 mode) 939 { 940 return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_ENCODE, &mode, 1); 941 } 942 943 static bool intel_sdvo_set_colorimetry(struct intel_sdvo *intel_sdvo, 944 u8 mode) 945 { 946 return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_COLORIMETRY, &mode, 1); 947 } 948 949 static bool intel_sdvo_set_pixel_replication(struct intel_sdvo *intel_sdvo, 950 u8 pixel_repeat) 951 { 952 return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_PIXEL_REPLI, 953 &pixel_repeat, 1); 954 } 955 956 static bool intel_sdvo_set_audio_state(struct intel_sdvo *intel_sdvo, 957 u8 audio_state) 958 { 959 return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_AUDIO_STAT, 960 &audio_state, 1); 961 } 962 963 static bool intel_sdvo_get_hbuf_size(struct intel_sdvo *intel_sdvo, 964 u8 *hbuf_size) 965 { 966 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_HBUF_INFO, 967 hbuf_size, 1)) 968 return false; 969 970 /* Buffer size is 0 based, hooray! However zero means zero. */ 971 if (*hbuf_size) 972 (*hbuf_size)++; 973 974 return true; 975 } 976 977 #if 0 978 static void intel_sdvo_dump_hdmi_buf(struct intel_sdvo *intel_sdvo) 979 { 980 int i, j; 981 u8 set_buf_index[2]; 982 u8 av_split; 983 u8 buf_size; 984 u8 buf[48]; 985 u8 *pos; 986 987 intel_sdvo_get_value(encoder, SDVO_CMD_GET_HBUF_AV_SPLIT, &av_split, 1); 988 989 for (i = 0; i <= av_split; i++) { 990 set_buf_index[0] = i; set_buf_index[1] = 0; 991 intel_sdvo_write_cmd(encoder, SDVO_CMD_SET_HBUF_INDEX, 992 set_buf_index, 2); 993 intel_sdvo_write_cmd(encoder, SDVO_CMD_GET_HBUF_INFO, NULL, 0); 994 intel_sdvo_read_response(encoder, &buf_size, 1); 995 996 pos = buf; 997 for (j = 0; j <= buf_size; j += 8) { 998 intel_sdvo_write_cmd(encoder, SDVO_CMD_GET_HBUF_DATA, 999 NULL, 0); 1000 intel_sdvo_read_response(encoder, pos, 8); 1001 pos += 8; 1002 } 1003 } 1004 } 1005 #endif 1006 1007 static bool intel_sdvo_write_infoframe(struct intel_sdvo *intel_sdvo, 1008 unsigned int if_index, u8 tx_rate, 1009 const u8 *data, unsigned int length) 1010 { 1011 struct intel_display *display = to_intel_display(&intel_sdvo->base); 1012 u8 set_buf_index[2] = { if_index, 0 }; 1013 u8 hbuf_size, tmp[8]; 1014 int i; 1015 1016 if (!intel_sdvo_set_value(intel_sdvo, 1017 SDVO_CMD_SET_HBUF_INDEX, 1018 set_buf_index, 2)) 1019 return false; 1020 1021 if (!intel_sdvo_get_hbuf_size(intel_sdvo, &hbuf_size)) 1022 return false; 1023 1024 drm_dbg_kms(display->drm, 1025 "writing sdvo hbuf: %i, length %u, hbuf_size: %i\n", 1026 if_index, length, hbuf_size); 1027 1028 if (hbuf_size < length) 1029 return false; 1030 1031 for (i = 0; i < hbuf_size; i += 8) { 1032 memset(tmp, 0, 8); 1033 if (i < length) 1034 memcpy(tmp, data + i, min_t(unsigned, 8, length - i)); 1035 1036 if (!intel_sdvo_set_value(intel_sdvo, 1037 SDVO_CMD_SET_HBUF_DATA, 1038 tmp, 8)) 1039 return false; 1040 } 1041 1042 return intel_sdvo_set_value(intel_sdvo, 1043 SDVO_CMD_SET_HBUF_TXRATE, 1044 &tx_rate, 1); 1045 } 1046 1047 static ssize_t intel_sdvo_read_infoframe(struct intel_sdvo *intel_sdvo, 1048 unsigned int if_index, 1049 u8 *data, unsigned int length) 1050 { 1051 struct intel_display *display = to_intel_display(&intel_sdvo->base); 1052 u8 set_buf_index[2] = { if_index, 0 }; 1053 u8 hbuf_size, tx_rate, av_split; 1054 int i; 1055 1056 if (!intel_sdvo_get_value(intel_sdvo, 1057 SDVO_CMD_GET_HBUF_AV_SPLIT, 1058 &av_split, 1)) 1059 return -ENXIO; 1060 1061 if (av_split < if_index) 1062 return 0; 1063 1064 if (!intel_sdvo_set_value(intel_sdvo, 1065 SDVO_CMD_SET_HBUF_INDEX, 1066 set_buf_index, 2)) 1067 return -ENXIO; 1068 1069 if (!intel_sdvo_get_value(intel_sdvo, 1070 SDVO_CMD_GET_HBUF_TXRATE, 1071 &tx_rate, 1)) 1072 return -ENXIO; 1073 1074 /* TX_DISABLED doesn't mean disabled for ELD */ 1075 if (if_index != SDVO_HBUF_INDEX_ELD && tx_rate == SDVO_HBUF_TX_DISABLED) 1076 return 0; 1077 1078 if (!intel_sdvo_get_hbuf_size(intel_sdvo, &hbuf_size)) 1079 return false; 1080 1081 drm_dbg_kms(display->drm, 1082 "reading sdvo hbuf: %i, length %u, hbuf_size: %i\n", 1083 if_index, length, hbuf_size); 1084 1085 hbuf_size = min_t(unsigned int, length, hbuf_size); 1086 1087 for (i = 0; i < hbuf_size; i += 8) { 1088 if (!intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_GET_HBUF_DATA, NULL, 0)) 1089 return -ENXIO; 1090 if (!intel_sdvo_read_response(intel_sdvo, &data[i], 1091 min_t(unsigned int, 8, hbuf_size - i))) 1092 return -ENXIO; 1093 } 1094 1095 return hbuf_size; 1096 } 1097 1098 static bool intel_sdvo_compute_avi_infoframe(struct intel_sdvo *intel_sdvo, 1099 struct intel_crtc_state *crtc_state, 1100 struct drm_connector_state *conn_state) 1101 { 1102 struct intel_display *display = to_intel_display(&intel_sdvo->base); 1103 struct hdmi_avi_infoframe *frame = &crtc_state->infoframes.avi.avi; 1104 const struct drm_display_mode *adjusted_mode = 1105 &crtc_state->hw.adjusted_mode; 1106 int ret; 1107 1108 if (!crtc_state->has_hdmi_sink) 1109 return true; 1110 1111 crtc_state->infoframes.enable |= 1112 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_AVI); 1113 1114 ret = drm_hdmi_avi_infoframe_from_display_mode(frame, 1115 conn_state->connector, 1116 adjusted_mode); 1117 if (ret) 1118 return false; 1119 1120 drm_hdmi_avi_infoframe_quant_range(frame, 1121 conn_state->connector, 1122 adjusted_mode, 1123 crtc_state->limited_color_range ? 1124 HDMI_QUANTIZATION_RANGE_LIMITED : 1125 HDMI_QUANTIZATION_RANGE_FULL); 1126 1127 ret = hdmi_avi_infoframe_check(frame); 1128 if (drm_WARN_ON(display->drm, ret)) 1129 return false; 1130 1131 return true; 1132 } 1133 1134 static bool intel_sdvo_set_avi_infoframe(struct intel_sdvo *intel_sdvo, 1135 const struct intel_crtc_state *crtc_state) 1136 { 1137 struct intel_display *display = to_intel_display(&intel_sdvo->base); 1138 u8 sdvo_data[HDMI_INFOFRAME_SIZE(AVI)]; 1139 const union hdmi_infoframe *frame = &crtc_state->infoframes.avi; 1140 ssize_t len; 1141 1142 if ((crtc_state->infoframes.enable & 1143 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_AVI)) == 0) 1144 return true; 1145 1146 if (drm_WARN_ON(display->drm, 1147 frame->any.type != HDMI_INFOFRAME_TYPE_AVI)) 1148 return false; 1149 1150 len = hdmi_infoframe_pack_only(frame, sdvo_data, sizeof(sdvo_data)); 1151 if (drm_WARN_ON(display->drm, len < 0)) 1152 return false; 1153 1154 return intel_sdvo_write_infoframe(intel_sdvo, SDVO_HBUF_INDEX_AVI_IF, 1155 SDVO_HBUF_TX_VSYNC, 1156 sdvo_data, len); 1157 } 1158 1159 static void intel_sdvo_get_avi_infoframe(struct intel_sdvo *intel_sdvo, 1160 struct intel_crtc_state *crtc_state) 1161 { 1162 struct intel_display *display = to_intel_display(&intel_sdvo->base); 1163 u8 sdvo_data[HDMI_INFOFRAME_SIZE(AVI)]; 1164 union hdmi_infoframe *frame = &crtc_state->infoframes.avi; 1165 ssize_t len; 1166 int ret; 1167 1168 if (!crtc_state->has_hdmi_sink) 1169 return; 1170 1171 len = intel_sdvo_read_infoframe(intel_sdvo, SDVO_HBUF_INDEX_AVI_IF, 1172 sdvo_data, sizeof(sdvo_data)); 1173 if (len < 0) { 1174 drm_dbg_kms(display->drm, "failed to read AVI infoframe\n"); 1175 return; 1176 } else if (len == 0) { 1177 return; 1178 } 1179 1180 crtc_state->infoframes.enable |= 1181 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_AVI); 1182 1183 ret = hdmi_infoframe_unpack(frame, sdvo_data, len); 1184 if (ret) { 1185 drm_dbg_kms(display->drm, "Failed to unpack AVI infoframe\n"); 1186 return; 1187 } 1188 1189 if (frame->any.type != HDMI_INFOFRAME_TYPE_AVI) 1190 drm_dbg_kms(display->drm, 1191 "Found the wrong infoframe type 0x%x (expected 0x%02x)\n", 1192 frame->any.type, HDMI_INFOFRAME_TYPE_AVI); 1193 } 1194 1195 static void intel_sdvo_get_eld(struct intel_sdvo *intel_sdvo, 1196 struct intel_crtc_state *crtc_state) 1197 { 1198 struct intel_display *display = to_intel_display(&intel_sdvo->base); 1199 ssize_t len; 1200 u8 val; 1201 1202 if (!crtc_state->has_audio) 1203 return; 1204 1205 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_AUDIO_STAT, &val, 1)) 1206 return; 1207 1208 if ((val & SDVO_AUDIO_ELD_VALID) == 0) 1209 return; 1210 1211 len = intel_sdvo_read_infoframe(intel_sdvo, SDVO_HBUF_INDEX_ELD, 1212 crtc_state->eld, sizeof(crtc_state->eld)); 1213 if (len < 0) 1214 drm_dbg_kms(display->drm, "failed to read ELD\n"); 1215 } 1216 1217 static bool intel_sdvo_set_tv_format(struct intel_sdvo *intel_sdvo, 1218 const struct drm_connector_state *conn_state) 1219 { 1220 struct intel_sdvo_tv_format format; 1221 u32 format_map; 1222 1223 format_map = 1 << conn_state->tv.legacy_mode; 1224 memset(&format, 0, sizeof(format)); 1225 memcpy(&format, &format_map, min(sizeof(format), sizeof(format_map))); 1226 1227 BUILD_BUG_ON(sizeof(format) != 6); 1228 return intel_sdvo_set_value(intel_sdvo, 1229 SDVO_CMD_SET_TV_FORMAT, 1230 &format, sizeof(format)); 1231 } 1232 1233 static bool 1234 intel_sdvo_set_output_timings_from_mode(struct intel_sdvo *intel_sdvo, 1235 struct intel_sdvo_connector *intel_sdvo_connector, 1236 const struct drm_display_mode *mode) 1237 { 1238 struct intel_sdvo_dtd output_dtd; 1239 1240 if (!intel_sdvo_set_target_output(intel_sdvo, 1241 intel_sdvo_connector->output_flag)) 1242 return false; 1243 1244 intel_sdvo_get_dtd_from_mode(&output_dtd, mode); 1245 if (!intel_sdvo_set_output_timing(intel_sdvo, &output_dtd)) 1246 return false; 1247 1248 return true; 1249 } 1250 1251 /* 1252 * Asks the sdvo controller for the preferred input mode given the output mode. 1253 * Unfortunately we have to set up the full output mode to do that. 1254 */ 1255 static bool 1256 intel_sdvo_get_preferred_input_mode(struct intel_sdvo *intel_sdvo, 1257 struct intel_sdvo_connector *intel_sdvo_connector, 1258 const struct drm_display_mode *mode, 1259 struct drm_display_mode *adjusted_mode) 1260 { 1261 struct intel_sdvo_dtd input_dtd; 1262 1263 /* Reset the input timing to the screen. Assume always input 0. */ 1264 if (!intel_sdvo_set_target_input(intel_sdvo)) 1265 return false; 1266 1267 if (!intel_sdvo_create_preferred_input_timing(intel_sdvo, 1268 intel_sdvo_connector, 1269 mode)) 1270 return false; 1271 1272 if (!intel_sdvo_get_preferred_input_timing(intel_sdvo, 1273 &input_dtd)) 1274 return false; 1275 1276 intel_sdvo_get_mode_from_dtd(adjusted_mode, &input_dtd); 1277 intel_sdvo->dtd_sdvo_flags = input_dtd.part2.sdvo_flags; 1278 1279 return true; 1280 } 1281 1282 static int i9xx_adjust_sdvo_tv_clock(struct intel_crtc_state *pipe_config) 1283 { 1284 struct intel_display *display = to_intel_display(pipe_config); 1285 unsigned int dotclock = pipe_config->hw.adjusted_mode.crtc_clock; 1286 struct dpll *clock = &pipe_config->dpll; 1287 1288 /* 1289 * SDVO TV has fixed PLL values depend on its clock range, 1290 * this mirrors vbios setting. 1291 */ 1292 if (dotclock >= 100000 && dotclock < 140500) { 1293 clock->p1 = 2; 1294 clock->p2 = 10; 1295 clock->n = 3; 1296 clock->m1 = 16; 1297 clock->m2 = 8; 1298 } else if (dotclock >= 140500 && dotclock <= 200000) { 1299 clock->p1 = 1; 1300 clock->p2 = 10; 1301 clock->n = 6; 1302 clock->m1 = 12; 1303 clock->m2 = 8; 1304 } else { 1305 drm_dbg_kms(display->drm, 1306 "SDVO TV clock out of range: %i\n", dotclock); 1307 return -EINVAL; 1308 } 1309 1310 pipe_config->clock_set = true; 1311 1312 return 0; 1313 } 1314 1315 static bool intel_has_hdmi_sink(struct intel_sdvo_connector *intel_sdvo_connector, 1316 const struct drm_connector_state *conn_state) 1317 { 1318 struct drm_connector *connector = conn_state->connector; 1319 1320 return intel_sdvo_connector->is_hdmi && 1321 connector->display_info.is_hdmi && 1322 READ_ONCE(to_intel_digital_connector_state(conn_state)->force_audio) != HDMI_AUDIO_OFF_DVI; 1323 } 1324 1325 static bool intel_sdvo_limited_color_range(struct intel_encoder *encoder, 1326 const struct intel_crtc_state *crtc_state, 1327 const struct drm_connector_state *conn_state) 1328 { 1329 struct intel_sdvo *intel_sdvo = to_sdvo(encoder); 1330 1331 if ((intel_sdvo->colorimetry_cap & SDVO_COLORIMETRY_RGB220) == 0) 1332 return false; 1333 1334 return intel_hdmi_limited_color_range(crtc_state, conn_state); 1335 } 1336 1337 static bool intel_sdvo_has_audio(struct intel_encoder *encoder, 1338 const struct intel_crtc_state *crtc_state, 1339 const struct drm_connector_state *conn_state) 1340 { 1341 struct drm_connector *connector = conn_state->connector; 1342 struct intel_sdvo_connector *intel_sdvo_connector = 1343 to_intel_sdvo_connector(connector); 1344 const struct intel_digital_connector_state *intel_conn_state = 1345 to_intel_digital_connector_state(conn_state); 1346 1347 if (!crtc_state->has_hdmi_sink) 1348 return false; 1349 1350 if (intel_conn_state->force_audio == HDMI_AUDIO_AUTO) 1351 return intel_sdvo_connector->is_hdmi && 1352 connector->display_info.has_audio; 1353 else 1354 return intel_conn_state->force_audio == HDMI_AUDIO_ON; 1355 } 1356 1357 static int intel_sdvo_compute_config(struct intel_atomic_state *state, 1358 struct intel_encoder *encoder, 1359 struct intel_crtc_state *pipe_config, 1360 struct drm_connector_state *conn_state) 1361 { 1362 struct intel_display *display = to_intel_display(encoder); 1363 struct intel_sdvo *intel_sdvo = to_sdvo(encoder); 1364 struct intel_sdvo_connector *intel_sdvo_connector = 1365 to_intel_sdvo_connector(conn_state->connector); 1366 struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode; 1367 struct drm_display_mode *mode = &pipe_config->hw.mode; 1368 1369 if (HAS_PCH_SPLIT(display)) { 1370 pipe_config->has_pch_encoder = true; 1371 if (!intel_link_bw_compute_pipe_bpp(pipe_config)) 1372 return -EINVAL; 1373 } 1374 1375 drm_dbg_kms(display->drm, "forcing bpc to 8 for SDVO\n"); 1376 /* FIXME: Don't increase pipe_bpp */ 1377 pipe_config->pipe_bpp = 8*3; 1378 pipe_config->sink_format = INTEL_OUTPUT_FORMAT_RGB; 1379 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; 1380 1381 /* 1382 * We need to construct preferred input timings based on our 1383 * output timings. To do that, we have to set the output 1384 * timings, even though this isn't really the right place in 1385 * the sequence to do it. Oh well. 1386 */ 1387 if (IS_TV(intel_sdvo_connector)) { 1388 if (!intel_sdvo_set_output_timings_from_mode(intel_sdvo, 1389 intel_sdvo_connector, 1390 mode)) 1391 return -EINVAL; 1392 1393 (void) intel_sdvo_get_preferred_input_mode(intel_sdvo, 1394 intel_sdvo_connector, 1395 mode, 1396 adjusted_mode); 1397 pipe_config->sdvo_tv_clock = true; 1398 } else if (IS_LVDS(intel_sdvo_connector)) { 1399 const struct drm_display_mode *fixed_mode; 1400 int ret; 1401 1402 ret = intel_panel_compute_config(state, pipe_config, 1403 &intel_sdvo_connector->base); 1404 if (ret) 1405 return ret; 1406 1407 fixed_mode = &pipe_config->hw.adjusted_mode; 1408 1409 if (!intel_sdvo_set_output_timings_from_mode(intel_sdvo, 1410 intel_sdvo_connector, 1411 fixed_mode)) 1412 return -EINVAL; 1413 1414 (void) intel_sdvo_get_preferred_input_mode(intel_sdvo, 1415 intel_sdvo_connector, 1416 mode, 1417 adjusted_mode); 1418 } 1419 1420 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN) 1421 return -EINVAL; 1422 1423 /* 1424 * Make the CRTC code factor in the SDVO pixel multiplier. The 1425 * SDVO device will factor out the multiplier during mode_set. 1426 */ 1427 pipe_config->pixel_multiplier = 1428 intel_sdvo_get_pixel_multiplier(adjusted_mode); 1429 1430 pipe_config->has_hdmi_sink = intel_has_hdmi_sink(intel_sdvo_connector, conn_state); 1431 1432 pipe_config->has_audio = 1433 intel_sdvo_has_audio(encoder, pipe_config, conn_state) && 1434 intel_audio_compute_config(encoder, pipe_config, conn_state); 1435 1436 pipe_config->limited_color_range = 1437 intel_sdvo_limited_color_range(encoder, pipe_config, 1438 conn_state); 1439 1440 /* Clock computation needs to happen after pixel multiplier. */ 1441 if (IS_TV(intel_sdvo_connector)) { 1442 int ret; 1443 1444 ret = i9xx_adjust_sdvo_tv_clock(pipe_config); 1445 if (ret) 1446 return ret; 1447 } 1448 1449 if (conn_state->picture_aspect_ratio) 1450 adjusted_mode->picture_aspect_ratio = 1451 conn_state->picture_aspect_ratio; 1452 1453 if (!intel_sdvo_compute_avi_infoframe(intel_sdvo, 1454 pipe_config, conn_state)) { 1455 drm_dbg_kms(display->drm, "bad AVI infoframe\n"); 1456 return -EINVAL; 1457 } 1458 1459 return 0; 1460 } 1461 1462 #define UPDATE_PROPERTY(input, NAME) \ 1463 do { \ 1464 val = input; \ 1465 intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_##NAME, &val, sizeof(val)); \ 1466 } while (0) 1467 1468 static void intel_sdvo_update_props(struct intel_sdvo *intel_sdvo, 1469 const struct intel_sdvo_connector_state *sdvo_state) 1470 { 1471 const struct drm_connector_state *conn_state = &sdvo_state->base.base; 1472 struct intel_sdvo_connector *intel_sdvo_conn = 1473 to_intel_sdvo_connector(conn_state->connector); 1474 u16 val; 1475 1476 if (intel_sdvo_conn->left) 1477 UPDATE_PROPERTY(sdvo_state->tv.overscan_h, OVERSCAN_H); 1478 1479 if (intel_sdvo_conn->top) 1480 UPDATE_PROPERTY(sdvo_state->tv.overscan_v, OVERSCAN_V); 1481 1482 if (intel_sdvo_conn->hpos) 1483 UPDATE_PROPERTY(sdvo_state->tv.hpos, HPOS); 1484 1485 if (intel_sdvo_conn->vpos) 1486 UPDATE_PROPERTY(sdvo_state->tv.vpos, VPOS); 1487 1488 if (intel_sdvo_conn->saturation) 1489 UPDATE_PROPERTY(conn_state->tv.saturation, SATURATION); 1490 1491 if (intel_sdvo_conn->contrast) 1492 UPDATE_PROPERTY(conn_state->tv.contrast, CONTRAST); 1493 1494 if (intel_sdvo_conn->hue) 1495 UPDATE_PROPERTY(conn_state->tv.hue, HUE); 1496 1497 if (intel_sdvo_conn->brightness) 1498 UPDATE_PROPERTY(conn_state->tv.brightness, BRIGHTNESS); 1499 1500 if (intel_sdvo_conn->sharpness) 1501 UPDATE_PROPERTY(sdvo_state->tv.sharpness, SHARPNESS); 1502 1503 if (intel_sdvo_conn->flicker_filter) 1504 UPDATE_PROPERTY(sdvo_state->tv.flicker_filter, FLICKER_FILTER); 1505 1506 if (intel_sdvo_conn->flicker_filter_2d) 1507 UPDATE_PROPERTY(sdvo_state->tv.flicker_filter_2d, FLICKER_FILTER_2D); 1508 1509 if (intel_sdvo_conn->flicker_filter_adaptive) 1510 UPDATE_PROPERTY(sdvo_state->tv.flicker_filter_adaptive, FLICKER_FILTER_ADAPTIVE); 1511 1512 if (intel_sdvo_conn->tv_chroma_filter) 1513 UPDATE_PROPERTY(sdvo_state->tv.chroma_filter, TV_CHROMA_FILTER); 1514 1515 if (intel_sdvo_conn->tv_luma_filter) 1516 UPDATE_PROPERTY(sdvo_state->tv.luma_filter, TV_LUMA_FILTER); 1517 1518 if (intel_sdvo_conn->dot_crawl) 1519 UPDATE_PROPERTY(sdvo_state->tv.dot_crawl, DOT_CRAWL); 1520 1521 #undef UPDATE_PROPERTY 1522 } 1523 1524 static void intel_sdvo_pre_enable(struct intel_atomic_state *state, 1525 struct intel_encoder *intel_encoder, 1526 const struct intel_crtc_state *crtc_state, 1527 const struct drm_connector_state *conn_state) 1528 { 1529 struct intel_display *display = to_intel_display(intel_encoder); 1530 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1531 const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; 1532 const struct intel_sdvo_connector_state *sdvo_state = 1533 to_intel_sdvo_connector_state(conn_state); 1534 struct intel_sdvo_connector *intel_sdvo_connector = 1535 to_intel_sdvo_connector(conn_state->connector); 1536 const struct drm_display_mode *mode = &crtc_state->hw.mode; 1537 struct intel_sdvo *intel_sdvo = to_sdvo(intel_encoder); 1538 u32 sdvox; 1539 struct intel_sdvo_in_out_map in_out; 1540 struct intel_sdvo_dtd input_dtd, output_dtd; 1541 int rate; 1542 1543 intel_sdvo_update_props(intel_sdvo, sdvo_state); 1544 1545 /* 1546 * First, set the input mapping for the first input to our controlled 1547 * output. This is only correct if we're a single-input device, in 1548 * which case the first input is the output from the appropriate SDVO 1549 * channel on the motherboard. In a two-input device, the first input 1550 * will be SDVOB and the second SDVOC. 1551 */ 1552 in_out.in0 = intel_sdvo_connector->output_flag; 1553 in_out.in1 = 0; 1554 1555 intel_sdvo_set_value(intel_sdvo, 1556 SDVO_CMD_SET_IN_OUT_MAP, 1557 &in_out, sizeof(in_out)); 1558 1559 /* Set the output timings to the screen */ 1560 if (!intel_sdvo_set_target_output(intel_sdvo, 1561 intel_sdvo_connector->output_flag)) 1562 return; 1563 1564 /* lvds has a special fixed output timing. */ 1565 if (IS_LVDS(intel_sdvo_connector)) { 1566 const struct drm_display_mode *fixed_mode = 1567 intel_panel_fixed_mode(&intel_sdvo_connector->base, mode); 1568 1569 intel_sdvo_get_dtd_from_mode(&output_dtd, fixed_mode); 1570 } else { 1571 intel_sdvo_get_dtd_from_mode(&output_dtd, mode); 1572 } 1573 if (!intel_sdvo_set_output_timing(intel_sdvo, &output_dtd)) 1574 drm_info(display->drm, 1575 "Setting output timings on %s failed\n", 1576 SDVO_NAME(intel_sdvo)); 1577 1578 /* Set the input timing to the screen. Assume always input 0. */ 1579 if (!intel_sdvo_set_target_input(intel_sdvo)) 1580 return; 1581 1582 if (crtc_state->has_hdmi_sink) { 1583 intel_sdvo_set_encode(intel_sdvo, SDVO_ENCODE_HDMI); 1584 intel_sdvo_set_colorimetry(intel_sdvo, 1585 crtc_state->limited_color_range ? 1586 SDVO_COLORIMETRY_RGB220 : 1587 SDVO_COLORIMETRY_RGB256); 1588 intel_sdvo_set_avi_infoframe(intel_sdvo, crtc_state); 1589 intel_sdvo_set_pixel_replication(intel_sdvo, 1590 !!(adjusted_mode->flags & 1591 DRM_MODE_FLAG_DBLCLK)); 1592 } else 1593 intel_sdvo_set_encode(intel_sdvo, SDVO_ENCODE_DVI); 1594 1595 if (IS_TV(intel_sdvo_connector) && 1596 !intel_sdvo_set_tv_format(intel_sdvo, conn_state)) 1597 return; 1598 1599 intel_sdvo_get_dtd_from_mode(&input_dtd, adjusted_mode); 1600 1601 if (IS_TV(intel_sdvo_connector) || IS_LVDS(intel_sdvo_connector)) 1602 input_dtd.part2.sdvo_flags = intel_sdvo->dtd_sdvo_flags; 1603 if (!intel_sdvo_set_input_timing(intel_sdvo, &input_dtd)) 1604 drm_info(display->drm, 1605 "Setting input timings on %s failed\n", 1606 SDVO_NAME(intel_sdvo)); 1607 1608 switch (crtc_state->pixel_multiplier) { 1609 default: 1610 drm_WARN(display->drm, 1, 1611 "unknown pixel multiplier specified\n"); 1612 fallthrough; 1613 case 1: rate = SDVO_CLOCK_RATE_MULT_1X; break; 1614 case 2: rate = SDVO_CLOCK_RATE_MULT_2X; break; 1615 case 4: rate = SDVO_CLOCK_RATE_MULT_4X; break; 1616 } 1617 if (!intel_sdvo_set_clock_rate_mult(intel_sdvo, rate)) 1618 return; 1619 1620 /* Set the SDVO control regs. */ 1621 if (DISPLAY_VER(display) >= 4) { 1622 /* The real mode polarity is set by the SDVO commands, using 1623 * struct intel_sdvo_dtd. */ 1624 sdvox = SDVO_VSYNC_ACTIVE_HIGH | SDVO_HSYNC_ACTIVE_HIGH; 1625 if (DISPLAY_VER(display) < 5) 1626 sdvox |= SDVO_BORDER_ENABLE; 1627 } else { 1628 sdvox = intel_de_read(display, intel_sdvo->sdvo_reg); 1629 if (intel_sdvo->base.port == PORT_B) 1630 sdvox &= SDVOB_PRESERVE_MASK; 1631 else 1632 sdvox &= SDVOC_PRESERVE_MASK; 1633 sdvox |= (9 << 19) | SDVO_BORDER_ENABLE; 1634 } 1635 1636 if (HAS_PCH_CPT(display)) 1637 sdvox |= SDVO_PIPE_SEL_CPT(crtc->pipe); 1638 else 1639 sdvox |= SDVO_PIPE_SEL(crtc->pipe); 1640 1641 if (DISPLAY_VER(display) >= 4) { 1642 /* done in crtc_mode_set as the dpll_md reg must be written early */ 1643 } else if (display->platform.i945g || display->platform.i945gm || 1644 display->platform.g33 || display->platform.pineview) { 1645 /* done in crtc_mode_set as it lives inside the dpll register */ 1646 } else { 1647 sdvox |= (crtc_state->pixel_multiplier - 1) 1648 << SDVO_PORT_MULTIPLY_SHIFT; 1649 } 1650 1651 if (input_dtd.part2.sdvo_flags & SDVO_NEED_TO_STALL && 1652 DISPLAY_VER(display) < 5) 1653 sdvox |= SDVO_STALL_SELECT; 1654 intel_sdvo_write_sdvox(intel_sdvo, sdvox); 1655 } 1656 1657 static bool intel_sdvo_connector_get_hw_state(struct intel_connector *connector) 1658 { 1659 struct intel_sdvo_connector *intel_sdvo_connector = 1660 to_intel_sdvo_connector(&connector->base); 1661 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector); 1662 u16 active_outputs = 0; 1663 1664 intel_sdvo_get_active_outputs(intel_sdvo, &active_outputs); 1665 1666 return active_outputs & intel_sdvo_connector->output_flag; 1667 } 1668 1669 bool intel_sdvo_port_enabled(struct intel_display *display, 1670 intel_reg_t sdvo_reg, enum pipe *pipe) 1671 { 1672 u32 val; 1673 1674 val = intel_de_read(display, sdvo_reg); 1675 1676 /* asserts want to know the pipe even if the port is disabled */ 1677 if (HAS_PCH_CPT(display)) 1678 *pipe = (val & SDVO_PIPE_SEL_MASK_CPT) >> SDVO_PIPE_SEL_SHIFT_CPT; 1679 else if (display->platform.cherryview) 1680 *pipe = (val & SDVO_PIPE_SEL_MASK_CHV) >> SDVO_PIPE_SEL_SHIFT_CHV; 1681 else 1682 *pipe = (val & SDVO_PIPE_SEL_MASK) >> SDVO_PIPE_SEL_SHIFT; 1683 1684 return val & SDVO_ENABLE; 1685 } 1686 1687 static bool intel_sdvo_get_hw_state(struct intel_encoder *encoder, 1688 enum pipe *pipe) 1689 { 1690 struct intel_display *display = to_intel_display(encoder); 1691 struct intel_sdvo *intel_sdvo = to_sdvo(encoder); 1692 u16 active_outputs = 0; 1693 bool ret; 1694 1695 intel_sdvo_get_active_outputs(intel_sdvo, &active_outputs); 1696 1697 ret = intel_sdvo_port_enabled(display, intel_sdvo->sdvo_reg, pipe); 1698 1699 return ret || active_outputs; 1700 } 1701 1702 static void intel_sdvo_get_config(struct intel_encoder *encoder, 1703 struct intel_crtc_state *pipe_config) 1704 { 1705 struct intel_display *display = to_intel_display(encoder); 1706 struct intel_sdvo *intel_sdvo = to_sdvo(encoder); 1707 struct intel_sdvo_dtd dtd; 1708 int encoder_pixel_multiplier = 0; 1709 int dotclock; 1710 u32 flags = 0, sdvox; 1711 u8 val; 1712 bool ret; 1713 1714 pipe_config->output_types |= BIT(INTEL_OUTPUT_SDVO); 1715 1716 sdvox = intel_de_read(display, intel_sdvo->sdvo_reg); 1717 1718 ret = intel_sdvo_get_input_timing(intel_sdvo, &dtd); 1719 if (!ret) { 1720 /* 1721 * Some sdvo encoders are not spec compliant and don't 1722 * implement the mandatory get_timings function. 1723 */ 1724 drm_dbg_kms(display->drm, "failed to retrieve SDVO DTD\n"); 1725 pipe_config->quirks |= PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS; 1726 } else { 1727 if (dtd.part2.dtd_flags & DTD_FLAG_HSYNC_POSITIVE) 1728 flags |= DRM_MODE_FLAG_PHSYNC; 1729 else 1730 flags |= DRM_MODE_FLAG_NHSYNC; 1731 1732 if (dtd.part2.dtd_flags & DTD_FLAG_VSYNC_POSITIVE) 1733 flags |= DRM_MODE_FLAG_PVSYNC; 1734 else 1735 flags |= DRM_MODE_FLAG_NVSYNC; 1736 } 1737 1738 pipe_config->hw.adjusted_mode.flags |= flags; 1739 1740 /* 1741 * pixel multiplier readout is tricky: Only on i915g/gm it is stored in 1742 * the sdvo port register, on all other platforms it is part of the dpll 1743 * state. Since the general pipe state readout happens before the 1744 * encoder->get_config we so already have a valid pixel multiplier on all 1745 * other platforms. 1746 */ 1747 if (display->platform.i915g || display->platform.i915gm) { 1748 pipe_config->pixel_multiplier = 1749 ((sdvox & SDVO_PORT_MULTIPLY_MASK) 1750 >> SDVO_PORT_MULTIPLY_SHIFT) + 1; 1751 } 1752 1753 dotclock = pipe_config->port_clock; 1754 1755 if (pipe_config->pixel_multiplier) 1756 dotclock /= pipe_config->pixel_multiplier; 1757 1758 pipe_config->hw.adjusted_mode.crtc_clock = dotclock; 1759 1760 /* Cross check the port pixel multiplier with the sdvo encoder state. */ 1761 if (intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_CLOCK_RATE_MULT, 1762 &val, 1)) { 1763 switch (val) { 1764 case SDVO_CLOCK_RATE_MULT_1X: 1765 encoder_pixel_multiplier = 1; 1766 break; 1767 case SDVO_CLOCK_RATE_MULT_2X: 1768 encoder_pixel_multiplier = 2; 1769 break; 1770 case SDVO_CLOCK_RATE_MULT_4X: 1771 encoder_pixel_multiplier = 4; 1772 break; 1773 } 1774 } 1775 1776 drm_WARN(display->drm, 1777 encoder_pixel_multiplier != pipe_config->pixel_multiplier, 1778 "SDVO pixel multiplier mismatch, port: %i, encoder: %i\n", 1779 pipe_config->pixel_multiplier, encoder_pixel_multiplier); 1780 1781 if (intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_COLORIMETRY, 1782 &val, 1)) { 1783 if (val == SDVO_COLORIMETRY_RGB220) 1784 pipe_config->limited_color_range = true; 1785 } 1786 1787 if (intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_AUDIO_STAT, 1788 &val, 1)) { 1789 if (val & SDVO_AUDIO_PRESENCE_DETECT) 1790 pipe_config->has_audio = true; 1791 } 1792 1793 if (intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_ENCODE, 1794 &val, 1)) { 1795 if (val == SDVO_ENCODE_HDMI) 1796 pipe_config->has_hdmi_sink = true; 1797 } 1798 1799 intel_sdvo_get_avi_infoframe(intel_sdvo, pipe_config); 1800 1801 intel_sdvo_get_eld(intel_sdvo, pipe_config); 1802 } 1803 1804 static void intel_sdvo_disable_audio(struct intel_encoder *encoder, 1805 const struct intel_crtc_state *old_crtc_state, 1806 const struct drm_connector_state *old_conn_state) 1807 { 1808 struct intel_sdvo *intel_sdvo = to_sdvo(encoder); 1809 1810 if (!old_crtc_state->has_audio) 1811 return; 1812 1813 intel_sdvo_set_audio_state(intel_sdvo, 0); 1814 } 1815 1816 static void intel_sdvo_enable_audio(struct intel_encoder *encoder, 1817 const struct intel_crtc_state *crtc_state, 1818 const struct drm_connector_state *conn_state) 1819 { 1820 struct intel_sdvo *intel_sdvo = to_sdvo(encoder); 1821 const u8 *eld = crtc_state->eld; 1822 1823 if (!crtc_state->has_audio) 1824 return; 1825 1826 intel_sdvo_set_audio_state(intel_sdvo, 0); 1827 1828 intel_sdvo_write_infoframe(intel_sdvo, SDVO_HBUF_INDEX_ELD, 1829 SDVO_HBUF_TX_DISABLED, 1830 eld, drm_eld_size(eld)); 1831 1832 intel_sdvo_set_audio_state(intel_sdvo, SDVO_AUDIO_ELD_VALID | 1833 SDVO_AUDIO_PRESENCE_DETECT); 1834 } 1835 1836 static void intel_disable_sdvo(struct intel_atomic_state *state, 1837 struct intel_encoder *encoder, 1838 const struct intel_crtc_state *old_crtc_state, 1839 const struct drm_connector_state *conn_state) 1840 { 1841 struct intel_display *display = to_intel_display(encoder); 1842 struct intel_sdvo *intel_sdvo = to_sdvo(encoder); 1843 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); 1844 u32 temp; 1845 1846 intel_sdvo_set_active_outputs(intel_sdvo, 0); 1847 if (0) 1848 intel_sdvo_set_encoder_power_state(intel_sdvo, 1849 DRM_MODE_DPMS_OFF); 1850 1851 temp = intel_de_read(display, intel_sdvo->sdvo_reg); 1852 1853 temp &= ~SDVO_ENABLE; 1854 intel_sdvo_write_sdvox(intel_sdvo, temp); 1855 1856 /* 1857 * HW workaround for IBX, we need to move the port 1858 * to transcoder A after disabling it to allow the 1859 * matching DP port to be enabled on transcoder A. 1860 */ 1861 if (HAS_PCH_IBX(display) && crtc->pipe == PIPE_B) { 1862 /* 1863 * We get CPU/PCH FIFO underruns on the other pipe when 1864 * doing the workaround. Sweep them under the rug. 1865 */ 1866 intel_set_cpu_fifo_underrun_reporting(display, PIPE_A, false); 1867 intel_set_pch_fifo_underrun_reporting(display, PIPE_A, false); 1868 1869 temp &= ~SDVO_PIPE_SEL_MASK; 1870 temp |= SDVO_ENABLE | SDVO_PIPE_SEL(PIPE_A); 1871 intel_sdvo_write_sdvox(intel_sdvo, temp); 1872 1873 temp &= ~SDVO_ENABLE; 1874 intel_sdvo_write_sdvox(intel_sdvo, temp); 1875 1876 intel_wait_for_vblank_if_active(display, PIPE_A); 1877 intel_set_cpu_fifo_underrun_reporting(display, PIPE_A, true); 1878 intel_set_pch_fifo_underrun_reporting(display, PIPE_A, true); 1879 } 1880 } 1881 1882 static void pch_disable_sdvo(struct intel_atomic_state *state, 1883 struct intel_encoder *encoder, 1884 const struct intel_crtc_state *old_crtc_state, 1885 const struct drm_connector_state *old_conn_state) 1886 { 1887 } 1888 1889 static void pch_post_disable_sdvo(struct intel_atomic_state *state, 1890 struct intel_encoder *encoder, 1891 const struct intel_crtc_state *old_crtc_state, 1892 const struct drm_connector_state *old_conn_state) 1893 { 1894 intel_disable_sdvo(state, encoder, old_crtc_state, old_conn_state); 1895 } 1896 1897 static void intel_enable_sdvo(struct intel_atomic_state *state, 1898 struct intel_encoder *encoder, 1899 const struct intel_crtc_state *pipe_config, 1900 const struct drm_connector_state *conn_state) 1901 { 1902 struct intel_display *display = to_intel_display(encoder); 1903 struct intel_sdvo *intel_sdvo = to_sdvo(encoder); 1904 struct intel_sdvo_connector *intel_sdvo_connector = 1905 to_intel_sdvo_connector(conn_state->connector); 1906 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 1907 u32 temp; 1908 bool input1, input2; 1909 int i; 1910 bool success; 1911 1912 temp = intel_de_read(display, intel_sdvo->sdvo_reg); 1913 temp |= SDVO_ENABLE; 1914 intel_sdvo_write_sdvox(intel_sdvo, temp); 1915 1916 for (i = 0; i < 2; i++) 1917 intel_crtc_wait_for_next_vblank(crtc); 1918 1919 success = intel_sdvo_get_trained_inputs(intel_sdvo, &input1, &input2); 1920 /* 1921 * Warn if the device reported failure to sync. 1922 * 1923 * A lot of SDVO devices fail to notify of sync, but it's 1924 * a given it the status is a success, we succeeded. 1925 */ 1926 if (success && !input1) { 1927 drm_dbg_kms(display->drm, 1928 "First %s output reported failure to sync\n", 1929 SDVO_NAME(intel_sdvo)); 1930 } 1931 1932 if (0) 1933 intel_sdvo_set_encoder_power_state(intel_sdvo, 1934 DRM_MODE_DPMS_ON); 1935 intel_sdvo_set_active_outputs(intel_sdvo, intel_sdvo_connector->output_flag); 1936 } 1937 1938 static enum drm_mode_status 1939 intel_sdvo_mode_valid(struct drm_connector *connector, 1940 const struct drm_display_mode *mode) 1941 { 1942 struct intel_display *display = to_intel_display(connector->dev); 1943 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(to_intel_connector(connector)); 1944 struct intel_sdvo_connector *intel_sdvo_connector = 1945 to_intel_sdvo_connector(connector); 1946 bool has_hdmi_sink = intel_has_hdmi_sink(intel_sdvo_connector, connector->state); 1947 int max_dotclk = display->cdclk.max_dotclk_freq; 1948 enum drm_mode_status status; 1949 int clock = mode->clock; 1950 1951 status = intel_cpu_transcoder_mode_valid(display, mode); 1952 if (status != MODE_OK) 1953 return status; 1954 1955 if (clock > max_dotclk) 1956 return MODE_CLOCK_HIGH; 1957 1958 if (mode->flags & DRM_MODE_FLAG_DBLCLK) { 1959 if (!has_hdmi_sink) 1960 return MODE_CLOCK_LOW; 1961 clock *= 2; 1962 } 1963 1964 if (intel_sdvo->pixel_clock_min > clock) 1965 return MODE_CLOCK_LOW; 1966 1967 if (intel_sdvo->pixel_clock_max < clock) 1968 return MODE_CLOCK_HIGH; 1969 1970 if (IS_LVDS(intel_sdvo_connector)) { 1971 enum drm_mode_status status; 1972 int target_clock; 1973 1974 status = intel_panel_mode_valid(&intel_sdvo_connector->base, mode, &target_clock); 1975 if (status != MODE_OK) 1976 return status; 1977 1978 if (target_clock > max_dotclk) 1979 return MODE_CLOCK_HIGH; 1980 } 1981 1982 return MODE_OK; 1983 } 1984 1985 static bool intel_sdvo_get_capabilities(struct intel_sdvo *intel_sdvo, struct intel_sdvo_caps *caps) 1986 { 1987 struct intel_display *display = to_intel_display(&intel_sdvo->base); 1988 1989 BUILD_BUG_ON(sizeof(*caps) != 8); 1990 if (!intel_sdvo_get_value(intel_sdvo, 1991 SDVO_CMD_GET_DEVICE_CAPS, 1992 caps, sizeof(*caps))) 1993 return false; 1994 1995 drm_dbg_kms(display->drm, "SDVO capabilities:\n" 1996 " vendor_id: %d\n" 1997 " device_id: %d\n" 1998 " device_rev_id: %d\n" 1999 " sdvo_version_major: %d\n" 2000 " sdvo_version_minor: %d\n" 2001 " sdvo_num_inputs: %d\n" 2002 " smooth_scaling: %d\n" 2003 " sharp_scaling: %d\n" 2004 " up_scaling: %d\n" 2005 " down_scaling: %d\n" 2006 " stall_support: %d\n" 2007 " output_flags: %d\n", 2008 caps->vendor_id, 2009 caps->device_id, 2010 caps->device_rev_id, 2011 caps->sdvo_version_major, 2012 caps->sdvo_version_minor, 2013 caps->sdvo_num_inputs, 2014 caps->smooth_scaling, 2015 caps->sharp_scaling, 2016 caps->up_scaling, 2017 caps->down_scaling, 2018 caps->stall_support, 2019 caps->output_flags); 2020 2021 return true; 2022 } 2023 2024 static u8 intel_sdvo_get_colorimetry_cap(struct intel_sdvo *intel_sdvo) 2025 { 2026 u8 cap; 2027 2028 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_COLORIMETRY_CAP, 2029 &cap, sizeof(cap))) 2030 return SDVO_COLORIMETRY_RGB256; 2031 2032 return cap; 2033 } 2034 2035 static u16 intel_sdvo_get_hotplug_support(struct intel_sdvo *intel_sdvo) 2036 { 2037 struct intel_display *display = to_intel_display(&intel_sdvo->base); 2038 u16 hotplug; 2039 2040 if (!HAS_HOTPLUG(display)) 2041 return 0; 2042 2043 /* 2044 * HW Erratum: SDVO Hotplug is broken on all i945G chips, there's noise 2045 * on the line. 2046 */ 2047 if (display->platform.i945g || display->platform.i945gm) 2048 return 0; 2049 2050 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_HOT_PLUG_SUPPORT, 2051 &hotplug, sizeof(hotplug))) 2052 return 0; 2053 2054 return hotplug; 2055 } 2056 2057 static void intel_sdvo_enable_hotplug(struct intel_encoder *encoder) 2058 { 2059 struct intel_sdvo *intel_sdvo = to_sdvo(encoder); 2060 2061 if (!intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_SET_ACTIVE_HOT_PLUG, 2062 &intel_sdvo->hotplug_active, 2)) 2063 drm_warn(intel_sdvo->base.base.dev, 2064 "Failed to enable hotplug on SDVO encoder\n"); 2065 } 2066 2067 static enum intel_hotplug_state 2068 intel_sdvo_hotplug(struct intel_encoder *encoder, 2069 struct intel_connector *connector) 2070 { 2071 intel_sdvo_enable_hotplug(encoder); 2072 2073 return intel_encoder_hotplug(encoder, connector); 2074 } 2075 2076 static const struct drm_edid * 2077 intel_sdvo_get_edid(struct drm_connector *connector) 2078 { 2079 struct i2c_adapter *ddc = connector->ddc; 2080 2081 if (!ddc) 2082 return NULL; 2083 2084 return drm_edid_read_ddc(connector, ddc); 2085 } 2086 2087 /* Mac mini hack -- use the same DDC as the analog connector */ 2088 static const struct drm_edid * 2089 intel_sdvo_get_analog_edid(struct drm_connector *connector) 2090 { 2091 struct intel_display *display = to_intel_display(connector->dev); 2092 struct i2c_adapter *ddc; 2093 2094 ddc = intel_gmbus_get_adapter(display, display->vbt.crt_ddc_pin); 2095 if (!ddc) 2096 return NULL; 2097 2098 return drm_edid_read_ddc(connector, ddc); 2099 } 2100 2101 static enum drm_connector_status 2102 intel_sdvo_tmds_sink_detect(struct drm_connector *connector) 2103 { 2104 enum drm_connector_status status; 2105 const struct drm_edid *drm_edid; 2106 2107 drm_edid = intel_sdvo_get_edid(connector); 2108 2109 /* 2110 * When there is no edid and no monitor is connected with VGA 2111 * port, try to use the CRT ddc to read the EDID for DVI-connector. 2112 */ 2113 if (!drm_edid) 2114 drm_edid = intel_sdvo_get_analog_edid(connector); 2115 2116 status = connector_status_unknown; 2117 if (drm_edid) { 2118 /* DDC bus is shared, match EDID to connector type */ 2119 if (drm_edid_is_digital(drm_edid)) 2120 status = connector_status_connected; 2121 else 2122 status = connector_status_disconnected; 2123 drm_edid_free(drm_edid); 2124 } 2125 2126 return status; 2127 } 2128 2129 static bool 2130 intel_sdvo_connector_matches_edid(struct intel_sdvo_connector *sdvo, 2131 const struct drm_edid *drm_edid) 2132 { 2133 bool monitor_is_digital = drm_edid_is_digital(drm_edid); 2134 bool connector_is_digital = !!IS_DIGITAL(sdvo); 2135 2136 drm_dbg_kms(sdvo->base.base.dev, 2137 "connector_is_digital? %d, monitor_is_digital? %d\n", 2138 connector_is_digital, monitor_is_digital); 2139 return connector_is_digital == monitor_is_digital; 2140 } 2141 2142 static enum drm_connector_status 2143 intel_sdvo_detect(struct drm_connector *connector, bool force) 2144 { 2145 struct intel_display *display = to_intel_display(connector->dev); 2146 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(to_intel_connector(connector)); 2147 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector); 2148 enum drm_connector_status ret; 2149 u16 response; 2150 2151 drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s]\n", 2152 connector->base.id, connector->name); 2153 2154 if (!intel_display_device_enabled(display)) 2155 return connector_status_disconnected; 2156 2157 if (!intel_display_driver_check_access(display)) 2158 return connector->status; 2159 2160 if (!intel_sdvo_set_target_output(intel_sdvo, 2161 intel_sdvo_connector->output_flag)) 2162 return connector_status_unknown; 2163 2164 if (!intel_sdvo_get_value(intel_sdvo, 2165 SDVO_CMD_GET_ATTACHED_DISPLAYS, 2166 &response, 2)) 2167 return connector_status_unknown; 2168 2169 drm_dbg_kms(display->drm, "SDVO response %d %d [%x]\n", 2170 response & 0xff, response >> 8, 2171 intel_sdvo_connector->output_flag); 2172 2173 if (response == 0) 2174 return connector_status_disconnected; 2175 2176 if ((intel_sdvo_connector->output_flag & response) == 0) 2177 ret = connector_status_disconnected; 2178 else if (IS_TMDS(intel_sdvo_connector)) 2179 ret = intel_sdvo_tmds_sink_detect(connector); 2180 else { 2181 const struct drm_edid *drm_edid; 2182 2183 /* if we have an edid check it matches the connection */ 2184 drm_edid = intel_sdvo_get_edid(connector); 2185 if (!drm_edid) 2186 drm_edid = intel_sdvo_get_analog_edid(connector); 2187 if (drm_edid) { 2188 if (intel_sdvo_connector_matches_edid(intel_sdvo_connector, 2189 drm_edid)) 2190 ret = connector_status_connected; 2191 else 2192 ret = connector_status_disconnected; 2193 2194 drm_edid_free(drm_edid); 2195 } else { 2196 ret = connector_status_connected; 2197 } 2198 } 2199 2200 return ret; 2201 } 2202 2203 static int intel_sdvo_get_ddc_modes(struct drm_connector *connector) 2204 { 2205 struct intel_display *display = to_intel_display(connector->dev); 2206 int num_modes = 0; 2207 const struct drm_edid *drm_edid; 2208 2209 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s]\n", 2210 connector->base.id, connector->name); 2211 2212 if (!intel_display_driver_check_access(display)) 2213 return drm_edid_connector_add_modes(connector); 2214 2215 /* set the bus switch and get the modes */ 2216 drm_edid = intel_sdvo_get_edid(connector); 2217 2218 /* 2219 * Mac mini hack. On this device, the DVI-I connector shares one DDC 2220 * link between analog and digital outputs. So, if the regular SDVO 2221 * DDC fails, check to see if the analog output is disconnected, in 2222 * which case we'll look there for the digital DDC data. 2223 */ 2224 if (!drm_edid) 2225 drm_edid = intel_sdvo_get_analog_edid(connector); 2226 2227 if (!drm_edid) 2228 return 0; 2229 2230 if (intel_sdvo_connector_matches_edid(to_intel_sdvo_connector(connector), 2231 drm_edid)) 2232 num_modes += intel_connector_update_modes(connector, drm_edid); 2233 2234 drm_edid_free(drm_edid); 2235 2236 return num_modes; 2237 } 2238 2239 /* 2240 * Set of SDVO TV modes. 2241 * Note! This is in reply order (see loop in get_tv_modes). 2242 * XXX: all 60Hz refresh? 2243 */ 2244 static const struct drm_display_mode sdvo_tv_modes[] = { 2245 { DRM_MODE("320x200", DRM_MODE_TYPE_DRIVER, 5815, 320, 321, 384, 2246 416, 0, 200, 201, 232, 233, 0, 2247 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 2248 { DRM_MODE("320x240", DRM_MODE_TYPE_DRIVER, 6814, 320, 321, 384, 2249 416, 0, 240, 241, 272, 273, 0, 2250 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 2251 { DRM_MODE("400x300", DRM_MODE_TYPE_DRIVER, 9910, 400, 401, 464, 2252 496, 0, 300, 301, 332, 333, 0, 2253 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 2254 { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 16913, 640, 641, 704, 2255 736, 0, 350, 351, 382, 383, 0, 2256 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 2257 { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 19121, 640, 641, 704, 2258 736, 0, 400, 401, 432, 433, 0, 2259 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 2260 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 22654, 640, 641, 704, 2261 736, 0, 480, 481, 512, 513, 0, 2262 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 2263 { DRM_MODE("704x480", DRM_MODE_TYPE_DRIVER, 24624, 704, 705, 768, 2264 800, 0, 480, 481, 512, 513, 0, 2265 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 2266 { DRM_MODE("704x576", DRM_MODE_TYPE_DRIVER, 29232, 704, 705, 768, 2267 800, 0, 576, 577, 608, 609, 0, 2268 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 2269 { DRM_MODE("720x350", DRM_MODE_TYPE_DRIVER, 18751, 720, 721, 784, 2270 816, 0, 350, 351, 382, 383, 0, 2271 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 2272 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 21199, 720, 721, 784, 2273 816, 0, 400, 401, 432, 433, 0, 2274 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 2275 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 25116, 720, 721, 784, 2276 816, 0, 480, 481, 512, 513, 0, 2277 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 2278 { DRM_MODE("720x540", DRM_MODE_TYPE_DRIVER, 28054, 720, 721, 784, 2279 816, 0, 540, 541, 572, 573, 0, 2280 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 2281 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 29816, 720, 721, 784, 2282 816, 0, 576, 577, 608, 609, 0, 2283 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 2284 { DRM_MODE("768x576", DRM_MODE_TYPE_DRIVER, 31570, 768, 769, 832, 2285 864, 0, 576, 577, 608, 609, 0, 2286 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 2287 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 34030, 800, 801, 864, 2288 896, 0, 600, 601, 632, 633, 0, 2289 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 2290 { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 36581, 832, 833, 896, 2291 928, 0, 624, 625, 656, 657, 0, 2292 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 2293 { DRM_MODE("920x766", DRM_MODE_TYPE_DRIVER, 48707, 920, 921, 984, 2294 1016, 0, 766, 767, 798, 799, 0, 2295 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 2296 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 53827, 1024, 1025, 1088, 2297 1120, 0, 768, 769, 800, 801, 0, 2298 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 2299 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 87265, 1280, 1281, 1344, 2300 1376, 0, 1024, 1025, 1056, 1057, 0, 2301 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 2302 }; 2303 2304 static int intel_sdvo_get_tv_modes(struct drm_connector *connector) 2305 { 2306 struct intel_display *display = to_intel_display(connector->dev); 2307 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(to_intel_connector(connector)); 2308 struct intel_sdvo_connector *intel_sdvo_connector = 2309 to_intel_sdvo_connector(connector); 2310 const struct drm_connector_state *conn_state = connector->state; 2311 struct intel_sdvo_sdtv_resolution_request tv_res; 2312 u32 reply = 0, format_map = 0; 2313 int num_modes = 0; 2314 int i; 2315 2316 drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s]\n", 2317 connector->base.id, connector->name); 2318 2319 if (!intel_display_driver_check_access(display)) 2320 return 0; 2321 2322 /* 2323 * Read the list of supported input resolutions for the selected TV 2324 * format. 2325 */ 2326 format_map = 1 << conn_state->tv.legacy_mode; 2327 memcpy(&tv_res, &format_map, 2328 min(sizeof(format_map), sizeof(struct intel_sdvo_sdtv_resolution_request))); 2329 2330 if (!intel_sdvo_set_target_output(intel_sdvo, intel_sdvo_connector->output_flag)) 2331 return 0; 2332 2333 BUILD_BUG_ON(sizeof(tv_res) != 3); 2334 if (!intel_sdvo_write_cmd(intel_sdvo, 2335 SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT, 2336 &tv_res, sizeof(tv_res))) 2337 return 0; 2338 if (!intel_sdvo_read_response(intel_sdvo, &reply, 3)) 2339 return 0; 2340 2341 for (i = 0; i < ARRAY_SIZE(sdvo_tv_modes); i++) { 2342 if (reply & (1 << i)) { 2343 struct drm_display_mode *nmode; 2344 nmode = drm_mode_duplicate(connector->dev, 2345 &sdvo_tv_modes[i]); 2346 if (nmode) { 2347 drm_mode_probed_add(connector, nmode); 2348 num_modes++; 2349 } 2350 } 2351 } 2352 2353 return num_modes; 2354 } 2355 2356 static int intel_sdvo_get_lvds_modes(struct drm_connector *connector) 2357 { 2358 struct intel_display *display = to_intel_display(connector->dev); 2359 2360 drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s]\n", 2361 connector->base.id, connector->name); 2362 2363 return intel_panel_get_modes(to_intel_connector(connector)); 2364 } 2365 2366 static int intel_sdvo_get_modes(struct drm_connector *connector) 2367 { 2368 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector); 2369 2370 if (IS_TV(intel_sdvo_connector)) 2371 return intel_sdvo_get_tv_modes(connector); 2372 else if (IS_LVDS(intel_sdvo_connector)) 2373 return intel_sdvo_get_lvds_modes(connector); 2374 else 2375 return intel_sdvo_get_ddc_modes(connector); 2376 } 2377 2378 static int 2379 intel_sdvo_connector_atomic_get_property(struct drm_connector *connector, 2380 const struct drm_connector_state *state, 2381 struct drm_property *property, 2382 u64 *val) 2383 { 2384 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector); 2385 const struct intel_sdvo_connector_state *sdvo_state = to_intel_sdvo_connector_state(state); 2386 2387 if (property == intel_sdvo_connector->tv_format) { 2388 int i; 2389 2390 for (i = 0; i < intel_sdvo_connector->format_supported_num; i++) 2391 if (state->tv.legacy_mode == intel_sdvo_connector->tv_format_supported[i]) { 2392 *val = i; 2393 2394 return 0; 2395 } 2396 2397 drm_WARN_ON(connector->dev, 1); 2398 *val = 0; 2399 } else if (property == intel_sdvo_connector->top || 2400 property == intel_sdvo_connector->bottom) 2401 *val = intel_sdvo_connector->max_vscan - sdvo_state->tv.overscan_v; 2402 else if (property == intel_sdvo_connector->left || 2403 property == intel_sdvo_connector->right) 2404 *val = intel_sdvo_connector->max_hscan - sdvo_state->tv.overscan_h; 2405 else if (property == intel_sdvo_connector->hpos) 2406 *val = sdvo_state->tv.hpos; 2407 else if (property == intel_sdvo_connector->vpos) 2408 *val = sdvo_state->tv.vpos; 2409 else if (property == intel_sdvo_connector->saturation) 2410 *val = state->tv.saturation; 2411 else if (property == intel_sdvo_connector->contrast) 2412 *val = state->tv.contrast; 2413 else if (property == intel_sdvo_connector->hue) 2414 *val = state->tv.hue; 2415 else if (property == intel_sdvo_connector->brightness) 2416 *val = state->tv.brightness; 2417 else if (property == intel_sdvo_connector->sharpness) 2418 *val = sdvo_state->tv.sharpness; 2419 else if (property == intel_sdvo_connector->flicker_filter) 2420 *val = sdvo_state->tv.flicker_filter; 2421 else if (property == intel_sdvo_connector->flicker_filter_2d) 2422 *val = sdvo_state->tv.flicker_filter_2d; 2423 else if (property == intel_sdvo_connector->flicker_filter_adaptive) 2424 *val = sdvo_state->tv.flicker_filter_adaptive; 2425 else if (property == intel_sdvo_connector->tv_chroma_filter) 2426 *val = sdvo_state->tv.chroma_filter; 2427 else if (property == intel_sdvo_connector->tv_luma_filter) 2428 *val = sdvo_state->tv.luma_filter; 2429 else if (property == intel_sdvo_connector->dot_crawl) 2430 *val = sdvo_state->tv.dot_crawl; 2431 else 2432 return intel_digital_connector_atomic_get_property(connector, state, property, val); 2433 2434 return 0; 2435 } 2436 2437 static int 2438 intel_sdvo_connector_atomic_set_property(struct drm_connector *connector, 2439 struct drm_connector_state *state, 2440 struct drm_property *property, 2441 u64 val) 2442 { 2443 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector); 2444 struct intel_sdvo_connector_state *sdvo_state = to_intel_sdvo_connector_state(state); 2445 2446 if (property == intel_sdvo_connector->tv_format) { 2447 state->tv.legacy_mode = intel_sdvo_connector->tv_format_supported[val]; 2448 2449 if (state->crtc) { 2450 struct drm_crtc_state *crtc_state = 2451 drm_atomic_get_new_crtc_state(state->state, state->crtc); 2452 2453 crtc_state->connectors_changed = true; 2454 } 2455 } else if (property == intel_sdvo_connector->top || 2456 property == intel_sdvo_connector->bottom) 2457 /* Cannot set these independent from each other */ 2458 sdvo_state->tv.overscan_v = intel_sdvo_connector->max_vscan - val; 2459 else if (property == intel_sdvo_connector->left || 2460 property == intel_sdvo_connector->right) 2461 /* Cannot set these independent from each other */ 2462 sdvo_state->tv.overscan_h = intel_sdvo_connector->max_hscan - val; 2463 else if (property == intel_sdvo_connector->hpos) 2464 sdvo_state->tv.hpos = val; 2465 else if (property == intel_sdvo_connector->vpos) 2466 sdvo_state->tv.vpos = val; 2467 else if (property == intel_sdvo_connector->saturation) 2468 state->tv.saturation = val; 2469 else if (property == intel_sdvo_connector->contrast) 2470 state->tv.contrast = val; 2471 else if (property == intel_sdvo_connector->hue) 2472 state->tv.hue = val; 2473 else if (property == intel_sdvo_connector->brightness) 2474 state->tv.brightness = val; 2475 else if (property == intel_sdvo_connector->sharpness) 2476 sdvo_state->tv.sharpness = val; 2477 else if (property == intel_sdvo_connector->flicker_filter) 2478 sdvo_state->tv.flicker_filter = val; 2479 else if (property == intel_sdvo_connector->flicker_filter_2d) 2480 sdvo_state->tv.flicker_filter_2d = val; 2481 else if (property == intel_sdvo_connector->flicker_filter_adaptive) 2482 sdvo_state->tv.flicker_filter_adaptive = val; 2483 else if (property == intel_sdvo_connector->tv_chroma_filter) 2484 sdvo_state->tv.chroma_filter = val; 2485 else if (property == intel_sdvo_connector->tv_luma_filter) 2486 sdvo_state->tv.luma_filter = val; 2487 else if (property == intel_sdvo_connector->dot_crawl) 2488 sdvo_state->tv.dot_crawl = val; 2489 else 2490 return intel_digital_connector_atomic_set_property(connector, state, property, val); 2491 2492 return 0; 2493 } 2494 2495 static struct drm_connector_state * 2496 intel_sdvo_connector_duplicate_state(struct drm_connector *connector) 2497 { 2498 struct intel_sdvo_connector_state *state; 2499 2500 state = kmemdup(connector->state, sizeof(*state), GFP_KERNEL); 2501 if (!state) 2502 return NULL; 2503 2504 __drm_atomic_helper_connector_duplicate_state(connector, &state->base.base); 2505 return &state->base.base; 2506 } 2507 2508 static const struct drm_connector_funcs intel_sdvo_connector_funcs = { 2509 .detect = intel_sdvo_detect, 2510 .fill_modes = drm_helper_probe_single_connector_modes, 2511 .atomic_get_property = intel_sdvo_connector_atomic_get_property, 2512 .atomic_set_property = intel_sdvo_connector_atomic_set_property, 2513 .late_register = intel_connector_register, 2514 .early_unregister = intel_connector_unregister, 2515 .destroy = intel_connector_destroy, 2516 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 2517 .atomic_duplicate_state = intel_sdvo_connector_duplicate_state, 2518 }; 2519 2520 static int intel_sdvo_atomic_check(struct drm_connector *conn, 2521 struct drm_atomic_commit *state) 2522 { 2523 struct drm_connector_state *new_conn_state = 2524 drm_atomic_get_new_connector_state(state, conn); 2525 struct drm_connector_state *old_conn_state = 2526 drm_atomic_get_old_connector_state(state, conn); 2527 struct intel_sdvo_connector_state *old_state = 2528 to_intel_sdvo_connector_state(old_conn_state); 2529 struct intel_sdvo_connector_state *new_state = 2530 to_intel_sdvo_connector_state(new_conn_state); 2531 2532 if (new_conn_state->crtc && 2533 (memcmp(&old_state->tv, &new_state->tv, sizeof(old_state->tv)) || 2534 memcmp(&old_conn_state->tv, &new_conn_state->tv, sizeof(old_conn_state->tv)))) { 2535 struct drm_crtc_state *crtc_state = 2536 drm_atomic_get_new_crtc_state(state, 2537 new_conn_state->crtc); 2538 2539 crtc_state->connectors_changed = true; 2540 } 2541 2542 return intel_digital_connector_atomic_check(conn, state); 2543 } 2544 2545 static const struct drm_connector_helper_funcs intel_sdvo_connector_helper_funcs = { 2546 .get_modes = intel_sdvo_get_modes, 2547 .mode_valid = intel_sdvo_mode_valid, 2548 .atomic_check = intel_sdvo_atomic_check, 2549 }; 2550 2551 static void intel_sdvo_encoder_destroy(struct drm_encoder *_encoder) 2552 { 2553 struct intel_encoder *encoder = to_intel_encoder(_encoder); 2554 struct intel_sdvo *sdvo = to_sdvo(encoder); 2555 int i; 2556 2557 for (i = 0; i < ARRAY_SIZE(sdvo->ddc); i++) { 2558 if (sdvo->ddc[i].ddc_bus) 2559 i2c_del_adapter(&sdvo->ddc[i].ddc); 2560 } 2561 2562 drm_encoder_cleanup(&encoder->base); 2563 kfree(sdvo); 2564 }; 2565 2566 static const struct drm_encoder_funcs intel_sdvo_enc_funcs = { 2567 .destroy = intel_sdvo_encoder_destroy, 2568 }; 2569 2570 static int 2571 intel_sdvo_guess_ddc_bus(struct intel_sdvo *sdvo, 2572 struct intel_sdvo_connector *connector) 2573 { 2574 u16 mask = 0; 2575 int num_bits; 2576 2577 /* 2578 * Make a mask of outputs less than or equal to our own priority in the 2579 * list. 2580 */ 2581 switch (connector->output_flag) { 2582 case SDVO_OUTPUT_LVDS1: 2583 mask |= SDVO_OUTPUT_LVDS1; 2584 fallthrough; 2585 case SDVO_OUTPUT_LVDS0: 2586 mask |= SDVO_OUTPUT_LVDS0; 2587 fallthrough; 2588 case SDVO_OUTPUT_TMDS1: 2589 mask |= SDVO_OUTPUT_TMDS1; 2590 fallthrough; 2591 case SDVO_OUTPUT_TMDS0: 2592 mask |= SDVO_OUTPUT_TMDS0; 2593 fallthrough; 2594 case SDVO_OUTPUT_RGB1: 2595 mask |= SDVO_OUTPUT_RGB1; 2596 fallthrough; 2597 case SDVO_OUTPUT_RGB0: 2598 mask |= SDVO_OUTPUT_RGB0; 2599 break; 2600 } 2601 2602 /* Count bits to find what number we are in the priority list. */ 2603 mask &= sdvo->caps.output_flags; 2604 num_bits = hweight16(mask); 2605 /* If more than 3 outputs, default to DDC bus 3 for now. */ 2606 if (num_bits > 3) 2607 num_bits = 3; 2608 2609 /* Corresponds to SDVO_CONTROL_BUS_DDCx */ 2610 return num_bits; 2611 } 2612 2613 /* 2614 * Choose the appropriate DDC bus for control bus switch command for this 2615 * SDVO output based on the controlled output. 2616 * 2617 * DDC bus number assignment is in a priority order of RGB outputs, then TMDS 2618 * outputs, then LVDS outputs. 2619 */ 2620 static struct intel_sdvo_ddc * 2621 intel_sdvo_select_ddc_bus(struct intel_sdvo *sdvo, 2622 struct intel_sdvo_connector *connector) 2623 { 2624 struct intel_display *display = to_intel_display(&sdvo->base); 2625 const struct sdvo_device_mapping *mapping; 2626 int ddc_bus; 2627 2628 if (sdvo->base.port == PORT_B) 2629 mapping = &display->vbt.sdvo_mappings[0]; 2630 else 2631 mapping = &display->vbt.sdvo_mappings[1]; 2632 2633 if (mapping->initialized) 2634 ddc_bus = (mapping->ddc_pin & 0xf0) >> 4; 2635 else 2636 ddc_bus = intel_sdvo_guess_ddc_bus(sdvo, connector); 2637 2638 if (ddc_bus < 1 || ddc_bus > 3) 2639 return NULL; 2640 2641 return &sdvo->ddc[ddc_bus - 1]; 2642 } 2643 2644 static void 2645 intel_sdvo_select_i2c_bus(struct intel_sdvo *sdvo) 2646 { 2647 struct intel_display *display = to_intel_display(&sdvo->base); 2648 const struct sdvo_device_mapping *mapping; 2649 u8 pin; 2650 2651 if (sdvo->base.port == PORT_B) 2652 mapping = &display->vbt.sdvo_mappings[0]; 2653 else 2654 mapping = &display->vbt.sdvo_mappings[1]; 2655 2656 if (mapping->initialized && 2657 intel_gmbus_is_valid_pin(display, mapping->i2c_pin)) 2658 pin = mapping->i2c_pin; 2659 else 2660 pin = GMBUS_PIN_DPB; 2661 2662 drm_dbg_kms(display->drm, "[ENCODER:%d:%s] I2C pin %d, target addr 0x%x\n", 2663 sdvo->base.base.base.id, sdvo->base.base.name, 2664 pin, sdvo->target_addr); 2665 2666 sdvo->i2c = intel_gmbus_get_adapter(display, pin); 2667 2668 /* 2669 * With gmbus we should be able to drive sdvo i2c at 2MHz, but somehow 2670 * our code totally fails once we start using gmbus. Hence fall back to 2671 * bit banging for now. 2672 */ 2673 intel_gmbus_force_bit(sdvo->i2c, true); 2674 } 2675 2676 /* undo any changes intel_sdvo_select_i2c_bus() did to sdvo->i2c */ 2677 static void 2678 intel_sdvo_unselect_i2c_bus(struct intel_sdvo *sdvo) 2679 { 2680 intel_gmbus_force_bit(sdvo->i2c, false); 2681 } 2682 2683 static bool 2684 intel_sdvo_is_hdmi_connector(struct intel_sdvo *intel_sdvo) 2685 { 2686 return intel_sdvo_check_supp_encode(intel_sdvo); 2687 } 2688 2689 static u8 2690 intel_sdvo_get_target_addr(struct intel_sdvo *sdvo) 2691 { 2692 struct intel_display *display = to_intel_display(&sdvo->base); 2693 const struct sdvo_device_mapping *my_mapping, *other_mapping; 2694 2695 if (sdvo->base.port == PORT_B) { 2696 my_mapping = &display->vbt.sdvo_mappings[0]; 2697 other_mapping = &display->vbt.sdvo_mappings[1]; 2698 } else { 2699 my_mapping = &display->vbt.sdvo_mappings[1]; 2700 other_mapping = &display->vbt.sdvo_mappings[0]; 2701 } 2702 2703 /* If the BIOS described our SDVO device, take advantage of it. */ 2704 if (my_mapping->target_addr) 2705 return my_mapping->target_addr; 2706 2707 /* 2708 * If the BIOS only described a different SDVO device, use the 2709 * address that it isn't using. 2710 */ 2711 if (other_mapping->target_addr) { 2712 if (other_mapping->target_addr == 0x70) 2713 return 0x72; 2714 else 2715 return 0x70; 2716 } 2717 2718 /* 2719 * No SDVO device info is found for another DVO port, 2720 * so use mapping assumption we had before BIOS parsing. 2721 */ 2722 if (sdvo->base.port == PORT_B) 2723 return 0x70; 2724 else 2725 return 0x72; 2726 } 2727 2728 static int 2729 intel_sdvo_init_ddc_proxy(struct intel_sdvo_ddc *ddc, 2730 struct intel_sdvo *sdvo, int bit); 2731 2732 static int 2733 intel_sdvo_connector_init(struct intel_sdvo_connector *connector, 2734 struct intel_sdvo *encoder) 2735 { 2736 struct intel_display *display = to_intel_display(&encoder->base); 2737 struct intel_sdvo_ddc *ddc = NULL; 2738 int ret; 2739 2740 if (HAS_DDC(connector)) 2741 ddc = intel_sdvo_select_ddc_bus(encoder, connector); 2742 2743 ret = drm_connector_init_with_ddc(encoder->base.base.dev, 2744 &connector->base.base, 2745 &intel_sdvo_connector_funcs, 2746 connector->base.base.connector_type, 2747 ddc ? &ddc->ddc : NULL); 2748 if (ret < 0) 2749 return ret; 2750 2751 drm_connector_helper_add(&connector->base.base, 2752 &intel_sdvo_connector_helper_funcs); 2753 2754 connector->base.base.display_info.subpixel_order = SubPixelHorizontalRGB; 2755 connector->base.base.interlace_allowed = true; 2756 connector->base.get_hw_state = intel_sdvo_connector_get_hw_state; 2757 2758 intel_connector_attach_encoder(&connector->base, &encoder->base); 2759 2760 if (ddc) 2761 drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s] using %s\n", 2762 connector->base.base.base.id, connector->base.base.name, 2763 ddc->ddc.name); 2764 2765 return 0; 2766 } 2767 2768 static void 2769 intel_sdvo_add_hdmi_properties(struct intel_sdvo *intel_sdvo, 2770 struct intel_sdvo_connector *connector) 2771 { 2772 intel_attach_force_audio_property(&connector->base.base); 2773 if (intel_sdvo->colorimetry_cap & SDVO_COLORIMETRY_RGB220) 2774 intel_attach_broadcast_rgb_property(&connector->base.base); 2775 intel_attach_aspect_ratio_property(&connector->base.base); 2776 } 2777 2778 static struct intel_sdvo_connector *intel_sdvo_connector_alloc(void) 2779 { 2780 struct intel_sdvo_connector *sdvo_connector; 2781 struct intel_sdvo_connector_state *conn_state; 2782 2783 sdvo_connector = kzalloc_obj(*sdvo_connector); 2784 if (!sdvo_connector) 2785 return NULL; 2786 2787 conn_state = kzalloc_obj(*conn_state); 2788 if (!conn_state) { 2789 kfree(sdvo_connector); 2790 return NULL; 2791 } 2792 2793 __drm_atomic_helper_connector_reset(&sdvo_connector->base.base, 2794 &conn_state->base.base); 2795 2796 intel_panel_init_alloc(&sdvo_connector->base); 2797 2798 return sdvo_connector; 2799 } 2800 2801 static bool 2802 intel_sdvo_dvi_init(struct intel_sdvo *intel_sdvo, u16 type) 2803 { 2804 struct intel_display *display = to_intel_display(&intel_sdvo->base); 2805 struct drm_encoder *encoder = &intel_sdvo->base.base; 2806 struct drm_connector *connector; 2807 struct intel_encoder *intel_encoder = to_intel_encoder(encoder); 2808 struct intel_connector *intel_connector; 2809 struct intel_sdvo_connector *intel_sdvo_connector; 2810 2811 drm_dbg_kms(display->drm, "initialising DVI type 0x%x\n", type); 2812 2813 intel_sdvo_connector = intel_sdvo_connector_alloc(); 2814 if (!intel_sdvo_connector) 2815 return false; 2816 2817 intel_sdvo_connector->output_flag = type; 2818 2819 intel_connector = &intel_sdvo_connector->base; 2820 connector = &intel_connector->base; 2821 if (intel_sdvo_get_hotplug_support(intel_sdvo) & 2822 intel_sdvo_connector->output_flag) { 2823 intel_sdvo->hotplug_active |= intel_sdvo_connector->output_flag; 2824 /* 2825 * Some SDVO devices have one-shot hotplug interrupts. 2826 * Ensure that they get re-enabled when an interrupt happens. 2827 */ 2828 intel_connector->polled = DRM_CONNECTOR_POLL_HPD; 2829 intel_encoder->hotplug = intel_sdvo_hotplug; 2830 intel_sdvo_enable_hotplug(intel_encoder); 2831 } else { 2832 intel_connector->polled = DRM_CONNECTOR_POLL_CONNECT | DRM_CONNECTOR_POLL_DISCONNECT; 2833 } 2834 intel_connector->base.polled = intel_connector->polled; 2835 encoder->encoder_type = DRM_MODE_ENCODER_TMDS; 2836 connector->connector_type = DRM_MODE_CONNECTOR_DVID; 2837 2838 if (intel_sdvo_is_hdmi_connector(intel_sdvo)) { 2839 connector->connector_type = DRM_MODE_CONNECTOR_HDMIA; 2840 intel_sdvo_connector->is_hdmi = true; 2841 } 2842 2843 if (intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo) < 0) { 2844 kfree(intel_sdvo_connector); 2845 return false; 2846 } 2847 2848 if (intel_sdvo_connector->is_hdmi) 2849 intel_sdvo_add_hdmi_properties(intel_sdvo, intel_sdvo_connector); 2850 2851 return true; 2852 } 2853 2854 static bool 2855 intel_sdvo_tv_init(struct intel_sdvo *intel_sdvo, u16 type) 2856 { 2857 struct intel_display *display = to_intel_display(&intel_sdvo->base); 2858 struct drm_encoder *encoder = &intel_sdvo->base.base; 2859 struct drm_connector *connector; 2860 struct intel_connector *intel_connector; 2861 struct intel_sdvo_connector *intel_sdvo_connector; 2862 2863 drm_dbg_kms(display->drm, "initialising TV type 0x%x\n", type); 2864 2865 intel_sdvo_connector = intel_sdvo_connector_alloc(); 2866 if (!intel_sdvo_connector) 2867 return false; 2868 2869 intel_connector = &intel_sdvo_connector->base; 2870 connector = &intel_connector->base; 2871 encoder->encoder_type = DRM_MODE_ENCODER_TVDAC; 2872 connector->connector_type = DRM_MODE_CONNECTOR_SVIDEO; 2873 2874 intel_sdvo_connector->output_flag = type; 2875 2876 if (intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo) < 0) { 2877 kfree(intel_sdvo_connector); 2878 return false; 2879 } 2880 2881 if (!intel_sdvo_tv_create_property(intel_sdvo, intel_sdvo_connector, type)) 2882 goto err; 2883 2884 if (!intel_sdvo_create_enhance_property(intel_sdvo, intel_sdvo_connector)) 2885 goto err; 2886 2887 return true; 2888 2889 err: 2890 intel_connector_destroy(connector); 2891 return false; 2892 } 2893 2894 static bool 2895 intel_sdvo_analog_init(struct intel_sdvo *intel_sdvo, u16 type) 2896 { 2897 struct intel_display *display = to_intel_display(&intel_sdvo->base); 2898 struct drm_encoder *encoder = &intel_sdvo->base.base; 2899 struct drm_connector *connector; 2900 struct intel_connector *intel_connector; 2901 struct intel_sdvo_connector *intel_sdvo_connector; 2902 2903 drm_dbg_kms(display->drm, "initialising analog type 0x%x\n", type); 2904 2905 intel_sdvo_connector = intel_sdvo_connector_alloc(); 2906 if (!intel_sdvo_connector) 2907 return false; 2908 2909 intel_connector = &intel_sdvo_connector->base; 2910 connector = &intel_connector->base; 2911 intel_connector->polled = DRM_CONNECTOR_POLL_CONNECT; 2912 intel_connector->base.polled = intel_connector->polled; 2913 encoder->encoder_type = DRM_MODE_ENCODER_DAC; 2914 connector->connector_type = DRM_MODE_CONNECTOR_VGA; 2915 2916 intel_sdvo_connector->output_flag = type; 2917 2918 if (intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo) < 0) { 2919 kfree(intel_sdvo_connector); 2920 return false; 2921 } 2922 2923 return true; 2924 } 2925 2926 static bool 2927 intel_sdvo_lvds_init(struct intel_sdvo *intel_sdvo, u16 type) 2928 { 2929 struct intel_display *display = to_intel_display(&intel_sdvo->base); 2930 struct drm_encoder *encoder = &intel_sdvo->base.base; 2931 struct drm_connector *connector; 2932 struct intel_connector *intel_connector; 2933 struct intel_sdvo_connector *intel_sdvo_connector; 2934 2935 drm_dbg_kms(display->drm, "initialising LVDS type 0x%x\n", type); 2936 2937 intel_sdvo_connector = intel_sdvo_connector_alloc(); 2938 if (!intel_sdvo_connector) 2939 return false; 2940 2941 intel_connector = &intel_sdvo_connector->base; 2942 connector = &intel_connector->base; 2943 encoder->encoder_type = DRM_MODE_ENCODER_LVDS; 2944 connector->connector_type = DRM_MODE_CONNECTOR_LVDS; 2945 2946 intel_sdvo_connector->output_flag = type; 2947 2948 if (intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo) < 0) { 2949 kfree(intel_sdvo_connector); 2950 return false; 2951 } 2952 2953 if (!intel_sdvo_create_enhance_property(intel_sdvo, intel_sdvo_connector)) 2954 goto err; 2955 2956 intel_bios_init_panel_late(display, &intel_connector->panel, NULL, NULL); 2957 2958 /* 2959 * Fetch modes from VBT. For SDVO prefer the VBT mode since some 2960 * SDVO->LVDS transcoders can't cope with the EDID mode. 2961 */ 2962 intel_panel_add_vbt_sdvo_fixed_mode(intel_connector); 2963 2964 if (!intel_panel_preferred_fixed_mode(intel_connector)) { 2965 mutex_lock(&display->drm->mode_config.mutex); 2966 2967 intel_ddc_get_modes(connector, connector->ddc); 2968 intel_panel_add_edid_fixed_modes(intel_connector, false); 2969 2970 mutex_unlock(&display->drm->mode_config.mutex); 2971 } 2972 2973 intel_panel_init(intel_connector, NULL); 2974 2975 if (!intel_panel_preferred_fixed_mode(intel_connector)) 2976 goto err; 2977 2978 return true; 2979 2980 err: 2981 intel_connector_destroy(connector); 2982 return false; 2983 } 2984 2985 static u16 intel_sdvo_filter_output_flags(u16 flags) 2986 { 2987 flags &= SDVO_OUTPUT_MASK; 2988 2989 /* SDVO requires XXX1 function may not exist unless it has XXX0 function.*/ 2990 if (!(flags & SDVO_OUTPUT_TMDS0)) 2991 flags &= ~SDVO_OUTPUT_TMDS1; 2992 2993 if (!(flags & SDVO_OUTPUT_RGB0)) 2994 flags &= ~SDVO_OUTPUT_RGB1; 2995 2996 if (!(flags & SDVO_OUTPUT_LVDS0)) 2997 flags &= ~SDVO_OUTPUT_LVDS1; 2998 2999 return flags; 3000 } 3001 3002 static bool intel_sdvo_output_init(struct intel_sdvo *sdvo, u16 type) 3003 { 3004 if (type & SDVO_TMDS_MASK) 3005 return intel_sdvo_dvi_init(sdvo, type); 3006 else if (type & SDVO_TV_MASK) 3007 return intel_sdvo_tv_init(sdvo, type); 3008 else if (type & SDVO_RGB_MASK) 3009 return intel_sdvo_analog_init(sdvo, type); 3010 else if (type & SDVO_LVDS_MASK) 3011 return intel_sdvo_lvds_init(sdvo, type); 3012 else 3013 return false; 3014 } 3015 3016 static bool 3017 intel_sdvo_output_setup(struct intel_sdvo *intel_sdvo) 3018 { 3019 struct intel_display *display = to_intel_display(&intel_sdvo->base); 3020 static const u16 probe_order[] = { 3021 SDVO_OUTPUT_TMDS0, 3022 SDVO_OUTPUT_TMDS1, 3023 /* TV has no XXX1 function block */ 3024 SDVO_OUTPUT_SVID0, 3025 SDVO_OUTPUT_CVBS0, 3026 SDVO_OUTPUT_YPRPB0, 3027 SDVO_OUTPUT_RGB0, 3028 SDVO_OUTPUT_RGB1, 3029 SDVO_OUTPUT_LVDS0, 3030 SDVO_OUTPUT_LVDS1, 3031 }; 3032 u16 flags; 3033 int i; 3034 3035 flags = intel_sdvo_filter_output_flags(intel_sdvo->caps.output_flags); 3036 3037 if (flags == 0) { 3038 drm_dbg_kms(display->drm, 3039 "%s: Unknown SDVO output type (0x%04x)\n", 3040 SDVO_NAME(intel_sdvo), intel_sdvo->caps.output_flags); 3041 return false; 3042 } 3043 3044 for (i = 0; i < ARRAY_SIZE(probe_order); i++) { 3045 u16 type = flags & probe_order[i]; 3046 3047 if (!type) 3048 continue; 3049 3050 if (!intel_sdvo_output_init(intel_sdvo, type)) 3051 return false; 3052 } 3053 3054 intel_sdvo->base.pipe_mask = ~0; 3055 3056 return true; 3057 } 3058 3059 static void intel_sdvo_output_cleanup(struct intel_sdvo *intel_sdvo) 3060 { 3061 struct intel_display *display = to_intel_display(&intel_sdvo->base); 3062 struct drm_connector *connector, *tmp; 3063 3064 list_for_each_entry_safe(connector, tmp, 3065 &display->drm->mode_config.connector_list, head) { 3066 if (intel_attached_encoder(to_intel_connector(connector)) == &intel_sdvo->base) { 3067 drm_connector_unregister(connector); 3068 intel_connector_destroy(connector); 3069 } 3070 } 3071 } 3072 3073 static bool intel_sdvo_tv_create_property(struct intel_sdvo *intel_sdvo, 3074 struct intel_sdvo_connector *intel_sdvo_connector, 3075 int type) 3076 { 3077 struct intel_display *display = to_intel_display(&intel_sdvo->base); 3078 struct intel_sdvo_tv_format format; 3079 u32 format_map, i; 3080 3081 if (!intel_sdvo_set_target_output(intel_sdvo, type)) 3082 return false; 3083 3084 BUILD_BUG_ON(sizeof(format) != 6); 3085 if (!intel_sdvo_get_value(intel_sdvo, 3086 SDVO_CMD_GET_SUPPORTED_TV_FORMATS, 3087 &format, sizeof(format))) 3088 return false; 3089 3090 memcpy(&format_map, &format, min(sizeof(format_map), sizeof(format))); 3091 3092 if (format_map == 0) 3093 return false; 3094 3095 intel_sdvo_connector->format_supported_num = 0; 3096 for (i = 0 ; i < TV_FORMAT_NUM; i++) 3097 if (format_map & (1 << i)) 3098 intel_sdvo_connector->tv_format_supported[intel_sdvo_connector->format_supported_num++] = i; 3099 3100 3101 intel_sdvo_connector->tv_format = 3102 drm_property_create(display->drm, DRM_MODE_PROP_ENUM, 3103 "mode", intel_sdvo_connector->format_supported_num); 3104 if (!intel_sdvo_connector->tv_format) 3105 return false; 3106 3107 for (i = 0; i < intel_sdvo_connector->format_supported_num; i++) 3108 drm_property_add_enum(intel_sdvo_connector->tv_format, i, 3109 tv_format_names[intel_sdvo_connector->tv_format_supported[i]]); 3110 3111 intel_sdvo_connector->base.base.state->tv.legacy_mode = intel_sdvo_connector->tv_format_supported[0]; 3112 drm_object_attach_property(&intel_sdvo_connector->base.base.base, 3113 intel_sdvo_connector->tv_format, 0); 3114 return true; 3115 3116 } 3117 3118 #define _ENHANCEMENT(state_assignment, name, NAME) do { \ 3119 if (enhancements.name) { \ 3120 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_MAX_##NAME, &data_value, 4) || \ 3121 !intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_##NAME, &response, 2)) \ 3122 return false; \ 3123 intel_sdvo_connector->name = \ 3124 drm_property_create_range(display->drm, 0, #name, 0, data_value[0]); \ 3125 if (!intel_sdvo_connector->name) return false; \ 3126 state_assignment = response; \ 3127 drm_object_attach_property(&connector->base, \ 3128 intel_sdvo_connector->name, 0); \ 3129 drm_dbg_kms(display->drm, #name ": max %d, default %d, current %d\n", \ 3130 data_value[0], data_value[1], response); \ 3131 } \ 3132 } while (0) 3133 3134 #define ENHANCEMENT(state, name, NAME) _ENHANCEMENT((state)->name, name, NAME) 3135 3136 static bool 3137 intel_sdvo_create_enhance_property_tv(struct intel_sdvo *intel_sdvo, 3138 struct intel_sdvo_connector *intel_sdvo_connector, 3139 struct intel_sdvo_enhancements_reply enhancements) 3140 { 3141 struct intel_display *display = to_intel_display(&intel_sdvo->base); 3142 struct drm_connector *connector = &intel_sdvo_connector->base.base; 3143 struct drm_connector_state *conn_state = connector->state; 3144 struct intel_sdvo_connector_state *sdvo_state = 3145 to_intel_sdvo_connector_state(conn_state); 3146 u16 response, data_value[2]; 3147 3148 /* when horizontal overscan is supported, Add the left/right property */ 3149 if (enhancements.overscan_h) { 3150 if (!intel_sdvo_get_value(intel_sdvo, 3151 SDVO_CMD_GET_MAX_OVERSCAN_H, 3152 &data_value, 4)) 3153 return false; 3154 3155 if (!intel_sdvo_get_value(intel_sdvo, 3156 SDVO_CMD_GET_OVERSCAN_H, 3157 &response, 2)) 3158 return false; 3159 3160 sdvo_state->tv.overscan_h = response; 3161 3162 intel_sdvo_connector->max_hscan = data_value[0]; 3163 intel_sdvo_connector->left = 3164 drm_property_create_range(display->drm, 0, "left_margin", 0, data_value[0]); 3165 if (!intel_sdvo_connector->left) 3166 return false; 3167 3168 drm_object_attach_property(&connector->base, 3169 intel_sdvo_connector->left, 0); 3170 3171 intel_sdvo_connector->right = 3172 drm_property_create_range(display->drm, 0, "right_margin", 0, data_value[0]); 3173 if (!intel_sdvo_connector->right) 3174 return false; 3175 3176 drm_object_attach_property(&connector->base, 3177 intel_sdvo_connector->right, 0); 3178 drm_dbg_kms(display->drm, "h_overscan: max %d, default %d, current %d\n", 3179 data_value[0], data_value[1], response); 3180 } 3181 3182 if (enhancements.overscan_v) { 3183 if (!intel_sdvo_get_value(intel_sdvo, 3184 SDVO_CMD_GET_MAX_OVERSCAN_V, 3185 &data_value, 4)) 3186 return false; 3187 3188 if (!intel_sdvo_get_value(intel_sdvo, 3189 SDVO_CMD_GET_OVERSCAN_V, 3190 &response, 2)) 3191 return false; 3192 3193 sdvo_state->tv.overscan_v = response; 3194 3195 intel_sdvo_connector->max_vscan = data_value[0]; 3196 intel_sdvo_connector->top = 3197 drm_property_create_range(display->drm, 0, 3198 "top_margin", 0, data_value[0]); 3199 if (!intel_sdvo_connector->top) 3200 return false; 3201 3202 drm_object_attach_property(&connector->base, 3203 intel_sdvo_connector->top, 0); 3204 3205 intel_sdvo_connector->bottom = 3206 drm_property_create_range(display->drm, 0, 3207 "bottom_margin", 0, data_value[0]); 3208 if (!intel_sdvo_connector->bottom) 3209 return false; 3210 3211 drm_object_attach_property(&connector->base, 3212 intel_sdvo_connector->bottom, 0); 3213 drm_dbg_kms(display->drm, "v_overscan: max %d, default %d, current %d\n", 3214 data_value[0], data_value[1], response); 3215 } 3216 3217 ENHANCEMENT(&sdvo_state->tv, hpos, HPOS); 3218 ENHANCEMENT(&sdvo_state->tv, vpos, VPOS); 3219 ENHANCEMENT(&conn_state->tv, saturation, SATURATION); 3220 ENHANCEMENT(&conn_state->tv, contrast, CONTRAST); 3221 ENHANCEMENT(&conn_state->tv, hue, HUE); 3222 ENHANCEMENT(&conn_state->tv, brightness, BRIGHTNESS); 3223 ENHANCEMENT(&sdvo_state->tv, sharpness, SHARPNESS); 3224 ENHANCEMENT(&sdvo_state->tv, flicker_filter, FLICKER_FILTER); 3225 ENHANCEMENT(&sdvo_state->tv, flicker_filter_adaptive, FLICKER_FILTER_ADAPTIVE); 3226 ENHANCEMENT(&sdvo_state->tv, flicker_filter_2d, FLICKER_FILTER_2D); 3227 _ENHANCEMENT(sdvo_state->tv.chroma_filter, tv_chroma_filter, TV_CHROMA_FILTER); 3228 _ENHANCEMENT(sdvo_state->tv.luma_filter, tv_luma_filter, TV_LUMA_FILTER); 3229 3230 if (enhancements.dot_crawl) { 3231 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_DOT_CRAWL, &response, 2)) 3232 return false; 3233 3234 sdvo_state->tv.dot_crawl = response & 0x1; 3235 intel_sdvo_connector->dot_crawl = 3236 drm_property_create_range(display->drm, 0, "dot_crawl", 0, 1); 3237 if (!intel_sdvo_connector->dot_crawl) 3238 return false; 3239 3240 drm_object_attach_property(&connector->base, 3241 intel_sdvo_connector->dot_crawl, 0); 3242 drm_dbg_kms(display->drm, "dot crawl: current %d\n", response); 3243 } 3244 3245 return true; 3246 } 3247 3248 static bool 3249 intel_sdvo_create_enhance_property_lvds(struct intel_sdvo *intel_sdvo, 3250 struct intel_sdvo_connector *intel_sdvo_connector, 3251 struct intel_sdvo_enhancements_reply enhancements) 3252 { 3253 struct intel_display *display = to_intel_display(&intel_sdvo->base); 3254 struct drm_connector *connector = &intel_sdvo_connector->base.base; 3255 u16 response, data_value[2]; 3256 3257 ENHANCEMENT(&connector->state->tv, brightness, BRIGHTNESS); 3258 3259 return true; 3260 } 3261 #undef ENHANCEMENT 3262 #undef _ENHANCEMENT 3263 3264 static bool intel_sdvo_create_enhance_property(struct intel_sdvo *intel_sdvo, 3265 struct intel_sdvo_connector *intel_sdvo_connector) 3266 { 3267 struct intel_display *display = to_intel_display(&intel_sdvo->base); 3268 union { 3269 struct intel_sdvo_enhancements_reply reply; 3270 u16 response; 3271 } enhancements; 3272 3273 BUILD_BUG_ON(sizeof(enhancements) != 2); 3274 3275 if (!intel_sdvo_get_value(intel_sdvo, 3276 SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS, 3277 &enhancements, sizeof(enhancements)) || 3278 enhancements.response == 0) { 3279 drm_dbg_kms(display->drm, "No enhancement is supported\n"); 3280 return true; 3281 } 3282 3283 if (IS_TV(intel_sdvo_connector)) 3284 return intel_sdvo_create_enhance_property_tv(intel_sdvo, intel_sdvo_connector, enhancements.reply); 3285 else if (IS_LVDS(intel_sdvo_connector)) 3286 return intel_sdvo_create_enhance_property_lvds(intel_sdvo, intel_sdvo_connector, enhancements.reply); 3287 else 3288 return true; 3289 } 3290 3291 static int intel_sdvo_ddc_proxy_xfer(struct i2c_adapter *adapter, 3292 struct i2c_msg *msgs, 3293 int num) 3294 { 3295 struct intel_sdvo_ddc *ddc = adapter->algo_data; 3296 struct intel_sdvo *sdvo = ddc->sdvo; 3297 3298 if (!__intel_sdvo_set_control_bus_switch(sdvo, 1 << ddc->ddc_bus)) 3299 return -EIO; 3300 3301 return sdvo->i2c->algo->master_xfer(sdvo->i2c, msgs, num); 3302 } 3303 3304 static u32 intel_sdvo_ddc_proxy_func(struct i2c_adapter *adapter) 3305 { 3306 struct intel_sdvo_ddc *ddc = adapter->algo_data; 3307 struct intel_sdvo *sdvo = ddc->sdvo; 3308 3309 return sdvo->i2c->algo->functionality(sdvo->i2c); 3310 } 3311 3312 static const struct i2c_algorithm intel_sdvo_ddc_proxy = { 3313 .master_xfer = intel_sdvo_ddc_proxy_xfer, 3314 .functionality = intel_sdvo_ddc_proxy_func 3315 }; 3316 3317 static void proxy_lock_bus(struct i2c_adapter *adapter, 3318 unsigned int flags) 3319 { 3320 struct intel_sdvo_ddc *ddc = adapter->algo_data; 3321 struct intel_sdvo *sdvo = ddc->sdvo; 3322 3323 i2c_lock_bus(sdvo->i2c, flags); 3324 } 3325 3326 static int proxy_trylock_bus(struct i2c_adapter *adapter, 3327 unsigned int flags) 3328 { 3329 struct intel_sdvo_ddc *ddc = adapter->algo_data; 3330 struct intel_sdvo *sdvo = ddc->sdvo; 3331 3332 return i2c_trylock_bus(sdvo->i2c, flags); 3333 } 3334 3335 static void proxy_unlock_bus(struct i2c_adapter *adapter, 3336 unsigned int flags) 3337 { 3338 struct intel_sdvo_ddc *ddc = adapter->algo_data; 3339 struct intel_sdvo *sdvo = ddc->sdvo; 3340 3341 i2c_unlock_bus(sdvo->i2c, flags); 3342 } 3343 3344 static const struct i2c_lock_operations proxy_lock_ops = { 3345 .lock_bus = proxy_lock_bus, 3346 .trylock_bus = proxy_trylock_bus, 3347 .unlock_bus = proxy_unlock_bus, 3348 }; 3349 3350 static int 3351 intel_sdvo_init_ddc_proxy(struct intel_sdvo_ddc *ddc, 3352 struct intel_sdvo *sdvo, int ddc_bus) 3353 { 3354 struct intel_display *display = to_intel_display(&sdvo->base); 3355 struct pci_dev *pdev = to_pci_dev(display->drm->dev); 3356 3357 ddc->sdvo = sdvo; 3358 ddc->ddc_bus = ddc_bus; 3359 3360 ddc->ddc.owner = THIS_MODULE; 3361 snprintf(ddc->ddc.name, I2C_NAME_SIZE, "SDVO %c DDC%d", 3362 port_name(sdvo->base.port), ddc_bus); 3363 ddc->ddc.dev.parent = &pdev->dev; 3364 ddc->ddc.algo_data = ddc; 3365 ddc->ddc.algo = &intel_sdvo_ddc_proxy; 3366 ddc->ddc.lock_ops = &proxy_lock_ops; 3367 3368 return i2c_add_adapter(&ddc->ddc); 3369 } 3370 3371 static bool is_sdvo_port_valid(struct intel_display *display, enum port port) 3372 { 3373 if (HAS_PCH_SPLIT(display)) 3374 return port == PORT_B; 3375 else 3376 return port == PORT_B || port == PORT_C; 3377 } 3378 3379 static bool assert_sdvo_port_valid(struct intel_display *display, enum port port) 3380 { 3381 return !drm_WARN(display->drm, !is_sdvo_port_valid(display, port), 3382 "Platform does not support SDVO %c\n", port_name(port)); 3383 } 3384 3385 bool intel_sdvo_init(struct intel_display *display, 3386 intel_reg_t sdvo_reg, enum port port) 3387 { 3388 struct intel_encoder *intel_encoder; 3389 struct intel_sdvo *intel_sdvo; 3390 int i; 3391 3392 if (!assert_port_valid(display, port)) 3393 return false; 3394 3395 if (!assert_sdvo_port_valid(display, port)) 3396 return false; 3397 3398 intel_sdvo = kzalloc_obj(*intel_sdvo); 3399 if (!intel_sdvo) 3400 return false; 3401 3402 /* encoder type will be decided later */ 3403 intel_encoder = &intel_sdvo->base; 3404 intel_encoder->type = INTEL_OUTPUT_SDVO; 3405 intel_encoder->power_domain = POWER_DOMAIN_PORT_OTHER; 3406 intel_encoder->port = port; 3407 3408 drm_encoder_init(display->drm, &intel_encoder->base, 3409 &intel_sdvo_enc_funcs, 0, 3410 "SDVO %c", port_name(port)); 3411 3412 intel_sdvo->sdvo_reg = sdvo_reg; 3413 intel_sdvo->target_addr = intel_sdvo_get_target_addr(intel_sdvo) >> 1; 3414 3415 intel_sdvo_select_i2c_bus(intel_sdvo); 3416 3417 /* Read the regs to test if we can talk to the device */ 3418 for (i = 0; i < 0x40; i++) { 3419 u8 byte; 3420 3421 if (!intel_sdvo_read_byte(intel_sdvo, i, &byte)) { 3422 drm_dbg_kms(display->drm, 3423 "No SDVO device found on %s\n", 3424 SDVO_NAME(intel_sdvo)); 3425 goto err; 3426 } 3427 } 3428 3429 intel_encoder->compute_config = intel_sdvo_compute_config; 3430 if (HAS_PCH_SPLIT(display)) { 3431 intel_encoder->disable = pch_disable_sdvo; 3432 intel_encoder->post_disable = pch_post_disable_sdvo; 3433 } else { 3434 intel_encoder->disable = intel_disable_sdvo; 3435 } 3436 intel_encoder->pre_enable = intel_sdvo_pre_enable; 3437 intel_encoder->enable = intel_enable_sdvo; 3438 intel_encoder->audio_enable = intel_sdvo_enable_audio; 3439 intel_encoder->audio_disable = intel_sdvo_disable_audio; 3440 intel_encoder->get_hw_state = intel_sdvo_get_hw_state; 3441 intel_encoder->get_config = intel_sdvo_get_config; 3442 3443 /* In default case sdvo lvds is false */ 3444 if (!intel_sdvo_get_capabilities(intel_sdvo, &intel_sdvo->caps)) 3445 goto err; 3446 3447 intel_sdvo->colorimetry_cap = 3448 intel_sdvo_get_colorimetry_cap(intel_sdvo); 3449 3450 for (i = 0; i < ARRAY_SIZE(intel_sdvo->ddc); i++) { 3451 int ret; 3452 3453 ret = intel_sdvo_init_ddc_proxy(&intel_sdvo->ddc[i], 3454 intel_sdvo, i + 1); 3455 if (ret) 3456 goto err; 3457 } 3458 3459 if (!intel_sdvo_output_setup(intel_sdvo)) { 3460 drm_dbg_kms(display->drm, 3461 "SDVO output failed to setup on %s\n", 3462 SDVO_NAME(intel_sdvo)); 3463 /* Output_setup can leave behind connectors! */ 3464 goto err_output; 3465 } 3466 3467 /* 3468 * Only enable the hotplug irq if we need it, to work around noisy 3469 * hotplug lines. 3470 */ 3471 if (intel_sdvo->hotplug_active) { 3472 if (intel_sdvo->base.port == PORT_B) 3473 intel_encoder->hpd_pin = HPD_SDVO_B; 3474 else 3475 intel_encoder->hpd_pin = HPD_SDVO_C; 3476 } 3477 3478 /* 3479 * Cloning SDVO with anything is often impossible, since the SDVO 3480 * encoder can request a special input timing mode. And even if that's 3481 * not the case we have evidence that cloning a plain unscaled mode with 3482 * VGA doesn't really work. Furthermore the cloning flags are way too 3483 * simplistic anyway to express such constraints, so just give up on 3484 * cloning for SDVO encoders. 3485 */ 3486 intel_sdvo->base.cloneable = 0; 3487 3488 /* Set the input timing to the screen. Assume always input 0. */ 3489 if (!intel_sdvo_set_target_input(intel_sdvo)) 3490 goto err_output; 3491 3492 if (!intel_sdvo_get_input_pixel_clock_range(intel_sdvo, 3493 &intel_sdvo->pixel_clock_min, 3494 &intel_sdvo->pixel_clock_max)) 3495 goto err_output; 3496 3497 drm_dbg_kms(display->drm, "%s device VID/DID: %02X:%02X.%02X, " 3498 "clock range %dMHz - %dMHz, " 3499 "num inputs: %d, " 3500 "output 1: %c, output 2: %c\n", 3501 SDVO_NAME(intel_sdvo), 3502 intel_sdvo->caps.vendor_id, intel_sdvo->caps.device_id, 3503 intel_sdvo->caps.device_rev_id, 3504 intel_sdvo->pixel_clock_min / 1000, 3505 intel_sdvo->pixel_clock_max / 1000, 3506 intel_sdvo->caps.sdvo_num_inputs, 3507 /* check currently supported outputs */ 3508 intel_sdvo->caps.output_flags & 3509 (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_RGB0 | 3510 SDVO_OUTPUT_LVDS0 | SDVO_OUTPUT_SVID0 | 3511 SDVO_OUTPUT_CVBS0 | SDVO_OUTPUT_YPRPB0) ? 'Y' : 'N', 3512 intel_sdvo->caps.output_flags & 3513 (SDVO_OUTPUT_TMDS1 | SDVO_OUTPUT_RGB1 | 3514 SDVO_OUTPUT_LVDS1) ? 'Y' : 'N'); 3515 return true; 3516 3517 err_output: 3518 intel_sdvo_output_cleanup(intel_sdvo); 3519 err: 3520 intel_sdvo_unselect_i2c_bus(intel_sdvo); 3521 intel_sdvo_encoder_destroy(&intel_encoder->base); 3522 3523 return false; 3524 } 3525