1 /* 2 * Copyright 2006 Dave Airlie <airlied@linux.ie> 3 * Copyright © 2006-2007 Intel Corporation 4 * Jesse Barnes <jesse.barnes@intel.com> 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice (including the next 14 * paragraph) shall be included in all copies or substantial portions of the 15 * Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 23 * DEALINGS IN THE SOFTWARE. 24 * 25 * Authors: 26 * Eric Anholt <eric@anholt.net> 27 */ 28 29 #include <linux/delay.h> 30 #include <linux/export.h> 31 #include <linux/i2c.h> 32 #include <linux/slab.h> 33 34 #include <drm/display/drm_hdmi_helper.h> 35 #include <drm/drm_atomic_helper.h> 36 #include <drm/drm_crtc.h> 37 #include <drm/drm_edid.h> 38 #include <drm/drm_eld.h> 39 #include <drm/drm_print.h> 40 #include <drm/drm_probe_helper.h> 41 42 #include "intel_atomic.h" 43 #include "intel_audio.h" 44 #include "intel_connector.h" 45 #include "intel_crtc.h" 46 #include "intel_de.h" 47 #include "intel_display_driver.h" 48 #include "intel_display_regs.h" 49 #include "intel_display_types.h" 50 #include "intel_fifo_underrun.h" 51 #include "intel_gmbus.h" 52 #include "intel_hdmi.h" 53 #include "intel_hotplug.h" 54 #include "intel_link_bw.h" 55 #include "intel_panel.h" 56 #include "intel_sdvo.h" 57 #include "intel_sdvo_regs.h" 58 59 #define SDVO_TMDS_MASK (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_TMDS1) 60 #define SDVO_RGB_MASK (SDVO_OUTPUT_RGB0 | SDVO_OUTPUT_RGB1) 61 #define SDVO_LVDS_MASK (SDVO_OUTPUT_LVDS0 | SDVO_OUTPUT_LVDS1) 62 #define SDVO_TV_MASK (SDVO_OUTPUT_CVBS0 | SDVO_OUTPUT_SVID0 | SDVO_OUTPUT_YPRPB0) 63 64 #define SDVO_OUTPUT_MASK (SDVO_TMDS_MASK | SDVO_RGB_MASK | SDVO_LVDS_MASK | SDVO_TV_MASK) 65 66 #define IS_TV(c) ((c)->output_flag & SDVO_TV_MASK) 67 #define IS_TMDS(c) ((c)->output_flag & SDVO_TMDS_MASK) 68 #define IS_LVDS(c) ((c)->output_flag & SDVO_LVDS_MASK) 69 #define IS_TV_OR_LVDS(c) ((c)->output_flag & (SDVO_TV_MASK | SDVO_LVDS_MASK)) 70 #define IS_DIGITAL(c) ((c)->output_flag & (SDVO_TMDS_MASK | SDVO_LVDS_MASK)) 71 72 #define HAS_DDC(c) ((c)->output_flag & (SDVO_RGB_MASK | SDVO_TMDS_MASK | \ 73 SDVO_LVDS_MASK)) 74 75 static const char * const tv_format_names[] = { 76 "NTSC_M" , "NTSC_J" , "NTSC_443", 77 "PAL_B" , "PAL_D" , "PAL_G" , 78 "PAL_H" , "PAL_I" , "PAL_M" , 79 "PAL_N" , "PAL_NC" , "PAL_60" , 80 "SECAM_B" , "SECAM_D" , "SECAM_G" , 81 "SECAM_K" , "SECAM_K1", "SECAM_L" , 82 "SECAM_60" 83 }; 84 85 #define TV_FORMAT_NUM ARRAY_SIZE(tv_format_names) 86 87 struct intel_sdvo; 88 89 struct intel_sdvo_ddc { 90 struct i2c_adapter ddc; 91 struct intel_sdvo *sdvo; 92 u8 ddc_bus; 93 }; 94 95 struct intel_sdvo { 96 struct intel_encoder base; 97 98 struct i2c_adapter *i2c; 99 u8 target_addr; 100 101 struct intel_sdvo_ddc ddc[3]; 102 103 /* Register for the SDVO device: SDVOB or SDVOC */ 104 intel_reg_t sdvo_reg; 105 106 /* 107 * Capabilities of the SDVO device returned by 108 * intel_sdvo_get_capabilities() 109 */ 110 struct intel_sdvo_caps caps; 111 112 u8 colorimetry_cap; 113 114 /* Pixel clock limitations reported by the SDVO device, in kHz */ 115 int pixel_clock_min, pixel_clock_max; 116 117 /* 118 * Hotplug activation bits for this device 119 */ 120 u16 hotplug_active; 121 122 /* 123 * the sdvo flag gets lost in round trip: dtd->adjusted_mode->dtd 124 */ 125 u8 dtd_sdvo_flags; 126 }; 127 128 struct intel_sdvo_connector { 129 struct intel_connector base; 130 131 /* Mark the type of connector */ 132 u16 output_flag; 133 134 /* This contains all current supported TV format */ 135 u8 tv_format_supported[TV_FORMAT_NUM]; 136 int format_supported_num; 137 struct drm_property *tv_format; 138 139 /* add the property for the SDVO-TV */ 140 struct drm_property *left; 141 struct drm_property *right; 142 struct drm_property *top; 143 struct drm_property *bottom; 144 struct drm_property *hpos; 145 struct drm_property *vpos; 146 struct drm_property *contrast; 147 struct drm_property *saturation; 148 struct drm_property *hue; 149 struct drm_property *sharpness; 150 struct drm_property *flicker_filter; 151 struct drm_property *flicker_filter_adaptive; 152 struct drm_property *flicker_filter_2d; 153 struct drm_property *tv_chroma_filter; 154 struct drm_property *tv_luma_filter; 155 struct drm_property *dot_crawl; 156 157 /* add the property for the SDVO-TV/LVDS */ 158 struct drm_property *brightness; 159 160 /* this is to get the range of margin.*/ 161 u32 max_hscan, max_vscan; 162 163 /** 164 * This is set if we treat the device as HDMI, instead of DVI. 165 */ 166 bool is_hdmi; 167 }; 168 169 struct intel_sdvo_connector_state { 170 /* base.base: tv.saturation/contrast/hue/brightness */ 171 struct intel_digital_connector_state base; 172 173 struct { 174 unsigned overscan_h, overscan_v, hpos, vpos, sharpness; 175 unsigned flicker_filter, flicker_filter_2d, flicker_filter_adaptive; 176 unsigned chroma_filter, luma_filter, dot_crawl; 177 } tv; 178 }; 179 180 static struct intel_sdvo *to_sdvo(struct intel_encoder *encoder) 181 { 182 return container_of(encoder, struct intel_sdvo, base); 183 } 184 185 static struct intel_sdvo *intel_attached_sdvo(struct intel_connector *connector) 186 { 187 return to_sdvo(intel_attached_encoder(connector)); 188 } 189 190 static struct intel_sdvo_connector * 191 to_intel_sdvo_connector(struct drm_connector *connector) 192 { 193 return container_of(connector, struct intel_sdvo_connector, base.base); 194 } 195 196 #define to_intel_sdvo_connector_state(conn_state) \ 197 container_of_const((conn_state), struct intel_sdvo_connector_state, base.base) 198 199 static bool 200 intel_sdvo_output_setup(struct intel_sdvo *intel_sdvo); 201 static bool 202 intel_sdvo_tv_create_property(struct intel_sdvo *intel_sdvo, 203 struct intel_sdvo_connector *intel_sdvo_connector, 204 int type); 205 static bool 206 intel_sdvo_create_enhance_property(struct intel_sdvo *intel_sdvo, 207 struct intel_sdvo_connector *intel_sdvo_connector); 208 209 /* 210 * Writes the SDVOB or SDVOC with the given value, but always writes both 211 * SDVOB and SDVOC to work around apparent hardware issues (according to 212 * comments in the BIOS). 213 */ 214 static void intel_sdvo_write_sdvox(struct intel_sdvo *intel_sdvo, u32 val) 215 { 216 struct intel_display *display = to_intel_display(&intel_sdvo->base); 217 u32 bval = val, cval = val; 218 int i; 219 220 if (HAS_PCH_SPLIT(display)) { 221 intel_de_write(display, intel_sdvo->sdvo_reg, val); 222 intel_de_posting_read(display, intel_sdvo->sdvo_reg); 223 /* 224 * HW workaround, need to write this twice for issue 225 * that may result in first write getting masked. 226 */ 227 if (HAS_PCH_IBX(display)) { 228 intel_de_write(display, intel_sdvo->sdvo_reg, val); 229 intel_de_posting_read(display, intel_sdvo->sdvo_reg); 230 } 231 return; 232 } 233 234 if (intel_sdvo->base.port == PORT_B) 235 cval = intel_de_read(display, GEN3_SDVOC); 236 else 237 bval = intel_de_read(display, GEN3_SDVOB); 238 239 /* 240 * Write the registers twice for luck. Sometimes, 241 * writing them only once doesn't appear to 'stick'. 242 * The BIOS does this too. Yay, magic 243 */ 244 for (i = 0; i < 2; i++) { 245 intel_de_write(display, GEN3_SDVOB, bval); 246 intel_de_posting_read(display, GEN3_SDVOB); 247 248 intel_de_write(display, GEN3_SDVOC, cval); 249 intel_de_posting_read(display, GEN3_SDVOC); 250 } 251 } 252 253 static bool intel_sdvo_read_byte(struct intel_sdvo *intel_sdvo, u8 addr, u8 *ch) 254 { 255 struct intel_display *display = to_intel_display(&intel_sdvo->base); 256 struct i2c_msg msgs[] = { 257 { 258 .addr = intel_sdvo->target_addr, 259 .flags = 0, 260 .len = 1, 261 .buf = &addr, 262 }, 263 { 264 .addr = intel_sdvo->target_addr, 265 .flags = I2C_M_RD, 266 .len = 1, 267 .buf = ch, 268 } 269 }; 270 int ret; 271 272 if ((ret = i2c_transfer(intel_sdvo->i2c, msgs, 2)) == 2) 273 return true; 274 275 drm_dbg_kms(display->drm, "i2c transfer returned %d\n", ret); 276 return false; 277 } 278 279 #define SDVO_CMD_NAME_ENTRY(cmd_) { .cmd = SDVO_CMD_ ## cmd_, .name = #cmd_ } 280 281 /** Mapping of command numbers to names, for debug output */ 282 static const struct { 283 u8 cmd; 284 const char *name; 285 } __packed sdvo_cmd_names[] = { 286 SDVO_CMD_NAME_ENTRY(RESET), 287 SDVO_CMD_NAME_ENTRY(GET_DEVICE_CAPS), 288 SDVO_CMD_NAME_ENTRY(GET_FIRMWARE_REV), 289 SDVO_CMD_NAME_ENTRY(GET_TRAINED_INPUTS), 290 SDVO_CMD_NAME_ENTRY(GET_ACTIVE_OUTPUTS), 291 SDVO_CMD_NAME_ENTRY(SET_ACTIVE_OUTPUTS), 292 SDVO_CMD_NAME_ENTRY(GET_IN_OUT_MAP), 293 SDVO_CMD_NAME_ENTRY(SET_IN_OUT_MAP), 294 SDVO_CMD_NAME_ENTRY(GET_ATTACHED_DISPLAYS), 295 SDVO_CMD_NAME_ENTRY(GET_HOT_PLUG_SUPPORT), 296 SDVO_CMD_NAME_ENTRY(SET_ACTIVE_HOT_PLUG), 297 SDVO_CMD_NAME_ENTRY(GET_ACTIVE_HOT_PLUG), 298 SDVO_CMD_NAME_ENTRY(GET_INTERRUPT_EVENT_SOURCE), 299 SDVO_CMD_NAME_ENTRY(SET_TARGET_INPUT), 300 SDVO_CMD_NAME_ENTRY(SET_TARGET_OUTPUT), 301 SDVO_CMD_NAME_ENTRY(GET_INPUT_TIMINGS_PART1), 302 SDVO_CMD_NAME_ENTRY(GET_INPUT_TIMINGS_PART2), 303 SDVO_CMD_NAME_ENTRY(SET_INPUT_TIMINGS_PART1), 304 SDVO_CMD_NAME_ENTRY(SET_INPUT_TIMINGS_PART2), 305 SDVO_CMD_NAME_ENTRY(SET_OUTPUT_TIMINGS_PART1), 306 SDVO_CMD_NAME_ENTRY(SET_OUTPUT_TIMINGS_PART2), 307 SDVO_CMD_NAME_ENTRY(GET_OUTPUT_TIMINGS_PART1), 308 SDVO_CMD_NAME_ENTRY(GET_OUTPUT_TIMINGS_PART2), 309 SDVO_CMD_NAME_ENTRY(CREATE_PREFERRED_INPUT_TIMING), 310 SDVO_CMD_NAME_ENTRY(GET_PREFERRED_INPUT_TIMING_PART1), 311 SDVO_CMD_NAME_ENTRY(GET_PREFERRED_INPUT_TIMING_PART2), 312 SDVO_CMD_NAME_ENTRY(GET_INPUT_PIXEL_CLOCK_RANGE), 313 SDVO_CMD_NAME_ENTRY(GET_OUTPUT_PIXEL_CLOCK_RANGE), 314 SDVO_CMD_NAME_ENTRY(GET_SUPPORTED_CLOCK_RATE_MULTS), 315 SDVO_CMD_NAME_ENTRY(GET_CLOCK_RATE_MULT), 316 SDVO_CMD_NAME_ENTRY(SET_CLOCK_RATE_MULT), 317 SDVO_CMD_NAME_ENTRY(GET_SUPPORTED_TV_FORMATS), 318 SDVO_CMD_NAME_ENTRY(GET_TV_FORMAT), 319 SDVO_CMD_NAME_ENTRY(SET_TV_FORMAT), 320 SDVO_CMD_NAME_ENTRY(GET_SUPPORTED_POWER_STATES), 321 SDVO_CMD_NAME_ENTRY(GET_POWER_STATE), 322 SDVO_CMD_NAME_ENTRY(SET_ENCODER_POWER_STATE), 323 SDVO_CMD_NAME_ENTRY(SET_DISPLAY_POWER_STATE), 324 SDVO_CMD_NAME_ENTRY(SET_CONTROL_BUS_SWITCH), 325 SDVO_CMD_NAME_ENTRY(GET_SDTV_RESOLUTION_SUPPORT), 326 SDVO_CMD_NAME_ENTRY(GET_SCALED_HDTV_RESOLUTION_SUPPORT), 327 SDVO_CMD_NAME_ENTRY(GET_SUPPORTED_ENHANCEMENTS), 328 329 /* Add the op code for SDVO enhancements */ 330 SDVO_CMD_NAME_ENTRY(GET_MAX_HPOS), 331 SDVO_CMD_NAME_ENTRY(GET_HPOS), 332 SDVO_CMD_NAME_ENTRY(SET_HPOS), 333 SDVO_CMD_NAME_ENTRY(GET_MAX_VPOS), 334 SDVO_CMD_NAME_ENTRY(GET_VPOS), 335 SDVO_CMD_NAME_ENTRY(SET_VPOS), 336 SDVO_CMD_NAME_ENTRY(GET_MAX_SATURATION), 337 SDVO_CMD_NAME_ENTRY(GET_SATURATION), 338 SDVO_CMD_NAME_ENTRY(SET_SATURATION), 339 SDVO_CMD_NAME_ENTRY(GET_MAX_HUE), 340 SDVO_CMD_NAME_ENTRY(GET_HUE), 341 SDVO_CMD_NAME_ENTRY(SET_HUE), 342 SDVO_CMD_NAME_ENTRY(GET_MAX_CONTRAST), 343 SDVO_CMD_NAME_ENTRY(GET_CONTRAST), 344 SDVO_CMD_NAME_ENTRY(SET_CONTRAST), 345 SDVO_CMD_NAME_ENTRY(GET_MAX_BRIGHTNESS), 346 SDVO_CMD_NAME_ENTRY(GET_BRIGHTNESS), 347 SDVO_CMD_NAME_ENTRY(SET_BRIGHTNESS), 348 SDVO_CMD_NAME_ENTRY(GET_MAX_OVERSCAN_H), 349 SDVO_CMD_NAME_ENTRY(GET_OVERSCAN_H), 350 SDVO_CMD_NAME_ENTRY(SET_OVERSCAN_H), 351 SDVO_CMD_NAME_ENTRY(GET_MAX_OVERSCAN_V), 352 SDVO_CMD_NAME_ENTRY(GET_OVERSCAN_V), 353 SDVO_CMD_NAME_ENTRY(SET_OVERSCAN_V), 354 SDVO_CMD_NAME_ENTRY(GET_MAX_FLICKER_FILTER), 355 SDVO_CMD_NAME_ENTRY(GET_FLICKER_FILTER), 356 SDVO_CMD_NAME_ENTRY(SET_FLICKER_FILTER), 357 SDVO_CMD_NAME_ENTRY(GET_MAX_FLICKER_FILTER_ADAPTIVE), 358 SDVO_CMD_NAME_ENTRY(GET_FLICKER_FILTER_ADAPTIVE), 359 SDVO_CMD_NAME_ENTRY(SET_FLICKER_FILTER_ADAPTIVE), 360 SDVO_CMD_NAME_ENTRY(GET_MAX_FLICKER_FILTER_2D), 361 SDVO_CMD_NAME_ENTRY(GET_FLICKER_FILTER_2D), 362 SDVO_CMD_NAME_ENTRY(SET_FLICKER_FILTER_2D), 363 SDVO_CMD_NAME_ENTRY(GET_MAX_SHARPNESS), 364 SDVO_CMD_NAME_ENTRY(GET_SHARPNESS), 365 SDVO_CMD_NAME_ENTRY(SET_SHARPNESS), 366 SDVO_CMD_NAME_ENTRY(GET_DOT_CRAWL), 367 SDVO_CMD_NAME_ENTRY(SET_DOT_CRAWL), 368 SDVO_CMD_NAME_ENTRY(GET_MAX_TV_CHROMA_FILTER), 369 SDVO_CMD_NAME_ENTRY(GET_TV_CHROMA_FILTER), 370 SDVO_CMD_NAME_ENTRY(SET_TV_CHROMA_FILTER), 371 SDVO_CMD_NAME_ENTRY(GET_MAX_TV_LUMA_FILTER), 372 SDVO_CMD_NAME_ENTRY(GET_TV_LUMA_FILTER), 373 SDVO_CMD_NAME_ENTRY(SET_TV_LUMA_FILTER), 374 375 /* HDMI op code */ 376 SDVO_CMD_NAME_ENTRY(GET_SUPP_ENCODE), 377 SDVO_CMD_NAME_ENTRY(GET_ENCODE), 378 SDVO_CMD_NAME_ENTRY(SET_ENCODE), 379 SDVO_CMD_NAME_ENTRY(SET_PIXEL_REPLI), 380 SDVO_CMD_NAME_ENTRY(GET_PIXEL_REPLI), 381 SDVO_CMD_NAME_ENTRY(GET_COLORIMETRY_CAP), 382 SDVO_CMD_NAME_ENTRY(SET_COLORIMETRY), 383 SDVO_CMD_NAME_ENTRY(GET_COLORIMETRY), 384 SDVO_CMD_NAME_ENTRY(GET_AUDIO_ENCRYPT_PREFER), 385 SDVO_CMD_NAME_ENTRY(SET_AUDIO_STAT), 386 SDVO_CMD_NAME_ENTRY(GET_AUDIO_STAT), 387 SDVO_CMD_NAME_ENTRY(GET_HBUF_INDEX), 388 SDVO_CMD_NAME_ENTRY(SET_HBUF_INDEX), 389 SDVO_CMD_NAME_ENTRY(GET_HBUF_INFO), 390 SDVO_CMD_NAME_ENTRY(GET_HBUF_AV_SPLIT), 391 SDVO_CMD_NAME_ENTRY(SET_HBUF_AV_SPLIT), 392 SDVO_CMD_NAME_ENTRY(GET_HBUF_TXRATE), 393 SDVO_CMD_NAME_ENTRY(SET_HBUF_TXRATE), 394 SDVO_CMD_NAME_ENTRY(SET_HBUF_DATA), 395 SDVO_CMD_NAME_ENTRY(GET_HBUF_DATA), 396 }; 397 398 #undef SDVO_CMD_NAME_ENTRY 399 400 static const char *sdvo_cmd_name(u8 cmd) 401 { 402 int i; 403 404 for (i = 0; i < ARRAY_SIZE(sdvo_cmd_names); i++) { 405 if (cmd == sdvo_cmd_names[i].cmd) 406 return sdvo_cmd_names[i].name; 407 } 408 409 return NULL; 410 } 411 412 #define SDVO_NAME(svdo) ((svdo)->base.port == PORT_B ? "SDVOB" : "SDVOC") 413 414 static void intel_sdvo_debug_write(struct intel_sdvo *intel_sdvo, u8 cmd, 415 const void *args, int args_len) 416 { 417 struct intel_display *display = to_intel_display(&intel_sdvo->base); 418 const char *cmd_name; 419 int i, pos = 0; 420 char buffer[64]; 421 422 #define BUF_PRINT(args...) \ 423 pos += snprintf(buffer + pos, max_t(int, sizeof(buffer) - pos, 0), args) 424 425 for (i = 0; i < args_len; i++) { 426 BUF_PRINT("%02X ", ((u8 *)args)[i]); 427 } 428 for (; i < 8; i++) { 429 BUF_PRINT(" "); 430 } 431 432 cmd_name = sdvo_cmd_name(cmd); 433 if (cmd_name) 434 BUF_PRINT("(%s)", cmd_name); 435 else 436 BUF_PRINT("(%02X)", cmd); 437 438 drm_WARN_ON(display->drm, pos >= sizeof(buffer) - 1); 439 #undef BUF_PRINT 440 441 drm_dbg_kms(display->drm, "%s: W: %02X %s\n", SDVO_NAME(intel_sdvo), 442 cmd, buffer); 443 } 444 445 static const char * const cmd_status_names[] = { 446 [SDVO_CMD_STATUS_POWER_ON] = "Power on", 447 [SDVO_CMD_STATUS_SUCCESS] = "Success", 448 [SDVO_CMD_STATUS_NOTSUPP] = "Not supported", 449 [SDVO_CMD_STATUS_INVALID_ARG] = "Invalid arg", 450 [SDVO_CMD_STATUS_PENDING] = "Pending", 451 [SDVO_CMD_STATUS_TARGET_NOT_SPECIFIED] = "Target not specified", 452 [SDVO_CMD_STATUS_SCALING_NOT_SUPP] = "Scaling not supported", 453 }; 454 455 static const char *sdvo_cmd_status(u8 status) 456 { 457 if (status < ARRAY_SIZE(cmd_status_names)) 458 return cmd_status_names[status]; 459 else 460 return NULL; 461 } 462 463 static bool __intel_sdvo_write_cmd(struct intel_sdvo *intel_sdvo, u8 cmd, 464 const void *args, int args_len, 465 bool unlocked) 466 { 467 struct intel_display *display = to_intel_display(&intel_sdvo->base); 468 u8 *buf, status; 469 struct i2c_msg *msgs; 470 int i, ret = true; 471 472 /* Would be simpler to allocate both in one go ? */ 473 buf = kzalloc(args_len * 2 + 2, GFP_KERNEL); 474 if (!buf) 475 return false; 476 477 msgs = kzalloc_objs(*msgs, args_len + 3); 478 if (!msgs) { 479 kfree(buf); 480 return false; 481 } 482 483 intel_sdvo_debug_write(intel_sdvo, cmd, args, args_len); 484 485 for (i = 0; i < args_len; i++) { 486 msgs[i].addr = intel_sdvo->target_addr; 487 msgs[i].flags = 0; 488 msgs[i].len = 2; 489 msgs[i].buf = buf + 2 *i; 490 buf[2*i + 0] = SDVO_I2C_ARG_0 - i; 491 buf[2*i + 1] = ((u8*)args)[i]; 492 } 493 msgs[i].addr = intel_sdvo->target_addr; 494 msgs[i].flags = 0; 495 msgs[i].len = 2; 496 msgs[i].buf = buf + 2*i; 497 buf[2*i + 0] = SDVO_I2C_OPCODE; 498 buf[2*i + 1] = cmd; 499 500 /* the following two are to read the response */ 501 status = SDVO_I2C_CMD_STATUS; 502 msgs[i+1].addr = intel_sdvo->target_addr; 503 msgs[i+1].flags = 0; 504 msgs[i+1].len = 1; 505 msgs[i+1].buf = &status; 506 507 msgs[i+2].addr = intel_sdvo->target_addr; 508 msgs[i+2].flags = I2C_M_RD; 509 msgs[i+2].len = 1; 510 msgs[i+2].buf = &status; 511 512 if (unlocked) 513 ret = i2c_transfer(intel_sdvo->i2c, msgs, i+3); 514 else 515 ret = __i2c_transfer(intel_sdvo->i2c, msgs, i+3); 516 if (ret < 0) { 517 drm_dbg_kms(display->drm, "I2c transfer returned %d\n", ret); 518 ret = false; 519 goto out; 520 } 521 if (ret != i+3) { 522 /* failure in I2C transfer */ 523 drm_dbg_kms(display->drm, "I2c transfer returned %d/%d\n", ret, i + 3); 524 ret = false; 525 } 526 527 out: 528 kfree(msgs); 529 kfree(buf); 530 return ret; 531 } 532 533 static bool intel_sdvo_write_cmd(struct intel_sdvo *intel_sdvo, u8 cmd, 534 const void *args, int args_len) 535 { 536 return __intel_sdvo_write_cmd(intel_sdvo, cmd, args, args_len, true); 537 } 538 539 static bool intel_sdvo_read_response(struct intel_sdvo *intel_sdvo, 540 void *response, int response_len) 541 { 542 struct intel_display *display = to_intel_display(&intel_sdvo->base); 543 const char *cmd_status; 544 u8 retry = 15; /* 5 quick checks, followed by 10 long checks */ 545 u8 status; 546 int i, pos = 0; 547 char buffer[64]; 548 549 buffer[0] = '\0'; 550 551 /* 552 * The documentation states that all commands will be 553 * processed within 15µs, and that we need only poll 554 * the status byte a maximum of 3 times in order for the 555 * command to be complete. 556 * 557 * Check 5 times in case the hardware failed to read the docs. 558 * 559 * Also beware that the first response by many devices is to 560 * reply PENDING and stall for time. TVs are notorious for 561 * requiring longer than specified to complete their replies. 562 * Originally (in the DDX long ago), the delay was only ever 15ms 563 * with an additional delay of 30ms applied for TVs added later after 564 * many experiments. To accommodate both sets of delays, we do a 565 * sequence of slow checks if the device is falling behind and fails 566 * to reply within 5*15µs. 567 */ 568 if (!intel_sdvo_read_byte(intel_sdvo, 569 SDVO_I2C_CMD_STATUS, 570 &status)) 571 goto log_fail; 572 573 while ((status == SDVO_CMD_STATUS_PENDING || 574 status == SDVO_CMD_STATUS_TARGET_NOT_SPECIFIED) && --retry) { 575 if (retry < 10) 576 msleep(15); 577 else 578 udelay(15); 579 580 if (!intel_sdvo_read_byte(intel_sdvo, 581 SDVO_I2C_CMD_STATUS, 582 &status)) 583 goto log_fail; 584 } 585 586 #define BUF_PRINT(args...) \ 587 pos += snprintf(buffer + pos, max_t(int, sizeof(buffer) - pos, 0), args) 588 589 cmd_status = sdvo_cmd_status(status); 590 if (cmd_status) 591 BUF_PRINT("(%s)", cmd_status); 592 else 593 BUF_PRINT("(??? %d)", status); 594 595 if (status != SDVO_CMD_STATUS_SUCCESS) 596 goto log_fail; 597 598 /* Read the command response */ 599 for (i = 0; i < response_len; i++) { 600 if (!intel_sdvo_read_byte(intel_sdvo, 601 SDVO_I2C_RETURN_0 + i, 602 &((u8 *)response)[i])) 603 goto log_fail; 604 BUF_PRINT(" %02X", ((u8 *)response)[i]); 605 } 606 607 drm_WARN_ON(display->drm, pos >= sizeof(buffer) - 1); 608 #undef BUF_PRINT 609 610 drm_dbg_kms(display->drm, "%s: R: %s\n", 611 SDVO_NAME(intel_sdvo), buffer); 612 return true; 613 614 log_fail: 615 drm_dbg_kms(display->drm, "%s: R: ... failed %s\n", 616 SDVO_NAME(intel_sdvo), buffer); 617 return false; 618 } 619 620 static int intel_sdvo_get_pixel_multiplier(const struct drm_display_mode *adjusted_mode) 621 { 622 if (adjusted_mode->crtc_clock >= 100000) 623 return 1; 624 else if (adjusted_mode->crtc_clock >= 50000) 625 return 2; 626 else 627 return 4; 628 } 629 630 static bool __intel_sdvo_set_control_bus_switch(struct intel_sdvo *intel_sdvo, 631 u8 ddc_bus) 632 { 633 /* This must be the immediately preceding write before the i2c xfer */ 634 return __intel_sdvo_write_cmd(intel_sdvo, 635 SDVO_CMD_SET_CONTROL_BUS_SWITCH, 636 &ddc_bus, 1, false); 637 } 638 639 static bool intel_sdvo_set_value(struct intel_sdvo *intel_sdvo, u8 cmd, const void *data, int len) 640 { 641 if (!intel_sdvo_write_cmd(intel_sdvo, cmd, data, len)) 642 return false; 643 644 return intel_sdvo_read_response(intel_sdvo, NULL, 0); 645 } 646 647 static bool 648 intel_sdvo_get_value(struct intel_sdvo *intel_sdvo, u8 cmd, void *value, int len) 649 { 650 if (!intel_sdvo_write_cmd(intel_sdvo, cmd, NULL, 0)) 651 return false; 652 653 return intel_sdvo_read_response(intel_sdvo, value, len); 654 } 655 656 static bool intel_sdvo_set_target_input(struct intel_sdvo *intel_sdvo) 657 { 658 struct intel_sdvo_set_target_input_args targets = {}; 659 return intel_sdvo_set_value(intel_sdvo, 660 SDVO_CMD_SET_TARGET_INPUT, 661 &targets, sizeof(targets)); 662 } 663 664 /* 665 * Return whether each input is trained. 666 * 667 * This function is making an assumption about the layout of the response, 668 * which should be checked against the docs. 669 */ 670 static bool intel_sdvo_get_trained_inputs(struct intel_sdvo *intel_sdvo, bool *input_1, bool *input_2) 671 { 672 struct intel_sdvo_get_trained_inputs_response response; 673 674 BUILD_BUG_ON(sizeof(response) != 1); 675 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_TRAINED_INPUTS, 676 &response, sizeof(response))) 677 return false; 678 679 *input_1 = response.input0_trained; 680 *input_2 = response.input1_trained; 681 return true; 682 } 683 684 static bool intel_sdvo_set_active_outputs(struct intel_sdvo *intel_sdvo, 685 u16 outputs) 686 { 687 return intel_sdvo_set_value(intel_sdvo, 688 SDVO_CMD_SET_ACTIVE_OUTPUTS, 689 &outputs, sizeof(outputs)); 690 } 691 692 static bool intel_sdvo_get_active_outputs(struct intel_sdvo *intel_sdvo, 693 u16 *outputs) 694 { 695 return intel_sdvo_get_value(intel_sdvo, 696 SDVO_CMD_GET_ACTIVE_OUTPUTS, 697 outputs, sizeof(*outputs)); 698 } 699 700 static bool intel_sdvo_set_encoder_power_state(struct intel_sdvo *intel_sdvo, 701 int mode) 702 { 703 u8 state = SDVO_ENCODER_STATE_ON; 704 705 switch (mode) { 706 case DRM_MODE_DPMS_ON: 707 state = SDVO_ENCODER_STATE_ON; 708 break; 709 case DRM_MODE_DPMS_STANDBY: 710 state = SDVO_ENCODER_STATE_STANDBY; 711 break; 712 case DRM_MODE_DPMS_SUSPEND: 713 state = SDVO_ENCODER_STATE_SUSPEND; 714 break; 715 case DRM_MODE_DPMS_OFF: 716 state = SDVO_ENCODER_STATE_OFF; 717 break; 718 } 719 720 return intel_sdvo_set_value(intel_sdvo, 721 SDVO_CMD_SET_ENCODER_POWER_STATE, &state, sizeof(state)); 722 } 723 724 static bool intel_sdvo_get_input_pixel_clock_range(struct intel_sdvo *intel_sdvo, 725 int *clock_min, 726 int *clock_max) 727 { 728 struct intel_sdvo_pixel_clock_range clocks; 729 730 BUILD_BUG_ON(sizeof(clocks) != 4); 731 if (!intel_sdvo_get_value(intel_sdvo, 732 SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE, 733 &clocks, sizeof(clocks))) 734 return false; 735 736 /* Convert the values from units of 10 kHz to kHz. */ 737 *clock_min = clocks.min * 10; 738 *clock_max = clocks.max * 10; 739 return true; 740 } 741 742 static bool intel_sdvo_set_target_output(struct intel_sdvo *intel_sdvo, 743 u16 outputs) 744 { 745 return intel_sdvo_set_value(intel_sdvo, 746 SDVO_CMD_SET_TARGET_OUTPUT, 747 &outputs, sizeof(outputs)); 748 } 749 750 static bool intel_sdvo_set_timing(struct intel_sdvo *intel_sdvo, u8 cmd, 751 struct intel_sdvo_dtd *dtd) 752 { 753 return intel_sdvo_set_value(intel_sdvo, cmd, &dtd->part1, sizeof(dtd->part1)) && 754 intel_sdvo_set_value(intel_sdvo, cmd + 1, &dtd->part2, sizeof(dtd->part2)); 755 } 756 757 static bool intel_sdvo_get_timing(struct intel_sdvo *intel_sdvo, u8 cmd, 758 struct intel_sdvo_dtd *dtd) 759 { 760 return intel_sdvo_get_value(intel_sdvo, cmd, &dtd->part1, sizeof(dtd->part1)) && 761 intel_sdvo_get_value(intel_sdvo, cmd + 1, &dtd->part2, sizeof(dtd->part2)); 762 } 763 764 static bool intel_sdvo_set_input_timing(struct intel_sdvo *intel_sdvo, 765 struct intel_sdvo_dtd *dtd) 766 { 767 return intel_sdvo_set_timing(intel_sdvo, 768 SDVO_CMD_SET_INPUT_TIMINGS_PART1, dtd); 769 } 770 771 static bool intel_sdvo_set_output_timing(struct intel_sdvo *intel_sdvo, 772 struct intel_sdvo_dtd *dtd) 773 { 774 return intel_sdvo_set_timing(intel_sdvo, 775 SDVO_CMD_SET_OUTPUT_TIMINGS_PART1, dtd); 776 } 777 778 static bool intel_sdvo_get_input_timing(struct intel_sdvo *intel_sdvo, 779 struct intel_sdvo_dtd *dtd) 780 { 781 return intel_sdvo_get_timing(intel_sdvo, 782 SDVO_CMD_GET_INPUT_TIMINGS_PART1, dtd); 783 } 784 785 static bool 786 intel_sdvo_create_preferred_input_timing(struct intel_sdvo *intel_sdvo, 787 struct intel_sdvo_connector *intel_sdvo_connector, 788 const struct drm_display_mode *mode) 789 { 790 struct intel_sdvo_preferred_input_timing_args args; 791 792 memset(&args, 0, sizeof(args)); 793 args.clock = mode->clock / 10; 794 args.width = mode->hdisplay; 795 args.height = mode->vdisplay; 796 args.interlace = 0; 797 798 if (IS_LVDS(intel_sdvo_connector)) { 799 const struct drm_display_mode *fixed_mode = 800 intel_panel_fixed_mode(&intel_sdvo_connector->base, mode); 801 802 if (fixed_mode->hdisplay != args.width || 803 fixed_mode->vdisplay != args.height) 804 args.scaled = 1; 805 } 806 807 return intel_sdvo_set_value(intel_sdvo, 808 SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING, 809 &args, sizeof(args)); 810 } 811 812 static bool intel_sdvo_get_preferred_input_timing(struct intel_sdvo *intel_sdvo, 813 struct intel_sdvo_dtd *dtd) 814 { 815 BUILD_BUG_ON(sizeof(dtd->part1) != 8); 816 BUILD_BUG_ON(sizeof(dtd->part2) != 8); 817 return intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1, 818 &dtd->part1, sizeof(dtd->part1)) && 819 intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2, 820 &dtd->part2, sizeof(dtd->part2)); 821 } 822 823 static bool intel_sdvo_set_clock_rate_mult(struct intel_sdvo *intel_sdvo, u8 val) 824 { 825 return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_CLOCK_RATE_MULT, &val, 1); 826 } 827 828 static void intel_sdvo_get_dtd_from_mode(struct intel_sdvo_dtd *dtd, 829 const struct drm_display_mode *mode) 830 { 831 u16 width, height; 832 u16 h_blank_len, h_sync_len, v_blank_len, v_sync_len; 833 u16 h_sync_offset, v_sync_offset; 834 int mode_clock; 835 836 memset(dtd, 0, sizeof(*dtd)); 837 838 width = mode->hdisplay; 839 height = mode->vdisplay; 840 841 /* do some mode translations */ 842 h_blank_len = mode->htotal - mode->hdisplay; 843 h_sync_len = mode->hsync_end - mode->hsync_start; 844 845 v_blank_len = mode->vtotal - mode->vdisplay; 846 v_sync_len = mode->vsync_end - mode->vsync_start; 847 848 h_sync_offset = mode->hsync_start - mode->hdisplay; 849 v_sync_offset = mode->vsync_start - mode->vdisplay; 850 851 mode_clock = mode->clock; 852 mode_clock /= 10; 853 dtd->part1.clock = mode_clock; 854 855 dtd->part1.h_active = width & 0xff; 856 dtd->part1.h_blank = h_blank_len & 0xff; 857 dtd->part1.h_high = (((width >> 8) & 0xf) << 4) | 858 ((h_blank_len >> 8) & 0xf); 859 dtd->part1.v_active = height & 0xff; 860 dtd->part1.v_blank = v_blank_len & 0xff; 861 dtd->part1.v_high = (((height >> 8) & 0xf) << 4) | 862 ((v_blank_len >> 8) & 0xf); 863 864 dtd->part2.h_sync_off = h_sync_offset & 0xff; 865 dtd->part2.h_sync_width = h_sync_len & 0xff; 866 dtd->part2.v_sync_off_width = (v_sync_offset & 0xf) << 4 | 867 (v_sync_len & 0xf); 868 dtd->part2.sync_off_width_high = ((h_sync_offset & 0x300) >> 2) | 869 ((h_sync_len & 0x300) >> 4) | ((v_sync_offset & 0x30) >> 2) | 870 ((v_sync_len & 0x30) >> 4); 871 872 dtd->part2.dtd_flags = 0x18; 873 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 874 dtd->part2.dtd_flags |= DTD_FLAG_INTERLACE; 875 if (mode->flags & DRM_MODE_FLAG_PHSYNC) 876 dtd->part2.dtd_flags |= DTD_FLAG_HSYNC_POSITIVE; 877 if (mode->flags & DRM_MODE_FLAG_PVSYNC) 878 dtd->part2.dtd_flags |= DTD_FLAG_VSYNC_POSITIVE; 879 880 dtd->part2.v_sync_off_high = v_sync_offset & 0xc0; 881 } 882 883 static void intel_sdvo_get_mode_from_dtd(struct drm_display_mode *pmode, 884 const struct intel_sdvo_dtd *dtd) 885 { 886 struct drm_display_mode mode = {}; 887 888 mode.hdisplay = dtd->part1.h_active; 889 mode.hdisplay += ((dtd->part1.h_high >> 4) & 0x0f) << 8; 890 mode.hsync_start = mode.hdisplay + dtd->part2.h_sync_off; 891 mode.hsync_start += (dtd->part2.sync_off_width_high & 0xc0) << 2; 892 mode.hsync_end = mode.hsync_start + dtd->part2.h_sync_width; 893 mode.hsync_end += (dtd->part2.sync_off_width_high & 0x30) << 4; 894 mode.htotal = mode.hdisplay + dtd->part1.h_blank; 895 mode.htotal += (dtd->part1.h_high & 0xf) << 8; 896 897 mode.vdisplay = dtd->part1.v_active; 898 mode.vdisplay += ((dtd->part1.v_high >> 4) & 0x0f) << 8; 899 mode.vsync_start = mode.vdisplay; 900 mode.vsync_start += (dtd->part2.v_sync_off_width >> 4) & 0xf; 901 mode.vsync_start += (dtd->part2.sync_off_width_high & 0x0c) << 2; 902 mode.vsync_start += dtd->part2.v_sync_off_high & 0xc0; 903 mode.vsync_end = mode.vsync_start + 904 (dtd->part2.v_sync_off_width & 0xf); 905 mode.vsync_end += (dtd->part2.sync_off_width_high & 0x3) << 4; 906 mode.vtotal = mode.vdisplay + dtd->part1.v_blank; 907 mode.vtotal += (dtd->part1.v_high & 0xf) << 8; 908 909 mode.clock = dtd->part1.clock * 10; 910 911 if (dtd->part2.dtd_flags & DTD_FLAG_INTERLACE) 912 mode.flags |= DRM_MODE_FLAG_INTERLACE; 913 if (dtd->part2.dtd_flags & DTD_FLAG_HSYNC_POSITIVE) 914 mode.flags |= DRM_MODE_FLAG_PHSYNC; 915 else 916 mode.flags |= DRM_MODE_FLAG_NHSYNC; 917 if (dtd->part2.dtd_flags & DTD_FLAG_VSYNC_POSITIVE) 918 mode.flags |= DRM_MODE_FLAG_PVSYNC; 919 else 920 mode.flags |= DRM_MODE_FLAG_NVSYNC; 921 922 drm_mode_set_crtcinfo(&mode, 0); 923 924 drm_mode_copy(pmode, &mode); 925 } 926 927 static bool intel_sdvo_check_supp_encode(struct intel_sdvo *intel_sdvo) 928 { 929 struct intel_sdvo_encode encode; 930 931 BUILD_BUG_ON(sizeof(encode) != 2); 932 return intel_sdvo_get_value(intel_sdvo, 933 SDVO_CMD_GET_SUPP_ENCODE, 934 &encode, sizeof(encode)); 935 } 936 937 static bool intel_sdvo_set_encode(struct intel_sdvo *intel_sdvo, 938 u8 mode) 939 { 940 return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_ENCODE, &mode, 1); 941 } 942 943 static bool intel_sdvo_set_colorimetry(struct intel_sdvo *intel_sdvo, 944 u8 mode) 945 { 946 return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_COLORIMETRY, &mode, 1); 947 } 948 949 static bool intel_sdvo_set_pixel_replication(struct intel_sdvo *intel_sdvo, 950 u8 pixel_repeat) 951 { 952 return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_PIXEL_REPLI, 953 &pixel_repeat, 1); 954 } 955 956 static bool intel_sdvo_set_audio_state(struct intel_sdvo *intel_sdvo, 957 u8 audio_state) 958 { 959 return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_AUDIO_STAT, 960 &audio_state, 1); 961 } 962 963 static bool intel_sdvo_get_hbuf_size(struct intel_sdvo *intel_sdvo, 964 u8 *hbuf_size) 965 { 966 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_HBUF_INFO, 967 hbuf_size, 1)) 968 return false; 969 970 /* Buffer size is 0 based, hooray! However zero means zero. */ 971 if (*hbuf_size) 972 (*hbuf_size)++; 973 974 return true; 975 } 976 977 #if 0 978 static void intel_sdvo_dump_hdmi_buf(struct intel_sdvo *intel_sdvo) 979 { 980 int i, j; 981 u8 set_buf_index[2]; 982 u8 av_split; 983 u8 buf_size; 984 u8 buf[48]; 985 u8 *pos; 986 987 intel_sdvo_get_value(encoder, SDVO_CMD_GET_HBUF_AV_SPLIT, &av_split, 1); 988 989 for (i = 0; i <= av_split; i++) { 990 set_buf_index[0] = i; set_buf_index[1] = 0; 991 intel_sdvo_write_cmd(encoder, SDVO_CMD_SET_HBUF_INDEX, 992 set_buf_index, 2); 993 intel_sdvo_write_cmd(encoder, SDVO_CMD_GET_HBUF_INFO, NULL, 0); 994 intel_sdvo_read_response(encoder, &buf_size, 1); 995 996 pos = buf; 997 for (j = 0; j <= buf_size; j += 8) { 998 intel_sdvo_write_cmd(encoder, SDVO_CMD_GET_HBUF_DATA, 999 NULL, 0); 1000 intel_sdvo_read_response(encoder, pos, 8); 1001 pos += 8; 1002 } 1003 } 1004 } 1005 #endif 1006 1007 static bool intel_sdvo_write_infoframe(struct intel_sdvo *intel_sdvo, 1008 unsigned int if_index, u8 tx_rate, 1009 const u8 *data, unsigned int length) 1010 { 1011 struct intel_display *display = to_intel_display(&intel_sdvo->base); 1012 u8 set_buf_index[2] = { if_index, 0 }; 1013 u8 hbuf_size, tmp[8]; 1014 int i; 1015 1016 if (!intel_sdvo_set_value(intel_sdvo, 1017 SDVO_CMD_SET_HBUF_INDEX, 1018 set_buf_index, 2)) 1019 return false; 1020 1021 if (!intel_sdvo_get_hbuf_size(intel_sdvo, &hbuf_size)) 1022 return false; 1023 1024 drm_dbg_kms(display->drm, 1025 "writing sdvo hbuf: %i, length %u, hbuf_size: %i\n", 1026 if_index, length, hbuf_size); 1027 1028 if (hbuf_size < length) 1029 return false; 1030 1031 for (i = 0; i < hbuf_size; i += 8) { 1032 memset(tmp, 0, 8); 1033 if (i < length) 1034 memcpy(tmp, data + i, min_t(unsigned, 8, length - i)); 1035 1036 if (!intel_sdvo_set_value(intel_sdvo, 1037 SDVO_CMD_SET_HBUF_DATA, 1038 tmp, 8)) 1039 return false; 1040 } 1041 1042 return intel_sdvo_set_value(intel_sdvo, 1043 SDVO_CMD_SET_HBUF_TXRATE, 1044 &tx_rate, 1); 1045 } 1046 1047 static ssize_t intel_sdvo_read_infoframe(struct intel_sdvo *intel_sdvo, 1048 unsigned int if_index, 1049 u8 *data, unsigned int length) 1050 { 1051 struct intel_display *display = to_intel_display(&intel_sdvo->base); 1052 u8 set_buf_index[2] = { if_index, 0 }; 1053 u8 hbuf_size, tx_rate, av_split; 1054 int i; 1055 1056 if (!intel_sdvo_get_value(intel_sdvo, 1057 SDVO_CMD_GET_HBUF_AV_SPLIT, 1058 &av_split, 1)) 1059 return -ENXIO; 1060 1061 if (av_split < if_index) 1062 return 0; 1063 1064 if (!intel_sdvo_set_value(intel_sdvo, 1065 SDVO_CMD_SET_HBUF_INDEX, 1066 set_buf_index, 2)) 1067 return -ENXIO; 1068 1069 if (!intel_sdvo_get_value(intel_sdvo, 1070 SDVO_CMD_GET_HBUF_TXRATE, 1071 &tx_rate, 1)) 1072 return -ENXIO; 1073 1074 /* TX_DISABLED doesn't mean disabled for ELD */ 1075 if (if_index != SDVO_HBUF_INDEX_ELD && tx_rate == SDVO_HBUF_TX_DISABLED) 1076 return 0; 1077 1078 if (!intel_sdvo_get_hbuf_size(intel_sdvo, &hbuf_size)) 1079 return false; 1080 1081 drm_dbg_kms(display->drm, 1082 "reading sdvo hbuf: %i, length %u, hbuf_size: %i\n", 1083 if_index, length, hbuf_size); 1084 1085 hbuf_size = min_t(unsigned int, length, hbuf_size); 1086 1087 for (i = 0; i < hbuf_size; i += 8) { 1088 if (!intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_GET_HBUF_DATA, NULL, 0)) 1089 return -ENXIO; 1090 if (!intel_sdvo_read_response(intel_sdvo, &data[i], 1091 min_t(unsigned int, 8, hbuf_size - i))) 1092 return -ENXIO; 1093 } 1094 1095 return hbuf_size; 1096 } 1097 1098 static bool intel_sdvo_compute_avi_infoframe(struct intel_sdvo *intel_sdvo, 1099 struct intel_crtc_state *crtc_state, 1100 struct drm_connector_state *conn_state) 1101 { 1102 struct intel_display *display = to_intel_display(&intel_sdvo->base); 1103 struct hdmi_avi_infoframe *frame = &crtc_state->infoframes.avi.avi; 1104 const struct drm_display_mode *adjusted_mode = 1105 &crtc_state->hw.adjusted_mode; 1106 int ret; 1107 1108 if (!crtc_state->has_hdmi_sink) 1109 return true; 1110 1111 crtc_state->infoframes.enable |= 1112 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_AVI); 1113 1114 ret = drm_hdmi_avi_infoframe_from_display_mode(frame, 1115 conn_state->connector, 1116 adjusted_mode); 1117 if (ret) 1118 return false; 1119 1120 drm_hdmi_avi_infoframe_quant_range(frame, 1121 conn_state->connector, 1122 adjusted_mode, 1123 crtc_state->limited_color_range ? 1124 HDMI_QUANTIZATION_RANGE_LIMITED : 1125 HDMI_QUANTIZATION_RANGE_FULL); 1126 1127 ret = hdmi_avi_infoframe_check(frame); 1128 if (drm_WARN_ON(display->drm, ret)) 1129 return false; 1130 1131 return true; 1132 } 1133 1134 static bool intel_sdvo_set_avi_infoframe(struct intel_sdvo *intel_sdvo, 1135 const struct intel_crtc_state *crtc_state) 1136 { 1137 struct intel_display *display = to_intel_display(&intel_sdvo->base); 1138 u8 sdvo_data[HDMI_INFOFRAME_SIZE(AVI)]; 1139 const union hdmi_infoframe *frame = &crtc_state->infoframes.avi; 1140 ssize_t len; 1141 1142 if ((crtc_state->infoframes.enable & 1143 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_AVI)) == 0) 1144 return true; 1145 1146 if (drm_WARN_ON(display->drm, 1147 frame->any.type != HDMI_INFOFRAME_TYPE_AVI)) 1148 return false; 1149 1150 len = hdmi_infoframe_pack_only(frame, sdvo_data, sizeof(sdvo_data)); 1151 if (drm_WARN_ON(display->drm, len < 0)) 1152 return false; 1153 1154 return intel_sdvo_write_infoframe(intel_sdvo, SDVO_HBUF_INDEX_AVI_IF, 1155 SDVO_HBUF_TX_VSYNC, 1156 sdvo_data, len); 1157 } 1158 1159 static void intel_sdvo_get_avi_infoframe(struct intel_sdvo *intel_sdvo, 1160 struct intel_crtc_state *crtc_state) 1161 { 1162 struct intel_display *display = to_intel_display(&intel_sdvo->base); 1163 u8 sdvo_data[HDMI_INFOFRAME_SIZE(AVI)]; 1164 union hdmi_infoframe *frame = &crtc_state->infoframes.avi; 1165 ssize_t len; 1166 int ret; 1167 1168 if (!crtc_state->has_hdmi_sink) 1169 return; 1170 1171 len = intel_sdvo_read_infoframe(intel_sdvo, SDVO_HBUF_INDEX_AVI_IF, 1172 sdvo_data, sizeof(sdvo_data)); 1173 if (len < 0) { 1174 drm_dbg_kms(display->drm, "failed to read AVI infoframe\n"); 1175 return; 1176 } else if (len == 0) { 1177 return; 1178 } 1179 1180 crtc_state->infoframes.enable |= 1181 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_AVI); 1182 1183 ret = hdmi_infoframe_unpack(frame, sdvo_data, len); 1184 if (ret) { 1185 drm_dbg_kms(display->drm, "Failed to unpack AVI infoframe\n"); 1186 return; 1187 } 1188 1189 if (frame->any.type != HDMI_INFOFRAME_TYPE_AVI) 1190 drm_dbg_kms(display->drm, 1191 "Found the wrong infoframe type 0x%x (expected 0x%02x)\n", 1192 frame->any.type, HDMI_INFOFRAME_TYPE_AVI); 1193 } 1194 1195 static void intel_sdvo_get_eld(struct intel_sdvo *intel_sdvo, 1196 struct intel_crtc_state *crtc_state) 1197 { 1198 struct intel_display *display = to_intel_display(&intel_sdvo->base); 1199 ssize_t len; 1200 u8 val; 1201 1202 if (!crtc_state->has_audio) 1203 return; 1204 1205 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_AUDIO_STAT, &val, 1)) 1206 return; 1207 1208 if ((val & SDVO_AUDIO_ELD_VALID) == 0) 1209 return; 1210 1211 len = intel_sdvo_read_infoframe(intel_sdvo, SDVO_HBUF_INDEX_ELD, 1212 crtc_state->eld, sizeof(crtc_state->eld)); 1213 if (len < 0) 1214 drm_dbg_kms(display->drm, "failed to read ELD\n"); 1215 } 1216 1217 static bool intel_sdvo_set_tv_format(struct intel_sdvo *intel_sdvo, 1218 const struct drm_connector_state *conn_state) 1219 { 1220 struct intel_sdvo_tv_format format; 1221 u32 format_map; 1222 1223 format_map = 1 << conn_state->tv.legacy_mode; 1224 memset(&format, 0, sizeof(format)); 1225 memcpy(&format, &format_map, min(sizeof(format), sizeof(format_map))); 1226 1227 BUILD_BUG_ON(sizeof(format) != 6); 1228 return intel_sdvo_set_value(intel_sdvo, 1229 SDVO_CMD_SET_TV_FORMAT, 1230 &format, sizeof(format)); 1231 } 1232 1233 static bool 1234 intel_sdvo_set_output_timings_from_mode(struct intel_sdvo *intel_sdvo, 1235 struct intel_sdvo_connector *intel_sdvo_connector, 1236 const struct drm_display_mode *mode) 1237 { 1238 struct intel_sdvo_dtd output_dtd; 1239 1240 if (!intel_sdvo_set_target_output(intel_sdvo, 1241 intel_sdvo_connector->output_flag)) 1242 return false; 1243 1244 intel_sdvo_get_dtd_from_mode(&output_dtd, mode); 1245 if (!intel_sdvo_set_output_timing(intel_sdvo, &output_dtd)) 1246 return false; 1247 1248 return true; 1249 } 1250 1251 /* 1252 * Asks the sdvo controller for the preferred input mode given the output mode. 1253 * Unfortunately we have to set up the full output mode to do that. 1254 */ 1255 static bool 1256 intel_sdvo_get_preferred_input_mode(struct intel_sdvo *intel_sdvo, 1257 struct intel_sdvo_connector *intel_sdvo_connector, 1258 const struct drm_display_mode *mode, 1259 struct drm_display_mode *adjusted_mode) 1260 { 1261 struct intel_sdvo_dtd input_dtd; 1262 1263 /* Reset the input timing to the screen. Assume always input 0. */ 1264 if (!intel_sdvo_set_target_input(intel_sdvo)) 1265 return false; 1266 1267 if (!intel_sdvo_create_preferred_input_timing(intel_sdvo, 1268 intel_sdvo_connector, 1269 mode)) 1270 return false; 1271 1272 if (!intel_sdvo_get_preferred_input_timing(intel_sdvo, 1273 &input_dtd)) 1274 return false; 1275 1276 intel_sdvo_get_mode_from_dtd(adjusted_mode, &input_dtd); 1277 intel_sdvo->dtd_sdvo_flags = input_dtd.part2.sdvo_flags; 1278 1279 return true; 1280 } 1281 1282 static int i9xx_adjust_sdvo_tv_clock(struct intel_crtc_state *pipe_config) 1283 { 1284 struct intel_display *display = to_intel_display(pipe_config); 1285 unsigned int dotclock = pipe_config->hw.adjusted_mode.crtc_clock; 1286 struct dpll *clock = &pipe_config->dpll; 1287 1288 /* 1289 * SDVO TV has fixed PLL values depend on its clock range, 1290 * this mirrors vbios setting. 1291 */ 1292 if (dotclock >= 100000 && dotclock < 140500) { 1293 clock->p1 = 2; 1294 clock->p2 = 10; 1295 clock->n = 3; 1296 clock->m1 = 16; 1297 clock->m2 = 8; 1298 } else if (dotclock >= 140500 && dotclock <= 200000) { 1299 clock->p1 = 1; 1300 clock->p2 = 10; 1301 clock->n = 6; 1302 clock->m1 = 12; 1303 clock->m2 = 8; 1304 } else { 1305 drm_dbg_kms(display->drm, 1306 "SDVO TV clock out of range: %i\n", dotclock); 1307 return -EINVAL; 1308 } 1309 1310 pipe_config->clock_set = true; 1311 1312 return 0; 1313 } 1314 1315 static bool intel_has_hdmi_sink(struct intel_sdvo_connector *intel_sdvo_connector, 1316 const struct drm_connector_state *conn_state) 1317 { 1318 struct drm_connector *connector = conn_state->connector; 1319 1320 return intel_sdvo_connector->is_hdmi && 1321 connector->display_info.is_hdmi && 1322 READ_ONCE(to_intel_digital_connector_state(conn_state)->force_audio) != HDMI_AUDIO_OFF_DVI; 1323 } 1324 1325 static bool intel_sdvo_limited_color_range(struct intel_encoder *encoder, 1326 const struct intel_crtc_state *crtc_state, 1327 const struct drm_connector_state *conn_state) 1328 { 1329 struct intel_sdvo *intel_sdvo = to_sdvo(encoder); 1330 1331 if ((intel_sdvo->colorimetry_cap & SDVO_COLORIMETRY_RGB220) == 0) 1332 return false; 1333 1334 return intel_hdmi_limited_color_range(crtc_state, conn_state); 1335 } 1336 1337 static bool intel_sdvo_has_audio(struct intel_encoder *encoder, 1338 const struct intel_crtc_state *crtc_state, 1339 const struct drm_connector_state *conn_state) 1340 { 1341 struct drm_connector *connector = conn_state->connector; 1342 struct intel_sdvo_connector *intel_sdvo_connector = 1343 to_intel_sdvo_connector(connector); 1344 const struct intel_digital_connector_state *intel_conn_state = 1345 to_intel_digital_connector_state(conn_state); 1346 1347 if (!crtc_state->has_hdmi_sink) 1348 return false; 1349 1350 if (intel_conn_state->force_audio == HDMI_AUDIO_AUTO) 1351 return intel_sdvo_connector->is_hdmi && 1352 connector->display_info.has_audio; 1353 else 1354 return intel_conn_state->force_audio == HDMI_AUDIO_ON; 1355 } 1356 1357 static int intel_sdvo_compute_config(struct intel_encoder *encoder, 1358 struct intel_crtc_state *pipe_config, 1359 struct drm_connector_state *conn_state) 1360 { 1361 struct intel_display *display = to_intel_display(encoder); 1362 struct intel_sdvo *intel_sdvo = to_sdvo(encoder); 1363 struct intel_sdvo_connector *intel_sdvo_connector = 1364 to_intel_sdvo_connector(conn_state->connector); 1365 struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode; 1366 struct drm_display_mode *mode = &pipe_config->hw.mode; 1367 1368 if (HAS_PCH_SPLIT(display)) { 1369 pipe_config->has_pch_encoder = true; 1370 if (!intel_link_bw_compute_pipe_bpp(pipe_config)) 1371 return -EINVAL; 1372 } 1373 1374 drm_dbg_kms(display->drm, "forcing bpc to 8 for SDVO\n"); 1375 /* FIXME: Don't increase pipe_bpp */ 1376 pipe_config->pipe_bpp = 8*3; 1377 pipe_config->sink_format = INTEL_OUTPUT_FORMAT_RGB; 1378 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; 1379 1380 /* 1381 * We need to construct preferred input timings based on our 1382 * output timings. To do that, we have to set the output 1383 * timings, even though this isn't really the right place in 1384 * the sequence to do it. Oh well. 1385 */ 1386 if (IS_TV(intel_sdvo_connector)) { 1387 if (!intel_sdvo_set_output_timings_from_mode(intel_sdvo, 1388 intel_sdvo_connector, 1389 mode)) 1390 return -EINVAL; 1391 1392 (void) intel_sdvo_get_preferred_input_mode(intel_sdvo, 1393 intel_sdvo_connector, 1394 mode, 1395 adjusted_mode); 1396 pipe_config->sdvo_tv_clock = true; 1397 } else if (IS_LVDS(intel_sdvo_connector)) { 1398 const struct drm_display_mode *fixed_mode; 1399 int ret; 1400 1401 ret = intel_panel_compute_config(&intel_sdvo_connector->base, 1402 adjusted_mode); 1403 if (ret) 1404 return ret; 1405 1406 fixed_mode = &pipe_config->hw.adjusted_mode; 1407 1408 if (!intel_sdvo_set_output_timings_from_mode(intel_sdvo, 1409 intel_sdvo_connector, 1410 fixed_mode)) 1411 return -EINVAL; 1412 1413 (void) intel_sdvo_get_preferred_input_mode(intel_sdvo, 1414 intel_sdvo_connector, 1415 mode, 1416 adjusted_mode); 1417 } 1418 1419 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN) 1420 return -EINVAL; 1421 1422 /* 1423 * Make the CRTC code factor in the SDVO pixel multiplier. The 1424 * SDVO device will factor out the multiplier during mode_set. 1425 */ 1426 pipe_config->pixel_multiplier = 1427 intel_sdvo_get_pixel_multiplier(adjusted_mode); 1428 1429 pipe_config->has_hdmi_sink = intel_has_hdmi_sink(intel_sdvo_connector, conn_state); 1430 1431 pipe_config->has_audio = 1432 intel_sdvo_has_audio(encoder, pipe_config, conn_state) && 1433 intel_audio_compute_config(encoder, pipe_config, conn_state); 1434 1435 pipe_config->limited_color_range = 1436 intel_sdvo_limited_color_range(encoder, pipe_config, 1437 conn_state); 1438 1439 /* Clock computation needs to happen after pixel multiplier. */ 1440 if (IS_TV(intel_sdvo_connector)) { 1441 int ret; 1442 1443 ret = i9xx_adjust_sdvo_tv_clock(pipe_config); 1444 if (ret) 1445 return ret; 1446 } 1447 1448 if (conn_state->picture_aspect_ratio) 1449 adjusted_mode->picture_aspect_ratio = 1450 conn_state->picture_aspect_ratio; 1451 1452 if (!intel_sdvo_compute_avi_infoframe(intel_sdvo, 1453 pipe_config, conn_state)) { 1454 drm_dbg_kms(display->drm, "bad AVI infoframe\n"); 1455 return -EINVAL; 1456 } 1457 1458 return 0; 1459 } 1460 1461 #define UPDATE_PROPERTY(input, NAME) \ 1462 do { \ 1463 val = input; \ 1464 intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_##NAME, &val, sizeof(val)); \ 1465 } while (0) 1466 1467 static void intel_sdvo_update_props(struct intel_sdvo *intel_sdvo, 1468 const struct intel_sdvo_connector_state *sdvo_state) 1469 { 1470 const struct drm_connector_state *conn_state = &sdvo_state->base.base; 1471 struct intel_sdvo_connector *intel_sdvo_conn = 1472 to_intel_sdvo_connector(conn_state->connector); 1473 u16 val; 1474 1475 if (intel_sdvo_conn->left) 1476 UPDATE_PROPERTY(sdvo_state->tv.overscan_h, OVERSCAN_H); 1477 1478 if (intel_sdvo_conn->top) 1479 UPDATE_PROPERTY(sdvo_state->tv.overscan_v, OVERSCAN_V); 1480 1481 if (intel_sdvo_conn->hpos) 1482 UPDATE_PROPERTY(sdvo_state->tv.hpos, HPOS); 1483 1484 if (intel_sdvo_conn->vpos) 1485 UPDATE_PROPERTY(sdvo_state->tv.vpos, VPOS); 1486 1487 if (intel_sdvo_conn->saturation) 1488 UPDATE_PROPERTY(conn_state->tv.saturation, SATURATION); 1489 1490 if (intel_sdvo_conn->contrast) 1491 UPDATE_PROPERTY(conn_state->tv.contrast, CONTRAST); 1492 1493 if (intel_sdvo_conn->hue) 1494 UPDATE_PROPERTY(conn_state->tv.hue, HUE); 1495 1496 if (intel_sdvo_conn->brightness) 1497 UPDATE_PROPERTY(conn_state->tv.brightness, BRIGHTNESS); 1498 1499 if (intel_sdvo_conn->sharpness) 1500 UPDATE_PROPERTY(sdvo_state->tv.sharpness, SHARPNESS); 1501 1502 if (intel_sdvo_conn->flicker_filter) 1503 UPDATE_PROPERTY(sdvo_state->tv.flicker_filter, FLICKER_FILTER); 1504 1505 if (intel_sdvo_conn->flicker_filter_2d) 1506 UPDATE_PROPERTY(sdvo_state->tv.flicker_filter_2d, FLICKER_FILTER_2D); 1507 1508 if (intel_sdvo_conn->flicker_filter_adaptive) 1509 UPDATE_PROPERTY(sdvo_state->tv.flicker_filter_adaptive, FLICKER_FILTER_ADAPTIVE); 1510 1511 if (intel_sdvo_conn->tv_chroma_filter) 1512 UPDATE_PROPERTY(sdvo_state->tv.chroma_filter, TV_CHROMA_FILTER); 1513 1514 if (intel_sdvo_conn->tv_luma_filter) 1515 UPDATE_PROPERTY(sdvo_state->tv.luma_filter, TV_LUMA_FILTER); 1516 1517 if (intel_sdvo_conn->dot_crawl) 1518 UPDATE_PROPERTY(sdvo_state->tv.dot_crawl, DOT_CRAWL); 1519 1520 #undef UPDATE_PROPERTY 1521 } 1522 1523 static void intel_sdvo_pre_enable(struct intel_atomic_state *state, 1524 struct intel_encoder *intel_encoder, 1525 const struct intel_crtc_state *crtc_state, 1526 const struct drm_connector_state *conn_state) 1527 { 1528 struct intel_display *display = to_intel_display(intel_encoder); 1529 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1530 const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; 1531 const struct intel_sdvo_connector_state *sdvo_state = 1532 to_intel_sdvo_connector_state(conn_state); 1533 struct intel_sdvo_connector *intel_sdvo_connector = 1534 to_intel_sdvo_connector(conn_state->connector); 1535 const struct drm_display_mode *mode = &crtc_state->hw.mode; 1536 struct intel_sdvo *intel_sdvo = to_sdvo(intel_encoder); 1537 u32 sdvox; 1538 struct intel_sdvo_in_out_map in_out; 1539 struct intel_sdvo_dtd input_dtd, output_dtd; 1540 int rate; 1541 1542 intel_sdvo_update_props(intel_sdvo, sdvo_state); 1543 1544 /* 1545 * First, set the input mapping for the first input to our controlled 1546 * output. This is only correct if we're a single-input device, in 1547 * which case the first input is the output from the appropriate SDVO 1548 * channel on the motherboard. In a two-input device, the first input 1549 * will be SDVOB and the second SDVOC. 1550 */ 1551 in_out.in0 = intel_sdvo_connector->output_flag; 1552 in_out.in1 = 0; 1553 1554 intel_sdvo_set_value(intel_sdvo, 1555 SDVO_CMD_SET_IN_OUT_MAP, 1556 &in_out, sizeof(in_out)); 1557 1558 /* Set the output timings to the screen */ 1559 if (!intel_sdvo_set_target_output(intel_sdvo, 1560 intel_sdvo_connector->output_flag)) 1561 return; 1562 1563 /* lvds has a special fixed output timing. */ 1564 if (IS_LVDS(intel_sdvo_connector)) { 1565 const struct drm_display_mode *fixed_mode = 1566 intel_panel_fixed_mode(&intel_sdvo_connector->base, mode); 1567 1568 intel_sdvo_get_dtd_from_mode(&output_dtd, fixed_mode); 1569 } else { 1570 intel_sdvo_get_dtd_from_mode(&output_dtd, mode); 1571 } 1572 if (!intel_sdvo_set_output_timing(intel_sdvo, &output_dtd)) 1573 drm_info(display->drm, 1574 "Setting output timings on %s failed\n", 1575 SDVO_NAME(intel_sdvo)); 1576 1577 /* Set the input timing to the screen. Assume always input 0. */ 1578 if (!intel_sdvo_set_target_input(intel_sdvo)) 1579 return; 1580 1581 if (crtc_state->has_hdmi_sink) { 1582 intel_sdvo_set_encode(intel_sdvo, SDVO_ENCODE_HDMI); 1583 intel_sdvo_set_colorimetry(intel_sdvo, 1584 crtc_state->limited_color_range ? 1585 SDVO_COLORIMETRY_RGB220 : 1586 SDVO_COLORIMETRY_RGB256); 1587 intel_sdvo_set_avi_infoframe(intel_sdvo, crtc_state); 1588 intel_sdvo_set_pixel_replication(intel_sdvo, 1589 !!(adjusted_mode->flags & 1590 DRM_MODE_FLAG_DBLCLK)); 1591 } else 1592 intel_sdvo_set_encode(intel_sdvo, SDVO_ENCODE_DVI); 1593 1594 if (IS_TV(intel_sdvo_connector) && 1595 !intel_sdvo_set_tv_format(intel_sdvo, conn_state)) 1596 return; 1597 1598 intel_sdvo_get_dtd_from_mode(&input_dtd, adjusted_mode); 1599 1600 if (IS_TV(intel_sdvo_connector) || IS_LVDS(intel_sdvo_connector)) 1601 input_dtd.part2.sdvo_flags = intel_sdvo->dtd_sdvo_flags; 1602 if (!intel_sdvo_set_input_timing(intel_sdvo, &input_dtd)) 1603 drm_info(display->drm, 1604 "Setting input timings on %s failed\n", 1605 SDVO_NAME(intel_sdvo)); 1606 1607 switch (crtc_state->pixel_multiplier) { 1608 default: 1609 drm_WARN(display->drm, 1, 1610 "unknown pixel multiplier specified\n"); 1611 fallthrough; 1612 case 1: rate = SDVO_CLOCK_RATE_MULT_1X; break; 1613 case 2: rate = SDVO_CLOCK_RATE_MULT_2X; break; 1614 case 4: rate = SDVO_CLOCK_RATE_MULT_4X; break; 1615 } 1616 if (!intel_sdvo_set_clock_rate_mult(intel_sdvo, rate)) 1617 return; 1618 1619 /* Set the SDVO control regs. */ 1620 if (DISPLAY_VER(display) >= 4) { 1621 /* The real mode polarity is set by the SDVO commands, using 1622 * struct intel_sdvo_dtd. */ 1623 sdvox = SDVO_VSYNC_ACTIVE_HIGH | SDVO_HSYNC_ACTIVE_HIGH; 1624 if (DISPLAY_VER(display) < 5) 1625 sdvox |= SDVO_BORDER_ENABLE; 1626 } else { 1627 sdvox = intel_de_read(display, intel_sdvo->sdvo_reg); 1628 if (intel_sdvo->base.port == PORT_B) 1629 sdvox &= SDVOB_PRESERVE_MASK; 1630 else 1631 sdvox &= SDVOC_PRESERVE_MASK; 1632 sdvox |= (9 << 19) | SDVO_BORDER_ENABLE; 1633 } 1634 1635 if (HAS_PCH_CPT(display)) 1636 sdvox |= SDVO_PIPE_SEL_CPT(crtc->pipe); 1637 else 1638 sdvox |= SDVO_PIPE_SEL(crtc->pipe); 1639 1640 if (DISPLAY_VER(display) >= 4) { 1641 /* done in crtc_mode_set as the dpll_md reg must be written early */ 1642 } else if (display->platform.i945g || display->platform.i945gm || 1643 display->platform.g33 || display->platform.pineview) { 1644 /* done in crtc_mode_set as it lives inside the dpll register */ 1645 } else { 1646 sdvox |= (crtc_state->pixel_multiplier - 1) 1647 << SDVO_PORT_MULTIPLY_SHIFT; 1648 } 1649 1650 if (input_dtd.part2.sdvo_flags & SDVO_NEED_TO_STALL && 1651 DISPLAY_VER(display) < 5) 1652 sdvox |= SDVO_STALL_SELECT; 1653 intel_sdvo_write_sdvox(intel_sdvo, sdvox); 1654 } 1655 1656 static bool intel_sdvo_connector_get_hw_state(struct intel_connector *connector) 1657 { 1658 struct intel_sdvo_connector *intel_sdvo_connector = 1659 to_intel_sdvo_connector(&connector->base); 1660 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector); 1661 u16 active_outputs = 0; 1662 1663 intel_sdvo_get_active_outputs(intel_sdvo, &active_outputs); 1664 1665 return active_outputs & intel_sdvo_connector->output_flag; 1666 } 1667 1668 bool intel_sdvo_port_enabled(struct intel_display *display, 1669 intel_reg_t sdvo_reg, enum pipe *pipe) 1670 { 1671 u32 val; 1672 1673 val = intel_de_read(display, sdvo_reg); 1674 1675 /* asserts want to know the pipe even if the port is disabled */ 1676 if (HAS_PCH_CPT(display)) 1677 *pipe = (val & SDVO_PIPE_SEL_MASK_CPT) >> SDVO_PIPE_SEL_SHIFT_CPT; 1678 else if (display->platform.cherryview) 1679 *pipe = (val & SDVO_PIPE_SEL_MASK_CHV) >> SDVO_PIPE_SEL_SHIFT_CHV; 1680 else 1681 *pipe = (val & SDVO_PIPE_SEL_MASK) >> SDVO_PIPE_SEL_SHIFT; 1682 1683 return val & SDVO_ENABLE; 1684 } 1685 1686 static bool intel_sdvo_get_hw_state(struct intel_encoder *encoder, 1687 enum pipe *pipe) 1688 { 1689 struct intel_display *display = to_intel_display(encoder); 1690 struct intel_sdvo *intel_sdvo = to_sdvo(encoder); 1691 u16 active_outputs = 0; 1692 bool ret; 1693 1694 intel_sdvo_get_active_outputs(intel_sdvo, &active_outputs); 1695 1696 ret = intel_sdvo_port_enabled(display, intel_sdvo->sdvo_reg, pipe); 1697 1698 return ret || active_outputs; 1699 } 1700 1701 static void intel_sdvo_get_config(struct intel_encoder *encoder, 1702 struct intel_crtc_state *pipe_config) 1703 { 1704 struct intel_display *display = to_intel_display(encoder); 1705 struct intel_sdvo *intel_sdvo = to_sdvo(encoder); 1706 struct intel_sdvo_dtd dtd; 1707 int encoder_pixel_multiplier = 0; 1708 int dotclock; 1709 u32 flags = 0, sdvox; 1710 u8 val; 1711 bool ret; 1712 1713 pipe_config->output_types |= BIT(INTEL_OUTPUT_SDVO); 1714 1715 sdvox = intel_de_read(display, intel_sdvo->sdvo_reg); 1716 1717 ret = intel_sdvo_get_input_timing(intel_sdvo, &dtd); 1718 if (!ret) { 1719 /* 1720 * Some sdvo encoders are not spec compliant and don't 1721 * implement the mandatory get_timings function. 1722 */ 1723 drm_dbg_kms(display->drm, "failed to retrieve SDVO DTD\n"); 1724 pipe_config->quirks |= PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS; 1725 } else { 1726 if (dtd.part2.dtd_flags & DTD_FLAG_HSYNC_POSITIVE) 1727 flags |= DRM_MODE_FLAG_PHSYNC; 1728 else 1729 flags |= DRM_MODE_FLAG_NHSYNC; 1730 1731 if (dtd.part2.dtd_flags & DTD_FLAG_VSYNC_POSITIVE) 1732 flags |= DRM_MODE_FLAG_PVSYNC; 1733 else 1734 flags |= DRM_MODE_FLAG_NVSYNC; 1735 } 1736 1737 pipe_config->hw.adjusted_mode.flags |= flags; 1738 1739 /* 1740 * pixel multiplier readout is tricky: Only on i915g/gm it is stored in 1741 * the sdvo port register, on all other platforms it is part of the dpll 1742 * state. Since the general pipe state readout happens before the 1743 * encoder->get_config we so already have a valid pixel multiplier on all 1744 * other platforms. 1745 */ 1746 if (display->platform.i915g || display->platform.i915gm) { 1747 pipe_config->pixel_multiplier = 1748 ((sdvox & SDVO_PORT_MULTIPLY_MASK) 1749 >> SDVO_PORT_MULTIPLY_SHIFT) + 1; 1750 } 1751 1752 dotclock = pipe_config->port_clock; 1753 1754 if (pipe_config->pixel_multiplier) 1755 dotclock /= pipe_config->pixel_multiplier; 1756 1757 pipe_config->hw.adjusted_mode.crtc_clock = dotclock; 1758 1759 /* Cross check the port pixel multiplier with the sdvo encoder state. */ 1760 if (intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_CLOCK_RATE_MULT, 1761 &val, 1)) { 1762 switch (val) { 1763 case SDVO_CLOCK_RATE_MULT_1X: 1764 encoder_pixel_multiplier = 1; 1765 break; 1766 case SDVO_CLOCK_RATE_MULT_2X: 1767 encoder_pixel_multiplier = 2; 1768 break; 1769 case SDVO_CLOCK_RATE_MULT_4X: 1770 encoder_pixel_multiplier = 4; 1771 break; 1772 } 1773 } 1774 1775 drm_WARN(display->drm, 1776 encoder_pixel_multiplier != pipe_config->pixel_multiplier, 1777 "SDVO pixel multiplier mismatch, port: %i, encoder: %i\n", 1778 pipe_config->pixel_multiplier, encoder_pixel_multiplier); 1779 1780 if (intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_COLORIMETRY, 1781 &val, 1)) { 1782 if (val == SDVO_COLORIMETRY_RGB220) 1783 pipe_config->limited_color_range = true; 1784 } 1785 1786 if (intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_AUDIO_STAT, 1787 &val, 1)) { 1788 if (val & SDVO_AUDIO_PRESENCE_DETECT) 1789 pipe_config->has_audio = true; 1790 } 1791 1792 if (intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_ENCODE, 1793 &val, 1)) { 1794 if (val == SDVO_ENCODE_HDMI) 1795 pipe_config->has_hdmi_sink = true; 1796 } 1797 1798 intel_sdvo_get_avi_infoframe(intel_sdvo, pipe_config); 1799 1800 intel_sdvo_get_eld(intel_sdvo, pipe_config); 1801 } 1802 1803 static void intel_sdvo_disable_audio(struct intel_encoder *encoder, 1804 const struct intel_crtc_state *old_crtc_state, 1805 const struct drm_connector_state *old_conn_state) 1806 { 1807 struct intel_sdvo *intel_sdvo = to_sdvo(encoder); 1808 1809 if (!old_crtc_state->has_audio) 1810 return; 1811 1812 intel_sdvo_set_audio_state(intel_sdvo, 0); 1813 } 1814 1815 static void intel_sdvo_enable_audio(struct intel_encoder *encoder, 1816 const struct intel_crtc_state *crtc_state, 1817 const struct drm_connector_state *conn_state) 1818 { 1819 struct intel_sdvo *intel_sdvo = to_sdvo(encoder); 1820 const u8 *eld = crtc_state->eld; 1821 1822 if (!crtc_state->has_audio) 1823 return; 1824 1825 intel_sdvo_set_audio_state(intel_sdvo, 0); 1826 1827 intel_sdvo_write_infoframe(intel_sdvo, SDVO_HBUF_INDEX_ELD, 1828 SDVO_HBUF_TX_DISABLED, 1829 eld, drm_eld_size(eld)); 1830 1831 intel_sdvo_set_audio_state(intel_sdvo, SDVO_AUDIO_ELD_VALID | 1832 SDVO_AUDIO_PRESENCE_DETECT); 1833 } 1834 1835 static void intel_disable_sdvo(struct intel_atomic_state *state, 1836 struct intel_encoder *encoder, 1837 const struct intel_crtc_state *old_crtc_state, 1838 const struct drm_connector_state *conn_state) 1839 { 1840 struct intel_display *display = to_intel_display(encoder); 1841 struct intel_sdvo *intel_sdvo = to_sdvo(encoder); 1842 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); 1843 u32 temp; 1844 1845 intel_sdvo_set_active_outputs(intel_sdvo, 0); 1846 if (0) 1847 intel_sdvo_set_encoder_power_state(intel_sdvo, 1848 DRM_MODE_DPMS_OFF); 1849 1850 temp = intel_de_read(display, intel_sdvo->sdvo_reg); 1851 1852 temp &= ~SDVO_ENABLE; 1853 intel_sdvo_write_sdvox(intel_sdvo, temp); 1854 1855 /* 1856 * HW workaround for IBX, we need to move the port 1857 * to transcoder A after disabling it to allow the 1858 * matching DP port to be enabled on transcoder A. 1859 */ 1860 if (HAS_PCH_IBX(display) && crtc->pipe == PIPE_B) { 1861 /* 1862 * We get CPU/PCH FIFO underruns on the other pipe when 1863 * doing the workaround. Sweep them under the rug. 1864 */ 1865 intel_set_cpu_fifo_underrun_reporting(display, PIPE_A, false); 1866 intel_set_pch_fifo_underrun_reporting(display, PIPE_A, false); 1867 1868 temp &= ~SDVO_PIPE_SEL_MASK; 1869 temp |= SDVO_ENABLE | SDVO_PIPE_SEL(PIPE_A); 1870 intel_sdvo_write_sdvox(intel_sdvo, temp); 1871 1872 temp &= ~SDVO_ENABLE; 1873 intel_sdvo_write_sdvox(intel_sdvo, temp); 1874 1875 intel_wait_for_vblank_if_active(display, PIPE_A); 1876 intel_set_cpu_fifo_underrun_reporting(display, PIPE_A, true); 1877 intel_set_pch_fifo_underrun_reporting(display, PIPE_A, true); 1878 } 1879 } 1880 1881 static void pch_disable_sdvo(struct intel_atomic_state *state, 1882 struct intel_encoder *encoder, 1883 const struct intel_crtc_state *old_crtc_state, 1884 const struct drm_connector_state *old_conn_state) 1885 { 1886 } 1887 1888 static void pch_post_disable_sdvo(struct intel_atomic_state *state, 1889 struct intel_encoder *encoder, 1890 const struct intel_crtc_state *old_crtc_state, 1891 const struct drm_connector_state *old_conn_state) 1892 { 1893 intel_disable_sdvo(state, encoder, old_crtc_state, old_conn_state); 1894 } 1895 1896 static void intel_enable_sdvo(struct intel_atomic_state *state, 1897 struct intel_encoder *encoder, 1898 const struct intel_crtc_state *pipe_config, 1899 const struct drm_connector_state *conn_state) 1900 { 1901 struct intel_display *display = to_intel_display(encoder); 1902 struct intel_sdvo *intel_sdvo = to_sdvo(encoder); 1903 struct intel_sdvo_connector *intel_sdvo_connector = 1904 to_intel_sdvo_connector(conn_state->connector); 1905 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 1906 u32 temp; 1907 bool input1, input2; 1908 int i; 1909 bool success; 1910 1911 temp = intel_de_read(display, intel_sdvo->sdvo_reg); 1912 temp |= SDVO_ENABLE; 1913 intel_sdvo_write_sdvox(intel_sdvo, temp); 1914 1915 for (i = 0; i < 2; i++) 1916 intel_crtc_wait_for_next_vblank(crtc); 1917 1918 success = intel_sdvo_get_trained_inputs(intel_sdvo, &input1, &input2); 1919 /* 1920 * Warn if the device reported failure to sync. 1921 * 1922 * A lot of SDVO devices fail to notify of sync, but it's 1923 * a given it the status is a success, we succeeded. 1924 */ 1925 if (success && !input1) { 1926 drm_dbg_kms(display->drm, 1927 "First %s output reported failure to sync\n", 1928 SDVO_NAME(intel_sdvo)); 1929 } 1930 1931 if (0) 1932 intel_sdvo_set_encoder_power_state(intel_sdvo, 1933 DRM_MODE_DPMS_ON); 1934 intel_sdvo_set_active_outputs(intel_sdvo, intel_sdvo_connector->output_flag); 1935 } 1936 1937 static enum drm_mode_status 1938 intel_sdvo_mode_valid(struct drm_connector *connector, 1939 const struct drm_display_mode *mode) 1940 { 1941 struct intel_display *display = to_intel_display(connector->dev); 1942 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(to_intel_connector(connector)); 1943 struct intel_sdvo_connector *intel_sdvo_connector = 1944 to_intel_sdvo_connector(connector); 1945 bool has_hdmi_sink = intel_has_hdmi_sink(intel_sdvo_connector, connector->state); 1946 int max_dotclk = display->cdclk.max_dotclk_freq; 1947 enum drm_mode_status status; 1948 int clock = mode->clock; 1949 1950 status = intel_cpu_transcoder_mode_valid(display, mode); 1951 if (status != MODE_OK) 1952 return status; 1953 1954 if (clock > max_dotclk) 1955 return MODE_CLOCK_HIGH; 1956 1957 if (mode->flags & DRM_MODE_FLAG_DBLCLK) { 1958 if (!has_hdmi_sink) 1959 return MODE_CLOCK_LOW; 1960 clock *= 2; 1961 } 1962 1963 if (intel_sdvo->pixel_clock_min > clock) 1964 return MODE_CLOCK_LOW; 1965 1966 if (intel_sdvo->pixel_clock_max < clock) 1967 return MODE_CLOCK_HIGH; 1968 1969 if (IS_LVDS(intel_sdvo_connector)) { 1970 enum drm_mode_status status; 1971 int target_clock; 1972 1973 status = intel_panel_mode_valid(&intel_sdvo_connector->base, mode, &target_clock); 1974 if (status != MODE_OK) 1975 return status; 1976 1977 if (target_clock > max_dotclk) 1978 return MODE_CLOCK_HIGH; 1979 } 1980 1981 return MODE_OK; 1982 } 1983 1984 static bool intel_sdvo_get_capabilities(struct intel_sdvo *intel_sdvo, struct intel_sdvo_caps *caps) 1985 { 1986 struct intel_display *display = to_intel_display(&intel_sdvo->base); 1987 1988 BUILD_BUG_ON(sizeof(*caps) != 8); 1989 if (!intel_sdvo_get_value(intel_sdvo, 1990 SDVO_CMD_GET_DEVICE_CAPS, 1991 caps, sizeof(*caps))) 1992 return false; 1993 1994 drm_dbg_kms(display->drm, "SDVO capabilities:\n" 1995 " vendor_id: %d\n" 1996 " device_id: %d\n" 1997 " device_rev_id: %d\n" 1998 " sdvo_version_major: %d\n" 1999 " sdvo_version_minor: %d\n" 2000 " sdvo_num_inputs: %d\n" 2001 " smooth_scaling: %d\n" 2002 " sharp_scaling: %d\n" 2003 " up_scaling: %d\n" 2004 " down_scaling: %d\n" 2005 " stall_support: %d\n" 2006 " output_flags: %d\n", 2007 caps->vendor_id, 2008 caps->device_id, 2009 caps->device_rev_id, 2010 caps->sdvo_version_major, 2011 caps->sdvo_version_minor, 2012 caps->sdvo_num_inputs, 2013 caps->smooth_scaling, 2014 caps->sharp_scaling, 2015 caps->up_scaling, 2016 caps->down_scaling, 2017 caps->stall_support, 2018 caps->output_flags); 2019 2020 return true; 2021 } 2022 2023 static u8 intel_sdvo_get_colorimetry_cap(struct intel_sdvo *intel_sdvo) 2024 { 2025 u8 cap; 2026 2027 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_COLORIMETRY_CAP, 2028 &cap, sizeof(cap))) 2029 return SDVO_COLORIMETRY_RGB256; 2030 2031 return cap; 2032 } 2033 2034 static u16 intel_sdvo_get_hotplug_support(struct intel_sdvo *intel_sdvo) 2035 { 2036 struct intel_display *display = to_intel_display(&intel_sdvo->base); 2037 u16 hotplug; 2038 2039 if (!HAS_HOTPLUG(display)) 2040 return 0; 2041 2042 /* 2043 * HW Erratum: SDVO Hotplug is broken on all i945G chips, there's noise 2044 * on the line. 2045 */ 2046 if (display->platform.i945g || display->platform.i945gm) 2047 return 0; 2048 2049 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_HOT_PLUG_SUPPORT, 2050 &hotplug, sizeof(hotplug))) 2051 return 0; 2052 2053 return hotplug; 2054 } 2055 2056 static void intel_sdvo_enable_hotplug(struct intel_encoder *encoder) 2057 { 2058 struct intel_sdvo *intel_sdvo = to_sdvo(encoder); 2059 2060 if (!intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_SET_ACTIVE_HOT_PLUG, 2061 &intel_sdvo->hotplug_active, 2)) 2062 drm_warn(intel_sdvo->base.base.dev, 2063 "Failed to enable hotplug on SDVO encoder\n"); 2064 } 2065 2066 static enum intel_hotplug_state 2067 intel_sdvo_hotplug(struct intel_encoder *encoder, 2068 struct intel_connector *connector) 2069 { 2070 intel_sdvo_enable_hotplug(encoder); 2071 2072 return intel_encoder_hotplug(encoder, connector); 2073 } 2074 2075 static const struct drm_edid * 2076 intel_sdvo_get_edid(struct drm_connector *connector) 2077 { 2078 struct i2c_adapter *ddc = connector->ddc; 2079 2080 if (!ddc) 2081 return NULL; 2082 2083 return drm_edid_read_ddc(connector, ddc); 2084 } 2085 2086 /* Mac mini hack -- use the same DDC as the analog connector */ 2087 static const struct drm_edid * 2088 intel_sdvo_get_analog_edid(struct drm_connector *connector) 2089 { 2090 struct intel_display *display = to_intel_display(connector->dev); 2091 struct i2c_adapter *ddc; 2092 2093 ddc = intel_gmbus_get_adapter(display, display->vbt.crt_ddc_pin); 2094 if (!ddc) 2095 return NULL; 2096 2097 return drm_edid_read_ddc(connector, ddc); 2098 } 2099 2100 static enum drm_connector_status 2101 intel_sdvo_tmds_sink_detect(struct drm_connector *connector) 2102 { 2103 enum drm_connector_status status; 2104 const struct drm_edid *drm_edid; 2105 2106 drm_edid = intel_sdvo_get_edid(connector); 2107 2108 /* 2109 * When there is no edid and no monitor is connected with VGA 2110 * port, try to use the CRT ddc to read the EDID for DVI-connector. 2111 */ 2112 if (!drm_edid) 2113 drm_edid = intel_sdvo_get_analog_edid(connector); 2114 2115 status = connector_status_unknown; 2116 if (drm_edid) { 2117 /* DDC bus is shared, match EDID to connector type */ 2118 if (drm_edid_is_digital(drm_edid)) 2119 status = connector_status_connected; 2120 else 2121 status = connector_status_disconnected; 2122 drm_edid_free(drm_edid); 2123 } 2124 2125 return status; 2126 } 2127 2128 static bool 2129 intel_sdvo_connector_matches_edid(struct intel_sdvo_connector *sdvo, 2130 const struct drm_edid *drm_edid) 2131 { 2132 bool monitor_is_digital = drm_edid_is_digital(drm_edid); 2133 bool connector_is_digital = !!IS_DIGITAL(sdvo); 2134 2135 drm_dbg_kms(sdvo->base.base.dev, 2136 "connector_is_digital? %d, monitor_is_digital? %d\n", 2137 connector_is_digital, monitor_is_digital); 2138 return connector_is_digital == monitor_is_digital; 2139 } 2140 2141 static enum drm_connector_status 2142 intel_sdvo_detect(struct drm_connector *connector, bool force) 2143 { 2144 struct intel_display *display = to_intel_display(connector->dev); 2145 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(to_intel_connector(connector)); 2146 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector); 2147 enum drm_connector_status ret; 2148 u16 response; 2149 2150 drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s]\n", 2151 connector->base.id, connector->name); 2152 2153 if (!intel_display_device_enabled(display)) 2154 return connector_status_disconnected; 2155 2156 if (!intel_display_driver_check_access(display)) 2157 return connector->status; 2158 2159 if (!intel_sdvo_set_target_output(intel_sdvo, 2160 intel_sdvo_connector->output_flag)) 2161 return connector_status_unknown; 2162 2163 if (!intel_sdvo_get_value(intel_sdvo, 2164 SDVO_CMD_GET_ATTACHED_DISPLAYS, 2165 &response, 2)) 2166 return connector_status_unknown; 2167 2168 drm_dbg_kms(display->drm, "SDVO response %d %d [%x]\n", 2169 response & 0xff, response >> 8, 2170 intel_sdvo_connector->output_flag); 2171 2172 if (response == 0) 2173 return connector_status_disconnected; 2174 2175 if ((intel_sdvo_connector->output_flag & response) == 0) 2176 ret = connector_status_disconnected; 2177 else if (IS_TMDS(intel_sdvo_connector)) 2178 ret = intel_sdvo_tmds_sink_detect(connector); 2179 else { 2180 const struct drm_edid *drm_edid; 2181 2182 /* if we have an edid check it matches the connection */ 2183 drm_edid = intel_sdvo_get_edid(connector); 2184 if (!drm_edid) 2185 drm_edid = intel_sdvo_get_analog_edid(connector); 2186 if (drm_edid) { 2187 if (intel_sdvo_connector_matches_edid(intel_sdvo_connector, 2188 drm_edid)) 2189 ret = connector_status_connected; 2190 else 2191 ret = connector_status_disconnected; 2192 2193 drm_edid_free(drm_edid); 2194 } else { 2195 ret = connector_status_connected; 2196 } 2197 } 2198 2199 return ret; 2200 } 2201 2202 static int intel_sdvo_get_ddc_modes(struct drm_connector *connector) 2203 { 2204 struct intel_display *display = to_intel_display(connector->dev); 2205 int num_modes = 0; 2206 const struct drm_edid *drm_edid; 2207 2208 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s]\n", 2209 connector->base.id, connector->name); 2210 2211 if (!intel_display_driver_check_access(display)) 2212 return drm_edid_connector_add_modes(connector); 2213 2214 /* set the bus switch and get the modes */ 2215 drm_edid = intel_sdvo_get_edid(connector); 2216 2217 /* 2218 * Mac mini hack. On this device, the DVI-I connector shares one DDC 2219 * link between analog and digital outputs. So, if the regular SDVO 2220 * DDC fails, check to see if the analog output is disconnected, in 2221 * which case we'll look there for the digital DDC data. 2222 */ 2223 if (!drm_edid) 2224 drm_edid = intel_sdvo_get_analog_edid(connector); 2225 2226 if (!drm_edid) 2227 return 0; 2228 2229 if (intel_sdvo_connector_matches_edid(to_intel_sdvo_connector(connector), 2230 drm_edid)) 2231 num_modes += intel_connector_update_modes(connector, drm_edid); 2232 2233 drm_edid_free(drm_edid); 2234 2235 return num_modes; 2236 } 2237 2238 /* 2239 * Set of SDVO TV modes. 2240 * Note! This is in reply order (see loop in get_tv_modes). 2241 * XXX: all 60Hz refresh? 2242 */ 2243 static const struct drm_display_mode sdvo_tv_modes[] = { 2244 { DRM_MODE("320x200", DRM_MODE_TYPE_DRIVER, 5815, 320, 321, 384, 2245 416, 0, 200, 201, 232, 233, 0, 2246 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 2247 { DRM_MODE("320x240", DRM_MODE_TYPE_DRIVER, 6814, 320, 321, 384, 2248 416, 0, 240, 241, 272, 273, 0, 2249 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 2250 { DRM_MODE("400x300", DRM_MODE_TYPE_DRIVER, 9910, 400, 401, 464, 2251 496, 0, 300, 301, 332, 333, 0, 2252 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 2253 { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 16913, 640, 641, 704, 2254 736, 0, 350, 351, 382, 383, 0, 2255 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 2256 { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 19121, 640, 641, 704, 2257 736, 0, 400, 401, 432, 433, 0, 2258 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 2259 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 22654, 640, 641, 704, 2260 736, 0, 480, 481, 512, 513, 0, 2261 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 2262 { DRM_MODE("704x480", DRM_MODE_TYPE_DRIVER, 24624, 704, 705, 768, 2263 800, 0, 480, 481, 512, 513, 0, 2264 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 2265 { DRM_MODE("704x576", DRM_MODE_TYPE_DRIVER, 29232, 704, 705, 768, 2266 800, 0, 576, 577, 608, 609, 0, 2267 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 2268 { DRM_MODE("720x350", DRM_MODE_TYPE_DRIVER, 18751, 720, 721, 784, 2269 816, 0, 350, 351, 382, 383, 0, 2270 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 2271 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 21199, 720, 721, 784, 2272 816, 0, 400, 401, 432, 433, 0, 2273 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 2274 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 25116, 720, 721, 784, 2275 816, 0, 480, 481, 512, 513, 0, 2276 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 2277 { DRM_MODE("720x540", DRM_MODE_TYPE_DRIVER, 28054, 720, 721, 784, 2278 816, 0, 540, 541, 572, 573, 0, 2279 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 2280 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 29816, 720, 721, 784, 2281 816, 0, 576, 577, 608, 609, 0, 2282 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 2283 { DRM_MODE("768x576", DRM_MODE_TYPE_DRIVER, 31570, 768, 769, 832, 2284 864, 0, 576, 577, 608, 609, 0, 2285 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 2286 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 34030, 800, 801, 864, 2287 896, 0, 600, 601, 632, 633, 0, 2288 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 2289 { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 36581, 832, 833, 896, 2290 928, 0, 624, 625, 656, 657, 0, 2291 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 2292 { DRM_MODE("920x766", DRM_MODE_TYPE_DRIVER, 48707, 920, 921, 984, 2293 1016, 0, 766, 767, 798, 799, 0, 2294 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 2295 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 53827, 1024, 1025, 1088, 2296 1120, 0, 768, 769, 800, 801, 0, 2297 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 2298 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 87265, 1280, 1281, 1344, 2299 1376, 0, 1024, 1025, 1056, 1057, 0, 2300 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 2301 }; 2302 2303 static int intel_sdvo_get_tv_modes(struct drm_connector *connector) 2304 { 2305 struct intel_display *display = to_intel_display(connector->dev); 2306 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(to_intel_connector(connector)); 2307 struct intel_sdvo_connector *intel_sdvo_connector = 2308 to_intel_sdvo_connector(connector); 2309 const struct drm_connector_state *conn_state = connector->state; 2310 struct intel_sdvo_sdtv_resolution_request tv_res; 2311 u32 reply = 0, format_map = 0; 2312 int num_modes = 0; 2313 int i; 2314 2315 drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s]\n", 2316 connector->base.id, connector->name); 2317 2318 if (!intel_display_driver_check_access(display)) 2319 return 0; 2320 2321 /* 2322 * Read the list of supported input resolutions for the selected TV 2323 * format. 2324 */ 2325 format_map = 1 << conn_state->tv.legacy_mode; 2326 memcpy(&tv_res, &format_map, 2327 min(sizeof(format_map), sizeof(struct intel_sdvo_sdtv_resolution_request))); 2328 2329 if (!intel_sdvo_set_target_output(intel_sdvo, intel_sdvo_connector->output_flag)) 2330 return 0; 2331 2332 BUILD_BUG_ON(sizeof(tv_res) != 3); 2333 if (!intel_sdvo_write_cmd(intel_sdvo, 2334 SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT, 2335 &tv_res, sizeof(tv_res))) 2336 return 0; 2337 if (!intel_sdvo_read_response(intel_sdvo, &reply, 3)) 2338 return 0; 2339 2340 for (i = 0; i < ARRAY_SIZE(sdvo_tv_modes); i++) { 2341 if (reply & (1 << i)) { 2342 struct drm_display_mode *nmode; 2343 nmode = drm_mode_duplicate(connector->dev, 2344 &sdvo_tv_modes[i]); 2345 if (nmode) { 2346 drm_mode_probed_add(connector, nmode); 2347 num_modes++; 2348 } 2349 } 2350 } 2351 2352 return num_modes; 2353 } 2354 2355 static int intel_sdvo_get_lvds_modes(struct drm_connector *connector) 2356 { 2357 struct intel_display *display = to_intel_display(connector->dev); 2358 2359 drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s]\n", 2360 connector->base.id, connector->name); 2361 2362 return intel_panel_get_modes(to_intel_connector(connector)); 2363 } 2364 2365 static int intel_sdvo_get_modes(struct drm_connector *connector) 2366 { 2367 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector); 2368 2369 if (IS_TV(intel_sdvo_connector)) 2370 return intel_sdvo_get_tv_modes(connector); 2371 else if (IS_LVDS(intel_sdvo_connector)) 2372 return intel_sdvo_get_lvds_modes(connector); 2373 else 2374 return intel_sdvo_get_ddc_modes(connector); 2375 } 2376 2377 static int 2378 intel_sdvo_connector_atomic_get_property(struct drm_connector *connector, 2379 const struct drm_connector_state *state, 2380 struct drm_property *property, 2381 u64 *val) 2382 { 2383 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector); 2384 const struct intel_sdvo_connector_state *sdvo_state = to_intel_sdvo_connector_state(state); 2385 2386 if (property == intel_sdvo_connector->tv_format) { 2387 int i; 2388 2389 for (i = 0; i < intel_sdvo_connector->format_supported_num; i++) 2390 if (state->tv.legacy_mode == intel_sdvo_connector->tv_format_supported[i]) { 2391 *val = i; 2392 2393 return 0; 2394 } 2395 2396 drm_WARN_ON(connector->dev, 1); 2397 *val = 0; 2398 } else if (property == intel_sdvo_connector->top || 2399 property == intel_sdvo_connector->bottom) 2400 *val = intel_sdvo_connector->max_vscan - sdvo_state->tv.overscan_v; 2401 else if (property == intel_sdvo_connector->left || 2402 property == intel_sdvo_connector->right) 2403 *val = intel_sdvo_connector->max_hscan - sdvo_state->tv.overscan_h; 2404 else if (property == intel_sdvo_connector->hpos) 2405 *val = sdvo_state->tv.hpos; 2406 else if (property == intel_sdvo_connector->vpos) 2407 *val = sdvo_state->tv.vpos; 2408 else if (property == intel_sdvo_connector->saturation) 2409 *val = state->tv.saturation; 2410 else if (property == intel_sdvo_connector->contrast) 2411 *val = state->tv.contrast; 2412 else if (property == intel_sdvo_connector->hue) 2413 *val = state->tv.hue; 2414 else if (property == intel_sdvo_connector->brightness) 2415 *val = state->tv.brightness; 2416 else if (property == intel_sdvo_connector->sharpness) 2417 *val = sdvo_state->tv.sharpness; 2418 else if (property == intel_sdvo_connector->flicker_filter) 2419 *val = sdvo_state->tv.flicker_filter; 2420 else if (property == intel_sdvo_connector->flicker_filter_2d) 2421 *val = sdvo_state->tv.flicker_filter_2d; 2422 else if (property == intel_sdvo_connector->flicker_filter_adaptive) 2423 *val = sdvo_state->tv.flicker_filter_adaptive; 2424 else if (property == intel_sdvo_connector->tv_chroma_filter) 2425 *val = sdvo_state->tv.chroma_filter; 2426 else if (property == intel_sdvo_connector->tv_luma_filter) 2427 *val = sdvo_state->tv.luma_filter; 2428 else if (property == intel_sdvo_connector->dot_crawl) 2429 *val = sdvo_state->tv.dot_crawl; 2430 else 2431 return intel_digital_connector_atomic_get_property(connector, state, property, val); 2432 2433 return 0; 2434 } 2435 2436 static int 2437 intel_sdvo_connector_atomic_set_property(struct drm_connector *connector, 2438 struct drm_connector_state *state, 2439 struct drm_property *property, 2440 u64 val) 2441 { 2442 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector); 2443 struct intel_sdvo_connector_state *sdvo_state = to_intel_sdvo_connector_state(state); 2444 2445 if (property == intel_sdvo_connector->tv_format) { 2446 state->tv.legacy_mode = intel_sdvo_connector->tv_format_supported[val]; 2447 2448 if (state->crtc) { 2449 struct drm_crtc_state *crtc_state = 2450 drm_atomic_get_new_crtc_state(state->state, state->crtc); 2451 2452 crtc_state->connectors_changed = true; 2453 } 2454 } else if (property == intel_sdvo_connector->top || 2455 property == intel_sdvo_connector->bottom) 2456 /* Cannot set these independent from each other */ 2457 sdvo_state->tv.overscan_v = intel_sdvo_connector->max_vscan - val; 2458 else if (property == intel_sdvo_connector->left || 2459 property == intel_sdvo_connector->right) 2460 /* Cannot set these independent from each other */ 2461 sdvo_state->tv.overscan_h = intel_sdvo_connector->max_hscan - val; 2462 else if (property == intel_sdvo_connector->hpos) 2463 sdvo_state->tv.hpos = val; 2464 else if (property == intel_sdvo_connector->vpos) 2465 sdvo_state->tv.vpos = val; 2466 else if (property == intel_sdvo_connector->saturation) 2467 state->tv.saturation = val; 2468 else if (property == intel_sdvo_connector->contrast) 2469 state->tv.contrast = val; 2470 else if (property == intel_sdvo_connector->hue) 2471 state->tv.hue = val; 2472 else if (property == intel_sdvo_connector->brightness) 2473 state->tv.brightness = val; 2474 else if (property == intel_sdvo_connector->sharpness) 2475 sdvo_state->tv.sharpness = val; 2476 else if (property == intel_sdvo_connector->flicker_filter) 2477 sdvo_state->tv.flicker_filter = val; 2478 else if (property == intel_sdvo_connector->flicker_filter_2d) 2479 sdvo_state->tv.flicker_filter_2d = val; 2480 else if (property == intel_sdvo_connector->flicker_filter_adaptive) 2481 sdvo_state->tv.flicker_filter_adaptive = val; 2482 else if (property == intel_sdvo_connector->tv_chroma_filter) 2483 sdvo_state->tv.chroma_filter = val; 2484 else if (property == intel_sdvo_connector->tv_luma_filter) 2485 sdvo_state->tv.luma_filter = val; 2486 else if (property == intel_sdvo_connector->dot_crawl) 2487 sdvo_state->tv.dot_crawl = val; 2488 else 2489 return intel_digital_connector_atomic_set_property(connector, state, property, val); 2490 2491 return 0; 2492 } 2493 2494 static struct drm_connector_state * 2495 intel_sdvo_connector_duplicate_state(struct drm_connector *connector) 2496 { 2497 struct intel_sdvo_connector_state *state; 2498 2499 state = kmemdup(connector->state, sizeof(*state), GFP_KERNEL); 2500 if (!state) 2501 return NULL; 2502 2503 __drm_atomic_helper_connector_duplicate_state(connector, &state->base.base); 2504 return &state->base.base; 2505 } 2506 2507 static const struct drm_connector_funcs intel_sdvo_connector_funcs = { 2508 .detect = intel_sdvo_detect, 2509 .fill_modes = drm_helper_probe_single_connector_modes, 2510 .atomic_get_property = intel_sdvo_connector_atomic_get_property, 2511 .atomic_set_property = intel_sdvo_connector_atomic_set_property, 2512 .late_register = intel_connector_register, 2513 .early_unregister = intel_connector_unregister, 2514 .destroy = intel_connector_destroy, 2515 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 2516 .atomic_duplicate_state = intel_sdvo_connector_duplicate_state, 2517 }; 2518 2519 static int intel_sdvo_atomic_check(struct drm_connector *conn, 2520 struct drm_atomic_commit *state) 2521 { 2522 struct drm_connector_state *new_conn_state = 2523 drm_atomic_get_new_connector_state(state, conn); 2524 struct drm_connector_state *old_conn_state = 2525 drm_atomic_get_old_connector_state(state, conn); 2526 struct intel_sdvo_connector_state *old_state = 2527 to_intel_sdvo_connector_state(old_conn_state); 2528 struct intel_sdvo_connector_state *new_state = 2529 to_intel_sdvo_connector_state(new_conn_state); 2530 2531 if (new_conn_state->crtc && 2532 (memcmp(&old_state->tv, &new_state->tv, sizeof(old_state->tv)) || 2533 memcmp(&old_conn_state->tv, &new_conn_state->tv, sizeof(old_conn_state->tv)))) { 2534 struct drm_crtc_state *crtc_state = 2535 drm_atomic_get_new_crtc_state(state, 2536 new_conn_state->crtc); 2537 2538 crtc_state->connectors_changed = true; 2539 } 2540 2541 return intel_digital_connector_atomic_check(conn, state); 2542 } 2543 2544 static const struct drm_connector_helper_funcs intel_sdvo_connector_helper_funcs = { 2545 .get_modes = intel_sdvo_get_modes, 2546 .mode_valid = intel_sdvo_mode_valid, 2547 .atomic_check = intel_sdvo_atomic_check, 2548 }; 2549 2550 static void intel_sdvo_encoder_destroy(struct drm_encoder *_encoder) 2551 { 2552 struct intel_encoder *encoder = to_intel_encoder(_encoder); 2553 struct intel_sdvo *sdvo = to_sdvo(encoder); 2554 int i; 2555 2556 for (i = 0; i < ARRAY_SIZE(sdvo->ddc); i++) { 2557 if (sdvo->ddc[i].ddc_bus) 2558 i2c_del_adapter(&sdvo->ddc[i].ddc); 2559 } 2560 2561 drm_encoder_cleanup(&encoder->base); 2562 kfree(sdvo); 2563 }; 2564 2565 static const struct drm_encoder_funcs intel_sdvo_enc_funcs = { 2566 .destroy = intel_sdvo_encoder_destroy, 2567 }; 2568 2569 static int 2570 intel_sdvo_guess_ddc_bus(struct intel_sdvo *sdvo, 2571 struct intel_sdvo_connector *connector) 2572 { 2573 u16 mask = 0; 2574 int num_bits; 2575 2576 /* 2577 * Make a mask of outputs less than or equal to our own priority in the 2578 * list. 2579 */ 2580 switch (connector->output_flag) { 2581 case SDVO_OUTPUT_LVDS1: 2582 mask |= SDVO_OUTPUT_LVDS1; 2583 fallthrough; 2584 case SDVO_OUTPUT_LVDS0: 2585 mask |= SDVO_OUTPUT_LVDS0; 2586 fallthrough; 2587 case SDVO_OUTPUT_TMDS1: 2588 mask |= SDVO_OUTPUT_TMDS1; 2589 fallthrough; 2590 case SDVO_OUTPUT_TMDS0: 2591 mask |= SDVO_OUTPUT_TMDS0; 2592 fallthrough; 2593 case SDVO_OUTPUT_RGB1: 2594 mask |= SDVO_OUTPUT_RGB1; 2595 fallthrough; 2596 case SDVO_OUTPUT_RGB0: 2597 mask |= SDVO_OUTPUT_RGB0; 2598 break; 2599 } 2600 2601 /* Count bits to find what number we are in the priority list. */ 2602 mask &= sdvo->caps.output_flags; 2603 num_bits = hweight16(mask); 2604 /* If more than 3 outputs, default to DDC bus 3 for now. */ 2605 if (num_bits > 3) 2606 num_bits = 3; 2607 2608 /* Corresponds to SDVO_CONTROL_BUS_DDCx */ 2609 return num_bits; 2610 } 2611 2612 /* 2613 * Choose the appropriate DDC bus for control bus switch command for this 2614 * SDVO output based on the controlled output. 2615 * 2616 * DDC bus number assignment is in a priority order of RGB outputs, then TMDS 2617 * outputs, then LVDS outputs. 2618 */ 2619 static struct intel_sdvo_ddc * 2620 intel_sdvo_select_ddc_bus(struct intel_sdvo *sdvo, 2621 struct intel_sdvo_connector *connector) 2622 { 2623 struct intel_display *display = to_intel_display(&sdvo->base); 2624 const struct sdvo_device_mapping *mapping; 2625 int ddc_bus; 2626 2627 if (sdvo->base.port == PORT_B) 2628 mapping = &display->vbt.sdvo_mappings[0]; 2629 else 2630 mapping = &display->vbt.sdvo_mappings[1]; 2631 2632 if (mapping->initialized) 2633 ddc_bus = (mapping->ddc_pin & 0xf0) >> 4; 2634 else 2635 ddc_bus = intel_sdvo_guess_ddc_bus(sdvo, connector); 2636 2637 if (ddc_bus < 1 || ddc_bus > 3) 2638 return NULL; 2639 2640 return &sdvo->ddc[ddc_bus - 1]; 2641 } 2642 2643 static void 2644 intel_sdvo_select_i2c_bus(struct intel_sdvo *sdvo) 2645 { 2646 struct intel_display *display = to_intel_display(&sdvo->base); 2647 const struct sdvo_device_mapping *mapping; 2648 u8 pin; 2649 2650 if (sdvo->base.port == PORT_B) 2651 mapping = &display->vbt.sdvo_mappings[0]; 2652 else 2653 mapping = &display->vbt.sdvo_mappings[1]; 2654 2655 if (mapping->initialized && 2656 intel_gmbus_is_valid_pin(display, mapping->i2c_pin)) 2657 pin = mapping->i2c_pin; 2658 else 2659 pin = GMBUS_PIN_DPB; 2660 2661 drm_dbg_kms(display->drm, "[ENCODER:%d:%s] I2C pin %d, target addr 0x%x\n", 2662 sdvo->base.base.base.id, sdvo->base.base.name, 2663 pin, sdvo->target_addr); 2664 2665 sdvo->i2c = intel_gmbus_get_adapter(display, pin); 2666 2667 /* 2668 * With gmbus we should be able to drive sdvo i2c at 2MHz, but somehow 2669 * our code totally fails once we start using gmbus. Hence fall back to 2670 * bit banging for now. 2671 */ 2672 intel_gmbus_force_bit(sdvo->i2c, true); 2673 } 2674 2675 /* undo any changes intel_sdvo_select_i2c_bus() did to sdvo->i2c */ 2676 static void 2677 intel_sdvo_unselect_i2c_bus(struct intel_sdvo *sdvo) 2678 { 2679 intel_gmbus_force_bit(sdvo->i2c, false); 2680 } 2681 2682 static bool 2683 intel_sdvo_is_hdmi_connector(struct intel_sdvo *intel_sdvo) 2684 { 2685 return intel_sdvo_check_supp_encode(intel_sdvo); 2686 } 2687 2688 static u8 2689 intel_sdvo_get_target_addr(struct intel_sdvo *sdvo) 2690 { 2691 struct intel_display *display = to_intel_display(&sdvo->base); 2692 const struct sdvo_device_mapping *my_mapping, *other_mapping; 2693 2694 if (sdvo->base.port == PORT_B) { 2695 my_mapping = &display->vbt.sdvo_mappings[0]; 2696 other_mapping = &display->vbt.sdvo_mappings[1]; 2697 } else { 2698 my_mapping = &display->vbt.sdvo_mappings[1]; 2699 other_mapping = &display->vbt.sdvo_mappings[0]; 2700 } 2701 2702 /* If the BIOS described our SDVO device, take advantage of it. */ 2703 if (my_mapping->target_addr) 2704 return my_mapping->target_addr; 2705 2706 /* 2707 * If the BIOS only described a different SDVO device, use the 2708 * address that it isn't using. 2709 */ 2710 if (other_mapping->target_addr) { 2711 if (other_mapping->target_addr == 0x70) 2712 return 0x72; 2713 else 2714 return 0x70; 2715 } 2716 2717 /* 2718 * No SDVO device info is found for another DVO port, 2719 * so use mapping assumption we had before BIOS parsing. 2720 */ 2721 if (sdvo->base.port == PORT_B) 2722 return 0x70; 2723 else 2724 return 0x72; 2725 } 2726 2727 static int 2728 intel_sdvo_init_ddc_proxy(struct intel_sdvo_ddc *ddc, 2729 struct intel_sdvo *sdvo, int bit); 2730 2731 static int 2732 intel_sdvo_connector_init(struct intel_sdvo_connector *connector, 2733 struct intel_sdvo *encoder) 2734 { 2735 struct intel_display *display = to_intel_display(&encoder->base); 2736 struct intel_sdvo_ddc *ddc = NULL; 2737 int ret; 2738 2739 if (HAS_DDC(connector)) 2740 ddc = intel_sdvo_select_ddc_bus(encoder, connector); 2741 2742 ret = drm_connector_init_with_ddc(encoder->base.base.dev, 2743 &connector->base.base, 2744 &intel_sdvo_connector_funcs, 2745 connector->base.base.connector_type, 2746 ddc ? &ddc->ddc : NULL); 2747 if (ret < 0) 2748 return ret; 2749 2750 drm_connector_helper_add(&connector->base.base, 2751 &intel_sdvo_connector_helper_funcs); 2752 2753 connector->base.base.display_info.subpixel_order = SubPixelHorizontalRGB; 2754 connector->base.base.interlace_allowed = true; 2755 connector->base.get_hw_state = intel_sdvo_connector_get_hw_state; 2756 2757 intel_connector_attach_encoder(&connector->base, &encoder->base); 2758 2759 if (ddc) 2760 drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s] using %s\n", 2761 connector->base.base.base.id, connector->base.base.name, 2762 ddc->ddc.name); 2763 2764 return 0; 2765 } 2766 2767 static void 2768 intel_sdvo_add_hdmi_properties(struct intel_sdvo *intel_sdvo, 2769 struct intel_sdvo_connector *connector) 2770 { 2771 intel_attach_force_audio_property(&connector->base.base); 2772 if (intel_sdvo->colorimetry_cap & SDVO_COLORIMETRY_RGB220) 2773 intel_attach_broadcast_rgb_property(&connector->base.base); 2774 intel_attach_aspect_ratio_property(&connector->base.base); 2775 } 2776 2777 static struct intel_sdvo_connector *intel_sdvo_connector_alloc(void) 2778 { 2779 struct intel_sdvo_connector *sdvo_connector; 2780 struct intel_sdvo_connector_state *conn_state; 2781 2782 sdvo_connector = kzalloc_obj(*sdvo_connector); 2783 if (!sdvo_connector) 2784 return NULL; 2785 2786 conn_state = kzalloc_obj(*conn_state); 2787 if (!conn_state) { 2788 kfree(sdvo_connector); 2789 return NULL; 2790 } 2791 2792 __drm_atomic_helper_connector_reset(&sdvo_connector->base.base, 2793 &conn_state->base.base); 2794 2795 intel_panel_init_alloc(&sdvo_connector->base); 2796 2797 return sdvo_connector; 2798 } 2799 2800 static bool 2801 intel_sdvo_dvi_init(struct intel_sdvo *intel_sdvo, u16 type) 2802 { 2803 struct intel_display *display = to_intel_display(&intel_sdvo->base); 2804 struct drm_encoder *encoder = &intel_sdvo->base.base; 2805 struct drm_connector *connector; 2806 struct intel_encoder *intel_encoder = to_intel_encoder(encoder); 2807 struct intel_connector *intel_connector; 2808 struct intel_sdvo_connector *intel_sdvo_connector; 2809 2810 drm_dbg_kms(display->drm, "initialising DVI type 0x%x\n", type); 2811 2812 intel_sdvo_connector = intel_sdvo_connector_alloc(); 2813 if (!intel_sdvo_connector) 2814 return false; 2815 2816 intel_sdvo_connector->output_flag = type; 2817 2818 intel_connector = &intel_sdvo_connector->base; 2819 connector = &intel_connector->base; 2820 if (intel_sdvo_get_hotplug_support(intel_sdvo) & 2821 intel_sdvo_connector->output_flag) { 2822 intel_sdvo->hotplug_active |= intel_sdvo_connector->output_flag; 2823 /* 2824 * Some SDVO devices have one-shot hotplug interrupts. 2825 * Ensure that they get re-enabled when an interrupt happens. 2826 */ 2827 intel_connector->polled = DRM_CONNECTOR_POLL_HPD; 2828 intel_encoder->hotplug = intel_sdvo_hotplug; 2829 intel_sdvo_enable_hotplug(intel_encoder); 2830 } else { 2831 intel_connector->polled = DRM_CONNECTOR_POLL_CONNECT | DRM_CONNECTOR_POLL_DISCONNECT; 2832 } 2833 intel_connector->base.polled = intel_connector->polled; 2834 encoder->encoder_type = DRM_MODE_ENCODER_TMDS; 2835 connector->connector_type = DRM_MODE_CONNECTOR_DVID; 2836 2837 if (intel_sdvo_is_hdmi_connector(intel_sdvo)) { 2838 connector->connector_type = DRM_MODE_CONNECTOR_HDMIA; 2839 intel_sdvo_connector->is_hdmi = true; 2840 } 2841 2842 if (intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo) < 0) { 2843 kfree(intel_sdvo_connector); 2844 return false; 2845 } 2846 2847 if (intel_sdvo_connector->is_hdmi) 2848 intel_sdvo_add_hdmi_properties(intel_sdvo, intel_sdvo_connector); 2849 2850 return true; 2851 } 2852 2853 static bool 2854 intel_sdvo_tv_init(struct intel_sdvo *intel_sdvo, u16 type) 2855 { 2856 struct intel_display *display = to_intel_display(&intel_sdvo->base); 2857 struct drm_encoder *encoder = &intel_sdvo->base.base; 2858 struct drm_connector *connector; 2859 struct intel_connector *intel_connector; 2860 struct intel_sdvo_connector *intel_sdvo_connector; 2861 2862 drm_dbg_kms(display->drm, "initialising TV type 0x%x\n", type); 2863 2864 intel_sdvo_connector = intel_sdvo_connector_alloc(); 2865 if (!intel_sdvo_connector) 2866 return false; 2867 2868 intel_connector = &intel_sdvo_connector->base; 2869 connector = &intel_connector->base; 2870 encoder->encoder_type = DRM_MODE_ENCODER_TVDAC; 2871 connector->connector_type = DRM_MODE_CONNECTOR_SVIDEO; 2872 2873 intel_sdvo_connector->output_flag = type; 2874 2875 if (intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo) < 0) { 2876 kfree(intel_sdvo_connector); 2877 return false; 2878 } 2879 2880 if (!intel_sdvo_tv_create_property(intel_sdvo, intel_sdvo_connector, type)) 2881 goto err; 2882 2883 if (!intel_sdvo_create_enhance_property(intel_sdvo, intel_sdvo_connector)) 2884 goto err; 2885 2886 return true; 2887 2888 err: 2889 intel_connector_destroy(connector); 2890 return false; 2891 } 2892 2893 static bool 2894 intel_sdvo_analog_init(struct intel_sdvo *intel_sdvo, u16 type) 2895 { 2896 struct intel_display *display = to_intel_display(&intel_sdvo->base); 2897 struct drm_encoder *encoder = &intel_sdvo->base.base; 2898 struct drm_connector *connector; 2899 struct intel_connector *intel_connector; 2900 struct intel_sdvo_connector *intel_sdvo_connector; 2901 2902 drm_dbg_kms(display->drm, "initialising analog type 0x%x\n", type); 2903 2904 intel_sdvo_connector = intel_sdvo_connector_alloc(); 2905 if (!intel_sdvo_connector) 2906 return false; 2907 2908 intel_connector = &intel_sdvo_connector->base; 2909 connector = &intel_connector->base; 2910 intel_connector->polled = DRM_CONNECTOR_POLL_CONNECT; 2911 intel_connector->base.polled = intel_connector->polled; 2912 encoder->encoder_type = DRM_MODE_ENCODER_DAC; 2913 connector->connector_type = DRM_MODE_CONNECTOR_VGA; 2914 2915 intel_sdvo_connector->output_flag = type; 2916 2917 if (intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo) < 0) { 2918 kfree(intel_sdvo_connector); 2919 return false; 2920 } 2921 2922 return true; 2923 } 2924 2925 static bool 2926 intel_sdvo_lvds_init(struct intel_sdvo *intel_sdvo, u16 type) 2927 { 2928 struct intel_display *display = to_intel_display(&intel_sdvo->base); 2929 struct drm_encoder *encoder = &intel_sdvo->base.base; 2930 struct drm_connector *connector; 2931 struct intel_connector *intel_connector; 2932 struct intel_sdvo_connector *intel_sdvo_connector; 2933 2934 drm_dbg_kms(display->drm, "initialising LVDS type 0x%x\n", type); 2935 2936 intel_sdvo_connector = intel_sdvo_connector_alloc(); 2937 if (!intel_sdvo_connector) 2938 return false; 2939 2940 intel_connector = &intel_sdvo_connector->base; 2941 connector = &intel_connector->base; 2942 encoder->encoder_type = DRM_MODE_ENCODER_LVDS; 2943 connector->connector_type = DRM_MODE_CONNECTOR_LVDS; 2944 2945 intel_sdvo_connector->output_flag = type; 2946 2947 if (intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo) < 0) { 2948 kfree(intel_sdvo_connector); 2949 return false; 2950 } 2951 2952 if (!intel_sdvo_create_enhance_property(intel_sdvo, intel_sdvo_connector)) 2953 goto err; 2954 2955 intel_bios_init_panel_late(display, &intel_connector->panel, NULL, NULL); 2956 2957 /* 2958 * Fetch modes from VBT. For SDVO prefer the VBT mode since some 2959 * SDVO->LVDS transcoders can't cope with the EDID mode. 2960 */ 2961 intel_panel_add_vbt_sdvo_fixed_mode(intel_connector); 2962 2963 if (!intel_panel_preferred_fixed_mode(intel_connector)) { 2964 mutex_lock(&display->drm->mode_config.mutex); 2965 2966 intel_ddc_get_modes(connector, connector->ddc); 2967 intel_panel_add_edid_fixed_modes(intel_connector, false); 2968 2969 mutex_unlock(&display->drm->mode_config.mutex); 2970 } 2971 2972 intel_panel_init(intel_connector, NULL); 2973 2974 if (!intel_panel_preferred_fixed_mode(intel_connector)) 2975 goto err; 2976 2977 return true; 2978 2979 err: 2980 intel_connector_destroy(connector); 2981 return false; 2982 } 2983 2984 static u16 intel_sdvo_filter_output_flags(u16 flags) 2985 { 2986 flags &= SDVO_OUTPUT_MASK; 2987 2988 /* SDVO requires XXX1 function may not exist unless it has XXX0 function.*/ 2989 if (!(flags & SDVO_OUTPUT_TMDS0)) 2990 flags &= ~SDVO_OUTPUT_TMDS1; 2991 2992 if (!(flags & SDVO_OUTPUT_RGB0)) 2993 flags &= ~SDVO_OUTPUT_RGB1; 2994 2995 if (!(flags & SDVO_OUTPUT_LVDS0)) 2996 flags &= ~SDVO_OUTPUT_LVDS1; 2997 2998 return flags; 2999 } 3000 3001 static bool intel_sdvo_output_init(struct intel_sdvo *sdvo, u16 type) 3002 { 3003 if (type & SDVO_TMDS_MASK) 3004 return intel_sdvo_dvi_init(sdvo, type); 3005 else if (type & SDVO_TV_MASK) 3006 return intel_sdvo_tv_init(sdvo, type); 3007 else if (type & SDVO_RGB_MASK) 3008 return intel_sdvo_analog_init(sdvo, type); 3009 else if (type & SDVO_LVDS_MASK) 3010 return intel_sdvo_lvds_init(sdvo, type); 3011 else 3012 return false; 3013 } 3014 3015 static bool 3016 intel_sdvo_output_setup(struct intel_sdvo *intel_sdvo) 3017 { 3018 struct intel_display *display = to_intel_display(&intel_sdvo->base); 3019 static const u16 probe_order[] = { 3020 SDVO_OUTPUT_TMDS0, 3021 SDVO_OUTPUT_TMDS1, 3022 /* TV has no XXX1 function block */ 3023 SDVO_OUTPUT_SVID0, 3024 SDVO_OUTPUT_CVBS0, 3025 SDVO_OUTPUT_YPRPB0, 3026 SDVO_OUTPUT_RGB0, 3027 SDVO_OUTPUT_RGB1, 3028 SDVO_OUTPUT_LVDS0, 3029 SDVO_OUTPUT_LVDS1, 3030 }; 3031 u16 flags; 3032 int i; 3033 3034 flags = intel_sdvo_filter_output_flags(intel_sdvo->caps.output_flags); 3035 3036 if (flags == 0) { 3037 drm_dbg_kms(display->drm, 3038 "%s: Unknown SDVO output type (0x%04x)\n", 3039 SDVO_NAME(intel_sdvo), intel_sdvo->caps.output_flags); 3040 return false; 3041 } 3042 3043 for (i = 0; i < ARRAY_SIZE(probe_order); i++) { 3044 u16 type = flags & probe_order[i]; 3045 3046 if (!type) 3047 continue; 3048 3049 if (!intel_sdvo_output_init(intel_sdvo, type)) 3050 return false; 3051 } 3052 3053 intel_sdvo->base.pipe_mask = ~0; 3054 3055 return true; 3056 } 3057 3058 static void intel_sdvo_output_cleanup(struct intel_sdvo *intel_sdvo) 3059 { 3060 struct intel_display *display = to_intel_display(&intel_sdvo->base); 3061 struct drm_connector *connector, *tmp; 3062 3063 list_for_each_entry_safe(connector, tmp, 3064 &display->drm->mode_config.connector_list, head) { 3065 if (intel_attached_encoder(to_intel_connector(connector)) == &intel_sdvo->base) { 3066 drm_connector_unregister(connector); 3067 intel_connector_destroy(connector); 3068 } 3069 } 3070 } 3071 3072 static bool intel_sdvo_tv_create_property(struct intel_sdvo *intel_sdvo, 3073 struct intel_sdvo_connector *intel_sdvo_connector, 3074 int type) 3075 { 3076 struct intel_display *display = to_intel_display(&intel_sdvo->base); 3077 struct intel_sdvo_tv_format format; 3078 u32 format_map, i; 3079 3080 if (!intel_sdvo_set_target_output(intel_sdvo, type)) 3081 return false; 3082 3083 BUILD_BUG_ON(sizeof(format) != 6); 3084 if (!intel_sdvo_get_value(intel_sdvo, 3085 SDVO_CMD_GET_SUPPORTED_TV_FORMATS, 3086 &format, sizeof(format))) 3087 return false; 3088 3089 memcpy(&format_map, &format, min(sizeof(format_map), sizeof(format))); 3090 3091 if (format_map == 0) 3092 return false; 3093 3094 intel_sdvo_connector->format_supported_num = 0; 3095 for (i = 0 ; i < TV_FORMAT_NUM; i++) 3096 if (format_map & (1 << i)) 3097 intel_sdvo_connector->tv_format_supported[intel_sdvo_connector->format_supported_num++] = i; 3098 3099 3100 intel_sdvo_connector->tv_format = 3101 drm_property_create(display->drm, DRM_MODE_PROP_ENUM, 3102 "mode", intel_sdvo_connector->format_supported_num); 3103 if (!intel_sdvo_connector->tv_format) 3104 return false; 3105 3106 for (i = 0; i < intel_sdvo_connector->format_supported_num; i++) 3107 drm_property_add_enum(intel_sdvo_connector->tv_format, i, 3108 tv_format_names[intel_sdvo_connector->tv_format_supported[i]]); 3109 3110 intel_sdvo_connector->base.base.state->tv.legacy_mode = intel_sdvo_connector->tv_format_supported[0]; 3111 drm_object_attach_property(&intel_sdvo_connector->base.base.base, 3112 intel_sdvo_connector->tv_format, 0); 3113 return true; 3114 3115 } 3116 3117 #define _ENHANCEMENT(state_assignment, name, NAME) do { \ 3118 if (enhancements.name) { \ 3119 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_MAX_##NAME, &data_value, 4) || \ 3120 !intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_##NAME, &response, 2)) \ 3121 return false; \ 3122 intel_sdvo_connector->name = \ 3123 drm_property_create_range(display->drm, 0, #name, 0, data_value[0]); \ 3124 if (!intel_sdvo_connector->name) return false; \ 3125 state_assignment = response; \ 3126 drm_object_attach_property(&connector->base, \ 3127 intel_sdvo_connector->name, 0); \ 3128 drm_dbg_kms(display->drm, #name ": max %d, default %d, current %d\n", \ 3129 data_value[0], data_value[1], response); \ 3130 } \ 3131 } while (0) 3132 3133 #define ENHANCEMENT(state, name, NAME) _ENHANCEMENT((state)->name, name, NAME) 3134 3135 static bool 3136 intel_sdvo_create_enhance_property_tv(struct intel_sdvo *intel_sdvo, 3137 struct intel_sdvo_connector *intel_sdvo_connector, 3138 struct intel_sdvo_enhancements_reply enhancements) 3139 { 3140 struct intel_display *display = to_intel_display(&intel_sdvo->base); 3141 struct drm_connector *connector = &intel_sdvo_connector->base.base; 3142 struct drm_connector_state *conn_state = connector->state; 3143 struct intel_sdvo_connector_state *sdvo_state = 3144 to_intel_sdvo_connector_state(conn_state); 3145 u16 response, data_value[2]; 3146 3147 /* when horizontal overscan is supported, Add the left/right property */ 3148 if (enhancements.overscan_h) { 3149 if (!intel_sdvo_get_value(intel_sdvo, 3150 SDVO_CMD_GET_MAX_OVERSCAN_H, 3151 &data_value, 4)) 3152 return false; 3153 3154 if (!intel_sdvo_get_value(intel_sdvo, 3155 SDVO_CMD_GET_OVERSCAN_H, 3156 &response, 2)) 3157 return false; 3158 3159 sdvo_state->tv.overscan_h = response; 3160 3161 intel_sdvo_connector->max_hscan = data_value[0]; 3162 intel_sdvo_connector->left = 3163 drm_property_create_range(display->drm, 0, "left_margin", 0, data_value[0]); 3164 if (!intel_sdvo_connector->left) 3165 return false; 3166 3167 drm_object_attach_property(&connector->base, 3168 intel_sdvo_connector->left, 0); 3169 3170 intel_sdvo_connector->right = 3171 drm_property_create_range(display->drm, 0, "right_margin", 0, data_value[0]); 3172 if (!intel_sdvo_connector->right) 3173 return false; 3174 3175 drm_object_attach_property(&connector->base, 3176 intel_sdvo_connector->right, 0); 3177 drm_dbg_kms(display->drm, "h_overscan: max %d, default %d, current %d\n", 3178 data_value[0], data_value[1], response); 3179 } 3180 3181 if (enhancements.overscan_v) { 3182 if (!intel_sdvo_get_value(intel_sdvo, 3183 SDVO_CMD_GET_MAX_OVERSCAN_V, 3184 &data_value, 4)) 3185 return false; 3186 3187 if (!intel_sdvo_get_value(intel_sdvo, 3188 SDVO_CMD_GET_OVERSCAN_V, 3189 &response, 2)) 3190 return false; 3191 3192 sdvo_state->tv.overscan_v = response; 3193 3194 intel_sdvo_connector->max_vscan = data_value[0]; 3195 intel_sdvo_connector->top = 3196 drm_property_create_range(display->drm, 0, 3197 "top_margin", 0, data_value[0]); 3198 if (!intel_sdvo_connector->top) 3199 return false; 3200 3201 drm_object_attach_property(&connector->base, 3202 intel_sdvo_connector->top, 0); 3203 3204 intel_sdvo_connector->bottom = 3205 drm_property_create_range(display->drm, 0, 3206 "bottom_margin", 0, data_value[0]); 3207 if (!intel_sdvo_connector->bottom) 3208 return false; 3209 3210 drm_object_attach_property(&connector->base, 3211 intel_sdvo_connector->bottom, 0); 3212 drm_dbg_kms(display->drm, "v_overscan: max %d, default %d, current %d\n", 3213 data_value[0], data_value[1], response); 3214 } 3215 3216 ENHANCEMENT(&sdvo_state->tv, hpos, HPOS); 3217 ENHANCEMENT(&sdvo_state->tv, vpos, VPOS); 3218 ENHANCEMENT(&conn_state->tv, saturation, SATURATION); 3219 ENHANCEMENT(&conn_state->tv, contrast, CONTRAST); 3220 ENHANCEMENT(&conn_state->tv, hue, HUE); 3221 ENHANCEMENT(&conn_state->tv, brightness, BRIGHTNESS); 3222 ENHANCEMENT(&sdvo_state->tv, sharpness, SHARPNESS); 3223 ENHANCEMENT(&sdvo_state->tv, flicker_filter, FLICKER_FILTER); 3224 ENHANCEMENT(&sdvo_state->tv, flicker_filter_adaptive, FLICKER_FILTER_ADAPTIVE); 3225 ENHANCEMENT(&sdvo_state->tv, flicker_filter_2d, FLICKER_FILTER_2D); 3226 _ENHANCEMENT(sdvo_state->tv.chroma_filter, tv_chroma_filter, TV_CHROMA_FILTER); 3227 _ENHANCEMENT(sdvo_state->tv.luma_filter, tv_luma_filter, TV_LUMA_FILTER); 3228 3229 if (enhancements.dot_crawl) { 3230 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_DOT_CRAWL, &response, 2)) 3231 return false; 3232 3233 sdvo_state->tv.dot_crawl = response & 0x1; 3234 intel_sdvo_connector->dot_crawl = 3235 drm_property_create_range(display->drm, 0, "dot_crawl", 0, 1); 3236 if (!intel_sdvo_connector->dot_crawl) 3237 return false; 3238 3239 drm_object_attach_property(&connector->base, 3240 intel_sdvo_connector->dot_crawl, 0); 3241 drm_dbg_kms(display->drm, "dot crawl: current %d\n", response); 3242 } 3243 3244 return true; 3245 } 3246 3247 static bool 3248 intel_sdvo_create_enhance_property_lvds(struct intel_sdvo *intel_sdvo, 3249 struct intel_sdvo_connector *intel_sdvo_connector, 3250 struct intel_sdvo_enhancements_reply enhancements) 3251 { 3252 struct intel_display *display = to_intel_display(&intel_sdvo->base); 3253 struct drm_connector *connector = &intel_sdvo_connector->base.base; 3254 u16 response, data_value[2]; 3255 3256 ENHANCEMENT(&connector->state->tv, brightness, BRIGHTNESS); 3257 3258 return true; 3259 } 3260 #undef ENHANCEMENT 3261 #undef _ENHANCEMENT 3262 3263 static bool intel_sdvo_create_enhance_property(struct intel_sdvo *intel_sdvo, 3264 struct intel_sdvo_connector *intel_sdvo_connector) 3265 { 3266 struct intel_display *display = to_intel_display(&intel_sdvo->base); 3267 union { 3268 struct intel_sdvo_enhancements_reply reply; 3269 u16 response; 3270 } enhancements; 3271 3272 BUILD_BUG_ON(sizeof(enhancements) != 2); 3273 3274 if (!intel_sdvo_get_value(intel_sdvo, 3275 SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS, 3276 &enhancements, sizeof(enhancements)) || 3277 enhancements.response == 0) { 3278 drm_dbg_kms(display->drm, "No enhancement is supported\n"); 3279 return true; 3280 } 3281 3282 if (IS_TV(intel_sdvo_connector)) 3283 return intel_sdvo_create_enhance_property_tv(intel_sdvo, intel_sdvo_connector, enhancements.reply); 3284 else if (IS_LVDS(intel_sdvo_connector)) 3285 return intel_sdvo_create_enhance_property_lvds(intel_sdvo, intel_sdvo_connector, enhancements.reply); 3286 else 3287 return true; 3288 } 3289 3290 static int intel_sdvo_ddc_proxy_xfer(struct i2c_adapter *adapter, 3291 struct i2c_msg *msgs, 3292 int num) 3293 { 3294 struct intel_sdvo_ddc *ddc = adapter->algo_data; 3295 struct intel_sdvo *sdvo = ddc->sdvo; 3296 3297 if (!__intel_sdvo_set_control_bus_switch(sdvo, 1 << ddc->ddc_bus)) 3298 return -EIO; 3299 3300 return sdvo->i2c->algo->master_xfer(sdvo->i2c, msgs, num); 3301 } 3302 3303 static u32 intel_sdvo_ddc_proxy_func(struct i2c_adapter *adapter) 3304 { 3305 struct intel_sdvo_ddc *ddc = adapter->algo_data; 3306 struct intel_sdvo *sdvo = ddc->sdvo; 3307 3308 return sdvo->i2c->algo->functionality(sdvo->i2c); 3309 } 3310 3311 static const struct i2c_algorithm intel_sdvo_ddc_proxy = { 3312 .master_xfer = intel_sdvo_ddc_proxy_xfer, 3313 .functionality = intel_sdvo_ddc_proxy_func 3314 }; 3315 3316 static void proxy_lock_bus(struct i2c_adapter *adapter, 3317 unsigned int flags) 3318 { 3319 struct intel_sdvo_ddc *ddc = adapter->algo_data; 3320 struct intel_sdvo *sdvo = ddc->sdvo; 3321 3322 i2c_lock_bus(sdvo->i2c, flags); 3323 } 3324 3325 static int proxy_trylock_bus(struct i2c_adapter *adapter, 3326 unsigned int flags) 3327 { 3328 struct intel_sdvo_ddc *ddc = adapter->algo_data; 3329 struct intel_sdvo *sdvo = ddc->sdvo; 3330 3331 return i2c_trylock_bus(sdvo->i2c, flags); 3332 } 3333 3334 static void proxy_unlock_bus(struct i2c_adapter *adapter, 3335 unsigned int flags) 3336 { 3337 struct intel_sdvo_ddc *ddc = adapter->algo_data; 3338 struct intel_sdvo *sdvo = ddc->sdvo; 3339 3340 i2c_unlock_bus(sdvo->i2c, flags); 3341 } 3342 3343 static const struct i2c_lock_operations proxy_lock_ops = { 3344 .lock_bus = proxy_lock_bus, 3345 .trylock_bus = proxy_trylock_bus, 3346 .unlock_bus = proxy_unlock_bus, 3347 }; 3348 3349 static int 3350 intel_sdvo_init_ddc_proxy(struct intel_sdvo_ddc *ddc, 3351 struct intel_sdvo *sdvo, int ddc_bus) 3352 { 3353 struct intel_display *display = to_intel_display(&sdvo->base); 3354 struct pci_dev *pdev = to_pci_dev(display->drm->dev); 3355 3356 ddc->sdvo = sdvo; 3357 ddc->ddc_bus = ddc_bus; 3358 3359 ddc->ddc.owner = THIS_MODULE; 3360 snprintf(ddc->ddc.name, I2C_NAME_SIZE, "SDVO %c DDC%d", 3361 port_name(sdvo->base.port), ddc_bus); 3362 ddc->ddc.dev.parent = &pdev->dev; 3363 ddc->ddc.algo_data = ddc; 3364 ddc->ddc.algo = &intel_sdvo_ddc_proxy; 3365 ddc->ddc.lock_ops = &proxy_lock_ops; 3366 3367 return i2c_add_adapter(&ddc->ddc); 3368 } 3369 3370 static bool is_sdvo_port_valid(struct intel_display *display, enum port port) 3371 { 3372 if (HAS_PCH_SPLIT(display)) 3373 return port == PORT_B; 3374 else 3375 return port == PORT_B || port == PORT_C; 3376 } 3377 3378 static bool assert_sdvo_port_valid(struct intel_display *display, enum port port) 3379 { 3380 return !drm_WARN(display->drm, !is_sdvo_port_valid(display, port), 3381 "Platform does not support SDVO %c\n", port_name(port)); 3382 } 3383 3384 bool intel_sdvo_init(struct intel_display *display, 3385 intel_reg_t sdvo_reg, enum port port) 3386 { 3387 struct intel_encoder *intel_encoder; 3388 struct intel_sdvo *intel_sdvo; 3389 int i; 3390 3391 if (!assert_port_valid(display, port)) 3392 return false; 3393 3394 if (!assert_sdvo_port_valid(display, port)) 3395 return false; 3396 3397 intel_sdvo = kzalloc_obj(*intel_sdvo); 3398 if (!intel_sdvo) 3399 return false; 3400 3401 /* encoder type will be decided later */ 3402 intel_encoder = &intel_sdvo->base; 3403 intel_encoder->type = INTEL_OUTPUT_SDVO; 3404 intel_encoder->power_domain = POWER_DOMAIN_PORT_OTHER; 3405 intel_encoder->port = port; 3406 3407 drm_encoder_init(display->drm, &intel_encoder->base, 3408 &intel_sdvo_enc_funcs, 0, 3409 "SDVO %c", port_name(port)); 3410 3411 intel_sdvo->sdvo_reg = sdvo_reg; 3412 intel_sdvo->target_addr = intel_sdvo_get_target_addr(intel_sdvo) >> 1; 3413 3414 intel_sdvo_select_i2c_bus(intel_sdvo); 3415 3416 /* Read the regs to test if we can talk to the device */ 3417 for (i = 0; i < 0x40; i++) { 3418 u8 byte; 3419 3420 if (!intel_sdvo_read_byte(intel_sdvo, i, &byte)) { 3421 drm_dbg_kms(display->drm, 3422 "No SDVO device found on %s\n", 3423 SDVO_NAME(intel_sdvo)); 3424 goto err; 3425 } 3426 } 3427 3428 intel_encoder->compute_config = intel_sdvo_compute_config; 3429 if (HAS_PCH_SPLIT(display)) { 3430 intel_encoder->disable = pch_disable_sdvo; 3431 intel_encoder->post_disable = pch_post_disable_sdvo; 3432 } else { 3433 intel_encoder->disable = intel_disable_sdvo; 3434 } 3435 intel_encoder->pre_enable = intel_sdvo_pre_enable; 3436 intel_encoder->enable = intel_enable_sdvo; 3437 intel_encoder->audio_enable = intel_sdvo_enable_audio; 3438 intel_encoder->audio_disable = intel_sdvo_disable_audio; 3439 intel_encoder->get_hw_state = intel_sdvo_get_hw_state; 3440 intel_encoder->get_config = intel_sdvo_get_config; 3441 3442 /* In default case sdvo lvds is false */ 3443 if (!intel_sdvo_get_capabilities(intel_sdvo, &intel_sdvo->caps)) 3444 goto err; 3445 3446 intel_sdvo->colorimetry_cap = 3447 intel_sdvo_get_colorimetry_cap(intel_sdvo); 3448 3449 for (i = 0; i < ARRAY_SIZE(intel_sdvo->ddc); i++) { 3450 int ret; 3451 3452 ret = intel_sdvo_init_ddc_proxy(&intel_sdvo->ddc[i], 3453 intel_sdvo, i + 1); 3454 if (ret) 3455 goto err; 3456 } 3457 3458 if (!intel_sdvo_output_setup(intel_sdvo)) { 3459 drm_dbg_kms(display->drm, 3460 "SDVO output failed to setup on %s\n", 3461 SDVO_NAME(intel_sdvo)); 3462 /* Output_setup can leave behind connectors! */ 3463 goto err_output; 3464 } 3465 3466 /* 3467 * Only enable the hotplug irq if we need it, to work around noisy 3468 * hotplug lines. 3469 */ 3470 if (intel_sdvo->hotplug_active) { 3471 if (intel_sdvo->base.port == PORT_B) 3472 intel_encoder->hpd_pin = HPD_SDVO_B; 3473 else 3474 intel_encoder->hpd_pin = HPD_SDVO_C; 3475 } 3476 3477 /* 3478 * Cloning SDVO with anything is often impossible, since the SDVO 3479 * encoder can request a special input timing mode. And even if that's 3480 * not the case we have evidence that cloning a plain unscaled mode with 3481 * VGA doesn't really work. Furthermore the cloning flags are way too 3482 * simplistic anyway to express such constraints, so just give up on 3483 * cloning for SDVO encoders. 3484 */ 3485 intel_sdvo->base.cloneable = 0; 3486 3487 /* Set the input timing to the screen. Assume always input 0. */ 3488 if (!intel_sdvo_set_target_input(intel_sdvo)) 3489 goto err_output; 3490 3491 if (!intel_sdvo_get_input_pixel_clock_range(intel_sdvo, 3492 &intel_sdvo->pixel_clock_min, 3493 &intel_sdvo->pixel_clock_max)) 3494 goto err_output; 3495 3496 drm_dbg_kms(display->drm, "%s device VID/DID: %02X:%02X.%02X, " 3497 "clock range %dMHz - %dMHz, " 3498 "num inputs: %d, " 3499 "output 1: %c, output 2: %c\n", 3500 SDVO_NAME(intel_sdvo), 3501 intel_sdvo->caps.vendor_id, intel_sdvo->caps.device_id, 3502 intel_sdvo->caps.device_rev_id, 3503 intel_sdvo->pixel_clock_min / 1000, 3504 intel_sdvo->pixel_clock_max / 1000, 3505 intel_sdvo->caps.sdvo_num_inputs, 3506 /* check currently supported outputs */ 3507 intel_sdvo->caps.output_flags & 3508 (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_RGB0 | 3509 SDVO_OUTPUT_LVDS0 | SDVO_OUTPUT_SVID0 | 3510 SDVO_OUTPUT_CVBS0 | SDVO_OUTPUT_YPRPB0) ? 'Y' : 'N', 3511 intel_sdvo->caps.output_flags & 3512 (SDVO_OUTPUT_TMDS1 | SDVO_OUTPUT_RGB1 | 3513 SDVO_OUTPUT_LVDS1) ? 'Y' : 'N'); 3514 return true; 3515 3516 err_output: 3517 intel_sdvo_output_cleanup(intel_sdvo); 3518 err: 3519 intel_sdvo_unselect_i2c_bus(intel_sdvo); 3520 intel_sdvo_encoder_destroy(&intel_encoder->base); 3521 3522 return false; 3523 } 3524