1 /* 2 * Copyright 2006 Dave Airlie <airlied@linux.ie> 3 * Copyright © 2006-2007 Intel Corporation 4 * Jesse Barnes <jesse.barnes@intel.com> 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice (including the next 14 * paragraph) shall be included in all copies or substantial portions of the 15 * Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 23 * DEALINGS IN THE SOFTWARE. 24 * 25 * Authors: 26 * Eric Anholt <eric@anholt.net> 27 */ 28 29 #include <linux/delay.h> 30 #include <linux/export.h> 31 #include <linux/i2c.h> 32 #include <linux/slab.h> 33 34 #include <drm/display/drm_hdmi_helper.h> 35 #include <drm/drm_atomic_helper.h> 36 #include <drm/drm_crtc.h> 37 #include <drm/drm_edid.h> 38 #include <drm/drm_eld.h> 39 #include <drm/drm_print.h> 40 #include <drm/drm_probe_helper.h> 41 42 #include "intel_atomic.h" 43 #include "intel_audio.h" 44 #include "intel_connector.h" 45 #include "intel_crtc.h" 46 #include "intel_de.h" 47 #include "intel_display_driver.h" 48 #include "intel_display_regs.h" 49 #include "intel_display_types.h" 50 #include "intel_fdi.h" 51 #include "intel_fifo_underrun.h" 52 #include "intel_gmbus.h" 53 #include "intel_hdmi.h" 54 #include "intel_hotplug.h" 55 #include "intel_panel.h" 56 #include "intel_sdvo.h" 57 #include "intel_sdvo_regs.h" 58 59 #define SDVO_TMDS_MASK (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_TMDS1) 60 #define SDVO_RGB_MASK (SDVO_OUTPUT_RGB0 | SDVO_OUTPUT_RGB1) 61 #define SDVO_LVDS_MASK (SDVO_OUTPUT_LVDS0 | SDVO_OUTPUT_LVDS1) 62 #define SDVO_TV_MASK (SDVO_OUTPUT_CVBS0 | SDVO_OUTPUT_SVID0 | SDVO_OUTPUT_YPRPB0) 63 64 #define SDVO_OUTPUT_MASK (SDVO_TMDS_MASK | SDVO_RGB_MASK | SDVO_LVDS_MASK | SDVO_TV_MASK) 65 66 #define IS_TV(c) ((c)->output_flag & SDVO_TV_MASK) 67 #define IS_TMDS(c) ((c)->output_flag & SDVO_TMDS_MASK) 68 #define IS_LVDS(c) ((c)->output_flag & SDVO_LVDS_MASK) 69 #define IS_TV_OR_LVDS(c) ((c)->output_flag & (SDVO_TV_MASK | SDVO_LVDS_MASK)) 70 #define IS_DIGITAL(c) ((c)->output_flag & (SDVO_TMDS_MASK | SDVO_LVDS_MASK)) 71 72 #define HAS_DDC(c) ((c)->output_flag & (SDVO_RGB_MASK | SDVO_TMDS_MASK | \ 73 SDVO_LVDS_MASK)) 74 75 static const char * const tv_format_names[] = { 76 "NTSC_M" , "NTSC_J" , "NTSC_443", 77 "PAL_B" , "PAL_D" , "PAL_G" , 78 "PAL_H" , "PAL_I" , "PAL_M" , 79 "PAL_N" , "PAL_NC" , "PAL_60" , 80 "SECAM_B" , "SECAM_D" , "SECAM_G" , 81 "SECAM_K" , "SECAM_K1", "SECAM_L" , 82 "SECAM_60" 83 }; 84 85 #define TV_FORMAT_NUM ARRAY_SIZE(tv_format_names) 86 87 struct intel_sdvo; 88 89 struct intel_sdvo_ddc { 90 struct i2c_adapter ddc; 91 struct intel_sdvo *sdvo; 92 u8 ddc_bus; 93 }; 94 95 struct intel_sdvo { 96 struct intel_encoder base; 97 98 struct i2c_adapter *i2c; 99 u8 target_addr; 100 101 struct intel_sdvo_ddc ddc[3]; 102 103 /* Register for the SDVO device: SDVOB or SDVOC */ 104 i915_reg_t sdvo_reg; 105 106 /* 107 * Capabilities of the SDVO device returned by 108 * intel_sdvo_get_capabilities() 109 */ 110 struct intel_sdvo_caps caps; 111 112 u8 colorimetry_cap; 113 114 /* Pixel clock limitations reported by the SDVO device, in kHz */ 115 int pixel_clock_min, pixel_clock_max; 116 117 /* 118 * Hotplug activation bits for this device 119 */ 120 u16 hotplug_active; 121 122 /* 123 * the sdvo flag gets lost in round trip: dtd->adjusted_mode->dtd 124 */ 125 u8 dtd_sdvo_flags; 126 }; 127 128 struct intel_sdvo_connector { 129 struct intel_connector base; 130 131 /* Mark the type of connector */ 132 u16 output_flag; 133 134 /* This contains all current supported TV format */ 135 u8 tv_format_supported[TV_FORMAT_NUM]; 136 int format_supported_num; 137 struct drm_property *tv_format; 138 139 /* add the property for the SDVO-TV */ 140 struct drm_property *left; 141 struct drm_property *right; 142 struct drm_property *top; 143 struct drm_property *bottom; 144 struct drm_property *hpos; 145 struct drm_property *vpos; 146 struct drm_property *contrast; 147 struct drm_property *saturation; 148 struct drm_property *hue; 149 struct drm_property *sharpness; 150 struct drm_property *flicker_filter; 151 struct drm_property *flicker_filter_adaptive; 152 struct drm_property *flicker_filter_2d; 153 struct drm_property *tv_chroma_filter; 154 struct drm_property *tv_luma_filter; 155 struct drm_property *dot_crawl; 156 157 /* add the property for the SDVO-TV/LVDS */ 158 struct drm_property *brightness; 159 160 /* this is to get the range of margin.*/ 161 u32 max_hscan, max_vscan; 162 163 /** 164 * This is set if we treat the device as HDMI, instead of DVI. 165 */ 166 bool is_hdmi; 167 }; 168 169 struct intel_sdvo_connector_state { 170 /* base.base: tv.saturation/contrast/hue/brightness */ 171 struct intel_digital_connector_state base; 172 173 struct { 174 unsigned overscan_h, overscan_v, hpos, vpos, sharpness; 175 unsigned flicker_filter, flicker_filter_2d, flicker_filter_adaptive; 176 unsigned chroma_filter, luma_filter, dot_crawl; 177 } tv; 178 }; 179 180 static struct intel_sdvo *to_sdvo(struct intel_encoder *encoder) 181 { 182 return container_of(encoder, struct intel_sdvo, base); 183 } 184 185 static struct intel_sdvo *intel_attached_sdvo(struct intel_connector *connector) 186 { 187 return to_sdvo(intel_attached_encoder(connector)); 188 } 189 190 static struct intel_sdvo_connector * 191 to_intel_sdvo_connector(struct drm_connector *connector) 192 { 193 return container_of(connector, struct intel_sdvo_connector, base.base); 194 } 195 196 #define to_intel_sdvo_connector_state(conn_state) \ 197 container_of_const((conn_state), struct intel_sdvo_connector_state, base.base) 198 199 static bool 200 intel_sdvo_output_setup(struct intel_sdvo *intel_sdvo); 201 static bool 202 intel_sdvo_tv_create_property(struct intel_sdvo *intel_sdvo, 203 struct intel_sdvo_connector *intel_sdvo_connector, 204 int type); 205 static bool 206 intel_sdvo_create_enhance_property(struct intel_sdvo *intel_sdvo, 207 struct intel_sdvo_connector *intel_sdvo_connector); 208 209 /* 210 * Writes the SDVOB or SDVOC with the given value, but always writes both 211 * SDVOB and SDVOC to work around apparent hardware issues (according to 212 * comments in the BIOS). 213 */ 214 static void intel_sdvo_write_sdvox(struct intel_sdvo *intel_sdvo, u32 val) 215 { 216 struct intel_display *display = to_intel_display(&intel_sdvo->base); 217 u32 bval = val, cval = val; 218 int i; 219 220 if (HAS_PCH_SPLIT(display)) { 221 intel_de_write(display, intel_sdvo->sdvo_reg, val); 222 intel_de_posting_read(display, intel_sdvo->sdvo_reg); 223 /* 224 * HW workaround, need to write this twice for issue 225 * that may result in first write getting masked. 226 */ 227 if (HAS_PCH_IBX(display)) { 228 intel_de_write(display, intel_sdvo->sdvo_reg, val); 229 intel_de_posting_read(display, intel_sdvo->sdvo_reg); 230 } 231 return; 232 } 233 234 if (intel_sdvo->base.port == PORT_B) 235 cval = intel_de_read(display, GEN3_SDVOC); 236 else 237 bval = intel_de_read(display, GEN3_SDVOB); 238 239 /* 240 * Write the registers twice for luck. Sometimes, 241 * writing them only once doesn't appear to 'stick'. 242 * The BIOS does this too. Yay, magic 243 */ 244 for (i = 0; i < 2; i++) { 245 intel_de_write(display, GEN3_SDVOB, bval); 246 intel_de_posting_read(display, GEN3_SDVOB); 247 248 intel_de_write(display, GEN3_SDVOC, cval); 249 intel_de_posting_read(display, GEN3_SDVOC); 250 } 251 } 252 253 static bool intel_sdvo_read_byte(struct intel_sdvo *intel_sdvo, u8 addr, u8 *ch) 254 { 255 struct intel_display *display = to_intel_display(&intel_sdvo->base); 256 struct i2c_msg msgs[] = { 257 { 258 .addr = intel_sdvo->target_addr, 259 .flags = 0, 260 .len = 1, 261 .buf = &addr, 262 }, 263 { 264 .addr = intel_sdvo->target_addr, 265 .flags = I2C_M_RD, 266 .len = 1, 267 .buf = ch, 268 } 269 }; 270 int ret; 271 272 if ((ret = i2c_transfer(intel_sdvo->i2c, msgs, 2)) == 2) 273 return true; 274 275 drm_dbg_kms(display->drm, "i2c transfer returned %d\n", ret); 276 return false; 277 } 278 279 #define SDVO_CMD_NAME_ENTRY(cmd_) { .cmd = SDVO_CMD_ ## cmd_, .name = #cmd_ } 280 281 /** Mapping of command numbers to names, for debug output */ 282 static const struct { 283 u8 cmd; 284 const char *name; 285 } __packed sdvo_cmd_names[] = { 286 SDVO_CMD_NAME_ENTRY(RESET), 287 SDVO_CMD_NAME_ENTRY(GET_DEVICE_CAPS), 288 SDVO_CMD_NAME_ENTRY(GET_FIRMWARE_REV), 289 SDVO_CMD_NAME_ENTRY(GET_TRAINED_INPUTS), 290 SDVO_CMD_NAME_ENTRY(GET_ACTIVE_OUTPUTS), 291 SDVO_CMD_NAME_ENTRY(SET_ACTIVE_OUTPUTS), 292 SDVO_CMD_NAME_ENTRY(GET_IN_OUT_MAP), 293 SDVO_CMD_NAME_ENTRY(SET_IN_OUT_MAP), 294 SDVO_CMD_NAME_ENTRY(GET_ATTACHED_DISPLAYS), 295 SDVO_CMD_NAME_ENTRY(GET_HOT_PLUG_SUPPORT), 296 SDVO_CMD_NAME_ENTRY(SET_ACTIVE_HOT_PLUG), 297 SDVO_CMD_NAME_ENTRY(GET_ACTIVE_HOT_PLUG), 298 SDVO_CMD_NAME_ENTRY(GET_INTERRUPT_EVENT_SOURCE), 299 SDVO_CMD_NAME_ENTRY(SET_TARGET_INPUT), 300 SDVO_CMD_NAME_ENTRY(SET_TARGET_OUTPUT), 301 SDVO_CMD_NAME_ENTRY(GET_INPUT_TIMINGS_PART1), 302 SDVO_CMD_NAME_ENTRY(GET_INPUT_TIMINGS_PART2), 303 SDVO_CMD_NAME_ENTRY(SET_INPUT_TIMINGS_PART1), 304 SDVO_CMD_NAME_ENTRY(SET_INPUT_TIMINGS_PART2), 305 SDVO_CMD_NAME_ENTRY(SET_OUTPUT_TIMINGS_PART1), 306 SDVO_CMD_NAME_ENTRY(SET_OUTPUT_TIMINGS_PART2), 307 SDVO_CMD_NAME_ENTRY(GET_OUTPUT_TIMINGS_PART1), 308 SDVO_CMD_NAME_ENTRY(GET_OUTPUT_TIMINGS_PART2), 309 SDVO_CMD_NAME_ENTRY(CREATE_PREFERRED_INPUT_TIMING), 310 SDVO_CMD_NAME_ENTRY(GET_PREFERRED_INPUT_TIMING_PART1), 311 SDVO_CMD_NAME_ENTRY(GET_PREFERRED_INPUT_TIMING_PART2), 312 SDVO_CMD_NAME_ENTRY(GET_INPUT_PIXEL_CLOCK_RANGE), 313 SDVO_CMD_NAME_ENTRY(GET_OUTPUT_PIXEL_CLOCK_RANGE), 314 SDVO_CMD_NAME_ENTRY(GET_SUPPORTED_CLOCK_RATE_MULTS), 315 SDVO_CMD_NAME_ENTRY(GET_CLOCK_RATE_MULT), 316 SDVO_CMD_NAME_ENTRY(SET_CLOCK_RATE_MULT), 317 SDVO_CMD_NAME_ENTRY(GET_SUPPORTED_TV_FORMATS), 318 SDVO_CMD_NAME_ENTRY(GET_TV_FORMAT), 319 SDVO_CMD_NAME_ENTRY(SET_TV_FORMAT), 320 SDVO_CMD_NAME_ENTRY(GET_SUPPORTED_POWER_STATES), 321 SDVO_CMD_NAME_ENTRY(GET_POWER_STATE), 322 SDVO_CMD_NAME_ENTRY(SET_ENCODER_POWER_STATE), 323 SDVO_CMD_NAME_ENTRY(SET_DISPLAY_POWER_STATE), 324 SDVO_CMD_NAME_ENTRY(SET_CONTROL_BUS_SWITCH), 325 SDVO_CMD_NAME_ENTRY(GET_SDTV_RESOLUTION_SUPPORT), 326 SDVO_CMD_NAME_ENTRY(GET_SCALED_HDTV_RESOLUTION_SUPPORT), 327 SDVO_CMD_NAME_ENTRY(GET_SUPPORTED_ENHANCEMENTS), 328 329 /* Add the op code for SDVO enhancements */ 330 SDVO_CMD_NAME_ENTRY(GET_MAX_HPOS), 331 SDVO_CMD_NAME_ENTRY(GET_HPOS), 332 SDVO_CMD_NAME_ENTRY(SET_HPOS), 333 SDVO_CMD_NAME_ENTRY(GET_MAX_VPOS), 334 SDVO_CMD_NAME_ENTRY(GET_VPOS), 335 SDVO_CMD_NAME_ENTRY(SET_VPOS), 336 SDVO_CMD_NAME_ENTRY(GET_MAX_SATURATION), 337 SDVO_CMD_NAME_ENTRY(GET_SATURATION), 338 SDVO_CMD_NAME_ENTRY(SET_SATURATION), 339 SDVO_CMD_NAME_ENTRY(GET_MAX_HUE), 340 SDVO_CMD_NAME_ENTRY(GET_HUE), 341 SDVO_CMD_NAME_ENTRY(SET_HUE), 342 SDVO_CMD_NAME_ENTRY(GET_MAX_CONTRAST), 343 SDVO_CMD_NAME_ENTRY(GET_CONTRAST), 344 SDVO_CMD_NAME_ENTRY(SET_CONTRAST), 345 SDVO_CMD_NAME_ENTRY(GET_MAX_BRIGHTNESS), 346 SDVO_CMD_NAME_ENTRY(GET_BRIGHTNESS), 347 SDVO_CMD_NAME_ENTRY(SET_BRIGHTNESS), 348 SDVO_CMD_NAME_ENTRY(GET_MAX_OVERSCAN_H), 349 SDVO_CMD_NAME_ENTRY(GET_OVERSCAN_H), 350 SDVO_CMD_NAME_ENTRY(SET_OVERSCAN_H), 351 SDVO_CMD_NAME_ENTRY(GET_MAX_OVERSCAN_V), 352 SDVO_CMD_NAME_ENTRY(GET_OVERSCAN_V), 353 SDVO_CMD_NAME_ENTRY(SET_OVERSCAN_V), 354 SDVO_CMD_NAME_ENTRY(GET_MAX_FLICKER_FILTER), 355 SDVO_CMD_NAME_ENTRY(GET_FLICKER_FILTER), 356 SDVO_CMD_NAME_ENTRY(SET_FLICKER_FILTER), 357 SDVO_CMD_NAME_ENTRY(GET_MAX_FLICKER_FILTER_ADAPTIVE), 358 SDVO_CMD_NAME_ENTRY(GET_FLICKER_FILTER_ADAPTIVE), 359 SDVO_CMD_NAME_ENTRY(SET_FLICKER_FILTER_ADAPTIVE), 360 SDVO_CMD_NAME_ENTRY(GET_MAX_FLICKER_FILTER_2D), 361 SDVO_CMD_NAME_ENTRY(GET_FLICKER_FILTER_2D), 362 SDVO_CMD_NAME_ENTRY(SET_FLICKER_FILTER_2D), 363 SDVO_CMD_NAME_ENTRY(GET_MAX_SHARPNESS), 364 SDVO_CMD_NAME_ENTRY(GET_SHARPNESS), 365 SDVO_CMD_NAME_ENTRY(SET_SHARPNESS), 366 SDVO_CMD_NAME_ENTRY(GET_DOT_CRAWL), 367 SDVO_CMD_NAME_ENTRY(SET_DOT_CRAWL), 368 SDVO_CMD_NAME_ENTRY(GET_MAX_TV_CHROMA_FILTER), 369 SDVO_CMD_NAME_ENTRY(GET_TV_CHROMA_FILTER), 370 SDVO_CMD_NAME_ENTRY(SET_TV_CHROMA_FILTER), 371 SDVO_CMD_NAME_ENTRY(GET_MAX_TV_LUMA_FILTER), 372 SDVO_CMD_NAME_ENTRY(GET_TV_LUMA_FILTER), 373 SDVO_CMD_NAME_ENTRY(SET_TV_LUMA_FILTER), 374 375 /* HDMI op code */ 376 SDVO_CMD_NAME_ENTRY(GET_SUPP_ENCODE), 377 SDVO_CMD_NAME_ENTRY(GET_ENCODE), 378 SDVO_CMD_NAME_ENTRY(SET_ENCODE), 379 SDVO_CMD_NAME_ENTRY(SET_PIXEL_REPLI), 380 SDVO_CMD_NAME_ENTRY(GET_PIXEL_REPLI), 381 SDVO_CMD_NAME_ENTRY(GET_COLORIMETRY_CAP), 382 SDVO_CMD_NAME_ENTRY(SET_COLORIMETRY), 383 SDVO_CMD_NAME_ENTRY(GET_COLORIMETRY), 384 SDVO_CMD_NAME_ENTRY(GET_AUDIO_ENCRYPT_PREFER), 385 SDVO_CMD_NAME_ENTRY(SET_AUDIO_STAT), 386 SDVO_CMD_NAME_ENTRY(GET_AUDIO_STAT), 387 SDVO_CMD_NAME_ENTRY(GET_HBUF_INDEX), 388 SDVO_CMD_NAME_ENTRY(SET_HBUF_INDEX), 389 SDVO_CMD_NAME_ENTRY(GET_HBUF_INFO), 390 SDVO_CMD_NAME_ENTRY(GET_HBUF_AV_SPLIT), 391 SDVO_CMD_NAME_ENTRY(SET_HBUF_AV_SPLIT), 392 SDVO_CMD_NAME_ENTRY(GET_HBUF_TXRATE), 393 SDVO_CMD_NAME_ENTRY(SET_HBUF_TXRATE), 394 SDVO_CMD_NAME_ENTRY(SET_HBUF_DATA), 395 SDVO_CMD_NAME_ENTRY(GET_HBUF_DATA), 396 }; 397 398 #undef SDVO_CMD_NAME_ENTRY 399 400 static const char *sdvo_cmd_name(u8 cmd) 401 { 402 int i; 403 404 for (i = 0; i < ARRAY_SIZE(sdvo_cmd_names); i++) { 405 if (cmd == sdvo_cmd_names[i].cmd) 406 return sdvo_cmd_names[i].name; 407 } 408 409 return NULL; 410 } 411 412 #define SDVO_NAME(svdo) ((svdo)->base.port == PORT_B ? "SDVOB" : "SDVOC") 413 414 static void intel_sdvo_debug_write(struct intel_sdvo *intel_sdvo, u8 cmd, 415 const void *args, int args_len) 416 { 417 struct intel_display *display = to_intel_display(&intel_sdvo->base); 418 const char *cmd_name; 419 int i, pos = 0; 420 char buffer[64]; 421 422 #define BUF_PRINT(args...) \ 423 pos += snprintf(buffer + pos, max_t(int, sizeof(buffer) - pos, 0), args) 424 425 for (i = 0; i < args_len; i++) { 426 BUF_PRINT("%02X ", ((u8 *)args)[i]); 427 } 428 for (; i < 8; i++) { 429 BUF_PRINT(" "); 430 } 431 432 cmd_name = sdvo_cmd_name(cmd); 433 if (cmd_name) 434 BUF_PRINT("(%s)", cmd_name); 435 else 436 BUF_PRINT("(%02X)", cmd); 437 438 drm_WARN_ON(display->drm, pos >= sizeof(buffer) - 1); 439 #undef BUF_PRINT 440 441 drm_dbg_kms(display->drm, "%s: W: %02X %s\n", SDVO_NAME(intel_sdvo), 442 cmd, buffer); 443 } 444 445 static const char * const cmd_status_names[] = { 446 [SDVO_CMD_STATUS_POWER_ON] = "Power on", 447 [SDVO_CMD_STATUS_SUCCESS] = "Success", 448 [SDVO_CMD_STATUS_NOTSUPP] = "Not supported", 449 [SDVO_CMD_STATUS_INVALID_ARG] = "Invalid arg", 450 [SDVO_CMD_STATUS_PENDING] = "Pending", 451 [SDVO_CMD_STATUS_TARGET_NOT_SPECIFIED] = "Target not specified", 452 [SDVO_CMD_STATUS_SCALING_NOT_SUPP] = "Scaling not supported", 453 }; 454 455 static const char *sdvo_cmd_status(u8 status) 456 { 457 if (status < ARRAY_SIZE(cmd_status_names)) 458 return cmd_status_names[status]; 459 else 460 return NULL; 461 } 462 463 static bool __intel_sdvo_write_cmd(struct intel_sdvo *intel_sdvo, u8 cmd, 464 const void *args, int args_len, 465 bool unlocked) 466 { 467 struct intel_display *display = to_intel_display(&intel_sdvo->base); 468 u8 *buf, status; 469 struct i2c_msg *msgs; 470 int i, ret = true; 471 472 /* Would be simpler to allocate both in one go ? */ 473 buf = kzalloc(args_len * 2 + 2, GFP_KERNEL); 474 if (!buf) 475 return false; 476 477 msgs = kcalloc(args_len + 3, sizeof(*msgs), GFP_KERNEL); 478 if (!msgs) { 479 kfree(buf); 480 return false; 481 } 482 483 intel_sdvo_debug_write(intel_sdvo, cmd, args, args_len); 484 485 for (i = 0; i < args_len; i++) { 486 msgs[i].addr = intel_sdvo->target_addr; 487 msgs[i].flags = 0; 488 msgs[i].len = 2; 489 msgs[i].buf = buf + 2 *i; 490 buf[2*i + 0] = SDVO_I2C_ARG_0 - i; 491 buf[2*i + 1] = ((u8*)args)[i]; 492 } 493 msgs[i].addr = intel_sdvo->target_addr; 494 msgs[i].flags = 0; 495 msgs[i].len = 2; 496 msgs[i].buf = buf + 2*i; 497 buf[2*i + 0] = SDVO_I2C_OPCODE; 498 buf[2*i + 1] = cmd; 499 500 /* the following two are to read the response */ 501 status = SDVO_I2C_CMD_STATUS; 502 msgs[i+1].addr = intel_sdvo->target_addr; 503 msgs[i+1].flags = 0; 504 msgs[i+1].len = 1; 505 msgs[i+1].buf = &status; 506 507 msgs[i+2].addr = intel_sdvo->target_addr; 508 msgs[i+2].flags = I2C_M_RD; 509 msgs[i+2].len = 1; 510 msgs[i+2].buf = &status; 511 512 if (unlocked) 513 ret = i2c_transfer(intel_sdvo->i2c, msgs, i+3); 514 else 515 ret = __i2c_transfer(intel_sdvo->i2c, msgs, i+3); 516 if (ret < 0) { 517 drm_dbg_kms(display->drm, "I2c transfer returned %d\n", ret); 518 ret = false; 519 goto out; 520 } 521 if (ret != i+3) { 522 /* failure in I2C transfer */ 523 drm_dbg_kms(display->drm, "I2c transfer returned %d/%d\n", ret, i + 3); 524 ret = false; 525 } 526 527 out: 528 kfree(msgs); 529 kfree(buf); 530 return ret; 531 } 532 533 static bool intel_sdvo_write_cmd(struct intel_sdvo *intel_sdvo, u8 cmd, 534 const void *args, int args_len) 535 { 536 return __intel_sdvo_write_cmd(intel_sdvo, cmd, args, args_len, true); 537 } 538 539 static bool intel_sdvo_read_response(struct intel_sdvo *intel_sdvo, 540 void *response, int response_len) 541 { 542 struct intel_display *display = to_intel_display(&intel_sdvo->base); 543 const char *cmd_status; 544 u8 retry = 15; /* 5 quick checks, followed by 10 long checks */ 545 u8 status; 546 int i, pos = 0; 547 char buffer[64]; 548 549 buffer[0] = '\0'; 550 551 /* 552 * The documentation states that all commands will be 553 * processed within 15µs, and that we need only poll 554 * the status byte a maximum of 3 times in order for the 555 * command to be complete. 556 * 557 * Check 5 times in case the hardware failed to read the docs. 558 * 559 * Also beware that the first response by many devices is to 560 * reply PENDING and stall for time. TVs are notorious for 561 * requiring longer than specified to complete their replies. 562 * Originally (in the DDX long ago), the delay was only ever 15ms 563 * with an additional delay of 30ms applied for TVs added later after 564 * many experiments. To accommodate both sets of delays, we do a 565 * sequence of slow checks if the device is falling behind and fails 566 * to reply within 5*15µs. 567 */ 568 if (!intel_sdvo_read_byte(intel_sdvo, 569 SDVO_I2C_CMD_STATUS, 570 &status)) 571 goto log_fail; 572 573 while ((status == SDVO_CMD_STATUS_PENDING || 574 status == SDVO_CMD_STATUS_TARGET_NOT_SPECIFIED) && --retry) { 575 if (retry < 10) 576 msleep(15); 577 else 578 udelay(15); 579 580 if (!intel_sdvo_read_byte(intel_sdvo, 581 SDVO_I2C_CMD_STATUS, 582 &status)) 583 goto log_fail; 584 } 585 586 #define BUF_PRINT(args...) \ 587 pos += snprintf(buffer + pos, max_t(int, sizeof(buffer) - pos, 0), args) 588 589 cmd_status = sdvo_cmd_status(status); 590 if (cmd_status) 591 BUF_PRINT("(%s)", cmd_status); 592 else 593 BUF_PRINT("(??? %d)", status); 594 595 if (status != SDVO_CMD_STATUS_SUCCESS) 596 goto log_fail; 597 598 /* Read the command response */ 599 for (i = 0; i < response_len; i++) { 600 if (!intel_sdvo_read_byte(intel_sdvo, 601 SDVO_I2C_RETURN_0 + i, 602 &((u8 *)response)[i])) 603 goto log_fail; 604 BUF_PRINT(" %02X", ((u8 *)response)[i]); 605 } 606 607 drm_WARN_ON(display->drm, pos >= sizeof(buffer) - 1); 608 #undef BUF_PRINT 609 610 drm_dbg_kms(display->drm, "%s: R: %s\n", 611 SDVO_NAME(intel_sdvo), buffer); 612 return true; 613 614 log_fail: 615 drm_dbg_kms(display->drm, "%s: R: ... failed %s\n", 616 SDVO_NAME(intel_sdvo), buffer); 617 return false; 618 } 619 620 static int intel_sdvo_get_pixel_multiplier(const struct drm_display_mode *adjusted_mode) 621 { 622 if (adjusted_mode->crtc_clock >= 100000) 623 return 1; 624 else if (adjusted_mode->crtc_clock >= 50000) 625 return 2; 626 else 627 return 4; 628 } 629 630 static bool __intel_sdvo_set_control_bus_switch(struct intel_sdvo *intel_sdvo, 631 u8 ddc_bus) 632 { 633 /* This must be the immediately preceding write before the i2c xfer */ 634 return __intel_sdvo_write_cmd(intel_sdvo, 635 SDVO_CMD_SET_CONTROL_BUS_SWITCH, 636 &ddc_bus, 1, false); 637 } 638 639 static bool intel_sdvo_set_value(struct intel_sdvo *intel_sdvo, u8 cmd, const void *data, int len) 640 { 641 if (!intel_sdvo_write_cmd(intel_sdvo, cmd, data, len)) 642 return false; 643 644 return intel_sdvo_read_response(intel_sdvo, NULL, 0); 645 } 646 647 static bool 648 intel_sdvo_get_value(struct intel_sdvo *intel_sdvo, u8 cmd, void *value, int len) 649 { 650 if (!intel_sdvo_write_cmd(intel_sdvo, cmd, NULL, 0)) 651 return false; 652 653 return intel_sdvo_read_response(intel_sdvo, value, len); 654 } 655 656 static bool intel_sdvo_set_target_input(struct intel_sdvo *intel_sdvo) 657 { 658 struct intel_sdvo_set_target_input_args targets = {}; 659 return intel_sdvo_set_value(intel_sdvo, 660 SDVO_CMD_SET_TARGET_INPUT, 661 &targets, sizeof(targets)); 662 } 663 664 /* 665 * Return whether each input is trained. 666 * 667 * This function is making an assumption about the layout of the response, 668 * which should be checked against the docs. 669 */ 670 static bool intel_sdvo_get_trained_inputs(struct intel_sdvo *intel_sdvo, bool *input_1, bool *input_2) 671 { 672 struct intel_sdvo_get_trained_inputs_response response; 673 674 BUILD_BUG_ON(sizeof(response) != 1); 675 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_TRAINED_INPUTS, 676 &response, sizeof(response))) 677 return false; 678 679 *input_1 = response.input0_trained; 680 *input_2 = response.input1_trained; 681 return true; 682 } 683 684 static bool intel_sdvo_set_active_outputs(struct intel_sdvo *intel_sdvo, 685 u16 outputs) 686 { 687 return intel_sdvo_set_value(intel_sdvo, 688 SDVO_CMD_SET_ACTIVE_OUTPUTS, 689 &outputs, sizeof(outputs)); 690 } 691 692 static bool intel_sdvo_get_active_outputs(struct intel_sdvo *intel_sdvo, 693 u16 *outputs) 694 { 695 return intel_sdvo_get_value(intel_sdvo, 696 SDVO_CMD_GET_ACTIVE_OUTPUTS, 697 outputs, sizeof(*outputs)); 698 } 699 700 static bool intel_sdvo_set_encoder_power_state(struct intel_sdvo *intel_sdvo, 701 int mode) 702 { 703 u8 state = SDVO_ENCODER_STATE_ON; 704 705 switch (mode) { 706 case DRM_MODE_DPMS_ON: 707 state = SDVO_ENCODER_STATE_ON; 708 break; 709 case DRM_MODE_DPMS_STANDBY: 710 state = SDVO_ENCODER_STATE_STANDBY; 711 break; 712 case DRM_MODE_DPMS_SUSPEND: 713 state = SDVO_ENCODER_STATE_SUSPEND; 714 break; 715 case DRM_MODE_DPMS_OFF: 716 state = SDVO_ENCODER_STATE_OFF; 717 break; 718 } 719 720 return intel_sdvo_set_value(intel_sdvo, 721 SDVO_CMD_SET_ENCODER_POWER_STATE, &state, sizeof(state)); 722 } 723 724 static bool intel_sdvo_get_input_pixel_clock_range(struct intel_sdvo *intel_sdvo, 725 int *clock_min, 726 int *clock_max) 727 { 728 struct intel_sdvo_pixel_clock_range clocks; 729 730 BUILD_BUG_ON(sizeof(clocks) != 4); 731 if (!intel_sdvo_get_value(intel_sdvo, 732 SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE, 733 &clocks, sizeof(clocks))) 734 return false; 735 736 /* Convert the values from units of 10 kHz to kHz. */ 737 *clock_min = clocks.min * 10; 738 *clock_max = clocks.max * 10; 739 return true; 740 } 741 742 static bool intel_sdvo_set_target_output(struct intel_sdvo *intel_sdvo, 743 u16 outputs) 744 { 745 return intel_sdvo_set_value(intel_sdvo, 746 SDVO_CMD_SET_TARGET_OUTPUT, 747 &outputs, sizeof(outputs)); 748 } 749 750 static bool intel_sdvo_set_timing(struct intel_sdvo *intel_sdvo, u8 cmd, 751 struct intel_sdvo_dtd *dtd) 752 { 753 return intel_sdvo_set_value(intel_sdvo, cmd, &dtd->part1, sizeof(dtd->part1)) && 754 intel_sdvo_set_value(intel_sdvo, cmd + 1, &dtd->part2, sizeof(dtd->part2)); 755 } 756 757 static bool intel_sdvo_get_timing(struct intel_sdvo *intel_sdvo, u8 cmd, 758 struct intel_sdvo_dtd *dtd) 759 { 760 return intel_sdvo_get_value(intel_sdvo, cmd, &dtd->part1, sizeof(dtd->part1)) && 761 intel_sdvo_get_value(intel_sdvo, cmd + 1, &dtd->part2, sizeof(dtd->part2)); 762 } 763 764 static bool intel_sdvo_set_input_timing(struct intel_sdvo *intel_sdvo, 765 struct intel_sdvo_dtd *dtd) 766 { 767 return intel_sdvo_set_timing(intel_sdvo, 768 SDVO_CMD_SET_INPUT_TIMINGS_PART1, dtd); 769 } 770 771 static bool intel_sdvo_set_output_timing(struct intel_sdvo *intel_sdvo, 772 struct intel_sdvo_dtd *dtd) 773 { 774 return intel_sdvo_set_timing(intel_sdvo, 775 SDVO_CMD_SET_OUTPUT_TIMINGS_PART1, dtd); 776 } 777 778 static bool intel_sdvo_get_input_timing(struct intel_sdvo *intel_sdvo, 779 struct intel_sdvo_dtd *dtd) 780 { 781 return intel_sdvo_get_timing(intel_sdvo, 782 SDVO_CMD_GET_INPUT_TIMINGS_PART1, dtd); 783 } 784 785 static bool 786 intel_sdvo_create_preferred_input_timing(struct intel_sdvo *intel_sdvo, 787 struct intel_sdvo_connector *intel_sdvo_connector, 788 const struct drm_display_mode *mode) 789 { 790 struct intel_sdvo_preferred_input_timing_args args; 791 792 memset(&args, 0, sizeof(args)); 793 args.clock = mode->clock / 10; 794 args.width = mode->hdisplay; 795 args.height = mode->vdisplay; 796 args.interlace = 0; 797 798 if (IS_LVDS(intel_sdvo_connector)) { 799 const struct drm_display_mode *fixed_mode = 800 intel_panel_fixed_mode(&intel_sdvo_connector->base, mode); 801 802 if (fixed_mode->hdisplay != args.width || 803 fixed_mode->vdisplay != args.height) 804 args.scaled = 1; 805 } 806 807 return intel_sdvo_set_value(intel_sdvo, 808 SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING, 809 &args, sizeof(args)); 810 } 811 812 static bool intel_sdvo_get_preferred_input_timing(struct intel_sdvo *intel_sdvo, 813 struct intel_sdvo_dtd *dtd) 814 { 815 BUILD_BUG_ON(sizeof(dtd->part1) != 8); 816 BUILD_BUG_ON(sizeof(dtd->part2) != 8); 817 return intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1, 818 &dtd->part1, sizeof(dtd->part1)) && 819 intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2, 820 &dtd->part2, sizeof(dtd->part2)); 821 } 822 823 static bool intel_sdvo_set_clock_rate_mult(struct intel_sdvo *intel_sdvo, u8 val) 824 { 825 return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_CLOCK_RATE_MULT, &val, 1); 826 } 827 828 static void intel_sdvo_get_dtd_from_mode(struct intel_sdvo_dtd *dtd, 829 const struct drm_display_mode *mode) 830 { 831 u16 width, height; 832 u16 h_blank_len, h_sync_len, v_blank_len, v_sync_len; 833 u16 h_sync_offset, v_sync_offset; 834 int mode_clock; 835 836 memset(dtd, 0, sizeof(*dtd)); 837 838 width = mode->hdisplay; 839 height = mode->vdisplay; 840 841 /* do some mode translations */ 842 h_blank_len = mode->htotal - mode->hdisplay; 843 h_sync_len = mode->hsync_end - mode->hsync_start; 844 845 v_blank_len = mode->vtotal - mode->vdisplay; 846 v_sync_len = mode->vsync_end - mode->vsync_start; 847 848 h_sync_offset = mode->hsync_start - mode->hdisplay; 849 v_sync_offset = mode->vsync_start - mode->vdisplay; 850 851 mode_clock = mode->clock; 852 mode_clock /= 10; 853 dtd->part1.clock = mode_clock; 854 855 dtd->part1.h_active = width & 0xff; 856 dtd->part1.h_blank = h_blank_len & 0xff; 857 dtd->part1.h_high = (((width >> 8) & 0xf) << 4) | 858 ((h_blank_len >> 8) & 0xf); 859 dtd->part1.v_active = height & 0xff; 860 dtd->part1.v_blank = v_blank_len & 0xff; 861 dtd->part1.v_high = (((height >> 8) & 0xf) << 4) | 862 ((v_blank_len >> 8) & 0xf); 863 864 dtd->part2.h_sync_off = h_sync_offset & 0xff; 865 dtd->part2.h_sync_width = h_sync_len & 0xff; 866 dtd->part2.v_sync_off_width = (v_sync_offset & 0xf) << 4 | 867 (v_sync_len & 0xf); 868 dtd->part2.sync_off_width_high = ((h_sync_offset & 0x300) >> 2) | 869 ((h_sync_len & 0x300) >> 4) | ((v_sync_offset & 0x30) >> 2) | 870 ((v_sync_len & 0x30) >> 4); 871 872 dtd->part2.dtd_flags = 0x18; 873 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 874 dtd->part2.dtd_flags |= DTD_FLAG_INTERLACE; 875 if (mode->flags & DRM_MODE_FLAG_PHSYNC) 876 dtd->part2.dtd_flags |= DTD_FLAG_HSYNC_POSITIVE; 877 if (mode->flags & DRM_MODE_FLAG_PVSYNC) 878 dtd->part2.dtd_flags |= DTD_FLAG_VSYNC_POSITIVE; 879 880 dtd->part2.v_sync_off_high = v_sync_offset & 0xc0; 881 } 882 883 static void intel_sdvo_get_mode_from_dtd(struct drm_display_mode *pmode, 884 const struct intel_sdvo_dtd *dtd) 885 { 886 struct drm_display_mode mode = {}; 887 888 mode.hdisplay = dtd->part1.h_active; 889 mode.hdisplay += ((dtd->part1.h_high >> 4) & 0x0f) << 8; 890 mode.hsync_start = mode.hdisplay + dtd->part2.h_sync_off; 891 mode.hsync_start += (dtd->part2.sync_off_width_high & 0xc0) << 2; 892 mode.hsync_end = mode.hsync_start + dtd->part2.h_sync_width; 893 mode.hsync_end += (dtd->part2.sync_off_width_high & 0x30) << 4; 894 mode.htotal = mode.hdisplay + dtd->part1.h_blank; 895 mode.htotal += (dtd->part1.h_high & 0xf) << 8; 896 897 mode.vdisplay = dtd->part1.v_active; 898 mode.vdisplay += ((dtd->part1.v_high >> 4) & 0x0f) << 8; 899 mode.vsync_start = mode.vdisplay; 900 mode.vsync_start += (dtd->part2.v_sync_off_width >> 4) & 0xf; 901 mode.vsync_start += (dtd->part2.sync_off_width_high & 0x0c) << 2; 902 mode.vsync_start += dtd->part2.v_sync_off_high & 0xc0; 903 mode.vsync_end = mode.vsync_start + 904 (dtd->part2.v_sync_off_width & 0xf); 905 mode.vsync_end += (dtd->part2.sync_off_width_high & 0x3) << 4; 906 mode.vtotal = mode.vdisplay + dtd->part1.v_blank; 907 mode.vtotal += (dtd->part1.v_high & 0xf) << 8; 908 909 mode.clock = dtd->part1.clock * 10; 910 911 if (dtd->part2.dtd_flags & DTD_FLAG_INTERLACE) 912 mode.flags |= DRM_MODE_FLAG_INTERLACE; 913 if (dtd->part2.dtd_flags & DTD_FLAG_HSYNC_POSITIVE) 914 mode.flags |= DRM_MODE_FLAG_PHSYNC; 915 else 916 mode.flags |= DRM_MODE_FLAG_NHSYNC; 917 if (dtd->part2.dtd_flags & DTD_FLAG_VSYNC_POSITIVE) 918 mode.flags |= DRM_MODE_FLAG_PVSYNC; 919 else 920 mode.flags |= DRM_MODE_FLAG_NVSYNC; 921 922 drm_mode_set_crtcinfo(&mode, 0); 923 924 drm_mode_copy(pmode, &mode); 925 } 926 927 static bool intel_sdvo_check_supp_encode(struct intel_sdvo *intel_sdvo) 928 { 929 struct intel_sdvo_encode encode; 930 931 BUILD_BUG_ON(sizeof(encode) != 2); 932 return intel_sdvo_get_value(intel_sdvo, 933 SDVO_CMD_GET_SUPP_ENCODE, 934 &encode, sizeof(encode)); 935 } 936 937 static bool intel_sdvo_set_encode(struct intel_sdvo *intel_sdvo, 938 u8 mode) 939 { 940 return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_ENCODE, &mode, 1); 941 } 942 943 static bool intel_sdvo_set_colorimetry(struct intel_sdvo *intel_sdvo, 944 u8 mode) 945 { 946 return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_COLORIMETRY, &mode, 1); 947 } 948 949 static bool intel_sdvo_set_pixel_replication(struct intel_sdvo *intel_sdvo, 950 u8 pixel_repeat) 951 { 952 return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_PIXEL_REPLI, 953 &pixel_repeat, 1); 954 } 955 956 static bool intel_sdvo_set_audio_state(struct intel_sdvo *intel_sdvo, 957 u8 audio_state) 958 { 959 return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_AUDIO_STAT, 960 &audio_state, 1); 961 } 962 963 static bool intel_sdvo_get_hbuf_size(struct intel_sdvo *intel_sdvo, 964 u8 *hbuf_size) 965 { 966 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_HBUF_INFO, 967 hbuf_size, 1)) 968 return false; 969 970 /* Buffer size is 0 based, hooray! However zero means zero. */ 971 if (*hbuf_size) 972 (*hbuf_size)++; 973 974 return true; 975 } 976 977 #if 0 978 static void intel_sdvo_dump_hdmi_buf(struct intel_sdvo *intel_sdvo) 979 { 980 int i, j; 981 u8 set_buf_index[2]; 982 u8 av_split; 983 u8 buf_size; 984 u8 buf[48]; 985 u8 *pos; 986 987 intel_sdvo_get_value(encoder, SDVO_CMD_GET_HBUF_AV_SPLIT, &av_split, 1); 988 989 for (i = 0; i <= av_split; i++) { 990 set_buf_index[0] = i; set_buf_index[1] = 0; 991 intel_sdvo_write_cmd(encoder, SDVO_CMD_SET_HBUF_INDEX, 992 set_buf_index, 2); 993 intel_sdvo_write_cmd(encoder, SDVO_CMD_GET_HBUF_INFO, NULL, 0); 994 intel_sdvo_read_response(encoder, &buf_size, 1); 995 996 pos = buf; 997 for (j = 0; j <= buf_size; j += 8) { 998 intel_sdvo_write_cmd(encoder, SDVO_CMD_GET_HBUF_DATA, 999 NULL, 0); 1000 intel_sdvo_read_response(encoder, pos, 8); 1001 pos += 8; 1002 } 1003 } 1004 } 1005 #endif 1006 1007 static bool intel_sdvo_write_infoframe(struct intel_sdvo *intel_sdvo, 1008 unsigned int if_index, u8 tx_rate, 1009 const u8 *data, unsigned int length) 1010 { 1011 struct intel_display *display = to_intel_display(&intel_sdvo->base); 1012 u8 set_buf_index[2] = { if_index, 0 }; 1013 u8 hbuf_size, tmp[8]; 1014 int i; 1015 1016 if (!intel_sdvo_set_value(intel_sdvo, 1017 SDVO_CMD_SET_HBUF_INDEX, 1018 set_buf_index, 2)) 1019 return false; 1020 1021 if (!intel_sdvo_get_hbuf_size(intel_sdvo, &hbuf_size)) 1022 return false; 1023 1024 drm_dbg_kms(display->drm, 1025 "writing sdvo hbuf: %i, length %u, hbuf_size: %i\n", 1026 if_index, length, hbuf_size); 1027 1028 if (hbuf_size < length) 1029 return false; 1030 1031 for (i = 0; i < hbuf_size; i += 8) { 1032 memset(tmp, 0, 8); 1033 if (i < length) 1034 memcpy(tmp, data + i, min_t(unsigned, 8, length - i)); 1035 1036 if (!intel_sdvo_set_value(intel_sdvo, 1037 SDVO_CMD_SET_HBUF_DATA, 1038 tmp, 8)) 1039 return false; 1040 } 1041 1042 return intel_sdvo_set_value(intel_sdvo, 1043 SDVO_CMD_SET_HBUF_TXRATE, 1044 &tx_rate, 1); 1045 } 1046 1047 static ssize_t intel_sdvo_read_infoframe(struct intel_sdvo *intel_sdvo, 1048 unsigned int if_index, 1049 u8 *data, unsigned int length) 1050 { 1051 struct intel_display *display = to_intel_display(&intel_sdvo->base); 1052 u8 set_buf_index[2] = { if_index, 0 }; 1053 u8 hbuf_size, tx_rate, av_split; 1054 int i; 1055 1056 if (!intel_sdvo_get_value(intel_sdvo, 1057 SDVO_CMD_GET_HBUF_AV_SPLIT, 1058 &av_split, 1)) 1059 return -ENXIO; 1060 1061 if (av_split < if_index) 1062 return 0; 1063 1064 if (!intel_sdvo_set_value(intel_sdvo, 1065 SDVO_CMD_SET_HBUF_INDEX, 1066 set_buf_index, 2)) 1067 return -ENXIO; 1068 1069 if (!intel_sdvo_get_value(intel_sdvo, 1070 SDVO_CMD_GET_HBUF_TXRATE, 1071 &tx_rate, 1)) 1072 return -ENXIO; 1073 1074 /* TX_DISABLED doesn't mean disabled for ELD */ 1075 if (if_index != SDVO_HBUF_INDEX_ELD && tx_rate == SDVO_HBUF_TX_DISABLED) 1076 return 0; 1077 1078 if (!intel_sdvo_get_hbuf_size(intel_sdvo, &hbuf_size)) 1079 return false; 1080 1081 drm_dbg_kms(display->drm, 1082 "reading sdvo hbuf: %i, length %u, hbuf_size: %i\n", 1083 if_index, length, hbuf_size); 1084 1085 hbuf_size = min_t(unsigned int, length, hbuf_size); 1086 1087 for (i = 0; i < hbuf_size; i += 8) { 1088 if (!intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_GET_HBUF_DATA, NULL, 0)) 1089 return -ENXIO; 1090 if (!intel_sdvo_read_response(intel_sdvo, &data[i], 1091 min_t(unsigned int, 8, hbuf_size - i))) 1092 return -ENXIO; 1093 } 1094 1095 return hbuf_size; 1096 } 1097 1098 static bool intel_sdvo_compute_avi_infoframe(struct intel_sdvo *intel_sdvo, 1099 struct intel_crtc_state *crtc_state, 1100 struct drm_connector_state *conn_state) 1101 { 1102 struct intel_display *display = to_intel_display(&intel_sdvo->base); 1103 struct hdmi_avi_infoframe *frame = &crtc_state->infoframes.avi.avi; 1104 const struct drm_display_mode *adjusted_mode = 1105 &crtc_state->hw.adjusted_mode; 1106 int ret; 1107 1108 if (!crtc_state->has_hdmi_sink) 1109 return true; 1110 1111 crtc_state->infoframes.enable |= 1112 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_AVI); 1113 1114 ret = drm_hdmi_avi_infoframe_from_display_mode(frame, 1115 conn_state->connector, 1116 adjusted_mode); 1117 if (ret) 1118 return false; 1119 1120 drm_hdmi_avi_infoframe_quant_range(frame, 1121 conn_state->connector, 1122 adjusted_mode, 1123 crtc_state->limited_color_range ? 1124 HDMI_QUANTIZATION_RANGE_LIMITED : 1125 HDMI_QUANTIZATION_RANGE_FULL); 1126 1127 ret = hdmi_avi_infoframe_check(frame); 1128 if (drm_WARN_ON(display->drm, ret)) 1129 return false; 1130 1131 return true; 1132 } 1133 1134 static bool intel_sdvo_set_avi_infoframe(struct intel_sdvo *intel_sdvo, 1135 const struct intel_crtc_state *crtc_state) 1136 { 1137 struct intel_display *display = to_intel_display(&intel_sdvo->base); 1138 u8 sdvo_data[HDMI_INFOFRAME_SIZE(AVI)]; 1139 const union hdmi_infoframe *frame = &crtc_state->infoframes.avi; 1140 ssize_t len; 1141 1142 if ((crtc_state->infoframes.enable & 1143 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_AVI)) == 0) 1144 return true; 1145 1146 if (drm_WARN_ON(display->drm, 1147 frame->any.type != HDMI_INFOFRAME_TYPE_AVI)) 1148 return false; 1149 1150 len = hdmi_infoframe_pack_only(frame, sdvo_data, sizeof(sdvo_data)); 1151 if (drm_WARN_ON(display->drm, len < 0)) 1152 return false; 1153 1154 return intel_sdvo_write_infoframe(intel_sdvo, SDVO_HBUF_INDEX_AVI_IF, 1155 SDVO_HBUF_TX_VSYNC, 1156 sdvo_data, len); 1157 } 1158 1159 static void intel_sdvo_get_avi_infoframe(struct intel_sdvo *intel_sdvo, 1160 struct intel_crtc_state *crtc_state) 1161 { 1162 struct intel_display *display = to_intel_display(&intel_sdvo->base); 1163 u8 sdvo_data[HDMI_INFOFRAME_SIZE(AVI)]; 1164 union hdmi_infoframe *frame = &crtc_state->infoframes.avi; 1165 ssize_t len; 1166 int ret; 1167 1168 if (!crtc_state->has_hdmi_sink) 1169 return; 1170 1171 len = intel_sdvo_read_infoframe(intel_sdvo, SDVO_HBUF_INDEX_AVI_IF, 1172 sdvo_data, sizeof(sdvo_data)); 1173 if (len < 0) { 1174 drm_dbg_kms(display->drm, "failed to read AVI infoframe\n"); 1175 return; 1176 } else if (len == 0) { 1177 return; 1178 } 1179 1180 crtc_state->infoframes.enable |= 1181 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_AVI); 1182 1183 ret = hdmi_infoframe_unpack(frame, sdvo_data, len); 1184 if (ret) { 1185 drm_dbg_kms(display->drm, "Failed to unpack AVI infoframe\n"); 1186 return; 1187 } 1188 1189 if (frame->any.type != HDMI_INFOFRAME_TYPE_AVI) 1190 drm_dbg_kms(display->drm, 1191 "Found the wrong infoframe type 0x%x (expected 0x%02x)\n", 1192 frame->any.type, HDMI_INFOFRAME_TYPE_AVI); 1193 } 1194 1195 static void intel_sdvo_get_eld(struct intel_sdvo *intel_sdvo, 1196 struct intel_crtc_state *crtc_state) 1197 { 1198 struct intel_display *display = to_intel_display(&intel_sdvo->base); 1199 ssize_t len; 1200 u8 val; 1201 1202 if (!crtc_state->has_audio) 1203 return; 1204 1205 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_AUDIO_STAT, &val, 1)) 1206 return; 1207 1208 if ((val & SDVO_AUDIO_ELD_VALID) == 0) 1209 return; 1210 1211 len = intel_sdvo_read_infoframe(intel_sdvo, SDVO_HBUF_INDEX_ELD, 1212 crtc_state->eld, sizeof(crtc_state->eld)); 1213 if (len < 0) 1214 drm_dbg_kms(display->drm, "failed to read ELD\n"); 1215 } 1216 1217 static bool intel_sdvo_set_tv_format(struct intel_sdvo *intel_sdvo, 1218 const struct drm_connector_state *conn_state) 1219 { 1220 struct intel_sdvo_tv_format format; 1221 u32 format_map; 1222 1223 format_map = 1 << conn_state->tv.legacy_mode; 1224 memset(&format, 0, sizeof(format)); 1225 memcpy(&format, &format_map, min(sizeof(format), sizeof(format_map))); 1226 1227 BUILD_BUG_ON(sizeof(format) != 6); 1228 return intel_sdvo_set_value(intel_sdvo, 1229 SDVO_CMD_SET_TV_FORMAT, 1230 &format, sizeof(format)); 1231 } 1232 1233 static bool 1234 intel_sdvo_set_output_timings_from_mode(struct intel_sdvo *intel_sdvo, 1235 struct intel_sdvo_connector *intel_sdvo_connector, 1236 const struct drm_display_mode *mode) 1237 { 1238 struct intel_sdvo_dtd output_dtd; 1239 1240 if (!intel_sdvo_set_target_output(intel_sdvo, 1241 intel_sdvo_connector->output_flag)) 1242 return false; 1243 1244 intel_sdvo_get_dtd_from_mode(&output_dtd, mode); 1245 if (!intel_sdvo_set_output_timing(intel_sdvo, &output_dtd)) 1246 return false; 1247 1248 return true; 1249 } 1250 1251 /* 1252 * Asks the sdvo controller for the preferred input mode given the output mode. 1253 * Unfortunately we have to set up the full output mode to do that. 1254 */ 1255 static bool 1256 intel_sdvo_get_preferred_input_mode(struct intel_sdvo *intel_sdvo, 1257 struct intel_sdvo_connector *intel_sdvo_connector, 1258 const struct drm_display_mode *mode, 1259 struct drm_display_mode *adjusted_mode) 1260 { 1261 struct intel_sdvo_dtd input_dtd; 1262 1263 /* Reset the input timing to the screen. Assume always input 0. */ 1264 if (!intel_sdvo_set_target_input(intel_sdvo)) 1265 return false; 1266 1267 if (!intel_sdvo_create_preferred_input_timing(intel_sdvo, 1268 intel_sdvo_connector, 1269 mode)) 1270 return false; 1271 1272 if (!intel_sdvo_get_preferred_input_timing(intel_sdvo, 1273 &input_dtd)) 1274 return false; 1275 1276 intel_sdvo_get_mode_from_dtd(adjusted_mode, &input_dtd); 1277 intel_sdvo->dtd_sdvo_flags = input_dtd.part2.sdvo_flags; 1278 1279 return true; 1280 } 1281 1282 static int i9xx_adjust_sdvo_tv_clock(struct intel_crtc_state *pipe_config) 1283 { 1284 struct intel_display *display = to_intel_display(pipe_config); 1285 unsigned int dotclock = pipe_config->hw.adjusted_mode.crtc_clock; 1286 struct dpll *clock = &pipe_config->dpll; 1287 1288 /* 1289 * SDVO TV has fixed PLL values depend on its clock range, 1290 * this mirrors vbios setting. 1291 */ 1292 if (dotclock >= 100000 && dotclock < 140500) { 1293 clock->p1 = 2; 1294 clock->p2 = 10; 1295 clock->n = 3; 1296 clock->m1 = 16; 1297 clock->m2 = 8; 1298 } else if (dotclock >= 140500 && dotclock <= 200000) { 1299 clock->p1 = 1; 1300 clock->p2 = 10; 1301 clock->n = 6; 1302 clock->m1 = 12; 1303 clock->m2 = 8; 1304 } else { 1305 drm_dbg_kms(display->drm, 1306 "SDVO TV clock out of range: %i\n", dotclock); 1307 return -EINVAL; 1308 } 1309 1310 pipe_config->clock_set = true; 1311 1312 return 0; 1313 } 1314 1315 static bool intel_has_hdmi_sink(struct intel_sdvo_connector *intel_sdvo_connector, 1316 const struct drm_connector_state *conn_state) 1317 { 1318 struct drm_connector *connector = conn_state->connector; 1319 1320 return intel_sdvo_connector->is_hdmi && 1321 connector->display_info.is_hdmi && 1322 READ_ONCE(to_intel_digital_connector_state(conn_state)->force_audio) != HDMI_AUDIO_OFF_DVI; 1323 } 1324 1325 static bool intel_sdvo_limited_color_range(struct intel_encoder *encoder, 1326 const struct intel_crtc_state *crtc_state, 1327 const struct drm_connector_state *conn_state) 1328 { 1329 struct intel_sdvo *intel_sdvo = to_sdvo(encoder); 1330 1331 if ((intel_sdvo->colorimetry_cap & SDVO_COLORIMETRY_RGB220) == 0) 1332 return false; 1333 1334 return intel_hdmi_limited_color_range(crtc_state, conn_state); 1335 } 1336 1337 static bool intel_sdvo_has_audio(struct intel_encoder *encoder, 1338 const struct intel_crtc_state *crtc_state, 1339 const struct drm_connector_state *conn_state) 1340 { 1341 struct drm_connector *connector = conn_state->connector; 1342 struct intel_sdvo_connector *intel_sdvo_connector = 1343 to_intel_sdvo_connector(connector); 1344 const struct intel_digital_connector_state *intel_conn_state = 1345 to_intel_digital_connector_state(conn_state); 1346 1347 if (!crtc_state->has_hdmi_sink) 1348 return false; 1349 1350 if (intel_conn_state->force_audio == HDMI_AUDIO_AUTO) 1351 return intel_sdvo_connector->is_hdmi && 1352 connector->display_info.has_audio; 1353 else 1354 return intel_conn_state->force_audio == HDMI_AUDIO_ON; 1355 } 1356 1357 static int intel_sdvo_compute_config(struct intel_encoder *encoder, 1358 struct intel_crtc_state *pipe_config, 1359 struct drm_connector_state *conn_state) 1360 { 1361 struct intel_display *display = to_intel_display(encoder); 1362 struct intel_sdvo *intel_sdvo = to_sdvo(encoder); 1363 struct intel_sdvo_connector *intel_sdvo_connector = 1364 to_intel_sdvo_connector(conn_state->connector); 1365 struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode; 1366 struct drm_display_mode *mode = &pipe_config->hw.mode; 1367 1368 if (HAS_PCH_SPLIT(display)) { 1369 pipe_config->has_pch_encoder = true; 1370 if (!intel_fdi_compute_pipe_bpp(pipe_config)) 1371 return -EINVAL; 1372 } 1373 1374 drm_dbg_kms(display->drm, "forcing bpc to 8 for SDVO\n"); 1375 /* FIXME: Don't increase pipe_bpp */ 1376 pipe_config->pipe_bpp = 8*3; 1377 pipe_config->sink_format = INTEL_OUTPUT_FORMAT_RGB; 1378 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; 1379 1380 /* 1381 * We need to construct preferred input timings based on our 1382 * output timings. To do that, we have to set the output 1383 * timings, even though this isn't really the right place in 1384 * the sequence to do it. Oh well. 1385 */ 1386 if (IS_TV(intel_sdvo_connector)) { 1387 if (!intel_sdvo_set_output_timings_from_mode(intel_sdvo, 1388 intel_sdvo_connector, 1389 mode)) 1390 return -EINVAL; 1391 1392 (void) intel_sdvo_get_preferred_input_mode(intel_sdvo, 1393 intel_sdvo_connector, 1394 mode, 1395 adjusted_mode); 1396 pipe_config->sdvo_tv_clock = true; 1397 } else if (IS_LVDS(intel_sdvo_connector)) { 1398 const struct drm_display_mode *fixed_mode = 1399 intel_panel_fixed_mode(&intel_sdvo_connector->base, mode); 1400 int ret; 1401 1402 ret = intel_panel_compute_config(&intel_sdvo_connector->base, 1403 adjusted_mode); 1404 if (ret) 1405 return ret; 1406 1407 if (!intel_sdvo_set_output_timings_from_mode(intel_sdvo, 1408 intel_sdvo_connector, 1409 fixed_mode)) 1410 return -EINVAL; 1411 1412 (void) intel_sdvo_get_preferred_input_mode(intel_sdvo, 1413 intel_sdvo_connector, 1414 mode, 1415 adjusted_mode); 1416 } 1417 1418 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN) 1419 return -EINVAL; 1420 1421 /* 1422 * Make the CRTC code factor in the SDVO pixel multiplier. The 1423 * SDVO device will factor out the multiplier during mode_set. 1424 */ 1425 pipe_config->pixel_multiplier = 1426 intel_sdvo_get_pixel_multiplier(adjusted_mode); 1427 1428 pipe_config->has_hdmi_sink = intel_has_hdmi_sink(intel_sdvo_connector, conn_state); 1429 1430 pipe_config->has_audio = 1431 intel_sdvo_has_audio(encoder, pipe_config, conn_state) && 1432 intel_audio_compute_config(encoder, pipe_config, conn_state); 1433 1434 pipe_config->limited_color_range = 1435 intel_sdvo_limited_color_range(encoder, pipe_config, 1436 conn_state); 1437 1438 /* Clock computation needs to happen after pixel multiplier. */ 1439 if (IS_TV(intel_sdvo_connector)) { 1440 int ret; 1441 1442 ret = i9xx_adjust_sdvo_tv_clock(pipe_config); 1443 if (ret) 1444 return ret; 1445 } 1446 1447 if (conn_state->picture_aspect_ratio) 1448 adjusted_mode->picture_aspect_ratio = 1449 conn_state->picture_aspect_ratio; 1450 1451 if (!intel_sdvo_compute_avi_infoframe(intel_sdvo, 1452 pipe_config, conn_state)) { 1453 drm_dbg_kms(display->drm, "bad AVI infoframe\n"); 1454 return -EINVAL; 1455 } 1456 1457 return 0; 1458 } 1459 1460 #define UPDATE_PROPERTY(input, NAME) \ 1461 do { \ 1462 val = input; \ 1463 intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_##NAME, &val, sizeof(val)); \ 1464 } while (0) 1465 1466 static void intel_sdvo_update_props(struct intel_sdvo *intel_sdvo, 1467 const struct intel_sdvo_connector_state *sdvo_state) 1468 { 1469 const struct drm_connector_state *conn_state = &sdvo_state->base.base; 1470 struct intel_sdvo_connector *intel_sdvo_conn = 1471 to_intel_sdvo_connector(conn_state->connector); 1472 u16 val; 1473 1474 if (intel_sdvo_conn->left) 1475 UPDATE_PROPERTY(sdvo_state->tv.overscan_h, OVERSCAN_H); 1476 1477 if (intel_sdvo_conn->top) 1478 UPDATE_PROPERTY(sdvo_state->tv.overscan_v, OVERSCAN_V); 1479 1480 if (intel_sdvo_conn->hpos) 1481 UPDATE_PROPERTY(sdvo_state->tv.hpos, HPOS); 1482 1483 if (intel_sdvo_conn->vpos) 1484 UPDATE_PROPERTY(sdvo_state->tv.vpos, VPOS); 1485 1486 if (intel_sdvo_conn->saturation) 1487 UPDATE_PROPERTY(conn_state->tv.saturation, SATURATION); 1488 1489 if (intel_sdvo_conn->contrast) 1490 UPDATE_PROPERTY(conn_state->tv.contrast, CONTRAST); 1491 1492 if (intel_sdvo_conn->hue) 1493 UPDATE_PROPERTY(conn_state->tv.hue, HUE); 1494 1495 if (intel_sdvo_conn->brightness) 1496 UPDATE_PROPERTY(conn_state->tv.brightness, BRIGHTNESS); 1497 1498 if (intel_sdvo_conn->sharpness) 1499 UPDATE_PROPERTY(sdvo_state->tv.sharpness, SHARPNESS); 1500 1501 if (intel_sdvo_conn->flicker_filter) 1502 UPDATE_PROPERTY(sdvo_state->tv.flicker_filter, FLICKER_FILTER); 1503 1504 if (intel_sdvo_conn->flicker_filter_2d) 1505 UPDATE_PROPERTY(sdvo_state->tv.flicker_filter_2d, FLICKER_FILTER_2D); 1506 1507 if (intel_sdvo_conn->flicker_filter_adaptive) 1508 UPDATE_PROPERTY(sdvo_state->tv.flicker_filter_adaptive, FLICKER_FILTER_ADAPTIVE); 1509 1510 if (intel_sdvo_conn->tv_chroma_filter) 1511 UPDATE_PROPERTY(sdvo_state->tv.chroma_filter, TV_CHROMA_FILTER); 1512 1513 if (intel_sdvo_conn->tv_luma_filter) 1514 UPDATE_PROPERTY(sdvo_state->tv.luma_filter, TV_LUMA_FILTER); 1515 1516 if (intel_sdvo_conn->dot_crawl) 1517 UPDATE_PROPERTY(sdvo_state->tv.dot_crawl, DOT_CRAWL); 1518 1519 #undef UPDATE_PROPERTY 1520 } 1521 1522 static void intel_sdvo_pre_enable(struct intel_atomic_state *state, 1523 struct intel_encoder *intel_encoder, 1524 const struct intel_crtc_state *crtc_state, 1525 const struct drm_connector_state *conn_state) 1526 { 1527 struct intel_display *display = to_intel_display(intel_encoder); 1528 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1529 const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; 1530 const struct intel_sdvo_connector_state *sdvo_state = 1531 to_intel_sdvo_connector_state(conn_state); 1532 struct intel_sdvo_connector *intel_sdvo_connector = 1533 to_intel_sdvo_connector(conn_state->connector); 1534 const struct drm_display_mode *mode = &crtc_state->hw.mode; 1535 struct intel_sdvo *intel_sdvo = to_sdvo(intel_encoder); 1536 u32 sdvox; 1537 struct intel_sdvo_in_out_map in_out; 1538 struct intel_sdvo_dtd input_dtd, output_dtd; 1539 int rate; 1540 1541 intel_sdvo_update_props(intel_sdvo, sdvo_state); 1542 1543 /* 1544 * First, set the input mapping for the first input to our controlled 1545 * output. This is only correct if we're a single-input device, in 1546 * which case the first input is the output from the appropriate SDVO 1547 * channel on the motherboard. In a two-input device, the first input 1548 * will be SDVOB and the second SDVOC. 1549 */ 1550 in_out.in0 = intel_sdvo_connector->output_flag; 1551 in_out.in1 = 0; 1552 1553 intel_sdvo_set_value(intel_sdvo, 1554 SDVO_CMD_SET_IN_OUT_MAP, 1555 &in_out, sizeof(in_out)); 1556 1557 /* Set the output timings to the screen */ 1558 if (!intel_sdvo_set_target_output(intel_sdvo, 1559 intel_sdvo_connector->output_flag)) 1560 return; 1561 1562 /* lvds has a special fixed output timing. */ 1563 if (IS_LVDS(intel_sdvo_connector)) { 1564 const struct drm_display_mode *fixed_mode = 1565 intel_panel_fixed_mode(&intel_sdvo_connector->base, mode); 1566 1567 intel_sdvo_get_dtd_from_mode(&output_dtd, fixed_mode); 1568 } else { 1569 intel_sdvo_get_dtd_from_mode(&output_dtd, mode); 1570 } 1571 if (!intel_sdvo_set_output_timing(intel_sdvo, &output_dtd)) 1572 drm_info(display->drm, 1573 "Setting output timings on %s failed\n", 1574 SDVO_NAME(intel_sdvo)); 1575 1576 /* Set the input timing to the screen. Assume always input 0. */ 1577 if (!intel_sdvo_set_target_input(intel_sdvo)) 1578 return; 1579 1580 if (crtc_state->has_hdmi_sink) { 1581 intel_sdvo_set_encode(intel_sdvo, SDVO_ENCODE_HDMI); 1582 intel_sdvo_set_colorimetry(intel_sdvo, 1583 crtc_state->limited_color_range ? 1584 SDVO_COLORIMETRY_RGB220 : 1585 SDVO_COLORIMETRY_RGB256); 1586 intel_sdvo_set_avi_infoframe(intel_sdvo, crtc_state); 1587 intel_sdvo_set_pixel_replication(intel_sdvo, 1588 !!(adjusted_mode->flags & 1589 DRM_MODE_FLAG_DBLCLK)); 1590 } else 1591 intel_sdvo_set_encode(intel_sdvo, SDVO_ENCODE_DVI); 1592 1593 if (IS_TV(intel_sdvo_connector) && 1594 !intel_sdvo_set_tv_format(intel_sdvo, conn_state)) 1595 return; 1596 1597 intel_sdvo_get_dtd_from_mode(&input_dtd, adjusted_mode); 1598 1599 if (IS_TV(intel_sdvo_connector) || IS_LVDS(intel_sdvo_connector)) 1600 input_dtd.part2.sdvo_flags = intel_sdvo->dtd_sdvo_flags; 1601 if (!intel_sdvo_set_input_timing(intel_sdvo, &input_dtd)) 1602 drm_info(display->drm, 1603 "Setting input timings on %s failed\n", 1604 SDVO_NAME(intel_sdvo)); 1605 1606 switch (crtc_state->pixel_multiplier) { 1607 default: 1608 drm_WARN(display->drm, 1, 1609 "unknown pixel multiplier specified\n"); 1610 fallthrough; 1611 case 1: rate = SDVO_CLOCK_RATE_MULT_1X; break; 1612 case 2: rate = SDVO_CLOCK_RATE_MULT_2X; break; 1613 case 4: rate = SDVO_CLOCK_RATE_MULT_4X; break; 1614 } 1615 if (!intel_sdvo_set_clock_rate_mult(intel_sdvo, rate)) 1616 return; 1617 1618 /* Set the SDVO control regs. */ 1619 if (DISPLAY_VER(display) >= 4) { 1620 /* The real mode polarity is set by the SDVO commands, using 1621 * struct intel_sdvo_dtd. */ 1622 sdvox = SDVO_VSYNC_ACTIVE_HIGH | SDVO_HSYNC_ACTIVE_HIGH; 1623 if (DISPLAY_VER(display) < 5) 1624 sdvox |= SDVO_BORDER_ENABLE; 1625 } else { 1626 sdvox = intel_de_read(display, intel_sdvo->sdvo_reg); 1627 if (intel_sdvo->base.port == PORT_B) 1628 sdvox &= SDVOB_PRESERVE_MASK; 1629 else 1630 sdvox &= SDVOC_PRESERVE_MASK; 1631 sdvox |= (9 << 19) | SDVO_BORDER_ENABLE; 1632 } 1633 1634 if (HAS_PCH_CPT(display)) 1635 sdvox |= SDVO_PIPE_SEL_CPT(crtc->pipe); 1636 else 1637 sdvox |= SDVO_PIPE_SEL(crtc->pipe); 1638 1639 if (DISPLAY_VER(display) >= 4) { 1640 /* done in crtc_mode_set as the dpll_md reg must be written early */ 1641 } else if (display->platform.i945g || display->platform.i945gm || 1642 display->platform.g33 || display->platform.pineview) { 1643 /* done in crtc_mode_set as it lives inside the dpll register */ 1644 } else { 1645 sdvox |= (crtc_state->pixel_multiplier - 1) 1646 << SDVO_PORT_MULTIPLY_SHIFT; 1647 } 1648 1649 if (input_dtd.part2.sdvo_flags & SDVO_NEED_TO_STALL && 1650 DISPLAY_VER(display) < 5) 1651 sdvox |= SDVO_STALL_SELECT; 1652 intel_sdvo_write_sdvox(intel_sdvo, sdvox); 1653 } 1654 1655 static bool intel_sdvo_connector_get_hw_state(struct intel_connector *connector) 1656 { 1657 struct intel_sdvo_connector *intel_sdvo_connector = 1658 to_intel_sdvo_connector(&connector->base); 1659 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector); 1660 u16 active_outputs = 0; 1661 1662 intel_sdvo_get_active_outputs(intel_sdvo, &active_outputs); 1663 1664 return active_outputs & intel_sdvo_connector->output_flag; 1665 } 1666 1667 bool intel_sdvo_port_enabled(struct intel_display *display, 1668 i915_reg_t sdvo_reg, enum pipe *pipe) 1669 { 1670 u32 val; 1671 1672 val = intel_de_read(display, sdvo_reg); 1673 1674 /* asserts want to know the pipe even if the port is disabled */ 1675 if (HAS_PCH_CPT(display)) 1676 *pipe = (val & SDVO_PIPE_SEL_MASK_CPT) >> SDVO_PIPE_SEL_SHIFT_CPT; 1677 else if (display->platform.cherryview) 1678 *pipe = (val & SDVO_PIPE_SEL_MASK_CHV) >> SDVO_PIPE_SEL_SHIFT_CHV; 1679 else 1680 *pipe = (val & SDVO_PIPE_SEL_MASK) >> SDVO_PIPE_SEL_SHIFT; 1681 1682 return val & SDVO_ENABLE; 1683 } 1684 1685 static bool intel_sdvo_get_hw_state(struct intel_encoder *encoder, 1686 enum pipe *pipe) 1687 { 1688 struct intel_display *display = to_intel_display(encoder); 1689 struct intel_sdvo *intel_sdvo = to_sdvo(encoder); 1690 u16 active_outputs = 0; 1691 bool ret; 1692 1693 intel_sdvo_get_active_outputs(intel_sdvo, &active_outputs); 1694 1695 ret = intel_sdvo_port_enabled(display, intel_sdvo->sdvo_reg, pipe); 1696 1697 return ret || active_outputs; 1698 } 1699 1700 static void intel_sdvo_get_config(struct intel_encoder *encoder, 1701 struct intel_crtc_state *pipe_config) 1702 { 1703 struct intel_display *display = to_intel_display(encoder); 1704 struct intel_sdvo *intel_sdvo = to_sdvo(encoder); 1705 struct intel_sdvo_dtd dtd; 1706 int encoder_pixel_multiplier = 0; 1707 int dotclock; 1708 u32 flags = 0, sdvox; 1709 u8 val; 1710 bool ret; 1711 1712 pipe_config->output_types |= BIT(INTEL_OUTPUT_SDVO); 1713 1714 sdvox = intel_de_read(display, intel_sdvo->sdvo_reg); 1715 1716 ret = intel_sdvo_get_input_timing(intel_sdvo, &dtd); 1717 if (!ret) { 1718 /* 1719 * Some sdvo encoders are not spec compliant and don't 1720 * implement the mandatory get_timings function. 1721 */ 1722 drm_dbg_kms(display->drm, "failed to retrieve SDVO DTD\n"); 1723 pipe_config->quirks |= PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS; 1724 } else { 1725 if (dtd.part2.dtd_flags & DTD_FLAG_HSYNC_POSITIVE) 1726 flags |= DRM_MODE_FLAG_PHSYNC; 1727 else 1728 flags |= DRM_MODE_FLAG_NHSYNC; 1729 1730 if (dtd.part2.dtd_flags & DTD_FLAG_VSYNC_POSITIVE) 1731 flags |= DRM_MODE_FLAG_PVSYNC; 1732 else 1733 flags |= DRM_MODE_FLAG_NVSYNC; 1734 } 1735 1736 pipe_config->hw.adjusted_mode.flags |= flags; 1737 1738 /* 1739 * pixel multiplier readout is tricky: Only on i915g/gm it is stored in 1740 * the sdvo port register, on all other platforms it is part of the dpll 1741 * state. Since the general pipe state readout happens before the 1742 * encoder->get_config we so already have a valid pixel multiplier on all 1743 * other platforms. 1744 */ 1745 if (display->platform.i915g || display->platform.i915gm) { 1746 pipe_config->pixel_multiplier = 1747 ((sdvox & SDVO_PORT_MULTIPLY_MASK) 1748 >> SDVO_PORT_MULTIPLY_SHIFT) + 1; 1749 } 1750 1751 dotclock = pipe_config->port_clock; 1752 1753 if (pipe_config->pixel_multiplier) 1754 dotclock /= pipe_config->pixel_multiplier; 1755 1756 pipe_config->hw.adjusted_mode.crtc_clock = dotclock; 1757 1758 /* Cross check the port pixel multiplier with the sdvo encoder state. */ 1759 if (intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_CLOCK_RATE_MULT, 1760 &val, 1)) { 1761 switch (val) { 1762 case SDVO_CLOCK_RATE_MULT_1X: 1763 encoder_pixel_multiplier = 1; 1764 break; 1765 case SDVO_CLOCK_RATE_MULT_2X: 1766 encoder_pixel_multiplier = 2; 1767 break; 1768 case SDVO_CLOCK_RATE_MULT_4X: 1769 encoder_pixel_multiplier = 4; 1770 break; 1771 } 1772 } 1773 1774 drm_WARN(display->drm, 1775 encoder_pixel_multiplier != pipe_config->pixel_multiplier, 1776 "SDVO pixel multiplier mismatch, port: %i, encoder: %i\n", 1777 pipe_config->pixel_multiplier, encoder_pixel_multiplier); 1778 1779 if (intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_COLORIMETRY, 1780 &val, 1)) { 1781 if (val == SDVO_COLORIMETRY_RGB220) 1782 pipe_config->limited_color_range = true; 1783 } 1784 1785 if (intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_AUDIO_STAT, 1786 &val, 1)) { 1787 if (val & SDVO_AUDIO_PRESENCE_DETECT) 1788 pipe_config->has_audio = true; 1789 } 1790 1791 if (intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_ENCODE, 1792 &val, 1)) { 1793 if (val == SDVO_ENCODE_HDMI) 1794 pipe_config->has_hdmi_sink = true; 1795 } 1796 1797 intel_sdvo_get_avi_infoframe(intel_sdvo, pipe_config); 1798 1799 intel_sdvo_get_eld(intel_sdvo, pipe_config); 1800 } 1801 1802 static void intel_sdvo_disable_audio(struct intel_encoder *encoder, 1803 const struct intel_crtc_state *old_crtc_state, 1804 const struct drm_connector_state *old_conn_state) 1805 { 1806 struct intel_sdvo *intel_sdvo = to_sdvo(encoder); 1807 1808 if (!old_crtc_state->has_audio) 1809 return; 1810 1811 intel_sdvo_set_audio_state(intel_sdvo, 0); 1812 } 1813 1814 static void intel_sdvo_enable_audio(struct intel_encoder *encoder, 1815 const struct intel_crtc_state *crtc_state, 1816 const struct drm_connector_state *conn_state) 1817 { 1818 struct intel_sdvo *intel_sdvo = to_sdvo(encoder); 1819 const u8 *eld = crtc_state->eld; 1820 1821 if (!crtc_state->has_audio) 1822 return; 1823 1824 intel_sdvo_set_audio_state(intel_sdvo, 0); 1825 1826 intel_sdvo_write_infoframe(intel_sdvo, SDVO_HBUF_INDEX_ELD, 1827 SDVO_HBUF_TX_DISABLED, 1828 eld, drm_eld_size(eld)); 1829 1830 intel_sdvo_set_audio_state(intel_sdvo, SDVO_AUDIO_ELD_VALID | 1831 SDVO_AUDIO_PRESENCE_DETECT); 1832 } 1833 1834 static void intel_disable_sdvo(struct intel_atomic_state *state, 1835 struct intel_encoder *encoder, 1836 const struct intel_crtc_state *old_crtc_state, 1837 const struct drm_connector_state *conn_state) 1838 { 1839 struct intel_display *display = to_intel_display(encoder); 1840 struct intel_sdvo *intel_sdvo = to_sdvo(encoder); 1841 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); 1842 u32 temp; 1843 1844 intel_sdvo_set_active_outputs(intel_sdvo, 0); 1845 if (0) 1846 intel_sdvo_set_encoder_power_state(intel_sdvo, 1847 DRM_MODE_DPMS_OFF); 1848 1849 temp = intel_de_read(display, intel_sdvo->sdvo_reg); 1850 1851 temp &= ~SDVO_ENABLE; 1852 intel_sdvo_write_sdvox(intel_sdvo, temp); 1853 1854 /* 1855 * HW workaround for IBX, we need to move the port 1856 * to transcoder A after disabling it to allow the 1857 * matching DP port to be enabled on transcoder A. 1858 */ 1859 if (HAS_PCH_IBX(display) && crtc->pipe == PIPE_B) { 1860 /* 1861 * We get CPU/PCH FIFO underruns on the other pipe when 1862 * doing the workaround. Sweep them under the rug. 1863 */ 1864 intel_set_cpu_fifo_underrun_reporting(display, PIPE_A, false); 1865 intel_set_pch_fifo_underrun_reporting(display, PIPE_A, false); 1866 1867 temp &= ~SDVO_PIPE_SEL_MASK; 1868 temp |= SDVO_ENABLE | SDVO_PIPE_SEL(PIPE_A); 1869 intel_sdvo_write_sdvox(intel_sdvo, temp); 1870 1871 temp &= ~SDVO_ENABLE; 1872 intel_sdvo_write_sdvox(intel_sdvo, temp); 1873 1874 intel_wait_for_vblank_if_active(display, PIPE_A); 1875 intel_set_cpu_fifo_underrun_reporting(display, PIPE_A, true); 1876 intel_set_pch_fifo_underrun_reporting(display, PIPE_A, true); 1877 } 1878 } 1879 1880 static void pch_disable_sdvo(struct intel_atomic_state *state, 1881 struct intel_encoder *encoder, 1882 const struct intel_crtc_state *old_crtc_state, 1883 const struct drm_connector_state *old_conn_state) 1884 { 1885 } 1886 1887 static void pch_post_disable_sdvo(struct intel_atomic_state *state, 1888 struct intel_encoder *encoder, 1889 const struct intel_crtc_state *old_crtc_state, 1890 const struct drm_connector_state *old_conn_state) 1891 { 1892 intel_disable_sdvo(state, encoder, old_crtc_state, old_conn_state); 1893 } 1894 1895 static void intel_enable_sdvo(struct intel_atomic_state *state, 1896 struct intel_encoder *encoder, 1897 const struct intel_crtc_state *pipe_config, 1898 const struct drm_connector_state *conn_state) 1899 { 1900 struct intel_display *display = to_intel_display(encoder); 1901 struct intel_sdvo *intel_sdvo = to_sdvo(encoder); 1902 struct intel_sdvo_connector *intel_sdvo_connector = 1903 to_intel_sdvo_connector(conn_state->connector); 1904 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 1905 u32 temp; 1906 bool input1, input2; 1907 int i; 1908 bool success; 1909 1910 temp = intel_de_read(display, intel_sdvo->sdvo_reg); 1911 temp |= SDVO_ENABLE; 1912 intel_sdvo_write_sdvox(intel_sdvo, temp); 1913 1914 for (i = 0; i < 2; i++) 1915 intel_crtc_wait_for_next_vblank(crtc); 1916 1917 success = intel_sdvo_get_trained_inputs(intel_sdvo, &input1, &input2); 1918 /* 1919 * Warn if the device reported failure to sync. 1920 * 1921 * A lot of SDVO devices fail to notify of sync, but it's 1922 * a given it the status is a success, we succeeded. 1923 */ 1924 if (success && !input1) { 1925 drm_dbg_kms(display->drm, 1926 "First %s output reported failure to sync\n", 1927 SDVO_NAME(intel_sdvo)); 1928 } 1929 1930 if (0) 1931 intel_sdvo_set_encoder_power_state(intel_sdvo, 1932 DRM_MODE_DPMS_ON); 1933 intel_sdvo_set_active_outputs(intel_sdvo, intel_sdvo_connector->output_flag); 1934 } 1935 1936 static enum drm_mode_status 1937 intel_sdvo_mode_valid(struct drm_connector *connector, 1938 const struct drm_display_mode *mode) 1939 { 1940 struct intel_display *display = to_intel_display(connector->dev); 1941 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(to_intel_connector(connector)); 1942 struct intel_sdvo_connector *intel_sdvo_connector = 1943 to_intel_sdvo_connector(connector); 1944 bool has_hdmi_sink = intel_has_hdmi_sink(intel_sdvo_connector, connector->state); 1945 int max_dotclk = display->cdclk.max_dotclk_freq; 1946 enum drm_mode_status status; 1947 int clock = mode->clock; 1948 1949 status = intel_cpu_transcoder_mode_valid(display, mode); 1950 if (status != MODE_OK) 1951 return status; 1952 1953 if (clock > max_dotclk) 1954 return MODE_CLOCK_HIGH; 1955 1956 if (mode->flags & DRM_MODE_FLAG_DBLCLK) { 1957 if (!has_hdmi_sink) 1958 return MODE_CLOCK_LOW; 1959 clock *= 2; 1960 } 1961 1962 if (intel_sdvo->pixel_clock_min > clock) 1963 return MODE_CLOCK_LOW; 1964 1965 if (intel_sdvo->pixel_clock_max < clock) 1966 return MODE_CLOCK_HIGH; 1967 1968 if (IS_LVDS(intel_sdvo_connector)) { 1969 enum drm_mode_status status; 1970 1971 status = intel_panel_mode_valid(&intel_sdvo_connector->base, mode); 1972 if (status != MODE_OK) 1973 return status; 1974 } 1975 1976 return MODE_OK; 1977 } 1978 1979 static bool intel_sdvo_get_capabilities(struct intel_sdvo *intel_sdvo, struct intel_sdvo_caps *caps) 1980 { 1981 struct intel_display *display = to_intel_display(&intel_sdvo->base); 1982 1983 BUILD_BUG_ON(sizeof(*caps) != 8); 1984 if (!intel_sdvo_get_value(intel_sdvo, 1985 SDVO_CMD_GET_DEVICE_CAPS, 1986 caps, sizeof(*caps))) 1987 return false; 1988 1989 drm_dbg_kms(display->drm, "SDVO capabilities:\n" 1990 " vendor_id: %d\n" 1991 " device_id: %d\n" 1992 " device_rev_id: %d\n" 1993 " sdvo_version_major: %d\n" 1994 " sdvo_version_minor: %d\n" 1995 " sdvo_num_inputs: %d\n" 1996 " smooth_scaling: %d\n" 1997 " sharp_scaling: %d\n" 1998 " up_scaling: %d\n" 1999 " down_scaling: %d\n" 2000 " stall_support: %d\n" 2001 " output_flags: %d\n", 2002 caps->vendor_id, 2003 caps->device_id, 2004 caps->device_rev_id, 2005 caps->sdvo_version_major, 2006 caps->sdvo_version_minor, 2007 caps->sdvo_num_inputs, 2008 caps->smooth_scaling, 2009 caps->sharp_scaling, 2010 caps->up_scaling, 2011 caps->down_scaling, 2012 caps->stall_support, 2013 caps->output_flags); 2014 2015 return true; 2016 } 2017 2018 static u8 intel_sdvo_get_colorimetry_cap(struct intel_sdvo *intel_sdvo) 2019 { 2020 u8 cap; 2021 2022 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_COLORIMETRY_CAP, 2023 &cap, sizeof(cap))) 2024 return SDVO_COLORIMETRY_RGB256; 2025 2026 return cap; 2027 } 2028 2029 static u16 intel_sdvo_get_hotplug_support(struct intel_sdvo *intel_sdvo) 2030 { 2031 struct intel_display *display = to_intel_display(&intel_sdvo->base); 2032 u16 hotplug; 2033 2034 if (!HAS_HOTPLUG(display)) 2035 return 0; 2036 2037 /* 2038 * HW Erratum: SDVO Hotplug is broken on all i945G chips, there's noise 2039 * on the line. 2040 */ 2041 if (display->platform.i945g || display->platform.i945gm) 2042 return 0; 2043 2044 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_HOT_PLUG_SUPPORT, 2045 &hotplug, sizeof(hotplug))) 2046 return 0; 2047 2048 return hotplug; 2049 } 2050 2051 static void intel_sdvo_enable_hotplug(struct intel_encoder *encoder) 2052 { 2053 struct intel_sdvo *intel_sdvo = to_sdvo(encoder); 2054 2055 intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_SET_ACTIVE_HOT_PLUG, 2056 &intel_sdvo->hotplug_active, 2); 2057 } 2058 2059 static enum intel_hotplug_state 2060 intel_sdvo_hotplug(struct intel_encoder *encoder, 2061 struct intel_connector *connector) 2062 { 2063 intel_sdvo_enable_hotplug(encoder); 2064 2065 return intel_encoder_hotplug(encoder, connector); 2066 } 2067 2068 static const struct drm_edid * 2069 intel_sdvo_get_edid(struct drm_connector *connector) 2070 { 2071 struct i2c_adapter *ddc = connector->ddc; 2072 2073 if (!ddc) 2074 return NULL; 2075 2076 return drm_edid_read_ddc(connector, ddc); 2077 } 2078 2079 /* Mac mini hack -- use the same DDC as the analog connector */ 2080 static const struct drm_edid * 2081 intel_sdvo_get_analog_edid(struct drm_connector *connector) 2082 { 2083 struct intel_display *display = to_intel_display(connector->dev); 2084 struct i2c_adapter *ddc; 2085 2086 ddc = intel_gmbus_get_adapter(display, display->vbt.crt_ddc_pin); 2087 if (!ddc) 2088 return NULL; 2089 2090 return drm_edid_read_ddc(connector, ddc); 2091 } 2092 2093 static enum drm_connector_status 2094 intel_sdvo_tmds_sink_detect(struct drm_connector *connector) 2095 { 2096 enum drm_connector_status status; 2097 const struct drm_edid *drm_edid; 2098 2099 drm_edid = intel_sdvo_get_edid(connector); 2100 2101 /* 2102 * When there is no edid and no monitor is connected with VGA 2103 * port, try to use the CRT ddc to read the EDID for DVI-connector. 2104 */ 2105 if (!drm_edid) 2106 drm_edid = intel_sdvo_get_analog_edid(connector); 2107 2108 status = connector_status_unknown; 2109 if (drm_edid) { 2110 /* DDC bus is shared, match EDID to connector type */ 2111 if (drm_edid_is_digital(drm_edid)) 2112 status = connector_status_connected; 2113 else 2114 status = connector_status_disconnected; 2115 drm_edid_free(drm_edid); 2116 } 2117 2118 return status; 2119 } 2120 2121 static bool 2122 intel_sdvo_connector_matches_edid(struct intel_sdvo_connector *sdvo, 2123 const struct drm_edid *drm_edid) 2124 { 2125 bool monitor_is_digital = drm_edid_is_digital(drm_edid); 2126 bool connector_is_digital = !!IS_DIGITAL(sdvo); 2127 2128 drm_dbg_kms(sdvo->base.base.dev, 2129 "connector_is_digital? %d, monitor_is_digital? %d\n", 2130 connector_is_digital, monitor_is_digital); 2131 return connector_is_digital == monitor_is_digital; 2132 } 2133 2134 static enum drm_connector_status 2135 intel_sdvo_detect(struct drm_connector *connector, bool force) 2136 { 2137 struct intel_display *display = to_intel_display(connector->dev); 2138 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(to_intel_connector(connector)); 2139 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector); 2140 enum drm_connector_status ret; 2141 u16 response; 2142 2143 drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s]\n", 2144 connector->base.id, connector->name); 2145 2146 if (!intel_display_device_enabled(display)) 2147 return connector_status_disconnected; 2148 2149 if (!intel_display_driver_check_access(display)) 2150 return connector->status; 2151 2152 if (!intel_sdvo_set_target_output(intel_sdvo, 2153 intel_sdvo_connector->output_flag)) 2154 return connector_status_unknown; 2155 2156 if (!intel_sdvo_get_value(intel_sdvo, 2157 SDVO_CMD_GET_ATTACHED_DISPLAYS, 2158 &response, 2)) 2159 return connector_status_unknown; 2160 2161 drm_dbg_kms(display->drm, "SDVO response %d %d [%x]\n", 2162 response & 0xff, response >> 8, 2163 intel_sdvo_connector->output_flag); 2164 2165 if (response == 0) 2166 return connector_status_disconnected; 2167 2168 if ((intel_sdvo_connector->output_flag & response) == 0) 2169 ret = connector_status_disconnected; 2170 else if (IS_TMDS(intel_sdvo_connector)) 2171 ret = intel_sdvo_tmds_sink_detect(connector); 2172 else { 2173 const struct drm_edid *drm_edid; 2174 2175 /* if we have an edid check it matches the connection */ 2176 drm_edid = intel_sdvo_get_edid(connector); 2177 if (!drm_edid) 2178 drm_edid = intel_sdvo_get_analog_edid(connector); 2179 if (drm_edid) { 2180 if (intel_sdvo_connector_matches_edid(intel_sdvo_connector, 2181 drm_edid)) 2182 ret = connector_status_connected; 2183 else 2184 ret = connector_status_disconnected; 2185 2186 drm_edid_free(drm_edid); 2187 } else { 2188 ret = connector_status_connected; 2189 } 2190 } 2191 2192 return ret; 2193 } 2194 2195 static int intel_sdvo_get_ddc_modes(struct drm_connector *connector) 2196 { 2197 struct intel_display *display = to_intel_display(connector->dev); 2198 int num_modes = 0; 2199 const struct drm_edid *drm_edid; 2200 2201 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s]\n", 2202 connector->base.id, connector->name); 2203 2204 if (!intel_display_driver_check_access(display)) 2205 return drm_edid_connector_add_modes(connector); 2206 2207 /* set the bus switch and get the modes */ 2208 drm_edid = intel_sdvo_get_edid(connector); 2209 2210 /* 2211 * Mac mini hack. On this device, the DVI-I connector shares one DDC 2212 * link between analog and digital outputs. So, if the regular SDVO 2213 * DDC fails, check to see if the analog output is disconnected, in 2214 * which case we'll look there for the digital DDC data. 2215 */ 2216 if (!drm_edid) 2217 drm_edid = intel_sdvo_get_analog_edid(connector); 2218 2219 if (!drm_edid) 2220 return 0; 2221 2222 if (intel_sdvo_connector_matches_edid(to_intel_sdvo_connector(connector), 2223 drm_edid)) 2224 num_modes += intel_connector_update_modes(connector, drm_edid); 2225 2226 drm_edid_free(drm_edid); 2227 2228 return num_modes; 2229 } 2230 2231 /* 2232 * Set of SDVO TV modes. 2233 * Note! This is in reply order (see loop in get_tv_modes). 2234 * XXX: all 60Hz refresh? 2235 */ 2236 static const struct drm_display_mode sdvo_tv_modes[] = { 2237 { DRM_MODE("320x200", DRM_MODE_TYPE_DRIVER, 5815, 320, 321, 384, 2238 416, 0, 200, 201, 232, 233, 0, 2239 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 2240 { DRM_MODE("320x240", DRM_MODE_TYPE_DRIVER, 6814, 320, 321, 384, 2241 416, 0, 240, 241, 272, 273, 0, 2242 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 2243 { DRM_MODE("400x300", DRM_MODE_TYPE_DRIVER, 9910, 400, 401, 464, 2244 496, 0, 300, 301, 332, 333, 0, 2245 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 2246 { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 16913, 640, 641, 704, 2247 736, 0, 350, 351, 382, 383, 0, 2248 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 2249 { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 19121, 640, 641, 704, 2250 736, 0, 400, 401, 432, 433, 0, 2251 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 2252 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 22654, 640, 641, 704, 2253 736, 0, 480, 481, 512, 513, 0, 2254 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 2255 { DRM_MODE("704x480", DRM_MODE_TYPE_DRIVER, 24624, 704, 705, 768, 2256 800, 0, 480, 481, 512, 513, 0, 2257 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 2258 { DRM_MODE("704x576", DRM_MODE_TYPE_DRIVER, 29232, 704, 705, 768, 2259 800, 0, 576, 577, 608, 609, 0, 2260 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 2261 { DRM_MODE("720x350", DRM_MODE_TYPE_DRIVER, 18751, 720, 721, 784, 2262 816, 0, 350, 351, 382, 383, 0, 2263 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 2264 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 21199, 720, 721, 784, 2265 816, 0, 400, 401, 432, 433, 0, 2266 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 2267 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 25116, 720, 721, 784, 2268 816, 0, 480, 481, 512, 513, 0, 2269 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 2270 { DRM_MODE("720x540", DRM_MODE_TYPE_DRIVER, 28054, 720, 721, 784, 2271 816, 0, 540, 541, 572, 573, 0, 2272 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 2273 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 29816, 720, 721, 784, 2274 816, 0, 576, 577, 608, 609, 0, 2275 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 2276 { DRM_MODE("768x576", DRM_MODE_TYPE_DRIVER, 31570, 768, 769, 832, 2277 864, 0, 576, 577, 608, 609, 0, 2278 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 2279 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 34030, 800, 801, 864, 2280 896, 0, 600, 601, 632, 633, 0, 2281 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 2282 { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 36581, 832, 833, 896, 2283 928, 0, 624, 625, 656, 657, 0, 2284 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 2285 { DRM_MODE("920x766", DRM_MODE_TYPE_DRIVER, 48707, 920, 921, 984, 2286 1016, 0, 766, 767, 798, 799, 0, 2287 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 2288 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 53827, 1024, 1025, 1088, 2289 1120, 0, 768, 769, 800, 801, 0, 2290 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 2291 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 87265, 1280, 1281, 1344, 2292 1376, 0, 1024, 1025, 1056, 1057, 0, 2293 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 2294 }; 2295 2296 static int intel_sdvo_get_tv_modes(struct drm_connector *connector) 2297 { 2298 struct intel_display *display = to_intel_display(connector->dev); 2299 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(to_intel_connector(connector)); 2300 struct intel_sdvo_connector *intel_sdvo_connector = 2301 to_intel_sdvo_connector(connector); 2302 const struct drm_connector_state *conn_state = connector->state; 2303 struct intel_sdvo_sdtv_resolution_request tv_res; 2304 u32 reply = 0, format_map = 0; 2305 int num_modes = 0; 2306 int i; 2307 2308 drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s]\n", 2309 connector->base.id, connector->name); 2310 2311 if (!intel_display_driver_check_access(display)) 2312 return 0; 2313 2314 /* 2315 * Read the list of supported input resolutions for the selected TV 2316 * format. 2317 */ 2318 format_map = 1 << conn_state->tv.legacy_mode; 2319 memcpy(&tv_res, &format_map, 2320 min(sizeof(format_map), sizeof(struct intel_sdvo_sdtv_resolution_request))); 2321 2322 if (!intel_sdvo_set_target_output(intel_sdvo, intel_sdvo_connector->output_flag)) 2323 return 0; 2324 2325 BUILD_BUG_ON(sizeof(tv_res) != 3); 2326 if (!intel_sdvo_write_cmd(intel_sdvo, 2327 SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT, 2328 &tv_res, sizeof(tv_res))) 2329 return 0; 2330 if (!intel_sdvo_read_response(intel_sdvo, &reply, 3)) 2331 return 0; 2332 2333 for (i = 0; i < ARRAY_SIZE(sdvo_tv_modes); i++) { 2334 if (reply & (1 << i)) { 2335 struct drm_display_mode *nmode; 2336 nmode = drm_mode_duplicate(connector->dev, 2337 &sdvo_tv_modes[i]); 2338 if (nmode) { 2339 drm_mode_probed_add(connector, nmode); 2340 num_modes++; 2341 } 2342 } 2343 } 2344 2345 return num_modes; 2346 } 2347 2348 static int intel_sdvo_get_lvds_modes(struct drm_connector *connector) 2349 { 2350 struct intel_display *display = to_intel_display(connector->dev); 2351 2352 drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s]\n", 2353 connector->base.id, connector->name); 2354 2355 return intel_panel_get_modes(to_intel_connector(connector)); 2356 } 2357 2358 static int intel_sdvo_get_modes(struct drm_connector *connector) 2359 { 2360 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector); 2361 2362 if (IS_TV(intel_sdvo_connector)) 2363 return intel_sdvo_get_tv_modes(connector); 2364 else if (IS_LVDS(intel_sdvo_connector)) 2365 return intel_sdvo_get_lvds_modes(connector); 2366 else 2367 return intel_sdvo_get_ddc_modes(connector); 2368 } 2369 2370 static int 2371 intel_sdvo_connector_atomic_get_property(struct drm_connector *connector, 2372 const struct drm_connector_state *state, 2373 struct drm_property *property, 2374 u64 *val) 2375 { 2376 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector); 2377 const struct intel_sdvo_connector_state *sdvo_state = to_intel_sdvo_connector_state(state); 2378 2379 if (property == intel_sdvo_connector->tv_format) { 2380 int i; 2381 2382 for (i = 0; i < intel_sdvo_connector->format_supported_num; i++) 2383 if (state->tv.legacy_mode == intel_sdvo_connector->tv_format_supported[i]) { 2384 *val = i; 2385 2386 return 0; 2387 } 2388 2389 drm_WARN_ON(connector->dev, 1); 2390 *val = 0; 2391 } else if (property == intel_sdvo_connector->top || 2392 property == intel_sdvo_connector->bottom) 2393 *val = intel_sdvo_connector->max_vscan - sdvo_state->tv.overscan_v; 2394 else if (property == intel_sdvo_connector->left || 2395 property == intel_sdvo_connector->right) 2396 *val = intel_sdvo_connector->max_hscan - sdvo_state->tv.overscan_h; 2397 else if (property == intel_sdvo_connector->hpos) 2398 *val = sdvo_state->tv.hpos; 2399 else if (property == intel_sdvo_connector->vpos) 2400 *val = sdvo_state->tv.vpos; 2401 else if (property == intel_sdvo_connector->saturation) 2402 *val = state->tv.saturation; 2403 else if (property == intel_sdvo_connector->contrast) 2404 *val = state->tv.contrast; 2405 else if (property == intel_sdvo_connector->hue) 2406 *val = state->tv.hue; 2407 else if (property == intel_sdvo_connector->brightness) 2408 *val = state->tv.brightness; 2409 else if (property == intel_sdvo_connector->sharpness) 2410 *val = sdvo_state->tv.sharpness; 2411 else if (property == intel_sdvo_connector->flicker_filter) 2412 *val = sdvo_state->tv.flicker_filter; 2413 else if (property == intel_sdvo_connector->flicker_filter_2d) 2414 *val = sdvo_state->tv.flicker_filter_2d; 2415 else if (property == intel_sdvo_connector->flicker_filter_adaptive) 2416 *val = sdvo_state->tv.flicker_filter_adaptive; 2417 else if (property == intel_sdvo_connector->tv_chroma_filter) 2418 *val = sdvo_state->tv.chroma_filter; 2419 else if (property == intel_sdvo_connector->tv_luma_filter) 2420 *val = sdvo_state->tv.luma_filter; 2421 else if (property == intel_sdvo_connector->dot_crawl) 2422 *val = sdvo_state->tv.dot_crawl; 2423 else 2424 return intel_digital_connector_atomic_get_property(connector, state, property, val); 2425 2426 return 0; 2427 } 2428 2429 static int 2430 intel_sdvo_connector_atomic_set_property(struct drm_connector *connector, 2431 struct drm_connector_state *state, 2432 struct drm_property *property, 2433 u64 val) 2434 { 2435 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector); 2436 struct intel_sdvo_connector_state *sdvo_state = to_intel_sdvo_connector_state(state); 2437 2438 if (property == intel_sdvo_connector->tv_format) { 2439 state->tv.legacy_mode = intel_sdvo_connector->tv_format_supported[val]; 2440 2441 if (state->crtc) { 2442 struct drm_crtc_state *crtc_state = 2443 drm_atomic_get_new_crtc_state(state->state, state->crtc); 2444 2445 crtc_state->connectors_changed = true; 2446 } 2447 } else if (property == intel_sdvo_connector->top || 2448 property == intel_sdvo_connector->bottom) 2449 /* Cannot set these independent from each other */ 2450 sdvo_state->tv.overscan_v = intel_sdvo_connector->max_vscan - val; 2451 else if (property == intel_sdvo_connector->left || 2452 property == intel_sdvo_connector->right) 2453 /* Cannot set these independent from each other */ 2454 sdvo_state->tv.overscan_h = intel_sdvo_connector->max_hscan - val; 2455 else if (property == intel_sdvo_connector->hpos) 2456 sdvo_state->tv.hpos = val; 2457 else if (property == intel_sdvo_connector->vpos) 2458 sdvo_state->tv.vpos = val; 2459 else if (property == intel_sdvo_connector->saturation) 2460 state->tv.saturation = val; 2461 else if (property == intel_sdvo_connector->contrast) 2462 state->tv.contrast = val; 2463 else if (property == intel_sdvo_connector->hue) 2464 state->tv.hue = val; 2465 else if (property == intel_sdvo_connector->brightness) 2466 state->tv.brightness = val; 2467 else if (property == intel_sdvo_connector->sharpness) 2468 sdvo_state->tv.sharpness = val; 2469 else if (property == intel_sdvo_connector->flicker_filter) 2470 sdvo_state->tv.flicker_filter = val; 2471 else if (property == intel_sdvo_connector->flicker_filter_2d) 2472 sdvo_state->tv.flicker_filter_2d = val; 2473 else if (property == intel_sdvo_connector->flicker_filter_adaptive) 2474 sdvo_state->tv.flicker_filter_adaptive = val; 2475 else if (property == intel_sdvo_connector->tv_chroma_filter) 2476 sdvo_state->tv.chroma_filter = val; 2477 else if (property == intel_sdvo_connector->tv_luma_filter) 2478 sdvo_state->tv.luma_filter = val; 2479 else if (property == intel_sdvo_connector->dot_crawl) 2480 sdvo_state->tv.dot_crawl = val; 2481 else 2482 return intel_digital_connector_atomic_set_property(connector, state, property, val); 2483 2484 return 0; 2485 } 2486 2487 static struct drm_connector_state * 2488 intel_sdvo_connector_duplicate_state(struct drm_connector *connector) 2489 { 2490 struct intel_sdvo_connector_state *state; 2491 2492 state = kmemdup(connector->state, sizeof(*state), GFP_KERNEL); 2493 if (!state) 2494 return NULL; 2495 2496 __drm_atomic_helper_connector_duplicate_state(connector, &state->base.base); 2497 return &state->base.base; 2498 } 2499 2500 static const struct drm_connector_funcs intel_sdvo_connector_funcs = { 2501 .detect = intel_sdvo_detect, 2502 .fill_modes = drm_helper_probe_single_connector_modes, 2503 .atomic_get_property = intel_sdvo_connector_atomic_get_property, 2504 .atomic_set_property = intel_sdvo_connector_atomic_set_property, 2505 .late_register = intel_connector_register, 2506 .early_unregister = intel_connector_unregister, 2507 .destroy = intel_connector_destroy, 2508 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 2509 .atomic_duplicate_state = intel_sdvo_connector_duplicate_state, 2510 }; 2511 2512 static int intel_sdvo_atomic_check(struct drm_connector *conn, 2513 struct drm_atomic_state *state) 2514 { 2515 struct drm_connector_state *new_conn_state = 2516 drm_atomic_get_new_connector_state(state, conn); 2517 struct drm_connector_state *old_conn_state = 2518 drm_atomic_get_old_connector_state(state, conn); 2519 struct intel_sdvo_connector_state *old_state = 2520 to_intel_sdvo_connector_state(old_conn_state); 2521 struct intel_sdvo_connector_state *new_state = 2522 to_intel_sdvo_connector_state(new_conn_state); 2523 2524 if (new_conn_state->crtc && 2525 (memcmp(&old_state->tv, &new_state->tv, sizeof(old_state->tv)) || 2526 memcmp(&old_conn_state->tv, &new_conn_state->tv, sizeof(old_conn_state->tv)))) { 2527 struct drm_crtc_state *crtc_state = 2528 drm_atomic_get_new_crtc_state(state, 2529 new_conn_state->crtc); 2530 2531 crtc_state->connectors_changed = true; 2532 } 2533 2534 return intel_digital_connector_atomic_check(conn, state); 2535 } 2536 2537 static const struct drm_connector_helper_funcs intel_sdvo_connector_helper_funcs = { 2538 .get_modes = intel_sdvo_get_modes, 2539 .mode_valid = intel_sdvo_mode_valid, 2540 .atomic_check = intel_sdvo_atomic_check, 2541 }; 2542 2543 static void intel_sdvo_encoder_destroy(struct drm_encoder *_encoder) 2544 { 2545 struct intel_encoder *encoder = to_intel_encoder(_encoder); 2546 struct intel_sdvo *sdvo = to_sdvo(encoder); 2547 int i; 2548 2549 for (i = 0; i < ARRAY_SIZE(sdvo->ddc); i++) { 2550 if (sdvo->ddc[i].ddc_bus) 2551 i2c_del_adapter(&sdvo->ddc[i].ddc); 2552 } 2553 2554 drm_encoder_cleanup(&encoder->base); 2555 kfree(sdvo); 2556 }; 2557 2558 static const struct drm_encoder_funcs intel_sdvo_enc_funcs = { 2559 .destroy = intel_sdvo_encoder_destroy, 2560 }; 2561 2562 static int 2563 intel_sdvo_guess_ddc_bus(struct intel_sdvo *sdvo, 2564 struct intel_sdvo_connector *connector) 2565 { 2566 u16 mask = 0; 2567 int num_bits; 2568 2569 /* 2570 * Make a mask of outputs less than or equal to our own priority in the 2571 * list. 2572 */ 2573 switch (connector->output_flag) { 2574 case SDVO_OUTPUT_LVDS1: 2575 mask |= SDVO_OUTPUT_LVDS1; 2576 fallthrough; 2577 case SDVO_OUTPUT_LVDS0: 2578 mask |= SDVO_OUTPUT_LVDS0; 2579 fallthrough; 2580 case SDVO_OUTPUT_TMDS1: 2581 mask |= SDVO_OUTPUT_TMDS1; 2582 fallthrough; 2583 case SDVO_OUTPUT_TMDS0: 2584 mask |= SDVO_OUTPUT_TMDS0; 2585 fallthrough; 2586 case SDVO_OUTPUT_RGB1: 2587 mask |= SDVO_OUTPUT_RGB1; 2588 fallthrough; 2589 case SDVO_OUTPUT_RGB0: 2590 mask |= SDVO_OUTPUT_RGB0; 2591 break; 2592 } 2593 2594 /* Count bits to find what number we are in the priority list. */ 2595 mask &= sdvo->caps.output_flags; 2596 num_bits = hweight16(mask); 2597 /* If more than 3 outputs, default to DDC bus 3 for now. */ 2598 if (num_bits > 3) 2599 num_bits = 3; 2600 2601 /* Corresponds to SDVO_CONTROL_BUS_DDCx */ 2602 return num_bits; 2603 } 2604 2605 /* 2606 * Choose the appropriate DDC bus for control bus switch command for this 2607 * SDVO output based on the controlled output. 2608 * 2609 * DDC bus number assignment is in a priority order of RGB outputs, then TMDS 2610 * outputs, then LVDS outputs. 2611 */ 2612 static struct intel_sdvo_ddc * 2613 intel_sdvo_select_ddc_bus(struct intel_sdvo *sdvo, 2614 struct intel_sdvo_connector *connector) 2615 { 2616 struct intel_display *display = to_intel_display(&sdvo->base); 2617 const struct sdvo_device_mapping *mapping; 2618 int ddc_bus; 2619 2620 if (sdvo->base.port == PORT_B) 2621 mapping = &display->vbt.sdvo_mappings[0]; 2622 else 2623 mapping = &display->vbt.sdvo_mappings[1]; 2624 2625 if (mapping->initialized) 2626 ddc_bus = (mapping->ddc_pin & 0xf0) >> 4; 2627 else 2628 ddc_bus = intel_sdvo_guess_ddc_bus(sdvo, connector); 2629 2630 if (ddc_bus < 1 || ddc_bus > 3) 2631 return NULL; 2632 2633 return &sdvo->ddc[ddc_bus - 1]; 2634 } 2635 2636 static void 2637 intel_sdvo_select_i2c_bus(struct intel_sdvo *sdvo) 2638 { 2639 struct intel_display *display = to_intel_display(&sdvo->base); 2640 const struct sdvo_device_mapping *mapping; 2641 u8 pin; 2642 2643 if (sdvo->base.port == PORT_B) 2644 mapping = &display->vbt.sdvo_mappings[0]; 2645 else 2646 mapping = &display->vbt.sdvo_mappings[1]; 2647 2648 if (mapping->initialized && 2649 intel_gmbus_is_valid_pin(display, mapping->i2c_pin)) 2650 pin = mapping->i2c_pin; 2651 else 2652 pin = GMBUS_PIN_DPB; 2653 2654 drm_dbg_kms(display->drm, "[ENCODER:%d:%s] I2C pin %d, target addr 0x%x\n", 2655 sdvo->base.base.base.id, sdvo->base.base.name, 2656 pin, sdvo->target_addr); 2657 2658 sdvo->i2c = intel_gmbus_get_adapter(display, pin); 2659 2660 /* 2661 * With gmbus we should be able to drive sdvo i2c at 2MHz, but somehow 2662 * our code totally fails once we start using gmbus. Hence fall back to 2663 * bit banging for now. 2664 */ 2665 intel_gmbus_force_bit(sdvo->i2c, true); 2666 } 2667 2668 /* undo any changes intel_sdvo_select_i2c_bus() did to sdvo->i2c */ 2669 static void 2670 intel_sdvo_unselect_i2c_bus(struct intel_sdvo *sdvo) 2671 { 2672 intel_gmbus_force_bit(sdvo->i2c, false); 2673 } 2674 2675 static bool 2676 intel_sdvo_is_hdmi_connector(struct intel_sdvo *intel_sdvo) 2677 { 2678 return intel_sdvo_check_supp_encode(intel_sdvo); 2679 } 2680 2681 static u8 2682 intel_sdvo_get_target_addr(struct intel_sdvo *sdvo) 2683 { 2684 struct intel_display *display = to_intel_display(&sdvo->base); 2685 const struct sdvo_device_mapping *my_mapping, *other_mapping; 2686 2687 if (sdvo->base.port == PORT_B) { 2688 my_mapping = &display->vbt.sdvo_mappings[0]; 2689 other_mapping = &display->vbt.sdvo_mappings[1]; 2690 } else { 2691 my_mapping = &display->vbt.sdvo_mappings[1]; 2692 other_mapping = &display->vbt.sdvo_mappings[0]; 2693 } 2694 2695 /* If the BIOS described our SDVO device, take advantage of it. */ 2696 if (my_mapping->target_addr) 2697 return my_mapping->target_addr; 2698 2699 /* 2700 * If the BIOS only described a different SDVO device, use the 2701 * address that it isn't using. 2702 */ 2703 if (other_mapping->target_addr) { 2704 if (other_mapping->target_addr == 0x70) 2705 return 0x72; 2706 else 2707 return 0x70; 2708 } 2709 2710 /* 2711 * No SDVO device info is found for another DVO port, 2712 * so use mapping assumption we had before BIOS parsing. 2713 */ 2714 if (sdvo->base.port == PORT_B) 2715 return 0x70; 2716 else 2717 return 0x72; 2718 } 2719 2720 static int 2721 intel_sdvo_init_ddc_proxy(struct intel_sdvo_ddc *ddc, 2722 struct intel_sdvo *sdvo, int bit); 2723 2724 static int 2725 intel_sdvo_connector_init(struct intel_sdvo_connector *connector, 2726 struct intel_sdvo *encoder) 2727 { 2728 struct intel_display *display = to_intel_display(&encoder->base); 2729 struct intel_sdvo_ddc *ddc = NULL; 2730 int ret; 2731 2732 if (HAS_DDC(connector)) 2733 ddc = intel_sdvo_select_ddc_bus(encoder, connector); 2734 2735 ret = drm_connector_init_with_ddc(encoder->base.base.dev, 2736 &connector->base.base, 2737 &intel_sdvo_connector_funcs, 2738 connector->base.base.connector_type, 2739 ddc ? &ddc->ddc : NULL); 2740 if (ret < 0) 2741 return ret; 2742 2743 drm_connector_helper_add(&connector->base.base, 2744 &intel_sdvo_connector_helper_funcs); 2745 2746 connector->base.base.display_info.subpixel_order = SubPixelHorizontalRGB; 2747 connector->base.base.interlace_allowed = true; 2748 connector->base.get_hw_state = intel_sdvo_connector_get_hw_state; 2749 2750 intel_connector_attach_encoder(&connector->base, &encoder->base); 2751 2752 if (ddc) 2753 drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s] using %s\n", 2754 connector->base.base.base.id, connector->base.base.name, 2755 ddc->ddc.name); 2756 2757 return 0; 2758 } 2759 2760 static void 2761 intel_sdvo_add_hdmi_properties(struct intel_sdvo *intel_sdvo, 2762 struct intel_sdvo_connector *connector) 2763 { 2764 intel_attach_force_audio_property(&connector->base.base); 2765 if (intel_sdvo->colorimetry_cap & SDVO_COLORIMETRY_RGB220) 2766 intel_attach_broadcast_rgb_property(&connector->base.base); 2767 intel_attach_aspect_ratio_property(&connector->base.base); 2768 } 2769 2770 static struct intel_sdvo_connector *intel_sdvo_connector_alloc(void) 2771 { 2772 struct intel_sdvo_connector *sdvo_connector; 2773 struct intel_sdvo_connector_state *conn_state; 2774 2775 sdvo_connector = kzalloc(sizeof(*sdvo_connector), GFP_KERNEL); 2776 if (!sdvo_connector) 2777 return NULL; 2778 2779 conn_state = kzalloc(sizeof(*conn_state), GFP_KERNEL); 2780 if (!conn_state) { 2781 kfree(sdvo_connector); 2782 return NULL; 2783 } 2784 2785 __drm_atomic_helper_connector_reset(&sdvo_connector->base.base, 2786 &conn_state->base.base); 2787 2788 intel_panel_init_alloc(&sdvo_connector->base); 2789 2790 return sdvo_connector; 2791 } 2792 2793 static bool 2794 intel_sdvo_dvi_init(struct intel_sdvo *intel_sdvo, u16 type) 2795 { 2796 struct intel_display *display = to_intel_display(&intel_sdvo->base); 2797 struct drm_encoder *encoder = &intel_sdvo->base.base; 2798 struct drm_connector *connector; 2799 struct intel_encoder *intel_encoder = to_intel_encoder(encoder); 2800 struct intel_connector *intel_connector; 2801 struct intel_sdvo_connector *intel_sdvo_connector; 2802 2803 drm_dbg_kms(display->drm, "initialising DVI type 0x%x\n", type); 2804 2805 intel_sdvo_connector = intel_sdvo_connector_alloc(); 2806 if (!intel_sdvo_connector) 2807 return false; 2808 2809 intel_sdvo_connector->output_flag = type; 2810 2811 intel_connector = &intel_sdvo_connector->base; 2812 connector = &intel_connector->base; 2813 if (intel_sdvo_get_hotplug_support(intel_sdvo) & 2814 intel_sdvo_connector->output_flag) { 2815 intel_sdvo->hotplug_active |= intel_sdvo_connector->output_flag; 2816 /* 2817 * Some SDVO devices have one-shot hotplug interrupts. 2818 * Ensure that they get re-enabled when an interrupt happens. 2819 */ 2820 intel_connector->polled = DRM_CONNECTOR_POLL_HPD; 2821 intel_encoder->hotplug = intel_sdvo_hotplug; 2822 intel_sdvo_enable_hotplug(intel_encoder); 2823 } else { 2824 intel_connector->polled = DRM_CONNECTOR_POLL_CONNECT | DRM_CONNECTOR_POLL_DISCONNECT; 2825 } 2826 intel_connector->base.polled = intel_connector->polled; 2827 encoder->encoder_type = DRM_MODE_ENCODER_TMDS; 2828 connector->connector_type = DRM_MODE_CONNECTOR_DVID; 2829 2830 if (intel_sdvo_is_hdmi_connector(intel_sdvo)) { 2831 connector->connector_type = DRM_MODE_CONNECTOR_HDMIA; 2832 intel_sdvo_connector->is_hdmi = true; 2833 } 2834 2835 if (intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo) < 0) { 2836 kfree(intel_sdvo_connector); 2837 return false; 2838 } 2839 2840 if (intel_sdvo_connector->is_hdmi) 2841 intel_sdvo_add_hdmi_properties(intel_sdvo, intel_sdvo_connector); 2842 2843 return true; 2844 } 2845 2846 static bool 2847 intel_sdvo_tv_init(struct intel_sdvo *intel_sdvo, u16 type) 2848 { 2849 struct intel_display *display = to_intel_display(&intel_sdvo->base); 2850 struct drm_encoder *encoder = &intel_sdvo->base.base; 2851 struct drm_connector *connector; 2852 struct intel_connector *intel_connector; 2853 struct intel_sdvo_connector *intel_sdvo_connector; 2854 2855 drm_dbg_kms(display->drm, "initialising TV type 0x%x\n", type); 2856 2857 intel_sdvo_connector = intel_sdvo_connector_alloc(); 2858 if (!intel_sdvo_connector) 2859 return false; 2860 2861 intel_connector = &intel_sdvo_connector->base; 2862 connector = &intel_connector->base; 2863 encoder->encoder_type = DRM_MODE_ENCODER_TVDAC; 2864 connector->connector_type = DRM_MODE_CONNECTOR_SVIDEO; 2865 2866 intel_sdvo_connector->output_flag = type; 2867 2868 if (intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo) < 0) { 2869 kfree(intel_sdvo_connector); 2870 return false; 2871 } 2872 2873 if (!intel_sdvo_tv_create_property(intel_sdvo, intel_sdvo_connector, type)) 2874 goto err; 2875 2876 if (!intel_sdvo_create_enhance_property(intel_sdvo, intel_sdvo_connector)) 2877 goto err; 2878 2879 return true; 2880 2881 err: 2882 intel_connector_destroy(connector); 2883 return false; 2884 } 2885 2886 static bool 2887 intel_sdvo_analog_init(struct intel_sdvo *intel_sdvo, u16 type) 2888 { 2889 struct intel_display *display = to_intel_display(&intel_sdvo->base); 2890 struct drm_encoder *encoder = &intel_sdvo->base.base; 2891 struct drm_connector *connector; 2892 struct intel_connector *intel_connector; 2893 struct intel_sdvo_connector *intel_sdvo_connector; 2894 2895 drm_dbg_kms(display->drm, "initialising analog type 0x%x\n", type); 2896 2897 intel_sdvo_connector = intel_sdvo_connector_alloc(); 2898 if (!intel_sdvo_connector) 2899 return false; 2900 2901 intel_connector = &intel_sdvo_connector->base; 2902 connector = &intel_connector->base; 2903 intel_connector->polled = DRM_CONNECTOR_POLL_CONNECT; 2904 intel_connector->base.polled = intel_connector->polled; 2905 encoder->encoder_type = DRM_MODE_ENCODER_DAC; 2906 connector->connector_type = DRM_MODE_CONNECTOR_VGA; 2907 2908 intel_sdvo_connector->output_flag = type; 2909 2910 if (intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo) < 0) { 2911 kfree(intel_sdvo_connector); 2912 return false; 2913 } 2914 2915 return true; 2916 } 2917 2918 static bool 2919 intel_sdvo_lvds_init(struct intel_sdvo *intel_sdvo, u16 type) 2920 { 2921 struct intel_display *display = to_intel_display(&intel_sdvo->base); 2922 struct drm_encoder *encoder = &intel_sdvo->base.base; 2923 struct drm_connector *connector; 2924 struct intel_connector *intel_connector; 2925 struct intel_sdvo_connector *intel_sdvo_connector; 2926 2927 drm_dbg_kms(display->drm, "initialising LVDS type 0x%x\n", type); 2928 2929 intel_sdvo_connector = intel_sdvo_connector_alloc(); 2930 if (!intel_sdvo_connector) 2931 return false; 2932 2933 intel_connector = &intel_sdvo_connector->base; 2934 connector = &intel_connector->base; 2935 encoder->encoder_type = DRM_MODE_ENCODER_LVDS; 2936 connector->connector_type = DRM_MODE_CONNECTOR_LVDS; 2937 2938 intel_sdvo_connector->output_flag = type; 2939 2940 if (intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo) < 0) { 2941 kfree(intel_sdvo_connector); 2942 return false; 2943 } 2944 2945 if (!intel_sdvo_create_enhance_property(intel_sdvo, intel_sdvo_connector)) 2946 goto err; 2947 2948 intel_bios_init_panel_late(display, &intel_connector->panel, NULL, NULL); 2949 2950 /* 2951 * Fetch modes from VBT. For SDVO prefer the VBT mode since some 2952 * SDVO->LVDS transcoders can't cope with the EDID mode. 2953 */ 2954 intel_panel_add_vbt_sdvo_fixed_mode(intel_connector); 2955 2956 if (!intel_panel_preferred_fixed_mode(intel_connector)) { 2957 mutex_lock(&display->drm->mode_config.mutex); 2958 2959 intel_ddc_get_modes(connector, connector->ddc); 2960 intel_panel_add_edid_fixed_modes(intel_connector, false); 2961 2962 mutex_unlock(&display->drm->mode_config.mutex); 2963 } 2964 2965 intel_panel_init(intel_connector, NULL); 2966 2967 if (!intel_panel_preferred_fixed_mode(intel_connector)) 2968 goto err; 2969 2970 return true; 2971 2972 err: 2973 intel_connector_destroy(connector); 2974 return false; 2975 } 2976 2977 static u16 intel_sdvo_filter_output_flags(u16 flags) 2978 { 2979 flags &= SDVO_OUTPUT_MASK; 2980 2981 /* SDVO requires XXX1 function may not exist unless it has XXX0 function.*/ 2982 if (!(flags & SDVO_OUTPUT_TMDS0)) 2983 flags &= ~SDVO_OUTPUT_TMDS1; 2984 2985 if (!(flags & SDVO_OUTPUT_RGB0)) 2986 flags &= ~SDVO_OUTPUT_RGB1; 2987 2988 if (!(flags & SDVO_OUTPUT_LVDS0)) 2989 flags &= ~SDVO_OUTPUT_LVDS1; 2990 2991 return flags; 2992 } 2993 2994 static bool intel_sdvo_output_init(struct intel_sdvo *sdvo, u16 type) 2995 { 2996 if (type & SDVO_TMDS_MASK) 2997 return intel_sdvo_dvi_init(sdvo, type); 2998 else if (type & SDVO_TV_MASK) 2999 return intel_sdvo_tv_init(sdvo, type); 3000 else if (type & SDVO_RGB_MASK) 3001 return intel_sdvo_analog_init(sdvo, type); 3002 else if (type & SDVO_LVDS_MASK) 3003 return intel_sdvo_lvds_init(sdvo, type); 3004 else 3005 return false; 3006 } 3007 3008 static bool 3009 intel_sdvo_output_setup(struct intel_sdvo *intel_sdvo) 3010 { 3011 struct intel_display *display = to_intel_display(&intel_sdvo->base); 3012 static const u16 probe_order[] = { 3013 SDVO_OUTPUT_TMDS0, 3014 SDVO_OUTPUT_TMDS1, 3015 /* TV has no XXX1 function block */ 3016 SDVO_OUTPUT_SVID0, 3017 SDVO_OUTPUT_CVBS0, 3018 SDVO_OUTPUT_YPRPB0, 3019 SDVO_OUTPUT_RGB0, 3020 SDVO_OUTPUT_RGB1, 3021 SDVO_OUTPUT_LVDS0, 3022 SDVO_OUTPUT_LVDS1, 3023 }; 3024 u16 flags; 3025 int i; 3026 3027 flags = intel_sdvo_filter_output_flags(intel_sdvo->caps.output_flags); 3028 3029 if (flags == 0) { 3030 drm_dbg_kms(display->drm, 3031 "%s: Unknown SDVO output type (0x%04x)\n", 3032 SDVO_NAME(intel_sdvo), intel_sdvo->caps.output_flags); 3033 return false; 3034 } 3035 3036 for (i = 0; i < ARRAY_SIZE(probe_order); i++) { 3037 u16 type = flags & probe_order[i]; 3038 3039 if (!type) 3040 continue; 3041 3042 if (!intel_sdvo_output_init(intel_sdvo, type)) 3043 return false; 3044 } 3045 3046 intel_sdvo->base.pipe_mask = ~0; 3047 3048 return true; 3049 } 3050 3051 static void intel_sdvo_output_cleanup(struct intel_sdvo *intel_sdvo) 3052 { 3053 struct intel_display *display = to_intel_display(&intel_sdvo->base); 3054 struct drm_connector *connector, *tmp; 3055 3056 list_for_each_entry_safe(connector, tmp, 3057 &display->drm->mode_config.connector_list, head) { 3058 if (intel_attached_encoder(to_intel_connector(connector)) == &intel_sdvo->base) { 3059 drm_connector_unregister(connector); 3060 intel_connector_destroy(connector); 3061 } 3062 } 3063 } 3064 3065 static bool intel_sdvo_tv_create_property(struct intel_sdvo *intel_sdvo, 3066 struct intel_sdvo_connector *intel_sdvo_connector, 3067 int type) 3068 { 3069 struct intel_display *display = to_intel_display(&intel_sdvo->base); 3070 struct intel_sdvo_tv_format format; 3071 u32 format_map, i; 3072 3073 if (!intel_sdvo_set_target_output(intel_sdvo, type)) 3074 return false; 3075 3076 BUILD_BUG_ON(sizeof(format) != 6); 3077 if (!intel_sdvo_get_value(intel_sdvo, 3078 SDVO_CMD_GET_SUPPORTED_TV_FORMATS, 3079 &format, sizeof(format))) 3080 return false; 3081 3082 memcpy(&format_map, &format, min(sizeof(format_map), sizeof(format))); 3083 3084 if (format_map == 0) 3085 return false; 3086 3087 intel_sdvo_connector->format_supported_num = 0; 3088 for (i = 0 ; i < TV_FORMAT_NUM; i++) 3089 if (format_map & (1 << i)) 3090 intel_sdvo_connector->tv_format_supported[intel_sdvo_connector->format_supported_num++] = i; 3091 3092 3093 intel_sdvo_connector->tv_format = 3094 drm_property_create(display->drm, DRM_MODE_PROP_ENUM, 3095 "mode", intel_sdvo_connector->format_supported_num); 3096 if (!intel_sdvo_connector->tv_format) 3097 return false; 3098 3099 for (i = 0; i < intel_sdvo_connector->format_supported_num; i++) 3100 drm_property_add_enum(intel_sdvo_connector->tv_format, i, 3101 tv_format_names[intel_sdvo_connector->tv_format_supported[i]]); 3102 3103 intel_sdvo_connector->base.base.state->tv.legacy_mode = intel_sdvo_connector->tv_format_supported[0]; 3104 drm_object_attach_property(&intel_sdvo_connector->base.base.base, 3105 intel_sdvo_connector->tv_format, 0); 3106 return true; 3107 3108 } 3109 3110 #define _ENHANCEMENT(state_assignment, name, NAME) do { \ 3111 if (enhancements.name) { \ 3112 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_MAX_##NAME, &data_value, 4) || \ 3113 !intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_##NAME, &response, 2)) \ 3114 return false; \ 3115 intel_sdvo_connector->name = \ 3116 drm_property_create_range(display->drm, 0, #name, 0, data_value[0]); \ 3117 if (!intel_sdvo_connector->name) return false; \ 3118 state_assignment = response; \ 3119 drm_object_attach_property(&connector->base, \ 3120 intel_sdvo_connector->name, 0); \ 3121 drm_dbg_kms(display->drm, #name ": max %d, default %d, current %d\n", \ 3122 data_value[0], data_value[1], response); \ 3123 } \ 3124 } while (0) 3125 3126 #define ENHANCEMENT(state, name, NAME) _ENHANCEMENT((state)->name, name, NAME) 3127 3128 static bool 3129 intel_sdvo_create_enhance_property_tv(struct intel_sdvo *intel_sdvo, 3130 struct intel_sdvo_connector *intel_sdvo_connector, 3131 struct intel_sdvo_enhancements_reply enhancements) 3132 { 3133 struct intel_display *display = to_intel_display(&intel_sdvo->base); 3134 struct drm_connector *connector = &intel_sdvo_connector->base.base; 3135 struct drm_connector_state *conn_state = connector->state; 3136 struct intel_sdvo_connector_state *sdvo_state = 3137 to_intel_sdvo_connector_state(conn_state); 3138 u16 response, data_value[2]; 3139 3140 /* when horizontal overscan is supported, Add the left/right property */ 3141 if (enhancements.overscan_h) { 3142 if (!intel_sdvo_get_value(intel_sdvo, 3143 SDVO_CMD_GET_MAX_OVERSCAN_H, 3144 &data_value, 4)) 3145 return false; 3146 3147 if (!intel_sdvo_get_value(intel_sdvo, 3148 SDVO_CMD_GET_OVERSCAN_H, 3149 &response, 2)) 3150 return false; 3151 3152 sdvo_state->tv.overscan_h = response; 3153 3154 intel_sdvo_connector->max_hscan = data_value[0]; 3155 intel_sdvo_connector->left = 3156 drm_property_create_range(display->drm, 0, "left_margin", 0, data_value[0]); 3157 if (!intel_sdvo_connector->left) 3158 return false; 3159 3160 drm_object_attach_property(&connector->base, 3161 intel_sdvo_connector->left, 0); 3162 3163 intel_sdvo_connector->right = 3164 drm_property_create_range(display->drm, 0, "right_margin", 0, data_value[0]); 3165 if (!intel_sdvo_connector->right) 3166 return false; 3167 3168 drm_object_attach_property(&connector->base, 3169 intel_sdvo_connector->right, 0); 3170 drm_dbg_kms(display->drm, "h_overscan: max %d, default %d, current %d\n", 3171 data_value[0], data_value[1], response); 3172 } 3173 3174 if (enhancements.overscan_v) { 3175 if (!intel_sdvo_get_value(intel_sdvo, 3176 SDVO_CMD_GET_MAX_OVERSCAN_V, 3177 &data_value, 4)) 3178 return false; 3179 3180 if (!intel_sdvo_get_value(intel_sdvo, 3181 SDVO_CMD_GET_OVERSCAN_V, 3182 &response, 2)) 3183 return false; 3184 3185 sdvo_state->tv.overscan_v = response; 3186 3187 intel_sdvo_connector->max_vscan = data_value[0]; 3188 intel_sdvo_connector->top = 3189 drm_property_create_range(display->drm, 0, 3190 "top_margin", 0, data_value[0]); 3191 if (!intel_sdvo_connector->top) 3192 return false; 3193 3194 drm_object_attach_property(&connector->base, 3195 intel_sdvo_connector->top, 0); 3196 3197 intel_sdvo_connector->bottom = 3198 drm_property_create_range(display->drm, 0, 3199 "bottom_margin", 0, data_value[0]); 3200 if (!intel_sdvo_connector->bottom) 3201 return false; 3202 3203 drm_object_attach_property(&connector->base, 3204 intel_sdvo_connector->bottom, 0); 3205 drm_dbg_kms(display->drm, "v_overscan: max %d, default %d, current %d\n", 3206 data_value[0], data_value[1], response); 3207 } 3208 3209 ENHANCEMENT(&sdvo_state->tv, hpos, HPOS); 3210 ENHANCEMENT(&sdvo_state->tv, vpos, VPOS); 3211 ENHANCEMENT(&conn_state->tv, saturation, SATURATION); 3212 ENHANCEMENT(&conn_state->tv, contrast, CONTRAST); 3213 ENHANCEMENT(&conn_state->tv, hue, HUE); 3214 ENHANCEMENT(&conn_state->tv, brightness, BRIGHTNESS); 3215 ENHANCEMENT(&sdvo_state->tv, sharpness, SHARPNESS); 3216 ENHANCEMENT(&sdvo_state->tv, flicker_filter, FLICKER_FILTER); 3217 ENHANCEMENT(&sdvo_state->tv, flicker_filter_adaptive, FLICKER_FILTER_ADAPTIVE); 3218 ENHANCEMENT(&sdvo_state->tv, flicker_filter_2d, FLICKER_FILTER_2D); 3219 _ENHANCEMENT(sdvo_state->tv.chroma_filter, tv_chroma_filter, TV_CHROMA_FILTER); 3220 _ENHANCEMENT(sdvo_state->tv.luma_filter, tv_luma_filter, TV_LUMA_FILTER); 3221 3222 if (enhancements.dot_crawl) { 3223 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_DOT_CRAWL, &response, 2)) 3224 return false; 3225 3226 sdvo_state->tv.dot_crawl = response & 0x1; 3227 intel_sdvo_connector->dot_crawl = 3228 drm_property_create_range(display->drm, 0, "dot_crawl", 0, 1); 3229 if (!intel_sdvo_connector->dot_crawl) 3230 return false; 3231 3232 drm_object_attach_property(&connector->base, 3233 intel_sdvo_connector->dot_crawl, 0); 3234 drm_dbg_kms(display->drm, "dot crawl: current %d\n", response); 3235 } 3236 3237 return true; 3238 } 3239 3240 static bool 3241 intel_sdvo_create_enhance_property_lvds(struct intel_sdvo *intel_sdvo, 3242 struct intel_sdvo_connector *intel_sdvo_connector, 3243 struct intel_sdvo_enhancements_reply enhancements) 3244 { 3245 struct intel_display *display = to_intel_display(&intel_sdvo->base); 3246 struct drm_connector *connector = &intel_sdvo_connector->base.base; 3247 u16 response, data_value[2]; 3248 3249 ENHANCEMENT(&connector->state->tv, brightness, BRIGHTNESS); 3250 3251 return true; 3252 } 3253 #undef ENHANCEMENT 3254 #undef _ENHANCEMENT 3255 3256 static bool intel_sdvo_create_enhance_property(struct intel_sdvo *intel_sdvo, 3257 struct intel_sdvo_connector *intel_sdvo_connector) 3258 { 3259 struct intel_display *display = to_intel_display(&intel_sdvo->base); 3260 union { 3261 struct intel_sdvo_enhancements_reply reply; 3262 u16 response; 3263 } enhancements; 3264 3265 BUILD_BUG_ON(sizeof(enhancements) != 2); 3266 3267 if (!intel_sdvo_get_value(intel_sdvo, 3268 SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS, 3269 &enhancements, sizeof(enhancements)) || 3270 enhancements.response == 0) { 3271 drm_dbg_kms(display->drm, "No enhancement is supported\n"); 3272 return true; 3273 } 3274 3275 if (IS_TV(intel_sdvo_connector)) 3276 return intel_sdvo_create_enhance_property_tv(intel_sdvo, intel_sdvo_connector, enhancements.reply); 3277 else if (IS_LVDS(intel_sdvo_connector)) 3278 return intel_sdvo_create_enhance_property_lvds(intel_sdvo, intel_sdvo_connector, enhancements.reply); 3279 else 3280 return true; 3281 } 3282 3283 static int intel_sdvo_ddc_proxy_xfer(struct i2c_adapter *adapter, 3284 struct i2c_msg *msgs, 3285 int num) 3286 { 3287 struct intel_sdvo_ddc *ddc = adapter->algo_data; 3288 struct intel_sdvo *sdvo = ddc->sdvo; 3289 3290 if (!__intel_sdvo_set_control_bus_switch(sdvo, 1 << ddc->ddc_bus)) 3291 return -EIO; 3292 3293 return sdvo->i2c->algo->master_xfer(sdvo->i2c, msgs, num); 3294 } 3295 3296 static u32 intel_sdvo_ddc_proxy_func(struct i2c_adapter *adapter) 3297 { 3298 struct intel_sdvo_ddc *ddc = adapter->algo_data; 3299 struct intel_sdvo *sdvo = ddc->sdvo; 3300 3301 return sdvo->i2c->algo->functionality(sdvo->i2c); 3302 } 3303 3304 static const struct i2c_algorithm intel_sdvo_ddc_proxy = { 3305 .master_xfer = intel_sdvo_ddc_proxy_xfer, 3306 .functionality = intel_sdvo_ddc_proxy_func 3307 }; 3308 3309 static void proxy_lock_bus(struct i2c_adapter *adapter, 3310 unsigned int flags) 3311 { 3312 struct intel_sdvo_ddc *ddc = adapter->algo_data; 3313 struct intel_sdvo *sdvo = ddc->sdvo; 3314 3315 sdvo->i2c->lock_ops->lock_bus(sdvo->i2c, flags); 3316 } 3317 3318 static int proxy_trylock_bus(struct i2c_adapter *adapter, 3319 unsigned int flags) 3320 { 3321 struct intel_sdvo_ddc *ddc = adapter->algo_data; 3322 struct intel_sdvo *sdvo = ddc->sdvo; 3323 3324 return sdvo->i2c->lock_ops->trylock_bus(sdvo->i2c, flags); 3325 } 3326 3327 static void proxy_unlock_bus(struct i2c_adapter *adapter, 3328 unsigned int flags) 3329 { 3330 struct intel_sdvo_ddc *ddc = adapter->algo_data; 3331 struct intel_sdvo *sdvo = ddc->sdvo; 3332 3333 sdvo->i2c->lock_ops->unlock_bus(sdvo->i2c, flags); 3334 } 3335 3336 static const struct i2c_lock_operations proxy_lock_ops = { 3337 .lock_bus = proxy_lock_bus, 3338 .trylock_bus = proxy_trylock_bus, 3339 .unlock_bus = proxy_unlock_bus, 3340 }; 3341 3342 static int 3343 intel_sdvo_init_ddc_proxy(struct intel_sdvo_ddc *ddc, 3344 struct intel_sdvo *sdvo, int ddc_bus) 3345 { 3346 struct intel_display *display = to_intel_display(&sdvo->base); 3347 struct pci_dev *pdev = to_pci_dev(display->drm->dev); 3348 3349 ddc->sdvo = sdvo; 3350 ddc->ddc_bus = ddc_bus; 3351 3352 ddc->ddc.owner = THIS_MODULE; 3353 snprintf(ddc->ddc.name, I2C_NAME_SIZE, "SDVO %c DDC%d", 3354 port_name(sdvo->base.port), ddc_bus); 3355 ddc->ddc.dev.parent = &pdev->dev; 3356 ddc->ddc.algo_data = ddc; 3357 ddc->ddc.algo = &intel_sdvo_ddc_proxy; 3358 ddc->ddc.lock_ops = &proxy_lock_ops; 3359 3360 return i2c_add_adapter(&ddc->ddc); 3361 } 3362 3363 static bool is_sdvo_port_valid(struct intel_display *display, enum port port) 3364 { 3365 if (HAS_PCH_SPLIT(display)) 3366 return port == PORT_B; 3367 else 3368 return port == PORT_B || port == PORT_C; 3369 } 3370 3371 static bool assert_sdvo_port_valid(struct intel_display *display, enum port port) 3372 { 3373 return !drm_WARN(display->drm, !is_sdvo_port_valid(display, port), 3374 "Platform does not support SDVO %c\n", port_name(port)); 3375 } 3376 3377 bool intel_sdvo_init(struct intel_display *display, 3378 i915_reg_t sdvo_reg, enum port port) 3379 { 3380 struct intel_encoder *intel_encoder; 3381 struct intel_sdvo *intel_sdvo; 3382 int i; 3383 3384 if (!assert_port_valid(display, port)) 3385 return false; 3386 3387 if (!assert_sdvo_port_valid(display, port)) 3388 return false; 3389 3390 intel_sdvo = kzalloc(sizeof(*intel_sdvo), GFP_KERNEL); 3391 if (!intel_sdvo) 3392 return false; 3393 3394 /* encoder type will be decided later */ 3395 intel_encoder = &intel_sdvo->base; 3396 intel_encoder->type = INTEL_OUTPUT_SDVO; 3397 intel_encoder->power_domain = POWER_DOMAIN_PORT_OTHER; 3398 intel_encoder->port = port; 3399 3400 drm_encoder_init(display->drm, &intel_encoder->base, 3401 &intel_sdvo_enc_funcs, 0, 3402 "SDVO %c", port_name(port)); 3403 3404 intel_sdvo->sdvo_reg = sdvo_reg; 3405 intel_sdvo->target_addr = intel_sdvo_get_target_addr(intel_sdvo) >> 1; 3406 3407 intel_sdvo_select_i2c_bus(intel_sdvo); 3408 3409 /* Read the regs to test if we can talk to the device */ 3410 for (i = 0; i < 0x40; i++) { 3411 u8 byte; 3412 3413 if (!intel_sdvo_read_byte(intel_sdvo, i, &byte)) { 3414 drm_dbg_kms(display->drm, 3415 "No SDVO device found on %s\n", 3416 SDVO_NAME(intel_sdvo)); 3417 goto err; 3418 } 3419 } 3420 3421 intel_encoder->compute_config = intel_sdvo_compute_config; 3422 if (HAS_PCH_SPLIT(display)) { 3423 intel_encoder->disable = pch_disable_sdvo; 3424 intel_encoder->post_disable = pch_post_disable_sdvo; 3425 } else { 3426 intel_encoder->disable = intel_disable_sdvo; 3427 } 3428 intel_encoder->pre_enable = intel_sdvo_pre_enable; 3429 intel_encoder->enable = intel_enable_sdvo; 3430 intel_encoder->audio_enable = intel_sdvo_enable_audio; 3431 intel_encoder->audio_disable = intel_sdvo_disable_audio; 3432 intel_encoder->get_hw_state = intel_sdvo_get_hw_state; 3433 intel_encoder->get_config = intel_sdvo_get_config; 3434 3435 /* In default case sdvo lvds is false */ 3436 if (!intel_sdvo_get_capabilities(intel_sdvo, &intel_sdvo->caps)) 3437 goto err; 3438 3439 intel_sdvo->colorimetry_cap = 3440 intel_sdvo_get_colorimetry_cap(intel_sdvo); 3441 3442 for (i = 0; i < ARRAY_SIZE(intel_sdvo->ddc); i++) { 3443 int ret; 3444 3445 ret = intel_sdvo_init_ddc_proxy(&intel_sdvo->ddc[i], 3446 intel_sdvo, i + 1); 3447 if (ret) 3448 goto err; 3449 } 3450 3451 if (!intel_sdvo_output_setup(intel_sdvo)) { 3452 drm_dbg_kms(display->drm, 3453 "SDVO output failed to setup on %s\n", 3454 SDVO_NAME(intel_sdvo)); 3455 /* Output_setup can leave behind connectors! */ 3456 goto err_output; 3457 } 3458 3459 /* 3460 * Only enable the hotplug irq if we need it, to work around noisy 3461 * hotplug lines. 3462 */ 3463 if (intel_sdvo->hotplug_active) { 3464 if (intel_sdvo->base.port == PORT_B) 3465 intel_encoder->hpd_pin = HPD_SDVO_B; 3466 else 3467 intel_encoder->hpd_pin = HPD_SDVO_C; 3468 } 3469 3470 /* 3471 * Cloning SDVO with anything is often impossible, since the SDVO 3472 * encoder can request a special input timing mode. And even if that's 3473 * not the case we have evidence that cloning a plain unscaled mode with 3474 * VGA doesn't really work. Furthermore the cloning flags are way too 3475 * simplistic anyway to express such constraints, so just give up on 3476 * cloning for SDVO encoders. 3477 */ 3478 intel_sdvo->base.cloneable = 0; 3479 3480 /* Set the input timing to the screen. Assume always input 0. */ 3481 if (!intel_sdvo_set_target_input(intel_sdvo)) 3482 goto err_output; 3483 3484 if (!intel_sdvo_get_input_pixel_clock_range(intel_sdvo, 3485 &intel_sdvo->pixel_clock_min, 3486 &intel_sdvo->pixel_clock_max)) 3487 goto err_output; 3488 3489 drm_dbg_kms(display->drm, "%s device VID/DID: %02X:%02X.%02X, " 3490 "clock range %dMHz - %dMHz, " 3491 "num inputs: %d, " 3492 "output 1: %c, output 2: %c\n", 3493 SDVO_NAME(intel_sdvo), 3494 intel_sdvo->caps.vendor_id, intel_sdvo->caps.device_id, 3495 intel_sdvo->caps.device_rev_id, 3496 intel_sdvo->pixel_clock_min / 1000, 3497 intel_sdvo->pixel_clock_max / 1000, 3498 intel_sdvo->caps.sdvo_num_inputs, 3499 /* check currently supported outputs */ 3500 intel_sdvo->caps.output_flags & 3501 (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_RGB0 | 3502 SDVO_OUTPUT_LVDS0 | SDVO_OUTPUT_SVID0 | 3503 SDVO_OUTPUT_CVBS0 | SDVO_OUTPUT_YPRPB0) ? 'Y' : 'N', 3504 intel_sdvo->caps.output_flags & 3505 (SDVO_OUTPUT_TMDS1 | SDVO_OUTPUT_RGB1 | 3506 SDVO_OUTPUT_LVDS1) ? 'Y' : 'N'); 3507 return true; 3508 3509 err_output: 3510 intel_sdvo_output_cleanup(intel_sdvo); 3511 err: 3512 intel_sdvo_unselect_i2c_bus(intel_sdvo); 3513 intel_sdvo_encoder_destroy(&intel_encoder->base); 3514 3515 return false; 3516 } 3517