1 /* 2 * Copyright 2006 Dave Airlie <airlied@linux.ie> 3 * Copyright © 2006-2007 Intel Corporation 4 * Jesse Barnes <jesse.barnes@intel.com> 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice (including the next 14 * paragraph) shall be included in all copies or substantial portions of the 15 * Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 23 * DEALINGS IN THE SOFTWARE. 24 * 25 * Authors: 26 * Eric Anholt <eric@anholt.net> 27 */ 28 29 #include <linux/delay.h> 30 #include <linux/export.h> 31 #include <linux/i2c.h> 32 #include <linux/slab.h> 33 34 #include <drm/drm_atomic_helper.h> 35 #include <drm/drm_crtc.h> 36 #include <drm/drm_edid.h> 37 38 #include "i915_drv.h" 39 #include "intel_atomic.h" 40 #include "intel_connector.h" 41 #include "intel_display_types.h" 42 #include "intel_fifo_underrun.h" 43 #include "intel_gmbus.h" 44 #include "intel_hdmi.h" 45 #include "intel_hotplug.h" 46 #include "intel_panel.h" 47 #include "intel_sdvo.h" 48 #include "intel_sdvo_regs.h" 49 50 #define SDVO_TMDS_MASK (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_TMDS1) 51 #define SDVO_RGB_MASK (SDVO_OUTPUT_RGB0 | SDVO_OUTPUT_RGB1) 52 #define SDVO_LVDS_MASK (SDVO_OUTPUT_LVDS0 | SDVO_OUTPUT_LVDS1) 53 #define SDVO_TV_MASK (SDVO_OUTPUT_CVBS0 | SDVO_OUTPUT_SVID0 | SDVO_OUTPUT_YPRPB0) 54 55 #define SDVO_OUTPUT_MASK (SDVO_TMDS_MASK | SDVO_RGB_MASK | SDVO_LVDS_MASK |\ 56 SDVO_TV_MASK) 57 58 #define IS_TV(c) (c->output_flag & SDVO_TV_MASK) 59 #define IS_TMDS(c) (c->output_flag & SDVO_TMDS_MASK) 60 #define IS_LVDS(c) (c->output_flag & SDVO_LVDS_MASK) 61 #define IS_TV_OR_LVDS(c) (c->output_flag & (SDVO_TV_MASK | SDVO_LVDS_MASK)) 62 #define IS_DIGITAL(c) (c->output_flag & (SDVO_TMDS_MASK | SDVO_LVDS_MASK)) 63 64 65 static const char * const tv_format_names[] = { 66 "NTSC_M" , "NTSC_J" , "NTSC_443", 67 "PAL_B" , "PAL_D" , "PAL_G" , 68 "PAL_H" , "PAL_I" , "PAL_M" , 69 "PAL_N" , "PAL_NC" , "PAL_60" , 70 "SECAM_B" , "SECAM_D" , "SECAM_G" , 71 "SECAM_K" , "SECAM_K1", "SECAM_L" , 72 "SECAM_60" 73 }; 74 75 #define TV_FORMAT_NUM ARRAY_SIZE(tv_format_names) 76 77 struct intel_sdvo { 78 struct intel_encoder base; 79 80 struct i2c_adapter *i2c; 81 u8 slave_addr; 82 83 struct i2c_adapter ddc; 84 85 /* Register for the SDVO device: SDVOB or SDVOC */ 86 i915_reg_t sdvo_reg; 87 88 /* Active outputs controlled by this SDVO output */ 89 u16 controlled_output; 90 91 /* 92 * Capabilities of the SDVO device returned by 93 * intel_sdvo_get_capabilities() 94 */ 95 struct intel_sdvo_caps caps; 96 97 /* Pixel clock limitations reported by the SDVO device, in kHz */ 98 int pixel_clock_min, pixel_clock_max; 99 100 /* 101 * For multiple function SDVO device, 102 * this is for current attached outputs. 103 */ 104 u16 attached_output; 105 106 /* 107 * Hotplug activation bits for this device 108 */ 109 u16 hotplug_active; 110 111 enum port port; 112 113 bool has_hdmi_monitor; 114 bool has_hdmi_audio; 115 116 /* DDC bus used by this SDVO encoder */ 117 u8 ddc_bus; 118 119 /* 120 * the sdvo flag gets lost in round trip: dtd->adjusted_mode->dtd 121 */ 122 u8 dtd_sdvo_flags; 123 }; 124 125 struct intel_sdvo_connector { 126 struct intel_connector base; 127 128 /* Mark the type of connector */ 129 u16 output_flag; 130 131 /* This contains all current supported TV format */ 132 u8 tv_format_supported[TV_FORMAT_NUM]; 133 int format_supported_num; 134 struct drm_property *tv_format; 135 136 /* add the property for the SDVO-TV */ 137 struct drm_property *left; 138 struct drm_property *right; 139 struct drm_property *top; 140 struct drm_property *bottom; 141 struct drm_property *hpos; 142 struct drm_property *vpos; 143 struct drm_property *contrast; 144 struct drm_property *saturation; 145 struct drm_property *hue; 146 struct drm_property *sharpness; 147 struct drm_property *flicker_filter; 148 struct drm_property *flicker_filter_adaptive; 149 struct drm_property *flicker_filter_2d; 150 struct drm_property *tv_chroma_filter; 151 struct drm_property *tv_luma_filter; 152 struct drm_property *dot_crawl; 153 154 /* add the property for the SDVO-TV/LVDS */ 155 struct drm_property *brightness; 156 157 /* this is to get the range of margin.*/ 158 u32 max_hscan, max_vscan; 159 160 /** 161 * This is set if we treat the device as HDMI, instead of DVI. 162 */ 163 bool is_hdmi; 164 }; 165 166 struct intel_sdvo_connector_state { 167 /* base.base: tv.saturation/contrast/hue/brightness */ 168 struct intel_digital_connector_state base; 169 170 struct { 171 unsigned overscan_h, overscan_v, hpos, vpos, sharpness; 172 unsigned flicker_filter, flicker_filter_2d, flicker_filter_adaptive; 173 unsigned chroma_filter, luma_filter, dot_crawl; 174 } tv; 175 }; 176 177 static struct intel_sdvo *to_sdvo(struct intel_encoder *encoder) 178 { 179 return container_of(encoder, struct intel_sdvo, base); 180 } 181 182 static struct intel_sdvo *intel_attached_sdvo(struct intel_connector *connector) 183 { 184 return to_sdvo(intel_attached_encoder(connector)); 185 } 186 187 static struct intel_sdvo_connector * 188 to_intel_sdvo_connector(struct drm_connector *connector) 189 { 190 return container_of(connector, struct intel_sdvo_connector, base.base); 191 } 192 193 #define to_intel_sdvo_connector_state(conn_state) \ 194 container_of((conn_state), struct intel_sdvo_connector_state, base.base) 195 196 static bool 197 intel_sdvo_output_setup(struct intel_sdvo *intel_sdvo, u16 flags); 198 static bool 199 intel_sdvo_tv_create_property(struct intel_sdvo *intel_sdvo, 200 struct intel_sdvo_connector *intel_sdvo_connector, 201 int type); 202 static bool 203 intel_sdvo_create_enhance_property(struct intel_sdvo *intel_sdvo, 204 struct intel_sdvo_connector *intel_sdvo_connector); 205 206 /* 207 * Writes the SDVOB or SDVOC with the given value, but always writes both 208 * SDVOB and SDVOC to work around apparent hardware issues (according to 209 * comments in the BIOS). 210 */ 211 static void intel_sdvo_write_sdvox(struct intel_sdvo *intel_sdvo, u32 val) 212 { 213 struct drm_device *dev = intel_sdvo->base.base.dev; 214 struct drm_i915_private *dev_priv = to_i915(dev); 215 u32 bval = val, cval = val; 216 int i; 217 218 if (HAS_PCH_SPLIT(dev_priv)) { 219 intel_de_write(dev_priv, intel_sdvo->sdvo_reg, val); 220 intel_de_posting_read(dev_priv, intel_sdvo->sdvo_reg); 221 /* 222 * HW workaround, need to write this twice for issue 223 * that may result in first write getting masked. 224 */ 225 if (HAS_PCH_IBX(dev_priv)) { 226 intel_de_write(dev_priv, intel_sdvo->sdvo_reg, val); 227 intel_de_posting_read(dev_priv, intel_sdvo->sdvo_reg); 228 } 229 return; 230 } 231 232 if (intel_sdvo->port == PORT_B) 233 cval = intel_de_read(dev_priv, GEN3_SDVOC); 234 else 235 bval = intel_de_read(dev_priv, GEN3_SDVOB); 236 237 /* 238 * Write the registers twice for luck. Sometimes, 239 * writing them only once doesn't appear to 'stick'. 240 * The BIOS does this too. Yay, magic 241 */ 242 for (i = 0; i < 2; i++) { 243 intel_de_write(dev_priv, GEN3_SDVOB, bval); 244 intel_de_posting_read(dev_priv, GEN3_SDVOB); 245 246 intel_de_write(dev_priv, GEN3_SDVOC, cval); 247 intel_de_posting_read(dev_priv, GEN3_SDVOC); 248 } 249 } 250 251 static bool intel_sdvo_read_byte(struct intel_sdvo *intel_sdvo, u8 addr, u8 *ch) 252 { 253 struct i2c_msg msgs[] = { 254 { 255 .addr = intel_sdvo->slave_addr, 256 .flags = 0, 257 .len = 1, 258 .buf = &addr, 259 }, 260 { 261 .addr = intel_sdvo->slave_addr, 262 .flags = I2C_M_RD, 263 .len = 1, 264 .buf = ch, 265 } 266 }; 267 int ret; 268 269 if ((ret = i2c_transfer(intel_sdvo->i2c, msgs, 2)) == 2) 270 return true; 271 272 DRM_DEBUG_KMS("i2c transfer returned %d\n", ret); 273 return false; 274 } 275 276 #define SDVO_CMD_NAME_ENTRY(cmd_) { .cmd = SDVO_CMD_ ## cmd_, .name = #cmd_ } 277 278 /** Mapping of command numbers to names, for debug output */ 279 static const struct { 280 u8 cmd; 281 const char *name; 282 } __attribute__ ((packed)) sdvo_cmd_names[] = { 283 SDVO_CMD_NAME_ENTRY(RESET), 284 SDVO_CMD_NAME_ENTRY(GET_DEVICE_CAPS), 285 SDVO_CMD_NAME_ENTRY(GET_FIRMWARE_REV), 286 SDVO_CMD_NAME_ENTRY(GET_TRAINED_INPUTS), 287 SDVO_CMD_NAME_ENTRY(GET_ACTIVE_OUTPUTS), 288 SDVO_CMD_NAME_ENTRY(SET_ACTIVE_OUTPUTS), 289 SDVO_CMD_NAME_ENTRY(GET_IN_OUT_MAP), 290 SDVO_CMD_NAME_ENTRY(SET_IN_OUT_MAP), 291 SDVO_CMD_NAME_ENTRY(GET_ATTACHED_DISPLAYS), 292 SDVO_CMD_NAME_ENTRY(GET_HOT_PLUG_SUPPORT), 293 SDVO_CMD_NAME_ENTRY(SET_ACTIVE_HOT_PLUG), 294 SDVO_CMD_NAME_ENTRY(GET_ACTIVE_HOT_PLUG), 295 SDVO_CMD_NAME_ENTRY(GET_INTERRUPT_EVENT_SOURCE), 296 SDVO_CMD_NAME_ENTRY(SET_TARGET_INPUT), 297 SDVO_CMD_NAME_ENTRY(SET_TARGET_OUTPUT), 298 SDVO_CMD_NAME_ENTRY(GET_INPUT_TIMINGS_PART1), 299 SDVO_CMD_NAME_ENTRY(GET_INPUT_TIMINGS_PART2), 300 SDVO_CMD_NAME_ENTRY(SET_INPUT_TIMINGS_PART1), 301 SDVO_CMD_NAME_ENTRY(SET_INPUT_TIMINGS_PART2), 302 SDVO_CMD_NAME_ENTRY(SET_OUTPUT_TIMINGS_PART1), 303 SDVO_CMD_NAME_ENTRY(SET_OUTPUT_TIMINGS_PART2), 304 SDVO_CMD_NAME_ENTRY(GET_OUTPUT_TIMINGS_PART1), 305 SDVO_CMD_NAME_ENTRY(GET_OUTPUT_TIMINGS_PART2), 306 SDVO_CMD_NAME_ENTRY(CREATE_PREFERRED_INPUT_TIMING), 307 SDVO_CMD_NAME_ENTRY(GET_PREFERRED_INPUT_TIMING_PART1), 308 SDVO_CMD_NAME_ENTRY(GET_PREFERRED_INPUT_TIMING_PART2), 309 SDVO_CMD_NAME_ENTRY(GET_INPUT_PIXEL_CLOCK_RANGE), 310 SDVO_CMD_NAME_ENTRY(GET_OUTPUT_PIXEL_CLOCK_RANGE), 311 SDVO_CMD_NAME_ENTRY(GET_SUPPORTED_CLOCK_RATE_MULTS), 312 SDVO_CMD_NAME_ENTRY(GET_CLOCK_RATE_MULT), 313 SDVO_CMD_NAME_ENTRY(SET_CLOCK_RATE_MULT), 314 SDVO_CMD_NAME_ENTRY(GET_SUPPORTED_TV_FORMATS), 315 SDVO_CMD_NAME_ENTRY(GET_TV_FORMAT), 316 SDVO_CMD_NAME_ENTRY(SET_TV_FORMAT), 317 SDVO_CMD_NAME_ENTRY(GET_SUPPORTED_POWER_STATES), 318 SDVO_CMD_NAME_ENTRY(GET_POWER_STATE), 319 SDVO_CMD_NAME_ENTRY(SET_ENCODER_POWER_STATE), 320 SDVO_CMD_NAME_ENTRY(SET_DISPLAY_POWER_STATE), 321 SDVO_CMD_NAME_ENTRY(SET_CONTROL_BUS_SWITCH), 322 SDVO_CMD_NAME_ENTRY(GET_SDTV_RESOLUTION_SUPPORT), 323 SDVO_CMD_NAME_ENTRY(GET_SCALED_HDTV_RESOLUTION_SUPPORT), 324 SDVO_CMD_NAME_ENTRY(GET_SUPPORTED_ENHANCEMENTS), 325 326 /* Add the op code for SDVO enhancements */ 327 SDVO_CMD_NAME_ENTRY(GET_MAX_HPOS), 328 SDVO_CMD_NAME_ENTRY(GET_HPOS), 329 SDVO_CMD_NAME_ENTRY(SET_HPOS), 330 SDVO_CMD_NAME_ENTRY(GET_MAX_VPOS), 331 SDVO_CMD_NAME_ENTRY(GET_VPOS), 332 SDVO_CMD_NAME_ENTRY(SET_VPOS), 333 SDVO_CMD_NAME_ENTRY(GET_MAX_SATURATION), 334 SDVO_CMD_NAME_ENTRY(GET_SATURATION), 335 SDVO_CMD_NAME_ENTRY(SET_SATURATION), 336 SDVO_CMD_NAME_ENTRY(GET_MAX_HUE), 337 SDVO_CMD_NAME_ENTRY(GET_HUE), 338 SDVO_CMD_NAME_ENTRY(SET_HUE), 339 SDVO_CMD_NAME_ENTRY(GET_MAX_CONTRAST), 340 SDVO_CMD_NAME_ENTRY(GET_CONTRAST), 341 SDVO_CMD_NAME_ENTRY(SET_CONTRAST), 342 SDVO_CMD_NAME_ENTRY(GET_MAX_BRIGHTNESS), 343 SDVO_CMD_NAME_ENTRY(GET_BRIGHTNESS), 344 SDVO_CMD_NAME_ENTRY(SET_BRIGHTNESS), 345 SDVO_CMD_NAME_ENTRY(GET_MAX_OVERSCAN_H), 346 SDVO_CMD_NAME_ENTRY(GET_OVERSCAN_H), 347 SDVO_CMD_NAME_ENTRY(SET_OVERSCAN_H), 348 SDVO_CMD_NAME_ENTRY(GET_MAX_OVERSCAN_V), 349 SDVO_CMD_NAME_ENTRY(GET_OVERSCAN_V), 350 SDVO_CMD_NAME_ENTRY(SET_OVERSCAN_V), 351 SDVO_CMD_NAME_ENTRY(GET_MAX_FLICKER_FILTER), 352 SDVO_CMD_NAME_ENTRY(GET_FLICKER_FILTER), 353 SDVO_CMD_NAME_ENTRY(SET_FLICKER_FILTER), 354 SDVO_CMD_NAME_ENTRY(GET_MAX_FLICKER_FILTER_ADAPTIVE), 355 SDVO_CMD_NAME_ENTRY(GET_FLICKER_FILTER_ADAPTIVE), 356 SDVO_CMD_NAME_ENTRY(SET_FLICKER_FILTER_ADAPTIVE), 357 SDVO_CMD_NAME_ENTRY(GET_MAX_FLICKER_FILTER_2D), 358 SDVO_CMD_NAME_ENTRY(GET_FLICKER_FILTER_2D), 359 SDVO_CMD_NAME_ENTRY(SET_FLICKER_FILTER_2D), 360 SDVO_CMD_NAME_ENTRY(GET_MAX_SHARPNESS), 361 SDVO_CMD_NAME_ENTRY(GET_SHARPNESS), 362 SDVO_CMD_NAME_ENTRY(SET_SHARPNESS), 363 SDVO_CMD_NAME_ENTRY(GET_DOT_CRAWL), 364 SDVO_CMD_NAME_ENTRY(SET_DOT_CRAWL), 365 SDVO_CMD_NAME_ENTRY(GET_MAX_TV_CHROMA_FILTER), 366 SDVO_CMD_NAME_ENTRY(GET_TV_CHROMA_FILTER), 367 SDVO_CMD_NAME_ENTRY(SET_TV_CHROMA_FILTER), 368 SDVO_CMD_NAME_ENTRY(GET_MAX_TV_LUMA_FILTER), 369 SDVO_CMD_NAME_ENTRY(GET_TV_LUMA_FILTER), 370 SDVO_CMD_NAME_ENTRY(SET_TV_LUMA_FILTER), 371 372 /* HDMI op code */ 373 SDVO_CMD_NAME_ENTRY(GET_SUPP_ENCODE), 374 SDVO_CMD_NAME_ENTRY(GET_ENCODE), 375 SDVO_CMD_NAME_ENTRY(SET_ENCODE), 376 SDVO_CMD_NAME_ENTRY(SET_PIXEL_REPLI), 377 SDVO_CMD_NAME_ENTRY(GET_PIXEL_REPLI), 378 SDVO_CMD_NAME_ENTRY(GET_COLORIMETRY_CAP), 379 SDVO_CMD_NAME_ENTRY(SET_COLORIMETRY), 380 SDVO_CMD_NAME_ENTRY(GET_COLORIMETRY), 381 SDVO_CMD_NAME_ENTRY(GET_AUDIO_ENCRYPT_PREFER), 382 SDVO_CMD_NAME_ENTRY(SET_AUDIO_STAT), 383 SDVO_CMD_NAME_ENTRY(GET_AUDIO_STAT), 384 SDVO_CMD_NAME_ENTRY(GET_HBUF_INDEX), 385 SDVO_CMD_NAME_ENTRY(SET_HBUF_INDEX), 386 SDVO_CMD_NAME_ENTRY(GET_HBUF_INFO), 387 SDVO_CMD_NAME_ENTRY(GET_HBUF_AV_SPLIT), 388 SDVO_CMD_NAME_ENTRY(SET_HBUF_AV_SPLIT), 389 SDVO_CMD_NAME_ENTRY(GET_HBUF_TXRATE), 390 SDVO_CMD_NAME_ENTRY(SET_HBUF_TXRATE), 391 SDVO_CMD_NAME_ENTRY(SET_HBUF_DATA), 392 SDVO_CMD_NAME_ENTRY(GET_HBUF_DATA), 393 }; 394 395 #undef SDVO_CMD_NAME_ENTRY 396 397 static const char *sdvo_cmd_name(u8 cmd) 398 { 399 int i; 400 401 for (i = 0; i < ARRAY_SIZE(sdvo_cmd_names); i++) { 402 if (cmd == sdvo_cmd_names[i].cmd) 403 return sdvo_cmd_names[i].name; 404 } 405 406 return NULL; 407 } 408 409 #define SDVO_NAME(svdo) ((svdo)->port == PORT_B ? "SDVOB" : "SDVOC") 410 411 static void intel_sdvo_debug_write(struct intel_sdvo *intel_sdvo, u8 cmd, 412 const void *args, int args_len) 413 { 414 struct drm_i915_private *dev_priv = to_i915(intel_sdvo->base.base.dev); 415 const char *cmd_name; 416 int i, pos = 0; 417 char buffer[64]; 418 419 #define BUF_PRINT(args...) \ 420 pos += snprintf(buffer + pos, max_t(int, sizeof(buffer) - pos, 0), args) 421 422 for (i = 0; i < args_len; i++) { 423 BUF_PRINT("%02X ", ((u8 *)args)[i]); 424 } 425 for (; i < 8; i++) { 426 BUF_PRINT(" "); 427 } 428 429 cmd_name = sdvo_cmd_name(cmd); 430 if (cmd_name) 431 BUF_PRINT("(%s)", cmd_name); 432 else 433 BUF_PRINT("(%02X)", cmd); 434 435 drm_WARN_ON(&dev_priv->drm, pos >= sizeof(buffer) - 1); 436 #undef BUF_PRINT 437 438 DRM_DEBUG_KMS("%s: W: %02X %s\n", SDVO_NAME(intel_sdvo), cmd, buffer); 439 } 440 441 static const char * const cmd_status_names[] = { 442 [SDVO_CMD_STATUS_POWER_ON] = "Power on", 443 [SDVO_CMD_STATUS_SUCCESS] = "Success", 444 [SDVO_CMD_STATUS_NOTSUPP] = "Not supported", 445 [SDVO_CMD_STATUS_INVALID_ARG] = "Invalid arg", 446 [SDVO_CMD_STATUS_PENDING] = "Pending", 447 [SDVO_CMD_STATUS_TARGET_NOT_SPECIFIED] = "Target not specified", 448 [SDVO_CMD_STATUS_SCALING_NOT_SUPP] = "Scaling not supported", 449 }; 450 451 static const char *sdvo_cmd_status(u8 status) 452 { 453 if (status < ARRAY_SIZE(cmd_status_names)) 454 return cmd_status_names[status]; 455 else 456 return NULL; 457 } 458 459 static bool __intel_sdvo_write_cmd(struct intel_sdvo *intel_sdvo, u8 cmd, 460 const void *args, int args_len, 461 bool unlocked) 462 { 463 u8 *buf, status; 464 struct i2c_msg *msgs; 465 int i, ret = true; 466 467 /* Would be simpler to allocate both in one go ? */ 468 buf = kzalloc(args_len * 2 + 2, GFP_KERNEL); 469 if (!buf) 470 return false; 471 472 msgs = kcalloc(args_len + 3, sizeof(*msgs), GFP_KERNEL); 473 if (!msgs) { 474 kfree(buf); 475 return false; 476 } 477 478 intel_sdvo_debug_write(intel_sdvo, cmd, args, args_len); 479 480 for (i = 0; i < args_len; i++) { 481 msgs[i].addr = intel_sdvo->slave_addr; 482 msgs[i].flags = 0; 483 msgs[i].len = 2; 484 msgs[i].buf = buf + 2 *i; 485 buf[2*i + 0] = SDVO_I2C_ARG_0 - i; 486 buf[2*i + 1] = ((u8*)args)[i]; 487 } 488 msgs[i].addr = intel_sdvo->slave_addr; 489 msgs[i].flags = 0; 490 msgs[i].len = 2; 491 msgs[i].buf = buf + 2*i; 492 buf[2*i + 0] = SDVO_I2C_OPCODE; 493 buf[2*i + 1] = cmd; 494 495 /* the following two are to read the response */ 496 status = SDVO_I2C_CMD_STATUS; 497 msgs[i+1].addr = intel_sdvo->slave_addr; 498 msgs[i+1].flags = 0; 499 msgs[i+1].len = 1; 500 msgs[i+1].buf = &status; 501 502 msgs[i+2].addr = intel_sdvo->slave_addr; 503 msgs[i+2].flags = I2C_M_RD; 504 msgs[i+2].len = 1; 505 msgs[i+2].buf = &status; 506 507 if (unlocked) 508 ret = i2c_transfer(intel_sdvo->i2c, msgs, i+3); 509 else 510 ret = __i2c_transfer(intel_sdvo->i2c, msgs, i+3); 511 if (ret < 0) { 512 DRM_DEBUG_KMS("I2c transfer returned %d\n", ret); 513 ret = false; 514 goto out; 515 } 516 if (ret != i+3) { 517 /* failure in I2C transfer */ 518 DRM_DEBUG_KMS("I2c transfer returned %d/%d\n", ret, i+3); 519 ret = false; 520 } 521 522 out: 523 kfree(msgs); 524 kfree(buf); 525 return ret; 526 } 527 528 static bool intel_sdvo_write_cmd(struct intel_sdvo *intel_sdvo, u8 cmd, 529 const void *args, int args_len) 530 { 531 return __intel_sdvo_write_cmd(intel_sdvo, cmd, args, args_len, true); 532 } 533 534 static bool intel_sdvo_read_response(struct intel_sdvo *intel_sdvo, 535 void *response, int response_len) 536 { 537 struct drm_i915_private *dev_priv = to_i915(intel_sdvo->base.base.dev); 538 const char *cmd_status; 539 u8 retry = 15; /* 5 quick checks, followed by 10 long checks */ 540 u8 status; 541 int i, pos = 0; 542 char buffer[64]; 543 544 buffer[0] = '\0'; 545 546 /* 547 * The documentation states that all commands will be 548 * processed within 15µs, and that we need only poll 549 * the status byte a maximum of 3 times in order for the 550 * command to be complete. 551 * 552 * Check 5 times in case the hardware failed to read the docs. 553 * 554 * Also beware that the first response by many devices is to 555 * reply PENDING and stall for time. TVs are notorious for 556 * requiring longer than specified to complete their replies. 557 * Originally (in the DDX long ago), the delay was only ever 15ms 558 * with an additional delay of 30ms applied for TVs added later after 559 * many experiments. To accommodate both sets of delays, we do a 560 * sequence of slow checks if the device is falling behind and fails 561 * to reply within 5*15µs. 562 */ 563 if (!intel_sdvo_read_byte(intel_sdvo, 564 SDVO_I2C_CMD_STATUS, 565 &status)) 566 goto log_fail; 567 568 while ((status == SDVO_CMD_STATUS_PENDING || 569 status == SDVO_CMD_STATUS_TARGET_NOT_SPECIFIED) && --retry) { 570 if (retry < 10) 571 msleep(15); 572 else 573 udelay(15); 574 575 if (!intel_sdvo_read_byte(intel_sdvo, 576 SDVO_I2C_CMD_STATUS, 577 &status)) 578 goto log_fail; 579 } 580 581 #define BUF_PRINT(args...) \ 582 pos += snprintf(buffer + pos, max_t(int, sizeof(buffer) - pos, 0), args) 583 584 cmd_status = sdvo_cmd_status(status); 585 if (cmd_status) 586 BUF_PRINT("(%s)", cmd_status); 587 else 588 BUF_PRINT("(??? %d)", status); 589 590 if (status != SDVO_CMD_STATUS_SUCCESS) 591 goto log_fail; 592 593 /* Read the command response */ 594 for (i = 0; i < response_len; i++) { 595 if (!intel_sdvo_read_byte(intel_sdvo, 596 SDVO_I2C_RETURN_0 + i, 597 &((u8 *)response)[i])) 598 goto log_fail; 599 BUF_PRINT(" %02X", ((u8 *)response)[i]); 600 } 601 602 drm_WARN_ON(&dev_priv->drm, pos >= sizeof(buffer) - 1); 603 #undef BUF_PRINT 604 605 DRM_DEBUG_KMS("%s: R: %s\n", SDVO_NAME(intel_sdvo), buffer); 606 return true; 607 608 log_fail: 609 DRM_DEBUG_KMS("%s: R: ... failed %s\n", 610 SDVO_NAME(intel_sdvo), buffer); 611 return false; 612 } 613 614 static int intel_sdvo_get_pixel_multiplier(const struct drm_display_mode *adjusted_mode) 615 { 616 if (adjusted_mode->crtc_clock >= 100000) 617 return 1; 618 else if (adjusted_mode->crtc_clock >= 50000) 619 return 2; 620 else 621 return 4; 622 } 623 624 static bool __intel_sdvo_set_control_bus_switch(struct intel_sdvo *intel_sdvo, 625 u8 ddc_bus) 626 { 627 /* This must be the immediately preceding write before the i2c xfer */ 628 return __intel_sdvo_write_cmd(intel_sdvo, 629 SDVO_CMD_SET_CONTROL_BUS_SWITCH, 630 &ddc_bus, 1, false); 631 } 632 633 static bool intel_sdvo_set_value(struct intel_sdvo *intel_sdvo, u8 cmd, const void *data, int len) 634 { 635 if (!intel_sdvo_write_cmd(intel_sdvo, cmd, data, len)) 636 return false; 637 638 return intel_sdvo_read_response(intel_sdvo, NULL, 0); 639 } 640 641 static bool 642 intel_sdvo_get_value(struct intel_sdvo *intel_sdvo, u8 cmd, void *value, int len) 643 { 644 if (!intel_sdvo_write_cmd(intel_sdvo, cmd, NULL, 0)) 645 return false; 646 647 return intel_sdvo_read_response(intel_sdvo, value, len); 648 } 649 650 static bool intel_sdvo_set_target_input(struct intel_sdvo *intel_sdvo) 651 { 652 struct intel_sdvo_set_target_input_args targets = {0}; 653 return intel_sdvo_set_value(intel_sdvo, 654 SDVO_CMD_SET_TARGET_INPUT, 655 &targets, sizeof(targets)); 656 } 657 658 /* 659 * Return whether each input is trained. 660 * 661 * This function is making an assumption about the layout of the response, 662 * which should be checked against the docs. 663 */ 664 static bool intel_sdvo_get_trained_inputs(struct intel_sdvo *intel_sdvo, bool *input_1, bool *input_2) 665 { 666 struct intel_sdvo_get_trained_inputs_response response; 667 668 BUILD_BUG_ON(sizeof(response) != 1); 669 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_TRAINED_INPUTS, 670 &response, sizeof(response))) 671 return false; 672 673 *input_1 = response.input0_trained; 674 *input_2 = response.input1_trained; 675 return true; 676 } 677 678 static bool intel_sdvo_set_active_outputs(struct intel_sdvo *intel_sdvo, 679 u16 outputs) 680 { 681 return intel_sdvo_set_value(intel_sdvo, 682 SDVO_CMD_SET_ACTIVE_OUTPUTS, 683 &outputs, sizeof(outputs)); 684 } 685 686 static bool intel_sdvo_get_active_outputs(struct intel_sdvo *intel_sdvo, 687 u16 *outputs) 688 { 689 return intel_sdvo_get_value(intel_sdvo, 690 SDVO_CMD_GET_ACTIVE_OUTPUTS, 691 outputs, sizeof(*outputs)); 692 } 693 694 static bool intel_sdvo_set_encoder_power_state(struct intel_sdvo *intel_sdvo, 695 int mode) 696 { 697 u8 state = SDVO_ENCODER_STATE_ON; 698 699 switch (mode) { 700 case DRM_MODE_DPMS_ON: 701 state = SDVO_ENCODER_STATE_ON; 702 break; 703 case DRM_MODE_DPMS_STANDBY: 704 state = SDVO_ENCODER_STATE_STANDBY; 705 break; 706 case DRM_MODE_DPMS_SUSPEND: 707 state = SDVO_ENCODER_STATE_SUSPEND; 708 break; 709 case DRM_MODE_DPMS_OFF: 710 state = SDVO_ENCODER_STATE_OFF; 711 break; 712 } 713 714 return intel_sdvo_set_value(intel_sdvo, 715 SDVO_CMD_SET_ENCODER_POWER_STATE, &state, sizeof(state)); 716 } 717 718 static bool intel_sdvo_get_input_pixel_clock_range(struct intel_sdvo *intel_sdvo, 719 int *clock_min, 720 int *clock_max) 721 { 722 struct intel_sdvo_pixel_clock_range clocks; 723 724 BUILD_BUG_ON(sizeof(clocks) != 4); 725 if (!intel_sdvo_get_value(intel_sdvo, 726 SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE, 727 &clocks, sizeof(clocks))) 728 return false; 729 730 /* Convert the values from units of 10 kHz to kHz. */ 731 *clock_min = clocks.min * 10; 732 *clock_max = clocks.max * 10; 733 return true; 734 } 735 736 static bool intel_sdvo_set_target_output(struct intel_sdvo *intel_sdvo, 737 u16 outputs) 738 { 739 return intel_sdvo_set_value(intel_sdvo, 740 SDVO_CMD_SET_TARGET_OUTPUT, 741 &outputs, sizeof(outputs)); 742 } 743 744 static bool intel_sdvo_set_timing(struct intel_sdvo *intel_sdvo, u8 cmd, 745 struct intel_sdvo_dtd *dtd) 746 { 747 return intel_sdvo_set_value(intel_sdvo, cmd, &dtd->part1, sizeof(dtd->part1)) && 748 intel_sdvo_set_value(intel_sdvo, cmd + 1, &dtd->part2, sizeof(dtd->part2)); 749 } 750 751 static bool intel_sdvo_get_timing(struct intel_sdvo *intel_sdvo, u8 cmd, 752 struct intel_sdvo_dtd *dtd) 753 { 754 return intel_sdvo_get_value(intel_sdvo, cmd, &dtd->part1, sizeof(dtd->part1)) && 755 intel_sdvo_get_value(intel_sdvo, cmd + 1, &dtd->part2, sizeof(dtd->part2)); 756 } 757 758 static bool intel_sdvo_set_input_timing(struct intel_sdvo *intel_sdvo, 759 struct intel_sdvo_dtd *dtd) 760 { 761 return intel_sdvo_set_timing(intel_sdvo, 762 SDVO_CMD_SET_INPUT_TIMINGS_PART1, dtd); 763 } 764 765 static bool intel_sdvo_set_output_timing(struct intel_sdvo *intel_sdvo, 766 struct intel_sdvo_dtd *dtd) 767 { 768 return intel_sdvo_set_timing(intel_sdvo, 769 SDVO_CMD_SET_OUTPUT_TIMINGS_PART1, dtd); 770 } 771 772 static bool intel_sdvo_get_input_timing(struct intel_sdvo *intel_sdvo, 773 struct intel_sdvo_dtd *dtd) 774 { 775 return intel_sdvo_get_timing(intel_sdvo, 776 SDVO_CMD_GET_INPUT_TIMINGS_PART1, dtd); 777 } 778 779 static bool 780 intel_sdvo_create_preferred_input_timing(struct intel_sdvo *intel_sdvo, 781 struct intel_sdvo_connector *intel_sdvo_connector, 782 u16 clock, 783 u16 width, 784 u16 height) 785 { 786 struct intel_sdvo_preferred_input_timing_args args; 787 788 memset(&args, 0, sizeof(args)); 789 args.clock = clock; 790 args.width = width; 791 args.height = height; 792 args.interlace = 0; 793 794 if (IS_LVDS(intel_sdvo_connector)) { 795 const struct drm_display_mode *fixed_mode = 796 intel_sdvo_connector->base.panel.fixed_mode; 797 798 if (fixed_mode->hdisplay != width || 799 fixed_mode->vdisplay != height) 800 args.scaled = 1; 801 } 802 803 return intel_sdvo_set_value(intel_sdvo, 804 SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING, 805 &args, sizeof(args)); 806 } 807 808 static bool intel_sdvo_get_preferred_input_timing(struct intel_sdvo *intel_sdvo, 809 struct intel_sdvo_dtd *dtd) 810 { 811 BUILD_BUG_ON(sizeof(dtd->part1) != 8); 812 BUILD_BUG_ON(sizeof(dtd->part2) != 8); 813 return intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1, 814 &dtd->part1, sizeof(dtd->part1)) && 815 intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2, 816 &dtd->part2, sizeof(dtd->part2)); 817 } 818 819 static bool intel_sdvo_set_clock_rate_mult(struct intel_sdvo *intel_sdvo, u8 val) 820 { 821 return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_CLOCK_RATE_MULT, &val, 1); 822 } 823 824 static void intel_sdvo_get_dtd_from_mode(struct intel_sdvo_dtd *dtd, 825 const struct drm_display_mode *mode) 826 { 827 u16 width, height; 828 u16 h_blank_len, h_sync_len, v_blank_len, v_sync_len; 829 u16 h_sync_offset, v_sync_offset; 830 int mode_clock; 831 832 memset(dtd, 0, sizeof(*dtd)); 833 834 width = mode->hdisplay; 835 height = mode->vdisplay; 836 837 /* do some mode translations */ 838 h_blank_len = mode->htotal - mode->hdisplay; 839 h_sync_len = mode->hsync_end - mode->hsync_start; 840 841 v_blank_len = mode->vtotal - mode->vdisplay; 842 v_sync_len = mode->vsync_end - mode->vsync_start; 843 844 h_sync_offset = mode->hsync_start - mode->hdisplay; 845 v_sync_offset = mode->vsync_start - mode->vdisplay; 846 847 mode_clock = mode->clock; 848 mode_clock /= 10; 849 dtd->part1.clock = mode_clock; 850 851 dtd->part1.h_active = width & 0xff; 852 dtd->part1.h_blank = h_blank_len & 0xff; 853 dtd->part1.h_high = (((width >> 8) & 0xf) << 4) | 854 ((h_blank_len >> 8) & 0xf); 855 dtd->part1.v_active = height & 0xff; 856 dtd->part1.v_blank = v_blank_len & 0xff; 857 dtd->part1.v_high = (((height >> 8) & 0xf) << 4) | 858 ((v_blank_len >> 8) & 0xf); 859 860 dtd->part2.h_sync_off = h_sync_offset & 0xff; 861 dtd->part2.h_sync_width = h_sync_len & 0xff; 862 dtd->part2.v_sync_off_width = (v_sync_offset & 0xf) << 4 | 863 (v_sync_len & 0xf); 864 dtd->part2.sync_off_width_high = ((h_sync_offset & 0x300) >> 2) | 865 ((h_sync_len & 0x300) >> 4) | ((v_sync_offset & 0x30) >> 2) | 866 ((v_sync_len & 0x30) >> 4); 867 868 dtd->part2.dtd_flags = 0x18; 869 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 870 dtd->part2.dtd_flags |= DTD_FLAG_INTERLACE; 871 if (mode->flags & DRM_MODE_FLAG_PHSYNC) 872 dtd->part2.dtd_flags |= DTD_FLAG_HSYNC_POSITIVE; 873 if (mode->flags & DRM_MODE_FLAG_PVSYNC) 874 dtd->part2.dtd_flags |= DTD_FLAG_VSYNC_POSITIVE; 875 876 dtd->part2.v_sync_off_high = v_sync_offset & 0xc0; 877 } 878 879 static void intel_sdvo_get_mode_from_dtd(struct drm_display_mode *pmode, 880 const struct intel_sdvo_dtd *dtd) 881 { 882 struct drm_display_mode mode = {}; 883 884 mode.hdisplay = dtd->part1.h_active; 885 mode.hdisplay += ((dtd->part1.h_high >> 4) & 0x0f) << 8; 886 mode.hsync_start = mode.hdisplay + dtd->part2.h_sync_off; 887 mode.hsync_start += (dtd->part2.sync_off_width_high & 0xc0) << 2; 888 mode.hsync_end = mode.hsync_start + dtd->part2.h_sync_width; 889 mode.hsync_end += (dtd->part2.sync_off_width_high & 0x30) << 4; 890 mode.htotal = mode.hdisplay + dtd->part1.h_blank; 891 mode.htotal += (dtd->part1.h_high & 0xf) << 8; 892 893 mode.vdisplay = dtd->part1.v_active; 894 mode.vdisplay += ((dtd->part1.v_high >> 4) & 0x0f) << 8; 895 mode.vsync_start = mode.vdisplay; 896 mode.vsync_start += (dtd->part2.v_sync_off_width >> 4) & 0xf; 897 mode.vsync_start += (dtd->part2.sync_off_width_high & 0x0c) << 2; 898 mode.vsync_start += dtd->part2.v_sync_off_high & 0xc0; 899 mode.vsync_end = mode.vsync_start + 900 (dtd->part2.v_sync_off_width & 0xf); 901 mode.vsync_end += (dtd->part2.sync_off_width_high & 0x3) << 4; 902 mode.vtotal = mode.vdisplay + dtd->part1.v_blank; 903 mode.vtotal += (dtd->part1.v_high & 0xf) << 8; 904 905 mode.clock = dtd->part1.clock * 10; 906 907 if (dtd->part2.dtd_flags & DTD_FLAG_INTERLACE) 908 mode.flags |= DRM_MODE_FLAG_INTERLACE; 909 if (dtd->part2.dtd_flags & DTD_FLAG_HSYNC_POSITIVE) 910 mode.flags |= DRM_MODE_FLAG_PHSYNC; 911 else 912 mode.flags |= DRM_MODE_FLAG_NHSYNC; 913 if (dtd->part2.dtd_flags & DTD_FLAG_VSYNC_POSITIVE) 914 mode.flags |= DRM_MODE_FLAG_PVSYNC; 915 else 916 mode.flags |= DRM_MODE_FLAG_NVSYNC; 917 918 drm_mode_set_crtcinfo(&mode, 0); 919 920 drm_mode_copy(pmode, &mode); 921 } 922 923 static bool intel_sdvo_check_supp_encode(struct intel_sdvo *intel_sdvo) 924 { 925 struct intel_sdvo_encode encode; 926 927 BUILD_BUG_ON(sizeof(encode) != 2); 928 return intel_sdvo_get_value(intel_sdvo, 929 SDVO_CMD_GET_SUPP_ENCODE, 930 &encode, sizeof(encode)); 931 } 932 933 static bool intel_sdvo_set_encode(struct intel_sdvo *intel_sdvo, 934 u8 mode) 935 { 936 return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_ENCODE, &mode, 1); 937 } 938 939 static bool intel_sdvo_set_colorimetry(struct intel_sdvo *intel_sdvo, 940 u8 mode) 941 { 942 return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_COLORIMETRY, &mode, 1); 943 } 944 945 static bool intel_sdvo_set_audio_state(struct intel_sdvo *intel_sdvo, 946 u8 audio_state) 947 { 948 return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_AUDIO_STAT, 949 &audio_state, 1); 950 } 951 952 static bool intel_sdvo_get_hbuf_size(struct intel_sdvo *intel_sdvo, 953 u8 *hbuf_size) 954 { 955 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_HBUF_INFO, 956 hbuf_size, 1)) 957 return false; 958 959 /* Buffer size is 0 based, hooray! However zero means zero. */ 960 if (*hbuf_size) 961 (*hbuf_size)++; 962 963 return true; 964 } 965 966 #if 0 967 static void intel_sdvo_dump_hdmi_buf(struct intel_sdvo *intel_sdvo) 968 { 969 int i, j; 970 u8 set_buf_index[2]; 971 u8 av_split; 972 u8 buf_size; 973 u8 buf[48]; 974 u8 *pos; 975 976 intel_sdvo_get_value(encoder, SDVO_CMD_GET_HBUF_AV_SPLIT, &av_split, 1); 977 978 for (i = 0; i <= av_split; i++) { 979 set_buf_index[0] = i; set_buf_index[1] = 0; 980 intel_sdvo_write_cmd(encoder, SDVO_CMD_SET_HBUF_INDEX, 981 set_buf_index, 2); 982 intel_sdvo_write_cmd(encoder, SDVO_CMD_GET_HBUF_INFO, NULL, 0); 983 intel_sdvo_read_response(encoder, &buf_size, 1); 984 985 pos = buf; 986 for (j = 0; j <= buf_size; j += 8) { 987 intel_sdvo_write_cmd(encoder, SDVO_CMD_GET_HBUF_DATA, 988 NULL, 0); 989 intel_sdvo_read_response(encoder, pos, 8); 990 pos += 8; 991 } 992 } 993 } 994 #endif 995 996 static bool intel_sdvo_write_infoframe(struct intel_sdvo *intel_sdvo, 997 unsigned int if_index, u8 tx_rate, 998 const u8 *data, unsigned int length) 999 { 1000 u8 set_buf_index[2] = { if_index, 0 }; 1001 u8 hbuf_size, tmp[8]; 1002 int i; 1003 1004 if (!intel_sdvo_set_value(intel_sdvo, 1005 SDVO_CMD_SET_HBUF_INDEX, 1006 set_buf_index, 2)) 1007 return false; 1008 1009 if (!intel_sdvo_get_hbuf_size(intel_sdvo, &hbuf_size)) 1010 return false; 1011 1012 DRM_DEBUG_KMS("writing sdvo hbuf: %i, length %u, hbuf_size: %i\n", 1013 if_index, length, hbuf_size); 1014 1015 if (hbuf_size < length) 1016 return false; 1017 1018 for (i = 0; i < hbuf_size; i += 8) { 1019 memset(tmp, 0, 8); 1020 if (i < length) 1021 memcpy(tmp, data + i, min_t(unsigned, 8, length - i)); 1022 1023 if (!intel_sdvo_set_value(intel_sdvo, 1024 SDVO_CMD_SET_HBUF_DATA, 1025 tmp, 8)) 1026 return false; 1027 } 1028 1029 return intel_sdvo_set_value(intel_sdvo, 1030 SDVO_CMD_SET_HBUF_TXRATE, 1031 &tx_rate, 1); 1032 } 1033 1034 static ssize_t intel_sdvo_read_infoframe(struct intel_sdvo *intel_sdvo, 1035 unsigned int if_index, 1036 u8 *data, unsigned int length) 1037 { 1038 u8 set_buf_index[2] = { if_index, 0 }; 1039 u8 hbuf_size, tx_rate, av_split; 1040 int i; 1041 1042 if (!intel_sdvo_get_value(intel_sdvo, 1043 SDVO_CMD_GET_HBUF_AV_SPLIT, 1044 &av_split, 1)) 1045 return -ENXIO; 1046 1047 if (av_split < if_index) 1048 return 0; 1049 1050 if (!intel_sdvo_set_value(intel_sdvo, 1051 SDVO_CMD_SET_HBUF_INDEX, 1052 set_buf_index, 2)) 1053 return -ENXIO; 1054 1055 if (!intel_sdvo_get_value(intel_sdvo, 1056 SDVO_CMD_GET_HBUF_TXRATE, 1057 &tx_rate, 1)) 1058 return -ENXIO; 1059 1060 if (tx_rate == SDVO_HBUF_TX_DISABLED) 1061 return 0; 1062 1063 if (!intel_sdvo_get_hbuf_size(intel_sdvo, &hbuf_size)) 1064 return false; 1065 1066 DRM_DEBUG_KMS("reading sdvo hbuf: %i, length %u, hbuf_size: %i\n", 1067 if_index, length, hbuf_size); 1068 1069 hbuf_size = min_t(unsigned int, length, hbuf_size); 1070 1071 for (i = 0; i < hbuf_size; i += 8) { 1072 if (!intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_GET_HBUF_DATA, NULL, 0)) 1073 return -ENXIO; 1074 if (!intel_sdvo_read_response(intel_sdvo, &data[i], 1075 min_t(unsigned int, 8, hbuf_size - i))) 1076 return -ENXIO; 1077 } 1078 1079 return hbuf_size; 1080 } 1081 1082 static bool intel_sdvo_compute_avi_infoframe(struct intel_sdvo *intel_sdvo, 1083 struct intel_crtc_state *crtc_state, 1084 struct drm_connector_state *conn_state) 1085 { 1086 struct drm_i915_private *dev_priv = to_i915(intel_sdvo->base.base.dev); 1087 struct hdmi_avi_infoframe *frame = &crtc_state->infoframes.avi.avi; 1088 const struct drm_display_mode *adjusted_mode = 1089 &crtc_state->hw.adjusted_mode; 1090 int ret; 1091 1092 if (!crtc_state->has_hdmi_sink) 1093 return true; 1094 1095 crtc_state->infoframes.enable |= 1096 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_AVI); 1097 1098 ret = drm_hdmi_avi_infoframe_from_display_mode(frame, 1099 conn_state->connector, 1100 adjusted_mode); 1101 if (ret) 1102 return false; 1103 1104 drm_hdmi_avi_infoframe_quant_range(frame, 1105 conn_state->connector, 1106 adjusted_mode, 1107 crtc_state->limited_color_range ? 1108 HDMI_QUANTIZATION_RANGE_LIMITED : 1109 HDMI_QUANTIZATION_RANGE_FULL); 1110 1111 ret = hdmi_avi_infoframe_check(frame); 1112 if (drm_WARN_ON(&dev_priv->drm, ret)) 1113 return false; 1114 1115 return true; 1116 } 1117 1118 static bool intel_sdvo_set_avi_infoframe(struct intel_sdvo *intel_sdvo, 1119 const struct intel_crtc_state *crtc_state) 1120 { 1121 struct drm_i915_private *dev_priv = to_i915(intel_sdvo->base.base.dev); 1122 u8 sdvo_data[HDMI_INFOFRAME_SIZE(AVI)]; 1123 const union hdmi_infoframe *frame = &crtc_state->infoframes.avi; 1124 ssize_t len; 1125 1126 if ((crtc_state->infoframes.enable & 1127 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_AVI)) == 0) 1128 return true; 1129 1130 if (drm_WARN_ON(&dev_priv->drm, 1131 frame->any.type != HDMI_INFOFRAME_TYPE_AVI)) 1132 return false; 1133 1134 len = hdmi_infoframe_pack_only(frame, sdvo_data, sizeof(sdvo_data)); 1135 if (drm_WARN_ON(&dev_priv->drm, len < 0)) 1136 return false; 1137 1138 return intel_sdvo_write_infoframe(intel_sdvo, SDVO_HBUF_INDEX_AVI_IF, 1139 SDVO_HBUF_TX_VSYNC, 1140 sdvo_data, len); 1141 } 1142 1143 static void intel_sdvo_get_avi_infoframe(struct intel_sdvo *intel_sdvo, 1144 struct intel_crtc_state *crtc_state) 1145 { 1146 u8 sdvo_data[HDMI_INFOFRAME_SIZE(AVI)]; 1147 union hdmi_infoframe *frame = &crtc_state->infoframes.avi; 1148 ssize_t len; 1149 int ret; 1150 1151 if (!crtc_state->has_hdmi_sink) 1152 return; 1153 1154 len = intel_sdvo_read_infoframe(intel_sdvo, SDVO_HBUF_INDEX_AVI_IF, 1155 sdvo_data, sizeof(sdvo_data)); 1156 if (len < 0) { 1157 DRM_DEBUG_KMS("failed to read AVI infoframe\n"); 1158 return; 1159 } else if (len == 0) { 1160 return; 1161 } 1162 1163 crtc_state->infoframes.enable |= 1164 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_AVI); 1165 1166 ret = hdmi_infoframe_unpack(frame, sdvo_data, len); 1167 if (ret) { 1168 DRM_DEBUG_KMS("Failed to unpack AVI infoframe\n"); 1169 return; 1170 } 1171 1172 if (frame->any.type != HDMI_INFOFRAME_TYPE_AVI) 1173 DRM_DEBUG_KMS("Found the wrong infoframe type 0x%x (expected 0x%02x)\n", 1174 frame->any.type, HDMI_INFOFRAME_TYPE_AVI); 1175 } 1176 1177 static bool intel_sdvo_set_tv_format(struct intel_sdvo *intel_sdvo, 1178 const struct drm_connector_state *conn_state) 1179 { 1180 struct intel_sdvo_tv_format format; 1181 u32 format_map; 1182 1183 format_map = 1 << conn_state->tv.mode; 1184 memset(&format, 0, sizeof(format)); 1185 memcpy(&format, &format_map, min(sizeof(format), sizeof(format_map))); 1186 1187 BUILD_BUG_ON(sizeof(format) != 6); 1188 return intel_sdvo_set_value(intel_sdvo, 1189 SDVO_CMD_SET_TV_FORMAT, 1190 &format, sizeof(format)); 1191 } 1192 1193 static bool 1194 intel_sdvo_set_output_timings_from_mode(struct intel_sdvo *intel_sdvo, 1195 const struct drm_display_mode *mode) 1196 { 1197 struct intel_sdvo_dtd output_dtd; 1198 1199 if (!intel_sdvo_set_target_output(intel_sdvo, 1200 intel_sdvo->attached_output)) 1201 return false; 1202 1203 intel_sdvo_get_dtd_from_mode(&output_dtd, mode); 1204 if (!intel_sdvo_set_output_timing(intel_sdvo, &output_dtd)) 1205 return false; 1206 1207 return true; 1208 } 1209 1210 /* 1211 * Asks the sdvo controller for the preferred input mode given the output mode. 1212 * Unfortunately we have to set up the full output mode to do that. 1213 */ 1214 static bool 1215 intel_sdvo_get_preferred_input_mode(struct intel_sdvo *intel_sdvo, 1216 struct intel_sdvo_connector *intel_sdvo_connector, 1217 const struct drm_display_mode *mode, 1218 struct drm_display_mode *adjusted_mode) 1219 { 1220 struct intel_sdvo_dtd input_dtd; 1221 1222 /* Reset the input timing to the screen. Assume always input 0. */ 1223 if (!intel_sdvo_set_target_input(intel_sdvo)) 1224 return false; 1225 1226 if (!intel_sdvo_create_preferred_input_timing(intel_sdvo, 1227 intel_sdvo_connector, 1228 mode->clock / 10, 1229 mode->hdisplay, 1230 mode->vdisplay)) 1231 return false; 1232 1233 if (!intel_sdvo_get_preferred_input_timing(intel_sdvo, 1234 &input_dtd)) 1235 return false; 1236 1237 intel_sdvo_get_mode_from_dtd(adjusted_mode, &input_dtd); 1238 intel_sdvo->dtd_sdvo_flags = input_dtd.part2.sdvo_flags; 1239 1240 return true; 1241 } 1242 1243 static void i9xx_adjust_sdvo_tv_clock(struct intel_crtc_state *pipe_config) 1244 { 1245 struct drm_i915_private *dev_priv = to_i915(pipe_config->uapi.crtc->dev); 1246 unsigned dotclock = pipe_config->port_clock; 1247 struct dpll *clock = &pipe_config->dpll; 1248 1249 /* 1250 * SDVO TV has fixed PLL values depend on its clock range, 1251 * this mirrors vbios setting. 1252 */ 1253 if (dotclock >= 100000 && dotclock < 140500) { 1254 clock->p1 = 2; 1255 clock->p2 = 10; 1256 clock->n = 3; 1257 clock->m1 = 16; 1258 clock->m2 = 8; 1259 } else if (dotclock >= 140500 && dotclock <= 200000) { 1260 clock->p1 = 1; 1261 clock->p2 = 10; 1262 clock->n = 6; 1263 clock->m1 = 12; 1264 clock->m2 = 8; 1265 } else { 1266 drm_WARN(&dev_priv->drm, 1, 1267 "SDVO TV clock out of range: %i\n", dotclock); 1268 } 1269 1270 pipe_config->clock_set = true; 1271 } 1272 1273 static bool intel_has_hdmi_sink(struct intel_sdvo *sdvo, 1274 const struct drm_connector_state *conn_state) 1275 { 1276 return sdvo->has_hdmi_monitor && 1277 READ_ONCE(to_intel_digital_connector_state(conn_state)->force_audio) != HDMI_AUDIO_OFF_DVI; 1278 } 1279 1280 static int intel_sdvo_compute_config(struct intel_encoder *encoder, 1281 struct intel_crtc_state *pipe_config, 1282 struct drm_connector_state *conn_state) 1283 { 1284 struct intel_sdvo *intel_sdvo = to_sdvo(encoder); 1285 struct intel_sdvo_connector_state *intel_sdvo_state = 1286 to_intel_sdvo_connector_state(conn_state); 1287 struct intel_sdvo_connector *intel_sdvo_connector = 1288 to_intel_sdvo_connector(conn_state->connector); 1289 struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode; 1290 struct drm_display_mode *mode = &pipe_config->hw.mode; 1291 1292 DRM_DEBUG_KMS("forcing bpc to 8 for SDVO\n"); 1293 pipe_config->pipe_bpp = 8*3; 1294 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; 1295 1296 if (HAS_PCH_SPLIT(to_i915(encoder->base.dev))) 1297 pipe_config->has_pch_encoder = true; 1298 1299 /* 1300 * We need to construct preferred input timings based on our 1301 * output timings. To do that, we have to set the output 1302 * timings, even though this isn't really the right place in 1303 * the sequence to do it. Oh well. 1304 */ 1305 if (IS_TV(intel_sdvo_connector)) { 1306 if (!intel_sdvo_set_output_timings_from_mode(intel_sdvo, mode)) 1307 return -EINVAL; 1308 1309 (void) intel_sdvo_get_preferred_input_mode(intel_sdvo, 1310 intel_sdvo_connector, 1311 mode, 1312 adjusted_mode); 1313 pipe_config->sdvo_tv_clock = true; 1314 } else if (IS_LVDS(intel_sdvo_connector)) { 1315 if (!intel_sdvo_set_output_timings_from_mode(intel_sdvo, 1316 intel_sdvo_connector->base.panel.fixed_mode)) 1317 return -EINVAL; 1318 1319 (void) intel_sdvo_get_preferred_input_mode(intel_sdvo, 1320 intel_sdvo_connector, 1321 mode, 1322 adjusted_mode); 1323 } 1324 1325 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN) 1326 return -EINVAL; 1327 1328 /* 1329 * Make the CRTC code factor in the SDVO pixel multiplier. The 1330 * SDVO device will factor out the multiplier during mode_set. 1331 */ 1332 pipe_config->pixel_multiplier = 1333 intel_sdvo_get_pixel_multiplier(adjusted_mode); 1334 1335 pipe_config->has_hdmi_sink = intel_has_hdmi_sink(intel_sdvo, conn_state); 1336 1337 if (pipe_config->has_hdmi_sink) { 1338 if (intel_sdvo_state->base.force_audio == HDMI_AUDIO_AUTO) 1339 pipe_config->has_audio = intel_sdvo->has_hdmi_audio; 1340 else 1341 pipe_config->has_audio = 1342 intel_sdvo_state->base.force_audio == HDMI_AUDIO_ON; 1343 } 1344 1345 if (intel_sdvo_state->base.broadcast_rgb == INTEL_BROADCAST_RGB_AUTO) { 1346 /* 1347 * See CEA-861-E - 5.1 Default Encoding Parameters 1348 * 1349 * FIXME: This bit is only valid when using TMDS encoding and 8 1350 * bit per color mode. 1351 */ 1352 if (pipe_config->has_hdmi_sink && 1353 drm_match_cea_mode(adjusted_mode) > 1) 1354 pipe_config->limited_color_range = true; 1355 } else { 1356 if (pipe_config->has_hdmi_sink && 1357 intel_sdvo_state->base.broadcast_rgb == INTEL_BROADCAST_RGB_LIMITED) 1358 pipe_config->limited_color_range = true; 1359 } 1360 1361 /* Clock computation needs to happen after pixel multiplier. */ 1362 if (IS_TV(intel_sdvo_connector)) 1363 i9xx_adjust_sdvo_tv_clock(pipe_config); 1364 1365 if (conn_state->picture_aspect_ratio) 1366 adjusted_mode->picture_aspect_ratio = 1367 conn_state->picture_aspect_ratio; 1368 1369 if (!intel_sdvo_compute_avi_infoframe(intel_sdvo, 1370 pipe_config, conn_state)) { 1371 DRM_DEBUG_KMS("bad AVI infoframe\n"); 1372 return -EINVAL; 1373 } 1374 1375 return 0; 1376 } 1377 1378 #define UPDATE_PROPERTY(input, NAME) \ 1379 do { \ 1380 val = input; \ 1381 intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_##NAME, &val, sizeof(val)); \ 1382 } while (0) 1383 1384 static void intel_sdvo_update_props(struct intel_sdvo *intel_sdvo, 1385 const struct intel_sdvo_connector_state *sdvo_state) 1386 { 1387 const struct drm_connector_state *conn_state = &sdvo_state->base.base; 1388 struct intel_sdvo_connector *intel_sdvo_conn = 1389 to_intel_sdvo_connector(conn_state->connector); 1390 u16 val; 1391 1392 if (intel_sdvo_conn->left) 1393 UPDATE_PROPERTY(sdvo_state->tv.overscan_h, OVERSCAN_H); 1394 1395 if (intel_sdvo_conn->top) 1396 UPDATE_PROPERTY(sdvo_state->tv.overscan_v, OVERSCAN_V); 1397 1398 if (intel_sdvo_conn->hpos) 1399 UPDATE_PROPERTY(sdvo_state->tv.hpos, HPOS); 1400 1401 if (intel_sdvo_conn->vpos) 1402 UPDATE_PROPERTY(sdvo_state->tv.vpos, VPOS); 1403 1404 if (intel_sdvo_conn->saturation) 1405 UPDATE_PROPERTY(conn_state->tv.saturation, SATURATION); 1406 1407 if (intel_sdvo_conn->contrast) 1408 UPDATE_PROPERTY(conn_state->tv.contrast, CONTRAST); 1409 1410 if (intel_sdvo_conn->hue) 1411 UPDATE_PROPERTY(conn_state->tv.hue, HUE); 1412 1413 if (intel_sdvo_conn->brightness) 1414 UPDATE_PROPERTY(conn_state->tv.brightness, BRIGHTNESS); 1415 1416 if (intel_sdvo_conn->sharpness) 1417 UPDATE_PROPERTY(sdvo_state->tv.sharpness, SHARPNESS); 1418 1419 if (intel_sdvo_conn->flicker_filter) 1420 UPDATE_PROPERTY(sdvo_state->tv.flicker_filter, FLICKER_FILTER); 1421 1422 if (intel_sdvo_conn->flicker_filter_2d) 1423 UPDATE_PROPERTY(sdvo_state->tv.flicker_filter_2d, FLICKER_FILTER_2D); 1424 1425 if (intel_sdvo_conn->flicker_filter_adaptive) 1426 UPDATE_PROPERTY(sdvo_state->tv.flicker_filter_adaptive, FLICKER_FILTER_ADAPTIVE); 1427 1428 if (intel_sdvo_conn->tv_chroma_filter) 1429 UPDATE_PROPERTY(sdvo_state->tv.chroma_filter, TV_CHROMA_FILTER); 1430 1431 if (intel_sdvo_conn->tv_luma_filter) 1432 UPDATE_PROPERTY(sdvo_state->tv.luma_filter, TV_LUMA_FILTER); 1433 1434 if (intel_sdvo_conn->dot_crawl) 1435 UPDATE_PROPERTY(sdvo_state->tv.dot_crawl, DOT_CRAWL); 1436 1437 #undef UPDATE_PROPERTY 1438 } 1439 1440 static void intel_sdvo_pre_enable(struct intel_atomic_state *state, 1441 struct intel_encoder *intel_encoder, 1442 const struct intel_crtc_state *crtc_state, 1443 const struct drm_connector_state *conn_state) 1444 { 1445 struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev); 1446 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1447 const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; 1448 const struct intel_sdvo_connector_state *sdvo_state = 1449 to_intel_sdvo_connector_state(conn_state); 1450 const struct intel_sdvo_connector *intel_sdvo_connector = 1451 to_intel_sdvo_connector(conn_state->connector); 1452 const struct drm_display_mode *mode = &crtc_state->hw.mode; 1453 struct intel_sdvo *intel_sdvo = to_sdvo(intel_encoder); 1454 u32 sdvox; 1455 struct intel_sdvo_in_out_map in_out; 1456 struct intel_sdvo_dtd input_dtd, output_dtd; 1457 int rate; 1458 1459 intel_sdvo_update_props(intel_sdvo, sdvo_state); 1460 1461 /* 1462 * First, set the input mapping for the first input to our controlled 1463 * output. This is only correct if we're a single-input device, in 1464 * which case the first input is the output from the appropriate SDVO 1465 * channel on the motherboard. In a two-input device, the first input 1466 * will be SDVOB and the second SDVOC. 1467 */ 1468 in_out.in0 = intel_sdvo->attached_output; 1469 in_out.in1 = 0; 1470 1471 intel_sdvo_set_value(intel_sdvo, 1472 SDVO_CMD_SET_IN_OUT_MAP, 1473 &in_out, sizeof(in_out)); 1474 1475 /* Set the output timings to the screen */ 1476 if (!intel_sdvo_set_target_output(intel_sdvo, 1477 intel_sdvo->attached_output)) 1478 return; 1479 1480 /* lvds has a special fixed output timing. */ 1481 if (IS_LVDS(intel_sdvo_connector)) 1482 intel_sdvo_get_dtd_from_mode(&output_dtd, 1483 intel_sdvo_connector->base.panel.fixed_mode); 1484 else 1485 intel_sdvo_get_dtd_from_mode(&output_dtd, mode); 1486 if (!intel_sdvo_set_output_timing(intel_sdvo, &output_dtd)) 1487 drm_info(&dev_priv->drm, 1488 "Setting output timings on %s failed\n", 1489 SDVO_NAME(intel_sdvo)); 1490 1491 /* Set the input timing to the screen. Assume always input 0. */ 1492 if (!intel_sdvo_set_target_input(intel_sdvo)) 1493 return; 1494 1495 if (crtc_state->has_hdmi_sink) { 1496 intel_sdvo_set_encode(intel_sdvo, SDVO_ENCODE_HDMI); 1497 intel_sdvo_set_colorimetry(intel_sdvo, 1498 SDVO_COLORIMETRY_RGB256); 1499 intel_sdvo_set_avi_infoframe(intel_sdvo, crtc_state); 1500 } else 1501 intel_sdvo_set_encode(intel_sdvo, SDVO_ENCODE_DVI); 1502 1503 if (IS_TV(intel_sdvo_connector) && 1504 !intel_sdvo_set_tv_format(intel_sdvo, conn_state)) 1505 return; 1506 1507 intel_sdvo_get_dtd_from_mode(&input_dtd, adjusted_mode); 1508 1509 if (IS_TV(intel_sdvo_connector) || IS_LVDS(intel_sdvo_connector)) 1510 input_dtd.part2.sdvo_flags = intel_sdvo->dtd_sdvo_flags; 1511 if (!intel_sdvo_set_input_timing(intel_sdvo, &input_dtd)) 1512 drm_info(&dev_priv->drm, 1513 "Setting input timings on %s failed\n", 1514 SDVO_NAME(intel_sdvo)); 1515 1516 switch (crtc_state->pixel_multiplier) { 1517 default: 1518 drm_WARN(&dev_priv->drm, 1, 1519 "unknown pixel multiplier specified\n"); 1520 /* fall through */ 1521 case 1: rate = SDVO_CLOCK_RATE_MULT_1X; break; 1522 case 2: rate = SDVO_CLOCK_RATE_MULT_2X; break; 1523 case 4: rate = SDVO_CLOCK_RATE_MULT_4X; break; 1524 } 1525 if (!intel_sdvo_set_clock_rate_mult(intel_sdvo, rate)) 1526 return; 1527 1528 /* Set the SDVO control regs. */ 1529 if (INTEL_GEN(dev_priv) >= 4) { 1530 /* The real mode polarity is set by the SDVO commands, using 1531 * struct intel_sdvo_dtd. */ 1532 sdvox = SDVO_VSYNC_ACTIVE_HIGH | SDVO_HSYNC_ACTIVE_HIGH; 1533 if (!HAS_PCH_SPLIT(dev_priv) && crtc_state->limited_color_range) 1534 sdvox |= HDMI_COLOR_RANGE_16_235; 1535 if (INTEL_GEN(dev_priv) < 5) 1536 sdvox |= SDVO_BORDER_ENABLE; 1537 } else { 1538 sdvox = intel_de_read(dev_priv, intel_sdvo->sdvo_reg); 1539 if (intel_sdvo->port == PORT_B) 1540 sdvox &= SDVOB_PRESERVE_MASK; 1541 else 1542 sdvox &= SDVOC_PRESERVE_MASK; 1543 sdvox |= (9 << 19) | SDVO_BORDER_ENABLE; 1544 } 1545 1546 if (HAS_PCH_CPT(dev_priv)) 1547 sdvox |= SDVO_PIPE_SEL_CPT(crtc->pipe); 1548 else 1549 sdvox |= SDVO_PIPE_SEL(crtc->pipe); 1550 1551 if (INTEL_GEN(dev_priv) >= 4) { 1552 /* done in crtc_mode_set as the dpll_md reg must be written early */ 1553 } else if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) || 1554 IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) { 1555 /* done in crtc_mode_set as it lives inside the dpll register */ 1556 } else { 1557 sdvox |= (crtc_state->pixel_multiplier - 1) 1558 << SDVO_PORT_MULTIPLY_SHIFT; 1559 } 1560 1561 if (input_dtd.part2.sdvo_flags & SDVO_NEED_TO_STALL && 1562 INTEL_GEN(dev_priv) < 5) 1563 sdvox |= SDVO_STALL_SELECT; 1564 intel_sdvo_write_sdvox(intel_sdvo, sdvox); 1565 } 1566 1567 static bool intel_sdvo_connector_get_hw_state(struct intel_connector *connector) 1568 { 1569 struct intel_sdvo_connector *intel_sdvo_connector = 1570 to_intel_sdvo_connector(&connector->base); 1571 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector); 1572 u16 active_outputs = 0; 1573 1574 intel_sdvo_get_active_outputs(intel_sdvo, &active_outputs); 1575 1576 return active_outputs & intel_sdvo_connector->output_flag; 1577 } 1578 1579 bool intel_sdvo_port_enabled(struct drm_i915_private *dev_priv, 1580 i915_reg_t sdvo_reg, enum pipe *pipe) 1581 { 1582 u32 val; 1583 1584 val = intel_de_read(dev_priv, sdvo_reg); 1585 1586 /* asserts want to know the pipe even if the port is disabled */ 1587 if (HAS_PCH_CPT(dev_priv)) 1588 *pipe = (val & SDVO_PIPE_SEL_MASK_CPT) >> SDVO_PIPE_SEL_SHIFT_CPT; 1589 else if (IS_CHERRYVIEW(dev_priv)) 1590 *pipe = (val & SDVO_PIPE_SEL_MASK_CHV) >> SDVO_PIPE_SEL_SHIFT_CHV; 1591 else 1592 *pipe = (val & SDVO_PIPE_SEL_MASK) >> SDVO_PIPE_SEL_SHIFT; 1593 1594 return val & SDVO_ENABLE; 1595 } 1596 1597 static bool intel_sdvo_get_hw_state(struct intel_encoder *encoder, 1598 enum pipe *pipe) 1599 { 1600 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1601 struct intel_sdvo *intel_sdvo = to_sdvo(encoder); 1602 u16 active_outputs = 0; 1603 bool ret; 1604 1605 intel_sdvo_get_active_outputs(intel_sdvo, &active_outputs); 1606 1607 ret = intel_sdvo_port_enabled(dev_priv, intel_sdvo->sdvo_reg, pipe); 1608 1609 return ret || active_outputs; 1610 } 1611 1612 static void intel_sdvo_get_config(struct intel_encoder *encoder, 1613 struct intel_crtc_state *pipe_config) 1614 { 1615 struct drm_device *dev = encoder->base.dev; 1616 struct drm_i915_private *dev_priv = to_i915(dev); 1617 struct intel_sdvo *intel_sdvo = to_sdvo(encoder); 1618 struct intel_sdvo_dtd dtd; 1619 int encoder_pixel_multiplier = 0; 1620 int dotclock; 1621 u32 flags = 0, sdvox; 1622 u8 val; 1623 bool ret; 1624 1625 pipe_config->output_types |= BIT(INTEL_OUTPUT_SDVO); 1626 1627 sdvox = intel_de_read(dev_priv, intel_sdvo->sdvo_reg); 1628 1629 ret = intel_sdvo_get_input_timing(intel_sdvo, &dtd); 1630 if (!ret) { 1631 /* 1632 * Some sdvo encoders are not spec compliant and don't 1633 * implement the mandatory get_timings function. 1634 */ 1635 drm_dbg(&dev_priv->drm, "failed to retrieve SDVO DTD\n"); 1636 pipe_config->quirks |= PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS; 1637 } else { 1638 if (dtd.part2.dtd_flags & DTD_FLAG_HSYNC_POSITIVE) 1639 flags |= DRM_MODE_FLAG_PHSYNC; 1640 else 1641 flags |= DRM_MODE_FLAG_NHSYNC; 1642 1643 if (dtd.part2.dtd_flags & DTD_FLAG_VSYNC_POSITIVE) 1644 flags |= DRM_MODE_FLAG_PVSYNC; 1645 else 1646 flags |= DRM_MODE_FLAG_NVSYNC; 1647 } 1648 1649 pipe_config->hw.adjusted_mode.flags |= flags; 1650 1651 /* 1652 * pixel multiplier readout is tricky: Only on i915g/gm it is stored in 1653 * the sdvo port register, on all other platforms it is part of the dpll 1654 * state. Since the general pipe state readout happens before the 1655 * encoder->get_config we so already have a valid pixel multplier on all 1656 * other platfroms. 1657 */ 1658 if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) { 1659 pipe_config->pixel_multiplier = 1660 ((sdvox & SDVO_PORT_MULTIPLY_MASK) 1661 >> SDVO_PORT_MULTIPLY_SHIFT) + 1; 1662 } 1663 1664 dotclock = pipe_config->port_clock; 1665 1666 if (pipe_config->pixel_multiplier) 1667 dotclock /= pipe_config->pixel_multiplier; 1668 1669 pipe_config->hw.adjusted_mode.crtc_clock = dotclock; 1670 1671 /* Cross check the port pixel multiplier with the sdvo encoder state. */ 1672 if (intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_CLOCK_RATE_MULT, 1673 &val, 1)) { 1674 switch (val) { 1675 case SDVO_CLOCK_RATE_MULT_1X: 1676 encoder_pixel_multiplier = 1; 1677 break; 1678 case SDVO_CLOCK_RATE_MULT_2X: 1679 encoder_pixel_multiplier = 2; 1680 break; 1681 case SDVO_CLOCK_RATE_MULT_4X: 1682 encoder_pixel_multiplier = 4; 1683 break; 1684 } 1685 } 1686 1687 drm_WARN(dev, 1688 encoder_pixel_multiplier != pipe_config->pixel_multiplier, 1689 "SDVO pixel multiplier mismatch, port: %i, encoder: %i\n", 1690 pipe_config->pixel_multiplier, encoder_pixel_multiplier); 1691 1692 if (sdvox & HDMI_COLOR_RANGE_16_235) 1693 pipe_config->limited_color_range = true; 1694 1695 if (intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_AUDIO_STAT, 1696 &val, 1)) { 1697 u8 mask = SDVO_AUDIO_ELD_VALID | SDVO_AUDIO_PRESENCE_DETECT; 1698 1699 if ((val & mask) == mask) 1700 pipe_config->has_audio = true; 1701 } 1702 1703 if (intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_ENCODE, 1704 &val, 1)) { 1705 if (val == SDVO_ENCODE_HDMI) 1706 pipe_config->has_hdmi_sink = true; 1707 } 1708 1709 intel_sdvo_get_avi_infoframe(intel_sdvo, pipe_config); 1710 } 1711 1712 static void intel_sdvo_disable_audio(struct intel_sdvo *intel_sdvo) 1713 { 1714 intel_sdvo_set_audio_state(intel_sdvo, 0); 1715 } 1716 1717 static void intel_sdvo_enable_audio(struct intel_sdvo *intel_sdvo, 1718 const struct intel_crtc_state *crtc_state, 1719 const struct drm_connector_state *conn_state) 1720 { 1721 const struct drm_display_mode *adjusted_mode = 1722 &crtc_state->hw.adjusted_mode; 1723 struct drm_connector *connector = conn_state->connector; 1724 u8 *eld = connector->eld; 1725 1726 eld[6] = drm_av_sync_delay(connector, adjusted_mode) / 2; 1727 1728 intel_sdvo_set_audio_state(intel_sdvo, 0); 1729 1730 intel_sdvo_write_infoframe(intel_sdvo, SDVO_HBUF_INDEX_ELD, 1731 SDVO_HBUF_TX_DISABLED, 1732 eld, drm_eld_size(eld)); 1733 1734 intel_sdvo_set_audio_state(intel_sdvo, SDVO_AUDIO_ELD_VALID | 1735 SDVO_AUDIO_PRESENCE_DETECT); 1736 } 1737 1738 static void intel_disable_sdvo(struct intel_atomic_state *state, 1739 struct intel_encoder *encoder, 1740 const struct intel_crtc_state *old_crtc_state, 1741 const struct drm_connector_state *conn_state) 1742 { 1743 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1744 struct intel_sdvo *intel_sdvo = to_sdvo(encoder); 1745 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); 1746 u32 temp; 1747 1748 if (old_crtc_state->has_audio) 1749 intel_sdvo_disable_audio(intel_sdvo); 1750 1751 intel_sdvo_set_active_outputs(intel_sdvo, 0); 1752 if (0) 1753 intel_sdvo_set_encoder_power_state(intel_sdvo, 1754 DRM_MODE_DPMS_OFF); 1755 1756 temp = intel_de_read(dev_priv, intel_sdvo->sdvo_reg); 1757 1758 temp &= ~SDVO_ENABLE; 1759 intel_sdvo_write_sdvox(intel_sdvo, temp); 1760 1761 /* 1762 * HW workaround for IBX, we need to move the port 1763 * to transcoder A after disabling it to allow the 1764 * matching DP port to be enabled on transcoder A. 1765 */ 1766 if (HAS_PCH_IBX(dev_priv) && crtc->pipe == PIPE_B) { 1767 /* 1768 * We get CPU/PCH FIFO underruns on the other pipe when 1769 * doing the workaround. Sweep them under the rug. 1770 */ 1771 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false); 1772 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false); 1773 1774 temp &= ~SDVO_PIPE_SEL_MASK; 1775 temp |= SDVO_ENABLE | SDVO_PIPE_SEL(PIPE_A); 1776 intel_sdvo_write_sdvox(intel_sdvo, temp); 1777 1778 temp &= ~SDVO_ENABLE; 1779 intel_sdvo_write_sdvox(intel_sdvo, temp); 1780 1781 intel_wait_for_vblank_if_active(dev_priv, PIPE_A); 1782 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true); 1783 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true); 1784 } 1785 } 1786 1787 static void pch_disable_sdvo(struct intel_atomic_state *state, 1788 struct intel_encoder *encoder, 1789 const struct intel_crtc_state *old_crtc_state, 1790 const struct drm_connector_state *old_conn_state) 1791 { 1792 } 1793 1794 static void pch_post_disable_sdvo(struct intel_atomic_state *state, 1795 struct intel_encoder *encoder, 1796 const struct intel_crtc_state *old_crtc_state, 1797 const struct drm_connector_state *old_conn_state) 1798 { 1799 intel_disable_sdvo(state, encoder, old_crtc_state, old_conn_state); 1800 } 1801 1802 static void intel_enable_sdvo(struct intel_atomic_state *state, 1803 struct intel_encoder *encoder, 1804 const struct intel_crtc_state *pipe_config, 1805 const struct drm_connector_state *conn_state) 1806 { 1807 struct drm_device *dev = encoder->base.dev; 1808 struct drm_i915_private *dev_priv = to_i915(dev); 1809 struct intel_sdvo *intel_sdvo = to_sdvo(encoder); 1810 struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->uapi.crtc); 1811 u32 temp; 1812 bool input1, input2; 1813 int i; 1814 bool success; 1815 1816 temp = intel_de_read(dev_priv, intel_sdvo->sdvo_reg); 1817 temp |= SDVO_ENABLE; 1818 intel_sdvo_write_sdvox(intel_sdvo, temp); 1819 1820 for (i = 0; i < 2; i++) 1821 intel_wait_for_vblank(dev_priv, intel_crtc->pipe); 1822 1823 success = intel_sdvo_get_trained_inputs(intel_sdvo, &input1, &input2); 1824 /* 1825 * Warn if the device reported failure to sync. 1826 * 1827 * A lot of SDVO devices fail to notify of sync, but it's 1828 * a given it the status is a success, we succeeded. 1829 */ 1830 if (success && !input1) { 1831 drm_dbg_kms(&dev_priv->drm, 1832 "First %s output reported failure to " 1833 "sync\n", SDVO_NAME(intel_sdvo)); 1834 } 1835 1836 if (0) 1837 intel_sdvo_set_encoder_power_state(intel_sdvo, 1838 DRM_MODE_DPMS_ON); 1839 intel_sdvo_set_active_outputs(intel_sdvo, intel_sdvo->attached_output); 1840 1841 if (pipe_config->has_audio) 1842 intel_sdvo_enable_audio(intel_sdvo, pipe_config, conn_state); 1843 } 1844 1845 static enum drm_mode_status 1846 intel_sdvo_mode_valid(struct drm_connector *connector, 1847 struct drm_display_mode *mode) 1848 { 1849 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(to_intel_connector(connector)); 1850 struct intel_sdvo_connector *intel_sdvo_connector = 1851 to_intel_sdvo_connector(connector); 1852 int max_dotclk = to_i915(connector->dev)->max_dotclk_freq; 1853 1854 if (mode->flags & DRM_MODE_FLAG_DBLSCAN) 1855 return MODE_NO_DBLESCAN; 1856 1857 if (intel_sdvo->pixel_clock_min > mode->clock) 1858 return MODE_CLOCK_LOW; 1859 1860 if (intel_sdvo->pixel_clock_max < mode->clock) 1861 return MODE_CLOCK_HIGH; 1862 1863 if (mode->clock > max_dotclk) 1864 return MODE_CLOCK_HIGH; 1865 1866 if (IS_LVDS(intel_sdvo_connector)) { 1867 const struct drm_display_mode *fixed_mode = 1868 intel_sdvo_connector->base.panel.fixed_mode; 1869 1870 if (mode->hdisplay > fixed_mode->hdisplay) 1871 return MODE_PANEL; 1872 1873 if (mode->vdisplay > fixed_mode->vdisplay) 1874 return MODE_PANEL; 1875 } 1876 1877 return MODE_OK; 1878 } 1879 1880 static bool intel_sdvo_get_capabilities(struct intel_sdvo *intel_sdvo, struct intel_sdvo_caps *caps) 1881 { 1882 BUILD_BUG_ON(sizeof(*caps) != 8); 1883 if (!intel_sdvo_get_value(intel_sdvo, 1884 SDVO_CMD_GET_DEVICE_CAPS, 1885 caps, sizeof(*caps))) 1886 return false; 1887 1888 DRM_DEBUG_KMS("SDVO capabilities:\n" 1889 " vendor_id: %d\n" 1890 " device_id: %d\n" 1891 " device_rev_id: %d\n" 1892 " sdvo_version_major: %d\n" 1893 " sdvo_version_minor: %d\n" 1894 " sdvo_inputs_mask: %d\n" 1895 " smooth_scaling: %d\n" 1896 " sharp_scaling: %d\n" 1897 " up_scaling: %d\n" 1898 " down_scaling: %d\n" 1899 " stall_support: %d\n" 1900 " output_flags: %d\n", 1901 caps->vendor_id, 1902 caps->device_id, 1903 caps->device_rev_id, 1904 caps->sdvo_version_major, 1905 caps->sdvo_version_minor, 1906 caps->sdvo_inputs_mask, 1907 caps->smooth_scaling, 1908 caps->sharp_scaling, 1909 caps->up_scaling, 1910 caps->down_scaling, 1911 caps->stall_support, 1912 caps->output_flags); 1913 1914 return true; 1915 } 1916 1917 static u16 intel_sdvo_get_hotplug_support(struct intel_sdvo *intel_sdvo) 1918 { 1919 struct drm_i915_private *dev_priv = to_i915(intel_sdvo->base.base.dev); 1920 u16 hotplug; 1921 1922 if (!I915_HAS_HOTPLUG(dev_priv)) 1923 return 0; 1924 1925 /* 1926 * HW Erratum: SDVO Hotplug is broken on all i945G chips, there's noise 1927 * on the line. 1928 */ 1929 if (IS_I945G(dev_priv) || IS_I945GM(dev_priv)) 1930 return 0; 1931 1932 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_HOT_PLUG_SUPPORT, 1933 &hotplug, sizeof(hotplug))) 1934 return 0; 1935 1936 return hotplug; 1937 } 1938 1939 static void intel_sdvo_enable_hotplug(struct intel_encoder *encoder) 1940 { 1941 struct intel_sdvo *intel_sdvo = to_sdvo(encoder); 1942 1943 intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_SET_ACTIVE_HOT_PLUG, 1944 &intel_sdvo->hotplug_active, 2); 1945 } 1946 1947 static enum intel_hotplug_state 1948 intel_sdvo_hotplug(struct intel_encoder *encoder, 1949 struct intel_connector *connector) 1950 { 1951 intel_sdvo_enable_hotplug(encoder); 1952 1953 return intel_encoder_hotplug(encoder, connector); 1954 } 1955 1956 static bool 1957 intel_sdvo_multifunc_encoder(struct intel_sdvo *intel_sdvo) 1958 { 1959 /* Is there more than one type of output? */ 1960 return hweight16(intel_sdvo->caps.output_flags) > 1; 1961 } 1962 1963 static struct edid * 1964 intel_sdvo_get_edid(struct drm_connector *connector) 1965 { 1966 struct intel_sdvo *sdvo = intel_attached_sdvo(to_intel_connector(connector)); 1967 return drm_get_edid(connector, &sdvo->ddc); 1968 } 1969 1970 /* Mac mini hack -- use the same DDC as the analog connector */ 1971 static struct edid * 1972 intel_sdvo_get_analog_edid(struct drm_connector *connector) 1973 { 1974 struct drm_i915_private *dev_priv = to_i915(connector->dev); 1975 1976 return drm_get_edid(connector, 1977 intel_gmbus_get_adapter(dev_priv, 1978 dev_priv->vbt.crt_ddc_pin)); 1979 } 1980 1981 static enum drm_connector_status 1982 intel_sdvo_tmds_sink_detect(struct drm_connector *connector) 1983 { 1984 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(to_intel_connector(connector)); 1985 struct intel_sdvo_connector *intel_sdvo_connector = 1986 to_intel_sdvo_connector(connector); 1987 enum drm_connector_status status; 1988 struct edid *edid; 1989 1990 edid = intel_sdvo_get_edid(connector); 1991 1992 if (edid == NULL && intel_sdvo_multifunc_encoder(intel_sdvo)) { 1993 u8 ddc, saved_ddc = intel_sdvo->ddc_bus; 1994 1995 /* 1996 * Don't use the 1 as the argument of DDC bus switch to get 1997 * the EDID. It is used for SDVO SPD ROM. 1998 */ 1999 for (ddc = intel_sdvo->ddc_bus >> 1; ddc > 1; ddc >>= 1) { 2000 intel_sdvo->ddc_bus = ddc; 2001 edid = intel_sdvo_get_edid(connector); 2002 if (edid) 2003 break; 2004 } 2005 /* 2006 * If we found the EDID on the other bus, 2007 * assume that is the correct DDC bus. 2008 */ 2009 if (edid == NULL) 2010 intel_sdvo->ddc_bus = saved_ddc; 2011 } 2012 2013 /* 2014 * When there is no edid and no monitor is connected with VGA 2015 * port, try to use the CRT ddc to read the EDID for DVI-connector. 2016 */ 2017 if (edid == NULL) 2018 edid = intel_sdvo_get_analog_edid(connector); 2019 2020 status = connector_status_unknown; 2021 if (edid != NULL) { 2022 /* DDC bus is shared, match EDID to connector type */ 2023 if (edid->input & DRM_EDID_INPUT_DIGITAL) { 2024 status = connector_status_connected; 2025 if (intel_sdvo_connector->is_hdmi) { 2026 intel_sdvo->has_hdmi_monitor = drm_detect_hdmi_monitor(edid); 2027 intel_sdvo->has_hdmi_audio = drm_detect_monitor_audio(edid); 2028 } 2029 } else 2030 status = connector_status_disconnected; 2031 kfree(edid); 2032 } 2033 2034 return status; 2035 } 2036 2037 static bool 2038 intel_sdvo_connector_matches_edid(struct intel_sdvo_connector *sdvo, 2039 struct edid *edid) 2040 { 2041 bool monitor_is_digital = !!(edid->input & DRM_EDID_INPUT_DIGITAL); 2042 bool connector_is_digital = !!IS_DIGITAL(sdvo); 2043 2044 DRM_DEBUG_KMS("connector_is_digital? %d, monitor_is_digital? %d\n", 2045 connector_is_digital, monitor_is_digital); 2046 return connector_is_digital == monitor_is_digital; 2047 } 2048 2049 static enum drm_connector_status 2050 intel_sdvo_detect(struct drm_connector *connector, bool force) 2051 { 2052 u16 response; 2053 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(to_intel_connector(connector)); 2054 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector); 2055 enum drm_connector_status ret; 2056 2057 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", 2058 connector->base.id, connector->name); 2059 2060 if (!intel_sdvo_get_value(intel_sdvo, 2061 SDVO_CMD_GET_ATTACHED_DISPLAYS, 2062 &response, 2)) 2063 return connector_status_unknown; 2064 2065 DRM_DEBUG_KMS("SDVO response %d %d [%x]\n", 2066 response & 0xff, response >> 8, 2067 intel_sdvo_connector->output_flag); 2068 2069 if (response == 0) 2070 return connector_status_disconnected; 2071 2072 intel_sdvo->attached_output = response; 2073 2074 intel_sdvo->has_hdmi_monitor = false; 2075 intel_sdvo->has_hdmi_audio = false; 2076 2077 if ((intel_sdvo_connector->output_flag & response) == 0) 2078 ret = connector_status_disconnected; 2079 else if (IS_TMDS(intel_sdvo_connector)) 2080 ret = intel_sdvo_tmds_sink_detect(connector); 2081 else { 2082 struct edid *edid; 2083 2084 /* if we have an edid check it matches the connection */ 2085 edid = intel_sdvo_get_edid(connector); 2086 if (edid == NULL) 2087 edid = intel_sdvo_get_analog_edid(connector); 2088 if (edid != NULL) { 2089 if (intel_sdvo_connector_matches_edid(intel_sdvo_connector, 2090 edid)) 2091 ret = connector_status_connected; 2092 else 2093 ret = connector_status_disconnected; 2094 2095 kfree(edid); 2096 } else 2097 ret = connector_status_connected; 2098 } 2099 2100 return ret; 2101 } 2102 2103 static void intel_sdvo_get_ddc_modes(struct drm_connector *connector) 2104 { 2105 struct edid *edid; 2106 2107 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", 2108 connector->base.id, connector->name); 2109 2110 /* set the bus switch and get the modes */ 2111 edid = intel_sdvo_get_edid(connector); 2112 2113 /* 2114 * Mac mini hack. On this device, the DVI-I connector shares one DDC 2115 * link between analog and digital outputs. So, if the regular SDVO 2116 * DDC fails, check to see if the analog output is disconnected, in 2117 * which case we'll look there for the digital DDC data. 2118 */ 2119 if (edid == NULL) 2120 edid = intel_sdvo_get_analog_edid(connector); 2121 2122 if (edid != NULL) { 2123 if (intel_sdvo_connector_matches_edid(to_intel_sdvo_connector(connector), 2124 edid)) { 2125 drm_connector_update_edid_property(connector, edid); 2126 drm_add_edid_modes(connector, edid); 2127 } 2128 2129 kfree(edid); 2130 } 2131 } 2132 2133 /* 2134 * Set of SDVO TV modes. 2135 * Note! This is in reply order (see loop in get_tv_modes). 2136 * XXX: all 60Hz refresh? 2137 */ 2138 static const struct drm_display_mode sdvo_tv_modes[] = { 2139 { DRM_MODE("320x200", DRM_MODE_TYPE_DRIVER, 5815, 320, 321, 384, 2140 416, 0, 200, 201, 232, 233, 0, 2141 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 2142 { DRM_MODE("320x240", DRM_MODE_TYPE_DRIVER, 6814, 320, 321, 384, 2143 416, 0, 240, 241, 272, 273, 0, 2144 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 2145 { DRM_MODE("400x300", DRM_MODE_TYPE_DRIVER, 9910, 400, 401, 464, 2146 496, 0, 300, 301, 332, 333, 0, 2147 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 2148 { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 16913, 640, 641, 704, 2149 736, 0, 350, 351, 382, 383, 0, 2150 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 2151 { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 19121, 640, 641, 704, 2152 736, 0, 400, 401, 432, 433, 0, 2153 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 2154 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 22654, 640, 641, 704, 2155 736, 0, 480, 481, 512, 513, 0, 2156 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 2157 { DRM_MODE("704x480", DRM_MODE_TYPE_DRIVER, 24624, 704, 705, 768, 2158 800, 0, 480, 481, 512, 513, 0, 2159 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 2160 { DRM_MODE("704x576", DRM_MODE_TYPE_DRIVER, 29232, 704, 705, 768, 2161 800, 0, 576, 577, 608, 609, 0, 2162 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 2163 { DRM_MODE("720x350", DRM_MODE_TYPE_DRIVER, 18751, 720, 721, 784, 2164 816, 0, 350, 351, 382, 383, 0, 2165 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 2166 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 21199, 720, 721, 784, 2167 816, 0, 400, 401, 432, 433, 0, 2168 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 2169 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 25116, 720, 721, 784, 2170 816, 0, 480, 481, 512, 513, 0, 2171 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 2172 { DRM_MODE("720x540", DRM_MODE_TYPE_DRIVER, 28054, 720, 721, 784, 2173 816, 0, 540, 541, 572, 573, 0, 2174 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 2175 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 29816, 720, 721, 784, 2176 816, 0, 576, 577, 608, 609, 0, 2177 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 2178 { DRM_MODE("768x576", DRM_MODE_TYPE_DRIVER, 31570, 768, 769, 832, 2179 864, 0, 576, 577, 608, 609, 0, 2180 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 2181 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 34030, 800, 801, 864, 2182 896, 0, 600, 601, 632, 633, 0, 2183 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 2184 { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 36581, 832, 833, 896, 2185 928, 0, 624, 625, 656, 657, 0, 2186 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 2187 { DRM_MODE("920x766", DRM_MODE_TYPE_DRIVER, 48707, 920, 921, 984, 2188 1016, 0, 766, 767, 798, 799, 0, 2189 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 2190 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 53827, 1024, 1025, 1088, 2191 1120, 0, 768, 769, 800, 801, 0, 2192 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 2193 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 87265, 1280, 1281, 1344, 2194 1376, 0, 1024, 1025, 1056, 1057, 0, 2195 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 2196 }; 2197 2198 static void intel_sdvo_get_tv_modes(struct drm_connector *connector) 2199 { 2200 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(to_intel_connector(connector)); 2201 const struct drm_connector_state *conn_state = connector->state; 2202 struct intel_sdvo_sdtv_resolution_request tv_res; 2203 u32 reply = 0, format_map = 0; 2204 int i; 2205 2206 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", 2207 connector->base.id, connector->name); 2208 2209 /* 2210 * Read the list of supported input resolutions for the selected TV 2211 * format. 2212 */ 2213 format_map = 1 << conn_state->tv.mode; 2214 memcpy(&tv_res, &format_map, 2215 min(sizeof(format_map), sizeof(struct intel_sdvo_sdtv_resolution_request))); 2216 2217 if (!intel_sdvo_set_target_output(intel_sdvo, intel_sdvo->attached_output)) 2218 return; 2219 2220 BUILD_BUG_ON(sizeof(tv_res) != 3); 2221 if (!intel_sdvo_write_cmd(intel_sdvo, 2222 SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT, 2223 &tv_res, sizeof(tv_res))) 2224 return; 2225 if (!intel_sdvo_read_response(intel_sdvo, &reply, 3)) 2226 return; 2227 2228 for (i = 0; i < ARRAY_SIZE(sdvo_tv_modes); i++) 2229 if (reply & (1 << i)) { 2230 struct drm_display_mode *nmode; 2231 nmode = drm_mode_duplicate(connector->dev, 2232 &sdvo_tv_modes[i]); 2233 if (nmode) 2234 drm_mode_probed_add(connector, nmode); 2235 } 2236 } 2237 2238 static void intel_sdvo_get_lvds_modes(struct drm_connector *connector) 2239 { 2240 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(to_intel_connector(connector)); 2241 struct drm_i915_private *dev_priv = to_i915(connector->dev); 2242 struct drm_display_mode *newmode; 2243 2244 drm_dbg_kms(&dev_priv->drm, "[CONNECTOR:%d:%s]\n", 2245 connector->base.id, connector->name); 2246 2247 /* 2248 * Fetch modes from VBT. For SDVO prefer the VBT mode since some 2249 * SDVO->LVDS transcoders can't cope with the EDID mode. 2250 */ 2251 if (dev_priv->vbt.sdvo_lvds_vbt_mode != NULL) { 2252 newmode = drm_mode_duplicate(connector->dev, 2253 dev_priv->vbt.sdvo_lvds_vbt_mode); 2254 if (newmode != NULL) { 2255 /* Guarantee the mode is preferred */ 2256 newmode->type = (DRM_MODE_TYPE_PREFERRED | 2257 DRM_MODE_TYPE_DRIVER); 2258 drm_mode_probed_add(connector, newmode); 2259 } 2260 } 2261 2262 /* 2263 * Attempt to get the mode list from DDC. 2264 * Assume that the preferred modes are 2265 * arranged in priority order. 2266 */ 2267 intel_ddc_get_modes(connector, &intel_sdvo->ddc); 2268 } 2269 2270 static int intel_sdvo_get_modes(struct drm_connector *connector) 2271 { 2272 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector); 2273 2274 if (IS_TV(intel_sdvo_connector)) 2275 intel_sdvo_get_tv_modes(connector); 2276 else if (IS_LVDS(intel_sdvo_connector)) 2277 intel_sdvo_get_lvds_modes(connector); 2278 else 2279 intel_sdvo_get_ddc_modes(connector); 2280 2281 return !list_empty(&connector->probed_modes); 2282 } 2283 2284 static int 2285 intel_sdvo_connector_atomic_get_property(struct drm_connector *connector, 2286 const struct drm_connector_state *state, 2287 struct drm_property *property, 2288 u64 *val) 2289 { 2290 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector); 2291 const struct intel_sdvo_connector_state *sdvo_state = to_intel_sdvo_connector_state((void *)state); 2292 2293 if (property == intel_sdvo_connector->tv_format) { 2294 int i; 2295 2296 for (i = 0; i < intel_sdvo_connector->format_supported_num; i++) 2297 if (state->tv.mode == intel_sdvo_connector->tv_format_supported[i]) { 2298 *val = i; 2299 2300 return 0; 2301 } 2302 2303 drm_WARN_ON(connector->dev, 1); 2304 *val = 0; 2305 } else if (property == intel_sdvo_connector->top || 2306 property == intel_sdvo_connector->bottom) 2307 *val = intel_sdvo_connector->max_vscan - sdvo_state->tv.overscan_v; 2308 else if (property == intel_sdvo_connector->left || 2309 property == intel_sdvo_connector->right) 2310 *val = intel_sdvo_connector->max_hscan - sdvo_state->tv.overscan_h; 2311 else if (property == intel_sdvo_connector->hpos) 2312 *val = sdvo_state->tv.hpos; 2313 else if (property == intel_sdvo_connector->vpos) 2314 *val = sdvo_state->tv.vpos; 2315 else if (property == intel_sdvo_connector->saturation) 2316 *val = state->tv.saturation; 2317 else if (property == intel_sdvo_connector->contrast) 2318 *val = state->tv.contrast; 2319 else if (property == intel_sdvo_connector->hue) 2320 *val = state->tv.hue; 2321 else if (property == intel_sdvo_connector->brightness) 2322 *val = state->tv.brightness; 2323 else if (property == intel_sdvo_connector->sharpness) 2324 *val = sdvo_state->tv.sharpness; 2325 else if (property == intel_sdvo_connector->flicker_filter) 2326 *val = sdvo_state->tv.flicker_filter; 2327 else if (property == intel_sdvo_connector->flicker_filter_2d) 2328 *val = sdvo_state->tv.flicker_filter_2d; 2329 else if (property == intel_sdvo_connector->flicker_filter_adaptive) 2330 *val = sdvo_state->tv.flicker_filter_adaptive; 2331 else if (property == intel_sdvo_connector->tv_chroma_filter) 2332 *val = sdvo_state->tv.chroma_filter; 2333 else if (property == intel_sdvo_connector->tv_luma_filter) 2334 *val = sdvo_state->tv.luma_filter; 2335 else if (property == intel_sdvo_connector->dot_crawl) 2336 *val = sdvo_state->tv.dot_crawl; 2337 else 2338 return intel_digital_connector_atomic_get_property(connector, state, property, val); 2339 2340 return 0; 2341 } 2342 2343 static int 2344 intel_sdvo_connector_atomic_set_property(struct drm_connector *connector, 2345 struct drm_connector_state *state, 2346 struct drm_property *property, 2347 u64 val) 2348 { 2349 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector); 2350 struct intel_sdvo_connector_state *sdvo_state = to_intel_sdvo_connector_state(state); 2351 2352 if (property == intel_sdvo_connector->tv_format) { 2353 state->tv.mode = intel_sdvo_connector->tv_format_supported[val]; 2354 2355 if (state->crtc) { 2356 struct drm_crtc_state *crtc_state = 2357 drm_atomic_get_new_crtc_state(state->state, state->crtc); 2358 2359 crtc_state->connectors_changed = true; 2360 } 2361 } else if (property == intel_sdvo_connector->top || 2362 property == intel_sdvo_connector->bottom) 2363 /* Cannot set these independent from each other */ 2364 sdvo_state->tv.overscan_v = intel_sdvo_connector->max_vscan - val; 2365 else if (property == intel_sdvo_connector->left || 2366 property == intel_sdvo_connector->right) 2367 /* Cannot set these independent from each other */ 2368 sdvo_state->tv.overscan_h = intel_sdvo_connector->max_hscan - val; 2369 else if (property == intel_sdvo_connector->hpos) 2370 sdvo_state->tv.hpos = val; 2371 else if (property == intel_sdvo_connector->vpos) 2372 sdvo_state->tv.vpos = val; 2373 else if (property == intel_sdvo_connector->saturation) 2374 state->tv.saturation = val; 2375 else if (property == intel_sdvo_connector->contrast) 2376 state->tv.contrast = val; 2377 else if (property == intel_sdvo_connector->hue) 2378 state->tv.hue = val; 2379 else if (property == intel_sdvo_connector->brightness) 2380 state->tv.brightness = val; 2381 else if (property == intel_sdvo_connector->sharpness) 2382 sdvo_state->tv.sharpness = val; 2383 else if (property == intel_sdvo_connector->flicker_filter) 2384 sdvo_state->tv.flicker_filter = val; 2385 else if (property == intel_sdvo_connector->flicker_filter_2d) 2386 sdvo_state->tv.flicker_filter_2d = val; 2387 else if (property == intel_sdvo_connector->flicker_filter_adaptive) 2388 sdvo_state->tv.flicker_filter_adaptive = val; 2389 else if (property == intel_sdvo_connector->tv_chroma_filter) 2390 sdvo_state->tv.chroma_filter = val; 2391 else if (property == intel_sdvo_connector->tv_luma_filter) 2392 sdvo_state->tv.luma_filter = val; 2393 else if (property == intel_sdvo_connector->dot_crawl) 2394 sdvo_state->tv.dot_crawl = val; 2395 else 2396 return intel_digital_connector_atomic_set_property(connector, state, property, val); 2397 2398 return 0; 2399 } 2400 2401 static int 2402 intel_sdvo_connector_register(struct drm_connector *connector) 2403 { 2404 struct intel_sdvo *sdvo = intel_attached_sdvo(to_intel_connector(connector)); 2405 int ret; 2406 2407 ret = intel_connector_register(connector); 2408 if (ret) 2409 return ret; 2410 2411 return sysfs_create_link(&connector->kdev->kobj, 2412 &sdvo->ddc.dev.kobj, 2413 sdvo->ddc.dev.kobj.name); 2414 } 2415 2416 static void 2417 intel_sdvo_connector_unregister(struct drm_connector *connector) 2418 { 2419 struct intel_sdvo *sdvo = intel_attached_sdvo(to_intel_connector(connector)); 2420 2421 sysfs_remove_link(&connector->kdev->kobj, 2422 sdvo->ddc.dev.kobj.name); 2423 intel_connector_unregister(connector); 2424 } 2425 2426 static struct drm_connector_state * 2427 intel_sdvo_connector_duplicate_state(struct drm_connector *connector) 2428 { 2429 struct intel_sdvo_connector_state *state; 2430 2431 state = kmemdup(connector->state, sizeof(*state), GFP_KERNEL); 2432 if (!state) 2433 return NULL; 2434 2435 __drm_atomic_helper_connector_duplicate_state(connector, &state->base.base); 2436 return &state->base.base; 2437 } 2438 2439 static const struct drm_connector_funcs intel_sdvo_connector_funcs = { 2440 .detect = intel_sdvo_detect, 2441 .fill_modes = drm_helper_probe_single_connector_modes, 2442 .atomic_get_property = intel_sdvo_connector_atomic_get_property, 2443 .atomic_set_property = intel_sdvo_connector_atomic_set_property, 2444 .late_register = intel_sdvo_connector_register, 2445 .early_unregister = intel_sdvo_connector_unregister, 2446 .destroy = intel_connector_destroy, 2447 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 2448 .atomic_duplicate_state = intel_sdvo_connector_duplicate_state, 2449 }; 2450 2451 static int intel_sdvo_atomic_check(struct drm_connector *conn, 2452 struct drm_atomic_state *state) 2453 { 2454 struct drm_connector_state *new_conn_state = 2455 drm_atomic_get_new_connector_state(state, conn); 2456 struct drm_connector_state *old_conn_state = 2457 drm_atomic_get_old_connector_state(state, conn); 2458 struct intel_sdvo_connector_state *old_state = 2459 to_intel_sdvo_connector_state(old_conn_state); 2460 struct intel_sdvo_connector_state *new_state = 2461 to_intel_sdvo_connector_state(new_conn_state); 2462 2463 if (new_conn_state->crtc && 2464 (memcmp(&old_state->tv, &new_state->tv, sizeof(old_state->tv)) || 2465 memcmp(&old_conn_state->tv, &new_conn_state->tv, sizeof(old_conn_state->tv)))) { 2466 struct drm_crtc_state *crtc_state = 2467 drm_atomic_get_new_crtc_state(state, 2468 new_conn_state->crtc); 2469 2470 crtc_state->connectors_changed = true; 2471 } 2472 2473 return intel_digital_connector_atomic_check(conn, state); 2474 } 2475 2476 static const struct drm_connector_helper_funcs intel_sdvo_connector_helper_funcs = { 2477 .get_modes = intel_sdvo_get_modes, 2478 .mode_valid = intel_sdvo_mode_valid, 2479 .atomic_check = intel_sdvo_atomic_check, 2480 }; 2481 2482 static void intel_sdvo_enc_destroy(struct drm_encoder *encoder) 2483 { 2484 struct intel_sdvo *intel_sdvo = to_sdvo(to_intel_encoder(encoder)); 2485 2486 i2c_del_adapter(&intel_sdvo->ddc); 2487 intel_encoder_destroy(encoder); 2488 } 2489 2490 static const struct drm_encoder_funcs intel_sdvo_enc_funcs = { 2491 .destroy = intel_sdvo_enc_destroy, 2492 }; 2493 2494 static void 2495 intel_sdvo_guess_ddc_bus(struct intel_sdvo *sdvo) 2496 { 2497 u16 mask = 0; 2498 unsigned int num_bits; 2499 2500 /* 2501 * Make a mask of outputs less than or equal to our own priority in the 2502 * list. 2503 */ 2504 switch (sdvo->controlled_output) { 2505 case SDVO_OUTPUT_LVDS1: 2506 mask |= SDVO_OUTPUT_LVDS1; 2507 /* fall through */ 2508 case SDVO_OUTPUT_LVDS0: 2509 mask |= SDVO_OUTPUT_LVDS0; 2510 /* fall through */ 2511 case SDVO_OUTPUT_TMDS1: 2512 mask |= SDVO_OUTPUT_TMDS1; 2513 /* fall through */ 2514 case SDVO_OUTPUT_TMDS0: 2515 mask |= SDVO_OUTPUT_TMDS0; 2516 /* fall through */ 2517 case SDVO_OUTPUT_RGB1: 2518 mask |= SDVO_OUTPUT_RGB1; 2519 /* fall through */ 2520 case SDVO_OUTPUT_RGB0: 2521 mask |= SDVO_OUTPUT_RGB0; 2522 break; 2523 } 2524 2525 /* Count bits to find what number we are in the priority list. */ 2526 mask &= sdvo->caps.output_flags; 2527 num_bits = hweight16(mask); 2528 /* If more than 3 outputs, default to DDC bus 3 for now. */ 2529 if (num_bits > 3) 2530 num_bits = 3; 2531 2532 /* Corresponds to SDVO_CONTROL_BUS_DDCx */ 2533 sdvo->ddc_bus = 1 << num_bits; 2534 } 2535 2536 /* 2537 * Choose the appropriate DDC bus for control bus switch command for this 2538 * SDVO output based on the controlled output. 2539 * 2540 * DDC bus number assignment is in a priority order of RGB outputs, then TMDS 2541 * outputs, then LVDS outputs. 2542 */ 2543 static void 2544 intel_sdvo_select_ddc_bus(struct drm_i915_private *dev_priv, 2545 struct intel_sdvo *sdvo) 2546 { 2547 struct sdvo_device_mapping *mapping; 2548 2549 if (sdvo->port == PORT_B) 2550 mapping = &dev_priv->vbt.sdvo_mappings[0]; 2551 else 2552 mapping = &dev_priv->vbt.sdvo_mappings[1]; 2553 2554 if (mapping->initialized) 2555 sdvo->ddc_bus = 1 << ((mapping->ddc_pin & 0xf0) >> 4); 2556 else 2557 intel_sdvo_guess_ddc_bus(sdvo); 2558 } 2559 2560 static void 2561 intel_sdvo_select_i2c_bus(struct drm_i915_private *dev_priv, 2562 struct intel_sdvo *sdvo) 2563 { 2564 struct sdvo_device_mapping *mapping; 2565 u8 pin; 2566 2567 if (sdvo->port == PORT_B) 2568 mapping = &dev_priv->vbt.sdvo_mappings[0]; 2569 else 2570 mapping = &dev_priv->vbt.sdvo_mappings[1]; 2571 2572 if (mapping->initialized && 2573 intel_gmbus_is_valid_pin(dev_priv, mapping->i2c_pin)) 2574 pin = mapping->i2c_pin; 2575 else 2576 pin = GMBUS_PIN_DPB; 2577 2578 sdvo->i2c = intel_gmbus_get_adapter(dev_priv, pin); 2579 2580 /* 2581 * With gmbus we should be able to drive sdvo i2c at 2MHz, but somehow 2582 * our code totally fails once we start using gmbus. Hence fall back to 2583 * bit banging for now. 2584 */ 2585 intel_gmbus_force_bit(sdvo->i2c, true); 2586 } 2587 2588 /* undo any changes intel_sdvo_select_i2c_bus() did to sdvo->i2c */ 2589 static void 2590 intel_sdvo_unselect_i2c_bus(struct intel_sdvo *sdvo) 2591 { 2592 intel_gmbus_force_bit(sdvo->i2c, false); 2593 } 2594 2595 static bool 2596 intel_sdvo_is_hdmi_connector(struct intel_sdvo *intel_sdvo, int device) 2597 { 2598 return intel_sdvo_check_supp_encode(intel_sdvo); 2599 } 2600 2601 static u8 2602 intel_sdvo_get_slave_addr(struct drm_i915_private *dev_priv, 2603 struct intel_sdvo *sdvo) 2604 { 2605 struct sdvo_device_mapping *my_mapping, *other_mapping; 2606 2607 if (sdvo->port == PORT_B) { 2608 my_mapping = &dev_priv->vbt.sdvo_mappings[0]; 2609 other_mapping = &dev_priv->vbt.sdvo_mappings[1]; 2610 } else { 2611 my_mapping = &dev_priv->vbt.sdvo_mappings[1]; 2612 other_mapping = &dev_priv->vbt.sdvo_mappings[0]; 2613 } 2614 2615 /* If the BIOS described our SDVO device, take advantage of it. */ 2616 if (my_mapping->slave_addr) 2617 return my_mapping->slave_addr; 2618 2619 /* 2620 * If the BIOS only described a different SDVO device, use the 2621 * address that it isn't using. 2622 */ 2623 if (other_mapping->slave_addr) { 2624 if (other_mapping->slave_addr == 0x70) 2625 return 0x72; 2626 else 2627 return 0x70; 2628 } 2629 2630 /* 2631 * No SDVO device info is found for another DVO port, 2632 * so use mapping assumption we had before BIOS parsing. 2633 */ 2634 if (sdvo->port == PORT_B) 2635 return 0x70; 2636 else 2637 return 0x72; 2638 } 2639 2640 static int 2641 intel_sdvo_connector_init(struct intel_sdvo_connector *connector, 2642 struct intel_sdvo *encoder) 2643 { 2644 struct drm_connector *drm_connector; 2645 int ret; 2646 2647 drm_connector = &connector->base.base; 2648 ret = drm_connector_init(encoder->base.base.dev, 2649 drm_connector, 2650 &intel_sdvo_connector_funcs, 2651 connector->base.base.connector_type); 2652 if (ret < 0) 2653 return ret; 2654 2655 drm_connector_helper_add(drm_connector, 2656 &intel_sdvo_connector_helper_funcs); 2657 2658 connector->base.base.interlace_allowed = 1; 2659 connector->base.base.doublescan_allowed = 0; 2660 connector->base.base.display_info.subpixel_order = SubPixelHorizontalRGB; 2661 connector->base.get_hw_state = intel_sdvo_connector_get_hw_state; 2662 2663 intel_connector_attach_encoder(&connector->base, &encoder->base); 2664 2665 return 0; 2666 } 2667 2668 static void 2669 intel_sdvo_add_hdmi_properties(struct intel_sdvo *intel_sdvo, 2670 struct intel_sdvo_connector *connector) 2671 { 2672 struct drm_i915_private *dev_priv = to_i915(connector->base.base.dev); 2673 2674 intel_attach_force_audio_property(&connector->base.base); 2675 if (INTEL_GEN(dev_priv) >= 4 && IS_MOBILE(dev_priv)) { 2676 intel_attach_broadcast_rgb_property(&connector->base.base); 2677 } 2678 intel_attach_aspect_ratio_property(&connector->base.base); 2679 } 2680 2681 static struct intel_sdvo_connector *intel_sdvo_connector_alloc(void) 2682 { 2683 struct intel_sdvo_connector *sdvo_connector; 2684 struct intel_sdvo_connector_state *conn_state; 2685 2686 sdvo_connector = kzalloc(sizeof(*sdvo_connector), GFP_KERNEL); 2687 if (!sdvo_connector) 2688 return NULL; 2689 2690 conn_state = kzalloc(sizeof(*conn_state), GFP_KERNEL); 2691 if (!conn_state) { 2692 kfree(sdvo_connector); 2693 return NULL; 2694 } 2695 2696 __drm_atomic_helper_connector_reset(&sdvo_connector->base.base, 2697 &conn_state->base.base); 2698 2699 return sdvo_connector; 2700 } 2701 2702 static bool 2703 intel_sdvo_dvi_init(struct intel_sdvo *intel_sdvo, int device) 2704 { 2705 struct drm_encoder *encoder = &intel_sdvo->base.base; 2706 struct drm_connector *connector; 2707 struct intel_encoder *intel_encoder = to_intel_encoder(encoder); 2708 struct intel_connector *intel_connector; 2709 struct intel_sdvo_connector *intel_sdvo_connector; 2710 2711 DRM_DEBUG_KMS("initialising DVI device %d\n", device); 2712 2713 intel_sdvo_connector = intel_sdvo_connector_alloc(); 2714 if (!intel_sdvo_connector) 2715 return false; 2716 2717 if (device == 0) { 2718 intel_sdvo->controlled_output |= SDVO_OUTPUT_TMDS0; 2719 intel_sdvo_connector->output_flag = SDVO_OUTPUT_TMDS0; 2720 } else if (device == 1) { 2721 intel_sdvo->controlled_output |= SDVO_OUTPUT_TMDS1; 2722 intel_sdvo_connector->output_flag = SDVO_OUTPUT_TMDS1; 2723 } 2724 2725 intel_connector = &intel_sdvo_connector->base; 2726 connector = &intel_connector->base; 2727 if (intel_sdvo_get_hotplug_support(intel_sdvo) & 2728 intel_sdvo_connector->output_flag) { 2729 intel_sdvo->hotplug_active |= intel_sdvo_connector->output_flag; 2730 /* 2731 * Some SDVO devices have one-shot hotplug interrupts. 2732 * Ensure that they get re-enabled when an interrupt happens. 2733 */ 2734 intel_connector->polled = DRM_CONNECTOR_POLL_HPD; 2735 intel_encoder->hotplug = intel_sdvo_hotplug; 2736 intel_sdvo_enable_hotplug(intel_encoder); 2737 } else { 2738 intel_connector->polled = DRM_CONNECTOR_POLL_CONNECT | DRM_CONNECTOR_POLL_DISCONNECT; 2739 } 2740 encoder->encoder_type = DRM_MODE_ENCODER_TMDS; 2741 connector->connector_type = DRM_MODE_CONNECTOR_DVID; 2742 2743 if (intel_sdvo_is_hdmi_connector(intel_sdvo, device)) { 2744 connector->connector_type = DRM_MODE_CONNECTOR_HDMIA; 2745 intel_sdvo_connector->is_hdmi = true; 2746 } 2747 2748 if (intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo) < 0) { 2749 kfree(intel_sdvo_connector); 2750 return false; 2751 } 2752 2753 if (intel_sdvo_connector->is_hdmi) 2754 intel_sdvo_add_hdmi_properties(intel_sdvo, intel_sdvo_connector); 2755 2756 return true; 2757 } 2758 2759 static bool 2760 intel_sdvo_tv_init(struct intel_sdvo *intel_sdvo, int type) 2761 { 2762 struct drm_encoder *encoder = &intel_sdvo->base.base; 2763 struct drm_connector *connector; 2764 struct intel_connector *intel_connector; 2765 struct intel_sdvo_connector *intel_sdvo_connector; 2766 2767 DRM_DEBUG_KMS("initialising TV type %d\n", type); 2768 2769 intel_sdvo_connector = intel_sdvo_connector_alloc(); 2770 if (!intel_sdvo_connector) 2771 return false; 2772 2773 intel_connector = &intel_sdvo_connector->base; 2774 connector = &intel_connector->base; 2775 encoder->encoder_type = DRM_MODE_ENCODER_TVDAC; 2776 connector->connector_type = DRM_MODE_CONNECTOR_SVIDEO; 2777 2778 intel_sdvo->controlled_output |= type; 2779 intel_sdvo_connector->output_flag = type; 2780 2781 if (intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo) < 0) { 2782 kfree(intel_sdvo_connector); 2783 return false; 2784 } 2785 2786 if (!intel_sdvo_tv_create_property(intel_sdvo, intel_sdvo_connector, type)) 2787 goto err; 2788 2789 if (!intel_sdvo_create_enhance_property(intel_sdvo, intel_sdvo_connector)) 2790 goto err; 2791 2792 return true; 2793 2794 err: 2795 intel_connector_destroy(connector); 2796 return false; 2797 } 2798 2799 static bool 2800 intel_sdvo_analog_init(struct intel_sdvo *intel_sdvo, int device) 2801 { 2802 struct drm_encoder *encoder = &intel_sdvo->base.base; 2803 struct drm_connector *connector; 2804 struct intel_connector *intel_connector; 2805 struct intel_sdvo_connector *intel_sdvo_connector; 2806 2807 DRM_DEBUG_KMS("initialising analog device %d\n", device); 2808 2809 intel_sdvo_connector = intel_sdvo_connector_alloc(); 2810 if (!intel_sdvo_connector) 2811 return false; 2812 2813 intel_connector = &intel_sdvo_connector->base; 2814 connector = &intel_connector->base; 2815 intel_connector->polled = DRM_CONNECTOR_POLL_CONNECT; 2816 encoder->encoder_type = DRM_MODE_ENCODER_DAC; 2817 connector->connector_type = DRM_MODE_CONNECTOR_VGA; 2818 2819 if (device == 0) { 2820 intel_sdvo->controlled_output |= SDVO_OUTPUT_RGB0; 2821 intel_sdvo_connector->output_flag = SDVO_OUTPUT_RGB0; 2822 } else if (device == 1) { 2823 intel_sdvo->controlled_output |= SDVO_OUTPUT_RGB1; 2824 intel_sdvo_connector->output_flag = SDVO_OUTPUT_RGB1; 2825 } 2826 2827 if (intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo) < 0) { 2828 kfree(intel_sdvo_connector); 2829 return false; 2830 } 2831 2832 return true; 2833 } 2834 2835 static bool 2836 intel_sdvo_lvds_init(struct intel_sdvo *intel_sdvo, int device) 2837 { 2838 struct drm_encoder *encoder = &intel_sdvo->base.base; 2839 struct drm_connector *connector; 2840 struct intel_connector *intel_connector; 2841 struct intel_sdvo_connector *intel_sdvo_connector; 2842 struct drm_display_mode *mode; 2843 2844 DRM_DEBUG_KMS("initialising LVDS device %d\n", device); 2845 2846 intel_sdvo_connector = intel_sdvo_connector_alloc(); 2847 if (!intel_sdvo_connector) 2848 return false; 2849 2850 intel_connector = &intel_sdvo_connector->base; 2851 connector = &intel_connector->base; 2852 encoder->encoder_type = DRM_MODE_ENCODER_LVDS; 2853 connector->connector_type = DRM_MODE_CONNECTOR_LVDS; 2854 2855 if (device == 0) { 2856 intel_sdvo->controlled_output |= SDVO_OUTPUT_LVDS0; 2857 intel_sdvo_connector->output_flag = SDVO_OUTPUT_LVDS0; 2858 } else if (device == 1) { 2859 intel_sdvo->controlled_output |= SDVO_OUTPUT_LVDS1; 2860 intel_sdvo_connector->output_flag = SDVO_OUTPUT_LVDS1; 2861 } 2862 2863 if (intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo) < 0) { 2864 kfree(intel_sdvo_connector); 2865 return false; 2866 } 2867 2868 if (!intel_sdvo_create_enhance_property(intel_sdvo, intel_sdvo_connector)) 2869 goto err; 2870 2871 intel_sdvo_get_lvds_modes(connector); 2872 2873 list_for_each_entry(mode, &connector->probed_modes, head) { 2874 if (mode->type & DRM_MODE_TYPE_PREFERRED) { 2875 struct drm_display_mode *fixed_mode = 2876 drm_mode_duplicate(connector->dev, mode); 2877 2878 intel_panel_init(&intel_connector->panel, 2879 fixed_mode, NULL); 2880 break; 2881 } 2882 } 2883 2884 if (!intel_connector->panel.fixed_mode) 2885 goto err; 2886 2887 return true; 2888 2889 err: 2890 intel_connector_destroy(connector); 2891 return false; 2892 } 2893 2894 static bool 2895 intel_sdvo_output_setup(struct intel_sdvo *intel_sdvo, u16 flags) 2896 { 2897 /* SDVO requires XXX1 function may not exist unless it has XXX0 function.*/ 2898 2899 if (flags & SDVO_OUTPUT_TMDS0) 2900 if (!intel_sdvo_dvi_init(intel_sdvo, 0)) 2901 return false; 2902 2903 if ((flags & SDVO_TMDS_MASK) == SDVO_TMDS_MASK) 2904 if (!intel_sdvo_dvi_init(intel_sdvo, 1)) 2905 return false; 2906 2907 /* TV has no XXX1 function block */ 2908 if (flags & SDVO_OUTPUT_SVID0) 2909 if (!intel_sdvo_tv_init(intel_sdvo, SDVO_OUTPUT_SVID0)) 2910 return false; 2911 2912 if (flags & SDVO_OUTPUT_CVBS0) 2913 if (!intel_sdvo_tv_init(intel_sdvo, SDVO_OUTPUT_CVBS0)) 2914 return false; 2915 2916 if (flags & SDVO_OUTPUT_YPRPB0) 2917 if (!intel_sdvo_tv_init(intel_sdvo, SDVO_OUTPUT_YPRPB0)) 2918 return false; 2919 2920 if (flags & SDVO_OUTPUT_RGB0) 2921 if (!intel_sdvo_analog_init(intel_sdvo, 0)) 2922 return false; 2923 2924 if ((flags & SDVO_RGB_MASK) == SDVO_RGB_MASK) 2925 if (!intel_sdvo_analog_init(intel_sdvo, 1)) 2926 return false; 2927 2928 if (flags & SDVO_OUTPUT_LVDS0) 2929 if (!intel_sdvo_lvds_init(intel_sdvo, 0)) 2930 return false; 2931 2932 if ((flags & SDVO_LVDS_MASK) == SDVO_LVDS_MASK) 2933 if (!intel_sdvo_lvds_init(intel_sdvo, 1)) 2934 return false; 2935 2936 if ((flags & SDVO_OUTPUT_MASK) == 0) { 2937 unsigned char bytes[2]; 2938 2939 intel_sdvo->controlled_output = 0; 2940 memcpy(bytes, &intel_sdvo->caps.output_flags, 2); 2941 DRM_DEBUG_KMS("%s: Unknown SDVO output type (0x%02x%02x)\n", 2942 SDVO_NAME(intel_sdvo), 2943 bytes[0], bytes[1]); 2944 return false; 2945 } 2946 intel_sdvo->base.pipe_mask = ~0; 2947 2948 return true; 2949 } 2950 2951 static void intel_sdvo_output_cleanup(struct intel_sdvo *intel_sdvo) 2952 { 2953 struct drm_device *dev = intel_sdvo->base.base.dev; 2954 struct drm_connector *connector, *tmp; 2955 2956 list_for_each_entry_safe(connector, tmp, 2957 &dev->mode_config.connector_list, head) { 2958 if (intel_attached_encoder(to_intel_connector(connector)) == &intel_sdvo->base) { 2959 drm_connector_unregister(connector); 2960 intel_connector_destroy(connector); 2961 } 2962 } 2963 } 2964 2965 static bool intel_sdvo_tv_create_property(struct intel_sdvo *intel_sdvo, 2966 struct intel_sdvo_connector *intel_sdvo_connector, 2967 int type) 2968 { 2969 struct drm_device *dev = intel_sdvo->base.base.dev; 2970 struct intel_sdvo_tv_format format; 2971 u32 format_map, i; 2972 2973 if (!intel_sdvo_set_target_output(intel_sdvo, type)) 2974 return false; 2975 2976 BUILD_BUG_ON(sizeof(format) != 6); 2977 if (!intel_sdvo_get_value(intel_sdvo, 2978 SDVO_CMD_GET_SUPPORTED_TV_FORMATS, 2979 &format, sizeof(format))) 2980 return false; 2981 2982 memcpy(&format_map, &format, min(sizeof(format_map), sizeof(format))); 2983 2984 if (format_map == 0) 2985 return false; 2986 2987 intel_sdvo_connector->format_supported_num = 0; 2988 for (i = 0 ; i < TV_FORMAT_NUM; i++) 2989 if (format_map & (1 << i)) 2990 intel_sdvo_connector->tv_format_supported[intel_sdvo_connector->format_supported_num++] = i; 2991 2992 2993 intel_sdvo_connector->tv_format = 2994 drm_property_create(dev, DRM_MODE_PROP_ENUM, 2995 "mode", intel_sdvo_connector->format_supported_num); 2996 if (!intel_sdvo_connector->tv_format) 2997 return false; 2998 2999 for (i = 0; i < intel_sdvo_connector->format_supported_num; i++) 3000 drm_property_add_enum(intel_sdvo_connector->tv_format, i, 3001 tv_format_names[intel_sdvo_connector->tv_format_supported[i]]); 3002 3003 intel_sdvo_connector->base.base.state->tv.mode = intel_sdvo_connector->tv_format_supported[0]; 3004 drm_object_attach_property(&intel_sdvo_connector->base.base.base, 3005 intel_sdvo_connector->tv_format, 0); 3006 return true; 3007 3008 } 3009 3010 #define _ENHANCEMENT(state_assignment, name, NAME) do { \ 3011 if (enhancements.name) { \ 3012 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_MAX_##NAME, &data_value, 4) || \ 3013 !intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_##NAME, &response, 2)) \ 3014 return false; \ 3015 intel_sdvo_connector->name = \ 3016 drm_property_create_range(dev, 0, #name, 0, data_value[0]); \ 3017 if (!intel_sdvo_connector->name) return false; \ 3018 state_assignment = response; \ 3019 drm_object_attach_property(&connector->base, \ 3020 intel_sdvo_connector->name, 0); \ 3021 DRM_DEBUG_KMS(#name ": max %d, default %d, current %d\n", \ 3022 data_value[0], data_value[1], response); \ 3023 } \ 3024 } while (0) 3025 3026 #define ENHANCEMENT(state, name, NAME) _ENHANCEMENT((state)->name, name, NAME) 3027 3028 static bool 3029 intel_sdvo_create_enhance_property_tv(struct intel_sdvo *intel_sdvo, 3030 struct intel_sdvo_connector *intel_sdvo_connector, 3031 struct intel_sdvo_enhancements_reply enhancements) 3032 { 3033 struct drm_device *dev = intel_sdvo->base.base.dev; 3034 struct drm_connector *connector = &intel_sdvo_connector->base.base; 3035 struct drm_connector_state *conn_state = connector->state; 3036 struct intel_sdvo_connector_state *sdvo_state = 3037 to_intel_sdvo_connector_state(conn_state); 3038 u16 response, data_value[2]; 3039 3040 /* when horizontal overscan is supported, Add the left/right property */ 3041 if (enhancements.overscan_h) { 3042 if (!intel_sdvo_get_value(intel_sdvo, 3043 SDVO_CMD_GET_MAX_OVERSCAN_H, 3044 &data_value, 4)) 3045 return false; 3046 3047 if (!intel_sdvo_get_value(intel_sdvo, 3048 SDVO_CMD_GET_OVERSCAN_H, 3049 &response, 2)) 3050 return false; 3051 3052 sdvo_state->tv.overscan_h = response; 3053 3054 intel_sdvo_connector->max_hscan = data_value[0]; 3055 intel_sdvo_connector->left = 3056 drm_property_create_range(dev, 0, "left_margin", 0, data_value[0]); 3057 if (!intel_sdvo_connector->left) 3058 return false; 3059 3060 drm_object_attach_property(&connector->base, 3061 intel_sdvo_connector->left, 0); 3062 3063 intel_sdvo_connector->right = 3064 drm_property_create_range(dev, 0, "right_margin", 0, data_value[0]); 3065 if (!intel_sdvo_connector->right) 3066 return false; 3067 3068 drm_object_attach_property(&connector->base, 3069 intel_sdvo_connector->right, 0); 3070 DRM_DEBUG_KMS("h_overscan: max %d, " 3071 "default %d, current %d\n", 3072 data_value[0], data_value[1], response); 3073 } 3074 3075 if (enhancements.overscan_v) { 3076 if (!intel_sdvo_get_value(intel_sdvo, 3077 SDVO_CMD_GET_MAX_OVERSCAN_V, 3078 &data_value, 4)) 3079 return false; 3080 3081 if (!intel_sdvo_get_value(intel_sdvo, 3082 SDVO_CMD_GET_OVERSCAN_V, 3083 &response, 2)) 3084 return false; 3085 3086 sdvo_state->tv.overscan_v = response; 3087 3088 intel_sdvo_connector->max_vscan = data_value[0]; 3089 intel_sdvo_connector->top = 3090 drm_property_create_range(dev, 0, 3091 "top_margin", 0, data_value[0]); 3092 if (!intel_sdvo_connector->top) 3093 return false; 3094 3095 drm_object_attach_property(&connector->base, 3096 intel_sdvo_connector->top, 0); 3097 3098 intel_sdvo_connector->bottom = 3099 drm_property_create_range(dev, 0, 3100 "bottom_margin", 0, data_value[0]); 3101 if (!intel_sdvo_connector->bottom) 3102 return false; 3103 3104 drm_object_attach_property(&connector->base, 3105 intel_sdvo_connector->bottom, 0); 3106 DRM_DEBUG_KMS("v_overscan: max %d, " 3107 "default %d, current %d\n", 3108 data_value[0], data_value[1], response); 3109 } 3110 3111 ENHANCEMENT(&sdvo_state->tv, hpos, HPOS); 3112 ENHANCEMENT(&sdvo_state->tv, vpos, VPOS); 3113 ENHANCEMENT(&conn_state->tv, saturation, SATURATION); 3114 ENHANCEMENT(&conn_state->tv, contrast, CONTRAST); 3115 ENHANCEMENT(&conn_state->tv, hue, HUE); 3116 ENHANCEMENT(&conn_state->tv, brightness, BRIGHTNESS); 3117 ENHANCEMENT(&sdvo_state->tv, sharpness, SHARPNESS); 3118 ENHANCEMENT(&sdvo_state->tv, flicker_filter, FLICKER_FILTER); 3119 ENHANCEMENT(&sdvo_state->tv, flicker_filter_adaptive, FLICKER_FILTER_ADAPTIVE); 3120 ENHANCEMENT(&sdvo_state->tv, flicker_filter_2d, FLICKER_FILTER_2D); 3121 _ENHANCEMENT(sdvo_state->tv.chroma_filter, tv_chroma_filter, TV_CHROMA_FILTER); 3122 _ENHANCEMENT(sdvo_state->tv.luma_filter, tv_luma_filter, TV_LUMA_FILTER); 3123 3124 if (enhancements.dot_crawl) { 3125 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_DOT_CRAWL, &response, 2)) 3126 return false; 3127 3128 sdvo_state->tv.dot_crawl = response & 0x1; 3129 intel_sdvo_connector->dot_crawl = 3130 drm_property_create_range(dev, 0, "dot_crawl", 0, 1); 3131 if (!intel_sdvo_connector->dot_crawl) 3132 return false; 3133 3134 drm_object_attach_property(&connector->base, 3135 intel_sdvo_connector->dot_crawl, 0); 3136 DRM_DEBUG_KMS("dot crawl: current %d\n", response); 3137 } 3138 3139 return true; 3140 } 3141 3142 static bool 3143 intel_sdvo_create_enhance_property_lvds(struct intel_sdvo *intel_sdvo, 3144 struct intel_sdvo_connector *intel_sdvo_connector, 3145 struct intel_sdvo_enhancements_reply enhancements) 3146 { 3147 struct drm_device *dev = intel_sdvo->base.base.dev; 3148 struct drm_connector *connector = &intel_sdvo_connector->base.base; 3149 u16 response, data_value[2]; 3150 3151 ENHANCEMENT(&connector->state->tv, brightness, BRIGHTNESS); 3152 3153 return true; 3154 } 3155 #undef ENHANCEMENT 3156 #undef _ENHANCEMENT 3157 3158 static bool intel_sdvo_create_enhance_property(struct intel_sdvo *intel_sdvo, 3159 struct intel_sdvo_connector *intel_sdvo_connector) 3160 { 3161 union { 3162 struct intel_sdvo_enhancements_reply reply; 3163 u16 response; 3164 } enhancements; 3165 3166 BUILD_BUG_ON(sizeof(enhancements) != 2); 3167 3168 if (!intel_sdvo_get_value(intel_sdvo, 3169 SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS, 3170 &enhancements, sizeof(enhancements)) || 3171 enhancements.response == 0) { 3172 DRM_DEBUG_KMS("No enhancement is supported\n"); 3173 return true; 3174 } 3175 3176 if (IS_TV(intel_sdvo_connector)) 3177 return intel_sdvo_create_enhance_property_tv(intel_sdvo, intel_sdvo_connector, enhancements.reply); 3178 else if (IS_LVDS(intel_sdvo_connector)) 3179 return intel_sdvo_create_enhance_property_lvds(intel_sdvo, intel_sdvo_connector, enhancements.reply); 3180 else 3181 return true; 3182 } 3183 3184 static int intel_sdvo_ddc_proxy_xfer(struct i2c_adapter *adapter, 3185 struct i2c_msg *msgs, 3186 int num) 3187 { 3188 struct intel_sdvo *sdvo = adapter->algo_data; 3189 3190 if (!__intel_sdvo_set_control_bus_switch(sdvo, sdvo->ddc_bus)) 3191 return -EIO; 3192 3193 return sdvo->i2c->algo->master_xfer(sdvo->i2c, msgs, num); 3194 } 3195 3196 static u32 intel_sdvo_ddc_proxy_func(struct i2c_adapter *adapter) 3197 { 3198 struct intel_sdvo *sdvo = adapter->algo_data; 3199 return sdvo->i2c->algo->functionality(sdvo->i2c); 3200 } 3201 3202 static const struct i2c_algorithm intel_sdvo_ddc_proxy = { 3203 .master_xfer = intel_sdvo_ddc_proxy_xfer, 3204 .functionality = intel_sdvo_ddc_proxy_func 3205 }; 3206 3207 static void proxy_lock_bus(struct i2c_adapter *adapter, 3208 unsigned int flags) 3209 { 3210 struct intel_sdvo *sdvo = adapter->algo_data; 3211 sdvo->i2c->lock_ops->lock_bus(sdvo->i2c, flags); 3212 } 3213 3214 static int proxy_trylock_bus(struct i2c_adapter *adapter, 3215 unsigned int flags) 3216 { 3217 struct intel_sdvo *sdvo = adapter->algo_data; 3218 return sdvo->i2c->lock_ops->trylock_bus(sdvo->i2c, flags); 3219 } 3220 3221 static void proxy_unlock_bus(struct i2c_adapter *adapter, 3222 unsigned int flags) 3223 { 3224 struct intel_sdvo *sdvo = adapter->algo_data; 3225 sdvo->i2c->lock_ops->unlock_bus(sdvo->i2c, flags); 3226 } 3227 3228 static const struct i2c_lock_operations proxy_lock_ops = { 3229 .lock_bus = proxy_lock_bus, 3230 .trylock_bus = proxy_trylock_bus, 3231 .unlock_bus = proxy_unlock_bus, 3232 }; 3233 3234 static bool 3235 intel_sdvo_init_ddc_proxy(struct intel_sdvo *sdvo, 3236 struct drm_i915_private *dev_priv) 3237 { 3238 struct pci_dev *pdev = dev_priv->drm.pdev; 3239 3240 sdvo->ddc.owner = THIS_MODULE; 3241 sdvo->ddc.class = I2C_CLASS_DDC; 3242 snprintf(sdvo->ddc.name, I2C_NAME_SIZE, "SDVO DDC proxy"); 3243 sdvo->ddc.dev.parent = &pdev->dev; 3244 sdvo->ddc.algo_data = sdvo; 3245 sdvo->ddc.algo = &intel_sdvo_ddc_proxy; 3246 sdvo->ddc.lock_ops = &proxy_lock_ops; 3247 3248 return i2c_add_adapter(&sdvo->ddc) == 0; 3249 } 3250 3251 static void assert_sdvo_port_valid(const struct drm_i915_private *dev_priv, 3252 enum port port) 3253 { 3254 if (HAS_PCH_SPLIT(dev_priv)) 3255 drm_WARN_ON(&dev_priv->drm, port != PORT_B); 3256 else 3257 drm_WARN_ON(&dev_priv->drm, port != PORT_B && port != PORT_C); 3258 } 3259 3260 bool intel_sdvo_init(struct drm_i915_private *dev_priv, 3261 i915_reg_t sdvo_reg, enum port port) 3262 { 3263 struct intel_encoder *intel_encoder; 3264 struct intel_sdvo *intel_sdvo; 3265 int i; 3266 3267 assert_sdvo_port_valid(dev_priv, port); 3268 3269 intel_sdvo = kzalloc(sizeof(*intel_sdvo), GFP_KERNEL); 3270 if (!intel_sdvo) 3271 return false; 3272 3273 intel_sdvo->sdvo_reg = sdvo_reg; 3274 intel_sdvo->port = port; 3275 intel_sdvo->slave_addr = 3276 intel_sdvo_get_slave_addr(dev_priv, intel_sdvo) >> 1; 3277 intel_sdvo_select_i2c_bus(dev_priv, intel_sdvo); 3278 if (!intel_sdvo_init_ddc_proxy(intel_sdvo, dev_priv)) 3279 goto err_i2c_bus; 3280 3281 /* encoder type will be decided later */ 3282 intel_encoder = &intel_sdvo->base; 3283 intel_encoder->type = INTEL_OUTPUT_SDVO; 3284 intel_encoder->power_domain = POWER_DOMAIN_PORT_OTHER; 3285 intel_encoder->port = port; 3286 drm_encoder_init(&dev_priv->drm, &intel_encoder->base, 3287 &intel_sdvo_enc_funcs, 0, 3288 "SDVO %c", port_name(port)); 3289 3290 /* Read the regs to test if we can talk to the device */ 3291 for (i = 0; i < 0x40; i++) { 3292 u8 byte; 3293 3294 if (!intel_sdvo_read_byte(intel_sdvo, i, &byte)) { 3295 drm_dbg_kms(&dev_priv->drm, 3296 "No SDVO device found on %s\n", 3297 SDVO_NAME(intel_sdvo)); 3298 goto err; 3299 } 3300 } 3301 3302 intel_encoder->compute_config = intel_sdvo_compute_config; 3303 if (HAS_PCH_SPLIT(dev_priv)) { 3304 intel_encoder->disable = pch_disable_sdvo; 3305 intel_encoder->post_disable = pch_post_disable_sdvo; 3306 } else { 3307 intel_encoder->disable = intel_disable_sdvo; 3308 } 3309 intel_encoder->pre_enable = intel_sdvo_pre_enable; 3310 intel_encoder->enable = intel_enable_sdvo; 3311 intel_encoder->get_hw_state = intel_sdvo_get_hw_state; 3312 intel_encoder->get_config = intel_sdvo_get_config; 3313 3314 /* In default case sdvo lvds is false */ 3315 if (!intel_sdvo_get_capabilities(intel_sdvo, &intel_sdvo->caps)) 3316 goto err; 3317 3318 if (intel_sdvo_output_setup(intel_sdvo, 3319 intel_sdvo->caps.output_flags) != true) { 3320 drm_dbg_kms(&dev_priv->drm, 3321 "SDVO output failed to setup on %s\n", 3322 SDVO_NAME(intel_sdvo)); 3323 /* Output_setup can leave behind connectors! */ 3324 goto err_output; 3325 } 3326 3327 /* 3328 * Only enable the hotplug irq if we need it, to work around noisy 3329 * hotplug lines. 3330 */ 3331 if (intel_sdvo->hotplug_active) { 3332 if (intel_sdvo->port == PORT_B) 3333 intel_encoder->hpd_pin = HPD_SDVO_B; 3334 else 3335 intel_encoder->hpd_pin = HPD_SDVO_C; 3336 } 3337 3338 /* 3339 * Cloning SDVO with anything is often impossible, since the SDVO 3340 * encoder can request a special input timing mode. And even if that's 3341 * not the case we have evidence that cloning a plain unscaled mode with 3342 * VGA doesn't really work. Furthermore the cloning flags are way too 3343 * simplistic anyway to express such constraints, so just give up on 3344 * cloning for SDVO encoders. 3345 */ 3346 intel_sdvo->base.cloneable = 0; 3347 3348 intel_sdvo_select_ddc_bus(dev_priv, intel_sdvo); 3349 3350 /* Set the input timing to the screen. Assume always input 0. */ 3351 if (!intel_sdvo_set_target_input(intel_sdvo)) 3352 goto err_output; 3353 3354 if (!intel_sdvo_get_input_pixel_clock_range(intel_sdvo, 3355 &intel_sdvo->pixel_clock_min, 3356 &intel_sdvo->pixel_clock_max)) 3357 goto err_output; 3358 3359 drm_dbg_kms(&dev_priv->drm, "%s device VID/DID: %02X:%02X.%02X, " 3360 "clock range %dMHz - %dMHz, " 3361 "input 1: %c, input 2: %c, " 3362 "output 1: %c, output 2: %c\n", 3363 SDVO_NAME(intel_sdvo), 3364 intel_sdvo->caps.vendor_id, intel_sdvo->caps.device_id, 3365 intel_sdvo->caps.device_rev_id, 3366 intel_sdvo->pixel_clock_min / 1000, 3367 intel_sdvo->pixel_clock_max / 1000, 3368 (intel_sdvo->caps.sdvo_inputs_mask & 0x1) ? 'Y' : 'N', 3369 (intel_sdvo->caps.sdvo_inputs_mask & 0x2) ? 'Y' : 'N', 3370 /* check currently supported outputs */ 3371 intel_sdvo->caps.output_flags & 3372 (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_RGB0) ? 'Y' : 'N', 3373 intel_sdvo->caps.output_flags & 3374 (SDVO_OUTPUT_TMDS1 | SDVO_OUTPUT_RGB1) ? 'Y' : 'N'); 3375 return true; 3376 3377 err_output: 3378 intel_sdvo_output_cleanup(intel_sdvo); 3379 3380 err: 3381 drm_encoder_cleanup(&intel_encoder->base); 3382 i2c_del_adapter(&intel_sdvo->ddc); 3383 err_i2c_bus: 3384 intel_sdvo_unselect_i2c_bus(intel_sdvo); 3385 kfree(intel_sdvo); 3386 3387 return false; 3388 } 3389