1 /* 2 * Copyright 2006 Dave Airlie <airlied@linux.ie> 3 * Copyright © 2006-2007 Intel Corporation 4 * Jesse Barnes <jesse.barnes@intel.com> 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice (including the next 14 * paragraph) shall be included in all copies or substantial portions of the 15 * Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 23 * DEALINGS IN THE SOFTWARE. 24 * 25 * Authors: 26 * Eric Anholt <eric@anholt.net> 27 */ 28 29 #include <linux/delay.h> 30 #include <linux/export.h> 31 #include <linux/i2c.h> 32 #include <linux/slab.h> 33 34 #include <drm/display/drm_hdmi_helper.h> 35 #include <drm/drm_atomic_helper.h> 36 #include <drm/drm_crtc.h> 37 #include <drm/drm_edid.h> 38 39 #include "i915_drv.h" 40 #include "i915_reg.h" 41 #include "intel_atomic.h" 42 #include "intel_audio.h" 43 #include "intel_connector.h" 44 #include "intel_crtc.h" 45 #include "intel_de.h" 46 #include "intel_display_types.h" 47 #include "intel_fdi.h" 48 #include "intel_fifo_underrun.h" 49 #include "intel_gmbus.h" 50 #include "intel_hdmi.h" 51 #include "intel_hotplug.h" 52 #include "intel_panel.h" 53 #include "intel_sdvo.h" 54 #include "intel_sdvo_regs.h" 55 56 #define SDVO_TMDS_MASK (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_TMDS1) 57 #define SDVO_RGB_MASK (SDVO_OUTPUT_RGB0 | SDVO_OUTPUT_RGB1) 58 #define SDVO_LVDS_MASK (SDVO_OUTPUT_LVDS0 | SDVO_OUTPUT_LVDS1) 59 #define SDVO_TV_MASK (SDVO_OUTPUT_CVBS0 | SDVO_OUTPUT_SVID0 | SDVO_OUTPUT_YPRPB0) 60 61 #define SDVO_OUTPUT_MASK (SDVO_TMDS_MASK | SDVO_RGB_MASK | SDVO_LVDS_MASK | SDVO_TV_MASK) 62 63 #define IS_TV(c) ((c)->output_flag & SDVO_TV_MASK) 64 #define IS_TMDS(c) ((c)->output_flag & SDVO_TMDS_MASK) 65 #define IS_LVDS(c) ((c)->output_flag & SDVO_LVDS_MASK) 66 #define IS_TV_OR_LVDS(c) ((c)->output_flag & (SDVO_TV_MASK | SDVO_LVDS_MASK)) 67 #define IS_DIGITAL(c) ((c)->output_flag & (SDVO_TMDS_MASK | SDVO_LVDS_MASK)) 68 69 #define HAS_DDC(c) ((c)->output_flag & (SDVO_RGB_MASK | SDVO_TMDS_MASK | \ 70 SDVO_LVDS_MASK)) 71 72 static const char * const tv_format_names[] = { 73 "NTSC_M" , "NTSC_J" , "NTSC_443", 74 "PAL_B" , "PAL_D" , "PAL_G" , 75 "PAL_H" , "PAL_I" , "PAL_M" , 76 "PAL_N" , "PAL_NC" , "PAL_60" , 77 "SECAM_B" , "SECAM_D" , "SECAM_G" , 78 "SECAM_K" , "SECAM_K1", "SECAM_L" , 79 "SECAM_60" 80 }; 81 82 #define TV_FORMAT_NUM ARRAY_SIZE(tv_format_names) 83 84 struct intel_sdvo; 85 86 struct intel_sdvo_ddc { 87 struct i2c_adapter ddc; 88 struct intel_sdvo *sdvo; 89 u8 ddc_bus; 90 }; 91 92 struct intel_sdvo { 93 struct intel_encoder base; 94 95 struct i2c_adapter *i2c; 96 u8 slave_addr; 97 98 struct intel_sdvo_ddc ddc[3]; 99 100 /* Register for the SDVO device: SDVOB or SDVOC */ 101 i915_reg_t sdvo_reg; 102 103 /* 104 * Capabilities of the SDVO device returned by 105 * intel_sdvo_get_capabilities() 106 */ 107 struct intel_sdvo_caps caps; 108 109 u8 colorimetry_cap; 110 111 /* Pixel clock limitations reported by the SDVO device, in kHz */ 112 int pixel_clock_min, pixel_clock_max; 113 114 /* 115 * Hotplug activation bits for this device 116 */ 117 u16 hotplug_active; 118 119 /* 120 * the sdvo flag gets lost in round trip: dtd->adjusted_mode->dtd 121 */ 122 u8 dtd_sdvo_flags; 123 }; 124 125 struct intel_sdvo_connector { 126 struct intel_connector base; 127 128 /* Mark the type of connector */ 129 u16 output_flag; 130 131 /* This contains all current supported TV format */ 132 u8 tv_format_supported[TV_FORMAT_NUM]; 133 int format_supported_num; 134 struct drm_property *tv_format; 135 136 /* add the property for the SDVO-TV */ 137 struct drm_property *left; 138 struct drm_property *right; 139 struct drm_property *top; 140 struct drm_property *bottom; 141 struct drm_property *hpos; 142 struct drm_property *vpos; 143 struct drm_property *contrast; 144 struct drm_property *saturation; 145 struct drm_property *hue; 146 struct drm_property *sharpness; 147 struct drm_property *flicker_filter; 148 struct drm_property *flicker_filter_adaptive; 149 struct drm_property *flicker_filter_2d; 150 struct drm_property *tv_chroma_filter; 151 struct drm_property *tv_luma_filter; 152 struct drm_property *dot_crawl; 153 154 /* add the property for the SDVO-TV/LVDS */ 155 struct drm_property *brightness; 156 157 /* this is to get the range of margin.*/ 158 u32 max_hscan, max_vscan; 159 160 /** 161 * This is set if we treat the device as HDMI, instead of DVI. 162 */ 163 bool is_hdmi; 164 }; 165 166 struct intel_sdvo_connector_state { 167 /* base.base: tv.saturation/contrast/hue/brightness */ 168 struct intel_digital_connector_state base; 169 170 struct { 171 unsigned overscan_h, overscan_v, hpos, vpos, sharpness; 172 unsigned flicker_filter, flicker_filter_2d, flicker_filter_adaptive; 173 unsigned chroma_filter, luma_filter, dot_crawl; 174 } tv; 175 }; 176 177 static struct intel_sdvo *to_sdvo(struct intel_encoder *encoder) 178 { 179 return container_of(encoder, struct intel_sdvo, base); 180 } 181 182 static struct intel_sdvo *intel_attached_sdvo(struct intel_connector *connector) 183 { 184 return to_sdvo(intel_attached_encoder(connector)); 185 } 186 187 static struct intel_sdvo_connector * 188 to_intel_sdvo_connector(struct drm_connector *connector) 189 { 190 return container_of(connector, struct intel_sdvo_connector, base.base); 191 } 192 193 #define to_intel_sdvo_connector_state(conn_state) \ 194 container_of((conn_state), struct intel_sdvo_connector_state, base.base) 195 196 static bool 197 intel_sdvo_output_setup(struct intel_sdvo *intel_sdvo); 198 static bool 199 intel_sdvo_tv_create_property(struct intel_sdvo *intel_sdvo, 200 struct intel_sdvo_connector *intel_sdvo_connector, 201 int type); 202 static bool 203 intel_sdvo_create_enhance_property(struct intel_sdvo *intel_sdvo, 204 struct intel_sdvo_connector *intel_sdvo_connector); 205 206 /* 207 * Writes the SDVOB or SDVOC with the given value, but always writes both 208 * SDVOB and SDVOC to work around apparent hardware issues (according to 209 * comments in the BIOS). 210 */ 211 static void intel_sdvo_write_sdvox(struct intel_sdvo *intel_sdvo, u32 val) 212 { 213 struct drm_device *dev = intel_sdvo->base.base.dev; 214 struct drm_i915_private *dev_priv = to_i915(dev); 215 u32 bval = val, cval = val; 216 int i; 217 218 if (HAS_PCH_SPLIT(dev_priv)) { 219 intel_de_write(dev_priv, intel_sdvo->sdvo_reg, val); 220 intel_de_posting_read(dev_priv, intel_sdvo->sdvo_reg); 221 /* 222 * HW workaround, need to write this twice for issue 223 * that may result in first write getting masked. 224 */ 225 if (HAS_PCH_IBX(dev_priv)) { 226 intel_de_write(dev_priv, intel_sdvo->sdvo_reg, val); 227 intel_de_posting_read(dev_priv, intel_sdvo->sdvo_reg); 228 } 229 return; 230 } 231 232 if (intel_sdvo->base.port == PORT_B) 233 cval = intel_de_read(dev_priv, GEN3_SDVOC); 234 else 235 bval = intel_de_read(dev_priv, GEN3_SDVOB); 236 237 /* 238 * Write the registers twice for luck. Sometimes, 239 * writing them only once doesn't appear to 'stick'. 240 * The BIOS does this too. Yay, magic 241 */ 242 for (i = 0; i < 2; i++) { 243 intel_de_write(dev_priv, GEN3_SDVOB, bval); 244 intel_de_posting_read(dev_priv, GEN3_SDVOB); 245 246 intel_de_write(dev_priv, GEN3_SDVOC, cval); 247 intel_de_posting_read(dev_priv, GEN3_SDVOC); 248 } 249 } 250 251 static bool intel_sdvo_read_byte(struct intel_sdvo *intel_sdvo, u8 addr, u8 *ch) 252 { 253 struct i2c_msg msgs[] = { 254 { 255 .addr = intel_sdvo->slave_addr, 256 .flags = 0, 257 .len = 1, 258 .buf = &addr, 259 }, 260 { 261 .addr = intel_sdvo->slave_addr, 262 .flags = I2C_M_RD, 263 .len = 1, 264 .buf = ch, 265 } 266 }; 267 int ret; 268 269 if ((ret = i2c_transfer(intel_sdvo->i2c, msgs, 2)) == 2) 270 return true; 271 272 DRM_DEBUG_KMS("i2c transfer returned %d\n", ret); 273 return false; 274 } 275 276 #define SDVO_CMD_NAME_ENTRY(cmd_) { .cmd = SDVO_CMD_ ## cmd_, .name = #cmd_ } 277 278 /** Mapping of command numbers to names, for debug output */ 279 static const struct { 280 u8 cmd; 281 const char *name; 282 } __packed sdvo_cmd_names[] = { 283 SDVO_CMD_NAME_ENTRY(RESET), 284 SDVO_CMD_NAME_ENTRY(GET_DEVICE_CAPS), 285 SDVO_CMD_NAME_ENTRY(GET_FIRMWARE_REV), 286 SDVO_CMD_NAME_ENTRY(GET_TRAINED_INPUTS), 287 SDVO_CMD_NAME_ENTRY(GET_ACTIVE_OUTPUTS), 288 SDVO_CMD_NAME_ENTRY(SET_ACTIVE_OUTPUTS), 289 SDVO_CMD_NAME_ENTRY(GET_IN_OUT_MAP), 290 SDVO_CMD_NAME_ENTRY(SET_IN_OUT_MAP), 291 SDVO_CMD_NAME_ENTRY(GET_ATTACHED_DISPLAYS), 292 SDVO_CMD_NAME_ENTRY(GET_HOT_PLUG_SUPPORT), 293 SDVO_CMD_NAME_ENTRY(SET_ACTIVE_HOT_PLUG), 294 SDVO_CMD_NAME_ENTRY(GET_ACTIVE_HOT_PLUG), 295 SDVO_CMD_NAME_ENTRY(GET_INTERRUPT_EVENT_SOURCE), 296 SDVO_CMD_NAME_ENTRY(SET_TARGET_INPUT), 297 SDVO_CMD_NAME_ENTRY(SET_TARGET_OUTPUT), 298 SDVO_CMD_NAME_ENTRY(GET_INPUT_TIMINGS_PART1), 299 SDVO_CMD_NAME_ENTRY(GET_INPUT_TIMINGS_PART2), 300 SDVO_CMD_NAME_ENTRY(SET_INPUT_TIMINGS_PART1), 301 SDVO_CMD_NAME_ENTRY(SET_INPUT_TIMINGS_PART2), 302 SDVO_CMD_NAME_ENTRY(SET_OUTPUT_TIMINGS_PART1), 303 SDVO_CMD_NAME_ENTRY(SET_OUTPUT_TIMINGS_PART2), 304 SDVO_CMD_NAME_ENTRY(GET_OUTPUT_TIMINGS_PART1), 305 SDVO_CMD_NAME_ENTRY(GET_OUTPUT_TIMINGS_PART2), 306 SDVO_CMD_NAME_ENTRY(CREATE_PREFERRED_INPUT_TIMING), 307 SDVO_CMD_NAME_ENTRY(GET_PREFERRED_INPUT_TIMING_PART1), 308 SDVO_CMD_NAME_ENTRY(GET_PREFERRED_INPUT_TIMING_PART2), 309 SDVO_CMD_NAME_ENTRY(GET_INPUT_PIXEL_CLOCK_RANGE), 310 SDVO_CMD_NAME_ENTRY(GET_OUTPUT_PIXEL_CLOCK_RANGE), 311 SDVO_CMD_NAME_ENTRY(GET_SUPPORTED_CLOCK_RATE_MULTS), 312 SDVO_CMD_NAME_ENTRY(GET_CLOCK_RATE_MULT), 313 SDVO_CMD_NAME_ENTRY(SET_CLOCK_RATE_MULT), 314 SDVO_CMD_NAME_ENTRY(GET_SUPPORTED_TV_FORMATS), 315 SDVO_CMD_NAME_ENTRY(GET_TV_FORMAT), 316 SDVO_CMD_NAME_ENTRY(SET_TV_FORMAT), 317 SDVO_CMD_NAME_ENTRY(GET_SUPPORTED_POWER_STATES), 318 SDVO_CMD_NAME_ENTRY(GET_POWER_STATE), 319 SDVO_CMD_NAME_ENTRY(SET_ENCODER_POWER_STATE), 320 SDVO_CMD_NAME_ENTRY(SET_DISPLAY_POWER_STATE), 321 SDVO_CMD_NAME_ENTRY(SET_CONTROL_BUS_SWITCH), 322 SDVO_CMD_NAME_ENTRY(GET_SDTV_RESOLUTION_SUPPORT), 323 SDVO_CMD_NAME_ENTRY(GET_SCALED_HDTV_RESOLUTION_SUPPORT), 324 SDVO_CMD_NAME_ENTRY(GET_SUPPORTED_ENHANCEMENTS), 325 326 /* Add the op code for SDVO enhancements */ 327 SDVO_CMD_NAME_ENTRY(GET_MAX_HPOS), 328 SDVO_CMD_NAME_ENTRY(GET_HPOS), 329 SDVO_CMD_NAME_ENTRY(SET_HPOS), 330 SDVO_CMD_NAME_ENTRY(GET_MAX_VPOS), 331 SDVO_CMD_NAME_ENTRY(GET_VPOS), 332 SDVO_CMD_NAME_ENTRY(SET_VPOS), 333 SDVO_CMD_NAME_ENTRY(GET_MAX_SATURATION), 334 SDVO_CMD_NAME_ENTRY(GET_SATURATION), 335 SDVO_CMD_NAME_ENTRY(SET_SATURATION), 336 SDVO_CMD_NAME_ENTRY(GET_MAX_HUE), 337 SDVO_CMD_NAME_ENTRY(GET_HUE), 338 SDVO_CMD_NAME_ENTRY(SET_HUE), 339 SDVO_CMD_NAME_ENTRY(GET_MAX_CONTRAST), 340 SDVO_CMD_NAME_ENTRY(GET_CONTRAST), 341 SDVO_CMD_NAME_ENTRY(SET_CONTRAST), 342 SDVO_CMD_NAME_ENTRY(GET_MAX_BRIGHTNESS), 343 SDVO_CMD_NAME_ENTRY(GET_BRIGHTNESS), 344 SDVO_CMD_NAME_ENTRY(SET_BRIGHTNESS), 345 SDVO_CMD_NAME_ENTRY(GET_MAX_OVERSCAN_H), 346 SDVO_CMD_NAME_ENTRY(GET_OVERSCAN_H), 347 SDVO_CMD_NAME_ENTRY(SET_OVERSCAN_H), 348 SDVO_CMD_NAME_ENTRY(GET_MAX_OVERSCAN_V), 349 SDVO_CMD_NAME_ENTRY(GET_OVERSCAN_V), 350 SDVO_CMD_NAME_ENTRY(SET_OVERSCAN_V), 351 SDVO_CMD_NAME_ENTRY(GET_MAX_FLICKER_FILTER), 352 SDVO_CMD_NAME_ENTRY(GET_FLICKER_FILTER), 353 SDVO_CMD_NAME_ENTRY(SET_FLICKER_FILTER), 354 SDVO_CMD_NAME_ENTRY(GET_MAX_FLICKER_FILTER_ADAPTIVE), 355 SDVO_CMD_NAME_ENTRY(GET_FLICKER_FILTER_ADAPTIVE), 356 SDVO_CMD_NAME_ENTRY(SET_FLICKER_FILTER_ADAPTIVE), 357 SDVO_CMD_NAME_ENTRY(GET_MAX_FLICKER_FILTER_2D), 358 SDVO_CMD_NAME_ENTRY(GET_FLICKER_FILTER_2D), 359 SDVO_CMD_NAME_ENTRY(SET_FLICKER_FILTER_2D), 360 SDVO_CMD_NAME_ENTRY(GET_MAX_SHARPNESS), 361 SDVO_CMD_NAME_ENTRY(GET_SHARPNESS), 362 SDVO_CMD_NAME_ENTRY(SET_SHARPNESS), 363 SDVO_CMD_NAME_ENTRY(GET_DOT_CRAWL), 364 SDVO_CMD_NAME_ENTRY(SET_DOT_CRAWL), 365 SDVO_CMD_NAME_ENTRY(GET_MAX_TV_CHROMA_FILTER), 366 SDVO_CMD_NAME_ENTRY(GET_TV_CHROMA_FILTER), 367 SDVO_CMD_NAME_ENTRY(SET_TV_CHROMA_FILTER), 368 SDVO_CMD_NAME_ENTRY(GET_MAX_TV_LUMA_FILTER), 369 SDVO_CMD_NAME_ENTRY(GET_TV_LUMA_FILTER), 370 SDVO_CMD_NAME_ENTRY(SET_TV_LUMA_FILTER), 371 372 /* HDMI op code */ 373 SDVO_CMD_NAME_ENTRY(GET_SUPP_ENCODE), 374 SDVO_CMD_NAME_ENTRY(GET_ENCODE), 375 SDVO_CMD_NAME_ENTRY(SET_ENCODE), 376 SDVO_CMD_NAME_ENTRY(SET_PIXEL_REPLI), 377 SDVO_CMD_NAME_ENTRY(GET_PIXEL_REPLI), 378 SDVO_CMD_NAME_ENTRY(GET_COLORIMETRY_CAP), 379 SDVO_CMD_NAME_ENTRY(SET_COLORIMETRY), 380 SDVO_CMD_NAME_ENTRY(GET_COLORIMETRY), 381 SDVO_CMD_NAME_ENTRY(GET_AUDIO_ENCRYPT_PREFER), 382 SDVO_CMD_NAME_ENTRY(SET_AUDIO_STAT), 383 SDVO_CMD_NAME_ENTRY(GET_AUDIO_STAT), 384 SDVO_CMD_NAME_ENTRY(GET_HBUF_INDEX), 385 SDVO_CMD_NAME_ENTRY(SET_HBUF_INDEX), 386 SDVO_CMD_NAME_ENTRY(GET_HBUF_INFO), 387 SDVO_CMD_NAME_ENTRY(GET_HBUF_AV_SPLIT), 388 SDVO_CMD_NAME_ENTRY(SET_HBUF_AV_SPLIT), 389 SDVO_CMD_NAME_ENTRY(GET_HBUF_TXRATE), 390 SDVO_CMD_NAME_ENTRY(SET_HBUF_TXRATE), 391 SDVO_CMD_NAME_ENTRY(SET_HBUF_DATA), 392 SDVO_CMD_NAME_ENTRY(GET_HBUF_DATA), 393 }; 394 395 #undef SDVO_CMD_NAME_ENTRY 396 397 static const char *sdvo_cmd_name(u8 cmd) 398 { 399 int i; 400 401 for (i = 0; i < ARRAY_SIZE(sdvo_cmd_names); i++) { 402 if (cmd == sdvo_cmd_names[i].cmd) 403 return sdvo_cmd_names[i].name; 404 } 405 406 return NULL; 407 } 408 409 #define SDVO_NAME(svdo) ((svdo)->base.port == PORT_B ? "SDVOB" : "SDVOC") 410 411 static void intel_sdvo_debug_write(struct intel_sdvo *intel_sdvo, u8 cmd, 412 const void *args, int args_len) 413 { 414 struct drm_i915_private *dev_priv = to_i915(intel_sdvo->base.base.dev); 415 const char *cmd_name; 416 int i, pos = 0; 417 char buffer[64]; 418 419 #define BUF_PRINT(args...) \ 420 pos += snprintf(buffer + pos, max_t(int, sizeof(buffer) - pos, 0), args) 421 422 for (i = 0; i < args_len; i++) { 423 BUF_PRINT("%02X ", ((u8 *)args)[i]); 424 } 425 for (; i < 8; i++) { 426 BUF_PRINT(" "); 427 } 428 429 cmd_name = sdvo_cmd_name(cmd); 430 if (cmd_name) 431 BUF_PRINT("(%s)", cmd_name); 432 else 433 BUF_PRINT("(%02X)", cmd); 434 435 drm_WARN_ON(&dev_priv->drm, pos >= sizeof(buffer) - 1); 436 #undef BUF_PRINT 437 438 DRM_DEBUG_KMS("%s: W: %02X %s\n", SDVO_NAME(intel_sdvo), cmd, buffer); 439 } 440 441 static const char * const cmd_status_names[] = { 442 [SDVO_CMD_STATUS_POWER_ON] = "Power on", 443 [SDVO_CMD_STATUS_SUCCESS] = "Success", 444 [SDVO_CMD_STATUS_NOTSUPP] = "Not supported", 445 [SDVO_CMD_STATUS_INVALID_ARG] = "Invalid arg", 446 [SDVO_CMD_STATUS_PENDING] = "Pending", 447 [SDVO_CMD_STATUS_TARGET_NOT_SPECIFIED] = "Target not specified", 448 [SDVO_CMD_STATUS_SCALING_NOT_SUPP] = "Scaling not supported", 449 }; 450 451 static const char *sdvo_cmd_status(u8 status) 452 { 453 if (status < ARRAY_SIZE(cmd_status_names)) 454 return cmd_status_names[status]; 455 else 456 return NULL; 457 } 458 459 static bool __intel_sdvo_write_cmd(struct intel_sdvo *intel_sdvo, u8 cmd, 460 const void *args, int args_len, 461 bool unlocked) 462 { 463 u8 *buf, status; 464 struct i2c_msg *msgs; 465 int i, ret = true; 466 467 /* Would be simpler to allocate both in one go ? */ 468 buf = kzalloc(args_len * 2 + 2, GFP_KERNEL); 469 if (!buf) 470 return false; 471 472 msgs = kcalloc(args_len + 3, sizeof(*msgs), GFP_KERNEL); 473 if (!msgs) { 474 kfree(buf); 475 return false; 476 } 477 478 intel_sdvo_debug_write(intel_sdvo, cmd, args, args_len); 479 480 for (i = 0; i < args_len; i++) { 481 msgs[i].addr = intel_sdvo->slave_addr; 482 msgs[i].flags = 0; 483 msgs[i].len = 2; 484 msgs[i].buf = buf + 2 *i; 485 buf[2*i + 0] = SDVO_I2C_ARG_0 - i; 486 buf[2*i + 1] = ((u8*)args)[i]; 487 } 488 msgs[i].addr = intel_sdvo->slave_addr; 489 msgs[i].flags = 0; 490 msgs[i].len = 2; 491 msgs[i].buf = buf + 2*i; 492 buf[2*i + 0] = SDVO_I2C_OPCODE; 493 buf[2*i + 1] = cmd; 494 495 /* the following two are to read the response */ 496 status = SDVO_I2C_CMD_STATUS; 497 msgs[i+1].addr = intel_sdvo->slave_addr; 498 msgs[i+1].flags = 0; 499 msgs[i+1].len = 1; 500 msgs[i+1].buf = &status; 501 502 msgs[i+2].addr = intel_sdvo->slave_addr; 503 msgs[i+2].flags = I2C_M_RD; 504 msgs[i+2].len = 1; 505 msgs[i+2].buf = &status; 506 507 if (unlocked) 508 ret = i2c_transfer(intel_sdvo->i2c, msgs, i+3); 509 else 510 ret = __i2c_transfer(intel_sdvo->i2c, msgs, i+3); 511 if (ret < 0) { 512 DRM_DEBUG_KMS("I2c transfer returned %d\n", ret); 513 ret = false; 514 goto out; 515 } 516 if (ret != i+3) { 517 /* failure in I2C transfer */ 518 DRM_DEBUG_KMS("I2c transfer returned %d/%d\n", ret, i+3); 519 ret = false; 520 } 521 522 out: 523 kfree(msgs); 524 kfree(buf); 525 return ret; 526 } 527 528 static bool intel_sdvo_write_cmd(struct intel_sdvo *intel_sdvo, u8 cmd, 529 const void *args, int args_len) 530 { 531 return __intel_sdvo_write_cmd(intel_sdvo, cmd, args, args_len, true); 532 } 533 534 static bool intel_sdvo_read_response(struct intel_sdvo *intel_sdvo, 535 void *response, int response_len) 536 { 537 struct drm_i915_private *dev_priv = to_i915(intel_sdvo->base.base.dev); 538 const char *cmd_status; 539 u8 retry = 15; /* 5 quick checks, followed by 10 long checks */ 540 u8 status; 541 int i, pos = 0; 542 char buffer[64]; 543 544 buffer[0] = '\0'; 545 546 /* 547 * The documentation states that all commands will be 548 * processed within 15µs, and that we need only poll 549 * the status byte a maximum of 3 times in order for the 550 * command to be complete. 551 * 552 * Check 5 times in case the hardware failed to read the docs. 553 * 554 * Also beware that the first response by many devices is to 555 * reply PENDING and stall for time. TVs are notorious for 556 * requiring longer than specified to complete their replies. 557 * Originally (in the DDX long ago), the delay was only ever 15ms 558 * with an additional delay of 30ms applied for TVs added later after 559 * many experiments. To accommodate both sets of delays, we do a 560 * sequence of slow checks if the device is falling behind and fails 561 * to reply within 5*15µs. 562 */ 563 if (!intel_sdvo_read_byte(intel_sdvo, 564 SDVO_I2C_CMD_STATUS, 565 &status)) 566 goto log_fail; 567 568 while ((status == SDVO_CMD_STATUS_PENDING || 569 status == SDVO_CMD_STATUS_TARGET_NOT_SPECIFIED) && --retry) { 570 if (retry < 10) 571 msleep(15); 572 else 573 udelay(15); 574 575 if (!intel_sdvo_read_byte(intel_sdvo, 576 SDVO_I2C_CMD_STATUS, 577 &status)) 578 goto log_fail; 579 } 580 581 #define BUF_PRINT(args...) \ 582 pos += snprintf(buffer + pos, max_t(int, sizeof(buffer) - pos, 0), args) 583 584 cmd_status = sdvo_cmd_status(status); 585 if (cmd_status) 586 BUF_PRINT("(%s)", cmd_status); 587 else 588 BUF_PRINT("(??? %d)", status); 589 590 if (status != SDVO_CMD_STATUS_SUCCESS) 591 goto log_fail; 592 593 /* Read the command response */ 594 for (i = 0; i < response_len; i++) { 595 if (!intel_sdvo_read_byte(intel_sdvo, 596 SDVO_I2C_RETURN_0 + i, 597 &((u8 *)response)[i])) 598 goto log_fail; 599 BUF_PRINT(" %02X", ((u8 *)response)[i]); 600 } 601 602 drm_WARN_ON(&dev_priv->drm, pos >= sizeof(buffer) - 1); 603 #undef BUF_PRINT 604 605 DRM_DEBUG_KMS("%s: R: %s\n", SDVO_NAME(intel_sdvo), buffer); 606 return true; 607 608 log_fail: 609 DRM_DEBUG_KMS("%s: R: ... failed %s\n", 610 SDVO_NAME(intel_sdvo), buffer); 611 return false; 612 } 613 614 static int intel_sdvo_get_pixel_multiplier(const struct drm_display_mode *adjusted_mode) 615 { 616 if (adjusted_mode->crtc_clock >= 100000) 617 return 1; 618 else if (adjusted_mode->crtc_clock >= 50000) 619 return 2; 620 else 621 return 4; 622 } 623 624 static bool __intel_sdvo_set_control_bus_switch(struct intel_sdvo *intel_sdvo, 625 u8 ddc_bus) 626 { 627 /* This must be the immediately preceding write before the i2c xfer */ 628 return __intel_sdvo_write_cmd(intel_sdvo, 629 SDVO_CMD_SET_CONTROL_BUS_SWITCH, 630 &ddc_bus, 1, false); 631 } 632 633 static bool intel_sdvo_set_value(struct intel_sdvo *intel_sdvo, u8 cmd, const void *data, int len) 634 { 635 if (!intel_sdvo_write_cmd(intel_sdvo, cmd, data, len)) 636 return false; 637 638 return intel_sdvo_read_response(intel_sdvo, NULL, 0); 639 } 640 641 static bool 642 intel_sdvo_get_value(struct intel_sdvo *intel_sdvo, u8 cmd, void *value, int len) 643 { 644 if (!intel_sdvo_write_cmd(intel_sdvo, cmd, NULL, 0)) 645 return false; 646 647 return intel_sdvo_read_response(intel_sdvo, value, len); 648 } 649 650 static bool intel_sdvo_set_target_input(struct intel_sdvo *intel_sdvo) 651 { 652 struct intel_sdvo_set_target_input_args targets = {}; 653 return intel_sdvo_set_value(intel_sdvo, 654 SDVO_CMD_SET_TARGET_INPUT, 655 &targets, sizeof(targets)); 656 } 657 658 /* 659 * Return whether each input is trained. 660 * 661 * This function is making an assumption about the layout of the response, 662 * which should be checked against the docs. 663 */ 664 static bool intel_sdvo_get_trained_inputs(struct intel_sdvo *intel_sdvo, bool *input_1, bool *input_2) 665 { 666 struct intel_sdvo_get_trained_inputs_response response; 667 668 BUILD_BUG_ON(sizeof(response) != 1); 669 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_TRAINED_INPUTS, 670 &response, sizeof(response))) 671 return false; 672 673 *input_1 = response.input0_trained; 674 *input_2 = response.input1_trained; 675 return true; 676 } 677 678 static bool intel_sdvo_set_active_outputs(struct intel_sdvo *intel_sdvo, 679 u16 outputs) 680 { 681 return intel_sdvo_set_value(intel_sdvo, 682 SDVO_CMD_SET_ACTIVE_OUTPUTS, 683 &outputs, sizeof(outputs)); 684 } 685 686 static bool intel_sdvo_get_active_outputs(struct intel_sdvo *intel_sdvo, 687 u16 *outputs) 688 { 689 return intel_sdvo_get_value(intel_sdvo, 690 SDVO_CMD_GET_ACTIVE_OUTPUTS, 691 outputs, sizeof(*outputs)); 692 } 693 694 static bool intel_sdvo_set_encoder_power_state(struct intel_sdvo *intel_sdvo, 695 int mode) 696 { 697 u8 state = SDVO_ENCODER_STATE_ON; 698 699 switch (mode) { 700 case DRM_MODE_DPMS_ON: 701 state = SDVO_ENCODER_STATE_ON; 702 break; 703 case DRM_MODE_DPMS_STANDBY: 704 state = SDVO_ENCODER_STATE_STANDBY; 705 break; 706 case DRM_MODE_DPMS_SUSPEND: 707 state = SDVO_ENCODER_STATE_SUSPEND; 708 break; 709 case DRM_MODE_DPMS_OFF: 710 state = SDVO_ENCODER_STATE_OFF; 711 break; 712 } 713 714 return intel_sdvo_set_value(intel_sdvo, 715 SDVO_CMD_SET_ENCODER_POWER_STATE, &state, sizeof(state)); 716 } 717 718 static bool intel_sdvo_get_input_pixel_clock_range(struct intel_sdvo *intel_sdvo, 719 int *clock_min, 720 int *clock_max) 721 { 722 struct intel_sdvo_pixel_clock_range clocks; 723 724 BUILD_BUG_ON(sizeof(clocks) != 4); 725 if (!intel_sdvo_get_value(intel_sdvo, 726 SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE, 727 &clocks, sizeof(clocks))) 728 return false; 729 730 /* Convert the values from units of 10 kHz to kHz. */ 731 *clock_min = clocks.min * 10; 732 *clock_max = clocks.max * 10; 733 return true; 734 } 735 736 static bool intel_sdvo_set_target_output(struct intel_sdvo *intel_sdvo, 737 u16 outputs) 738 { 739 return intel_sdvo_set_value(intel_sdvo, 740 SDVO_CMD_SET_TARGET_OUTPUT, 741 &outputs, sizeof(outputs)); 742 } 743 744 static bool intel_sdvo_set_timing(struct intel_sdvo *intel_sdvo, u8 cmd, 745 struct intel_sdvo_dtd *dtd) 746 { 747 return intel_sdvo_set_value(intel_sdvo, cmd, &dtd->part1, sizeof(dtd->part1)) && 748 intel_sdvo_set_value(intel_sdvo, cmd + 1, &dtd->part2, sizeof(dtd->part2)); 749 } 750 751 static bool intel_sdvo_get_timing(struct intel_sdvo *intel_sdvo, u8 cmd, 752 struct intel_sdvo_dtd *dtd) 753 { 754 return intel_sdvo_get_value(intel_sdvo, cmd, &dtd->part1, sizeof(dtd->part1)) && 755 intel_sdvo_get_value(intel_sdvo, cmd + 1, &dtd->part2, sizeof(dtd->part2)); 756 } 757 758 static bool intel_sdvo_set_input_timing(struct intel_sdvo *intel_sdvo, 759 struct intel_sdvo_dtd *dtd) 760 { 761 return intel_sdvo_set_timing(intel_sdvo, 762 SDVO_CMD_SET_INPUT_TIMINGS_PART1, dtd); 763 } 764 765 static bool intel_sdvo_set_output_timing(struct intel_sdvo *intel_sdvo, 766 struct intel_sdvo_dtd *dtd) 767 { 768 return intel_sdvo_set_timing(intel_sdvo, 769 SDVO_CMD_SET_OUTPUT_TIMINGS_PART1, dtd); 770 } 771 772 static bool intel_sdvo_get_input_timing(struct intel_sdvo *intel_sdvo, 773 struct intel_sdvo_dtd *dtd) 774 { 775 return intel_sdvo_get_timing(intel_sdvo, 776 SDVO_CMD_GET_INPUT_TIMINGS_PART1, dtd); 777 } 778 779 static bool 780 intel_sdvo_create_preferred_input_timing(struct intel_sdvo *intel_sdvo, 781 struct intel_sdvo_connector *intel_sdvo_connector, 782 const struct drm_display_mode *mode) 783 { 784 struct intel_sdvo_preferred_input_timing_args args; 785 786 memset(&args, 0, sizeof(args)); 787 args.clock = mode->clock / 10; 788 args.width = mode->hdisplay; 789 args.height = mode->vdisplay; 790 args.interlace = 0; 791 792 if (IS_LVDS(intel_sdvo_connector)) { 793 const struct drm_display_mode *fixed_mode = 794 intel_panel_fixed_mode(&intel_sdvo_connector->base, mode); 795 796 if (fixed_mode->hdisplay != args.width || 797 fixed_mode->vdisplay != args.height) 798 args.scaled = 1; 799 } 800 801 return intel_sdvo_set_value(intel_sdvo, 802 SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING, 803 &args, sizeof(args)); 804 } 805 806 static bool intel_sdvo_get_preferred_input_timing(struct intel_sdvo *intel_sdvo, 807 struct intel_sdvo_dtd *dtd) 808 { 809 BUILD_BUG_ON(sizeof(dtd->part1) != 8); 810 BUILD_BUG_ON(sizeof(dtd->part2) != 8); 811 return intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1, 812 &dtd->part1, sizeof(dtd->part1)) && 813 intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2, 814 &dtd->part2, sizeof(dtd->part2)); 815 } 816 817 static bool intel_sdvo_set_clock_rate_mult(struct intel_sdvo *intel_sdvo, u8 val) 818 { 819 return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_CLOCK_RATE_MULT, &val, 1); 820 } 821 822 static void intel_sdvo_get_dtd_from_mode(struct intel_sdvo_dtd *dtd, 823 const struct drm_display_mode *mode) 824 { 825 u16 width, height; 826 u16 h_blank_len, h_sync_len, v_blank_len, v_sync_len; 827 u16 h_sync_offset, v_sync_offset; 828 int mode_clock; 829 830 memset(dtd, 0, sizeof(*dtd)); 831 832 width = mode->hdisplay; 833 height = mode->vdisplay; 834 835 /* do some mode translations */ 836 h_blank_len = mode->htotal - mode->hdisplay; 837 h_sync_len = mode->hsync_end - mode->hsync_start; 838 839 v_blank_len = mode->vtotal - mode->vdisplay; 840 v_sync_len = mode->vsync_end - mode->vsync_start; 841 842 h_sync_offset = mode->hsync_start - mode->hdisplay; 843 v_sync_offset = mode->vsync_start - mode->vdisplay; 844 845 mode_clock = mode->clock; 846 mode_clock /= 10; 847 dtd->part1.clock = mode_clock; 848 849 dtd->part1.h_active = width & 0xff; 850 dtd->part1.h_blank = h_blank_len & 0xff; 851 dtd->part1.h_high = (((width >> 8) & 0xf) << 4) | 852 ((h_blank_len >> 8) & 0xf); 853 dtd->part1.v_active = height & 0xff; 854 dtd->part1.v_blank = v_blank_len & 0xff; 855 dtd->part1.v_high = (((height >> 8) & 0xf) << 4) | 856 ((v_blank_len >> 8) & 0xf); 857 858 dtd->part2.h_sync_off = h_sync_offset & 0xff; 859 dtd->part2.h_sync_width = h_sync_len & 0xff; 860 dtd->part2.v_sync_off_width = (v_sync_offset & 0xf) << 4 | 861 (v_sync_len & 0xf); 862 dtd->part2.sync_off_width_high = ((h_sync_offset & 0x300) >> 2) | 863 ((h_sync_len & 0x300) >> 4) | ((v_sync_offset & 0x30) >> 2) | 864 ((v_sync_len & 0x30) >> 4); 865 866 dtd->part2.dtd_flags = 0x18; 867 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 868 dtd->part2.dtd_flags |= DTD_FLAG_INTERLACE; 869 if (mode->flags & DRM_MODE_FLAG_PHSYNC) 870 dtd->part2.dtd_flags |= DTD_FLAG_HSYNC_POSITIVE; 871 if (mode->flags & DRM_MODE_FLAG_PVSYNC) 872 dtd->part2.dtd_flags |= DTD_FLAG_VSYNC_POSITIVE; 873 874 dtd->part2.v_sync_off_high = v_sync_offset & 0xc0; 875 } 876 877 static void intel_sdvo_get_mode_from_dtd(struct drm_display_mode *pmode, 878 const struct intel_sdvo_dtd *dtd) 879 { 880 struct drm_display_mode mode = {}; 881 882 mode.hdisplay = dtd->part1.h_active; 883 mode.hdisplay += ((dtd->part1.h_high >> 4) & 0x0f) << 8; 884 mode.hsync_start = mode.hdisplay + dtd->part2.h_sync_off; 885 mode.hsync_start += (dtd->part2.sync_off_width_high & 0xc0) << 2; 886 mode.hsync_end = mode.hsync_start + dtd->part2.h_sync_width; 887 mode.hsync_end += (dtd->part2.sync_off_width_high & 0x30) << 4; 888 mode.htotal = mode.hdisplay + dtd->part1.h_blank; 889 mode.htotal += (dtd->part1.h_high & 0xf) << 8; 890 891 mode.vdisplay = dtd->part1.v_active; 892 mode.vdisplay += ((dtd->part1.v_high >> 4) & 0x0f) << 8; 893 mode.vsync_start = mode.vdisplay; 894 mode.vsync_start += (dtd->part2.v_sync_off_width >> 4) & 0xf; 895 mode.vsync_start += (dtd->part2.sync_off_width_high & 0x0c) << 2; 896 mode.vsync_start += dtd->part2.v_sync_off_high & 0xc0; 897 mode.vsync_end = mode.vsync_start + 898 (dtd->part2.v_sync_off_width & 0xf); 899 mode.vsync_end += (dtd->part2.sync_off_width_high & 0x3) << 4; 900 mode.vtotal = mode.vdisplay + dtd->part1.v_blank; 901 mode.vtotal += (dtd->part1.v_high & 0xf) << 8; 902 903 mode.clock = dtd->part1.clock * 10; 904 905 if (dtd->part2.dtd_flags & DTD_FLAG_INTERLACE) 906 mode.flags |= DRM_MODE_FLAG_INTERLACE; 907 if (dtd->part2.dtd_flags & DTD_FLAG_HSYNC_POSITIVE) 908 mode.flags |= DRM_MODE_FLAG_PHSYNC; 909 else 910 mode.flags |= DRM_MODE_FLAG_NHSYNC; 911 if (dtd->part2.dtd_flags & DTD_FLAG_VSYNC_POSITIVE) 912 mode.flags |= DRM_MODE_FLAG_PVSYNC; 913 else 914 mode.flags |= DRM_MODE_FLAG_NVSYNC; 915 916 drm_mode_set_crtcinfo(&mode, 0); 917 918 drm_mode_copy(pmode, &mode); 919 } 920 921 static bool intel_sdvo_check_supp_encode(struct intel_sdvo *intel_sdvo) 922 { 923 struct intel_sdvo_encode encode; 924 925 BUILD_BUG_ON(sizeof(encode) != 2); 926 return intel_sdvo_get_value(intel_sdvo, 927 SDVO_CMD_GET_SUPP_ENCODE, 928 &encode, sizeof(encode)); 929 } 930 931 static bool intel_sdvo_set_encode(struct intel_sdvo *intel_sdvo, 932 u8 mode) 933 { 934 return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_ENCODE, &mode, 1); 935 } 936 937 static bool intel_sdvo_set_colorimetry(struct intel_sdvo *intel_sdvo, 938 u8 mode) 939 { 940 return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_COLORIMETRY, &mode, 1); 941 } 942 943 static bool intel_sdvo_set_pixel_replication(struct intel_sdvo *intel_sdvo, 944 u8 pixel_repeat) 945 { 946 return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_PIXEL_REPLI, 947 &pixel_repeat, 1); 948 } 949 950 static bool intel_sdvo_set_audio_state(struct intel_sdvo *intel_sdvo, 951 u8 audio_state) 952 { 953 return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_AUDIO_STAT, 954 &audio_state, 1); 955 } 956 957 static bool intel_sdvo_get_hbuf_size(struct intel_sdvo *intel_sdvo, 958 u8 *hbuf_size) 959 { 960 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_HBUF_INFO, 961 hbuf_size, 1)) 962 return false; 963 964 /* Buffer size is 0 based, hooray! However zero means zero. */ 965 if (*hbuf_size) 966 (*hbuf_size)++; 967 968 return true; 969 } 970 971 #if 0 972 static void intel_sdvo_dump_hdmi_buf(struct intel_sdvo *intel_sdvo) 973 { 974 int i, j; 975 u8 set_buf_index[2]; 976 u8 av_split; 977 u8 buf_size; 978 u8 buf[48]; 979 u8 *pos; 980 981 intel_sdvo_get_value(encoder, SDVO_CMD_GET_HBUF_AV_SPLIT, &av_split, 1); 982 983 for (i = 0; i <= av_split; i++) { 984 set_buf_index[0] = i; set_buf_index[1] = 0; 985 intel_sdvo_write_cmd(encoder, SDVO_CMD_SET_HBUF_INDEX, 986 set_buf_index, 2); 987 intel_sdvo_write_cmd(encoder, SDVO_CMD_GET_HBUF_INFO, NULL, 0); 988 intel_sdvo_read_response(encoder, &buf_size, 1); 989 990 pos = buf; 991 for (j = 0; j <= buf_size; j += 8) { 992 intel_sdvo_write_cmd(encoder, SDVO_CMD_GET_HBUF_DATA, 993 NULL, 0); 994 intel_sdvo_read_response(encoder, pos, 8); 995 pos += 8; 996 } 997 } 998 } 999 #endif 1000 1001 static bool intel_sdvo_write_infoframe(struct intel_sdvo *intel_sdvo, 1002 unsigned int if_index, u8 tx_rate, 1003 const u8 *data, unsigned int length) 1004 { 1005 u8 set_buf_index[2] = { if_index, 0 }; 1006 u8 hbuf_size, tmp[8]; 1007 int i; 1008 1009 if (!intel_sdvo_set_value(intel_sdvo, 1010 SDVO_CMD_SET_HBUF_INDEX, 1011 set_buf_index, 2)) 1012 return false; 1013 1014 if (!intel_sdvo_get_hbuf_size(intel_sdvo, &hbuf_size)) 1015 return false; 1016 1017 DRM_DEBUG_KMS("writing sdvo hbuf: %i, length %u, hbuf_size: %i\n", 1018 if_index, length, hbuf_size); 1019 1020 if (hbuf_size < length) 1021 return false; 1022 1023 for (i = 0; i < hbuf_size; i += 8) { 1024 memset(tmp, 0, 8); 1025 if (i < length) 1026 memcpy(tmp, data + i, min_t(unsigned, 8, length - i)); 1027 1028 if (!intel_sdvo_set_value(intel_sdvo, 1029 SDVO_CMD_SET_HBUF_DATA, 1030 tmp, 8)) 1031 return false; 1032 } 1033 1034 return intel_sdvo_set_value(intel_sdvo, 1035 SDVO_CMD_SET_HBUF_TXRATE, 1036 &tx_rate, 1); 1037 } 1038 1039 static ssize_t intel_sdvo_read_infoframe(struct intel_sdvo *intel_sdvo, 1040 unsigned int if_index, 1041 u8 *data, unsigned int length) 1042 { 1043 u8 set_buf_index[2] = { if_index, 0 }; 1044 u8 hbuf_size, tx_rate, av_split; 1045 int i; 1046 1047 if (!intel_sdvo_get_value(intel_sdvo, 1048 SDVO_CMD_GET_HBUF_AV_SPLIT, 1049 &av_split, 1)) 1050 return -ENXIO; 1051 1052 if (av_split < if_index) 1053 return 0; 1054 1055 if (!intel_sdvo_set_value(intel_sdvo, 1056 SDVO_CMD_SET_HBUF_INDEX, 1057 set_buf_index, 2)) 1058 return -ENXIO; 1059 1060 if (!intel_sdvo_get_value(intel_sdvo, 1061 SDVO_CMD_GET_HBUF_TXRATE, 1062 &tx_rate, 1)) 1063 return -ENXIO; 1064 1065 /* TX_DISABLED doesn't mean disabled for ELD */ 1066 if (if_index != SDVO_HBUF_INDEX_ELD && tx_rate == SDVO_HBUF_TX_DISABLED) 1067 return 0; 1068 1069 if (!intel_sdvo_get_hbuf_size(intel_sdvo, &hbuf_size)) 1070 return false; 1071 1072 DRM_DEBUG_KMS("reading sdvo hbuf: %i, length %u, hbuf_size: %i\n", 1073 if_index, length, hbuf_size); 1074 1075 hbuf_size = min_t(unsigned int, length, hbuf_size); 1076 1077 for (i = 0; i < hbuf_size; i += 8) { 1078 if (!intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_GET_HBUF_DATA, NULL, 0)) 1079 return -ENXIO; 1080 if (!intel_sdvo_read_response(intel_sdvo, &data[i], 1081 min_t(unsigned int, 8, hbuf_size - i))) 1082 return -ENXIO; 1083 } 1084 1085 return hbuf_size; 1086 } 1087 1088 static bool intel_sdvo_compute_avi_infoframe(struct intel_sdvo *intel_sdvo, 1089 struct intel_crtc_state *crtc_state, 1090 struct drm_connector_state *conn_state) 1091 { 1092 struct drm_i915_private *dev_priv = to_i915(intel_sdvo->base.base.dev); 1093 struct hdmi_avi_infoframe *frame = &crtc_state->infoframes.avi.avi; 1094 const struct drm_display_mode *adjusted_mode = 1095 &crtc_state->hw.adjusted_mode; 1096 int ret; 1097 1098 if (!crtc_state->has_hdmi_sink) 1099 return true; 1100 1101 crtc_state->infoframes.enable |= 1102 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_AVI); 1103 1104 ret = drm_hdmi_avi_infoframe_from_display_mode(frame, 1105 conn_state->connector, 1106 adjusted_mode); 1107 if (ret) 1108 return false; 1109 1110 drm_hdmi_avi_infoframe_quant_range(frame, 1111 conn_state->connector, 1112 adjusted_mode, 1113 crtc_state->limited_color_range ? 1114 HDMI_QUANTIZATION_RANGE_LIMITED : 1115 HDMI_QUANTIZATION_RANGE_FULL); 1116 1117 ret = hdmi_avi_infoframe_check(frame); 1118 if (drm_WARN_ON(&dev_priv->drm, ret)) 1119 return false; 1120 1121 return true; 1122 } 1123 1124 static bool intel_sdvo_set_avi_infoframe(struct intel_sdvo *intel_sdvo, 1125 const struct intel_crtc_state *crtc_state) 1126 { 1127 struct drm_i915_private *dev_priv = to_i915(intel_sdvo->base.base.dev); 1128 u8 sdvo_data[HDMI_INFOFRAME_SIZE(AVI)]; 1129 const union hdmi_infoframe *frame = &crtc_state->infoframes.avi; 1130 ssize_t len; 1131 1132 if ((crtc_state->infoframes.enable & 1133 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_AVI)) == 0) 1134 return true; 1135 1136 if (drm_WARN_ON(&dev_priv->drm, 1137 frame->any.type != HDMI_INFOFRAME_TYPE_AVI)) 1138 return false; 1139 1140 len = hdmi_infoframe_pack_only(frame, sdvo_data, sizeof(sdvo_data)); 1141 if (drm_WARN_ON(&dev_priv->drm, len < 0)) 1142 return false; 1143 1144 return intel_sdvo_write_infoframe(intel_sdvo, SDVO_HBUF_INDEX_AVI_IF, 1145 SDVO_HBUF_TX_VSYNC, 1146 sdvo_data, len); 1147 } 1148 1149 static void intel_sdvo_get_avi_infoframe(struct intel_sdvo *intel_sdvo, 1150 struct intel_crtc_state *crtc_state) 1151 { 1152 u8 sdvo_data[HDMI_INFOFRAME_SIZE(AVI)]; 1153 union hdmi_infoframe *frame = &crtc_state->infoframes.avi; 1154 ssize_t len; 1155 int ret; 1156 1157 if (!crtc_state->has_hdmi_sink) 1158 return; 1159 1160 len = intel_sdvo_read_infoframe(intel_sdvo, SDVO_HBUF_INDEX_AVI_IF, 1161 sdvo_data, sizeof(sdvo_data)); 1162 if (len < 0) { 1163 DRM_DEBUG_KMS("failed to read AVI infoframe\n"); 1164 return; 1165 } else if (len == 0) { 1166 return; 1167 } 1168 1169 crtc_state->infoframes.enable |= 1170 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_AVI); 1171 1172 ret = hdmi_infoframe_unpack(frame, sdvo_data, len); 1173 if (ret) { 1174 DRM_DEBUG_KMS("Failed to unpack AVI infoframe\n"); 1175 return; 1176 } 1177 1178 if (frame->any.type != HDMI_INFOFRAME_TYPE_AVI) 1179 DRM_DEBUG_KMS("Found the wrong infoframe type 0x%x (expected 0x%02x)\n", 1180 frame->any.type, HDMI_INFOFRAME_TYPE_AVI); 1181 } 1182 1183 static void intel_sdvo_get_eld(struct intel_sdvo *intel_sdvo, 1184 struct intel_crtc_state *crtc_state) 1185 { 1186 struct drm_i915_private *i915 = to_i915(intel_sdvo->base.base.dev); 1187 ssize_t len; 1188 u8 val; 1189 1190 if (!crtc_state->has_audio) 1191 return; 1192 1193 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_AUDIO_STAT, &val, 1)) 1194 return; 1195 1196 if ((val & SDVO_AUDIO_ELD_VALID) == 0) 1197 return; 1198 1199 len = intel_sdvo_read_infoframe(intel_sdvo, SDVO_HBUF_INDEX_ELD, 1200 crtc_state->eld, sizeof(crtc_state->eld)); 1201 if (len < 0) 1202 drm_dbg_kms(&i915->drm, "failed to read ELD\n"); 1203 } 1204 1205 static bool intel_sdvo_set_tv_format(struct intel_sdvo *intel_sdvo, 1206 const struct drm_connector_state *conn_state) 1207 { 1208 struct intel_sdvo_tv_format format; 1209 u32 format_map; 1210 1211 format_map = 1 << conn_state->tv.mode; 1212 memset(&format, 0, sizeof(format)); 1213 memcpy(&format, &format_map, min(sizeof(format), sizeof(format_map))); 1214 1215 BUILD_BUG_ON(sizeof(format) != 6); 1216 return intel_sdvo_set_value(intel_sdvo, 1217 SDVO_CMD_SET_TV_FORMAT, 1218 &format, sizeof(format)); 1219 } 1220 1221 static bool 1222 intel_sdvo_set_output_timings_from_mode(struct intel_sdvo *intel_sdvo, 1223 struct intel_sdvo_connector *intel_sdvo_connector, 1224 const struct drm_display_mode *mode) 1225 { 1226 struct intel_sdvo_dtd output_dtd; 1227 1228 if (!intel_sdvo_set_target_output(intel_sdvo, 1229 intel_sdvo_connector->output_flag)) 1230 return false; 1231 1232 intel_sdvo_get_dtd_from_mode(&output_dtd, mode); 1233 if (!intel_sdvo_set_output_timing(intel_sdvo, &output_dtd)) 1234 return false; 1235 1236 return true; 1237 } 1238 1239 /* 1240 * Asks the sdvo controller for the preferred input mode given the output mode. 1241 * Unfortunately we have to set up the full output mode to do that. 1242 */ 1243 static bool 1244 intel_sdvo_get_preferred_input_mode(struct intel_sdvo *intel_sdvo, 1245 struct intel_sdvo_connector *intel_sdvo_connector, 1246 const struct drm_display_mode *mode, 1247 struct drm_display_mode *adjusted_mode) 1248 { 1249 struct intel_sdvo_dtd input_dtd; 1250 1251 /* Reset the input timing to the screen. Assume always input 0. */ 1252 if (!intel_sdvo_set_target_input(intel_sdvo)) 1253 return false; 1254 1255 if (!intel_sdvo_create_preferred_input_timing(intel_sdvo, 1256 intel_sdvo_connector, 1257 mode)) 1258 return false; 1259 1260 if (!intel_sdvo_get_preferred_input_timing(intel_sdvo, 1261 &input_dtd)) 1262 return false; 1263 1264 intel_sdvo_get_mode_from_dtd(adjusted_mode, &input_dtd); 1265 intel_sdvo->dtd_sdvo_flags = input_dtd.part2.sdvo_flags; 1266 1267 return true; 1268 } 1269 1270 static int i9xx_adjust_sdvo_tv_clock(struct intel_crtc_state *pipe_config) 1271 { 1272 struct drm_i915_private *dev_priv = to_i915(pipe_config->uapi.crtc->dev); 1273 unsigned int dotclock = pipe_config->hw.adjusted_mode.crtc_clock; 1274 struct dpll *clock = &pipe_config->dpll; 1275 1276 /* 1277 * SDVO TV has fixed PLL values depend on its clock range, 1278 * this mirrors vbios setting. 1279 */ 1280 if (dotclock >= 100000 && dotclock < 140500) { 1281 clock->p1 = 2; 1282 clock->p2 = 10; 1283 clock->n = 3; 1284 clock->m1 = 16; 1285 clock->m2 = 8; 1286 } else if (dotclock >= 140500 && dotclock <= 200000) { 1287 clock->p1 = 1; 1288 clock->p2 = 10; 1289 clock->n = 6; 1290 clock->m1 = 12; 1291 clock->m2 = 8; 1292 } else { 1293 drm_dbg_kms(&dev_priv->drm, 1294 "SDVO TV clock out of range: %i\n", dotclock); 1295 return -EINVAL; 1296 } 1297 1298 pipe_config->clock_set = true; 1299 1300 return 0; 1301 } 1302 1303 static bool intel_has_hdmi_sink(struct intel_sdvo_connector *intel_sdvo_connector, 1304 const struct drm_connector_state *conn_state) 1305 { 1306 struct drm_connector *connector = conn_state->connector; 1307 1308 return intel_sdvo_connector->is_hdmi && 1309 connector->display_info.is_hdmi && 1310 READ_ONCE(to_intel_digital_connector_state(conn_state)->force_audio) != HDMI_AUDIO_OFF_DVI; 1311 } 1312 1313 static bool intel_sdvo_limited_color_range(struct intel_encoder *encoder, 1314 const struct intel_crtc_state *crtc_state, 1315 const struct drm_connector_state *conn_state) 1316 { 1317 struct intel_sdvo *intel_sdvo = to_sdvo(encoder); 1318 1319 if ((intel_sdvo->colorimetry_cap & SDVO_COLORIMETRY_RGB220) == 0) 1320 return false; 1321 1322 return intel_hdmi_limited_color_range(crtc_state, conn_state); 1323 } 1324 1325 static bool intel_sdvo_has_audio(struct intel_encoder *encoder, 1326 const struct intel_crtc_state *crtc_state, 1327 const struct drm_connector_state *conn_state) 1328 { 1329 struct drm_connector *connector = conn_state->connector; 1330 struct intel_sdvo_connector *intel_sdvo_connector = 1331 to_intel_sdvo_connector(connector); 1332 const struct intel_digital_connector_state *intel_conn_state = 1333 to_intel_digital_connector_state(conn_state); 1334 1335 if (!crtc_state->has_hdmi_sink) 1336 return false; 1337 1338 if (intel_conn_state->force_audio == HDMI_AUDIO_AUTO) 1339 return intel_sdvo_connector->is_hdmi && 1340 connector->display_info.has_audio; 1341 else 1342 return intel_conn_state->force_audio == HDMI_AUDIO_ON; 1343 } 1344 1345 static int intel_sdvo_compute_config(struct intel_encoder *encoder, 1346 struct intel_crtc_state *pipe_config, 1347 struct drm_connector_state *conn_state) 1348 { 1349 struct intel_sdvo *intel_sdvo = to_sdvo(encoder); 1350 struct intel_sdvo_connector *intel_sdvo_connector = 1351 to_intel_sdvo_connector(conn_state->connector); 1352 struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode; 1353 struct drm_display_mode *mode = &pipe_config->hw.mode; 1354 1355 if (HAS_PCH_SPLIT(to_i915(encoder->base.dev))) { 1356 pipe_config->has_pch_encoder = true; 1357 if (!intel_fdi_compute_pipe_bpp(pipe_config)) 1358 return -EINVAL; 1359 } 1360 1361 DRM_DEBUG_KMS("forcing bpc to 8 for SDVO\n"); 1362 /* FIXME: Don't increase pipe_bpp */ 1363 pipe_config->pipe_bpp = 8*3; 1364 pipe_config->sink_format = INTEL_OUTPUT_FORMAT_RGB; 1365 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; 1366 1367 /* 1368 * We need to construct preferred input timings based on our 1369 * output timings. To do that, we have to set the output 1370 * timings, even though this isn't really the right place in 1371 * the sequence to do it. Oh well. 1372 */ 1373 if (IS_TV(intel_sdvo_connector)) { 1374 if (!intel_sdvo_set_output_timings_from_mode(intel_sdvo, 1375 intel_sdvo_connector, 1376 mode)) 1377 return -EINVAL; 1378 1379 (void) intel_sdvo_get_preferred_input_mode(intel_sdvo, 1380 intel_sdvo_connector, 1381 mode, 1382 adjusted_mode); 1383 pipe_config->sdvo_tv_clock = true; 1384 } else if (IS_LVDS(intel_sdvo_connector)) { 1385 const struct drm_display_mode *fixed_mode = 1386 intel_panel_fixed_mode(&intel_sdvo_connector->base, mode); 1387 int ret; 1388 1389 ret = intel_panel_compute_config(&intel_sdvo_connector->base, 1390 adjusted_mode); 1391 if (ret) 1392 return ret; 1393 1394 if (!intel_sdvo_set_output_timings_from_mode(intel_sdvo, 1395 intel_sdvo_connector, 1396 fixed_mode)) 1397 return -EINVAL; 1398 1399 (void) intel_sdvo_get_preferred_input_mode(intel_sdvo, 1400 intel_sdvo_connector, 1401 mode, 1402 adjusted_mode); 1403 } 1404 1405 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN) 1406 return -EINVAL; 1407 1408 /* 1409 * Make the CRTC code factor in the SDVO pixel multiplier. The 1410 * SDVO device will factor out the multiplier during mode_set. 1411 */ 1412 pipe_config->pixel_multiplier = 1413 intel_sdvo_get_pixel_multiplier(adjusted_mode); 1414 1415 pipe_config->has_hdmi_sink = intel_has_hdmi_sink(intel_sdvo_connector, conn_state); 1416 1417 pipe_config->has_audio = 1418 intel_sdvo_has_audio(encoder, pipe_config, conn_state) && 1419 intel_audio_compute_config(encoder, pipe_config, conn_state); 1420 1421 pipe_config->limited_color_range = 1422 intel_sdvo_limited_color_range(encoder, pipe_config, 1423 conn_state); 1424 1425 /* Clock computation needs to happen after pixel multiplier. */ 1426 if (IS_TV(intel_sdvo_connector)) { 1427 int ret; 1428 1429 ret = i9xx_adjust_sdvo_tv_clock(pipe_config); 1430 if (ret) 1431 return ret; 1432 } 1433 1434 if (conn_state->picture_aspect_ratio) 1435 adjusted_mode->picture_aspect_ratio = 1436 conn_state->picture_aspect_ratio; 1437 1438 if (!intel_sdvo_compute_avi_infoframe(intel_sdvo, 1439 pipe_config, conn_state)) { 1440 DRM_DEBUG_KMS("bad AVI infoframe\n"); 1441 return -EINVAL; 1442 } 1443 1444 return 0; 1445 } 1446 1447 #define UPDATE_PROPERTY(input, NAME) \ 1448 do { \ 1449 val = input; \ 1450 intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_##NAME, &val, sizeof(val)); \ 1451 } while (0) 1452 1453 static void intel_sdvo_update_props(struct intel_sdvo *intel_sdvo, 1454 const struct intel_sdvo_connector_state *sdvo_state) 1455 { 1456 const struct drm_connector_state *conn_state = &sdvo_state->base.base; 1457 struct intel_sdvo_connector *intel_sdvo_conn = 1458 to_intel_sdvo_connector(conn_state->connector); 1459 u16 val; 1460 1461 if (intel_sdvo_conn->left) 1462 UPDATE_PROPERTY(sdvo_state->tv.overscan_h, OVERSCAN_H); 1463 1464 if (intel_sdvo_conn->top) 1465 UPDATE_PROPERTY(sdvo_state->tv.overscan_v, OVERSCAN_V); 1466 1467 if (intel_sdvo_conn->hpos) 1468 UPDATE_PROPERTY(sdvo_state->tv.hpos, HPOS); 1469 1470 if (intel_sdvo_conn->vpos) 1471 UPDATE_PROPERTY(sdvo_state->tv.vpos, VPOS); 1472 1473 if (intel_sdvo_conn->saturation) 1474 UPDATE_PROPERTY(conn_state->tv.saturation, SATURATION); 1475 1476 if (intel_sdvo_conn->contrast) 1477 UPDATE_PROPERTY(conn_state->tv.contrast, CONTRAST); 1478 1479 if (intel_sdvo_conn->hue) 1480 UPDATE_PROPERTY(conn_state->tv.hue, HUE); 1481 1482 if (intel_sdvo_conn->brightness) 1483 UPDATE_PROPERTY(conn_state->tv.brightness, BRIGHTNESS); 1484 1485 if (intel_sdvo_conn->sharpness) 1486 UPDATE_PROPERTY(sdvo_state->tv.sharpness, SHARPNESS); 1487 1488 if (intel_sdvo_conn->flicker_filter) 1489 UPDATE_PROPERTY(sdvo_state->tv.flicker_filter, FLICKER_FILTER); 1490 1491 if (intel_sdvo_conn->flicker_filter_2d) 1492 UPDATE_PROPERTY(sdvo_state->tv.flicker_filter_2d, FLICKER_FILTER_2D); 1493 1494 if (intel_sdvo_conn->flicker_filter_adaptive) 1495 UPDATE_PROPERTY(sdvo_state->tv.flicker_filter_adaptive, FLICKER_FILTER_ADAPTIVE); 1496 1497 if (intel_sdvo_conn->tv_chroma_filter) 1498 UPDATE_PROPERTY(sdvo_state->tv.chroma_filter, TV_CHROMA_FILTER); 1499 1500 if (intel_sdvo_conn->tv_luma_filter) 1501 UPDATE_PROPERTY(sdvo_state->tv.luma_filter, TV_LUMA_FILTER); 1502 1503 if (intel_sdvo_conn->dot_crawl) 1504 UPDATE_PROPERTY(sdvo_state->tv.dot_crawl, DOT_CRAWL); 1505 1506 #undef UPDATE_PROPERTY 1507 } 1508 1509 static void intel_sdvo_pre_enable(struct intel_atomic_state *state, 1510 struct intel_encoder *intel_encoder, 1511 const struct intel_crtc_state *crtc_state, 1512 const struct drm_connector_state *conn_state) 1513 { 1514 struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev); 1515 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1516 const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; 1517 const struct intel_sdvo_connector_state *sdvo_state = 1518 to_intel_sdvo_connector_state(conn_state); 1519 struct intel_sdvo_connector *intel_sdvo_connector = 1520 to_intel_sdvo_connector(conn_state->connector); 1521 const struct drm_display_mode *mode = &crtc_state->hw.mode; 1522 struct intel_sdvo *intel_sdvo = to_sdvo(intel_encoder); 1523 u32 sdvox; 1524 struct intel_sdvo_in_out_map in_out; 1525 struct intel_sdvo_dtd input_dtd, output_dtd; 1526 int rate; 1527 1528 intel_sdvo_update_props(intel_sdvo, sdvo_state); 1529 1530 /* 1531 * First, set the input mapping for the first input to our controlled 1532 * output. This is only correct if we're a single-input device, in 1533 * which case the first input is the output from the appropriate SDVO 1534 * channel on the motherboard. In a two-input device, the first input 1535 * will be SDVOB and the second SDVOC. 1536 */ 1537 in_out.in0 = intel_sdvo_connector->output_flag; 1538 in_out.in1 = 0; 1539 1540 intel_sdvo_set_value(intel_sdvo, 1541 SDVO_CMD_SET_IN_OUT_MAP, 1542 &in_out, sizeof(in_out)); 1543 1544 /* Set the output timings to the screen */ 1545 if (!intel_sdvo_set_target_output(intel_sdvo, 1546 intel_sdvo_connector->output_flag)) 1547 return; 1548 1549 /* lvds has a special fixed output timing. */ 1550 if (IS_LVDS(intel_sdvo_connector)) { 1551 const struct drm_display_mode *fixed_mode = 1552 intel_panel_fixed_mode(&intel_sdvo_connector->base, mode); 1553 1554 intel_sdvo_get_dtd_from_mode(&output_dtd, fixed_mode); 1555 } else { 1556 intel_sdvo_get_dtd_from_mode(&output_dtd, mode); 1557 } 1558 if (!intel_sdvo_set_output_timing(intel_sdvo, &output_dtd)) 1559 drm_info(&dev_priv->drm, 1560 "Setting output timings on %s failed\n", 1561 SDVO_NAME(intel_sdvo)); 1562 1563 /* Set the input timing to the screen. Assume always input 0. */ 1564 if (!intel_sdvo_set_target_input(intel_sdvo)) 1565 return; 1566 1567 if (crtc_state->has_hdmi_sink) { 1568 intel_sdvo_set_encode(intel_sdvo, SDVO_ENCODE_HDMI); 1569 intel_sdvo_set_colorimetry(intel_sdvo, 1570 crtc_state->limited_color_range ? 1571 SDVO_COLORIMETRY_RGB220 : 1572 SDVO_COLORIMETRY_RGB256); 1573 intel_sdvo_set_avi_infoframe(intel_sdvo, crtc_state); 1574 intel_sdvo_set_pixel_replication(intel_sdvo, 1575 !!(adjusted_mode->flags & 1576 DRM_MODE_FLAG_DBLCLK)); 1577 } else 1578 intel_sdvo_set_encode(intel_sdvo, SDVO_ENCODE_DVI); 1579 1580 if (IS_TV(intel_sdvo_connector) && 1581 !intel_sdvo_set_tv_format(intel_sdvo, conn_state)) 1582 return; 1583 1584 intel_sdvo_get_dtd_from_mode(&input_dtd, adjusted_mode); 1585 1586 if (IS_TV(intel_sdvo_connector) || IS_LVDS(intel_sdvo_connector)) 1587 input_dtd.part2.sdvo_flags = intel_sdvo->dtd_sdvo_flags; 1588 if (!intel_sdvo_set_input_timing(intel_sdvo, &input_dtd)) 1589 drm_info(&dev_priv->drm, 1590 "Setting input timings on %s failed\n", 1591 SDVO_NAME(intel_sdvo)); 1592 1593 switch (crtc_state->pixel_multiplier) { 1594 default: 1595 drm_WARN(&dev_priv->drm, 1, 1596 "unknown pixel multiplier specified\n"); 1597 fallthrough; 1598 case 1: rate = SDVO_CLOCK_RATE_MULT_1X; break; 1599 case 2: rate = SDVO_CLOCK_RATE_MULT_2X; break; 1600 case 4: rate = SDVO_CLOCK_RATE_MULT_4X; break; 1601 } 1602 if (!intel_sdvo_set_clock_rate_mult(intel_sdvo, rate)) 1603 return; 1604 1605 /* Set the SDVO control regs. */ 1606 if (DISPLAY_VER(dev_priv) >= 4) { 1607 /* The real mode polarity is set by the SDVO commands, using 1608 * struct intel_sdvo_dtd. */ 1609 sdvox = SDVO_VSYNC_ACTIVE_HIGH | SDVO_HSYNC_ACTIVE_HIGH; 1610 if (DISPLAY_VER(dev_priv) < 5) 1611 sdvox |= SDVO_BORDER_ENABLE; 1612 } else { 1613 sdvox = intel_de_read(dev_priv, intel_sdvo->sdvo_reg); 1614 if (intel_sdvo->base.port == PORT_B) 1615 sdvox &= SDVOB_PRESERVE_MASK; 1616 else 1617 sdvox &= SDVOC_PRESERVE_MASK; 1618 sdvox |= (9 << 19) | SDVO_BORDER_ENABLE; 1619 } 1620 1621 if (HAS_PCH_CPT(dev_priv)) 1622 sdvox |= SDVO_PIPE_SEL_CPT(crtc->pipe); 1623 else 1624 sdvox |= SDVO_PIPE_SEL(crtc->pipe); 1625 1626 if (DISPLAY_VER(dev_priv) >= 4) { 1627 /* done in crtc_mode_set as the dpll_md reg must be written early */ 1628 } else if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) || 1629 IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) { 1630 /* done in crtc_mode_set as it lives inside the dpll register */ 1631 } else { 1632 sdvox |= (crtc_state->pixel_multiplier - 1) 1633 << SDVO_PORT_MULTIPLY_SHIFT; 1634 } 1635 1636 if (input_dtd.part2.sdvo_flags & SDVO_NEED_TO_STALL && 1637 DISPLAY_VER(dev_priv) < 5) 1638 sdvox |= SDVO_STALL_SELECT; 1639 intel_sdvo_write_sdvox(intel_sdvo, sdvox); 1640 } 1641 1642 static bool intel_sdvo_connector_get_hw_state(struct intel_connector *connector) 1643 { 1644 struct intel_sdvo_connector *intel_sdvo_connector = 1645 to_intel_sdvo_connector(&connector->base); 1646 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector); 1647 u16 active_outputs = 0; 1648 1649 intel_sdvo_get_active_outputs(intel_sdvo, &active_outputs); 1650 1651 return active_outputs & intel_sdvo_connector->output_flag; 1652 } 1653 1654 bool intel_sdvo_port_enabled(struct drm_i915_private *dev_priv, 1655 i915_reg_t sdvo_reg, enum pipe *pipe) 1656 { 1657 u32 val; 1658 1659 val = intel_de_read(dev_priv, sdvo_reg); 1660 1661 /* asserts want to know the pipe even if the port is disabled */ 1662 if (HAS_PCH_CPT(dev_priv)) 1663 *pipe = (val & SDVO_PIPE_SEL_MASK_CPT) >> SDVO_PIPE_SEL_SHIFT_CPT; 1664 else if (IS_CHERRYVIEW(dev_priv)) 1665 *pipe = (val & SDVO_PIPE_SEL_MASK_CHV) >> SDVO_PIPE_SEL_SHIFT_CHV; 1666 else 1667 *pipe = (val & SDVO_PIPE_SEL_MASK) >> SDVO_PIPE_SEL_SHIFT; 1668 1669 return val & SDVO_ENABLE; 1670 } 1671 1672 static bool intel_sdvo_get_hw_state(struct intel_encoder *encoder, 1673 enum pipe *pipe) 1674 { 1675 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1676 struct intel_sdvo *intel_sdvo = to_sdvo(encoder); 1677 u16 active_outputs = 0; 1678 bool ret; 1679 1680 intel_sdvo_get_active_outputs(intel_sdvo, &active_outputs); 1681 1682 ret = intel_sdvo_port_enabled(dev_priv, intel_sdvo->sdvo_reg, pipe); 1683 1684 return ret || active_outputs; 1685 } 1686 1687 static void intel_sdvo_get_config(struct intel_encoder *encoder, 1688 struct intel_crtc_state *pipe_config) 1689 { 1690 struct drm_device *dev = encoder->base.dev; 1691 struct drm_i915_private *dev_priv = to_i915(dev); 1692 struct intel_sdvo *intel_sdvo = to_sdvo(encoder); 1693 struct intel_sdvo_dtd dtd; 1694 int encoder_pixel_multiplier = 0; 1695 int dotclock; 1696 u32 flags = 0, sdvox; 1697 u8 val; 1698 bool ret; 1699 1700 pipe_config->output_types |= BIT(INTEL_OUTPUT_SDVO); 1701 1702 sdvox = intel_de_read(dev_priv, intel_sdvo->sdvo_reg); 1703 1704 ret = intel_sdvo_get_input_timing(intel_sdvo, &dtd); 1705 if (!ret) { 1706 /* 1707 * Some sdvo encoders are not spec compliant and don't 1708 * implement the mandatory get_timings function. 1709 */ 1710 drm_dbg(&dev_priv->drm, "failed to retrieve SDVO DTD\n"); 1711 pipe_config->quirks |= PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS; 1712 } else { 1713 if (dtd.part2.dtd_flags & DTD_FLAG_HSYNC_POSITIVE) 1714 flags |= DRM_MODE_FLAG_PHSYNC; 1715 else 1716 flags |= DRM_MODE_FLAG_NHSYNC; 1717 1718 if (dtd.part2.dtd_flags & DTD_FLAG_VSYNC_POSITIVE) 1719 flags |= DRM_MODE_FLAG_PVSYNC; 1720 else 1721 flags |= DRM_MODE_FLAG_NVSYNC; 1722 } 1723 1724 pipe_config->hw.adjusted_mode.flags |= flags; 1725 1726 /* 1727 * pixel multiplier readout is tricky: Only on i915g/gm it is stored in 1728 * the sdvo port register, on all other platforms it is part of the dpll 1729 * state. Since the general pipe state readout happens before the 1730 * encoder->get_config we so already have a valid pixel multplier on all 1731 * other platfroms. 1732 */ 1733 if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) { 1734 pipe_config->pixel_multiplier = 1735 ((sdvox & SDVO_PORT_MULTIPLY_MASK) 1736 >> SDVO_PORT_MULTIPLY_SHIFT) + 1; 1737 } 1738 1739 dotclock = pipe_config->port_clock; 1740 1741 if (pipe_config->pixel_multiplier) 1742 dotclock /= pipe_config->pixel_multiplier; 1743 1744 pipe_config->hw.adjusted_mode.crtc_clock = dotclock; 1745 1746 /* Cross check the port pixel multiplier with the sdvo encoder state. */ 1747 if (intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_CLOCK_RATE_MULT, 1748 &val, 1)) { 1749 switch (val) { 1750 case SDVO_CLOCK_RATE_MULT_1X: 1751 encoder_pixel_multiplier = 1; 1752 break; 1753 case SDVO_CLOCK_RATE_MULT_2X: 1754 encoder_pixel_multiplier = 2; 1755 break; 1756 case SDVO_CLOCK_RATE_MULT_4X: 1757 encoder_pixel_multiplier = 4; 1758 break; 1759 } 1760 } 1761 1762 drm_WARN(dev, 1763 encoder_pixel_multiplier != pipe_config->pixel_multiplier, 1764 "SDVO pixel multiplier mismatch, port: %i, encoder: %i\n", 1765 pipe_config->pixel_multiplier, encoder_pixel_multiplier); 1766 1767 if (intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_COLORIMETRY, 1768 &val, 1)) { 1769 if (val == SDVO_COLORIMETRY_RGB220) 1770 pipe_config->limited_color_range = true; 1771 } 1772 1773 if (intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_AUDIO_STAT, 1774 &val, 1)) { 1775 if (val & SDVO_AUDIO_PRESENCE_DETECT) 1776 pipe_config->has_audio = true; 1777 } 1778 1779 if (intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_ENCODE, 1780 &val, 1)) { 1781 if (val == SDVO_ENCODE_HDMI) 1782 pipe_config->has_hdmi_sink = true; 1783 } 1784 1785 intel_sdvo_get_avi_infoframe(intel_sdvo, pipe_config); 1786 1787 intel_sdvo_get_eld(intel_sdvo, pipe_config); 1788 } 1789 1790 static void intel_sdvo_disable_audio(struct intel_sdvo *intel_sdvo) 1791 { 1792 intel_sdvo_set_audio_state(intel_sdvo, 0); 1793 } 1794 1795 static void intel_sdvo_enable_audio(struct intel_sdvo *intel_sdvo, 1796 const struct intel_crtc_state *crtc_state, 1797 const struct drm_connector_state *conn_state) 1798 { 1799 const u8 *eld = crtc_state->eld; 1800 1801 intel_sdvo_set_audio_state(intel_sdvo, 0); 1802 1803 intel_sdvo_write_infoframe(intel_sdvo, SDVO_HBUF_INDEX_ELD, 1804 SDVO_HBUF_TX_DISABLED, 1805 eld, drm_eld_size(eld)); 1806 1807 intel_sdvo_set_audio_state(intel_sdvo, SDVO_AUDIO_ELD_VALID | 1808 SDVO_AUDIO_PRESENCE_DETECT); 1809 } 1810 1811 static void intel_disable_sdvo(struct intel_atomic_state *state, 1812 struct intel_encoder *encoder, 1813 const struct intel_crtc_state *old_crtc_state, 1814 const struct drm_connector_state *conn_state) 1815 { 1816 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1817 struct intel_sdvo *intel_sdvo = to_sdvo(encoder); 1818 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); 1819 u32 temp; 1820 1821 if (old_crtc_state->has_audio) 1822 intel_sdvo_disable_audio(intel_sdvo); 1823 1824 intel_sdvo_set_active_outputs(intel_sdvo, 0); 1825 if (0) 1826 intel_sdvo_set_encoder_power_state(intel_sdvo, 1827 DRM_MODE_DPMS_OFF); 1828 1829 temp = intel_de_read(dev_priv, intel_sdvo->sdvo_reg); 1830 1831 temp &= ~SDVO_ENABLE; 1832 intel_sdvo_write_sdvox(intel_sdvo, temp); 1833 1834 /* 1835 * HW workaround for IBX, we need to move the port 1836 * to transcoder A after disabling it to allow the 1837 * matching DP port to be enabled on transcoder A. 1838 */ 1839 if (HAS_PCH_IBX(dev_priv) && crtc->pipe == PIPE_B) { 1840 /* 1841 * We get CPU/PCH FIFO underruns on the other pipe when 1842 * doing the workaround. Sweep them under the rug. 1843 */ 1844 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false); 1845 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false); 1846 1847 temp &= ~SDVO_PIPE_SEL_MASK; 1848 temp |= SDVO_ENABLE | SDVO_PIPE_SEL(PIPE_A); 1849 intel_sdvo_write_sdvox(intel_sdvo, temp); 1850 1851 temp &= ~SDVO_ENABLE; 1852 intel_sdvo_write_sdvox(intel_sdvo, temp); 1853 1854 intel_wait_for_vblank_if_active(dev_priv, PIPE_A); 1855 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true); 1856 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true); 1857 } 1858 } 1859 1860 static void pch_disable_sdvo(struct intel_atomic_state *state, 1861 struct intel_encoder *encoder, 1862 const struct intel_crtc_state *old_crtc_state, 1863 const struct drm_connector_state *old_conn_state) 1864 { 1865 } 1866 1867 static void pch_post_disable_sdvo(struct intel_atomic_state *state, 1868 struct intel_encoder *encoder, 1869 const struct intel_crtc_state *old_crtc_state, 1870 const struct drm_connector_state *old_conn_state) 1871 { 1872 intel_disable_sdvo(state, encoder, old_crtc_state, old_conn_state); 1873 } 1874 1875 static void intel_enable_sdvo(struct intel_atomic_state *state, 1876 struct intel_encoder *encoder, 1877 const struct intel_crtc_state *pipe_config, 1878 const struct drm_connector_state *conn_state) 1879 { 1880 struct drm_device *dev = encoder->base.dev; 1881 struct drm_i915_private *dev_priv = to_i915(dev); 1882 struct intel_sdvo *intel_sdvo = to_sdvo(encoder); 1883 struct intel_sdvo_connector *intel_sdvo_connector = 1884 to_intel_sdvo_connector(conn_state->connector); 1885 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 1886 u32 temp; 1887 bool input1, input2; 1888 int i; 1889 bool success; 1890 1891 temp = intel_de_read(dev_priv, intel_sdvo->sdvo_reg); 1892 temp |= SDVO_ENABLE; 1893 intel_sdvo_write_sdvox(intel_sdvo, temp); 1894 1895 for (i = 0; i < 2; i++) 1896 intel_crtc_wait_for_next_vblank(crtc); 1897 1898 success = intel_sdvo_get_trained_inputs(intel_sdvo, &input1, &input2); 1899 /* 1900 * Warn if the device reported failure to sync. 1901 * 1902 * A lot of SDVO devices fail to notify of sync, but it's 1903 * a given it the status is a success, we succeeded. 1904 */ 1905 if (success && !input1) { 1906 drm_dbg_kms(&dev_priv->drm, 1907 "First %s output reported failure to " 1908 "sync\n", SDVO_NAME(intel_sdvo)); 1909 } 1910 1911 if (0) 1912 intel_sdvo_set_encoder_power_state(intel_sdvo, 1913 DRM_MODE_DPMS_ON); 1914 intel_sdvo_set_active_outputs(intel_sdvo, intel_sdvo_connector->output_flag); 1915 1916 if (pipe_config->has_audio) 1917 intel_sdvo_enable_audio(intel_sdvo, pipe_config, conn_state); 1918 } 1919 1920 static enum drm_mode_status 1921 intel_sdvo_mode_valid(struct drm_connector *connector, 1922 struct drm_display_mode *mode) 1923 { 1924 struct drm_i915_private *i915 = to_i915(connector->dev); 1925 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(to_intel_connector(connector)); 1926 struct intel_sdvo_connector *intel_sdvo_connector = 1927 to_intel_sdvo_connector(connector); 1928 bool has_hdmi_sink = intel_has_hdmi_sink(intel_sdvo_connector, connector->state); 1929 int max_dotclk = i915->max_dotclk_freq; 1930 enum drm_mode_status status; 1931 int clock = mode->clock; 1932 1933 status = intel_cpu_transcoder_mode_valid(i915, mode); 1934 if (status != MODE_OK) 1935 return status; 1936 1937 if (mode->flags & DRM_MODE_FLAG_DBLSCAN) 1938 return MODE_NO_DBLESCAN; 1939 1940 if (clock > max_dotclk) 1941 return MODE_CLOCK_HIGH; 1942 1943 if (mode->flags & DRM_MODE_FLAG_DBLCLK) { 1944 if (!has_hdmi_sink) 1945 return MODE_CLOCK_LOW; 1946 clock *= 2; 1947 } 1948 1949 if (intel_sdvo->pixel_clock_min > clock) 1950 return MODE_CLOCK_LOW; 1951 1952 if (intel_sdvo->pixel_clock_max < clock) 1953 return MODE_CLOCK_HIGH; 1954 1955 if (IS_LVDS(intel_sdvo_connector)) { 1956 enum drm_mode_status status; 1957 1958 status = intel_panel_mode_valid(&intel_sdvo_connector->base, mode); 1959 if (status != MODE_OK) 1960 return status; 1961 } 1962 1963 return MODE_OK; 1964 } 1965 1966 static bool intel_sdvo_get_capabilities(struct intel_sdvo *intel_sdvo, struct intel_sdvo_caps *caps) 1967 { 1968 BUILD_BUG_ON(sizeof(*caps) != 8); 1969 if (!intel_sdvo_get_value(intel_sdvo, 1970 SDVO_CMD_GET_DEVICE_CAPS, 1971 caps, sizeof(*caps))) 1972 return false; 1973 1974 DRM_DEBUG_KMS("SDVO capabilities:\n" 1975 " vendor_id: %d\n" 1976 " device_id: %d\n" 1977 " device_rev_id: %d\n" 1978 " sdvo_version_major: %d\n" 1979 " sdvo_version_minor: %d\n" 1980 " sdvo_num_inputs: %d\n" 1981 " smooth_scaling: %d\n" 1982 " sharp_scaling: %d\n" 1983 " up_scaling: %d\n" 1984 " down_scaling: %d\n" 1985 " stall_support: %d\n" 1986 " output_flags: %d\n", 1987 caps->vendor_id, 1988 caps->device_id, 1989 caps->device_rev_id, 1990 caps->sdvo_version_major, 1991 caps->sdvo_version_minor, 1992 caps->sdvo_num_inputs, 1993 caps->smooth_scaling, 1994 caps->sharp_scaling, 1995 caps->up_scaling, 1996 caps->down_scaling, 1997 caps->stall_support, 1998 caps->output_flags); 1999 2000 return true; 2001 } 2002 2003 static u8 intel_sdvo_get_colorimetry_cap(struct intel_sdvo *intel_sdvo) 2004 { 2005 u8 cap; 2006 2007 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_COLORIMETRY_CAP, 2008 &cap, sizeof(cap))) 2009 return SDVO_COLORIMETRY_RGB256; 2010 2011 return cap; 2012 } 2013 2014 static u16 intel_sdvo_get_hotplug_support(struct intel_sdvo *intel_sdvo) 2015 { 2016 struct drm_i915_private *dev_priv = to_i915(intel_sdvo->base.base.dev); 2017 u16 hotplug; 2018 2019 if (!I915_HAS_HOTPLUG(dev_priv)) 2020 return 0; 2021 2022 /* 2023 * HW Erratum: SDVO Hotplug is broken on all i945G chips, there's noise 2024 * on the line. 2025 */ 2026 if (IS_I945G(dev_priv) || IS_I945GM(dev_priv)) 2027 return 0; 2028 2029 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_HOT_PLUG_SUPPORT, 2030 &hotplug, sizeof(hotplug))) 2031 return 0; 2032 2033 return hotplug; 2034 } 2035 2036 static void intel_sdvo_enable_hotplug(struct intel_encoder *encoder) 2037 { 2038 struct intel_sdvo *intel_sdvo = to_sdvo(encoder); 2039 2040 intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_SET_ACTIVE_HOT_PLUG, 2041 &intel_sdvo->hotplug_active, 2); 2042 } 2043 2044 static enum intel_hotplug_state 2045 intel_sdvo_hotplug(struct intel_encoder *encoder, 2046 struct intel_connector *connector) 2047 { 2048 intel_sdvo_enable_hotplug(encoder); 2049 2050 return intel_encoder_hotplug(encoder, connector); 2051 } 2052 2053 static const struct drm_edid * 2054 intel_sdvo_get_edid(struct drm_connector *connector) 2055 { 2056 struct i2c_adapter *ddc = connector->ddc; 2057 2058 if (!ddc) 2059 return NULL; 2060 2061 return drm_edid_read_ddc(connector, ddc); 2062 } 2063 2064 /* Mac mini hack -- use the same DDC as the analog connector */ 2065 static const struct drm_edid * 2066 intel_sdvo_get_analog_edid(struct drm_connector *connector) 2067 { 2068 struct drm_i915_private *i915 = to_i915(connector->dev); 2069 struct i2c_adapter *ddc; 2070 2071 ddc = intel_gmbus_get_adapter(i915, i915->display.vbt.crt_ddc_pin); 2072 if (!ddc) 2073 return NULL; 2074 2075 return drm_edid_read_ddc(connector, ddc); 2076 } 2077 2078 static enum drm_connector_status 2079 intel_sdvo_tmds_sink_detect(struct drm_connector *connector) 2080 { 2081 enum drm_connector_status status; 2082 const struct drm_edid *drm_edid; 2083 2084 drm_edid = intel_sdvo_get_edid(connector); 2085 2086 /* 2087 * When there is no edid and no monitor is connected with VGA 2088 * port, try to use the CRT ddc to read the EDID for DVI-connector. 2089 */ 2090 if (!drm_edid) 2091 drm_edid = intel_sdvo_get_analog_edid(connector); 2092 2093 status = connector_status_unknown; 2094 if (drm_edid) { 2095 /* DDC bus is shared, match EDID to connector type */ 2096 if (drm_edid_is_digital(drm_edid)) 2097 status = connector_status_connected; 2098 else 2099 status = connector_status_disconnected; 2100 drm_edid_free(drm_edid); 2101 } 2102 2103 return status; 2104 } 2105 2106 static bool 2107 intel_sdvo_connector_matches_edid(struct intel_sdvo_connector *sdvo, 2108 const struct drm_edid *drm_edid) 2109 { 2110 bool monitor_is_digital = drm_edid_is_digital(drm_edid); 2111 bool connector_is_digital = !!IS_DIGITAL(sdvo); 2112 2113 DRM_DEBUG_KMS("connector_is_digital? %d, monitor_is_digital? %d\n", 2114 connector_is_digital, monitor_is_digital); 2115 return connector_is_digital == monitor_is_digital; 2116 } 2117 2118 static enum drm_connector_status 2119 intel_sdvo_detect(struct drm_connector *connector, bool force) 2120 { 2121 struct drm_i915_private *i915 = to_i915(connector->dev); 2122 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(to_intel_connector(connector)); 2123 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector); 2124 enum drm_connector_status ret; 2125 u16 response; 2126 2127 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", 2128 connector->base.id, connector->name); 2129 2130 if (!intel_display_device_enabled(i915)) 2131 return connector_status_disconnected; 2132 2133 if (!intel_sdvo_set_target_output(intel_sdvo, 2134 intel_sdvo_connector->output_flag)) 2135 return connector_status_unknown; 2136 2137 if (!intel_sdvo_get_value(intel_sdvo, 2138 SDVO_CMD_GET_ATTACHED_DISPLAYS, 2139 &response, 2)) 2140 return connector_status_unknown; 2141 2142 DRM_DEBUG_KMS("SDVO response %d %d [%x]\n", 2143 response & 0xff, response >> 8, 2144 intel_sdvo_connector->output_flag); 2145 2146 if (response == 0) 2147 return connector_status_disconnected; 2148 2149 if ((intel_sdvo_connector->output_flag & response) == 0) 2150 ret = connector_status_disconnected; 2151 else if (IS_TMDS(intel_sdvo_connector)) 2152 ret = intel_sdvo_tmds_sink_detect(connector); 2153 else { 2154 const struct drm_edid *drm_edid; 2155 2156 /* if we have an edid check it matches the connection */ 2157 drm_edid = intel_sdvo_get_edid(connector); 2158 if (!drm_edid) 2159 drm_edid = intel_sdvo_get_analog_edid(connector); 2160 if (drm_edid) { 2161 if (intel_sdvo_connector_matches_edid(intel_sdvo_connector, 2162 drm_edid)) 2163 ret = connector_status_connected; 2164 else 2165 ret = connector_status_disconnected; 2166 2167 drm_edid_free(drm_edid); 2168 } else { 2169 ret = connector_status_connected; 2170 } 2171 } 2172 2173 return ret; 2174 } 2175 2176 static int intel_sdvo_get_ddc_modes(struct drm_connector *connector) 2177 { 2178 int num_modes = 0; 2179 const struct drm_edid *drm_edid; 2180 2181 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", 2182 connector->base.id, connector->name); 2183 2184 /* set the bus switch and get the modes */ 2185 drm_edid = intel_sdvo_get_edid(connector); 2186 2187 /* 2188 * Mac mini hack. On this device, the DVI-I connector shares one DDC 2189 * link between analog and digital outputs. So, if the regular SDVO 2190 * DDC fails, check to see if the analog output is disconnected, in 2191 * which case we'll look there for the digital DDC data. 2192 */ 2193 if (!drm_edid) 2194 drm_edid = intel_sdvo_get_analog_edid(connector); 2195 2196 if (!drm_edid) 2197 return 0; 2198 2199 if (intel_sdvo_connector_matches_edid(to_intel_sdvo_connector(connector), 2200 drm_edid)) 2201 num_modes += intel_connector_update_modes(connector, drm_edid); 2202 2203 drm_edid_free(drm_edid); 2204 2205 return num_modes; 2206 } 2207 2208 /* 2209 * Set of SDVO TV modes. 2210 * Note! This is in reply order (see loop in get_tv_modes). 2211 * XXX: all 60Hz refresh? 2212 */ 2213 static const struct drm_display_mode sdvo_tv_modes[] = { 2214 { DRM_MODE("320x200", DRM_MODE_TYPE_DRIVER, 5815, 320, 321, 384, 2215 416, 0, 200, 201, 232, 233, 0, 2216 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 2217 { DRM_MODE("320x240", DRM_MODE_TYPE_DRIVER, 6814, 320, 321, 384, 2218 416, 0, 240, 241, 272, 273, 0, 2219 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 2220 { DRM_MODE("400x300", DRM_MODE_TYPE_DRIVER, 9910, 400, 401, 464, 2221 496, 0, 300, 301, 332, 333, 0, 2222 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 2223 { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 16913, 640, 641, 704, 2224 736, 0, 350, 351, 382, 383, 0, 2225 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 2226 { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 19121, 640, 641, 704, 2227 736, 0, 400, 401, 432, 433, 0, 2228 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 2229 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 22654, 640, 641, 704, 2230 736, 0, 480, 481, 512, 513, 0, 2231 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 2232 { DRM_MODE("704x480", DRM_MODE_TYPE_DRIVER, 24624, 704, 705, 768, 2233 800, 0, 480, 481, 512, 513, 0, 2234 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 2235 { DRM_MODE("704x576", DRM_MODE_TYPE_DRIVER, 29232, 704, 705, 768, 2236 800, 0, 576, 577, 608, 609, 0, 2237 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 2238 { DRM_MODE("720x350", DRM_MODE_TYPE_DRIVER, 18751, 720, 721, 784, 2239 816, 0, 350, 351, 382, 383, 0, 2240 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 2241 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 21199, 720, 721, 784, 2242 816, 0, 400, 401, 432, 433, 0, 2243 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 2244 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 25116, 720, 721, 784, 2245 816, 0, 480, 481, 512, 513, 0, 2246 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 2247 { DRM_MODE("720x540", DRM_MODE_TYPE_DRIVER, 28054, 720, 721, 784, 2248 816, 0, 540, 541, 572, 573, 0, 2249 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 2250 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 29816, 720, 721, 784, 2251 816, 0, 576, 577, 608, 609, 0, 2252 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 2253 { DRM_MODE("768x576", DRM_MODE_TYPE_DRIVER, 31570, 768, 769, 832, 2254 864, 0, 576, 577, 608, 609, 0, 2255 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 2256 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 34030, 800, 801, 864, 2257 896, 0, 600, 601, 632, 633, 0, 2258 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 2259 { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 36581, 832, 833, 896, 2260 928, 0, 624, 625, 656, 657, 0, 2261 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 2262 { DRM_MODE("920x766", DRM_MODE_TYPE_DRIVER, 48707, 920, 921, 984, 2263 1016, 0, 766, 767, 798, 799, 0, 2264 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 2265 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 53827, 1024, 1025, 1088, 2266 1120, 0, 768, 769, 800, 801, 0, 2267 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 2268 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 87265, 1280, 1281, 1344, 2269 1376, 0, 1024, 1025, 1056, 1057, 0, 2270 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 2271 }; 2272 2273 static int intel_sdvo_get_tv_modes(struct drm_connector *connector) 2274 { 2275 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(to_intel_connector(connector)); 2276 struct intel_sdvo_connector *intel_sdvo_connector = 2277 to_intel_sdvo_connector(connector); 2278 const struct drm_connector_state *conn_state = connector->state; 2279 struct intel_sdvo_sdtv_resolution_request tv_res; 2280 u32 reply = 0, format_map = 0; 2281 int num_modes = 0; 2282 int i; 2283 2284 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", 2285 connector->base.id, connector->name); 2286 2287 /* 2288 * Read the list of supported input resolutions for the selected TV 2289 * format. 2290 */ 2291 format_map = 1 << conn_state->tv.mode; 2292 memcpy(&tv_res, &format_map, 2293 min(sizeof(format_map), sizeof(struct intel_sdvo_sdtv_resolution_request))); 2294 2295 if (!intel_sdvo_set_target_output(intel_sdvo, intel_sdvo_connector->output_flag)) 2296 return 0; 2297 2298 BUILD_BUG_ON(sizeof(tv_res) != 3); 2299 if (!intel_sdvo_write_cmd(intel_sdvo, 2300 SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT, 2301 &tv_res, sizeof(tv_res))) 2302 return 0; 2303 if (!intel_sdvo_read_response(intel_sdvo, &reply, 3)) 2304 return 0; 2305 2306 for (i = 0; i < ARRAY_SIZE(sdvo_tv_modes); i++) { 2307 if (reply & (1 << i)) { 2308 struct drm_display_mode *nmode; 2309 nmode = drm_mode_duplicate(connector->dev, 2310 &sdvo_tv_modes[i]); 2311 if (nmode) { 2312 drm_mode_probed_add(connector, nmode); 2313 num_modes++; 2314 } 2315 } 2316 } 2317 2318 return num_modes; 2319 } 2320 2321 static int intel_sdvo_get_lvds_modes(struct drm_connector *connector) 2322 { 2323 struct drm_i915_private *dev_priv = to_i915(connector->dev); 2324 2325 drm_dbg_kms(&dev_priv->drm, "[CONNECTOR:%d:%s]\n", 2326 connector->base.id, connector->name); 2327 2328 return intel_panel_get_modes(to_intel_connector(connector)); 2329 } 2330 2331 static int intel_sdvo_get_modes(struct drm_connector *connector) 2332 { 2333 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector); 2334 2335 if (IS_TV(intel_sdvo_connector)) 2336 return intel_sdvo_get_tv_modes(connector); 2337 else if (IS_LVDS(intel_sdvo_connector)) 2338 return intel_sdvo_get_lvds_modes(connector); 2339 else 2340 return intel_sdvo_get_ddc_modes(connector); 2341 } 2342 2343 static int 2344 intel_sdvo_connector_atomic_get_property(struct drm_connector *connector, 2345 const struct drm_connector_state *state, 2346 struct drm_property *property, 2347 u64 *val) 2348 { 2349 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector); 2350 const struct intel_sdvo_connector_state *sdvo_state = to_intel_sdvo_connector_state((void *)state); 2351 2352 if (property == intel_sdvo_connector->tv_format) { 2353 int i; 2354 2355 for (i = 0; i < intel_sdvo_connector->format_supported_num; i++) 2356 if (state->tv.mode == intel_sdvo_connector->tv_format_supported[i]) { 2357 *val = i; 2358 2359 return 0; 2360 } 2361 2362 drm_WARN_ON(connector->dev, 1); 2363 *val = 0; 2364 } else if (property == intel_sdvo_connector->top || 2365 property == intel_sdvo_connector->bottom) 2366 *val = intel_sdvo_connector->max_vscan - sdvo_state->tv.overscan_v; 2367 else if (property == intel_sdvo_connector->left || 2368 property == intel_sdvo_connector->right) 2369 *val = intel_sdvo_connector->max_hscan - sdvo_state->tv.overscan_h; 2370 else if (property == intel_sdvo_connector->hpos) 2371 *val = sdvo_state->tv.hpos; 2372 else if (property == intel_sdvo_connector->vpos) 2373 *val = sdvo_state->tv.vpos; 2374 else if (property == intel_sdvo_connector->saturation) 2375 *val = state->tv.saturation; 2376 else if (property == intel_sdvo_connector->contrast) 2377 *val = state->tv.contrast; 2378 else if (property == intel_sdvo_connector->hue) 2379 *val = state->tv.hue; 2380 else if (property == intel_sdvo_connector->brightness) 2381 *val = state->tv.brightness; 2382 else if (property == intel_sdvo_connector->sharpness) 2383 *val = sdvo_state->tv.sharpness; 2384 else if (property == intel_sdvo_connector->flicker_filter) 2385 *val = sdvo_state->tv.flicker_filter; 2386 else if (property == intel_sdvo_connector->flicker_filter_2d) 2387 *val = sdvo_state->tv.flicker_filter_2d; 2388 else if (property == intel_sdvo_connector->flicker_filter_adaptive) 2389 *val = sdvo_state->tv.flicker_filter_adaptive; 2390 else if (property == intel_sdvo_connector->tv_chroma_filter) 2391 *val = sdvo_state->tv.chroma_filter; 2392 else if (property == intel_sdvo_connector->tv_luma_filter) 2393 *val = sdvo_state->tv.luma_filter; 2394 else if (property == intel_sdvo_connector->dot_crawl) 2395 *val = sdvo_state->tv.dot_crawl; 2396 else 2397 return intel_digital_connector_atomic_get_property(connector, state, property, val); 2398 2399 return 0; 2400 } 2401 2402 static int 2403 intel_sdvo_connector_atomic_set_property(struct drm_connector *connector, 2404 struct drm_connector_state *state, 2405 struct drm_property *property, 2406 u64 val) 2407 { 2408 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector); 2409 struct intel_sdvo_connector_state *sdvo_state = to_intel_sdvo_connector_state(state); 2410 2411 if (property == intel_sdvo_connector->tv_format) { 2412 state->tv.mode = intel_sdvo_connector->tv_format_supported[val]; 2413 2414 if (state->crtc) { 2415 struct drm_crtc_state *crtc_state = 2416 drm_atomic_get_new_crtc_state(state->state, state->crtc); 2417 2418 crtc_state->connectors_changed = true; 2419 } 2420 } else if (property == intel_sdvo_connector->top || 2421 property == intel_sdvo_connector->bottom) 2422 /* Cannot set these independent from each other */ 2423 sdvo_state->tv.overscan_v = intel_sdvo_connector->max_vscan - val; 2424 else if (property == intel_sdvo_connector->left || 2425 property == intel_sdvo_connector->right) 2426 /* Cannot set these independent from each other */ 2427 sdvo_state->tv.overscan_h = intel_sdvo_connector->max_hscan - val; 2428 else if (property == intel_sdvo_connector->hpos) 2429 sdvo_state->tv.hpos = val; 2430 else if (property == intel_sdvo_connector->vpos) 2431 sdvo_state->tv.vpos = val; 2432 else if (property == intel_sdvo_connector->saturation) 2433 state->tv.saturation = val; 2434 else if (property == intel_sdvo_connector->contrast) 2435 state->tv.contrast = val; 2436 else if (property == intel_sdvo_connector->hue) 2437 state->tv.hue = val; 2438 else if (property == intel_sdvo_connector->brightness) 2439 state->tv.brightness = val; 2440 else if (property == intel_sdvo_connector->sharpness) 2441 sdvo_state->tv.sharpness = val; 2442 else if (property == intel_sdvo_connector->flicker_filter) 2443 sdvo_state->tv.flicker_filter = val; 2444 else if (property == intel_sdvo_connector->flicker_filter_2d) 2445 sdvo_state->tv.flicker_filter_2d = val; 2446 else if (property == intel_sdvo_connector->flicker_filter_adaptive) 2447 sdvo_state->tv.flicker_filter_adaptive = val; 2448 else if (property == intel_sdvo_connector->tv_chroma_filter) 2449 sdvo_state->tv.chroma_filter = val; 2450 else if (property == intel_sdvo_connector->tv_luma_filter) 2451 sdvo_state->tv.luma_filter = val; 2452 else if (property == intel_sdvo_connector->dot_crawl) 2453 sdvo_state->tv.dot_crawl = val; 2454 else 2455 return intel_digital_connector_atomic_set_property(connector, state, property, val); 2456 2457 return 0; 2458 } 2459 2460 static struct drm_connector_state * 2461 intel_sdvo_connector_duplicate_state(struct drm_connector *connector) 2462 { 2463 struct intel_sdvo_connector_state *state; 2464 2465 state = kmemdup(connector->state, sizeof(*state), GFP_KERNEL); 2466 if (!state) 2467 return NULL; 2468 2469 __drm_atomic_helper_connector_duplicate_state(connector, &state->base.base); 2470 return &state->base.base; 2471 } 2472 2473 static const struct drm_connector_funcs intel_sdvo_connector_funcs = { 2474 .detect = intel_sdvo_detect, 2475 .fill_modes = drm_helper_probe_single_connector_modes, 2476 .atomic_get_property = intel_sdvo_connector_atomic_get_property, 2477 .atomic_set_property = intel_sdvo_connector_atomic_set_property, 2478 .late_register = intel_connector_register, 2479 .early_unregister = intel_connector_unregister, 2480 .destroy = intel_connector_destroy, 2481 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 2482 .atomic_duplicate_state = intel_sdvo_connector_duplicate_state, 2483 }; 2484 2485 static int intel_sdvo_atomic_check(struct drm_connector *conn, 2486 struct drm_atomic_state *state) 2487 { 2488 struct drm_connector_state *new_conn_state = 2489 drm_atomic_get_new_connector_state(state, conn); 2490 struct drm_connector_state *old_conn_state = 2491 drm_atomic_get_old_connector_state(state, conn); 2492 struct intel_sdvo_connector_state *old_state = 2493 to_intel_sdvo_connector_state(old_conn_state); 2494 struct intel_sdvo_connector_state *new_state = 2495 to_intel_sdvo_connector_state(new_conn_state); 2496 2497 if (new_conn_state->crtc && 2498 (memcmp(&old_state->tv, &new_state->tv, sizeof(old_state->tv)) || 2499 memcmp(&old_conn_state->tv, &new_conn_state->tv, sizeof(old_conn_state->tv)))) { 2500 struct drm_crtc_state *crtc_state = 2501 drm_atomic_get_new_crtc_state(state, 2502 new_conn_state->crtc); 2503 2504 crtc_state->connectors_changed = true; 2505 } 2506 2507 return intel_digital_connector_atomic_check(conn, state); 2508 } 2509 2510 static const struct drm_connector_helper_funcs intel_sdvo_connector_helper_funcs = { 2511 .get_modes = intel_sdvo_get_modes, 2512 .mode_valid = intel_sdvo_mode_valid, 2513 .atomic_check = intel_sdvo_atomic_check, 2514 }; 2515 2516 static void intel_sdvo_encoder_destroy(struct drm_encoder *_encoder) 2517 { 2518 struct intel_encoder *encoder = to_intel_encoder(_encoder); 2519 struct intel_sdvo *sdvo = to_sdvo(encoder); 2520 int i; 2521 2522 for (i = 0; i < ARRAY_SIZE(sdvo->ddc); i++) { 2523 if (sdvo->ddc[i].ddc_bus) 2524 i2c_del_adapter(&sdvo->ddc[i].ddc); 2525 } 2526 2527 drm_encoder_cleanup(&encoder->base); 2528 kfree(sdvo); 2529 }; 2530 2531 static const struct drm_encoder_funcs intel_sdvo_enc_funcs = { 2532 .destroy = intel_sdvo_encoder_destroy, 2533 }; 2534 2535 static int 2536 intel_sdvo_guess_ddc_bus(struct intel_sdvo *sdvo, 2537 struct intel_sdvo_connector *connector) 2538 { 2539 u16 mask = 0; 2540 int num_bits; 2541 2542 /* 2543 * Make a mask of outputs less than or equal to our own priority in the 2544 * list. 2545 */ 2546 switch (connector->output_flag) { 2547 case SDVO_OUTPUT_LVDS1: 2548 mask |= SDVO_OUTPUT_LVDS1; 2549 fallthrough; 2550 case SDVO_OUTPUT_LVDS0: 2551 mask |= SDVO_OUTPUT_LVDS0; 2552 fallthrough; 2553 case SDVO_OUTPUT_TMDS1: 2554 mask |= SDVO_OUTPUT_TMDS1; 2555 fallthrough; 2556 case SDVO_OUTPUT_TMDS0: 2557 mask |= SDVO_OUTPUT_TMDS0; 2558 fallthrough; 2559 case SDVO_OUTPUT_RGB1: 2560 mask |= SDVO_OUTPUT_RGB1; 2561 fallthrough; 2562 case SDVO_OUTPUT_RGB0: 2563 mask |= SDVO_OUTPUT_RGB0; 2564 break; 2565 } 2566 2567 /* Count bits to find what number we are in the priority list. */ 2568 mask &= sdvo->caps.output_flags; 2569 num_bits = hweight16(mask); 2570 /* If more than 3 outputs, default to DDC bus 3 for now. */ 2571 if (num_bits > 3) 2572 num_bits = 3; 2573 2574 /* Corresponds to SDVO_CONTROL_BUS_DDCx */ 2575 return num_bits; 2576 } 2577 2578 /* 2579 * Choose the appropriate DDC bus for control bus switch command for this 2580 * SDVO output based on the controlled output. 2581 * 2582 * DDC bus number assignment is in a priority order of RGB outputs, then TMDS 2583 * outputs, then LVDS outputs. 2584 */ 2585 static struct intel_sdvo_ddc * 2586 intel_sdvo_select_ddc_bus(struct intel_sdvo *sdvo, 2587 struct intel_sdvo_connector *connector) 2588 { 2589 struct drm_i915_private *dev_priv = to_i915(sdvo->base.base.dev); 2590 const struct sdvo_device_mapping *mapping; 2591 int ddc_bus; 2592 2593 if (sdvo->base.port == PORT_B) 2594 mapping = &dev_priv->display.vbt.sdvo_mappings[0]; 2595 else 2596 mapping = &dev_priv->display.vbt.sdvo_mappings[1]; 2597 2598 if (mapping->initialized) 2599 ddc_bus = (mapping->ddc_pin & 0xf0) >> 4; 2600 else 2601 ddc_bus = intel_sdvo_guess_ddc_bus(sdvo, connector); 2602 2603 if (ddc_bus < 1 || ddc_bus > 3) 2604 return NULL; 2605 2606 return &sdvo->ddc[ddc_bus - 1]; 2607 } 2608 2609 static void 2610 intel_sdvo_select_i2c_bus(struct intel_sdvo *sdvo) 2611 { 2612 struct drm_i915_private *dev_priv = to_i915(sdvo->base.base.dev); 2613 const struct sdvo_device_mapping *mapping; 2614 u8 pin; 2615 2616 if (sdvo->base.port == PORT_B) 2617 mapping = &dev_priv->display.vbt.sdvo_mappings[0]; 2618 else 2619 mapping = &dev_priv->display.vbt.sdvo_mappings[1]; 2620 2621 if (mapping->initialized && 2622 intel_gmbus_is_valid_pin(dev_priv, mapping->i2c_pin)) 2623 pin = mapping->i2c_pin; 2624 else 2625 pin = GMBUS_PIN_DPB; 2626 2627 drm_dbg_kms(&dev_priv->drm, "[ENCODER:%d:%s] I2C pin %d, slave addr 0x%x\n", 2628 sdvo->base.base.base.id, sdvo->base.base.name, 2629 pin, sdvo->slave_addr); 2630 2631 sdvo->i2c = intel_gmbus_get_adapter(dev_priv, pin); 2632 2633 /* 2634 * With gmbus we should be able to drive sdvo i2c at 2MHz, but somehow 2635 * our code totally fails once we start using gmbus. Hence fall back to 2636 * bit banging for now. 2637 */ 2638 intel_gmbus_force_bit(sdvo->i2c, true); 2639 } 2640 2641 /* undo any changes intel_sdvo_select_i2c_bus() did to sdvo->i2c */ 2642 static void 2643 intel_sdvo_unselect_i2c_bus(struct intel_sdvo *sdvo) 2644 { 2645 intel_gmbus_force_bit(sdvo->i2c, false); 2646 } 2647 2648 static bool 2649 intel_sdvo_is_hdmi_connector(struct intel_sdvo *intel_sdvo) 2650 { 2651 return intel_sdvo_check_supp_encode(intel_sdvo); 2652 } 2653 2654 static u8 2655 intel_sdvo_get_slave_addr(struct intel_sdvo *sdvo) 2656 { 2657 struct drm_i915_private *dev_priv = to_i915(sdvo->base.base.dev); 2658 const struct sdvo_device_mapping *my_mapping, *other_mapping; 2659 2660 if (sdvo->base.port == PORT_B) { 2661 my_mapping = &dev_priv->display.vbt.sdvo_mappings[0]; 2662 other_mapping = &dev_priv->display.vbt.sdvo_mappings[1]; 2663 } else { 2664 my_mapping = &dev_priv->display.vbt.sdvo_mappings[1]; 2665 other_mapping = &dev_priv->display.vbt.sdvo_mappings[0]; 2666 } 2667 2668 /* If the BIOS described our SDVO device, take advantage of it. */ 2669 if (my_mapping->slave_addr) 2670 return my_mapping->slave_addr; 2671 2672 /* 2673 * If the BIOS only described a different SDVO device, use the 2674 * address that it isn't using. 2675 */ 2676 if (other_mapping->slave_addr) { 2677 if (other_mapping->slave_addr == 0x70) 2678 return 0x72; 2679 else 2680 return 0x70; 2681 } 2682 2683 /* 2684 * No SDVO device info is found for another DVO port, 2685 * so use mapping assumption we had before BIOS parsing. 2686 */ 2687 if (sdvo->base.port == PORT_B) 2688 return 0x70; 2689 else 2690 return 0x72; 2691 } 2692 2693 static int 2694 intel_sdvo_init_ddc_proxy(struct intel_sdvo_ddc *ddc, 2695 struct intel_sdvo *sdvo, int bit); 2696 2697 static int 2698 intel_sdvo_connector_init(struct intel_sdvo_connector *connector, 2699 struct intel_sdvo *encoder) 2700 { 2701 struct drm_i915_private *i915 = to_i915(encoder->base.base.dev); 2702 struct intel_sdvo_ddc *ddc = NULL; 2703 int ret; 2704 2705 if (HAS_DDC(connector)) 2706 ddc = intel_sdvo_select_ddc_bus(encoder, connector); 2707 2708 ret = drm_connector_init_with_ddc(encoder->base.base.dev, 2709 &connector->base.base, 2710 &intel_sdvo_connector_funcs, 2711 connector->base.base.connector_type, 2712 ddc ? &ddc->ddc : NULL); 2713 if (ret < 0) 2714 return ret; 2715 2716 drm_connector_helper_add(&connector->base.base, 2717 &intel_sdvo_connector_helper_funcs); 2718 2719 connector->base.base.display_info.subpixel_order = SubPixelHorizontalRGB; 2720 connector->base.base.interlace_allowed = true; 2721 connector->base.get_hw_state = intel_sdvo_connector_get_hw_state; 2722 2723 intel_connector_attach_encoder(&connector->base, &encoder->base); 2724 2725 if (ddc) 2726 drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s] using %s\n", 2727 connector->base.base.base.id, connector->base.base.name, 2728 ddc->ddc.name); 2729 2730 return 0; 2731 } 2732 2733 static void 2734 intel_sdvo_add_hdmi_properties(struct intel_sdvo *intel_sdvo, 2735 struct intel_sdvo_connector *connector) 2736 { 2737 intel_attach_force_audio_property(&connector->base.base); 2738 if (intel_sdvo->colorimetry_cap & SDVO_COLORIMETRY_RGB220) 2739 intel_attach_broadcast_rgb_property(&connector->base.base); 2740 intel_attach_aspect_ratio_property(&connector->base.base); 2741 } 2742 2743 static struct intel_sdvo_connector *intel_sdvo_connector_alloc(void) 2744 { 2745 struct intel_sdvo_connector *sdvo_connector; 2746 struct intel_sdvo_connector_state *conn_state; 2747 2748 sdvo_connector = kzalloc(sizeof(*sdvo_connector), GFP_KERNEL); 2749 if (!sdvo_connector) 2750 return NULL; 2751 2752 conn_state = kzalloc(sizeof(*conn_state), GFP_KERNEL); 2753 if (!conn_state) { 2754 kfree(sdvo_connector); 2755 return NULL; 2756 } 2757 2758 __drm_atomic_helper_connector_reset(&sdvo_connector->base.base, 2759 &conn_state->base.base); 2760 2761 intel_panel_init_alloc(&sdvo_connector->base); 2762 2763 return sdvo_connector; 2764 } 2765 2766 static bool 2767 intel_sdvo_dvi_init(struct intel_sdvo *intel_sdvo, u16 type) 2768 { 2769 struct drm_encoder *encoder = &intel_sdvo->base.base; 2770 struct drm_connector *connector; 2771 struct intel_encoder *intel_encoder = to_intel_encoder(encoder); 2772 struct intel_connector *intel_connector; 2773 struct intel_sdvo_connector *intel_sdvo_connector; 2774 2775 DRM_DEBUG_KMS("initialising DVI type 0x%x\n", type); 2776 2777 intel_sdvo_connector = intel_sdvo_connector_alloc(); 2778 if (!intel_sdvo_connector) 2779 return false; 2780 2781 intel_sdvo_connector->output_flag = type; 2782 2783 intel_connector = &intel_sdvo_connector->base; 2784 connector = &intel_connector->base; 2785 if (intel_sdvo_get_hotplug_support(intel_sdvo) & 2786 intel_sdvo_connector->output_flag) { 2787 intel_sdvo->hotplug_active |= intel_sdvo_connector->output_flag; 2788 /* 2789 * Some SDVO devices have one-shot hotplug interrupts. 2790 * Ensure that they get re-enabled when an interrupt happens. 2791 */ 2792 intel_connector->polled = DRM_CONNECTOR_POLL_HPD; 2793 intel_encoder->hotplug = intel_sdvo_hotplug; 2794 intel_sdvo_enable_hotplug(intel_encoder); 2795 } else { 2796 intel_connector->polled = DRM_CONNECTOR_POLL_CONNECT | DRM_CONNECTOR_POLL_DISCONNECT; 2797 } 2798 encoder->encoder_type = DRM_MODE_ENCODER_TMDS; 2799 connector->connector_type = DRM_MODE_CONNECTOR_DVID; 2800 2801 if (intel_sdvo_is_hdmi_connector(intel_sdvo)) { 2802 connector->connector_type = DRM_MODE_CONNECTOR_HDMIA; 2803 intel_sdvo_connector->is_hdmi = true; 2804 } 2805 2806 if (intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo) < 0) { 2807 kfree(intel_sdvo_connector); 2808 return false; 2809 } 2810 2811 if (intel_sdvo_connector->is_hdmi) 2812 intel_sdvo_add_hdmi_properties(intel_sdvo, intel_sdvo_connector); 2813 2814 return true; 2815 } 2816 2817 static bool 2818 intel_sdvo_tv_init(struct intel_sdvo *intel_sdvo, u16 type) 2819 { 2820 struct drm_encoder *encoder = &intel_sdvo->base.base; 2821 struct drm_connector *connector; 2822 struct intel_connector *intel_connector; 2823 struct intel_sdvo_connector *intel_sdvo_connector; 2824 2825 DRM_DEBUG_KMS("initialising TV type 0x%x\n", type); 2826 2827 intel_sdvo_connector = intel_sdvo_connector_alloc(); 2828 if (!intel_sdvo_connector) 2829 return false; 2830 2831 intel_connector = &intel_sdvo_connector->base; 2832 connector = &intel_connector->base; 2833 encoder->encoder_type = DRM_MODE_ENCODER_TVDAC; 2834 connector->connector_type = DRM_MODE_CONNECTOR_SVIDEO; 2835 2836 intel_sdvo_connector->output_flag = type; 2837 2838 if (intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo) < 0) { 2839 kfree(intel_sdvo_connector); 2840 return false; 2841 } 2842 2843 if (!intel_sdvo_tv_create_property(intel_sdvo, intel_sdvo_connector, type)) 2844 goto err; 2845 2846 if (!intel_sdvo_create_enhance_property(intel_sdvo, intel_sdvo_connector)) 2847 goto err; 2848 2849 return true; 2850 2851 err: 2852 intel_connector_destroy(connector); 2853 return false; 2854 } 2855 2856 static bool 2857 intel_sdvo_analog_init(struct intel_sdvo *intel_sdvo, u16 type) 2858 { 2859 struct drm_encoder *encoder = &intel_sdvo->base.base; 2860 struct drm_connector *connector; 2861 struct intel_connector *intel_connector; 2862 struct intel_sdvo_connector *intel_sdvo_connector; 2863 2864 DRM_DEBUG_KMS("initialising analog type 0x%x\n", type); 2865 2866 intel_sdvo_connector = intel_sdvo_connector_alloc(); 2867 if (!intel_sdvo_connector) 2868 return false; 2869 2870 intel_connector = &intel_sdvo_connector->base; 2871 connector = &intel_connector->base; 2872 intel_connector->polled = DRM_CONNECTOR_POLL_CONNECT; 2873 encoder->encoder_type = DRM_MODE_ENCODER_DAC; 2874 connector->connector_type = DRM_MODE_CONNECTOR_VGA; 2875 2876 intel_sdvo_connector->output_flag = type; 2877 2878 if (intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo) < 0) { 2879 kfree(intel_sdvo_connector); 2880 return false; 2881 } 2882 2883 return true; 2884 } 2885 2886 static bool 2887 intel_sdvo_lvds_init(struct intel_sdvo *intel_sdvo, u16 type) 2888 { 2889 struct drm_encoder *encoder = &intel_sdvo->base.base; 2890 struct drm_i915_private *i915 = to_i915(encoder->dev); 2891 struct drm_connector *connector; 2892 struct intel_connector *intel_connector; 2893 struct intel_sdvo_connector *intel_sdvo_connector; 2894 2895 DRM_DEBUG_KMS("initialising LVDS type 0x%x\n", type); 2896 2897 intel_sdvo_connector = intel_sdvo_connector_alloc(); 2898 if (!intel_sdvo_connector) 2899 return false; 2900 2901 intel_connector = &intel_sdvo_connector->base; 2902 connector = &intel_connector->base; 2903 encoder->encoder_type = DRM_MODE_ENCODER_LVDS; 2904 connector->connector_type = DRM_MODE_CONNECTOR_LVDS; 2905 2906 intel_sdvo_connector->output_flag = type; 2907 2908 if (intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo) < 0) { 2909 kfree(intel_sdvo_connector); 2910 return false; 2911 } 2912 2913 if (!intel_sdvo_create_enhance_property(intel_sdvo, intel_sdvo_connector)) 2914 goto err; 2915 2916 intel_bios_init_panel_late(i915, &intel_connector->panel, NULL, NULL); 2917 2918 /* 2919 * Fetch modes from VBT. For SDVO prefer the VBT mode since some 2920 * SDVO->LVDS transcoders can't cope with the EDID mode. 2921 */ 2922 intel_panel_add_vbt_sdvo_fixed_mode(intel_connector); 2923 2924 if (!intel_panel_preferred_fixed_mode(intel_connector)) { 2925 mutex_lock(&i915->drm.mode_config.mutex); 2926 2927 intel_ddc_get_modes(connector, connector->ddc); 2928 intel_panel_add_edid_fixed_modes(intel_connector, false); 2929 2930 mutex_unlock(&i915->drm.mode_config.mutex); 2931 } 2932 2933 intel_panel_init(intel_connector, NULL); 2934 2935 if (!intel_panel_preferred_fixed_mode(intel_connector)) 2936 goto err; 2937 2938 return true; 2939 2940 err: 2941 intel_connector_destroy(connector); 2942 return false; 2943 } 2944 2945 static u16 intel_sdvo_filter_output_flags(u16 flags) 2946 { 2947 flags &= SDVO_OUTPUT_MASK; 2948 2949 /* SDVO requires XXX1 function may not exist unless it has XXX0 function.*/ 2950 if (!(flags & SDVO_OUTPUT_TMDS0)) 2951 flags &= ~SDVO_OUTPUT_TMDS1; 2952 2953 if (!(flags & SDVO_OUTPUT_RGB0)) 2954 flags &= ~SDVO_OUTPUT_RGB1; 2955 2956 if (!(flags & SDVO_OUTPUT_LVDS0)) 2957 flags &= ~SDVO_OUTPUT_LVDS1; 2958 2959 return flags; 2960 } 2961 2962 static bool intel_sdvo_output_init(struct intel_sdvo *sdvo, u16 type) 2963 { 2964 if (type & SDVO_TMDS_MASK) 2965 return intel_sdvo_dvi_init(sdvo, type); 2966 else if (type & SDVO_TV_MASK) 2967 return intel_sdvo_tv_init(sdvo, type); 2968 else if (type & SDVO_RGB_MASK) 2969 return intel_sdvo_analog_init(sdvo, type); 2970 else if (type & SDVO_LVDS_MASK) 2971 return intel_sdvo_lvds_init(sdvo, type); 2972 else 2973 return false; 2974 } 2975 2976 static bool 2977 intel_sdvo_output_setup(struct intel_sdvo *intel_sdvo) 2978 { 2979 static const u16 probe_order[] = { 2980 SDVO_OUTPUT_TMDS0, 2981 SDVO_OUTPUT_TMDS1, 2982 /* TV has no XXX1 function block */ 2983 SDVO_OUTPUT_SVID0, 2984 SDVO_OUTPUT_CVBS0, 2985 SDVO_OUTPUT_YPRPB0, 2986 SDVO_OUTPUT_RGB0, 2987 SDVO_OUTPUT_RGB1, 2988 SDVO_OUTPUT_LVDS0, 2989 SDVO_OUTPUT_LVDS1, 2990 }; 2991 u16 flags; 2992 int i; 2993 2994 flags = intel_sdvo_filter_output_flags(intel_sdvo->caps.output_flags); 2995 2996 if (flags == 0) { 2997 DRM_DEBUG_KMS("%s: Unknown SDVO output type (0x%04x)\n", 2998 SDVO_NAME(intel_sdvo), intel_sdvo->caps.output_flags); 2999 return false; 3000 } 3001 3002 for (i = 0; i < ARRAY_SIZE(probe_order); i++) { 3003 u16 type = flags & probe_order[i]; 3004 3005 if (!type) 3006 continue; 3007 3008 if (!intel_sdvo_output_init(intel_sdvo, type)) 3009 return false; 3010 } 3011 3012 intel_sdvo->base.pipe_mask = ~0; 3013 3014 return true; 3015 } 3016 3017 static void intel_sdvo_output_cleanup(struct intel_sdvo *intel_sdvo) 3018 { 3019 struct drm_device *dev = intel_sdvo->base.base.dev; 3020 struct drm_connector *connector, *tmp; 3021 3022 list_for_each_entry_safe(connector, tmp, 3023 &dev->mode_config.connector_list, head) { 3024 if (intel_attached_encoder(to_intel_connector(connector)) == &intel_sdvo->base) { 3025 drm_connector_unregister(connector); 3026 intel_connector_destroy(connector); 3027 } 3028 } 3029 } 3030 3031 static bool intel_sdvo_tv_create_property(struct intel_sdvo *intel_sdvo, 3032 struct intel_sdvo_connector *intel_sdvo_connector, 3033 int type) 3034 { 3035 struct drm_device *dev = intel_sdvo->base.base.dev; 3036 struct intel_sdvo_tv_format format; 3037 u32 format_map, i; 3038 3039 if (!intel_sdvo_set_target_output(intel_sdvo, type)) 3040 return false; 3041 3042 BUILD_BUG_ON(sizeof(format) != 6); 3043 if (!intel_sdvo_get_value(intel_sdvo, 3044 SDVO_CMD_GET_SUPPORTED_TV_FORMATS, 3045 &format, sizeof(format))) 3046 return false; 3047 3048 memcpy(&format_map, &format, min(sizeof(format_map), sizeof(format))); 3049 3050 if (format_map == 0) 3051 return false; 3052 3053 intel_sdvo_connector->format_supported_num = 0; 3054 for (i = 0 ; i < TV_FORMAT_NUM; i++) 3055 if (format_map & (1 << i)) 3056 intel_sdvo_connector->tv_format_supported[intel_sdvo_connector->format_supported_num++] = i; 3057 3058 3059 intel_sdvo_connector->tv_format = 3060 drm_property_create(dev, DRM_MODE_PROP_ENUM, 3061 "mode", intel_sdvo_connector->format_supported_num); 3062 if (!intel_sdvo_connector->tv_format) 3063 return false; 3064 3065 for (i = 0; i < intel_sdvo_connector->format_supported_num; i++) 3066 drm_property_add_enum(intel_sdvo_connector->tv_format, i, 3067 tv_format_names[intel_sdvo_connector->tv_format_supported[i]]); 3068 3069 intel_sdvo_connector->base.base.state->tv.mode = intel_sdvo_connector->tv_format_supported[0]; 3070 drm_object_attach_property(&intel_sdvo_connector->base.base.base, 3071 intel_sdvo_connector->tv_format, 0); 3072 return true; 3073 3074 } 3075 3076 #define _ENHANCEMENT(state_assignment, name, NAME) do { \ 3077 if (enhancements.name) { \ 3078 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_MAX_##NAME, &data_value, 4) || \ 3079 !intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_##NAME, &response, 2)) \ 3080 return false; \ 3081 intel_sdvo_connector->name = \ 3082 drm_property_create_range(dev, 0, #name, 0, data_value[0]); \ 3083 if (!intel_sdvo_connector->name) return false; \ 3084 state_assignment = response; \ 3085 drm_object_attach_property(&connector->base, \ 3086 intel_sdvo_connector->name, 0); \ 3087 DRM_DEBUG_KMS(#name ": max %d, default %d, current %d\n", \ 3088 data_value[0], data_value[1], response); \ 3089 } \ 3090 } while (0) 3091 3092 #define ENHANCEMENT(state, name, NAME) _ENHANCEMENT((state)->name, name, NAME) 3093 3094 static bool 3095 intel_sdvo_create_enhance_property_tv(struct intel_sdvo *intel_sdvo, 3096 struct intel_sdvo_connector *intel_sdvo_connector, 3097 struct intel_sdvo_enhancements_reply enhancements) 3098 { 3099 struct drm_device *dev = intel_sdvo->base.base.dev; 3100 struct drm_connector *connector = &intel_sdvo_connector->base.base; 3101 struct drm_connector_state *conn_state = connector->state; 3102 struct intel_sdvo_connector_state *sdvo_state = 3103 to_intel_sdvo_connector_state(conn_state); 3104 u16 response, data_value[2]; 3105 3106 /* when horizontal overscan is supported, Add the left/right property */ 3107 if (enhancements.overscan_h) { 3108 if (!intel_sdvo_get_value(intel_sdvo, 3109 SDVO_CMD_GET_MAX_OVERSCAN_H, 3110 &data_value, 4)) 3111 return false; 3112 3113 if (!intel_sdvo_get_value(intel_sdvo, 3114 SDVO_CMD_GET_OVERSCAN_H, 3115 &response, 2)) 3116 return false; 3117 3118 sdvo_state->tv.overscan_h = response; 3119 3120 intel_sdvo_connector->max_hscan = data_value[0]; 3121 intel_sdvo_connector->left = 3122 drm_property_create_range(dev, 0, "left_margin", 0, data_value[0]); 3123 if (!intel_sdvo_connector->left) 3124 return false; 3125 3126 drm_object_attach_property(&connector->base, 3127 intel_sdvo_connector->left, 0); 3128 3129 intel_sdvo_connector->right = 3130 drm_property_create_range(dev, 0, "right_margin", 0, data_value[0]); 3131 if (!intel_sdvo_connector->right) 3132 return false; 3133 3134 drm_object_attach_property(&connector->base, 3135 intel_sdvo_connector->right, 0); 3136 DRM_DEBUG_KMS("h_overscan: max %d, " 3137 "default %d, current %d\n", 3138 data_value[0], data_value[1], response); 3139 } 3140 3141 if (enhancements.overscan_v) { 3142 if (!intel_sdvo_get_value(intel_sdvo, 3143 SDVO_CMD_GET_MAX_OVERSCAN_V, 3144 &data_value, 4)) 3145 return false; 3146 3147 if (!intel_sdvo_get_value(intel_sdvo, 3148 SDVO_CMD_GET_OVERSCAN_V, 3149 &response, 2)) 3150 return false; 3151 3152 sdvo_state->tv.overscan_v = response; 3153 3154 intel_sdvo_connector->max_vscan = data_value[0]; 3155 intel_sdvo_connector->top = 3156 drm_property_create_range(dev, 0, 3157 "top_margin", 0, data_value[0]); 3158 if (!intel_sdvo_connector->top) 3159 return false; 3160 3161 drm_object_attach_property(&connector->base, 3162 intel_sdvo_connector->top, 0); 3163 3164 intel_sdvo_connector->bottom = 3165 drm_property_create_range(dev, 0, 3166 "bottom_margin", 0, data_value[0]); 3167 if (!intel_sdvo_connector->bottom) 3168 return false; 3169 3170 drm_object_attach_property(&connector->base, 3171 intel_sdvo_connector->bottom, 0); 3172 DRM_DEBUG_KMS("v_overscan: max %d, " 3173 "default %d, current %d\n", 3174 data_value[0], data_value[1], response); 3175 } 3176 3177 ENHANCEMENT(&sdvo_state->tv, hpos, HPOS); 3178 ENHANCEMENT(&sdvo_state->tv, vpos, VPOS); 3179 ENHANCEMENT(&conn_state->tv, saturation, SATURATION); 3180 ENHANCEMENT(&conn_state->tv, contrast, CONTRAST); 3181 ENHANCEMENT(&conn_state->tv, hue, HUE); 3182 ENHANCEMENT(&conn_state->tv, brightness, BRIGHTNESS); 3183 ENHANCEMENT(&sdvo_state->tv, sharpness, SHARPNESS); 3184 ENHANCEMENT(&sdvo_state->tv, flicker_filter, FLICKER_FILTER); 3185 ENHANCEMENT(&sdvo_state->tv, flicker_filter_adaptive, FLICKER_FILTER_ADAPTIVE); 3186 ENHANCEMENT(&sdvo_state->tv, flicker_filter_2d, FLICKER_FILTER_2D); 3187 _ENHANCEMENT(sdvo_state->tv.chroma_filter, tv_chroma_filter, TV_CHROMA_FILTER); 3188 _ENHANCEMENT(sdvo_state->tv.luma_filter, tv_luma_filter, TV_LUMA_FILTER); 3189 3190 if (enhancements.dot_crawl) { 3191 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_DOT_CRAWL, &response, 2)) 3192 return false; 3193 3194 sdvo_state->tv.dot_crawl = response & 0x1; 3195 intel_sdvo_connector->dot_crawl = 3196 drm_property_create_range(dev, 0, "dot_crawl", 0, 1); 3197 if (!intel_sdvo_connector->dot_crawl) 3198 return false; 3199 3200 drm_object_attach_property(&connector->base, 3201 intel_sdvo_connector->dot_crawl, 0); 3202 DRM_DEBUG_KMS("dot crawl: current %d\n", response); 3203 } 3204 3205 return true; 3206 } 3207 3208 static bool 3209 intel_sdvo_create_enhance_property_lvds(struct intel_sdvo *intel_sdvo, 3210 struct intel_sdvo_connector *intel_sdvo_connector, 3211 struct intel_sdvo_enhancements_reply enhancements) 3212 { 3213 struct drm_device *dev = intel_sdvo->base.base.dev; 3214 struct drm_connector *connector = &intel_sdvo_connector->base.base; 3215 u16 response, data_value[2]; 3216 3217 ENHANCEMENT(&connector->state->tv, brightness, BRIGHTNESS); 3218 3219 return true; 3220 } 3221 #undef ENHANCEMENT 3222 #undef _ENHANCEMENT 3223 3224 static bool intel_sdvo_create_enhance_property(struct intel_sdvo *intel_sdvo, 3225 struct intel_sdvo_connector *intel_sdvo_connector) 3226 { 3227 union { 3228 struct intel_sdvo_enhancements_reply reply; 3229 u16 response; 3230 } enhancements; 3231 3232 BUILD_BUG_ON(sizeof(enhancements) != 2); 3233 3234 if (!intel_sdvo_get_value(intel_sdvo, 3235 SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS, 3236 &enhancements, sizeof(enhancements)) || 3237 enhancements.response == 0) { 3238 DRM_DEBUG_KMS("No enhancement is supported\n"); 3239 return true; 3240 } 3241 3242 if (IS_TV(intel_sdvo_connector)) 3243 return intel_sdvo_create_enhance_property_tv(intel_sdvo, intel_sdvo_connector, enhancements.reply); 3244 else if (IS_LVDS(intel_sdvo_connector)) 3245 return intel_sdvo_create_enhance_property_lvds(intel_sdvo, intel_sdvo_connector, enhancements.reply); 3246 else 3247 return true; 3248 } 3249 3250 static int intel_sdvo_ddc_proxy_xfer(struct i2c_adapter *adapter, 3251 struct i2c_msg *msgs, 3252 int num) 3253 { 3254 struct intel_sdvo_ddc *ddc = adapter->algo_data; 3255 struct intel_sdvo *sdvo = ddc->sdvo; 3256 3257 if (!__intel_sdvo_set_control_bus_switch(sdvo, 1 << ddc->ddc_bus)) 3258 return -EIO; 3259 3260 return sdvo->i2c->algo->master_xfer(sdvo->i2c, msgs, num); 3261 } 3262 3263 static u32 intel_sdvo_ddc_proxy_func(struct i2c_adapter *adapter) 3264 { 3265 struct intel_sdvo_ddc *ddc = adapter->algo_data; 3266 struct intel_sdvo *sdvo = ddc->sdvo; 3267 3268 return sdvo->i2c->algo->functionality(sdvo->i2c); 3269 } 3270 3271 static const struct i2c_algorithm intel_sdvo_ddc_proxy = { 3272 .master_xfer = intel_sdvo_ddc_proxy_xfer, 3273 .functionality = intel_sdvo_ddc_proxy_func 3274 }; 3275 3276 static void proxy_lock_bus(struct i2c_adapter *adapter, 3277 unsigned int flags) 3278 { 3279 struct intel_sdvo_ddc *ddc = adapter->algo_data; 3280 struct intel_sdvo *sdvo = ddc->sdvo; 3281 3282 sdvo->i2c->lock_ops->lock_bus(sdvo->i2c, flags); 3283 } 3284 3285 static int proxy_trylock_bus(struct i2c_adapter *adapter, 3286 unsigned int flags) 3287 { 3288 struct intel_sdvo_ddc *ddc = adapter->algo_data; 3289 struct intel_sdvo *sdvo = ddc->sdvo; 3290 3291 return sdvo->i2c->lock_ops->trylock_bus(sdvo->i2c, flags); 3292 } 3293 3294 static void proxy_unlock_bus(struct i2c_adapter *adapter, 3295 unsigned int flags) 3296 { 3297 struct intel_sdvo_ddc *ddc = adapter->algo_data; 3298 struct intel_sdvo *sdvo = ddc->sdvo; 3299 3300 sdvo->i2c->lock_ops->unlock_bus(sdvo->i2c, flags); 3301 } 3302 3303 static const struct i2c_lock_operations proxy_lock_ops = { 3304 .lock_bus = proxy_lock_bus, 3305 .trylock_bus = proxy_trylock_bus, 3306 .unlock_bus = proxy_unlock_bus, 3307 }; 3308 3309 static int 3310 intel_sdvo_init_ddc_proxy(struct intel_sdvo_ddc *ddc, 3311 struct intel_sdvo *sdvo, int ddc_bus) 3312 { 3313 struct drm_i915_private *dev_priv = to_i915(sdvo->base.base.dev); 3314 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); 3315 3316 ddc->sdvo = sdvo; 3317 ddc->ddc_bus = ddc_bus; 3318 3319 ddc->ddc.owner = THIS_MODULE; 3320 ddc->ddc.class = I2C_CLASS_DDC; 3321 snprintf(ddc->ddc.name, I2C_NAME_SIZE, "SDVO %c DDC%d", 3322 port_name(sdvo->base.port), ddc_bus); 3323 ddc->ddc.dev.parent = &pdev->dev; 3324 ddc->ddc.algo_data = ddc; 3325 ddc->ddc.algo = &intel_sdvo_ddc_proxy; 3326 ddc->ddc.lock_ops = &proxy_lock_ops; 3327 3328 return i2c_add_adapter(&ddc->ddc); 3329 } 3330 3331 static bool is_sdvo_port_valid(struct drm_i915_private *dev_priv, enum port port) 3332 { 3333 if (HAS_PCH_SPLIT(dev_priv)) 3334 return port == PORT_B; 3335 else 3336 return port == PORT_B || port == PORT_C; 3337 } 3338 3339 static bool assert_sdvo_port_valid(struct drm_i915_private *dev_priv, 3340 enum port port) 3341 { 3342 return !drm_WARN(&dev_priv->drm, !is_sdvo_port_valid(dev_priv, port), 3343 "Platform does not support SDVO %c\n", port_name(port)); 3344 } 3345 3346 bool intel_sdvo_init(struct drm_i915_private *dev_priv, 3347 i915_reg_t sdvo_reg, enum port port) 3348 { 3349 struct intel_encoder *intel_encoder; 3350 struct intel_sdvo *intel_sdvo; 3351 int i; 3352 3353 if (!assert_port_valid(dev_priv, port)) 3354 return false; 3355 3356 if (!assert_sdvo_port_valid(dev_priv, port)) 3357 return false; 3358 3359 intel_sdvo = kzalloc(sizeof(*intel_sdvo), GFP_KERNEL); 3360 if (!intel_sdvo) 3361 return false; 3362 3363 /* encoder type will be decided later */ 3364 intel_encoder = &intel_sdvo->base; 3365 intel_encoder->type = INTEL_OUTPUT_SDVO; 3366 intel_encoder->power_domain = POWER_DOMAIN_PORT_OTHER; 3367 intel_encoder->port = port; 3368 3369 drm_encoder_init(&dev_priv->drm, &intel_encoder->base, 3370 &intel_sdvo_enc_funcs, 0, 3371 "SDVO %c", port_name(port)); 3372 3373 intel_sdvo->sdvo_reg = sdvo_reg; 3374 intel_sdvo->slave_addr = intel_sdvo_get_slave_addr(intel_sdvo) >> 1; 3375 3376 intel_sdvo_select_i2c_bus(intel_sdvo); 3377 3378 /* Read the regs to test if we can talk to the device */ 3379 for (i = 0; i < 0x40; i++) { 3380 u8 byte; 3381 3382 if (!intel_sdvo_read_byte(intel_sdvo, i, &byte)) { 3383 drm_dbg_kms(&dev_priv->drm, 3384 "No SDVO device found on %s\n", 3385 SDVO_NAME(intel_sdvo)); 3386 goto err; 3387 } 3388 } 3389 3390 intel_encoder->compute_config = intel_sdvo_compute_config; 3391 if (HAS_PCH_SPLIT(dev_priv)) { 3392 intel_encoder->disable = pch_disable_sdvo; 3393 intel_encoder->post_disable = pch_post_disable_sdvo; 3394 } else { 3395 intel_encoder->disable = intel_disable_sdvo; 3396 } 3397 intel_encoder->pre_enable = intel_sdvo_pre_enable; 3398 intel_encoder->enable = intel_enable_sdvo; 3399 intel_encoder->get_hw_state = intel_sdvo_get_hw_state; 3400 intel_encoder->get_config = intel_sdvo_get_config; 3401 3402 /* In default case sdvo lvds is false */ 3403 if (!intel_sdvo_get_capabilities(intel_sdvo, &intel_sdvo->caps)) 3404 goto err; 3405 3406 intel_sdvo->colorimetry_cap = 3407 intel_sdvo_get_colorimetry_cap(intel_sdvo); 3408 3409 for (i = 0; i < ARRAY_SIZE(intel_sdvo->ddc); i++) { 3410 int ret; 3411 3412 ret = intel_sdvo_init_ddc_proxy(&intel_sdvo->ddc[i], 3413 intel_sdvo, i + 1); 3414 if (ret) 3415 goto err; 3416 } 3417 3418 if (!intel_sdvo_output_setup(intel_sdvo)) { 3419 drm_dbg_kms(&dev_priv->drm, 3420 "SDVO output failed to setup on %s\n", 3421 SDVO_NAME(intel_sdvo)); 3422 /* Output_setup can leave behind connectors! */ 3423 goto err_output; 3424 } 3425 3426 /* 3427 * Only enable the hotplug irq if we need it, to work around noisy 3428 * hotplug lines. 3429 */ 3430 if (intel_sdvo->hotplug_active) { 3431 if (intel_sdvo->base.port == PORT_B) 3432 intel_encoder->hpd_pin = HPD_SDVO_B; 3433 else 3434 intel_encoder->hpd_pin = HPD_SDVO_C; 3435 } 3436 3437 /* 3438 * Cloning SDVO with anything is often impossible, since the SDVO 3439 * encoder can request a special input timing mode. And even if that's 3440 * not the case we have evidence that cloning a plain unscaled mode with 3441 * VGA doesn't really work. Furthermore the cloning flags are way too 3442 * simplistic anyway to express such constraints, so just give up on 3443 * cloning for SDVO encoders. 3444 */ 3445 intel_sdvo->base.cloneable = 0; 3446 3447 /* Set the input timing to the screen. Assume always input 0. */ 3448 if (!intel_sdvo_set_target_input(intel_sdvo)) 3449 goto err_output; 3450 3451 if (!intel_sdvo_get_input_pixel_clock_range(intel_sdvo, 3452 &intel_sdvo->pixel_clock_min, 3453 &intel_sdvo->pixel_clock_max)) 3454 goto err_output; 3455 3456 drm_dbg_kms(&dev_priv->drm, "%s device VID/DID: %02X:%02X.%02X, " 3457 "clock range %dMHz - %dMHz, " 3458 "num inputs: %d, " 3459 "output 1: %c, output 2: %c\n", 3460 SDVO_NAME(intel_sdvo), 3461 intel_sdvo->caps.vendor_id, intel_sdvo->caps.device_id, 3462 intel_sdvo->caps.device_rev_id, 3463 intel_sdvo->pixel_clock_min / 1000, 3464 intel_sdvo->pixel_clock_max / 1000, 3465 intel_sdvo->caps.sdvo_num_inputs, 3466 /* check currently supported outputs */ 3467 intel_sdvo->caps.output_flags & 3468 (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_RGB0 | 3469 SDVO_OUTPUT_LVDS0 | SDVO_OUTPUT_SVID0 | 3470 SDVO_OUTPUT_CVBS0 | SDVO_OUTPUT_YPRPB0) ? 'Y' : 'N', 3471 intel_sdvo->caps.output_flags & 3472 (SDVO_OUTPUT_TMDS1 | SDVO_OUTPUT_RGB1 | 3473 SDVO_OUTPUT_LVDS1) ? 'Y' : 'N'); 3474 return true; 3475 3476 err_output: 3477 intel_sdvo_output_cleanup(intel_sdvo); 3478 err: 3479 intel_sdvo_unselect_i2c_bus(intel_sdvo); 3480 intel_sdvo_encoder_destroy(&intel_encoder->base); 3481 3482 return false; 3483 } 3484