10b6d7dbfSJani Nikula /* SPDX-License-Identifier: MIT */ 20b6d7dbfSJani Nikula /* Copyright © 2025 Intel Corporation */ 30b6d7dbfSJani Nikula 40b6d7dbfSJani Nikula #ifndef __INTEL_SBI_REGS_H__ 50b6d7dbfSJani Nikula #define __INTEL_SBI_REGS_H__ 60b6d7dbfSJani Nikula 7*fd585ee8SJani Nikula #include "intel_display_reg_defs.h" 80b6d7dbfSJani Nikula 90b6d7dbfSJani Nikula /* 100b6d7dbfSJani Nikula * Sideband Interface (SBI) is programmed indirectly, via SBI_ADDR, which 110b6d7dbfSJani Nikula * contains the register offset; and SBI_DATA, which contains the payload. 120b6d7dbfSJani Nikula */ 130b6d7dbfSJani Nikula #define SBI_ADDR _MMIO(0xC6000) 14e583c27aSJani Nikula #define SBI_ADDR_MASK REG_GENMASK(31, 16) 15e583c27aSJani Nikula #define SBI_ADDR_VALUE(addr) REG_FIELD_PREP(SBI_ADDR_MASK, (addr)) 16e583c27aSJani Nikula 170b6d7dbfSJani Nikula #define SBI_DATA _MMIO(0xC6004) 18e583c27aSJani Nikula 190b6d7dbfSJani Nikula #define SBI_CTL_STAT _MMIO(0xC6008) 20e583c27aSJani Nikula #define SBI_CTL_DEST_MASK REG_GENMASK(16, 16) 21e583c27aSJani Nikula #define SBI_CTL_DEST_ICLK REG_FIELD_PREP(SBI_CTL_DEST_MASK, 0) 22e583c27aSJani Nikula #define SBI_CTL_DEST_MPHY REG_FIELD_PREP(SBI_CTL_DEST_MASK, 1) 23e583c27aSJani Nikula #define SBI_CTL_OP_MASK REG_GENMASK(15, 8) 24e583c27aSJani Nikula #define SBI_CTL_OP_IORD REG_FIELD_PREP(SBI_CTL_OP_MASK, 2) 25e583c27aSJani Nikula #define SBI_CTL_OP_IOWR REG_FIELD_PREP(SBI_CTL_OP_MASK, 3) 26e583c27aSJani Nikula #define SBI_CTL_OP_CRRD REG_FIELD_PREP(SBI_CTL_OP_MASK, 6) 27e583c27aSJani Nikula #define SBI_CTL_OP_CRWR REG_FIELD_PREP(SBI_CTL_OP_MASK, 7) 28e583c27aSJani Nikula #define SBI_CTL_OP_WR REG_BIT(8) 29e583c27aSJani Nikula #define SBI_RESPONSE_MASK REG_GENMASK(2, 1) 30e583c27aSJani Nikula #define SBI_RESPONSE_FAIL REG_FIELD_PREP(SBI_RESPONSE_MASK, 1) 31e583c27aSJani Nikula #define SBI_RESPONSE_SUCCESS REG_FIELD_PREP(SBI_RESPONSE_MASK, 0) 32e583c27aSJani Nikula #define SBI_STATUS_MASK REG_GENMASK(0, 0) 33e583c27aSJani Nikula #define SBI_STATUS_BUSY REG_FIELD_PREP(SBI_STATUS_MASK, 1) 34e583c27aSJani Nikula #define SBI_STATUS_READY REG_FIELD_PREP(SBI_STATUS_MASK, 0) 350b6d7dbfSJani Nikula 360b6d7dbfSJani Nikula /* SBI offsets */ 370b6d7dbfSJani Nikula #define SBI_SSCDIVINTPHASE 0x0200 38e583c27aSJani Nikula 390b6d7dbfSJani Nikula #define SBI_SSCDIVINTPHASE6 0x0600 400b6d7dbfSJani Nikula #define SBI_SSCDIVINTPHASE_DIVSEL_SHIFT 1 410b6d7dbfSJani Nikula #define SBI_SSCDIVINTPHASE_DIVSEL_MASK (0x7f << 1) 420b6d7dbfSJani Nikula #define SBI_SSCDIVINTPHASE_DIVSEL(x) ((x) << 1) 430b6d7dbfSJani Nikula #define SBI_SSCDIVINTPHASE_INCVAL_SHIFT 8 440b6d7dbfSJani Nikula #define SBI_SSCDIVINTPHASE_INCVAL_MASK (0x7f << 8) 450b6d7dbfSJani Nikula #define SBI_SSCDIVINTPHASE_INCVAL(x) ((x) << 8) 460b6d7dbfSJani Nikula #define SBI_SSCDIVINTPHASE_DIR(x) ((x) << 15) 470b6d7dbfSJani Nikula #define SBI_SSCDIVINTPHASE_PROPAGATE (1 << 0) 48e583c27aSJani Nikula 490b6d7dbfSJani Nikula #define SBI_SSCDITHPHASE 0x0204 500b6d7dbfSJani Nikula #define SBI_SSCCTL 0x020c 510b6d7dbfSJani Nikula #define SBI_SSCCTL6 0x060C 520b6d7dbfSJani Nikula #define SBI_SSCCTL_PATHALT (1 << 3) 530b6d7dbfSJani Nikula #define SBI_SSCCTL_DISABLE (1 << 0) 54e583c27aSJani Nikula 550b6d7dbfSJani Nikula #define SBI_SSCAUXDIV6 0x0610 560b6d7dbfSJani Nikula #define SBI_SSCAUXDIV_FINALDIV2SEL_SHIFT 4 570b6d7dbfSJani Nikula #define SBI_SSCAUXDIV_FINALDIV2SEL_MASK (1 << 4) 580b6d7dbfSJani Nikula #define SBI_SSCAUXDIV_FINALDIV2SEL(x) ((x) << 4) 59e583c27aSJani Nikula 600b6d7dbfSJani Nikula #define SBI_DBUFF0 0x2a00 61e583c27aSJani Nikula 620b6d7dbfSJani Nikula #define SBI_GEN0 0x1f00 630b6d7dbfSJani Nikula #define SBI_GEN0_CFG_BUFFENABLE_DISABLE (1 << 0) 640b6d7dbfSJani Nikula 650b6d7dbfSJani Nikula #endif /* __INTEL_SBI_REGS_H__ */ 66