xref: /linux/drivers/gpu/drm/i915/display/intel_sbi.c (revision 2cddfc2e8fc78c13b0f5286ea5dd48cdf527ad41)
1 // SPDX-License-Identifier: MIT
2 /*
3  * Copyright © 2013-2021 Intel Corporation
4  *
5  * LPT/WPT IOSF sideband.
6  */
7 
8 #include <drm/drm_print.h>
9 
10 #include "intel_de.h"
11 #include "intel_display_core.h"
12 #include "intel_sbi.h"
13 #include "intel_sbi_regs.h"
14 
15 /* SBI access */
16 static int intel_sbi_rw(struct intel_display *display, u16 reg,
17 			enum intel_sbi_destination destination,
18 			u32 *val, bool is_read)
19 {
20 	u32 cmd;
21 
22 	lockdep_assert_held(&display->sbi.lock);
23 
24 	if (intel_de_wait_fw_ms(display, SBI_CTL_STAT,
25 				SBI_STATUS_MASK, SBI_STATUS_READY, 100, NULL)) {
26 		drm_err(display->drm, "timeout waiting for SBI to become ready\n");
27 		return -EBUSY;
28 	}
29 
30 	intel_de_write_fw(display, SBI_ADDR, SBI_ADDR_VALUE(reg));
31 	intel_de_write_fw(display, SBI_DATA, is_read ? 0 : *val);
32 
33 	if (destination == SBI_ICLK)
34 		cmd = SBI_CTL_DEST_ICLK | SBI_CTL_OP_CRRD;
35 	else
36 		cmd = SBI_CTL_DEST_MPHY | SBI_CTL_OP_IORD;
37 	if (!is_read)
38 		cmd |= SBI_CTL_OP_WR;
39 	intel_de_write_fw(display, SBI_CTL_STAT, cmd | SBI_STATUS_BUSY);
40 
41 	if (intel_de_wait_fw_ms(display, SBI_CTL_STAT,
42 				SBI_STATUS_MASK, SBI_STATUS_READY, 100, &cmd)) {
43 		drm_err(display->drm, "timeout waiting for SBI to complete read\n");
44 		return -ETIMEDOUT;
45 	}
46 
47 	if (cmd & SBI_RESPONSE_FAIL) {
48 		drm_err(display->drm, "error during SBI read of reg %x\n", reg);
49 		return -ENXIO;
50 	}
51 
52 	if (is_read)
53 		*val = intel_de_read_fw(display, SBI_DATA);
54 
55 	return 0;
56 }
57 
58 void intel_sbi_lock(struct intel_display *display)
59 {
60 	mutex_lock(&display->sbi.lock);
61 }
62 
63 void intel_sbi_unlock(struct intel_display *display)
64 {
65 	mutex_unlock(&display->sbi.lock);
66 }
67 
68 u32 intel_sbi_read(struct intel_display *display, u16 reg,
69 		   enum intel_sbi_destination destination)
70 {
71 	u32 result = 0;
72 
73 	intel_sbi_rw(display, reg, destination, &result, true);
74 
75 	return result;
76 }
77 
78 void intel_sbi_write(struct intel_display *display, u16 reg, u32 value,
79 		     enum intel_sbi_destination destination)
80 {
81 	intel_sbi_rw(display, reg, destination, &value, false);
82 }
83 
84 void intel_sbi_init(struct intel_display *display)
85 {
86 	mutex_init(&display->sbi.lock);
87 }
88 
89 void intel_sbi_fini(struct intel_display *display)
90 {
91 	mutex_destroy(&display->sbi.lock);
92 }
93