1 /* 2 * Copyright © 2014 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 */ 23 24 #include <linux/debugfs.h> 25 26 #include <drm/drm_atomic_helper.h> 27 #include <drm/drm_damage_helper.h> 28 #include <drm/drm_debugfs.h> 29 #include <drm/drm_print.h> 30 #include <drm/drm_vblank.h> 31 #include <drm/intel/step.h> 32 33 #include "intel_alpm.h" 34 #include "intel_atomic.h" 35 #include "intel_crtc.h" 36 #include "intel_cursor_regs.h" 37 #include "intel_ddi.h" 38 #include "intel_de.h" 39 #include "intel_display_irq.h" 40 #include "intel_display_regs.h" 41 #include "intel_display_rpm.h" 42 #include "intel_display_types.h" 43 #include "intel_display_utils.h" 44 #include "intel_display_wa.h" 45 #include "intel_dmc.h" 46 #include "intel_dp.h" 47 #include "intel_dpcd.h" 48 #include "intel_dp_aux.h" 49 #include "intel_dp_tunnel.h" 50 #include "intel_dsb.h" 51 #include "intel_frontbuffer.h" 52 #include "intel_hdmi.h" 53 #include "intel_psr.h" 54 #include "intel_psr_regs.h" 55 #include "intel_quirks.h" 56 #include "intel_snps_phy.h" 57 #include "intel_vblank.h" 58 #include "intel_vdsc.h" 59 #include "intel_vrr.h" 60 #include "skl_universal_plane.h" 61 62 /** 63 * DOC: Panel Self Refresh (PSR/SRD) 64 * 65 * Since Haswell Display controller supports Panel Self-Refresh on display 66 * panels witch have a remote frame buffer (RFB) implemented according to PSR 67 * spec in eDP1.3. PSR feature allows the display to go to lower standby states 68 * when system is idle but display is on as it eliminates display refresh 69 * request to DDR memory completely as long as the frame buffer for that 70 * display is unchanged. 71 * 72 * Panel Self Refresh must be supported by both Hardware (source) and 73 * Panel (sink). 74 * 75 * PSR saves power by caching the framebuffer in the panel RFB, which allows us 76 * to power down the link and memory controller. For DSI panels the same idea 77 * is called "manual mode". 78 * 79 * The implementation uses the hardware-based PSR support which automatically 80 * enters/exits self-refresh mode. The hardware takes care of sending the 81 * required DP aux message and could even retrain the link (that part isn't 82 * enabled yet though). The hardware also keeps track of any frontbuffer 83 * changes to know when to exit self-refresh mode again. Unfortunately that 84 * part doesn't work too well, hence why the i915 PSR support uses the 85 * software frontbuffer tracking to make sure it doesn't miss a screen 86 * update. For this integration intel_psr_invalidate() and intel_psr_flush() 87 * get called by the frontbuffer tracking code. Note that because of locking 88 * issues the self-refresh re-enable code is done from a work queue, which 89 * must be correctly synchronized/cancelled when shutting down the pipe." 90 * 91 * DC3CO (DC3 clock off) 92 * 93 * On top of PSR2, GEN12 adds a intermediate power savings state that turns 94 * clock off automatically during PSR2 idle state. 95 * The smaller overhead of DC3co entry/exit vs. the overhead of PSR2 deep sleep 96 * entry/exit allows the HW to enter a low-power state even when page flipping 97 * periodically (for instance a 30fps video playback scenario). 98 * 99 * Every time a flips occurs PSR2 will get out of deep sleep state(if it was), 100 * so DC3CO is enabled and tgl_dc3co_disable_work is schedule to run after 6 101 * frames, if no other flip occurs and the function above is executed, DC3CO is 102 * disabled and PSR2 is configured to enter deep sleep, resetting again in case 103 * of another flip. 104 * Front buffer modifications do not trigger DC3CO activation on purpose as it 105 * would bring a lot of complexity and most of the moderns systems will only 106 * use page flips. 107 */ 108 109 /* 110 * Description of PSR mask bits: 111 * 112 * EDP_PSR_DEBUG[16]/EDP_PSR_DEBUG_MASK_DISP_REG_WRITE (hsw-skl): 113 * 114 * When unmasked (nearly) all display register writes (eg. even 115 * SWF) trigger a PSR exit. Some registers are excluded from this 116 * and they have a more specific mask (described below). On icl+ 117 * this bit no longer exists and is effectively always set. 118 * 119 * PIPE_MISC[21]/PIPE_MISC_PSR_MASK_PIPE_REG_WRITE (skl+): 120 * 121 * When unmasked (nearly) all pipe/plane register writes 122 * trigger a PSR exit. Some plane registers are excluded from this 123 * and they have a more specific mask (described below). 124 * 125 * CHICKEN_PIPESL_1[11]/SKL_PSR_MASK_PLANE_FLIP (skl+): 126 * PIPE_MISC[23]/PIPE_MISC_PSR_MASK_PRIMARY_FLIP (bdw): 127 * EDP_PSR_DEBUG[23]/EDP_PSR_DEBUG_MASK_PRIMARY_FLIP (hsw): 128 * 129 * When unmasked PRI_SURF/PLANE_SURF writes trigger a PSR exit. 130 * SPR_SURF/CURBASE are not included in this and instead are 131 * controlled by PIPE_MISC_PSR_MASK_PIPE_REG_WRITE (skl+) or 132 * EDP_PSR_DEBUG_MASK_DISP_REG_WRITE (hsw/bdw). 133 * 134 * PIPE_MISC[22]/PIPE_MISC_PSR_MASK_SPRITE_ENABLE (bdw): 135 * EDP_PSR_DEBUG[21]/EDP_PSR_DEBUG_MASK_SPRITE_ENABLE (hsw): 136 * 137 * When unmasked PSR is blocked as long as the sprite 138 * plane is enabled. skl+ with their universal planes no 139 * longer have a mask bit like this, and no plane being 140 * enabledb blocks PSR. 141 * 142 * PIPE_MISC[21]/PIPE_MISC_PSR_MASK_CURSOR_MOVE (bdw): 143 * EDP_PSR_DEBUG[20]/EDP_PSR_DEBUG_MASK_CURSOR_MOVE (hsw): 144 * 145 * When umasked CURPOS writes trigger a PSR exit. On skl+ 146 * this doesn't exit but CURPOS is included in the 147 * PIPE_MISC_PSR_MASK_PIPE_REG_WRITE mask. 148 * 149 * PIPE_MISC[20]/PIPE_MISC_PSR_MASK_VBLANK_VSYNC_INT (bdw+): 150 * EDP_PSR_DEBUG[19]/EDP_PSR_DEBUG_MASK_VBLANK_VSYNC_INT (hsw): 151 * 152 * When unmasked PSR is blocked as long as vblank and/or vsync 153 * interrupt is unmasked in IMR *and* enabled in IER. 154 * 155 * CHICKEN_TRANS[30]/SKL_UNMASK_VBL_TO_PIPE_IN_SRD (skl+): 156 * CHICKEN_PAR1_1[15]/HSW_MASK_VBL_TO_PIPE_IN_SRD (hsw/bdw): 157 * 158 * Selectcs whether PSR exit generates an extra vblank before 159 * the first frame is transmitted. Also note the opposite polarity 160 * if the bit on hsw/bdw vs. skl+ (masked==generate the extra vblank, 161 * unmasked==do not generate the extra vblank). 162 * 163 * With DC states enabled the extra vblank happens after link training, 164 * with DC states disabled it happens immediately upuon PSR exit trigger. 165 * No idea as of now why there is a difference. HSW/BDW (which don't 166 * even have DMC) always generate it after link training. Go figure. 167 * 168 * Unfortunately CHICKEN_TRANS itself seems to be double buffered 169 * and thus won't latch until the first vblank. So with DC states 170 * enabled the register effectively uses the reset value during DC5 171 * exit+PSR exit sequence, and thus the bit does nothing until 172 * latched by the vblank that it was trying to prevent from being 173 * generated in the first place. So we should probably call this 174 * one a chicken/egg bit instead on skl+. 175 * 176 * In standby mode (as opposed to link-off) this makes no difference 177 * as the timing generator keeps running the whole time generating 178 * normal periodic vblanks. 179 * 180 * WaPsrDPAMaskVBlankInSRD asks us to set the bit on hsw/bdw, 181 * and doing so makes the behaviour match the skl+ reset value. 182 * 183 * CHICKEN_PIPESL_1[0]/BDW_UNMASK_VBL_TO_REGS_IN_SRD (bdw): 184 * CHICKEN_PIPESL_1[15]/HSW_UNMASK_VBL_TO_REGS_IN_SRD (hsw): 185 * 186 * On BDW without this bit is no vblanks whatsoever are 187 * generated after PSR exit. On HSW this has no apparent effect. 188 * WaPsrDPRSUnmaskVBlankInSRD says to set this. 189 * 190 * The rest of the bits are more self-explanatory and/or 191 * irrelevant for normal operation. 192 * 193 * Description of intel_crtc_state variables. has_psr, has_panel_replay and 194 * has_sel_update: 195 * 196 * has_psr (alone): PSR1 197 * has_psr + has_sel_update: PSR2 198 * has_psr + has_panel_replay: Panel Replay 199 * has_psr + has_panel_replay + has_sel_update: Panel Replay Selective Update 200 * 201 * Description of some intel_psr variables. enabled, panel_replay_enabled, 202 * sel_update_enabled 203 * 204 * enabled (alone): PSR1 205 * enabled + sel_update_enabled: PSR2 206 * enabled + panel_replay_enabled: Panel Replay 207 * enabled + panel_replay_enabled + sel_update_enabled: Panel Replay SU 208 */ 209 210 #define CAN_PSR(intel_dp) ((intel_dp)->psr.sink_support && \ 211 (intel_dp)->psr.source_support) 212 213 bool intel_encoder_can_psr(struct intel_encoder *encoder) 214 { 215 if (intel_encoder_is_dp(encoder) || encoder->type == INTEL_OUTPUT_DP_MST) 216 return CAN_PSR(enc_to_intel_dp(encoder)) || 217 CAN_PANEL_REPLAY(enc_to_intel_dp(encoder)); 218 else 219 return false; 220 } 221 222 bool intel_psr_needs_aux_io_power(struct intel_encoder *encoder, 223 const struct intel_crtc_state *crtc_state) 224 { 225 /* 226 * For PSR/PR modes only eDP requires the AUX IO power to be enabled whenever 227 * the output is enabled. For non-eDP outputs the main link is always 228 * on, hence it doesn't require the HW initiated AUX wake-up signaling used 229 * for eDP. 230 * 231 * TODO: 232 * - Consider leaving AUX IO disabled for eDP / PR as well, in case 233 * the ALPM with main-link off mode is not enabled. 234 * - Leave AUX IO enabled for DP / PR, once support for ALPM with 235 * main-link off mode is added for it and this mode gets enabled. 236 */ 237 return intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP) && 238 intel_encoder_can_psr(encoder); 239 } 240 241 static bool psr_global_enabled(struct intel_dp *intel_dp) 242 { 243 struct intel_connector *connector = intel_dp->attached_connector; 244 245 switch (intel_dp->psr.debug & I915_PSR_DEBUG_MODE_MASK) { 246 case I915_PSR_DEBUG_DEFAULT: 247 return intel_dp_is_edp(intel_dp) ? 248 connector->panel.vbt.psr.enable : true; 249 case I915_PSR_DEBUG_DISABLE: 250 return false; 251 default: 252 return true; 253 } 254 } 255 256 static bool sel_update_global_enabled(struct intel_dp *intel_dp) 257 { 258 switch (intel_dp->psr.debug & I915_PSR_DEBUG_MODE_MASK) { 259 case I915_PSR_DEBUG_DISABLE: 260 case I915_PSR_DEBUG_FORCE_PSR1: 261 return false; 262 default: 263 return true; 264 } 265 } 266 267 static bool panel_replay_global_enabled(struct intel_dp *intel_dp) 268 { 269 struct intel_display *display = to_intel_display(intel_dp); 270 271 return !(intel_dp->psr.debug & I915_PSR_DEBUG_PANEL_REPLAY_DISABLE) && 272 display->params.enable_panel_replay; 273 } 274 275 static u32 psr_irq_psr_error_bit_get(struct intel_dp *intel_dp) 276 { 277 struct intel_display *display = to_intel_display(intel_dp); 278 279 return DISPLAY_VER(display) >= 12 ? TGL_PSR_ERROR : 280 EDP_PSR_ERROR(intel_dp->psr.transcoder); 281 } 282 283 static u32 psr_irq_post_exit_bit_get(struct intel_dp *intel_dp) 284 { 285 struct intel_display *display = to_intel_display(intel_dp); 286 287 return DISPLAY_VER(display) >= 12 ? TGL_PSR_POST_EXIT : 288 EDP_PSR_POST_EXIT(intel_dp->psr.transcoder); 289 } 290 291 static u32 psr_irq_pre_entry_bit_get(struct intel_dp *intel_dp) 292 { 293 struct intel_display *display = to_intel_display(intel_dp); 294 295 return DISPLAY_VER(display) >= 12 ? TGL_PSR_PRE_ENTRY : 296 EDP_PSR_PRE_ENTRY(intel_dp->psr.transcoder); 297 } 298 299 static u32 psr_irq_mask_get(struct intel_dp *intel_dp) 300 { 301 struct intel_display *display = to_intel_display(intel_dp); 302 303 return DISPLAY_VER(display) >= 12 ? TGL_PSR_MASK : 304 EDP_PSR_MASK(intel_dp->psr.transcoder); 305 } 306 307 static intel_reg_t psr_ctl_reg(struct intel_display *display, 308 enum transcoder cpu_transcoder) 309 { 310 if (DISPLAY_VER(display) >= 8) 311 return EDP_PSR_CTL(display, cpu_transcoder); 312 else 313 return HSW_SRD_CTL; 314 } 315 316 static intel_reg_t psr_debug_reg(struct intel_display *display, 317 enum transcoder cpu_transcoder) 318 { 319 if (DISPLAY_VER(display) >= 8) 320 return EDP_PSR_DEBUG(display, cpu_transcoder); 321 else 322 return HSW_SRD_DEBUG; 323 } 324 325 static intel_reg_t psr_perf_cnt_reg(struct intel_display *display, 326 enum transcoder cpu_transcoder) 327 { 328 if (DISPLAY_VER(display) >= 8) 329 return EDP_PSR_PERF_CNT(display, cpu_transcoder); 330 else 331 return HSW_SRD_PERF_CNT; 332 } 333 334 static intel_reg_t psr_status_reg(struct intel_display *display, 335 enum transcoder cpu_transcoder) 336 { 337 if (DISPLAY_VER(display) >= 8) 338 return EDP_PSR_STATUS(display, cpu_transcoder); 339 else 340 return HSW_SRD_STATUS; 341 } 342 343 static intel_reg_t psr_imr_reg(struct intel_display *display, 344 enum transcoder cpu_transcoder) 345 { 346 if (DISPLAY_VER(display) >= 12) 347 return TRANS_PSR_IMR(display, cpu_transcoder); 348 else 349 return EDP_PSR_IMR; 350 } 351 352 static intel_reg_t psr_iir_reg(struct intel_display *display, 353 enum transcoder cpu_transcoder) 354 { 355 if (DISPLAY_VER(display) >= 12) 356 return TRANS_PSR_IIR(display, cpu_transcoder); 357 else 358 return EDP_PSR_IIR; 359 } 360 361 static intel_reg_t psr_aux_ctl_reg(struct intel_display *display, 362 enum transcoder cpu_transcoder) 363 { 364 if (DISPLAY_VER(display) >= 8) 365 return EDP_PSR_AUX_CTL(display, cpu_transcoder); 366 else 367 return HSW_SRD_AUX_CTL; 368 } 369 370 static intel_reg_t psr_aux_data_reg(struct intel_display *display, 371 enum transcoder cpu_transcoder, int i) 372 { 373 if (DISPLAY_VER(display) >= 8) 374 return EDP_PSR_AUX_DATA(display, cpu_transcoder, i); 375 else 376 return HSW_SRD_AUX_DATA(i); 377 } 378 379 static void psr_irq_control(struct intel_dp *intel_dp) 380 { 381 struct intel_display *display = to_intel_display(intel_dp); 382 enum transcoder cpu_transcoder = intel_dp->psr.transcoder; 383 u32 mask; 384 385 if (intel_dp->psr.panel_replay_enabled) 386 return; 387 388 mask = psr_irq_psr_error_bit_get(intel_dp); 389 if (intel_dp->psr.debug & I915_PSR_DEBUG_IRQ) 390 mask |= psr_irq_post_exit_bit_get(intel_dp) | 391 psr_irq_pre_entry_bit_get(intel_dp); 392 393 intel_de_rmw(display, psr_imr_reg(display, cpu_transcoder), 394 psr_irq_mask_get(intel_dp), ~mask); 395 } 396 397 static void psr_event_print(struct intel_display *display, 398 u32 val, bool sel_update_enabled) 399 { 400 drm_dbg_kms(display->drm, "PSR exit events: 0x%x\n", val); 401 if (val & PSR_EVENT_PSR2_WD_TIMER_EXPIRE) 402 drm_dbg_kms(display->drm, "\tPSR2 watchdog timer expired\n"); 403 if ((val & PSR_EVENT_PSR2_DISABLED) && sel_update_enabled) 404 drm_dbg_kms(display->drm, "\tPSR2 disabled\n"); 405 if (val & PSR_EVENT_SU_DIRTY_FIFO_UNDERRUN) 406 drm_dbg_kms(display->drm, "\tSU dirty FIFO underrun\n"); 407 if (val & PSR_EVENT_SU_CRC_FIFO_UNDERRUN) 408 drm_dbg_kms(display->drm, "\tSU CRC FIFO underrun\n"); 409 if (val & PSR_EVENT_GRAPHICS_RESET) 410 drm_dbg_kms(display->drm, "\tGraphics reset\n"); 411 if (val & PSR_EVENT_PCH_INTERRUPT) 412 drm_dbg_kms(display->drm, "\tPCH interrupt\n"); 413 if (val & PSR_EVENT_MEMORY_UP) 414 drm_dbg_kms(display->drm, "\tMemory up\n"); 415 if (val & PSR_EVENT_FRONT_BUFFER_MODIFY) 416 drm_dbg_kms(display->drm, "\tFront buffer modification\n"); 417 if (val & PSR_EVENT_WD_TIMER_EXPIRE) 418 drm_dbg_kms(display->drm, "\tPSR watchdog timer expired\n"); 419 if (val & PSR_EVENT_PIPE_REGISTERS_UPDATE) 420 drm_dbg_kms(display->drm, "\tPIPE registers updated\n"); 421 if (val & PSR_EVENT_REGISTER_UPDATE) 422 drm_dbg_kms(display->drm, "\tRegister updated\n"); 423 if (val & PSR_EVENT_HDCP_ENABLE) 424 drm_dbg_kms(display->drm, "\tHDCP enabled\n"); 425 if (val & PSR_EVENT_KVMR_SESSION_ENABLE) 426 drm_dbg_kms(display->drm, "\tKVMR session enabled\n"); 427 if (val & PSR_EVENT_VBI_ENABLE) 428 drm_dbg_kms(display->drm, "\tVBI enabled\n"); 429 if (val & PSR_EVENT_LPSP_MODE_EXIT) 430 drm_dbg_kms(display->drm, "\tLPSP mode exited\n"); 431 if ((val & PSR_EVENT_PSR_DISABLE) && !sel_update_enabled) 432 drm_dbg_kms(display->drm, "\tPSR disabled\n"); 433 } 434 435 void intel_psr_irq_handler(struct intel_dp *intel_dp, u32 psr_iir) 436 { 437 struct intel_display *display = to_intel_display(intel_dp); 438 enum transcoder cpu_transcoder = intel_dp->psr.transcoder; 439 ktime_t time_ns = ktime_get(); 440 441 if (psr_iir & psr_irq_pre_entry_bit_get(intel_dp)) { 442 intel_dp->psr.last_entry_attempt = time_ns; 443 drm_dbg_kms(display->drm, 444 "[transcoder %s] PSR entry attempt in 2 vblanks\n", 445 transcoder_name(cpu_transcoder)); 446 } 447 448 if (psr_iir & psr_irq_post_exit_bit_get(intel_dp)) { 449 intel_dp->psr.last_exit = time_ns; 450 drm_dbg_kms(display->drm, 451 "[transcoder %s] PSR exit completed\n", 452 transcoder_name(cpu_transcoder)); 453 454 if (DISPLAY_VER(display) >= 9) { 455 u32 val; 456 457 val = intel_de_rmw(display, 458 PSR_EVENT(display, cpu_transcoder), 459 0, 0); 460 461 psr_event_print(display, val, intel_dp->psr.sel_update_enabled); 462 } 463 } 464 465 if (psr_iir & psr_irq_psr_error_bit_get(intel_dp)) { 466 drm_warn(display->drm, "[transcoder %s] PSR aux error\n", 467 transcoder_name(cpu_transcoder)); 468 469 intel_dp->psr.irq_aux_error = true; 470 471 /* 472 * If this interruption is not masked it will keep 473 * interrupting so fast that it prevents the scheduled 474 * work to run. 475 * Also after a PSR error, we don't want to arm PSR 476 * again so we don't care about unmask the interruption 477 * or unset irq_aux_error. 478 */ 479 intel_de_rmw(display, psr_imr_reg(display, cpu_transcoder), 480 0, psr_irq_psr_error_bit_get(intel_dp)); 481 482 queue_work(display->wq.unordered, &intel_dp->psr.work); 483 } 484 } 485 486 static u8 intel_dp_get_sink_sync_latency(struct intel_dp *intel_dp) 487 { 488 struct intel_display *display = to_intel_display(intel_dp); 489 u8 val = 8; /* assume the worst if we can't read the value */ 490 491 if (drm_dp_dpcd_readb(&intel_dp->aux, 492 DP_SYNCHRONIZATION_LATENCY_IN_SINK, &val) == 1) 493 val &= DP_MAX_RESYNC_FRAME_COUNT_MASK; 494 else 495 drm_dbg_kms(display->drm, 496 "Unable to get sink synchronization latency, assuming 8 frames\n"); 497 return val; 498 } 499 500 static void _psr_compute_su_granularity(struct intel_dp *intel_dp, 501 struct intel_connector *connector) 502 { 503 struct intel_display *display = to_intel_display(intel_dp); 504 ssize_t r; 505 __le16 w; 506 u8 y; 507 508 /* 509 * If sink don't have specific granularity requirements set legacy 510 * ones. 511 */ 512 if (!(connector->dp.psr_caps.dpcd[1] & DP_PSR2_SU_GRANULARITY_REQUIRED)) { 513 /* As PSR2 HW sends full lines, we do not care about x granularity */ 514 w = cpu_to_le16(4); 515 y = 4; 516 goto exit; 517 } 518 519 r = drm_dp_dpcd_read(&intel_dp->aux, DP_PSR2_SU_X_GRANULARITY, &w, sizeof(w)); 520 if (r != sizeof(w)) 521 drm_dbg_kms(display->drm, 522 "Unable to read selective update x granularity\n"); 523 /* 524 * Spec says that if the value read is 0 the default granularity should 525 * be used instead. 526 */ 527 if (r != sizeof(w) || w == 0) 528 w = cpu_to_le16(4); 529 530 r = drm_dp_dpcd_read(&intel_dp->aux, DP_PSR2_SU_Y_GRANULARITY, &y, 1); 531 if (r != 1) { 532 drm_dbg_kms(display->drm, 533 "Unable to read selective update y granularity\n"); 534 y = 4; 535 } 536 if (y == 0) 537 y = 1; 538 539 exit: 540 connector->dp.psr_caps.su_w_granularity = le16_to_cpu(w); 541 connector->dp.psr_caps.su_y_granularity = y; 542 } 543 544 static enum intel_panel_replay_dsc_support 545 compute_pr_dsc_support(struct intel_connector *connector) 546 { 547 u8 pr_dsc_mode; 548 u8 val; 549 550 val = connector->dp.panel_replay_caps.dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_CAPABILITY)]; 551 pr_dsc_mode = REG_FIELD_GET8(DP_PANEL_REPLAY_DSC_DECODE_CAPABILITY_IN_PR_MASK, val); 552 553 switch (pr_dsc_mode) { 554 case DP_DSC_DECODE_CAPABILITY_IN_PR_FULL_FRAME_ONLY: 555 return INTEL_DP_PANEL_REPLAY_DSC_FULL_FRAME_ONLY; 556 case DP_DSC_DECODE_CAPABILITY_IN_PR_SUPPORTED: 557 return INTEL_DP_PANEL_REPLAY_DSC_SELECTIVE_UPDATE; 558 default: 559 MISSING_CASE(pr_dsc_mode); 560 fallthrough; 561 case DP_DSC_DECODE_CAPABILITY_IN_PR_NOT_SUPPORTED: 562 case DP_DSC_DECODE_CAPABILITY_IN_PR_RESERVED: 563 return INTEL_DP_PANEL_REPLAY_DSC_NOT_SUPPORTED; 564 } 565 } 566 567 static const char *panel_replay_dsc_support_str(enum intel_panel_replay_dsc_support dsc_support) 568 { 569 switch (dsc_support) { 570 case INTEL_DP_PANEL_REPLAY_DSC_NOT_SUPPORTED: 571 return "not supported"; 572 case INTEL_DP_PANEL_REPLAY_DSC_FULL_FRAME_ONLY: 573 return "full frame only"; 574 case INTEL_DP_PANEL_REPLAY_DSC_SELECTIVE_UPDATE: 575 return "selective update"; 576 default: 577 MISSING_CASE(dsc_support); 578 return "n/a"; 579 }; 580 } 581 582 static void _panel_replay_compute_su_granularity(struct intel_connector *connector) 583 { 584 u16 w; 585 u8 y; 586 587 if (!(connector->dp.panel_replay_caps.dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_CAPABILITY)] & 588 DP_PANEL_REPLAY_SU_GRANULARITY_REQUIRED)) { 589 w = 4; 590 y = 4; 591 goto exit; 592 } 593 594 /* 595 * Spec says that if the value read is 0 the default granularity should 596 * be used instead. 597 */ 598 w = le16_to_cpu(*(__le16 *)&connector->dp.panel_replay_caps.dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_X_GRANULARITY)]) ? : 4; 599 y = connector->dp.panel_replay_caps.dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_Y_GRANULARITY)] ? : 1; 600 601 exit: 602 connector->dp.panel_replay_caps.su_w_granularity = w; 603 connector->dp.panel_replay_caps.su_y_granularity = y; 604 } 605 606 static void _panel_replay_init_dpcd(struct intel_dp *intel_dp, struct intel_connector *connector) 607 { 608 struct intel_display *display = to_intel_display(intel_dp); 609 int ret; 610 611 /* TODO: Enable Panel Replay on MST once it's properly implemented. */ 612 if (intel_dp->mst_detect == DRM_DP_MST) 613 return; 614 615 if (intel_dp_is_edp(intel_dp) && 616 intel_has_dpcd_quirk(intel_dp, QUIRK_DISABLE_EDP_PANEL_REPLAY)) { 617 drm_dbg_kms(display->drm, 618 "Panel Replay support not currently available for this setup\n"); 619 return; 620 } 621 622 ret = drm_dp_dpcd_read_data(&intel_dp->aux, DP_PANEL_REPLAY_CAP_SUPPORT, 623 &connector->dp.panel_replay_caps.dpcd, 624 sizeof(connector->dp.panel_replay_caps.dpcd)); 625 if (ret < 0) 626 return; 627 628 if (!(connector->dp.panel_replay_caps.dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_SUPPORT)] & 629 DP_PANEL_REPLAY_SUPPORT)) 630 return; 631 632 if (intel_dp_is_edp(intel_dp)) { 633 if (!intel_alpm_aux_less_wake_supported(intel_dp)) { 634 drm_dbg_kms(display->drm, 635 "Panel doesn't support AUX-less ALPM, eDP Panel Replay not possible\n"); 636 return; 637 } 638 639 if (!(connector->dp.panel_replay_caps.dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_SUPPORT)] & 640 DP_PANEL_REPLAY_EARLY_TRANSPORT_SUPPORT)) { 641 drm_dbg_kms(display->drm, 642 "Panel doesn't support early transport, eDP Panel Replay not possible\n"); 643 return; 644 } 645 } 646 647 connector->dp.panel_replay_caps.support = true; 648 intel_dp->psr.sink_panel_replay_support = true; 649 650 if (connector->dp.panel_replay_caps.dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_SUPPORT)] & 651 DP_PANEL_REPLAY_SU_SUPPORT) { 652 connector->dp.panel_replay_caps.su_support = true; 653 654 _panel_replay_compute_su_granularity(connector); 655 } 656 657 connector->dp.panel_replay_caps.dsc_support = compute_pr_dsc_support(connector); 658 659 drm_dbg_kms(display->drm, 660 "Panel replay %sis supported by panel (in DSC mode: %s)\n", 661 connector->dp.panel_replay_caps.su_support ? 662 "selective_update " : "", 663 panel_replay_dsc_support_str(connector->dp.panel_replay_caps.dsc_support)); 664 } 665 666 static void _psr_init_dpcd(struct intel_dp *intel_dp, struct intel_connector *connector) 667 { 668 struct intel_display *display = to_intel_display(intel_dp); 669 int ret; 670 671 ret = drm_dp_dpcd_read_data(&intel_dp->aux, DP_PSR_SUPPORT, connector->dp.psr_caps.dpcd, 672 sizeof(connector->dp.psr_caps.dpcd)); 673 if (ret < 0) 674 return; 675 676 if (!connector->dp.psr_caps.dpcd[0]) 677 return; 678 679 drm_dbg_kms(display->drm, "eDP panel supports PSR version %x\n", 680 connector->dp.psr_caps.dpcd[0]); 681 682 if (drm_dp_has_quirk(&intel_dp->desc, DP_DPCD_QUIRK_NO_PSR)) { 683 drm_dbg_kms(display->drm, 684 "PSR support not currently available for this panel\n"); 685 return; 686 } 687 688 if (!(intel_dp->edp_dpcd[1] & DP_EDP_SET_POWER_CAP)) { 689 drm_dbg_kms(display->drm, 690 "Panel lacks power state control, PSR cannot be enabled\n"); 691 return; 692 } 693 694 connector->dp.psr_caps.support = true; 695 intel_dp->psr.sink_support = true; 696 697 connector->dp.psr_caps.sync_latency = intel_dp_get_sink_sync_latency(intel_dp); 698 699 if (intel_has_quirk(display, QUIRK_DISABLE_PSR2)) 700 return; 701 702 if (DISPLAY_VER(display) >= 9 && 703 connector->dp.psr_caps.dpcd[0] >= DP_PSR2_WITH_Y_COORD_IS_SUPPORTED) { 704 bool y_req = connector->dp.psr_caps.dpcd[1] & 705 DP_PSR2_SU_Y_COORDINATE_REQUIRED; 706 707 /* 708 * All panels that supports PSR version 03h (PSR2 + 709 * Y-coordinate) can handle Y-coordinates in VSC but we are 710 * only sure that it is going to be used when required by the 711 * panel. This way panel is capable to do selective update 712 * without a aux frame sync. 713 * 714 * To support PSR version 02h and PSR version 03h without 715 * Y-coordinate requirement panels we would need to enable 716 * GTC first. 717 */ 718 connector->dp.psr_caps.su_support = y_req && 719 intel_alpm_aux_wake_supported(intel_dp); 720 drm_dbg_kms(display->drm, "PSR2 %ssupported\n", 721 connector->dp.psr_caps.su_support ? "" : "not "); 722 } 723 724 if (connector->dp.psr_caps.su_support) { 725 ret = drm_dp_dpcd_read_byte(&intel_dp->aux, 726 INTEL_DPCD_INTEL_WA_REGISTER_CAPS, 727 &connector->dp.psr_caps.intel_wa_dpcd); 728 if (ret < 0) 729 return; 730 _psr_compute_su_granularity(intel_dp, connector); 731 } 732 } 733 734 void intel_psr_init_dpcd(struct intel_dp *intel_dp, struct intel_connector *connector) 735 { 736 _psr_init_dpcd(intel_dp, connector); 737 738 _panel_replay_init_dpcd(intel_dp, connector); 739 } 740 741 static void hsw_psr_setup_aux(struct intel_dp *intel_dp) 742 { 743 struct intel_display *display = to_intel_display(intel_dp); 744 enum transcoder cpu_transcoder = intel_dp->psr.transcoder; 745 u32 aux_clock_divider, aux_ctl; 746 /* write DP_SET_POWER=D0 */ 747 static const u8 aux_msg[] = { 748 [0] = (DP_AUX_NATIVE_WRITE << 4) | ((DP_SET_POWER >> 16) & 0xf), 749 [1] = (DP_SET_POWER >> 8) & 0xff, 750 [2] = DP_SET_POWER & 0xff, 751 [3] = 1 - 1, 752 [4] = DP_SET_POWER_D0, 753 }; 754 int i; 755 756 BUILD_BUG_ON(sizeof(aux_msg) > 20); 757 for (i = 0; i < sizeof(aux_msg); i += 4) 758 intel_de_write(display, 759 psr_aux_data_reg(display, cpu_transcoder, i >> 2), 760 intel_dp_aux_pack(&aux_msg[i], sizeof(aux_msg) - i)); 761 762 aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, 0); 763 764 /* Start with bits set for DDI_AUX_CTL register */ 765 aux_ctl = intel_dp->get_aux_send_ctl(intel_dp, sizeof(aux_msg), 766 aux_clock_divider); 767 768 /* Select only valid bits for SRD_AUX_CTL */ 769 aux_ctl &= EDP_PSR_AUX_CTL_TIME_OUT_MASK | 770 EDP_PSR_AUX_CTL_MESSAGE_SIZE_MASK | 771 EDP_PSR_AUX_CTL_PRECHARGE_2US_MASK | 772 EDP_PSR_AUX_CTL_BIT_CLOCK_2X_MASK; 773 774 intel_de_write(display, psr_aux_ctl_reg(display, cpu_transcoder), 775 aux_ctl); 776 } 777 778 static bool psr2_su_region_et_valid(struct intel_connector *connector, bool panel_replay) 779 { 780 struct intel_dp *intel_dp = intel_attached_dp(connector); 781 struct intel_display *display = to_intel_display(intel_dp); 782 783 if (DISPLAY_VER(display) < 20 || !intel_dp_is_edp(intel_dp) || 784 intel_dp->psr.debug & I915_PSR_DEBUG_SU_REGION_ET_DISABLE) 785 return false; 786 787 return panel_replay ? 788 connector->dp.panel_replay_caps.dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_SUPPORT)] & 789 DP_PANEL_REPLAY_EARLY_TRANSPORT_SUPPORT : 790 connector->dp.psr_caps.dpcd[0] == DP_PSR2_WITH_Y_COORD_ET_SUPPORTED; 791 } 792 793 static void _panel_replay_enable_sink(struct intel_dp *intel_dp, 794 const struct intel_crtc_state *crtc_state) 795 { 796 u8 panel_replay_config[2]; 797 u8 panel_replay_config_3; 798 799 panel_replay_config[0] = DP_PANEL_REPLAY_ENABLE | 800 DP_PANEL_REPLAY_VSC_SDP_CRC_EN | 801 DP_PANEL_REPLAY_UNRECOVERABLE_ERROR_EN | 802 DP_PANEL_REPLAY_RFB_STORAGE_ERROR_EN | 803 DP_PANEL_REPLAY_ACTIVE_FRAME_CRC_ERROR_EN; 804 panel_replay_config[1] = DP_PANEL_REPLAY_CRC_VERIFICATION; 805 if (crtc_state->has_sel_update) 806 panel_replay_config[0] |= DP_PANEL_REPLAY_SU_ENABLE; 807 808 if (crtc_state->enable_psr2_su_region_et) 809 panel_replay_config[0] |= DP_PANEL_REPLAY_ENABLE_SU_REGION_ET; 810 811 if (crtc_state->req_psr2_sdp_prior_scanline) 812 panel_replay_config[1] |= 813 DP_PANEL_REPLAY_SU_REGION_SCANLINE_CAPTURE; 814 815 drm_dp_dpcd_write(&intel_dp->aux, PANEL_REPLAY_CONFIG, 816 panel_replay_config, sizeof(panel_replay_config)); 817 818 panel_replay_config_3 = intel_dp_as_sdp_transmission_time(); 819 drm_dp_dpcd_writeb(&intel_dp->aux, PANEL_REPLAY_CONFIG3, panel_replay_config_3); 820 } 821 822 static void _psr_enable_sink(struct intel_dp *intel_dp, 823 const struct intel_crtc_state *crtc_state) 824 { 825 struct intel_display *display = to_intel_display(intel_dp); 826 u8 val = 0; 827 828 if (crtc_state->has_sel_update) { 829 val |= DP_PSR_ENABLE_PSR2 | DP_PSR_IRQ_HPD_WITH_CRC_ERRORS; 830 } else { 831 if (intel_dp->psr.link_standby) 832 val |= DP_PSR_MAIN_LINK_ACTIVE; 833 834 if (DISPLAY_VER(display) >= 8) 835 val |= DP_PSR_CRC_VERIFICATION; 836 } 837 838 if (crtc_state->req_psr2_sdp_prior_scanline) 839 val |= DP_PSR_SU_REGION_SCANLINE_CAPTURE; 840 841 if (crtc_state->enable_psr2_su_region_et) 842 val |= DP_PANEL_REPLAY_ENABLE_SU_REGION_ET; 843 844 if (intel_dp->psr.entry_setup_frames > 0) 845 val |= DP_PSR_FRAME_CAPTURE; 846 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, val); 847 848 val |= DP_PSR_ENABLE; 849 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, val); 850 } 851 852 static void intel_psr_enable_sink(struct intel_dp *intel_dp, 853 const struct intel_crtc_state *crtc_state) 854 { 855 intel_alpm_enable_sink(intel_dp, crtc_state); 856 857 crtc_state->has_panel_replay ? 858 _panel_replay_enable_sink(intel_dp, crtc_state) : 859 _psr_enable_sink(intel_dp, crtc_state); 860 861 if (intel_dp_is_edp(intel_dp)) 862 drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, DP_SET_POWER_D0); 863 } 864 865 void intel_psr_panel_replay_enable_sink(struct intel_dp *intel_dp) 866 { 867 /* 868 * NOTE: We might want to trigger mode set when 869 * disabling/enabling Panel Replay via debugfs interface to 870 * ensure this bit is cleared/set accordingly. 871 */ 872 if (CAN_PANEL_REPLAY(intel_dp) && panel_replay_global_enabled(intel_dp)) 873 drm_dp_dpcd_writeb(&intel_dp->aux, PANEL_REPLAY_CONFIG, 874 DP_PANEL_REPLAY_ENABLE); 875 } 876 877 static u32 intel_psr1_get_tp_time(struct intel_dp *intel_dp) 878 { 879 struct intel_display *display = to_intel_display(intel_dp); 880 struct intel_connector *connector = intel_dp->attached_connector; 881 u32 val = 0; 882 883 if (DISPLAY_VER(display) >= 11) 884 val |= EDP_PSR_TP4_TIME_0us; 885 886 if (display->params.psr_safest_params) { 887 val |= EDP_PSR_TP1_TIME_2500us; 888 val |= EDP_PSR_TP2_TP3_TIME_2500us; 889 goto check_tp3_sel; 890 } 891 892 if (connector->panel.vbt.psr.tp1_wakeup_time_us == 0) 893 val |= EDP_PSR_TP1_TIME_0us; 894 else if (connector->panel.vbt.psr.tp1_wakeup_time_us <= 100) 895 val |= EDP_PSR_TP1_TIME_100us; 896 else if (connector->panel.vbt.psr.tp1_wakeup_time_us <= 500) 897 val |= EDP_PSR_TP1_TIME_500us; 898 else 899 val |= EDP_PSR_TP1_TIME_2500us; 900 901 if (connector->panel.vbt.psr.tp2_tp3_wakeup_time_us == 0) 902 val |= EDP_PSR_TP2_TP3_TIME_0us; 903 else if (connector->panel.vbt.psr.tp2_tp3_wakeup_time_us <= 100) 904 val |= EDP_PSR_TP2_TP3_TIME_100us; 905 else if (connector->panel.vbt.psr.tp2_tp3_wakeup_time_us <= 500) 906 val |= EDP_PSR_TP2_TP3_TIME_500us; 907 else 908 val |= EDP_PSR_TP2_TP3_TIME_2500us; 909 910 /* 911 * WA 0479: hsw,bdw 912 * "Do not skip both TP1 and TP2/TP3" 913 */ 914 if (DISPLAY_VER(display) < 9 && 915 connector->panel.vbt.psr.tp1_wakeup_time_us == 0 && 916 connector->panel.vbt.psr.tp2_tp3_wakeup_time_us == 0) 917 val |= EDP_PSR_TP2_TP3_TIME_100us; 918 919 check_tp3_sel: 920 if (intel_dp_source_supports_tps3(display) && 921 drm_dp_tps3_supported(intel_dp->dpcd)) 922 val |= EDP_PSR_TP_TP1_TP3; 923 else 924 val |= EDP_PSR_TP_TP1_TP2; 925 926 return val; 927 } 928 929 static u8 psr_compute_idle_frames(struct intel_dp *intel_dp) 930 { 931 struct intel_display *display = to_intel_display(intel_dp); 932 struct intel_connector *connector = intel_dp->attached_connector; 933 int idle_frames; 934 935 /* Let's use 6 as the minimum to cover all known cases including the 936 * off-by-one issue that HW has in some cases. 937 */ 938 idle_frames = max(6, connector->panel.vbt.psr.idle_frames); 939 idle_frames = max(idle_frames, connector->dp.psr_caps.sync_latency + 1); 940 941 if (drm_WARN_ON(display->drm, idle_frames > 0xf)) 942 idle_frames = 0xf; 943 944 return idle_frames; 945 } 946 947 static bool is_dc5_dc6_blocked(struct intel_dp *intel_dp) 948 { 949 struct intel_display *display = to_intel_display(intel_dp); 950 u32 current_dc_state = intel_display_power_get_current_dc_state(display); 951 struct intel_crtc *crtc = intel_crtc_for_pipe(display, intel_dp->psr.pipe); 952 struct drm_vblank_crtc *vblank = drm_crtc_vblank_crtc(&crtc->base); 953 954 return (current_dc_state != DC_STATE_EN_UPTO_DC5 && 955 current_dc_state != DC_STATE_EN_UPTO_DC6) || 956 intel_dp->psr.active_non_psr_pipes || 957 READ_ONCE(vblank->enabled); 958 } 959 960 static void hsw_activate_psr1(struct intel_dp *intel_dp) 961 { 962 struct intel_display *display = to_intel_display(intel_dp); 963 enum transcoder cpu_transcoder = intel_dp->psr.transcoder; 964 u32 max_sleep_time = 0x1f; 965 u32 val = EDP_PSR_ENABLE; 966 967 val |= EDP_PSR_IDLE_FRAMES(psr_compute_idle_frames(intel_dp)); 968 969 if (DISPLAY_VER(display) < 20) 970 val |= EDP_PSR_MAX_SLEEP_TIME(max_sleep_time); 971 972 if (display->platform.haswell) 973 val |= EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES; 974 975 if (intel_dp->psr.link_standby) 976 val |= EDP_PSR_LINK_STANDBY; 977 978 val |= intel_psr1_get_tp_time(intel_dp); 979 980 if (DISPLAY_VER(display) >= 8) 981 val |= EDP_PSR_CRC_ENABLE; 982 983 if (DISPLAY_VER(display) >= 20) 984 val |= LNL_EDP_PSR_ENTRY_SETUP_FRAMES(intel_dp->psr.entry_setup_frames); 985 986 intel_de_rmw(display, psr_ctl_reg(display, cpu_transcoder), 987 ~EDP_PSR_RESTORE_PSR_ACTIVE_CTX_MASK, val); 988 989 /* Wa_16025596647 */ 990 if ((DISPLAY_VER(display) == 20 || 991 IS_DISPLAY_VERx100_STEP(display, 3000, STEP_A0, STEP_B0)) && 992 is_dc5_dc6_blocked(intel_dp) && intel_dp->psr.pkg_c_latency_used) 993 intel_dmc_start_pkgc_exit_at_start_of_undelayed_vblank(display, 994 intel_dp->psr.pipe, 995 true); 996 } 997 998 static u32 intel_psr2_get_tp_time(struct intel_dp *intel_dp) 999 { 1000 struct intel_display *display = to_intel_display(intel_dp); 1001 struct intel_connector *connector = intel_dp->attached_connector; 1002 u32 val = 0; 1003 1004 if (display->params.psr_safest_params) 1005 return EDP_PSR2_TP2_TIME_2500us; 1006 1007 if (connector->panel.vbt.psr.psr2_tp2_tp3_wakeup_time_us >= 0 && 1008 connector->panel.vbt.psr.psr2_tp2_tp3_wakeup_time_us <= 50) 1009 val |= EDP_PSR2_TP2_TIME_50us; 1010 else if (connector->panel.vbt.psr.psr2_tp2_tp3_wakeup_time_us <= 100) 1011 val |= EDP_PSR2_TP2_TIME_100us; 1012 else if (connector->panel.vbt.psr.psr2_tp2_tp3_wakeup_time_us <= 500) 1013 val |= EDP_PSR2_TP2_TIME_500us; 1014 else 1015 val |= EDP_PSR2_TP2_TIME_2500us; 1016 1017 return val; 1018 } 1019 1020 static int 1021 psr2_block_count_lines(u8 io_wake_lines, u8 fast_wake_lines) 1022 { 1023 return io_wake_lines < 9 && fast_wake_lines < 9 ? 8 : 12; 1024 } 1025 1026 static int psr2_block_count(struct intel_dp *intel_dp) 1027 { 1028 return psr2_block_count_lines(intel_dp->psr.io_wake_lines, 1029 intel_dp->psr.fast_wake_lines) / 4; 1030 } 1031 1032 static u8 frames_before_su_entry(struct intel_dp *intel_dp) 1033 { 1034 struct intel_connector *connector = intel_dp->attached_connector; 1035 u8 frames_before_su_entry; 1036 1037 frames_before_su_entry = max_t(u8, 1038 connector->dp.psr_caps.sync_latency + 1, 1039 2); 1040 1041 /* Entry setup frames must be at least 1 less than frames before SU entry */ 1042 if (intel_dp->psr.entry_setup_frames >= frames_before_su_entry) 1043 frames_before_su_entry = intel_dp->psr.entry_setup_frames + 1; 1044 1045 return frames_before_su_entry; 1046 } 1047 1048 static bool intel_psr_allow_pr_bw_optimization(struct intel_dp *intel_dp) 1049 { 1050 if (intel_dp_is_edp(intel_dp)) 1051 return false; 1052 1053 if (!intel_dp_tunnel_bw_alloc_is_enabled(intel_dp)) 1054 return false; 1055 1056 if (!intel_dp_tunnel_pr_optimization_supported(intel_dp)) 1057 return false; 1058 1059 return true; 1060 } 1061 1062 static void dg2_activate_panel_replay(struct intel_dp *intel_dp) 1063 { 1064 struct intel_display *display = to_intel_display(intel_dp); 1065 struct intel_psr *psr = &intel_dp->psr; 1066 enum transcoder cpu_transcoder = intel_dp->psr.transcoder; 1067 u32 dp2_ctl_set = TRANS_DP2_PANEL_REPLAY_ENABLE; 1068 u32 dp2_ctl_clear = 0; 1069 1070 if (intel_dp_is_edp(intel_dp) && psr->sel_update_enabled) { 1071 u32 val = psr->su_region_et_enabled ? 1072 LNL_EDP_PSR2_SU_REGION_ET_ENABLE : 0; 1073 1074 if (intel_dp->psr.req_psr2_sdp_prior_scanline) 1075 val |= EDP_PSR2_SU_SDP_SCANLINE; 1076 1077 intel_de_write(display, EDP_PSR2_CTL(display, cpu_transcoder), 1078 val); 1079 } 1080 1081 if (intel_psr_allow_pr_bw_optimization(intel_dp)) 1082 dp2_ctl_set |= TRANS_DP2_PR_TUNNELING_ENABLE; 1083 else 1084 dp2_ctl_clear = TRANS_DP2_PR_TUNNELING_ENABLE; 1085 1086 intel_de_rmw(display, 1087 PSR2_MAN_TRK_CTL(display, intel_dp->psr.transcoder), 1088 0, ADLP_PSR2_MAN_TRK_CTL_SF_CONTINUOS_FULL_FRAME); 1089 1090 intel_de_rmw(display, TRANS_DP2_CTL(intel_dp->psr.transcoder), dp2_ctl_clear, dp2_ctl_set); 1091 } 1092 1093 static void hsw_activate_psr2(struct intel_dp *intel_dp) 1094 { 1095 struct intel_display *display = to_intel_display(intel_dp); 1096 enum transcoder cpu_transcoder = intel_dp->psr.transcoder; 1097 u32 val = EDP_PSR2_ENABLE; 1098 u32 psr_val = 0; 1099 u8 idle_frames; 1100 1101 /* Wa_16025596647 */ 1102 if ((DISPLAY_VER(display) == 20 || 1103 IS_DISPLAY_VERx100_STEP(display, 3000, STEP_A0, STEP_B0)) && 1104 is_dc5_dc6_blocked(intel_dp) && intel_dp->psr.pkg_c_latency_used) 1105 idle_frames = 0; 1106 else 1107 idle_frames = psr_compute_idle_frames(intel_dp); 1108 val |= EDP_PSR2_IDLE_FRAMES(idle_frames); 1109 1110 if (DISPLAY_VER(display) < 14 && !display->platform.alderlake_p) 1111 val |= EDP_SU_TRACK_ENABLE; 1112 1113 if (DISPLAY_VER(display) >= 10 && DISPLAY_VER(display) < 13) 1114 val |= EDP_Y_COORDINATE_ENABLE; 1115 1116 val |= EDP_PSR2_FRAME_BEFORE_SU(frames_before_su_entry(intel_dp)); 1117 1118 val |= intel_psr2_get_tp_time(intel_dp); 1119 1120 if (DISPLAY_VER(display) >= 12 && DISPLAY_VER(display) < 20) { 1121 if (psr2_block_count(intel_dp) > 2) 1122 val |= TGL_EDP_PSR2_BLOCK_COUNT_NUM_3; 1123 else 1124 val |= TGL_EDP_PSR2_BLOCK_COUNT_NUM_2; 1125 } 1126 1127 /* Wa_22012278275:adl-p */ 1128 if (intel_display_wa(display, INTEL_DISPLAY_WA_22012278275)) { 1129 static const u8 map[] = { 1130 2, /* 5 lines */ 1131 1, /* 6 lines */ 1132 0, /* 7 lines */ 1133 3, /* 8 lines */ 1134 6, /* 9 lines */ 1135 5, /* 10 lines */ 1136 4, /* 11 lines */ 1137 7, /* 12 lines */ 1138 }; 1139 /* 1140 * Still using the default IO_BUFFER_WAKE and FAST_WAKE, see 1141 * comments below for more information 1142 */ 1143 int tmp; 1144 1145 tmp = map[intel_dp->psr.io_wake_lines - 1146 TGL_EDP_PSR2_IO_BUFFER_WAKE_MIN_LINES]; 1147 val |= TGL_EDP_PSR2_IO_BUFFER_WAKE(tmp + TGL_EDP_PSR2_IO_BUFFER_WAKE_MIN_LINES); 1148 1149 tmp = map[intel_dp->psr.fast_wake_lines - TGL_EDP_PSR2_FAST_WAKE_MIN_LINES]; 1150 val |= TGL_EDP_PSR2_FAST_WAKE(tmp + TGL_EDP_PSR2_FAST_WAKE_MIN_LINES); 1151 } else if (DISPLAY_VER(display) >= 20) { 1152 val |= LNL_EDP_PSR2_IO_BUFFER_WAKE(intel_dp->psr.io_wake_lines); 1153 } else if (DISPLAY_VER(display) >= 12) { 1154 val |= TGL_EDP_PSR2_IO_BUFFER_WAKE(intel_dp->psr.io_wake_lines); 1155 val |= TGL_EDP_PSR2_FAST_WAKE(intel_dp->psr.fast_wake_lines); 1156 } else if (DISPLAY_VER(display) >= 9) { 1157 val |= EDP_PSR2_IO_BUFFER_WAKE(intel_dp->psr.io_wake_lines); 1158 val |= EDP_PSR2_FAST_WAKE(intel_dp->psr.fast_wake_lines); 1159 } 1160 1161 if (intel_dp->psr.req_psr2_sdp_prior_scanline) 1162 val |= EDP_PSR2_SU_SDP_SCANLINE; 1163 1164 if (DISPLAY_VER(display) >= 20) 1165 psr_val |= LNL_EDP_PSR_ENTRY_SETUP_FRAMES(intel_dp->psr.entry_setup_frames); 1166 1167 if (intel_dp->psr.psr2_sel_fetch_enabled) { 1168 u32 tmp; 1169 1170 tmp = intel_de_read(display, 1171 PSR2_MAN_TRK_CTL(display, cpu_transcoder)); 1172 drm_WARN_ON(display->drm, !(tmp & PSR2_MAN_TRK_CTL_ENABLE)); 1173 } else if (HAS_PSR2_SEL_FETCH(display)) { 1174 intel_de_write(display, 1175 PSR2_MAN_TRK_CTL(display, cpu_transcoder), 0); 1176 } 1177 1178 if (intel_dp->psr.su_region_et_enabled) 1179 val |= LNL_EDP_PSR2_SU_REGION_ET_ENABLE; 1180 1181 /* 1182 * PSR2 HW is incorrectly using EDP_PSR_TP1_TP3_SEL and BSpec is 1183 * recommending keep this bit unset while PSR2 is enabled. 1184 */ 1185 intel_de_write(display, psr_ctl_reg(display, cpu_transcoder), psr_val); 1186 1187 intel_de_write(display, EDP_PSR2_CTL(display, cpu_transcoder), val); 1188 } 1189 1190 static bool 1191 transcoder_has_psr2(struct intel_display *display, enum transcoder cpu_transcoder) 1192 { 1193 if (display->platform.alderlake_p || DISPLAY_VER(display) >= 14) 1194 return cpu_transcoder == TRANSCODER_A || cpu_transcoder == TRANSCODER_B; 1195 else if (DISPLAY_VER(display) >= 12) 1196 return cpu_transcoder == TRANSCODER_A; 1197 else if (DISPLAY_VER(display) >= 9) 1198 return cpu_transcoder == TRANSCODER_EDP; 1199 else 1200 return false; 1201 } 1202 1203 static u32 intel_get_frame_time_us(const struct intel_crtc_state *crtc_state) 1204 { 1205 if (!crtc_state->hw.active) 1206 return 0; 1207 1208 return DIV_ROUND_UP(1000 * 1000, 1209 drm_mode_vrefresh(&crtc_state->hw.adjusted_mode)); 1210 } 1211 1212 static void psr2_program_idle_frames(struct intel_dp *intel_dp, 1213 u32 idle_frames) 1214 { 1215 struct intel_display *display = to_intel_display(intel_dp); 1216 enum transcoder cpu_transcoder = intel_dp->psr.transcoder; 1217 1218 intel_de_rmw(display, EDP_PSR2_CTL(display, cpu_transcoder), 1219 EDP_PSR2_IDLE_FRAMES_MASK, 1220 EDP_PSR2_IDLE_FRAMES(idle_frames)); 1221 } 1222 1223 static void tgl_psr2_enable_dc3co(struct intel_dp *intel_dp) 1224 { 1225 struct intel_display *display = to_intel_display(intel_dp); 1226 1227 psr2_program_idle_frames(intel_dp, 0); 1228 intel_display_power_set_target_dc_state(display, DC_STATE_EN_DC3CO); 1229 } 1230 1231 static void tgl_psr2_disable_dc3co(struct intel_dp *intel_dp) 1232 { 1233 struct intel_display *display = to_intel_display(intel_dp); 1234 1235 intel_display_power_set_target_dc_state(display, DC_STATE_EN_UPTO_DC6); 1236 psr2_program_idle_frames(intel_dp, psr_compute_idle_frames(intel_dp)); 1237 } 1238 1239 static void tgl_dc3co_disable_work(struct work_struct *work) 1240 { 1241 struct intel_dp *intel_dp = 1242 container_of(work, typeof(*intel_dp), psr.dc3co_work.work); 1243 1244 mutex_lock(&intel_dp->psr.lock); 1245 /* If delayed work is pending, it is not idle */ 1246 if (delayed_work_pending(&intel_dp->psr.dc3co_work)) 1247 goto unlock; 1248 1249 tgl_psr2_disable_dc3co(intel_dp); 1250 unlock: 1251 mutex_unlock(&intel_dp->psr.lock); 1252 } 1253 1254 static void tgl_disallow_dc3co_on_psr2_exit(struct intel_dp *intel_dp) 1255 { 1256 if (!intel_dp->psr.dc3co_exitline) 1257 return; 1258 1259 cancel_delayed_work(&intel_dp->psr.dc3co_work); 1260 /* Before PSR2 exit disallow dc3co*/ 1261 tgl_psr2_disable_dc3co(intel_dp); 1262 } 1263 1264 static bool 1265 dc3co_is_pipe_port_compatible(struct intel_dp *intel_dp, 1266 struct intel_crtc_state *crtc_state) 1267 { 1268 struct intel_display *display = to_intel_display(intel_dp); 1269 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 1270 enum pipe pipe = to_intel_crtc(crtc_state->uapi.crtc)->pipe; 1271 enum port port = dig_port->base.port; 1272 1273 if (display->platform.alderlake_p || DISPLAY_VER(display) >= 14) 1274 return pipe <= PIPE_B && port <= PORT_B; 1275 else 1276 return pipe == PIPE_A && port == PORT_A; 1277 } 1278 1279 static void 1280 tgl_dc3co_exitline_compute_config(struct intel_dp *intel_dp, 1281 struct intel_crtc_state *crtc_state) 1282 { 1283 struct intel_display *display = to_intel_display(intel_dp); 1284 const u32 crtc_vdisplay = crtc_state->uapi.adjusted_mode.crtc_vdisplay; 1285 struct i915_power_domains *power_domains = &display->power.domains; 1286 u32 exit_scanlines; 1287 1288 /* 1289 * FIXME: Due to the changed sequence of activating/deactivating DC3CO, 1290 * disable DC3CO until the changed dc3co activating/deactivating sequence 1291 * is applied. B.Specs:49196 1292 */ 1293 return; 1294 1295 /* 1296 * DMC's DC3CO exit mechanism has an issue with Selective Fecth 1297 * TODO: when the issue is addressed, this restriction should be removed. 1298 */ 1299 if (crtc_state->enable_psr2_sel_fetch) 1300 return; 1301 1302 if (!(power_domains->allowed_dc_mask & DC_STATE_EN_DC3CO)) 1303 return; 1304 1305 if (!dc3co_is_pipe_port_compatible(intel_dp, crtc_state)) 1306 return; 1307 1308 /* Wa_16011303918:adl-p */ 1309 if (intel_display_wa(display, INTEL_DISPLAY_WA_16011303918)) 1310 return; 1311 1312 /* 1313 * DC3CO Exit time 200us B.Spec 49196 1314 * PSR2 transcoder Early Exit scanlines = ROUNDUP(200 / line time) + 1 1315 */ 1316 exit_scanlines = 1317 intel_usecs_to_scanlines(&crtc_state->uapi.adjusted_mode, 200) + 1; 1318 1319 if (drm_WARN_ON(display->drm, exit_scanlines > crtc_vdisplay)) 1320 return; 1321 1322 crtc_state->dc3co_exitline = crtc_vdisplay - exit_scanlines; 1323 } 1324 1325 static bool intel_psr2_sel_fetch_config_valid(struct intel_dp *intel_dp, 1326 struct intel_crtc_state *crtc_state) 1327 { 1328 struct intel_display *display = to_intel_display(intel_dp); 1329 1330 if (!display->params.enable_psr2_sel_fetch && 1331 intel_dp->psr.debug != I915_PSR_DEBUG_ENABLE_SEL_FETCH) { 1332 drm_dbg_kms(display->drm, 1333 "PSR2 sel fetch not enabled, disabled by parameter\n"); 1334 return false; 1335 } 1336 1337 return crtc_state->enable_psr2_sel_fetch = true; 1338 } 1339 1340 static bool psr2_granularity_check(struct intel_crtc_state *crtc_state, 1341 struct intel_connector *connector) 1342 { 1343 struct intel_dp *intel_dp = intel_attached_dp(connector); 1344 struct intel_display *display = to_intel_display(intel_dp); 1345 const struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config; 1346 const int crtc_hdisplay = crtc_state->hw.adjusted_mode.crtc_hdisplay; 1347 const int crtc_vdisplay = crtc_state->hw.adjusted_mode.crtc_vdisplay; 1348 u16 y_granularity = 0; 1349 u16 sink_y_granularity = crtc_state->has_panel_replay ? 1350 connector->dp.panel_replay_caps.su_y_granularity : 1351 connector->dp.psr_caps.su_y_granularity; 1352 u16 sink_w_granularity; 1353 1354 if (crtc_state->has_panel_replay) 1355 sink_w_granularity = connector->dp.panel_replay_caps.su_w_granularity == 1356 DP_PANEL_REPLAY_FULL_LINE_GRANULARITY ? 1357 crtc_hdisplay : connector->dp.panel_replay_caps.su_w_granularity; 1358 else 1359 sink_w_granularity = connector->dp.psr_caps.su_w_granularity; 1360 1361 /* PSR2 HW only send full lines so we only need to validate the width */ 1362 if (crtc_hdisplay % sink_w_granularity) 1363 return false; 1364 1365 if (crtc_vdisplay % sink_y_granularity) 1366 return false; 1367 1368 /* HW tracking is only aligned to 4 lines */ 1369 if (!crtc_state->enable_psr2_sel_fetch) 1370 return sink_y_granularity == 4; 1371 1372 /* 1373 * adl_p and mtl platforms have 1 line granularity. 1374 * For other platforms with SW tracking we can adjust the y coordinates 1375 * to match sink requirement if multiple of 4. 1376 */ 1377 if (display->platform.alderlake_p || DISPLAY_VER(display) >= 14) 1378 y_granularity = sink_y_granularity; 1379 else if (sink_y_granularity <= 2) 1380 y_granularity = 4; 1381 else if ((sink_y_granularity % 4) == 0) 1382 y_granularity = sink_y_granularity; 1383 1384 if (y_granularity == 0 || crtc_vdisplay % y_granularity) 1385 return false; 1386 1387 if (crtc_state->dsc.compression_enable && 1388 vdsc_cfg->slice_height % y_granularity) 1389 return false; 1390 1391 crtc_state->su_y_granularity = y_granularity; 1392 return true; 1393 } 1394 1395 static bool apply_scanline_indication_wa(struct intel_crtc_state *crtc_state, 1396 struct intel_connector *connector) 1397 { 1398 struct intel_dp *intel_dp = intel_attached_dp(connector); 1399 u8 early_scanline_support = connector->dp.psr_caps.intel_wa_dpcd & 1400 INTEL_DPCD_INTEL_WA_REGISTER_CAPS_PSR2_EARLYSCANLINE_SDP_SUPPORT_MASK; 1401 1402 if (intel_dp->edp_dpcd[0] >= DP_EDP_15) 1403 return true; 1404 1405 switch (early_scanline_support) { 1406 case INTEL_DPCD_INTEL_WA_REGISTER_CAPS_FALL_BACK_TO_PSR1: 1407 crtc_state->req_psr2_sdp_prior_scanline = false; 1408 return false; 1409 case INTEL_DPCD_INTEL_WA_REGISTER_CAPS_PSR2_WITH_EARLY_SCANLINE: 1410 return true; 1411 case INTEL_DPCD_INTEL_WA_REGISTER_CAPS_PSR2_WITHOUT_EARLY_SCANLINE: 1412 crtc_state->req_psr2_sdp_prior_scanline = false; 1413 return true; 1414 default: 1415 MISSING_CASE(early_scanline_support); 1416 return false; 1417 } 1418 } 1419 1420 static bool _compute_psr2_sdp_prior_scanline_indication(struct intel_crtc_state *crtc_state, 1421 struct intel_connector *connector) 1422 { 1423 struct intel_dp *intel_dp = intel_attached_dp(connector); 1424 struct intel_display *display = to_intel_display(intel_dp); 1425 const struct drm_display_mode *adjusted_mode = &crtc_state->uapi.adjusted_mode; 1426 u32 hblank_total, hblank_ns, req_ns; 1427 1428 hblank_total = adjusted_mode->crtc_hblank_end - adjusted_mode->crtc_hblank_start; 1429 hblank_ns = div_u64(1000000ULL * hblank_total, adjusted_mode->crtc_clock); 1430 1431 /* From spec: ((60 / number of lanes) + 11) * 1000 / symbol clock frequency MHz */ 1432 req_ns = ((60 / crtc_state->lane_count) + 11) * 1000 / (crtc_state->port_clock / 1000); 1433 1434 if ((hblank_ns - req_ns) > 100) 1435 return true; 1436 1437 /* Not supported <13 / Wa_22012279113:adl-p */ 1438 if (DISPLAY_VER(display) < 14 || intel_dp->edp_dpcd[0] < DP_EDP_14b) 1439 return false; 1440 1441 crtc_state->req_psr2_sdp_prior_scanline = true; 1442 1443 return apply_scanline_indication_wa(crtc_state, connector); 1444 } 1445 1446 static int intel_psr_entry_setup_frames(struct intel_dp *intel_dp, 1447 struct drm_connector_state *conn_state, 1448 const struct drm_display_mode *adjusted_mode) 1449 { 1450 struct intel_display *display = to_intel_display(intel_dp); 1451 struct intel_connector *connector = to_intel_connector(conn_state->connector); 1452 int psr_setup_time = drm_dp_psr_setup_time(connector->dp.psr_caps.dpcd); 1453 int entry_setup_frames = 0; 1454 1455 if (psr_setup_time < 0) { 1456 drm_dbg_kms(display->drm, 1457 "PSR condition failed: Invalid PSR setup time (0x%02x)\n", 1458 connector->dp.psr_caps.dpcd[1]); 1459 return -ETIME; 1460 } 1461 1462 if (intel_usecs_to_scanlines(adjusted_mode, psr_setup_time) > 1463 adjusted_mode->crtc_vtotal - adjusted_mode->crtc_vdisplay - 1) { 1464 if (DISPLAY_VER(display) >= 20) { 1465 /* setup entry frames can be up to 3 frames */ 1466 entry_setup_frames = 1; 1467 drm_dbg_kms(display->drm, 1468 "PSR setup entry frames %d\n", 1469 entry_setup_frames); 1470 } else { 1471 drm_dbg_kms(display->drm, 1472 "PSR condition failed: PSR setup time (%d us) too long\n", 1473 psr_setup_time); 1474 return -ETIME; 1475 } 1476 } 1477 1478 return entry_setup_frames; 1479 } 1480 1481 static 1482 int _intel_psr_min_set_context_latency(const struct intel_crtc_state *crtc_state, 1483 bool needs_panel_replay, 1484 bool needs_sel_update) 1485 { 1486 struct intel_display *display = to_intel_display(crtc_state); 1487 1488 if (!crtc_state->has_psr) 1489 return 0; 1490 1491 /* Wa_14015401596 */ 1492 if (intel_vrr_possible(crtc_state) && IS_DISPLAY_VER(display, 13, 14)) 1493 return 1; 1494 1495 /* Rest is for SRD_STATUS needed on LunarLake and onwards */ 1496 if (DISPLAY_VER(display) < 20) 1497 return 0; 1498 1499 /* 1500 * Comment on SRD_STATUS register in Bspec for LunarLake and onwards: 1501 * 1502 * To deterministically capture the transition of the state machine 1503 * going from SRDOFFACK to IDLE, the delayed V. Blank should be at least 1504 * one line after the non-delayed V. Blank. 1505 * 1506 * Legacy TG: TRANS_SET_CONTEXT_LATENCY > 0 1507 * VRR TG: TRANS_VRR_CTL[ VRR Guardband ] < (TRANS_VRR_VMAX[ VRR Vmax ] 1508 * - TRANS_VTOTAL[ Vertical Active ]) 1509 * 1510 * SRD_STATUS is used only by PSR1 on PantherLake. 1511 * SRD_STATUS is used by PSR1 and Panel Replay DP on LunarLake. 1512 */ 1513 1514 if (needs_sel_update) 1515 return 0; 1516 1517 if (DISPLAY_VER(display) < 30 && 1518 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) 1519 return 0; 1520 1521 if (DISPLAY_VER(display) >= 30 && 1522 needs_panel_replay) 1523 return 0; 1524 1525 return 1; 1526 } 1527 1528 static bool _wake_lines_fit_into_vblank(const struct intel_crtc_state *crtc_state, 1529 int vblank, 1530 int wake_lines) 1531 { 1532 if (crtc_state->req_psr2_sdp_prior_scanline) 1533 vblank -= 1; 1534 1535 /* Vblank >= PSR2_CTL Block Count Number maximum line count */ 1536 if (vblank < wake_lines) 1537 return false; 1538 1539 return true; 1540 } 1541 1542 static bool wake_lines_fit_into_vblank(struct intel_dp *intel_dp, 1543 const struct intel_crtc_state *crtc_state, 1544 bool aux_less, 1545 bool needs_panel_replay, 1546 bool needs_sel_update) 1547 { 1548 struct intel_display *display = to_intel_display(intel_dp); 1549 int vblank = crtc_state->hw.adjusted_mode.crtc_vblank_end - 1550 crtc_state->hw.adjusted_mode.crtc_vblank_start; 1551 int wake_lines; 1552 int scl = _intel_psr_min_set_context_latency(crtc_state, 1553 needs_panel_replay, 1554 needs_sel_update); 1555 vblank -= scl; 1556 1557 if (aux_less) 1558 wake_lines = crtc_state->alpm_state.aux_less_wake_lines; 1559 else 1560 wake_lines = DISPLAY_VER(display) < 20 ? 1561 psr2_block_count_lines(crtc_state->alpm_state.io_wake_lines, 1562 crtc_state->alpm_state.fast_wake_lines) : 1563 crtc_state->alpm_state.io_wake_lines; 1564 1565 /* 1566 * Guardband has not been computed yet, so we conservatively check if the 1567 * full vblank duration is sufficient to accommodate wake line requirements 1568 * for PSR features like Panel Replay and Selective Update. 1569 * 1570 * Once the actual guardband is available, a more accurate validation is 1571 * performed in intel_psr_compute_config_late(), and PSR features are 1572 * disabled if wake lines exceed the available guardband. 1573 */ 1574 return _wake_lines_fit_into_vblank(crtc_state, vblank, wake_lines); 1575 } 1576 1577 static bool alpm_config_valid(struct intel_dp *intel_dp, 1578 struct intel_crtc_state *crtc_state, 1579 bool aux_less, 1580 bool needs_panel_replay, 1581 bool needs_sel_update) 1582 { 1583 struct intel_display *display = to_intel_display(intel_dp); 1584 1585 if (!intel_alpm_compute_params(intel_dp, crtc_state)) { 1586 drm_dbg_kms(display->drm, 1587 "PSR2/Panel Replay not enabled, Unable to use long enough wake times\n"); 1588 return false; 1589 } 1590 1591 if (!wake_lines_fit_into_vblank(intel_dp, crtc_state, aux_less, 1592 needs_panel_replay, needs_sel_update)) { 1593 drm_dbg_kms(display->drm, 1594 "PSR2/Panel Replay not enabled, too short vblank time\n"); 1595 return false; 1596 } 1597 1598 return true; 1599 } 1600 1601 static bool intel_psr2_config_valid(struct intel_dp *intel_dp, 1602 struct intel_crtc_state *crtc_state, 1603 struct drm_connector_state *conn_state) 1604 { 1605 struct intel_display *display = to_intel_display(intel_dp); 1606 struct intel_connector *connector = to_intel_connector(conn_state->connector); 1607 int crtc_hdisplay = crtc_state->hw.adjusted_mode.crtc_hdisplay; 1608 int crtc_vdisplay = crtc_state->hw.adjusted_mode.crtc_vdisplay; 1609 int psr_max_h = 0, psr_max_v = 0, max_bpp = 0; 1610 1611 if (!connector->dp.psr_caps.su_support || display->params.enable_psr == 1) 1612 return false; 1613 1614 /* JSL and EHL only supports eDP 1.3 */ 1615 if (display->platform.jasperlake || display->platform.elkhartlake) { 1616 drm_dbg_kms(display->drm, "PSR2 not supported by phy\n"); 1617 return false; 1618 } 1619 1620 /* Wa_16011181250 */ 1621 if (intel_display_wa(display, INTEL_DISPLAY_WA_16011181250)) { 1622 drm_dbg_kms(display->drm, 1623 "PSR2 is defeatured for this platform\n"); 1624 return false; 1625 } 1626 1627 if (display->platform.alderlake_p && IS_DISPLAY_STEP(display, STEP_A0, STEP_B0)) { 1628 drm_dbg_kms(display->drm, 1629 "PSR2 not completely functional in this stepping\n"); 1630 return false; 1631 } 1632 1633 if (!transcoder_has_psr2(display, crtc_state->cpu_transcoder)) { 1634 drm_dbg_kms(display->drm, 1635 "PSR2 not supported in transcoder %s\n", 1636 transcoder_name(crtc_state->cpu_transcoder)); 1637 return false; 1638 } 1639 1640 /* 1641 * DSC and PSR2 cannot be enabled simultaneously. If a requested 1642 * resolution requires DSC to be enabled, priority is given to DSC 1643 * over PSR2. 1644 */ 1645 if (crtc_state->dsc.compression_enable && 1646 (DISPLAY_VER(display) < 14 && !display->platform.alderlake_p)) { 1647 drm_dbg_kms(display->drm, 1648 "PSR2 cannot be enabled since DSC is enabled\n"); 1649 return false; 1650 } 1651 1652 if (DISPLAY_VER(display) >= 20) { 1653 psr_max_h = crtc_hdisplay; 1654 psr_max_v = crtc_vdisplay; 1655 max_bpp = crtc_state->pipe_bpp; 1656 } else if (IS_DISPLAY_VER(display, 12, 14)) { 1657 psr_max_h = 5120; 1658 psr_max_v = 3200; 1659 max_bpp = 30; 1660 } else if (IS_DISPLAY_VER(display, 10, 11)) { 1661 psr_max_h = 4096; 1662 psr_max_v = 2304; 1663 max_bpp = 24; 1664 } else if (DISPLAY_VER(display) == 9) { 1665 psr_max_h = 3640; 1666 psr_max_v = 2304; 1667 max_bpp = 24; 1668 } 1669 1670 if (crtc_state->pipe_bpp > max_bpp) { 1671 drm_dbg_kms(display->drm, 1672 "PSR2 not enabled, pipe bpp %d > max supported %d\n", 1673 crtc_state->pipe_bpp, max_bpp); 1674 return false; 1675 } 1676 1677 /* Wa_16011303918:adl-p */ 1678 if (crtc_state->vrr.enable && 1679 display->platform.alderlake_p && IS_DISPLAY_STEP(display, STEP_A0, STEP_B0)) { 1680 drm_dbg_kms(display->drm, 1681 "PSR2 not enabled, not compatible with HW stepping + VRR\n"); 1682 return false; 1683 } 1684 1685 if (!alpm_config_valid(intel_dp, crtc_state, false, false, true)) 1686 return false; 1687 1688 if (!crtc_state->enable_psr2_sel_fetch && 1689 (crtc_hdisplay > psr_max_h || crtc_vdisplay > psr_max_v)) { 1690 drm_dbg_kms(display->drm, 1691 "PSR2 not enabled, resolution %dx%d > max supported %dx%d\n", 1692 crtc_hdisplay, crtc_vdisplay, 1693 psr_max_h, psr_max_v); 1694 return false; 1695 } 1696 1697 tgl_dc3co_exitline_compute_config(intel_dp, crtc_state); 1698 1699 return true; 1700 } 1701 1702 static bool intel_sel_update_config_valid(struct intel_crtc_state *crtc_state, 1703 struct drm_connector_state *conn_state) 1704 { 1705 struct intel_connector *connector = to_intel_connector(conn_state->connector); 1706 struct intel_dp *intel_dp = intel_attached_dp(connector); 1707 struct intel_display *display = to_intel_display(intel_dp); 1708 1709 if (HAS_PSR2_SEL_FETCH(display) && 1710 !intel_psr2_sel_fetch_config_valid(intel_dp, crtc_state) && 1711 !HAS_PSR_HW_TRACKING(display)) { 1712 drm_dbg_kms(display->drm, 1713 "Selective update not enabled, selective fetch not valid and no HW tracking available\n"); 1714 goto unsupported; 1715 } 1716 1717 if (!sel_update_global_enabled(intel_dp)) { 1718 drm_dbg_kms(display->drm, 1719 "Selective update disabled by flag\n"); 1720 goto unsupported; 1721 } 1722 1723 if (!crtc_state->has_panel_replay && !intel_psr2_config_valid(intel_dp, crtc_state, 1724 conn_state)) 1725 goto unsupported; 1726 1727 if (!_compute_psr2_sdp_prior_scanline_indication(crtc_state, connector)) { 1728 drm_dbg_kms(display->drm, 1729 "Selective update not enabled, SDP indication do not fit in hblank\n"); 1730 goto unsupported; 1731 } 1732 1733 if (crtc_state->has_panel_replay) { 1734 if (DISPLAY_VER(display) < 14) 1735 goto unsupported; 1736 1737 if (!connector->dp.panel_replay_caps.su_support) 1738 goto unsupported; 1739 1740 if (intel_dsc_enabled_on_link(crtc_state) && 1741 connector->dp.panel_replay_caps.dsc_support != 1742 INTEL_DP_PANEL_REPLAY_DSC_SELECTIVE_UPDATE) { 1743 drm_dbg_kms(display->drm, 1744 "Selective update with Panel Replay not enabled because it's not supported with DSC\n"); 1745 goto unsupported; 1746 } 1747 } 1748 1749 if (crtc_state->crc_enabled) { 1750 drm_dbg_kms(display->drm, 1751 "Selective update not enabled because it would inhibit pipe CRC calculation\n"); 1752 goto unsupported; 1753 } 1754 1755 if (!psr2_granularity_check(crtc_state, connector)) { 1756 drm_dbg_kms(display->drm, 1757 "Selective update not enabled, SU granularity not compatible\n"); 1758 goto unsupported; 1759 } 1760 1761 crtc_state->enable_psr2_su_region_et = psr2_su_region_et_valid(connector, 1762 crtc_state->has_panel_replay); 1763 1764 return true; 1765 1766 unsupported: 1767 crtc_state->enable_psr2_sel_fetch = false; 1768 return false; 1769 } 1770 1771 static bool _psr_compute_config(struct intel_dp *intel_dp, 1772 struct intel_crtc_state *crtc_state, 1773 struct drm_connector_state *conn_state) 1774 { 1775 struct intel_display *display = to_intel_display(intel_dp); 1776 const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; 1777 int entry_setup_frames; 1778 1779 if (!CAN_PSR(intel_dp) || !display->params.enable_psr) 1780 return false; 1781 1782 /* 1783 * Currently PSR doesn't work reliably with VRR enabled. 1784 */ 1785 if (crtc_state->vrr.enable) 1786 return false; 1787 1788 entry_setup_frames = intel_psr_entry_setup_frames(intel_dp, conn_state, adjusted_mode); 1789 1790 if (entry_setup_frames >= 0) { 1791 crtc_state->entry_setup_frames = entry_setup_frames; 1792 } else { 1793 crtc_state->no_psr_reason = "PSR setup timing not met"; 1794 drm_dbg_kms(display->drm, 1795 "PSR condition failed: PSR setup timing not met\n"); 1796 return false; 1797 } 1798 1799 return true; 1800 } 1801 1802 static inline bool compute_link_off_after_as_sdp_when_pr_active(struct intel_connector *connector) 1803 { 1804 return (connector->dp.panel_replay_caps.dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_CAPABILITY)] & 1805 DP_PANEL_REPLAY_LINK_OFF_SUPPORTED_IN_PR_AFTER_ADAPTIVE_SYNC_SDP); 1806 } 1807 1808 static inline bool compute_disable_as_sdp_when_pr_active(struct intel_connector *connector) 1809 { 1810 return !(connector->dp.panel_replay_caps.dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_CAPABILITY)] & 1811 DP_PANEL_REPLAY_ASYNC_VIDEO_TIMING_NOT_SUPPORTED_IN_PR); 1812 } 1813 1814 static bool _panel_replay_compute_config(struct intel_crtc_state *crtc_state, 1815 const struct drm_connector_state *conn_state) 1816 { 1817 struct intel_connector *connector = 1818 to_intel_connector(conn_state->connector); 1819 struct intel_dp *intel_dp = intel_attached_dp(connector); 1820 struct intel_display *display = to_intel_display(intel_dp); 1821 struct intel_hdcp *hdcp = &connector->hdcp; 1822 1823 if (!CAN_PANEL_REPLAY(intel_dp)) 1824 return false; 1825 1826 if (!connector->dp.panel_replay_caps.support) 1827 return false; 1828 1829 if (!panel_replay_global_enabled(intel_dp)) { 1830 drm_dbg_kms(display->drm, "Panel Replay disabled by flag\n"); 1831 return false; 1832 } 1833 1834 if (crtc_state->crc_enabled) { 1835 drm_dbg_kms(display->drm, 1836 "Panel Replay not enabled because it would inhibit pipe CRC calculation\n"); 1837 return false; 1838 } 1839 1840 if (intel_dsc_enabled_on_link(crtc_state) && 1841 connector->dp.panel_replay_caps.dsc_support == 1842 INTEL_DP_PANEL_REPLAY_DSC_NOT_SUPPORTED) { 1843 drm_dbg_kms(display->drm, 1844 "Panel Replay not enabled because it's not supported with DSC\n"); 1845 return false; 1846 } 1847 1848 crtc_state->link_off_after_as_sdp_when_pr_active = compute_link_off_after_as_sdp_when_pr_active(connector); 1849 crtc_state->disable_as_sdp_when_pr_active = compute_disable_as_sdp_when_pr_active(connector); 1850 1851 if (!intel_dp_is_edp(intel_dp)) 1852 return true; 1853 1854 /* Remaining checks are for eDP only */ 1855 1856 if (to_intel_crtc(crtc_state->uapi.crtc)->pipe != PIPE_A && 1857 to_intel_crtc(crtc_state->uapi.crtc)->pipe != PIPE_B) 1858 return false; 1859 1860 /* 128b/132b Panel Replay is not supported on eDP */ 1861 if (intel_dp_is_uhbr(crtc_state)) { 1862 drm_dbg_kms(display->drm, 1863 "Panel Replay is not supported with 128b/132b\n"); 1864 return false; 1865 } 1866 1867 /* HW will not allow Panel Replay on eDP when HDCP enabled */ 1868 if (conn_state->content_protection == 1869 DRM_MODE_CONTENT_PROTECTION_DESIRED || 1870 (conn_state->content_protection == 1871 DRM_MODE_CONTENT_PROTECTION_ENABLED && hdcp->value == 1872 DRM_MODE_CONTENT_PROTECTION_UNDESIRED)) { 1873 drm_dbg_kms(display->drm, 1874 "Panel Replay is not supported with HDCP\n"); 1875 return false; 1876 } 1877 1878 if (!alpm_config_valid(intel_dp, crtc_state, true, true, false)) 1879 return false; 1880 1881 return true; 1882 } 1883 1884 static bool intel_psr_needs_wa_18037818876(struct intel_dp *intel_dp, 1885 struct intel_crtc_state *crtc_state) 1886 { 1887 struct intel_display *display = to_intel_display(intel_dp); 1888 1889 return (DISPLAY_VER(display) == 20 && crtc_state->entry_setup_frames > 0 && 1890 !crtc_state->has_sel_update); 1891 } 1892 1893 static 1894 void intel_psr_set_non_psr_pipes(struct intel_dp *intel_dp, 1895 struct intel_crtc_state *crtc_state) 1896 { 1897 struct intel_display *display = to_intel_display(intel_dp); 1898 struct intel_atomic_state *state = to_intel_atomic_state(crtc_state->uapi.state); 1899 struct intel_crtc *crtc; 1900 u8 active_pipes = 0; 1901 1902 /* Wa_16025596647 */ 1903 if (!intel_display_wa(display, INTEL_DISPLAY_WA_16025596647)) 1904 return; 1905 1906 /* Not needed by Panel Replay */ 1907 if (crtc_state->has_panel_replay) 1908 return; 1909 1910 /* We ignore possible secondary PSR/Panel Replay capable eDP */ 1911 for_each_intel_crtc(display, crtc) 1912 active_pipes |= crtc->active ? BIT(crtc->pipe) : 0; 1913 1914 active_pipes = intel_calc_active_pipes(state, active_pipes); 1915 1916 crtc_state->active_non_psr_pipes = active_pipes & 1917 ~BIT(to_intel_crtc(crtc_state->uapi.crtc)->pipe); 1918 } 1919 1920 void intel_psr_compute_config(struct intel_dp *intel_dp, 1921 struct intel_crtc_state *crtc_state, 1922 struct drm_connector_state *conn_state) 1923 { 1924 struct intel_display *display = to_intel_display(intel_dp); 1925 struct intel_connector *connector = to_intel_connector(conn_state->connector); 1926 const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; 1927 1928 if (!psr_global_enabled(intel_dp)) { 1929 drm_dbg_kms(display->drm, "PSR disabled by flag\n"); 1930 return; 1931 } 1932 1933 if (intel_dp->psr.sink_not_reliable) { 1934 drm_dbg_kms(display->drm, 1935 "PSR sink implementation is not reliable\n"); 1936 return; 1937 } 1938 1939 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { 1940 drm_dbg_kms(display->drm, 1941 "PSR condition failed: Interlaced mode enabled\n"); 1942 return; 1943 } 1944 1945 /* 1946 * FIXME figure out what is wrong with PSR+joiner and 1947 * fix it. Presumably something related to the fact that 1948 * PSR is a transcoder level feature. 1949 */ 1950 if (crtc_state->joiner_pipes) { 1951 drm_dbg_kms(display->drm, 1952 "PSR disabled due to joiner\n"); 1953 return; 1954 } 1955 1956 /* Only used for state verification. */ 1957 crtc_state->panel_replay_dsc_support = connector->dp.panel_replay_caps.dsc_support; 1958 crtc_state->has_panel_replay = _panel_replay_compute_config(crtc_state, conn_state); 1959 1960 crtc_state->has_psr = crtc_state->has_panel_replay ? true : 1961 _psr_compute_config(intel_dp, crtc_state, conn_state); 1962 1963 if (!crtc_state->has_psr) 1964 return; 1965 1966 crtc_state->has_sel_update = intel_sel_update_config_valid(crtc_state, conn_state); 1967 } 1968 1969 void intel_psr_get_config(struct intel_encoder *encoder, 1970 struct intel_crtc_state *pipe_config) 1971 { 1972 struct intel_display *display = to_intel_display(encoder); 1973 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 1974 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; 1975 struct intel_dp *intel_dp; 1976 u32 val; 1977 1978 if (!dig_port) 1979 return; 1980 1981 intel_dp = &dig_port->dp; 1982 if (!(CAN_PSR(intel_dp) || CAN_PANEL_REPLAY(intel_dp))) 1983 return; 1984 1985 mutex_lock(&intel_dp->psr.lock); 1986 if (!intel_dp->psr.enabled) 1987 goto unlock; 1988 1989 if (intel_dp->psr.panel_replay_enabled) { 1990 pipe_config->has_psr = pipe_config->has_panel_replay = true; 1991 } else { 1992 /* 1993 * Not possible to read EDP_PSR/PSR2_CTL registers as it is 1994 * enabled/disabled because of frontbuffer tracking and others. 1995 */ 1996 pipe_config->has_psr = true; 1997 } 1998 1999 pipe_config->has_sel_update = intel_dp->psr.sel_update_enabled; 2000 pipe_config->infoframes.enable |= intel_hdmi_infoframe_enable(DP_SDP_VSC); 2001 2002 if (!intel_dp->psr.sel_update_enabled) 2003 goto unlock; 2004 2005 if (HAS_PSR2_SEL_FETCH(display)) { 2006 val = intel_de_read(display, 2007 PSR2_MAN_TRK_CTL(display, cpu_transcoder)); 2008 if (val & PSR2_MAN_TRK_CTL_ENABLE) 2009 pipe_config->enable_psr2_sel_fetch = true; 2010 } 2011 2012 pipe_config->enable_psr2_su_region_et = intel_dp->psr.su_region_et_enabled; 2013 2014 if (DISPLAY_VER(display) >= 12) { 2015 val = intel_de_read(display, 2016 TRANS_EXITLINE(display, cpu_transcoder)); 2017 pipe_config->dc3co_exitline = REG_FIELD_GET(EXITLINE_MASK, val); 2018 } 2019 unlock: 2020 mutex_unlock(&intel_dp->psr.lock); 2021 } 2022 2023 static void intel_psr_activate(struct intel_dp *intel_dp) 2024 { 2025 struct intel_display *display = to_intel_display(intel_dp); 2026 enum transcoder cpu_transcoder = intel_dp->psr.transcoder; 2027 2028 drm_WARN_ON(display->drm, 2029 transcoder_has_psr2(display, cpu_transcoder) && 2030 intel_de_read(display, EDP_PSR2_CTL(display, cpu_transcoder)) & EDP_PSR2_ENABLE); 2031 2032 drm_WARN_ON(display->drm, 2033 intel_de_read(display, psr_ctl_reg(display, cpu_transcoder)) & EDP_PSR_ENABLE); 2034 2035 drm_WARN_ON(display->drm, intel_dp->psr.active); 2036 2037 drm_WARN_ON(display->drm, !intel_dp->psr.enabled); 2038 2039 lockdep_assert_held(&intel_dp->psr.lock); 2040 2041 /* psr1, psr2 and panel-replay are mutually exclusive.*/ 2042 if (intel_dp->psr.panel_replay_enabled) 2043 dg2_activate_panel_replay(intel_dp); 2044 else if (intel_dp->psr.sel_update_enabled) 2045 hsw_activate_psr2(intel_dp); 2046 else 2047 hsw_activate_psr1(intel_dp); 2048 2049 intel_dp->psr.active = true; 2050 intel_dp->psr.no_psr_reason = NULL; 2051 } 2052 2053 /* 2054 * Wa_16013835468 2055 * Wa_14015648006 2056 */ 2057 static void wm_optimization_wa(struct intel_dp *intel_dp, 2058 const struct intel_crtc_state *crtc_state) 2059 { 2060 struct intel_display *display = to_intel_display(intel_dp); 2061 enum pipe pipe = intel_dp->psr.pipe; 2062 bool activate = false; 2063 2064 /* Wa_14015648006 */ 2065 if (IS_DISPLAY_VER(display, 11, 14) && crtc_state->wm_level_disabled) 2066 activate = true; 2067 2068 /* Wa_16013835468 */ 2069 if (DISPLAY_VER(display) == 12 && 2070 crtc_state->hw.adjusted_mode.crtc_vblank_start != 2071 crtc_state->hw.adjusted_mode.crtc_vdisplay) 2072 activate = true; 2073 2074 if (activate) 2075 intel_de_rmw(display, GEN8_CHICKEN_DCPR_1, 2076 0, LATENCY_REPORTING_REMOVED(pipe)); 2077 else 2078 intel_de_rmw(display, GEN8_CHICKEN_DCPR_1, 2079 LATENCY_REPORTING_REMOVED(pipe), 0); 2080 } 2081 2082 static void intel_psr_enable_source(struct intel_dp *intel_dp, 2083 const struct intel_crtc_state *crtc_state) 2084 { 2085 struct intel_display *display = to_intel_display(intel_dp); 2086 enum transcoder cpu_transcoder = intel_dp->psr.transcoder; 2087 u32 mask = 0; 2088 2089 /* 2090 * Only HSW and BDW have PSR AUX registers that need to be setup. 2091 * SKL+ use hardcoded values PSR AUX transactions 2092 */ 2093 if (DISPLAY_VER(display) < 9) 2094 hsw_psr_setup_aux(intel_dp); 2095 2096 /* 2097 * Per Spec: Avoid continuous PSR exit by masking MEMUP and HPD also 2098 * mask LPSP to avoid dependency on other drivers that might block 2099 * runtime_pm besides preventing other hw tracking issues now we 2100 * can rely on frontbuffer tracking. 2101 * 2102 * From bspec prior LunarLake: 2103 * Only PSR_MASK[Mask FBC modify] and PSR_MASK[Mask Hotplug] are used in 2104 * panel replay mode. 2105 * 2106 * From bspec beyod LunarLake: 2107 * Panel Replay on DP: No bits are applicable 2108 * Panel Replay on eDP: All bits are applicable 2109 */ 2110 if (DISPLAY_VER(display) < 20 || intel_dp_is_edp(intel_dp)) 2111 mask = EDP_PSR_DEBUG_MASK_HPD; 2112 2113 if (intel_dp_is_edp(intel_dp)) { 2114 mask |= EDP_PSR_DEBUG_MASK_MEMUP; 2115 2116 /* 2117 * For some unknown reason on HSW non-ULT (or at least on 2118 * Dell Latitude E6540) external displays start to flicker 2119 * when PSR is enabled on the eDP. SR/PC6 residency is much 2120 * higher than should be possible with an external display. 2121 * As a workaround leave LPSP unmasked to prevent PSR entry 2122 * when external displays are active. 2123 */ 2124 if (DISPLAY_VER(display) >= 8 || display->platform.haswell_ult) 2125 mask |= EDP_PSR_DEBUG_MASK_LPSP; 2126 2127 if (DISPLAY_VER(display) < 20) 2128 mask |= EDP_PSR_DEBUG_MASK_MAX_SLEEP; 2129 2130 /* 2131 * No separate pipe reg write mask on hsw/bdw, so have to unmask all 2132 * registers in order to keep the CURSURFLIVE tricks working :( 2133 */ 2134 if (IS_DISPLAY_VER(display, 9, 10)) 2135 mask |= EDP_PSR_DEBUG_MASK_DISP_REG_WRITE; 2136 2137 /* allow PSR with sprite enabled */ 2138 if (display->platform.haswell) 2139 mask |= EDP_PSR_DEBUG_MASK_SPRITE_ENABLE; 2140 } 2141 2142 intel_de_write(display, psr_debug_reg(display, cpu_transcoder), mask); 2143 2144 psr_irq_control(intel_dp); 2145 2146 /* 2147 * TODO: if future platforms supports DC3CO in more than one 2148 * transcoder, EXITLINE will need to be unset when disabling PSR 2149 */ 2150 if (intel_dp->psr.dc3co_exitline) 2151 intel_de_rmw(display, 2152 TRANS_EXITLINE(display, cpu_transcoder), 2153 EXITLINE_MASK, 2154 intel_dp->psr.dc3co_exitline << EXITLINE_SHIFT | EXITLINE_ENABLE); 2155 2156 if (HAS_PSR_HW_TRACKING(display) && HAS_PSR2_SEL_FETCH(display)) 2157 intel_de_rmw(display, CHICKEN_PAR1_1, IGNORE_PSR2_HW_TRACKING, 2158 intel_dp->psr.psr2_sel_fetch_enabled ? 2159 IGNORE_PSR2_HW_TRACKING : 0); 2160 2161 /* 2162 * Wa_16013835468 2163 * Wa_14015648006 2164 */ 2165 wm_optimization_wa(intel_dp, crtc_state); 2166 2167 if (intel_dp->psr.sel_update_enabled) { 2168 if (DISPLAY_VER(display) == 9) 2169 intel_de_rmw(display, CHICKEN_TRANS(display, cpu_transcoder), 0, 2170 PSR2_VSC_ENABLE_PROG_HEADER | 2171 PSR2_ADD_VERTICAL_LINE_COUNT); 2172 2173 /* 2174 * Wa_16014451276:adlp,mtl[a0,b0] 2175 * All supported adlp panels have 1-based X granularity, this may 2176 * cause issues if non-supported panels are used. 2177 */ 2178 if (!intel_dp->psr.panel_replay_enabled && 2179 (IS_DISPLAY_VERx100_STEP(display, 1400, STEP_A0, STEP_B0) || 2180 display->platform.alderlake_p)) 2181 intel_de_rmw(display, CHICKEN_TRANS(display, cpu_transcoder), 2182 0, ADLP_1_BASED_X_GRANULARITY); 2183 2184 /* Wa_16012604467:adlp,mtl[a0,b0] */ 2185 if (!intel_dp->psr.panel_replay_enabled && 2186 IS_DISPLAY_VERx100_STEP(display, 1400, STEP_A0, STEP_B0)) 2187 intel_de_rmw(display, 2188 MTL_CLKGATE_DIS_TRANS(display, cpu_transcoder), 2189 0, 2190 MTL_CLKGATE_DIS_TRANS_DMASC_GATING_DIS); 2191 else if (display->platform.alderlake_p) 2192 intel_de_rmw(display, CLKGATE_DIS_MISC, 0, 2193 CLKGATE_DIS_MISC_DMASC_GATING_DIS); 2194 } 2195 2196 /* Wa_16025596647 */ 2197 if ((DISPLAY_VER(display) == 20 || 2198 IS_DISPLAY_VERx100_STEP(display, 3000, STEP_A0, STEP_B0)) && 2199 !intel_dp->psr.panel_replay_enabled) 2200 intel_dmc_block_pkgc(display, intel_dp->psr.pipe, true); 2201 2202 intel_alpm_configure(intel_dp, crtc_state); 2203 2204 if (HAS_PSR_TRANS_PUSH_FRAME_CHANGE(display)) 2205 intel_vrr_psr_frame_change_enable(crtc_state); 2206 } 2207 2208 static bool psr_interrupt_error_check(struct intel_dp *intel_dp) 2209 { 2210 struct intel_display *display = to_intel_display(intel_dp); 2211 enum transcoder cpu_transcoder = intel_dp->psr.transcoder; 2212 u32 val; 2213 2214 if (intel_dp->psr.panel_replay_enabled) 2215 goto no_err; 2216 2217 /* 2218 * If a PSR error happened and the driver is reloaded, the EDP_PSR_IIR 2219 * will still keep the error set even after the reset done in the 2220 * irq_preinstall and irq_uninstall hooks. 2221 * And enabling in this situation cause the screen to freeze in the 2222 * first time that PSR HW tries to activate so lets keep PSR disabled 2223 * to avoid any rendering problems. 2224 */ 2225 val = intel_de_read(display, psr_iir_reg(display, cpu_transcoder)); 2226 val &= psr_irq_psr_error_bit_get(intel_dp); 2227 if (val) { 2228 intel_dp->psr.sink_not_reliable = true; 2229 drm_dbg_kms(display->drm, 2230 "PSR interruption error set, not enabling PSR\n"); 2231 return false; 2232 } 2233 2234 no_err: 2235 return true; 2236 } 2237 2238 static void intel_psr_enable_locked(struct intel_dp *intel_dp, 2239 const struct intel_crtc_state *crtc_state) 2240 { 2241 struct intel_display *display = to_intel_display(intel_dp); 2242 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 2243 u32 val; 2244 2245 drm_WARN_ON(display->drm, intel_dp->psr.enabled); 2246 2247 intel_dp->psr.sel_update_enabled = crtc_state->has_sel_update; 2248 intel_dp->psr.panel_replay_enabled = crtc_state->has_panel_replay; 2249 intel_dp->psr.busy_frontbuffer_bits = 0; 2250 intel_dp->psr.pipe = to_intel_crtc(crtc_state->uapi.crtc)->pipe; 2251 intel_dp->psr.transcoder = crtc_state->cpu_transcoder; 2252 /* DC5/DC6 requires at least 6 idle frames */ 2253 val = usecs_to_jiffies(intel_get_frame_time_us(crtc_state) * 6); 2254 intel_dp->psr.dc3co_exit_delay = val; 2255 intel_dp->psr.dc3co_exitline = crtc_state->dc3co_exitline; 2256 intel_dp->psr.psr2_sel_fetch_enabled = crtc_state->enable_psr2_sel_fetch; 2257 intel_dp->psr.su_region_et_enabled = crtc_state->enable_psr2_su_region_et; 2258 intel_dp->psr.psr2_sel_fetch_cff_enabled = false; 2259 intel_dp->psr.req_psr2_sdp_prior_scanline = 2260 crtc_state->req_psr2_sdp_prior_scanline; 2261 intel_dp->psr.active_non_psr_pipes = crtc_state->active_non_psr_pipes; 2262 intel_dp->psr.pkg_c_latency_used = crtc_state->pkg_c_latency_used; 2263 intel_dp->psr.io_wake_lines = crtc_state->alpm_state.io_wake_lines; 2264 intel_dp->psr.fast_wake_lines = crtc_state->alpm_state.fast_wake_lines; 2265 intel_dp->psr.entry_setup_frames = crtc_state->entry_setup_frames; 2266 2267 if (!psr_interrupt_error_check(intel_dp)) 2268 return; 2269 2270 if (intel_dp->psr.panel_replay_enabled) 2271 drm_dbg_kms(display->drm, "Enabling Panel Replay\n"); 2272 else 2273 drm_dbg_kms(display->drm, "Enabling PSR%s\n", 2274 intel_dp->psr.sel_update_enabled ? "2" : "1"); 2275 2276 /* 2277 * Enabling sink PSR/Panel Replay here only for PSR. Panel Replay enable 2278 * bit is already written at this point. Sink ALPM is enabled here for 2279 * PSR and Panel Replay. See 2280 * intel_psr_panel_replay_enable_sink. Modifiers/options: 2281 * - Selective Update 2282 * - Region Early Transport 2283 * - Selective Update Region Scanline Capture 2284 * - VSC_SDP_CRC 2285 * - HPD on different Errors 2286 * - CRC verification 2287 * are written for PSR and Panel Replay here. 2288 */ 2289 intel_psr_enable_sink(intel_dp, crtc_state); 2290 2291 if (intel_dp_is_edp(intel_dp)) 2292 intel_snps_phy_update_psr_power_state(&dig_port->base, true); 2293 2294 intel_psr_enable_source(intel_dp, crtc_state); 2295 intel_dp->psr.enabled = true; 2296 intel_dp->psr.pause_counter = 0; 2297 2298 /* 2299 * Link_ok is sticky and set here on PSR enable. We can assume link 2300 * training is complete as we never continue to PSR enable with 2301 * untrained link. Link_ok is kept as set until first short pulse 2302 * interrupt. This is targeted to workaround panels stating bad link 2303 * after PSR is enabled. 2304 */ 2305 intel_dp->psr.link_ok = true; 2306 2307 intel_psr_activate(intel_dp); 2308 } 2309 2310 static void intel_psr_exit(struct intel_dp *intel_dp) 2311 { 2312 struct intel_display *display = to_intel_display(intel_dp); 2313 enum transcoder cpu_transcoder = intel_dp->psr.transcoder; 2314 u32 val; 2315 2316 if (!intel_dp->psr.active) { 2317 if (transcoder_has_psr2(display, cpu_transcoder)) { 2318 val = intel_de_read(display, 2319 EDP_PSR2_CTL(display, cpu_transcoder)); 2320 drm_WARN_ON(display->drm, val & EDP_PSR2_ENABLE); 2321 } 2322 2323 val = intel_de_read(display, 2324 psr_ctl_reg(display, cpu_transcoder)); 2325 drm_WARN_ON(display->drm, val & EDP_PSR_ENABLE); 2326 2327 return; 2328 } 2329 2330 if (intel_dp->psr.panel_replay_enabled) { 2331 intel_de_rmw(display, TRANS_DP2_CTL(intel_dp->psr.transcoder), 2332 TRANS_DP2_PANEL_REPLAY_ENABLE, 0); 2333 } else if (intel_dp->psr.sel_update_enabled) { 2334 tgl_disallow_dc3co_on_psr2_exit(intel_dp); 2335 2336 val = intel_de_rmw(display, 2337 EDP_PSR2_CTL(display, cpu_transcoder), 2338 EDP_PSR2_ENABLE, 0); 2339 2340 drm_WARN_ON(display->drm, !(val & EDP_PSR2_ENABLE)); 2341 } else { 2342 if ((DISPLAY_VER(display) == 20 || 2343 IS_DISPLAY_VERx100_STEP(display, 3000, STEP_A0, STEP_B0)) && 2344 intel_dp->psr.pkg_c_latency_used) 2345 intel_dmc_start_pkgc_exit_at_start_of_undelayed_vblank(display, 2346 intel_dp->psr.pipe, 2347 false); 2348 2349 val = intel_de_rmw(display, 2350 psr_ctl_reg(display, cpu_transcoder), 2351 EDP_PSR_ENABLE, 0); 2352 2353 drm_WARN_ON(display->drm, !(val & EDP_PSR_ENABLE)); 2354 } 2355 intel_dp->psr.active = false; 2356 } 2357 2358 static void intel_psr_wait_exit_locked(struct intel_dp *intel_dp) 2359 { 2360 struct intel_display *display = to_intel_display(intel_dp); 2361 enum transcoder cpu_transcoder = intel_dp->psr.transcoder; 2362 intel_reg_t psr_status; 2363 u32 psr_status_mask; 2364 2365 if (intel_dp_is_edp(intel_dp) && (intel_dp->psr.sel_update_enabled || 2366 intel_dp->psr.panel_replay_enabled)) { 2367 psr_status = EDP_PSR2_STATUS(display, cpu_transcoder); 2368 psr_status_mask = EDP_PSR2_STATUS_STATE_MASK; 2369 } else { 2370 psr_status = psr_status_reg(display, cpu_transcoder); 2371 psr_status_mask = EDP_PSR_STATUS_STATE_MASK; 2372 } 2373 2374 /* Wait till PSR is idle */ 2375 if (intel_de_wait_for_clear_ms(display, psr_status, 2376 psr_status_mask, 2000)) 2377 drm_err(display->drm, "Timed out waiting PSR idle state\n"); 2378 } 2379 2380 static void intel_psr_disable_locked(struct intel_dp *intel_dp) 2381 { 2382 struct intel_display *display = to_intel_display(intel_dp); 2383 enum transcoder cpu_transcoder = intel_dp->psr.transcoder; 2384 2385 lockdep_assert_held(&intel_dp->psr.lock); 2386 2387 if (!intel_dp->psr.enabled) 2388 return; 2389 2390 if (intel_dp->psr.panel_replay_enabled) 2391 drm_dbg_kms(display->drm, "Disabling Panel Replay\n"); 2392 else 2393 drm_dbg_kms(display->drm, "Disabling PSR%s\n", 2394 intel_dp->psr.sel_update_enabled ? "2" : "1"); 2395 2396 intel_psr_exit(intel_dp); 2397 intel_psr_wait_exit_locked(intel_dp); 2398 2399 /* 2400 * Wa_16013835468 2401 * Wa_14015648006 2402 */ 2403 if (DISPLAY_VER(display) >= 11) 2404 intel_de_rmw(display, GEN8_CHICKEN_DCPR_1, 2405 LATENCY_REPORTING_REMOVED(intel_dp->psr.pipe), 0); 2406 2407 if (intel_dp->psr.sel_update_enabled) { 2408 /* Wa_16012604467:adlp,mtl[a0,b0] */ 2409 if (!intel_dp->psr.panel_replay_enabled && 2410 IS_DISPLAY_VERx100_STEP(display, 1400, STEP_A0, STEP_B0)) 2411 intel_de_rmw(display, 2412 MTL_CLKGATE_DIS_TRANS(display, cpu_transcoder), 2413 MTL_CLKGATE_DIS_TRANS_DMASC_GATING_DIS, 0); 2414 else if (display->platform.alderlake_p) 2415 intel_de_rmw(display, CLKGATE_DIS_MISC, 2416 CLKGATE_DIS_MISC_DMASC_GATING_DIS, 0); 2417 } 2418 2419 if (intel_dp_is_edp(intel_dp)) 2420 intel_snps_phy_update_psr_power_state(&dp_to_dig_port(intel_dp)->base, false); 2421 2422 if (intel_dp->psr.panel_replay_enabled && intel_dp_is_edp(intel_dp)) 2423 intel_alpm_disable(intel_dp); 2424 2425 /* Disable PSR on Sink */ 2426 if (!intel_dp->psr.panel_replay_enabled) { 2427 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, 0); 2428 2429 if (intel_dp->psr.sel_update_enabled) 2430 drm_dp_dpcd_writeb(&intel_dp->aux, 2431 DP_RECEIVER_ALPM_CONFIG, 0); 2432 } 2433 2434 /* Wa_16025596647 */ 2435 if ((DISPLAY_VER(display) == 20 || 2436 IS_DISPLAY_VERx100_STEP(display, 3000, STEP_A0, STEP_B0)) && 2437 !intel_dp->psr.panel_replay_enabled) 2438 intel_dmc_block_pkgc(display, intel_dp->psr.pipe, false); 2439 2440 intel_dp->psr.enabled = false; 2441 intel_dp->psr.panel_replay_enabled = false; 2442 intel_dp->psr.sel_update_enabled = false; 2443 intel_dp->psr.psr2_sel_fetch_enabled = false; 2444 intel_dp->psr.su_region_et_enabled = false; 2445 intel_dp->psr.psr2_sel_fetch_cff_enabled = false; 2446 intel_dp->psr.active_non_psr_pipes = 0; 2447 intel_dp->psr.pkg_c_latency_used = 0; 2448 } 2449 2450 /** 2451 * intel_psr_disable - Disable PSR 2452 * @intel_dp: Intel DP 2453 * @old_crtc_state: old CRTC state 2454 * 2455 * This function needs to be called before disabling pipe. 2456 */ 2457 void intel_psr_disable(struct intel_dp *intel_dp, 2458 const struct intel_crtc_state *old_crtc_state) 2459 { 2460 struct intel_display *display = to_intel_display(intel_dp); 2461 2462 if (!old_crtc_state->has_psr) 2463 return; 2464 2465 if (drm_WARN_ON(display->drm, !CAN_PSR(intel_dp) && 2466 !CAN_PANEL_REPLAY(intel_dp))) 2467 return; 2468 2469 mutex_lock(&intel_dp->psr.lock); 2470 2471 intel_psr_disable_locked(intel_dp); 2472 2473 intel_dp->psr.link_ok = false; 2474 2475 mutex_unlock(&intel_dp->psr.lock); 2476 cancel_work_sync(&intel_dp->psr.work); 2477 cancel_delayed_work_sync(&intel_dp->psr.dc3co_work); 2478 } 2479 2480 /** 2481 * intel_psr_pause - Pause PSR 2482 * @intel_dp: Intel DP 2483 * 2484 * This function need to be called after enabling psr. 2485 */ 2486 void intel_psr_pause(struct intel_dp *intel_dp) 2487 { 2488 struct intel_psr *psr = &intel_dp->psr; 2489 2490 if (!CAN_PSR(intel_dp) && !CAN_PANEL_REPLAY(intel_dp)) 2491 return; 2492 2493 mutex_lock(&psr->lock); 2494 2495 if (!psr->enabled) { 2496 mutex_unlock(&psr->lock); 2497 return; 2498 } 2499 2500 if (intel_dp->psr.pause_counter++ == 0) { 2501 intel_psr_exit(intel_dp); 2502 intel_psr_wait_exit_locked(intel_dp); 2503 } 2504 2505 mutex_unlock(&psr->lock); 2506 2507 cancel_work_sync(&psr->work); 2508 cancel_delayed_work_sync(&psr->dc3co_work); 2509 } 2510 2511 /** 2512 * intel_psr_resume - Resume PSR 2513 * @intel_dp: Intel DP 2514 * 2515 * This function need to be called after pausing psr. 2516 */ 2517 void intel_psr_resume(struct intel_dp *intel_dp) 2518 { 2519 struct intel_display *display = to_intel_display(intel_dp); 2520 struct intel_psr *psr = &intel_dp->psr; 2521 2522 if (!CAN_PSR(intel_dp) && !CAN_PANEL_REPLAY(intel_dp)) 2523 return; 2524 2525 mutex_lock(&psr->lock); 2526 2527 if (!psr->enabled) 2528 goto out; 2529 2530 if (!psr->pause_counter) { 2531 drm_warn(display->drm, "Unbalanced PSR pause/resume!\n"); 2532 goto out; 2533 } 2534 2535 if (--intel_dp->psr.pause_counter == 0) 2536 intel_psr_activate(intel_dp); 2537 2538 out: 2539 mutex_unlock(&psr->lock); 2540 } 2541 2542 /** 2543 * intel_psr_needs_vblank_notification - Check if PSR need vblank enable/disable 2544 * notification. 2545 * @crtc_state: CRTC status 2546 * 2547 * We need to block DC6 entry in case of Panel Replay as enabling VBI doesn't 2548 * prevent it in case of Panel Replay. Panel Replay switches main link off on 2549 * DC entry. This means vblank interrupts are not fired and is a problem if 2550 * user-space is polling for vblank events. Also Wa_16025596647 needs 2551 * information when vblank is enabled/disabled. 2552 */ 2553 bool intel_psr_needs_vblank_notification(const struct intel_crtc_state *crtc_state) 2554 { 2555 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2556 struct intel_display *display = to_intel_display(crtc_state); 2557 struct intel_encoder *encoder; 2558 2559 for_each_encoder_on_crtc(crtc->base.dev, &crtc->base, encoder) { 2560 struct intel_dp *intel_dp; 2561 2562 if (!intel_encoder_is_dp(encoder)) 2563 continue; 2564 2565 intel_dp = enc_to_intel_dp(encoder); 2566 2567 if (!intel_dp_is_edp(intel_dp)) 2568 continue; 2569 2570 if (CAN_PANEL_REPLAY(intel_dp)) 2571 return true; 2572 2573 if ((DISPLAY_VER(display) == 20 || 2574 IS_DISPLAY_VERx100_STEP(display, 3000, STEP_A0, STEP_B0)) && 2575 CAN_PSR(intel_dp)) 2576 return true; 2577 } 2578 2579 return false; 2580 } 2581 2582 /** 2583 * intel_psr_trigger_frame_change_event - Trigger "Frame Change" event 2584 * @dsb: DSB context 2585 * @state: the atomic state 2586 * @crtc: the CRTC 2587 * 2588 * Generate PSR "Frame Change" event. 2589 */ 2590 void intel_psr_trigger_frame_change_event(struct intel_dsb *dsb, 2591 struct intel_atomic_state *state, 2592 struct intel_crtc *crtc) 2593 { 2594 const struct intel_crtc_state *crtc_state = 2595 intel_pre_commit_crtc_state(state, crtc); 2596 struct intel_display *display = to_intel_display(crtc); 2597 2598 if (!crtc_state->has_psr || intel_psr_use_trans_push(crtc_state)) 2599 return; 2600 2601 intel_de_write_dsb(display, dsb, 2602 CURSURFLIVE(display, crtc->pipe), 0); 2603 } 2604 2605 /** 2606 * intel_psr_min_set_context_latency - Minimum 'set context latency' lines needed by PSR 2607 * @crtc_state: the crtc state 2608 * 2609 * Return minimum SCL lines/delay needed by PSR. 2610 */ 2611 int intel_psr_min_set_context_latency(const struct intel_crtc_state *crtc_state) 2612 { 2613 2614 return _intel_psr_min_set_context_latency(crtc_state, 2615 crtc_state->has_panel_replay, 2616 crtc_state->has_sel_update); 2617 } 2618 2619 static u32 man_trk_ctl_enable_bit_get(struct intel_display *display) 2620 { 2621 return display->platform.alderlake_p || DISPLAY_VER(display) >= 14 ? 0 : 2622 PSR2_MAN_TRK_CTL_ENABLE; 2623 } 2624 2625 static u32 man_trk_ctl_single_full_frame_bit_get(struct intel_display *display) 2626 { 2627 return display->platform.alderlake_p || DISPLAY_VER(display) >= 14 ? 2628 ADLP_PSR2_MAN_TRK_CTL_SF_SINGLE_FULL_FRAME : 2629 PSR2_MAN_TRK_CTL_SF_SINGLE_FULL_FRAME; 2630 } 2631 2632 static u32 man_trk_ctl_partial_frame_bit_get(struct intel_display *display) 2633 { 2634 return display->platform.alderlake_p || DISPLAY_VER(display) >= 14 ? 2635 ADLP_PSR2_MAN_TRK_CTL_SF_PARTIAL_FRAME_UPDATE : 2636 PSR2_MAN_TRK_CTL_SF_PARTIAL_FRAME_UPDATE; 2637 } 2638 2639 static u32 man_trk_ctl_continuos_full_frame(struct intel_display *display) 2640 { 2641 return display->platform.alderlake_p || DISPLAY_VER(display) >= 14 ? 2642 ADLP_PSR2_MAN_TRK_CTL_SF_CONTINUOS_FULL_FRAME : 2643 PSR2_MAN_TRK_CTL_SF_CONTINUOS_FULL_FRAME; 2644 } 2645 2646 static void intel_psr_force_update(struct intel_dp *intel_dp) 2647 { 2648 struct intel_display *display = to_intel_display(intel_dp); 2649 2650 /* 2651 * Display WA #0884: skl+ 2652 * This documented WA for bxt can be safely applied 2653 * broadly so we can force HW tracking to exit PSR 2654 * instead of disabling and re-enabling. 2655 * Workaround tells us to write 0 to CUR_SURFLIVE_A, 2656 * but it makes more sense write to the current active 2657 * pipe. 2658 * 2659 * This workaround do not exist for platforms with display 10 or newer 2660 * but testing proved that it works for up display 13, for newer 2661 * than that testing will be needed. 2662 */ 2663 intel_de_write(display, CURSURFLIVE(display, intel_dp->psr.pipe), 0); 2664 } 2665 2666 void intel_psr2_program_trans_man_trk_ctl(struct intel_dsb *dsb, 2667 const struct intel_crtc_state *crtc_state) 2668 { 2669 struct intel_display *display = to_intel_display(crtc_state); 2670 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2671 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 2672 struct intel_encoder *encoder; 2673 2674 if (!crtc_state->enable_psr2_sel_fetch) 2675 return; 2676 2677 for_each_intel_encoder_mask_with_psr(display->drm, encoder, 2678 crtc_state->uapi.encoder_mask) { 2679 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2680 2681 if (!dsb) 2682 lockdep_assert_held(&intel_dp->psr.lock); 2683 2684 if (DISPLAY_VER(display) < 20 && intel_dp->psr.psr2_sel_fetch_cff_enabled) 2685 return; 2686 break; 2687 } 2688 2689 intel_de_write_dsb(display, dsb, 2690 PSR2_MAN_TRK_CTL(display, cpu_transcoder), 2691 crtc_state->psr2_man_track_ctl); 2692 2693 if (!crtc_state->enable_psr2_su_region_et) 2694 return; 2695 2696 intel_de_write_dsb(display, dsb, PIPE_SRCSZ_ERLY_TPT(crtc->pipe), 2697 crtc_state->pipe_srcsz_early_tpt); 2698 2699 if (!crtc_state->dsc.compression_enable) 2700 return; 2701 2702 intel_dsc_su_et_parameters_configure(dsb, encoder, crtc_state, 2703 drm_rect_height(&crtc_state->psr2_su_area)); 2704 } 2705 2706 static void psr2_man_trk_ctl_calc(struct intel_crtc_state *crtc_state, 2707 bool full_update) 2708 { 2709 struct intel_display *display = to_intel_display(crtc_state); 2710 u32 val = man_trk_ctl_enable_bit_get(display); 2711 2712 /* SF partial frame enable has to be set even on full update */ 2713 val |= man_trk_ctl_partial_frame_bit_get(display); 2714 2715 if (full_update) { 2716 val |= man_trk_ctl_continuos_full_frame(display); 2717 goto exit; 2718 } 2719 2720 if (crtc_state->psr2_su_area.y1 == -1) 2721 goto exit; 2722 2723 if (display->platform.alderlake_p || DISPLAY_VER(display) >= 14) { 2724 val |= ADLP_PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR(crtc_state->psr2_su_area.y1); 2725 val |= ADLP_PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR(crtc_state->psr2_su_area.y2 - 1); 2726 } else { 2727 drm_WARN_ON(crtc_state->uapi.crtc->dev, 2728 crtc_state->psr2_su_area.y1 % 4 || 2729 crtc_state->psr2_su_area.y2 % 4); 2730 2731 val |= PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR( 2732 crtc_state->psr2_su_area.y1 / 4 + 1); 2733 val |= PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR( 2734 crtc_state->psr2_su_area.y2 / 4 + 1); 2735 } 2736 exit: 2737 crtc_state->psr2_man_track_ctl = val; 2738 } 2739 2740 static u32 psr2_pipe_srcsz_early_tpt_calc(struct intel_crtc_state *crtc_state, 2741 bool full_update) 2742 { 2743 int width, height; 2744 2745 if (!crtc_state->enable_psr2_su_region_et || full_update) 2746 return 0; 2747 2748 width = drm_rect_width(&crtc_state->psr2_su_area); 2749 height = drm_rect_height(&crtc_state->psr2_su_area); 2750 2751 return PIPESRC_WIDTH(width - 1) | PIPESRC_HEIGHT(height - 1); 2752 } 2753 2754 static void clip_area_update(struct drm_rect *overlap_damage_area, 2755 struct drm_rect *damage_area, 2756 struct drm_rect *display_area) 2757 { 2758 if (!drm_rect_intersect(damage_area, display_area)) 2759 return; 2760 2761 if (overlap_damage_area->y1 == -1) { 2762 overlap_damage_area->y1 = damage_area->y1; 2763 overlap_damage_area->y2 = damage_area->y2; 2764 return; 2765 } 2766 2767 if (damage_area->y1 < overlap_damage_area->y1) 2768 overlap_damage_area->y1 = damage_area->y1; 2769 2770 if (damage_area->y2 > overlap_damage_area->y2) 2771 overlap_damage_area->y2 = damage_area->y2; 2772 } 2773 2774 static bool intel_psr2_sel_fetch_pipe_alignment(struct intel_crtc_state *crtc_state) 2775 { 2776 struct intel_display *display = to_intel_display(crtc_state); 2777 const struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config; 2778 u16 y_alignment; 2779 bool su_area_changed = false; 2780 2781 /* ADLP aligns the SU region to vdsc slice height in case dsc is enabled */ 2782 if (crtc_state->dsc.compression_enable && 2783 (display->platform.alderlake_p || DISPLAY_VER(display) >= 14)) 2784 y_alignment = vdsc_cfg->slice_height; 2785 else 2786 y_alignment = crtc_state->su_y_granularity; 2787 2788 if (crtc_state->psr2_su_area.y1 % y_alignment) { 2789 crtc_state->psr2_su_area.y1 -= crtc_state->psr2_su_area.y1 % y_alignment; 2790 su_area_changed = true; 2791 } 2792 2793 if (crtc_state->psr2_su_area.y2 % y_alignment) { 2794 crtc_state->psr2_su_area.y2 = ((crtc_state->psr2_su_area.y2 / 2795 y_alignment) + 1) * y_alignment; 2796 su_area_changed = true; 2797 } 2798 2799 return su_area_changed; 2800 } 2801 2802 /* 2803 * When early transport is in use we need to extend SU area to cover 2804 * cursor fully when cursor is in SU area. 2805 */ 2806 static void 2807 intel_psr2_sel_fetch_et_alignment(struct intel_atomic_state *state, 2808 struct intel_crtc *crtc, 2809 struct drm_rect *display_area, 2810 bool *cursor_in_su_area) 2811 { 2812 struct intel_crtc_state *crtc_state = intel_atomic_get_new_crtc_state(state, crtc); 2813 struct intel_plane_state *new_plane_state; 2814 struct intel_plane *plane; 2815 int i; 2816 2817 if (!crtc_state->enable_psr2_su_region_et) 2818 return; 2819 2820 for_each_new_intel_plane_in_state(state, plane, new_plane_state, i) { 2821 struct drm_rect inter; 2822 2823 if (new_plane_state->hw.crtc != crtc_state->uapi.crtc) 2824 continue; 2825 2826 if (plane->id != PLANE_CURSOR) 2827 continue; 2828 2829 if (!new_plane_state->uapi.visible) 2830 continue; 2831 2832 inter = crtc_state->psr2_su_area; 2833 if (!drm_rect_intersect(&inter, &new_plane_state->uapi.dst)) 2834 continue; 2835 2836 clip_area_update(&crtc_state->psr2_su_area, &new_plane_state->uapi.dst, 2837 display_area); 2838 *cursor_in_su_area = true; 2839 } 2840 } 2841 2842 /* 2843 * TODO: Not clear how to handle planes with negative position, 2844 * also planes are not updated if they have a negative X 2845 * position so for now doing a full update in this cases 2846 * 2847 * Plane scaling and rotation is not supported by selective fetch and both 2848 * properties can change without a modeset, so need to be check at every 2849 * atomic commit. 2850 */ 2851 static bool psr2_sel_fetch_plane_state_supported(const struct intel_plane_state *plane_state) 2852 { 2853 if (plane_state->uapi.dst.y1 < 0 || 2854 plane_state->uapi.dst.x1 < 0 || 2855 plane_state->scaler_id >= 0 || 2856 plane_state->hw.rotation != DRM_MODE_ROTATE_0) 2857 return false; 2858 2859 return true; 2860 } 2861 2862 /* 2863 * Check for pipe properties that is not supported by selective fetch. 2864 * 2865 * TODO: pipe scaling causes a modeset but skl_update_scaler_crtc() is executed 2866 * after intel_psr_compute_config(), so for now keeping PSR2 selective fetch 2867 * enabled and going to the full update path. 2868 */ 2869 static bool psr2_sel_fetch_pipe_state_supported(const struct intel_crtc_state *crtc_state) 2870 { 2871 if (crtc_state->scaler_state.scaler_id >= 0 || 2872 crtc_state->async_flip_planes) 2873 return false; 2874 2875 return true; 2876 } 2877 2878 /* Wa 14019834836 */ 2879 static void intel_psr_apply_pr_link_on_su_wa(struct intel_crtc_state *crtc_state) 2880 { 2881 struct intel_display *display = to_intel_display(crtc_state); 2882 struct intel_encoder *encoder; 2883 int hactive_limit; 2884 2885 if (crtc_state->psr2_su_area.y1 != 0 || 2886 crtc_state->psr2_su_area.y2 != 0) 2887 return; 2888 2889 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) 2890 hactive_limit = intel_dp_is_uhbr(crtc_state) ? 1230 : 546; 2891 else 2892 hactive_limit = intel_dp_is_uhbr(crtc_state) ? 615 : 273; 2893 2894 if (crtc_state->hw.adjusted_mode.hdisplay < hactive_limit) 2895 return; 2896 2897 for_each_intel_encoder_mask_with_psr(display->drm, encoder, 2898 crtc_state->uapi.encoder_mask) { 2899 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2900 2901 if (!intel_dp_is_edp(intel_dp) && 2902 intel_dp->psr.panel_replay_enabled && 2903 intel_dp->psr.sel_update_enabled) { 2904 crtc_state->psr2_su_area.y2++; 2905 return; 2906 } 2907 } 2908 } 2909 2910 static void 2911 intel_psr_apply_su_area_workarounds(struct intel_crtc_state *crtc_state) 2912 { 2913 struct intel_display *display = to_intel_display(crtc_state); 2914 2915 /* Wa_14014971492 */ 2916 if (!crtc_state->has_panel_replay && 2917 ((IS_DISPLAY_VERx100_STEP(display, 1400, STEP_A0, STEP_B0) || 2918 display->platform.alderlake_p || display->platform.tigerlake)) && 2919 crtc_state->splitter.enable) 2920 crtc_state->psr2_su_area.y1 = 0; 2921 2922 if (intel_display_wa(display, INTEL_DISPLAY_WA_16029024088) && 2923 crtc_state->req_psr2_sdp_prior_scanline && 2924 !crtc_state->enable_psr2_su_region_et) 2925 crtc_state->psr2_su_area.y1 = 0; 2926 2927 /* Wa 14019834836 */ 2928 if (DISPLAY_VER(display) == 30) 2929 intel_psr_apply_pr_link_on_su_wa(crtc_state); 2930 } 2931 2932 int intel_psr2_sel_fetch_update(struct intel_atomic_state *state, 2933 struct intel_crtc *crtc) 2934 { 2935 struct intel_display *display = to_intel_display(state); 2936 struct intel_crtc_state *crtc_state = intel_atomic_get_new_crtc_state(state, crtc); 2937 struct intel_plane_state *new_plane_state, *old_plane_state; 2938 struct intel_plane *plane; 2939 struct drm_rect display_area = { 2940 .x1 = 0, 2941 .y1 = 0, 2942 .x2 = crtc_state->hw.adjusted_mode.crtc_hdisplay, 2943 .y2 = crtc_state->hw.adjusted_mode.crtc_vdisplay, 2944 }; 2945 bool full_update = false, su_area_changed; 2946 int i, ret; 2947 2948 if (!crtc_state->enable_psr2_sel_fetch) 2949 return 0; 2950 2951 if (!psr2_sel_fetch_pipe_state_supported(crtc_state)) { 2952 full_update = true; 2953 goto skip_sel_fetch_set_loop; 2954 } 2955 2956 crtc_state->psr2_su_area.x1 = 0; 2957 crtc_state->psr2_su_area.y1 = -1; 2958 crtc_state->psr2_su_area.x2 = drm_rect_width(&display_area); 2959 crtc_state->psr2_su_area.y2 = -1; 2960 2961 /* 2962 * Calculate minimal selective fetch area of each plane and calculate 2963 * the pipe damaged area. 2964 * In the next loop the plane selective fetch area will actually be set 2965 * using whole pipe damaged area. 2966 */ 2967 for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state, 2968 new_plane_state, i) { 2969 struct drm_rect src, damaged_area = { .x1 = 0, .y1 = -1, 2970 .x2 = INT_MAX }; 2971 2972 if (new_plane_state->hw.crtc != crtc_state->uapi.crtc) 2973 continue; 2974 2975 if (!new_plane_state->uapi.visible && 2976 !old_plane_state->uapi.visible) 2977 continue; 2978 2979 if (!psr2_sel_fetch_plane_state_supported(new_plane_state)) { 2980 full_update = true; 2981 break; 2982 } 2983 2984 /* 2985 * If visibility or plane moved, mark the whole plane area as 2986 * damaged as it needs to be complete redraw in the new and old 2987 * position. 2988 */ 2989 if (new_plane_state->uapi.visible != old_plane_state->uapi.visible || 2990 !drm_rect_equals(&new_plane_state->uapi.dst, 2991 &old_plane_state->uapi.dst)) { 2992 if (old_plane_state->uapi.visible) { 2993 damaged_area.y1 = old_plane_state->uapi.dst.y1; 2994 damaged_area.y2 = old_plane_state->uapi.dst.y2; 2995 clip_area_update(&crtc_state->psr2_su_area, &damaged_area, 2996 &display_area); 2997 } 2998 2999 if (new_plane_state->uapi.visible) { 3000 damaged_area.y1 = new_plane_state->uapi.dst.y1; 3001 damaged_area.y2 = new_plane_state->uapi.dst.y2; 3002 clip_area_update(&crtc_state->psr2_su_area, &damaged_area, 3003 &display_area); 3004 } 3005 continue; 3006 } else if (new_plane_state->uapi.alpha != old_plane_state->uapi.alpha) { 3007 /* If alpha changed mark the whole plane area as damaged */ 3008 damaged_area.y1 = new_plane_state->uapi.dst.y1; 3009 damaged_area.y2 = new_plane_state->uapi.dst.y2; 3010 clip_area_update(&crtc_state->psr2_su_area, &damaged_area, 3011 &display_area); 3012 continue; 3013 } 3014 3015 src = drm_plane_state_src(&new_plane_state->uapi); 3016 drm_rect_fp_to_int(&src, &src); 3017 3018 if (!drm_atomic_helper_damage_merged(&old_plane_state->uapi, 3019 &new_plane_state->uapi, &damaged_area)) 3020 continue; 3021 3022 damaged_area.y1 += new_plane_state->uapi.dst.y1 - src.y1; 3023 damaged_area.y2 += new_plane_state->uapi.dst.y1 - src.y1; 3024 damaged_area.x1 += new_plane_state->uapi.dst.x1 - src.x1; 3025 damaged_area.x2 += new_plane_state->uapi.dst.x1 - src.x1; 3026 3027 clip_area_update(&crtc_state->psr2_su_area, &damaged_area, &display_area); 3028 } 3029 3030 /* 3031 * TODO: For now we are just using full update in case 3032 * selective fetch area calculation fails. To optimize this we 3033 * should identify cases where this happens and fix the area 3034 * calculation for those. 3035 */ 3036 if (crtc_state->psr2_su_area.y1 == -1) { 3037 drm_info_once(display->drm, 3038 "Selective fetch area calculation failed in pipe %c\n", 3039 pipe_name(crtc->pipe)); 3040 full_update = true; 3041 } 3042 3043 if (full_update) 3044 goto skip_sel_fetch_set_loop; 3045 3046 intel_psr_apply_su_area_workarounds(crtc_state); 3047 3048 ret = drm_atomic_add_affected_planes(&state->base, &crtc->base); 3049 if (ret) 3050 return ret; 3051 3052 do { 3053 bool cursor_in_su_area = false; 3054 3055 /* 3056 * Adjust su area to cover cursor fully as necessary 3057 * (early transport). This needs to be done after 3058 * drm_atomic_add_affected_planes to ensure visible 3059 * cursor is added into affected planes even when 3060 * cursor is not updated by itself. 3061 */ 3062 intel_psr2_sel_fetch_et_alignment(state, crtc, &display_area, 3063 &cursor_in_su_area); 3064 3065 su_area_changed = intel_psr2_sel_fetch_pipe_alignment(crtc_state); 3066 3067 /* 3068 * If the cursor was outside the SU area before 3069 * alignment, the alignment step (which only expands 3070 * SU) may pull the cursor partially inside, so we 3071 * must run ET alignment again to fully cover it. But 3072 * if the cursor was already fully inside before 3073 * alignment, expanding the SU area won't change that, 3074 * so no further work is needed. 3075 */ 3076 if (cursor_in_su_area) 3077 break; 3078 } while (su_area_changed); 3079 3080 /* 3081 * Now that we have the pipe damaged area check if it intersect with 3082 * every plane, if it does set the plane selective fetch area. 3083 */ 3084 for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state, 3085 new_plane_state, i) { 3086 struct drm_rect *sel_fetch_area, inter; 3087 struct intel_plane *linked = new_plane_state->planar_linked_plane; 3088 3089 if (new_plane_state->hw.crtc != crtc_state->uapi.crtc || 3090 !new_plane_state->uapi.visible) 3091 continue; 3092 3093 inter = crtc_state->psr2_su_area; 3094 sel_fetch_area = &new_plane_state->psr2_sel_fetch_area; 3095 if (!drm_rect_intersect(&inter, &new_plane_state->uapi.dst)) { 3096 sel_fetch_area->y1 = -1; 3097 sel_fetch_area->y2 = -1; 3098 /* 3099 * if plane sel fetch was previously enabled -> 3100 * disable it 3101 */ 3102 if (drm_rect_height(&old_plane_state->psr2_sel_fetch_area) > 0) 3103 crtc_state->update_planes |= BIT(plane->id); 3104 3105 continue; 3106 } 3107 3108 if (!psr2_sel_fetch_plane_state_supported(new_plane_state)) { 3109 full_update = true; 3110 break; 3111 } 3112 3113 sel_fetch_area = &new_plane_state->psr2_sel_fetch_area; 3114 sel_fetch_area->y1 = inter.y1 - new_plane_state->uapi.dst.y1; 3115 sel_fetch_area->y2 = inter.y2 - new_plane_state->uapi.dst.y1; 3116 crtc_state->update_planes |= BIT(plane->id); 3117 3118 /* 3119 * Sel_fetch_area is calculated for UV plane. Use 3120 * same area for Y plane as well. 3121 */ 3122 if (linked) { 3123 struct intel_plane_state *linked_new_plane_state; 3124 struct drm_rect *linked_sel_fetch_area; 3125 3126 linked_new_plane_state = intel_atomic_get_plane_state(state, linked); 3127 if (IS_ERR(linked_new_plane_state)) 3128 return PTR_ERR(linked_new_plane_state); 3129 3130 linked_sel_fetch_area = &linked_new_plane_state->psr2_sel_fetch_area; 3131 linked_sel_fetch_area->y1 = sel_fetch_area->y1; 3132 linked_sel_fetch_area->y2 = sel_fetch_area->y2; 3133 crtc_state->update_planes |= BIT(linked->id); 3134 } 3135 } 3136 3137 skip_sel_fetch_set_loop: 3138 if (full_update) 3139 clip_area_update(&crtc_state->psr2_su_area, &display_area, 3140 &display_area); 3141 3142 psr2_man_trk_ctl_calc(crtc_state, full_update); 3143 crtc_state->pipe_srcsz_early_tpt = 3144 psr2_pipe_srcsz_early_tpt_calc(crtc_state, full_update); 3145 return 0; 3146 } 3147 3148 void intel_psr2_panic_force_full_update(const struct intel_crtc_state *crtc_state) 3149 { 3150 struct intel_display *display = to_intel_display(crtc_state); 3151 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 3152 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 3153 u32 val = man_trk_ctl_enable_bit_get(display); 3154 3155 /* SF partial frame enable has to be set even on full update */ 3156 val |= man_trk_ctl_partial_frame_bit_get(display); 3157 val |= man_trk_ctl_continuos_full_frame(display); 3158 3159 /* Directly write the register */ 3160 intel_de_write_fw(display, PSR2_MAN_TRK_CTL(display, cpu_transcoder), val); 3161 3162 if (!crtc_state->enable_psr2_su_region_et) 3163 return; 3164 3165 intel_de_write_fw(display, PIPE_SRCSZ_ERLY_TPT(crtc->pipe), 0); 3166 } 3167 3168 void intel_psr_pre_plane_update(struct intel_atomic_state *state, 3169 struct intel_crtc *crtc) 3170 { 3171 struct intel_display *display = to_intel_display(state); 3172 const struct intel_crtc_state *old_crtc_state = 3173 intel_atomic_get_old_crtc_state(state, crtc); 3174 const struct intel_crtc_state *new_crtc_state = 3175 intel_atomic_get_new_crtc_state(state, crtc); 3176 struct intel_encoder *encoder; 3177 3178 if (!HAS_PSR(display)) 3179 return; 3180 3181 for_each_intel_encoder_mask_with_psr(state->base.dev, encoder, 3182 old_crtc_state->uapi.encoder_mask) { 3183 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 3184 struct intel_psr *psr = &intel_dp->psr; 3185 3186 mutex_lock(&psr->lock); 3187 3188 if (!new_crtc_state->has_psr) 3189 psr->no_psr_reason = new_crtc_state->no_psr_reason; 3190 3191 if (psr->enabled) { 3192 /* 3193 * Reasons to disable: 3194 * - PSR disabled in new state 3195 * - All planes will go inactive 3196 * - Changing between PSR versions 3197 * - Region Early Transport changing 3198 * - Display WA #1136: skl, bxt 3199 */ 3200 if (intel_crtc_needs_modeset(new_crtc_state) || 3201 new_crtc_state->update_m_n || 3202 new_crtc_state->update_lrr || 3203 !new_crtc_state->has_psr || 3204 !new_crtc_state->active_planes || 3205 new_crtc_state->has_sel_update != psr->sel_update_enabled || 3206 new_crtc_state->enable_psr2_su_region_et != psr->su_region_et_enabled || 3207 new_crtc_state->has_panel_replay != psr->panel_replay_enabled || 3208 (DISPLAY_VER(display) < 11 && new_crtc_state->wm_level_disabled)) 3209 intel_psr_disable_locked(intel_dp); 3210 else if (new_crtc_state->wm_level_disabled) 3211 /* Wa_14015648006 */ 3212 wm_optimization_wa(intel_dp, new_crtc_state); 3213 } 3214 3215 mutex_unlock(&psr->lock); 3216 } 3217 } 3218 3219 static void 3220 verify_panel_replay_dsc_state(const struct intel_crtc_state *crtc_state) 3221 { 3222 struct intel_display *display = to_intel_display(crtc_state); 3223 3224 if (!crtc_state->has_panel_replay) 3225 return; 3226 3227 drm_WARN_ON(display->drm, 3228 intel_dsc_enabled_on_link(crtc_state) && 3229 crtc_state->panel_replay_dsc_support == 3230 INTEL_DP_PANEL_REPLAY_DSC_NOT_SUPPORTED); 3231 } 3232 3233 void intel_psr_post_plane_update(struct intel_atomic_state *state, 3234 struct intel_crtc *crtc) 3235 { 3236 struct intel_display *display = to_intel_display(state); 3237 const struct intel_crtc_state *crtc_state = 3238 intel_atomic_get_new_crtc_state(state, crtc); 3239 struct intel_encoder *encoder; 3240 3241 if (!crtc_state->has_psr) 3242 return; 3243 3244 verify_panel_replay_dsc_state(crtc_state); 3245 3246 for_each_intel_encoder_mask_with_psr(state->base.dev, encoder, 3247 crtc_state->uapi.encoder_mask) { 3248 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 3249 struct intel_psr *psr = &intel_dp->psr; 3250 bool keep_disabled = false; 3251 3252 mutex_lock(&psr->lock); 3253 3254 drm_WARN_ON(display->drm, 3255 psr->enabled && !crtc_state->active_planes); 3256 3257 if (psr->sink_not_reliable) 3258 keep_disabled = true; 3259 3260 if (!crtc_state->active_planes) { 3261 psr->no_psr_reason = "All planes inactive"; 3262 keep_disabled = true; 3263 } 3264 3265 /* Display WA #1136: skl, bxt */ 3266 if (DISPLAY_VER(display) < 11 && crtc_state->wm_level_disabled) { 3267 psr->no_psr_reason = "Workaround #1136 for skl, bxt"; 3268 keep_disabled = true; 3269 } 3270 3271 if (!psr->enabled && !keep_disabled) 3272 intel_psr_enable_locked(intel_dp, crtc_state); 3273 else if (psr->enabled && !crtc_state->wm_level_disabled) 3274 /* Wa_14015648006 */ 3275 wm_optimization_wa(intel_dp, crtc_state); 3276 3277 /* Force a PSR exit when enabling CRC to avoid CRC timeouts */ 3278 if (crtc_state->crc_enabled && psr->enabled) 3279 intel_psr_force_update(intel_dp); 3280 3281 /* 3282 * Clear possible busy bits in case we have 3283 * invalidate -> flip -> flush sequence. 3284 */ 3285 intel_dp->psr.busy_frontbuffer_bits = 0; 3286 3287 mutex_unlock(&psr->lock); 3288 } 3289 } 3290 3291 /* 3292 * From bspec: Panel Self Refresh (BDW+) 3293 * Max. time for PSR to idle = Inverse of the refresh rate + 6 ms of 3294 * exit training time + 1.5 ms of aux channel handshake. 50 ms is 3295 * defensive enough to cover everything. 3296 */ 3297 #define PSR_IDLE_TIMEOUT_MS 50 3298 3299 static int 3300 _psr2_ready_for_pipe_update_locked(const struct intel_crtc_state *new_crtc_state, 3301 struct intel_dsb *dsb) 3302 { 3303 struct intel_display *display = to_intel_display(new_crtc_state); 3304 enum transcoder cpu_transcoder = new_crtc_state->cpu_transcoder; 3305 3306 /* 3307 * Any state lower than EDP_PSR2_STATUS_STATE_DEEP_SLEEP is enough. 3308 * As all higher states has bit 4 of PSR2 state set we can just wait for 3309 * EDP_PSR2_STATUS_STATE_DEEP_SLEEP to be cleared. 3310 */ 3311 if (dsb) { 3312 intel_dsb_poll(dsb, EDP_PSR2_STATUS(display, cpu_transcoder), 3313 EDP_PSR2_STATUS_STATE_DEEP_SLEEP, 0, 200, 3314 PSR_IDLE_TIMEOUT_MS * 1000 / 200); 3315 return true; 3316 } 3317 3318 return intel_de_wait_for_clear_ms(display, 3319 EDP_PSR2_STATUS(display, cpu_transcoder), 3320 EDP_PSR2_STATUS_STATE_DEEP_SLEEP, 3321 PSR_IDLE_TIMEOUT_MS); 3322 } 3323 3324 static int 3325 _psr1_ready_for_pipe_update_locked(const struct intel_crtc_state *new_crtc_state, 3326 struct intel_dsb *dsb) 3327 { 3328 struct intel_display *display = to_intel_display(new_crtc_state); 3329 enum transcoder cpu_transcoder = new_crtc_state->cpu_transcoder; 3330 3331 if (dsb) { 3332 intel_dsb_poll(dsb, psr_status_reg(display, cpu_transcoder), 3333 EDP_PSR_STATUS_STATE_MASK, 0, 200, 3334 PSR_IDLE_TIMEOUT_MS * 1000 / 200); 3335 return true; 3336 } 3337 3338 return intel_de_wait_for_clear_ms(display, 3339 psr_status_reg(display, cpu_transcoder), 3340 EDP_PSR_STATUS_STATE_MASK, 3341 PSR_IDLE_TIMEOUT_MS); 3342 } 3343 3344 /** 3345 * intel_psr_wait_for_idle_locked - wait for PSR be ready for a pipe update 3346 * @new_crtc_state: new CRTC state 3347 * 3348 * This function is expected to be called from pipe_update_start() where it is 3349 * not expected to race with PSR enable or disable. 3350 */ 3351 void intel_psr_wait_for_idle_locked(const struct intel_crtc_state *new_crtc_state) 3352 { 3353 struct intel_display *display = to_intel_display(new_crtc_state); 3354 struct intel_encoder *encoder; 3355 3356 if (!new_crtc_state->has_psr) 3357 return; 3358 3359 for_each_intel_encoder_mask_with_psr(display->drm, encoder, 3360 new_crtc_state->uapi.encoder_mask) { 3361 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 3362 int ret; 3363 3364 lockdep_assert_held(&intel_dp->psr.lock); 3365 3366 if (!intel_dp->psr.enabled || intel_dp->psr.panel_replay_enabled) 3367 continue; 3368 3369 if (intel_dp->psr.sel_update_enabled) 3370 ret = _psr2_ready_for_pipe_update_locked(new_crtc_state, 3371 NULL); 3372 else 3373 ret = _psr1_ready_for_pipe_update_locked(new_crtc_state, 3374 NULL); 3375 3376 if (ret) 3377 drm_err(display->drm, 3378 "PSR wait timed out, atomic update may fail\n"); 3379 } 3380 } 3381 3382 void intel_psr_wait_for_idle_dsb(struct intel_dsb *dsb, 3383 const struct intel_crtc_state *new_crtc_state) 3384 { 3385 if (!new_crtc_state->has_psr || new_crtc_state->has_panel_replay) 3386 return; 3387 3388 if (new_crtc_state->has_sel_update) 3389 _psr2_ready_for_pipe_update_locked(new_crtc_state, dsb); 3390 else 3391 _psr1_ready_for_pipe_update_locked(new_crtc_state, dsb); 3392 } 3393 3394 static bool __psr_wait_for_idle_locked(struct intel_dp *intel_dp) 3395 { 3396 struct intel_display *display = to_intel_display(intel_dp); 3397 enum transcoder cpu_transcoder = intel_dp->psr.transcoder; 3398 intel_reg_t reg; 3399 u32 mask; 3400 int err; 3401 3402 if (!intel_dp->psr.enabled) 3403 return false; 3404 3405 if (intel_dp_is_edp(intel_dp) && (intel_dp->psr.sel_update_enabled || 3406 intel_dp->psr.panel_replay_enabled)) { 3407 reg = EDP_PSR2_STATUS(display, cpu_transcoder); 3408 mask = EDP_PSR2_STATUS_STATE_MASK; 3409 } else { 3410 reg = psr_status_reg(display, cpu_transcoder); 3411 mask = EDP_PSR_STATUS_STATE_MASK; 3412 } 3413 3414 mutex_unlock(&intel_dp->psr.lock); 3415 3416 err = intel_de_wait_for_clear_ms(display, reg, mask, 50); 3417 if (err) 3418 drm_err(display->drm, 3419 "Timed out waiting for PSR Idle for re-enable\n"); 3420 3421 /* After the unlocked wait, verify that PSR is still wanted! */ 3422 mutex_lock(&intel_dp->psr.lock); 3423 return err == 0 && intel_dp->psr.enabled && !intel_dp->psr.pause_counter; 3424 } 3425 3426 static int intel_psr_fastset_force(struct intel_display *display) 3427 { 3428 struct drm_connector_list_iter conn_iter; 3429 struct drm_modeset_acquire_ctx ctx; 3430 struct drm_atomic_commit *state; 3431 struct drm_connector *conn; 3432 int err = 0; 3433 3434 state = drm_atomic_commit_alloc(display->drm); 3435 if (!state) 3436 return -ENOMEM; 3437 3438 drm_modeset_acquire_init(&ctx, DRM_MODESET_ACQUIRE_INTERRUPTIBLE); 3439 3440 state->acquire_ctx = &ctx; 3441 to_intel_atomic_state(state)->internal = true; 3442 3443 retry: 3444 drm_connector_list_iter_begin(display->drm, &conn_iter); 3445 drm_for_each_connector_iter(conn, &conn_iter) { 3446 struct drm_connector_state *conn_state; 3447 struct drm_crtc_state *crtc_state; 3448 3449 if (conn->connector_type != DRM_MODE_CONNECTOR_eDP) 3450 continue; 3451 3452 conn_state = drm_atomic_get_connector_state(state, conn); 3453 if (IS_ERR(conn_state)) { 3454 err = PTR_ERR(conn_state); 3455 break; 3456 } 3457 3458 if (!conn_state->crtc) 3459 continue; 3460 3461 crtc_state = drm_atomic_get_crtc_state(state, conn_state->crtc); 3462 if (IS_ERR(crtc_state)) { 3463 err = PTR_ERR(crtc_state); 3464 break; 3465 } 3466 3467 /* Mark mode as changed to trigger a pipe->update() */ 3468 crtc_state->mode_changed = true; 3469 } 3470 drm_connector_list_iter_end(&conn_iter); 3471 3472 if (err == 0) 3473 err = drm_atomic_commit(state); 3474 3475 if (err == -EDEADLK) { 3476 drm_atomic_commit_clear(state); 3477 err = drm_modeset_backoff(&ctx); 3478 if (!err) 3479 goto retry; 3480 } 3481 3482 drm_modeset_drop_locks(&ctx); 3483 drm_modeset_acquire_fini(&ctx); 3484 drm_atomic_commit_put(state); 3485 3486 return err; 3487 } 3488 3489 int intel_psr_debug_set(struct intel_dp *intel_dp, u64 val) 3490 { 3491 struct intel_display *display = to_intel_display(intel_dp); 3492 const u32 mode = val & I915_PSR_DEBUG_MODE_MASK; 3493 const u32 disable_bits = val & (I915_PSR_DEBUG_SU_REGION_ET_DISABLE | 3494 I915_PSR_DEBUG_PANEL_REPLAY_DISABLE); 3495 u32 old_mode, old_disable_bits; 3496 int ret; 3497 3498 if (val & ~(I915_PSR_DEBUG_IRQ | I915_PSR_DEBUG_SU_REGION_ET_DISABLE | 3499 I915_PSR_DEBUG_PANEL_REPLAY_DISABLE | 3500 I915_PSR_DEBUG_MODE_MASK) || 3501 mode > I915_PSR_DEBUG_ENABLE_SEL_FETCH) { 3502 drm_dbg_kms(display->drm, "Invalid debug mask %llx\n", val); 3503 return -EINVAL; 3504 } 3505 3506 ret = mutex_lock_interruptible(&intel_dp->psr.lock); 3507 if (ret) 3508 return ret; 3509 3510 old_mode = intel_dp->psr.debug & I915_PSR_DEBUG_MODE_MASK; 3511 old_disable_bits = intel_dp->psr.debug & 3512 (I915_PSR_DEBUG_SU_REGION_ET_DISABLE | 3513 I915_PSR_DEBUG_PANEL_REPLAY_DISABLE); 3514 3515 intel_dp->psr.debug = val; 3516 3517 /* 3518 * Do it right away if it's already enabled, otherwise it will be done 3519 * when enabling the source. 3520 */ 3521 if (intel_dp->psr.enabled) 3522 psr_irq_control(intel_dp); 3523 3524 mutex_unlock(&intel_dp->psr.lock); 3525 3526 if (old_mode != mode || old_disable_bits != disable_bits) 3527 ret = intel_psr_fastset_force(display); 3528 3529 return ret; 3530 } 3531 3532 static void intel_psr_handle_irq(struct intel_dp *intel_dp) 3533 { 3534 struct intel_psr *psr = &intel_dp->psr; 3535 3536 intel_psr_disable_locked(intel_dp); 3537 psr->sink_not_reliable = true; 3538 /* let's make sure that sink is awaken */ 3539 drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, DP_SET_POWER_D0); 3540 } 3541 3542 static void intel_psr_work(struct work_struct *work) 3543 { 3544 struct intel_dp *intel_dp = 3545 container_of(work, typeof(*intel_dp), psr.work); 3546 3547 mutex_lock(&intel_dp->psr.lock); 3548 3549 if (!intel_dp->psr.enabled) 3550 goto unlock; 3551 3552 if (READ_ONCE(intel_dp->psr.irq_aux_error)) { 3553 intel_psr_handle_irq(intel_dp); 3554 goto unlock; 3555 } 3556 3557 if (intel_dp->psr.pause_counter) 3558 goto unlock; 3559 3560 /* 3561 * We have to make sure PSR is ready for re-enable 3562 * otherwise it keeps disabled until next full enable/disable cycle. 3563 * PSR might take some time to get fully disabled 3564 * and be ready for re-enable. 3565 */ 3566 if (!__psr_wait_for_idle_locked(intel_dp)) 3567 goto unlock; 3568 3569 /* 3570 * The delayed work can race with an invalidate hence we need to 3571 * recheck. Since psr_flush first clears this and then reschedules we 3572 * won't ever miss a flush when bailing out here. 3573 */ 3574 if (intel_dp->psr.busy_frontbuffer_bits || intel_dp->psr.active) 3575 goto unlock; 3576 3577 intel_psr_activate(intel_dp); 3578 unlock: 3579 mutex_unlock(&intel_dp->psr.lock); 3580 } 3581 3582 static void intel_psr_configure_full_frame_update(struct intel_dp *intel_dp) 3583 { 3584 struct intel_display *display = to_intel_display(intel_dp); 3585 enum transcoder cpu_transcoder = intel_dp->psr.transcoder; 3586 3587 if (!intel_dp->psr.psr2_sel_fetch_enabled) 3588 return; 3589 3590 if (DISPLAY_VER(display) >= 20) 3591 intel_de_write(display, LNL_SFF_CTL(cpu_transcoder), 3592 LNL_SFF_CTL_SF_SINGLE_FULL_FRAME); 3593 else 3594 intel_de_write(display, 3595 PSR2_MAN_TRK_CTL(display, cpu_transcoder), 3596 man_trk_ctl_enable_bit_get(display) | 3597 man_trk_ctl_partial_frame_bit_get(display) | 3598 man_trk_ctl_single_full_frame_bit_get(display) | 3599 man_trk_ctl_continuos_full_frame(display)); 3600 } 3601 3602 static void _psr_invalidate_handle(struct intel_dp *intel_dp) 3603 { 3604 struct intel_display *display = to_intel_display(intel_dp); 3605 3606 if (DISPLAY_VER(display) < 20 && intel_dp->psr.psr2_sel_fetch_enabled) { 3607 if (!intel_dp->psr.psr2_sel_fetch_cff_enabled) { 3608 intel_dp->psr.psr2_sel_fetch_cff_enabled = true; 3609 intel_psr_configure_full_frame_update(intel_dp); 3610 } 3611 3612 intel_psr_force_update(intel_dp); 3613 } else { 3614 intel_psr_exit(intel_dp); 3615 } 3616 } 3617 3618 /** 3619 * intel_psr_invalidate - Invalidate PSR 3620 * @display: display device 3621 * @frontbuffer_bits: frontbuffer plane tracking bits 3622 * @origin: which operation caused the invalidate 3623 * 3624 * Since the hardware frontbuffer tracking has gaps we need to integrate 3625 * with the software frontbuffer tracking. This function gets called every 3626 * time frontbuffer rendering starts and a buffer gets dirtied. PSR must be 3627 * disabled if the frontbuffer mask contains a buffer relevant to PSR. 3628 * 3629 * Dirty frontbuffers relevant to PSR are tracked in busy_frontbuffer_bits." 3630 */ 3631 void intel_psr_invalidate(struct intel_display *display, 3632 unsigned frontbuffer_bits, enum fb_op_origin origin) 3633 { 3634 struct intel_encoder *encoder; 3635 3636 if (origin == ORIGIN_FLIP) 3637 return; 3638 3639 for_each_intel_encoder_with_psr(display->drm, encoder) { 3640 unsigned int pipe_frontbuffer_bits = frontbuffer_bits; 3641 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 3642 3643 mutex_lock(&intel_dp->psr.lock); 3644 if (!intel_dp->psr.enabled) { 3645 mutex_unlock(&intel_dp->psr.lock); 3646 continue; 3647 } 3648 3649 pipe_frontbuffer_bits &= 3650 INTEL_FRONTBUFFER_ALL_MASK(intel_dp->psr.pipe); 3651 intel_dp->psr.busy_frontbuffer_bits |= pipe_frontbuffer_bits; 3652 3653 if (pipe_frontbuffer_bits) 3654 _psr_invalidate_handle(intel_dp); 3655 3656 mutex_unlock(&intel_dp->psr.lock); 3657 } 3658 } 3659 /* 3660 * When we will be completely rely on PSR2 S/W tracking in future, 3661 * intel_psr_flush() will invalidate and flush the PSR for ORIGIN_FLIP 3662 * event also therefore tgl_dc3co_flush_locked() require to be changed 3663 * accordingly in future. 3664 */ 3665 static void 3666 tgl_dc3co_flush_locked(struct intel_dp *intel_dp, unsigned int frontbuffer_bits, 3667 enum fb_op_origin origin) 3668 { 3669 struct intel_display *display = to_intel_display(intel_dp); 3670 3671 if (!intel_dp->psr.dc3co_exitline || !intel_dp->psr.sel_update_enabled || 3672 !intel_dp->psr.active) 3673 return; 3674 3675 /* 3676 * At every frontbuffer flush flip event modified delay of delayed work, 3677 * when delayed work schedules that means display has been idle. 3678 */ 3679 if (!(frontbuffer_bits & 3680 INTEL_FRONTBUFFER_ALL_MASK(intel_dp->psr.pipe))) 3681 return; 3682 3683 tgl_psr2_enable_dc3co(intel_dp); 3684 mod_delayed_work(display->wq.unordered, &intel_dp->psr.dc3co_work, 3685 intel_dp->psr.dc3co_exit_delay); 3686 } 3687 3688 static void _psr_flush_handle(struct intel_dp *intel_dp) 3689 { 3690 struct intel_display *display = to_intel_display(intel_dp); 3691 3692 if (DISPLAY_VER(display) >= 20) { 3693 /* 3694 * We can use PSR exit on LunarLake onwards. Also 3695 * using trans push mechanism to trigger Frame Change 3696 * event requires using PSR exit. 3697 */ 3698 intel_psr_exit(intel_dp); 3699 } else if (intel_dp->psr.psr2_sel_fetch_enabled) { 3700 /* Selective fetch prior LNL */ 3701 if (intel_dp->psr.psr2_sel_fetch_cff_enabled) { 3702 /* can we turn CFF off? */ 3703 if (intel_dp->psr.busy_frontbuffer_bits == 0) 3704 intel_dp->psr.psr2_sel_fetch_cff_enabled = false; 3705 } 3706 3707 /* 3708 * Still keep cff bit enabled as we don't have proper SU 3709 * configuration in case update is sent for any reason after 3710 * sff bit gets cleared by the HW on next vblank. 3711 * 3712 * NOTE: Setting cff bit is not needed for LunarLake onwards as 3713 * we have own register for SFF bit and we are not overwriting 3714 * existing SU configuration 3715 */ 3716 intel_psr_configure_full_frame_update(intel_dp); 3717 3718 intel_psr_force_update(intel_dp); 3719 } else { 3720 /* 3721 * On older platforms using PSR exit was seen causing problems 3722 */ 3723 intel_psr_force_update(intel_dp); 3724 } 3725 3726 if (!intel_dp->psr.active && !intel_dp->psr.busy_frontbuffer_bits) 3727 queue_work(display->wq.unordered, &intel_dp->psr.work); 3728 } 3729 3730 /** 3731 * intel_psr_flush - Flush PSR 3732 * @display: display device 3733 * @frontbuffer_bits: frontbuffer plane tracking bits 3734 * @origin: which operation caused the flush 3735 * 3736 * Since the hardware frontbuffer tracking has gaps we need to integrate 3737 * with the software frontbuffer tracking. This function gets called every 3738 * time frontbuffer rendering has completed and flushed out to memory. PSR 3739 * can be enabled again if no other frontbuffer relevant to PSR is dirty. 3740 * 3741 * Dirty frontbuffers relevant to PSR are tracked in busy_frontbuffer_bits. 3742 */ 3743 void intel_psr_flush(struct intel_display *display, 3744 unsigned frontbuffer_bits, enum fb_op_origin origin) 3745 { 3746 struct intel_encoder *encoder; 3747 3748 for_each_intel_encoder_with_psr(display->drm, encoder) { 3749 unsigned int pipe_frontbuffer_bits = frontbuffer_bits; 3750 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 3751 3752 mutex_lock(&intel_dp->psr.lock); 3753 if (!intel_dp->psr.enabled) { 3754 mutex_unlock(&intel_dp->psr.lock); 3755 continue; 3756 } 3757 3758 pipe_frontbuffer_bits &= 3759 INTEL_FRONTBUFFER_ALL_MASK(intel_dp->psr.pipe); 3760 intel_dp->psr.busy_frontbuffer_bits &= ~pipe_frontbuffer_bits; 3761 3762 /* 3763 * If the PSR is paused by an explicit intel_psr_paused() call, 3764 * we have to ensure that the PSR is not activated until 3765 * intel_psr_resume() is called. 3766 */ 3767 if (intel_dp->psr.pause_counter) 3768 goto unlock; 3769 3770 if (origin == ORIGIN_FLIP || 3771 (origin == ORIGIN_CURSOR_UPDATE && 3772 !intel_dp->psr.psr2_sel_fetch_enabled)) { 3773 tgl_dc3co_flush_locked(intel_dp, frontbuffer_bits, origin); 3774 goto unlock; 3775 } 3776 3777 if (pipe_frontbuffer_bits == 0) 3778 goto unlock; 3779 3780 /* By definition flush = invalidate + flush */ 3781 _psr_flush_handle(intel_dp); 3782 unlock: 3783 mutex_unlock(&intel_dp->psr.lock); 3784 } 3785 } 3786 3787 /** 3788 * intel_psr_init - Init basic PSR work and mutex. 3789 * @intel_dp: Intel DP 3790 * 3791 * This function is called after the initializing connector. 3792 * (the initializing of connector treats the handling of connector capabilities) 3793 * And it initializes basic PSR stuff for each DP Encoder. 3794 */ 3795 void intel_psr_init(struct intel_dp *intel_dp) 3796 { 3797 struct intel_display *display = to_intel_display(intel_dp); 3798 struct intel_connector *connector = intel_dp->attached_connector; 3799 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 3800 3801 if (!(HAS_PSR(display) || HAS_DP20(display))) 3802 return; 3803 3804 /* 3805 * HSW spec explicitly says PSR is tied to port A. 3806 * BDW+ platforms have a instance of PSR registers per transcoder but 3807 * BDW, GEN9 and GEN11 are not validated by HW team in other transcoder 3808 * than eDP one. 3809 * For now it only supports one instance of PSR for BDW, GEN9 and GEN11. 3810 * So lets keep it hardcoded to PORT_A for BDW, GEN9 and GEN11. 3811 * But GEN12 supports a instance of PSR registers per transcoder. 3812 */ 3813 if (DISPLAY_VER(display) < 12 && dig_port->base.port != PORT_A) { 3814 drm_dbg_kms(display->drm, 3815 "PSR condition failed: Port not supported\n"); 3816 return; 3817 } 3818 3819 if ((HAS_DP20(display) && !intel_dp_is_edp(intel_dp)) || 3820 DISPLAY_VER(display) >= 20) 3821 intel_dp->psr.source_panel_replay_support = true; 3822 3823 if (HAS_PSR(display) && intel_dp_is_edp(intel_dp)) 3824 intel_dp->psr.source_support = true; 3825 3826 /* Set link_standby x link_off defaults */ 3827 if (DISPLAY_VER(display) < 12) 3828 /* For new platforms up to TGL let's respect VBT back again */ 3829 intel_dp->psr.link_standby = connector->panel.vbt.psr.full_link; 3830 3831 INIT_WORK(&intel_dp->psr.work, intel_psr_work); 3832 INIT_DELAYED_WORK(&intel_dp->psr.dc3co_work, tgl_dc3co_disable_work); 3833 mutex_init(&intel_dp->psr.lock); 3834 } 3835 3836 static int psr_get_status_and_error_status(struct intel_dp *intel_dp, 3837 u8 *status, u8 *error_status) 3838 { 3839 struct drm_dp_aux *aux = &intel_dp->aux; 3840 int ret; 3841 unsigned int offset; 3842 3843 offset = intel_dp->psr.panel_replay_enabled ? 3844 DP_SINK_DEVICE_PR_AND_FRAME_LOCK_STATUS : DP_PSR_STATUS; 3845 3846 ret = drm_dp_dpcd_readb(aux, offset, status); 3847 if (ret != 1) 3848 return ret; 3849 3850 offset = intel_dp->psr.panel_replay_enabled ? 3851 DP_PANEL_REPLAY_ERROR_STATUS : DP_PSR_ERROR_STATUS; 3852 3853 ret = drm_dp_dpcd_readb(aux, offset, error_status); 3854 if (ret != 1) 3855 return ret; 3856 3857 *status = *status & DP_PSR_SINK_STATE_MASK; 3858 3859 return 0; 3860 } 3861 3862 static void psr_alpm_check(struct intel_dp *intel_dp) 3863 { 3864 struct intel_psr *psr = &intel_dp->psr; 3865 3866 if (!psr->sel_update_enabled) 3867 return; 3868 3869 if (intel_alpm_get_error(intel_dp)) { 3870 intel_psr_disable_locked(intel_dp); 3871 psr->sink_not_reliable = true; 3872 } 3873 } 3874 3875 static void psr_capability_changed_check(struct intel_dp *intel_dp) 3876 { 3877 struct intel_display *display = to_intel_display(intel_dp); 3878 struct intel_psr *psr = &intel_dp->psr; 3879 u8 val; 3880 int r; 3881 3882 r = drm_dp_dpcd_readb(&intel_dp->aux, DP_PSR_ESI, &val); 3883 if (r != 1) { 3884 drm_err(display->drm, "Error reading DP_PSR_ESI\n"); 3885 return; 3886 } 3887 3888 if (val & DP_PSR_CAPS_CHANGE) { 3889 intel_psr_disable_locked(intel_dp); 3890 psr->sink_not_reliable = true; 3891 drm_dbg_kms(display->drm, 3892 "Sink PSR capability changed, disabling PSR\n"); 3893 3894 /* Clearing it */ 3895 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_ESI, val); 3896 } 3897 } 3898 3899 /* 3900 * On common bits: 3901 * DP_PSR_RFB_STORAGE_ERROR == DP_PANEL_REPLAY_RFB_STORAGE_ERROR 3902 * DP_PSR_VSC_SDP_UNCORRECTABLE_ERROR == DP_PANEL_REPLAY_VSC_SDP_UNCORRECTABLE_ERROR 3903 * DP_PSR_LINK_CRC_ERROR == DP_PANEL_REPLAY_LINK_CRC_ERROR 3904 * this function is relying on PSR definitions 3905 */ 3906 void intel_psr_short_pulse(struct intel_dp *intel_dp) 3907 { 3908 struct intel_display *display = to_intel_display(intel_dp); 3909 struct intel_psr *psr = &intel_dp->psr; 3910 u8 status, error_status; 3911 const u8 errors = DP_PSR_RFB_STORAGE_ERROR | 3912 DP_PSR_VSC_SDP_UNCORRECTABLE_ERROR | 3913 DP_PSR_LINK_CRC_ERROR; 3914 3915 if (!CAN_PSR(intel_dp) && !CAN_PANEL_REPLAY(intel_dp)) 3916 return; 3917 3918 mutex_lock(&psr->lock); 3919 3920 psr->link_ok = false; 3921 3922 if (!psr->enabled) 3923 goto exit; 3924 3925 if (psr_get_status_and_error_status(intel_dp, &status, &error_status)) { 3926 drm_err(display->drm, 3927 "Error reading PSR status or error status\n"); 3928 goto exit; 3929 } 3930 3931 if ((!psr->panel_replay_enabled && status == DP_PSR_SINK_INTERNAL_ERROR) || 3932 (error_status & errors)) { 3933 intel_psr_disable_locked(intel_dp); 3934 psr->sink_not_reliable = true; 3935 } 3936 3937 if (!psr->panel_replay_enabled && status == DP_PSR_SINK_INTERNAL_ERROR && 3938 !error_status) 3939 drm_dbg_kms(display->drm, 3940 "PSR sink internal error, disabling PSR\n"); 3941 if (error_status & DP_PSR_RFB_STORAGE_ERROR) 3942 drm_dbg_kms(display->drm, 3943 "PSR RFB storage error, disabling PSR\n"); 3944 if (error_status & DP_PSR_VSC_SDP_UNCORRECTABLE_ERROR) 3945 drm_dbg_kms(display->drm, 3946 "PSR VSC SDP uncorrectable error, disabling PSR\n"); 3947 if (error_status & DP_PSR_LINK_CRC_ERROR) 3948 drm_dbg_kms(display->drm, 3949 "PSR Link CRC error, disabling PSR\n"); 3950 3951 if (error_status & ~errors) 3952 drm_err(display->drm, 3953 "PSR_ERROR_STATUS unhandled errors %x\n", 3954 error_status & ~errors); 3955 /* clear status register */ 3956 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_ERROR_STATUS, error_status); 3957 3958 if (!psr->panel_replay_enabled) { 3959 psr_alpm_check(intel_dp); 3960 psr_capability_changed_check(intel_dp); 3961 } 3962 3963 exit: 3964 mutex_unlock(&psr->lock); 3965 } 3966 3967 bool intel_psr_enabled(struct intel_dp *intel_dp) 3968 { 3969 bool ret; 3970 3971 if (!CAN_PSR(intel_dp)) 3972 return false; 3973 3974 mutex_lock(&intel_dp->psr.lock); 3975 ret = intel_dp->psr.enabled; 3976 mutex_unlock(&intel_dp->psr.lock); 3977 3978 return ret; 3979 } 3980 3981 /** 3982 * intel_psr_link_ok - return psr->link_ok 3983 * @intel_dp: struct intel_dp 3984 * 3985 * We are seeing unexpected link re-trainings with some panels. This is caused 3986 * by panel stating bad link status after PSR is enabled. Code checking link 3987 * status can call this to ensure it can ignore bad link status stated by the 3988 * panel I.e. if panel is stating bad link and intel_psr_link_ok is stating link 3989 * is ok caller should rely on latter. 3990 * 3991 * Return value of link_ok 3992 */ 3993 bool intel_psr_link_ok(struct intel_dp *intel_dp) 3994 { 3995 bool ret; 3996 3997 if ((!CAN_PSR(intel_dp) && !CAN_PANEL_REPLAY(intel_dp)) || 3998 !intel_dp_is_edp(intel_dp)) 3999 return false; 4000 4001 mutex_lock(&intel_dp->psr.lock); 4002 ret = intel_dp->psr.link_ok; 4003 mutex_unlock(&intel_dp->psr.lock); 4004 4005 return ret; 4006 } 4007 4008 /** 4009 * intel_psr_lock - grab PSR lock 4010 * @crtc_state: the crtc state 4011 * 4012 * This is initially meant to be used by around CRTC update, when 4013 * vblank sensitive registers are updated and we need grab the lock 4014 * before it to avoid vblank evasion. 4015 */ 4016 void intel_psr_lock(const struct intel_crtc_state *crtc_state) 4017 { 4018 struct intel_display *display = to_intel_display(crtc_state); 4019 struct intel_encoder *encoder; 4020 4021 if (!crtc_state->has_psr) 4022 return; 4023 4024 for_each_intel_encoder_mask_with_psr(display->drm, encoder, 4025 crtc_state->uapi.encoder_mask) { 4026 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 4027 4028 mutex_lock(&intel_dp->psr.lock); 4029 break; 4030 } 4031 } 4032 4033 /** 4034 * intel_psr_unlock - release PSR lock 4035 * @crtc_state: the crtc state 4036 * 4037 * Release the PSR lock that was held during pipe update. 4038 */ 4039 void intel_psr_unlock(const struct intel_crtc_state *crtc_state) 4040 { 4041 struct intel_display *display = to_intel_display(crtc_state); 4042 struct intel_encoder *encoder; 4043 4044 if (!crtc_state->has_psr) 4045 return; 4046 4047 for_each_intel_encoder_mask_with_psr(display->drm, encoder, 4048 crtc_state->uapi.encoder_mask) { 4049 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 4050 4051 mutex_unlock(&intel_dp->psr.lock); 4052 break; 4053 } 4054 } 4055 4056 /* Wa_16025596647 */ 4057 static void intel_psr_apply_underrun_on_idle_wa_locked(struct intel_dp *intel_dp) 4058 { 4059 struct intel_display *display = to_intel_display(intel_dp); 4060 bool dc5_dc6_blocked; 4061 4062 if (!intel_dp->psr.active || !intel_dp->psr.pkg_c_latency_used) 4063 return; 4064 4065 dc5_dc6_blocked = is_dc5_dc6_blocked(intel_dp); 4066 4067 if (intel_dp->psr.sel_update_enabled) 4068 psr2_program_idle_frames(intel_dp, dc5_dc6_blocked ? 0 : 4069 psr_compute_idle_frames(intel_dp)); 4070 else 4071 intel_dmc_start_pkgc_exit_at_start_of_undelayed_vblank(display, 4072 intel_dp->psr.pipe, 4073 dc5_dc6_blocked); 4074 } 4075 4076 static void psr_dc5_dc6_wa_work(struct work_struct *work) 4077 { 4078 struct intel_display *display = container_of(work, typeof(*display), 4079 psr_dc5_dc6_wa_work); 4080 struct intel_encoder *encoder; 4081 4082 for_each_intel_encoder_with_psr(display->drm, encoder) { 4083 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 4084 4085 mutex_lock(&intel_dp->psr.lock); 4086 4087 if (intel_dp->psr.enabled && !intel_dp->psr.panel_replay_enabled && 4088 !intel_dp->psr.pkg_c_latency_used) 4089 intel_psr_apply_underrun_on_idle_wa_locked(intel_dp); 4090 4091 mutex_unlock(&intel_dp->psr.lock); 4092 } 4093 } 4094 4095 /** 4096 * intel_psr_notify_dc5_dc6 - Notify PSR about enable/disable dc5/dc6 4097 * @display: intel atomic state 4098 * 4099 * This is targeted for underrun on idle PSR HW bug (Wa_16025596647) to schedule 4100 * psr_dc5_dc6_wa_work used for applying/removing the workaround. 4101 */ 4102 void intel_psr_notify_dc5_dc6(struct intel_display *display) 4103 { 4104 if (!intel_display_wa(display, INTEL_DISPLAY_WA_16025596647)) 4105 return; 4106 4107 schedule_work(&display->psr_dc5_dc6_wa_work); 4108 } 4109 4110 /** 4111 * intel_psr_dc5_dc6_wa_init - Init work for underrun on idle PSR HW bug wa 4112 * @display: intel atomic state 4113 * 4114 * This is targeted for underrun on idle PSR HW bug (Wa_16025596647) to init 4115 * psr_dc5_dc6_wa_work used for applying the workaround. 4116 */ 4117 void intel_psr_dc5_dc6_wa_init(struct intel_display *display) 4118 { 4119 if (!intel_display_wa(display, INTEL_DISPLAY_WA_16025596647)) 4120 return; 4121 4122 INIT_WORK(&display->psr_dc5_dc6_wa_work, psr_dc5_dc6_wa_work); 4123 } 4124 4125 /** 4126 * intel_psr_notify_pipe_change - Notify PSR about enable/disable of a pipe 4127 * @state: intel atomic state 4128 * @crtc: intel crtc 4129 * @enable: enable/disable 4130 * 4131 * This is targeted for underrun on idle PSR HW bug (Wa_16025596647) to apply 4132 * remove the workaround when pipe is getting enabled/disabled 4133 */ 4134 void intel_psr_notify_pipe_change(struct intel_atomic_state *state, 4135 struct intel_crtc *crtc, bool enable) 4136 { 4137 struct intel_display *display = to_intel_display(state); 4138 struct intel_encoder *encoder; 4139 4140 if (!intel_display_wa(display, INTEL_DISPLAY_WA_16025596647)) 4141 return; 4142 4143 for_each_intel_encoder_with_psr(display->drm, encoder) { 4144 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 4145 u8 active_non_psr_pipes; 4146 4147 mutex_lock(&intel_dp->psr.lock); 4148 4149 if (!intel_dp->psr.enabled || intel_dp->psr.panel_replay_enabled) 4150 goto unlock; 4151 4152 active_non_psr_pipes = intel_dp->psr.active_non_psr_pipes; 4153 4154 if (enable) 4155 active_non_psr_pipes |= BIT(crtc->pipe); 4156 else 4157 active_non_psr_pipes &= ~BIT(crtc->pipe); 4158 4159 if (active_non_psr_pipes == intel_dp->psr.active_non_psr_pipes) 4160 goto unlock; 4161 4162 if ((enable && intel_dp->psr.active_non_psr_pipes) || 4163 (!enable && !intel_dp->psr.active_non_psr_pipes) || 4164 !intel_dp->psr.pkg_c_latency_used) { 4165 intel_dp->psr.active_non_psr_pipes = active_non_psr_pipes; 4166 goto unlock; 4167 } 4168 4169 intel_dp->psr.active_non_psr_pipes = active_non_psr_pipes; 4170 4171 intel_psr_apply_underrun_on_idle_wa_locked(intel_dp); 4172 unlock: 4173 mutex_unlock(&intel_dp->psr.lock); 4174 } 4175 } 4176 4177 /** 4178 * intel_psr_notify_vblank_enable_disable - Notify PSR about enable/disable of vblank 4179 * @display: intel display struct 4180 * @enable: enable/disable 4181 * 4182 * This is targeted for underrun on idle PSR HW bug (Wa_16025596647) to apply 4183 * remove the workaround when vblank is getting enabled/disabled 4184 */ 4185 void intel_psr_notify_vblank_enable_disable(struct intel_display *display, 4186 bool enable) 4187 { 4188 struct intel_encoder *encoder; 4189 4190 for_each_intel_encoder_with_psr(display->drm, encoder) { 4191 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 4192 4193 mutex_lock(&intel_dp->psr.lock); 4194 if (CAN_PANEL_REPLAY(intel_dp)) { 4195 if (enable) 4196 intel_dp->psr.vblank_wakeref = 4197 intel_display_power_get(display, 4198 POWER_DOMAIN_DC_OFF); 4199 else 4200 intel_display_power_put(display, POWER_DOMAIN_DC_OFF, 4201 intel_dp->psr.vblank_wakeref); 4202 } 4203 4204 if (intel_dp->psr.enabled && !intel_dp->psr.panel_replay_enabled && 4205 intel_dp->psr.pkg_c_latency_used) 4206 intel_psr_apply_underrun_on_idle_wa_locked(intel_dp); 4207 4208 mutex_unlock(&intel_dp->psr.lock); 4209 } 4210 } 4211 4212 static void 4213 psr_source_status(struct intel_dp *intel_dp, struct seq_file *m) 4214 { 4215 struct intel_display *display = to_intel_display(intel_dp); 4216 enum transcoder cpu_transcoder = intel_dp->psr.transcoder; 4217 const char *status = "unknown"; 4218 u32 val, status_val; 4219 4220 if ((intel_dp_is_edp(intel_dp) || DISPLAY_VER(display) >= 30) && 4221 (intel_dp->psr.sel_update_enabled || intel_dp->psr.panel_replay_enabled)) { 4222 static const char * const live_status[] = { 4223 "IDLE", 4224 "CAPTURE", 4225 "CAPTURE_FS", 4226 "SLEEP", 4227 "BUFON_FW", 4228 "ML_UP", 4229 "SU_STANDBY", 4230 "FAST_SLEEP", 4231 "DEEP_SLEEP", 4232 "BUF_ON", 4233 "TG_ON" 4234 }; 4235 val = intel_de_read(display, 4236 EDP_PSR2_STATUS(display, cpu_transcoder)); 4237 status_val = REG_FIELD_GET(EDP_PSR2_STATUS_STATE_MASK, val); 4238 if (status_val < ARRAY_SIZE(live_status)) 4239 status = live_status[status_val]; 4240 } else { 4241 static const char * const live_status[] = { 4242 "IDLE", 4243 "SRDONACK", 4244 "SRDENT", 4245 "BUFOFF", 4246 "BUFON", 4247 "AUXACK", 4248 "SRDOFFACK", 4249 "SRDENT_ON", 4250 }; 4251 val = intel_de_read(display, 4252 psr_status_reg(display, cpu_transcoder)); 4253 status_val = REG_FIELD_GET(EDP_PSR_STATUS_STATE_MASK, val); 4254 if (status_val < ARRAY_SIZE(live_status)) 4255 status = live_status[status_val]; 4256 } 4257 4258 seq_printf(m, "Source PSR/PanelReplay status: %s [0x%08x]\n", status, val); 4259 } 4260 4261 static void intel_psr_sink_capability(struct intel_connector *connector, 4262 struct seq_file *m) 4263 { 4264 seq_printf(m, "Sink support: PSR = %s", 4265 str_yes_no(connector->dp.psr_caps.support)); 4266 4267 if (connector->dp.psr_caps.support) 4268 seq_printf(m, " [0x%02x]", connector->dp.psr_caps.dpcd[0]); 4269 if (connector->dp.psr_caps.dpcd[0] == DP_PSR2_WITH_Y_COORD_ET_SUPPORTED) 4270 seq_printf(m, " (Early Transport)"); 4271 seq_printf(m, ", Panel Replay = %s", str_yes_no(connector->dp.panel_replay_caps.support)); 4272 seq_printf(m, ", Panel Replay Selective Update = %s", 4273 str_yes_no(connector->dp.panel_replay_caps.su_support)); 4274 seq_printf(m, ", Panel Replay DSC support = %s", 4275 panel_replay_dsc_support_str(connector->dp.panel_replay_caps.dsc_support)); 4276 if (connector->dp.panel_replay_caps.dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_SUPPORT)] & 4277 DP_PANEL_REPLAY_EARLY_TRANSPORT_SUPPORT) 4278 seq_printf(m, " (Early Transport)"); 4279 seq_printf(m, "\n"); 4280 } 4281 4282 static void intel_psr_print_mode(struct intel_dp *intel_dp, 4283 struct seq_file *m) 4284 { 4285 struct intel_psr *psr = &intel_dp->psr; 4286 const char *status, *mode, *region_et; 4287 4288 if (psr->enabled) 4289 status = " enabled"; 4290 else 4291 status = "disabled"; 4292 4293 if (psr->panel_replay_enabled && psr->sel_update_enabled) 4294 mode = "Panel Replay Selective Update"; 4295 else if (psr->panel_replay_enabled) 4296 mode = "Panel Replay"; 4297 else if (psr->sel_update_enabled) 4298 mode = "PSR2"; 4299 else if (psr->enabled) 4300 mode = "PSR1"; 4301 else 4302 mode = ""; 4303 4304 if (psr->su_region_et_enabled) 4305 region_et = " (Early Transport)"; 4306 else 4307 region_et = ""; 4308 4309 seq_printf(m, "PSR mode: %s%s%s\n", mode, status, region_et); 4310 if (psr->no_psr_reason) 4311 seq_printf(m, " %s\n", psr->no_psr_reason); 4312 } 4313 4314 static int intel_psr_status(struct seq_file *m, struct intel_dp *intel_dp, 4315 struct intel_connector *connector) 4316 { 4317 struct intel_display *display = to_intel_display(intel_dp); 4318 enum transcoder cpu_transcoder = intel_dp->psr.transcoder; 4319 struct intel_psr *psr = &intel_dp->psr; 4320 struct ref_tracker *wakeref; 4321 bool enabled; 4322 u32 val, psr2_ctl; 4323 4324 intel_psr_sink_capability(connector, m); 4325 4326 if (!(connector->dp.psr_caps.support || connector->dp.panel_replay_caps.support)) 4327 return 0; 4328 4329 wakeref = intel_display_rpm_get(display); 4330 mutex_lock(&psr->lock); 4331 4332 intel_psr_print_mode(intel_dp, m); 4333 4334 if (!psr->enabled) { 4335 seq_printf(m, "PSR sink not reliable: %s\n", 4336 str_yes_no(psr->sink_not_reliable)); 4337 4338 goto unlock; 4339 } 4340 4341 if (psr->panel_replay_enabled) { 4342 val = intel_de_read(display, TRANS_DP2_CTL(cpu_transcoder)); 4343 4344 if (intel_dp_is_edp(intel_dp)) 4345 psr2_ctl = intel_de_read(display, 4346 EDP_PSR2_CTL(display, 4347 cpu_transcoder)); 4348 4349 enabled = val & TRANS_DP2_PANEL_REPLAY_ENABLE; 4350 } else if (psr->sel_update_enabled) { 4351 val = intel_de_read(display, 4352 EDP_PSR2_CTL(display, cpu_transcoder)); 4353 enabled = val & EDP_PSR2_ENABLE; 4354 } else { 4355 val = intel_de_read(display, psr_ctl_reg(display, cpu_transcoder)); 4356 enabled = val & EDP_PSR_ENABLE; 4357 } 4358 seq_printf(m, "Source PSR/PanelReplay ctl: %s [0x%08x]\n", 4359 str_enabled_disabled(enabled), val); 4360 if (psr->panel_replay_enabled && intel_dp_is_edp(intel_dp)) 4361 seq_printf(m, "PSR2_CTL: 0x%08x\n", 4362 psr2_ctl); 4363 psr_source_status(intel_dp, m); 4364 seq_printf(m, "Busy frontbuffer bits: 0x%08x\n", 4365 psr->busy_frontbuffer_bits); 4366 4367 /* 4368 * SKL+ Perf counter is reset to 0 everytime DC state is entered 4369 */ 4370 val = intel_de_read(display, psr_perf_cnt_reg(display, cpu_transcoder)); 4371 seq_printf(m, "Performance counter: %u\n", 4372 REG_FIELD_GET(EDP_PSR_PERF_CNT_MASK, val)); 4373 4374 if (psr->debug & I915_PSR_DEBUG_IRQ) { 4375 seq_printf(m, "Last attempted entry at: %lld\n", 4376 psr->last_entry_attempt); 4377 seq_printf(m, "Last exit at: %lld\n", psr->last_exit); 4378 } 4379 4380 if (psr->sel_update_enabled) { 4381 u32 su_frames_val[3]; 4382 int frame; 4383 4384 /* 4385 * PSR2_SU_STATUS register has been tied-off since DG2/ADL-P 4386 * (it returns zeros only) and it has been removed on Xe2_LPD. 4387 */ 4388 if (DISPLAY_VER(display) < 13) { 4389 /* 4390 * Reading all 3 registers before hand to minimize crossing a 4391 * frame boundary between register reads 4392 */ 4393 for (frame = 0; frame < PSR2_SU_STATUS_FRAMES; frame += 3) { 4394 val = intel_de_read(display, 4395 PSR2_SU_STATUS(display, cpu_transcoder, frame)); 4396 su_frames_val[frame / 3] = val; 4397 } 4398 4399 seq_puts(m, "Frame:\tPSR2 SU blocks:\n"); 4400 4401 for (frame = 0; frame < PSR2_SU_STATUS_FRAMES; frame++) { 4402 u32 su_blocks; 4403 4404 su_blocks = su_frames_val[frame / 3] & 4405 PSR2_SU_STATUS_MASK(frame); 4406 su_blocks = su_blocks >> PSR2_SU_STATUS_SHIFT(frame); 4407 seq_printf(m, "%d\t%d\n", frame, su_blocks); 4408 } 4409 } 4410 4411 seq_printf(m, "PSR2 selective fetch: %s\n", 4412 str_enabled_disabled(psr->psr2_sel_fetch_enabled)); 4413 } 4414 4415 unlock: 4416 mutex_unlock(&psr->lock); 4417 intel_display_rpm_put(display, wakeref); 4418 4419 return 0; 4420 } 4421 4422 static int i915_edp_psr_status_show(struct seq_file *m, void *data) 4423 { 4424 struct intel_display *display = m->private; 4425 struct intel_dp *intel_dp = NULL; 4426 struct intel_encoder *encoder; 4427 4428 if (!HAS_PSR(display)) 4429 return -ENODEV; 4430 4431 /* Find the first EDP which supports PSR */ 4432 for_each_intel_encoder_with_psr(display->drm, encoder) { 4433 intel_dp = enc_to_intel_dp(encoder); 4434 break; 4435 } 4436 4437 if (!intel_dp) 4438 return -ENODEV; 4439 4440 return intel_psr_status(m, intel_dp, intel_dp->attached_connector); 4441 } 4442 DEFINE_SHOW_ATTRIBUTE(i915_edp_psr_status); 4443 4444 static int 4445 i915_edp_psr_debug_set(void *data, u64 val) 4446 { 4447 struct intel_display *display = data; 4448 struct intel_encoder *encoder; 4449 int ret = -ENODEV; 4450 4451 if (!HAS_PSR(display)) 4452 return ret; 4453 4454 for_each_intel_encoder_with_psr(display->drm, encoder) { 4455 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 4456 4457 drm_dbg_kms(display->drm, "Setting PSR debug to %llx\n", val); 4458 4459 // TODO: split to each transcoder's PSR debug state 4460 with_intel_display_rpm(display) 4461 ret = intel_psr_debug_set(intel_dp, val); 4462 } 4463 4464 return ret; 4465 } 4466 4467 static int 4468 i915_edp_psr_debug_get(void *data, u64 *val) 4469 { 4470 struct intel_display *display = data; 4471 struct intel_encoder *encoder; 4472 4473 if (!HAS_PSR(display)) 4474 return -ENODEV; 4475 4476 for_each_intel_encoder_with_psr(display->drm, encoder) { 4477 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 4478 4479 // TODO: split to each transcoder's PSR debug state 4480 *val = READ_ONCE(intel_dp->psr.debug); 4481 return 0; 4482 } 4483 4484 return -ENODEV; 4485 } 4486 4487 DEFINE_SIMPLE_ATTRIBUTE(i915_edp_psr_debug_fops, 4488 i915_edp_psr_debug_get, i915_edp_psr_debug_set, 4489 "%llu\n"); 4490 4491 void intel_psr_debugfs_register(struct intel_display *display) 4492 { 4493 struct dentry *debugfs_root = display->drm->debugfs_root; 4494 4495 debugfs_create_file("i915_edp_psr_debug", 0644, debugfs_root, 4496 display, &i915_edp_psr_debug_fops); 4497 4498 debugfs_create_file("i915_edp_psr_status", 0444, debugfs_root, 4499 display, &i915_edp_psr_status_fops); 4500 } 4501 4502 static const char *psr_mode_str(struct intel_dp *intel_dp) 4503 { 4504 if (intel_dp->psr.panel_replay_enabled) 4505 return "PANEL-REPLAY"; 4506 else if (intel_dp->psr.enabled) 4507 return "PSR"; 4508 4509 return "unknown"; 4510 } 4511 4512 static int i915_psr_sink_status_show(struct seq_file *m, void *data) 4513 { 4514 struct intel_connector *connector = m->private; 4515 struct intel_dp *intel_dp = intel_attached_dp(connector); 4516 static const char * const sink_status[] = { 4517 "inactive", 4518 "transition to active, capture and display", 4519 "active, display from RFB", 4520 "active, capture and display on sink device timings", 4521 "transition to inactive, capture and display, timing re-sync", 4522 "reserved", 4523 "reserved", 4524 "sink internal error", 4525 }; 4526 const char *str; 4527 int ret; 4528 u8 status, error_status; 4529 4530 if (!(CAN_PSR(intel_dp) || CAN_PANEL_REPLAY(intel_dp))) { 4531 seq_puts(m, "PSR/Panel-Replay Unsupported\n"); 4532 return -ENODEV; 4533 } 4534 4535 if (connector->base.status != connector_status_connected) 4536 return -ENODEV; 4537 4538 ret = psr_get_status_and_error_status(intel_dp, &status, &error_status); 4539 if (ret) 4540 return ret; 4541 4542 status &= DP_PSR_SINK_STATE_MASK; 4543 if (status < ARRAY_SIZE(sink_status)) 4544 str = sink_status[status]; 4545 else 4546 str = "unknown"; 4547 4548 seq_printf(m, "Sink %s status: 0x%x [%s]\n", psr_mode_str(intel_dp), status, str); 4549 4550 seq_printf(m, "Sink %s error status: 0x%x", psr_mode_str(intel_dp), error_status); 4551 4552 if (error_status & (DP_PSR_RFB_STORAGE_ERROR | 4553 DP_PSR_VSC_SDP_UNCORRECTABLE_ERROR | 4554 DP_PSR_LINK_CRC_ERROR)) 4555 seq_puts(m, ":\n"); 4556 else 4557 seq_puts(m, "\n"); 4558 if (error_status & DP_PSR_RFB_STORAGE_ERROR) 4559 seq_printf(m, "\t%s RFB storage error\n", psr_mode_str(intel_dp)); 4560 if (error_status & DP_PSR_VSC_SDP_UNCORRECTABLE_ERROR) 4561 seq_printf(m, "\t%s VSC SDP uncorrectable error\n", psr_mode_str(intel_dp)); 4562 if (error_status & DP_PSR_LINK_CRC_ERROR) 4563 seq_printf(m, "\t%s Link CRC error\n", psr_mode_str(intel_dp)); 4564 4565 return ret; 4566 } 4567 DEFINE_SHOW_ATTRIBUTE(i915_psr_sink_status); 4568 4569 static int i915_psr_status_show(struct seq_file *m, void *data) 4570 { 4571 struct intel_connector *connector = m->private; 4572 struct intel_dp *intel_dp = intel_attached_dp(connector); 4573 4574 return intel_psr_status(m, intel_dp, connector); 4575 } 4576 DEFINE_SHOW_ATTRIBUTE(i915_psr_status); 4577 4578 void intel_psr_connector_debugfs_add(struct intel_connector *connector) 4579 { 4580 struct intel_display *display = to_intel_display(connector); 4581 struct dentry *root = connector->base.debugfs_entry; 4582 4583 if (connector->base.connector_type != DRM_MODE_CONNECTOR_eDP && 4584 connector->base.connector_type != DRM_MODE_CONNECTOR_DisplayPort) 4585 return; 4586 4587 debugfs_create_file("i915_psr_sink_status", 0444, root, 4588 connector, &i915_psr_sink_status_fops); 4589 4590 if (HAS_PSR(display) || HAS_DP20(display)) 4591 debugfs_create_file("i915_psr_status", 0444, root, 4592 connector, &i915_psr_status_fops); 4593 } 4594 4595 bool intel_psr_needs_alpm(struct intel_dp *intel_dp, const struct intel_crtc_state *crtc_state) 4596 { 4597 /* 4598 * eDP Panel Replay uses always ALPM 4599 * PSR2 uses ALPM but PSR1 doesn't 4600 */ 4601 return intel_dp_is_edp(intel_dp) && (crtc_state->has_sel_update || 4602 crtc_state->has_panel_replay); 4603 } 4604 4605 bool intel_psr_needs_alpm_aux_less(struct intel_dp *intel_dp, 4606 const struct intel_crtc_state *crtc_state) 4607 { 4608 return intel_dp_is_edp(intel_dp) && crtc_state->has_panel_replay; 4609 } 4610 4611 void intel_psr_compute_config_late(struct intel_dp *intel_dp, 4612 struct intel_crtc_state *crtc_state) 4613 { 4614 struct intel_display *display = to_intel_display(intel_dp); 4615 int vblank = intel_crtc_vblank_length(crtc_state); 4616 int wake_lines; 4617 4618 if (intel_psr_needs_alpm_aux_less(intel_dp, crtc_state)) 4619 wake_lines = crtc_state->alpm_state.aux_less_wake_lines; 4620 else if (intel_psr_needs_alpm(intel_dp, crtc_state)) 4621 wake_lines = DISPLAY_VER(display) < 20 ? 4622 psr2_block_count_lines(crtc_state->alpm_state.io_wake_lines, 4623 crtc_state->alpm_state.fast_wake_lines) : 4624 crtc_state->alpm_state.io_wake_lines; 4625 else 4626 wake_lines = 0; 4627 4628 /* 4629 * Disable the PSR features if wake lines exceed the available vblank. 4630 * Though SCL is computed based on these PSR features, it is not reset 4631 * even if the PSR features are disabled to avoid changing vblank start 4632 * at this stage. 4633 */ 4634 if (wake_lines && !_wake_lines_fit_into_vblank(crtc_state, vblank, wake_lines)) { 4635 drm_dbg_kms(display->drm, 4636 "Adjusting PSR/PR mode: vblank too short for wake lines = %d\n", 4637 wake_lines); 4638 4639 if (crtc_state->has_panel_replay) { 4640 crtc_state->has_panel_replay = false; 4641 /* 4642 * #TODO : Add fall back to PSR/PSR2 4643 * Since panel replay cannot be supported, we can fall back to PSR/PSR2. 4644 * This will require calling compute_config for psr and psr2 with check for 4645 * actual guardband instead of vblank_length. 4646 */ 4647 crtc_state->has_psr = false; 4648 } 4649 4650 crtc_state->has_sel_update = false; 4651 crtc_state->enable_psr2_su_region_et = false; 4652 crtc_state->enable_psr2_sel_fetch = false; 4653 } 4654 4655 /* Wa_18037818876 */ 4656 if (intel_psr_needs_wa_18037818876(intel_dp, crtc_state)) { 4657 crtc_state->has_psr = false; 4658 drm_dbg_kms(display->drm, 4659 "PSR disabled to workaround PSR FSM hang issue\n"); 4660 } 4661 4662 intel_psr_set_non_psr_pipes(intel_dp, crtc_state); 4663 } 4664 4665 int intel_psr_min_guardband(struct intel_crtc_state *crtc_state) 4666 { 4667 struct intel_display *display = to_intel_display(crtc_state); 4668 int psr_min_guardband; 4669 int wake_lines; 4670 4671 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) 4672 return 0; 4673 4674 if (crtc_state->has_panel_replay) 4675 wake_lines = crtc_state->alpm_state.aux_less_wake_lines; 4676 else if (crtc_state->has_sel_update) 4677 wake_lines = DISPLAY_VER(display) < 20 ? 4678 psr2_block_count_lines(crtc_state->alpm_state.io_wake_lines, 4679 crtc_state->alpm_state.fast_wake_lines) : 4680 crtc_state->alpm_state.io_wake_lines; 4681 else 4682 return 0; 4683 4684 psr_min_guardband = wake_lines + crtc_state->set_context_latency; 4685 4686 if (crtc_state->req_psr2_sdp_prior_scanline) 4687 psr_min_guardband++; 4688 4689 return psr_min_guardband; 4690 } 4691 4692 bool intel_psr_use_trans_push(const struct intel_crtc_state *crtc_state) 4693 { 4694 struct intel_display *display = to_intel_display(crtc_state); 4695 4696 return HAS_PSR_TRANS_PUSH_FRAME_CHANGE(display) && crtc_state->has_psr; 4697 } 4698 4699 bool intel_psr_pr_async_video_timing_supported(struct intel_dp *intel_dp) 4700 { 4701 struct intel_connector *connector = intel_dp->attached_connector; 4702 u8 *dpcd = connector->dp.panel_replay_caps.dpcd; 4703 u8 pr_support = dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_SUPPORT)]; 4704 u8 pr_cap = dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_CAPABILITY)]; 4705 4706 return (pr_support & DP_PANEL_REPLAY_SUPPORT) && 4707 !(pr_cap & DP_PANEL_REPLAY_ASYNC_VIDEO_TIMING_NOT_SUPPORTED_IN_PR); 4708 } 4709