1 /* 2 * Copyright © 2014 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 */ 23 24 #include <linux/debugfs.h> 25 26 #include <drm/drm_atomic_helper.h> 27 #include <drm/drm_damage_helper.h> 28 #include <drm/drm_debugfs.h> 29 #include <drm/drm_print.h> 30 #include <drm/drm_vblank.h> 31 32 #include "i915_reg.h" 33 #include "intel_alpm.h" 34 #include "intel_atomic.h" 35 #include "intel_crtc.h" 36 #include "intel_cursor_regs.h" 37 #include "intel_ddi.h" 38 #include "intel_de.h" 39 #include "intel_display_irq.h" 40 #include "intel_display_regs.h" 41 #include "intel_display_rpm.h" 42 #include "intel_display_types.h" 43 #include "intel_display_utils.h" 44 #include "intel_dmc.h" 45 #include "intel_dp.h" 46 #include "intel_dp_aux.h" 47 #include "intel_dsb.h" 48 #include "intel_frontbuffer.h" 49 #include "intel_hdmi.h" 50 #include "intel_psr.h" 51 #include "intel_psr_regs.h" 52 #include "intel_snps_phy.h" 53 #include "intel_step.h" 54 #include "intel_vblank.h" 55 #include "intel_vdsc.h" 56 #include "intel_vrr.h" 57 #include "skl_universal_plane.h" 58 59 /** 60 * DOC: Panel Self Refresh (PSR/SRD) 61 * 62 * Since Haswell Display controller supports Panel Self-Refresh on display 63 * panels witch have a remote frame buffer (RFB) implemented according to PSR 64 * spec in eDP1.3. PSR feature allows the display to go to lower standby states 65 * when system is idle but display is on as it eliminates display refresh 66 * request to DDR memory completely as long as the frame buffer for that 67 * display is unchanged. 68 * 69 * Panel Self Refresh must be supported by both Hardware (source) and 70 * Panel (sink). 71 * 72 * PSR saves power by caching the framebuffer in the panel RFB, which allows us 73 * to power down the link and memory controller. For DSI panels the same idea 74 * is called "manual mode". 75 * 76 * The implementation uses the hardware-based PSR support which automatically 77 * enters/exits self-refresh mode. The hardware takes care of sending the 78 * required DP aux message and could even retrain the link (that part isn't 79 * enabled yet though). The hardware also keeps track of any frontbuffer 80 * changes to know when to exit self-refresh mode again. Unfortunately that 81 * part doesn't work too well, hence why the i915 PSR support uses the 82 * software frontbuffer tracking to make sure it doesn't miss a screen 83 * update. For this integration intel_psr_invalidate() and intel_psr_flush() 84 * get called by the frontbuffer tracking code. Note that because of locking 85 * issues the self-refresh re-enable code is done from a work queue, which 86 * must be correctly synchronized/cancelled when shutting down the pipe." 87 * 88 * DC3CO (DC3 clock off) 89 * 90 * On top of PSR2, GEN12 adds a intermediate power savings state that turns 91 * clock off automatically during PSR2 idle state. 92 * The smaller overhead of DC3co entry/exit vs. the overhead of PSR2 deep sleep 93 * entry/exit allows the HW to enter a low-power state even when page flipping 94 * periodically (for instance a 30fps video playback scenario). 95 * 96 * Every time a flips occurs PSR2 will get out of deep sleep state(if it was), 97 * so DC3CO is enabled and tgl_dc3co_disable_work is schedule to run after 6 98 * frames, if no other flip occurs and the function above is executed, DC3CO is 99 * disabled and PSR2 is configured to enter deep sleep, resetting again in case 100 * of another flip. 101 * Front buffer modifications do not trigger DC3CO activation on purpose as it 102 * would bring a lot of complexity and most of the moderns systems will only 103 * use page flips. 104 */ 105 106 /* 107 * Description of PSR mask bits: 108 * 109 * EDP_PSR_DEBUG[16]/EDP_PSR_DEBUG_MASK_DISP_REG_WRITE (hsw-skl): 110 * 111 * When unmasked (nearly) all display register writes (eg. even 112 * SWF) trigger a PSR exit. Some registers are excluded from this 113 * and they have a more specific mask (described below). On icl+ 114 * this bit no longer exists and is effectively always set. 115 * 116 * PIPE_MISC[21]/PIPE_MISC_PSR_MASK_PIPE_REG_WRITE (skl+): 117 * 118 * When unmasked (nearly) all pipe/plane register writes 119 * trigger a PSR exit. Some plane registers are excluded from this 120 * and they have a more specific mask (described below). 121 * 122 * CHICKEN_PIPESL_1[11]/SKL_PSR_MASK_PLANE_FLIP (skl+): 123 * PIPE_MISC[23]/PIPE_MISC_PSR_MASK_PRIMARY_FLIP (bdw): 124 * EDP_PSR_DEBUG[23]/EDP_PSR_DEBUG_MASK_PRIMARY_FLIP (hsw): 125 * 126 * When unmasked PRI_SURF/PLANE_SURF writes trigger a PSR exit. 127 * SPR_SURF/CURBASE are not included in this and instead are 128 * controlled by PIPE_MISC_PSR_MASK_PIPE_REG_WRITE (skl+) or 129 * EDP_PSR_DEBUG_MASK_DISP_REG_WRITE (hsw/bdw). 130 * 131 * PIPE_MISC[22]/PIPE_MISC_PSR_MASK_SPRITE_ENABLE (bdw): 132 * EDP_PSR_DEBUG[21]/EDP_PSR_DEBUG_MASK_SPRITE_ENABLE (hsw): 133 * 134 * When unmasked PSR is blocked as long as the sprite 135 * plane is enabled. skl+ with their universal planes no 136 * longer have a mask bit like this, and no plane being 137 * enabledb blocks PSR. 138 * 139 * PIPE_MISC[21]/PIPE_MISC_PSR_MASK_CURSOR_MOVE (bdw): 140 * EDP_PSR_DEBUG[20]/EDP_PSR_DEBUG_MASK_CURSOR_MOVE (hsw): 141 * 142 * When umasked CURPOS writes trigger a PSR exit. On skl+ 143 * this doesn't exit but CURPOS is included in the 144 * PIPE_MISC_PSR_MASK_PIPE_REG_WRITE mask. 145 * 146 * PIPE_MISC[20]/PIPE_MISC_PSR_MASK_VBLANK_VSYNC_INT (bdw+): 147 * EDP_PSR_DEBUG[19]/EDP_PSR_DEBUG_MASK_VBLANK_VSYNC_INT (hsw): 148 * 149 * When unmasked PSR is blocked as long as vblank and/or vsync 150 * interrupt is unmasked in IMR *and* enabled in IER. 151 * 152 * CHICKEN_TRANS[30]/SKL_UNMASK_VBL_TO_PIPE_IN_SRD (skl+): 153 * CHICKEN_PAR1_1[15]/HSW_MASK_VBL_TO_PIPE_IN_SRD (hsw/bdw): 154 * 155 * Selectcs whether PSR exit generates an extra vblank before 156 * the first frame is transmitted. Also note the opposite polarity 157 * if the bit on hsw/bdw vs. skl+ (masked==generate the extra vblank, 158 * unmasked==do not generate the extra vblank). 159 * 160 * With DC states enabled the extra vblank happens after link training, 161 * with DC states disabled it happens immediately upuon PSR exit trigger. 162 * No idea as of now why there is a difference. HSW/BDW (which don't 163 * even have DMC) always generate it after link training. Go figure. 164 * 165 * Unfortunately CHICKEN_TRANS itself seems to be double buffered 166 * and thus won't latch until the first vblank. So with DC states 167 * enabled the register effectively uses the reset value during DC5 168 * exit+PSR exit sequence, and thus the bit does nothing until 169 * latched by the vblank that it was trying to prevent from being 170 * generated in the first place. So we should probably call this 171 * one a chicken/egg bit instead on skl+. 172 * 173 * In standby mode (as opposed to link-off) this makes no difference 174 * as the timing generator keeps running the whole time generating 175 * normal periodic vblanks. 176 * 177 * WaPsrDPAMaskVBlankInSRD asks us to set the bit on hsw/bdw, 178 * and doing so makes the behaviour match the skl+ reset value. 179 * 180 * CHICKEN_PIPESL_1[0]/BDW_UNMASK_VBL_TO_REGS_IN_SRD (bdw): 181 * CHICKEN_PIPESL_1[15]/HSW_UNMASK_VBL_TO_REGS_IN_SRD (hsw): 182 * 183 * On BDW without this bit is no vblanks whatsoever are 184 * generated after PSR exit. On HSW this has no apparent effect. 185 * WaPsrDPRSUnmaskVBlankInSRD says to set this. 186 * 187 * The rest of the bits are more self-explanatory and/or 188 * irrelevant for normal operation. 189 * 190 * Description of intel_crtc_state variables. has_psr, has_panel_replay and 191 * has_sel_update: 192 * 193 * has_psr (alone): PSR1 194 * has_psr + has_sel_update: PSR2 195 * has_psr + has_panel_replay: Panel Replay 196 * has_psr + has_panel_replay + has_sel_update: Panel Replay Selective Update 197 * 198 * Description of some intel_psr variables. enabled, panel_replay_enabled, 199 * sel_update_enabled 200 * 201 * enabled (alone): PSR1 202 * enabled + sel_update_enabled: PSR2 203 * enabled + panel_replay_enabled: Panel Replay 204 * enabled + panel_replay_enabled + sel_update_enabled: Panel Replay SU 205 */ 206 207 #define CAN_PSR(intel_dp) ((intel_dp)->psr.sink_support && \ 208 (intel_dp)->psr.source_support) 209 210 bool intel_encoder_can_psr(struct intel_encoder *encoder) 211 { 212 if (intel_encoder_is_dp(encoder) || encoder->type == INTEL_OUTPUT_DP_MST) 213 return CAN_PSR(enc_to_intel_dp(encoder)) || 214 CAN_PANEL_REPLAY(enc_to_intel_dp(encoder)); 215 else 216 return false; 217 } 218 219 bool intel_psr_needs_aux_io_power(struct intel_encoder *encoder, 220 const struct intel_crtc_state *crtc_state) 221 { 222 /* 223 * For PSR/PR modes only eDP requires the AUX IO power to be enabled whenever 224 * the output is enabled. For non-eDP outputs the main link is always 225 * on, hence it doesn't require the HW initiated AUX wake-up signaling used 226 * for eDP. 227 * 228 * TODO: 229 * - Consider leaving AUX IO disabled for eDP / PR as well, in case 230 * the ALPM with main-link off mode is not enabled. 231 * - Leave AUX IO enabled for DP / PR, once support for ALPM with 232 * main-link off mode is added for it and this mode gets enabled. 233 */ 234 return intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP) && 235 intel_encoder_can_psr(encoder); 236 } 237 238 static bool psr_global_enabled(struct intel_dp *intel_dp) 239 { 240 struct intel_connector *connector = intel_dp->attached_connector; 241 242 switch (intel_dp->psr.debug & I915_PSR_DEBUG_MODE_MASK) { 243 case I915_PSR_DEBUG_DEFAULT: 244 return intel_dp_is_edp(intel_dp) ? 245 connector->panel.vbt.psr.enable : true; 246 case I915_PSR_DEBUG_DISABLE: 247 return false; 248 default: 249 return true; 250 } 251 } 252 253 static bool sel_update_global_enabled(struct intel_dp *intel_dp) 254 { 255 switch (intel_dp->psr.debug & I915_PSR_DEBUG_MODE_MASK) { 256 case I915_PSR_DEBUG_DISABLE: 257 case I915_PSR_DEBUG_FORCE_PSR1: 258 return false; 259 default: 260 return true; 261 } 262 } 263 264 static bool panel_replay_global_enabled(struct intel_dp *intel_dp) 265 { 266 struct intel_display *display = to_intel_display(intel_dp); 267 268 return !(intel_dp->psr.debug & I915_PSR_DEBUG_PANEL_REPLAY_DISABLE) && 269 display->params.enable_panel_replay; 270 } 271 272 static u32 psr_irq_psr_error_bit_get(struct intel_dp *intel_dp) 273 { 274 struct intel_display *display = to_intel_display(intel_dp); 275 276 return DISPLAY_VER(display) >= 12 ? TGL_PSR_ERROR : 277 EDP_PSR_ERROR(intel_dp->psr.transcoder); 278 } 279 280 static u32 psr_irq_post_exit_bit_get(struct intel_dp *intel_dp) 281 { 282 struct intel_display *display = to_intel_display(intel_dp); 283 284 return DISPLAY_VER(display) >= 12 ? TGL_PSR_POST_EXIT : 285 EDP_PSR_POST_EXIT(intel_dp->psr.transcoder); 286 } 287 288 static u32 psr_irq_pre_entry_bit_get(struct intel_dp *intel_dp) 289 { 290 struct intel_display *display = to_intel_display(intel_dp); 291 292 return DISPLAY_VER(display) >= 12 ? TGL_PSR_PRE_ENTRY : 293 EDP_PSR_PRE_ENTRY(intel_dp->psr.transcoder); 294 } 295 296 static u32 psr_irq_mask_get(struct intel_dp *intel_dp) 297 { 298 struct intel_display *display = to_intel_display(intel_dp); 299 300 return DISPLAY_VER(display) >= 12 ? TGL_PSR_MASK : 301 EDP_PSR_MASK(intel_dp->psr.transcoder); 302 } 303 304 static i915_reg_t psr_ctl_reg(struct intel_display *display, 305 enum transcoder cpu_transcoder) 306 { 307 if (DISPLAY_VER(display) >= 8) 308 return EDP_PSR_CTL(display, cpu_transcoder); 309 else 310 return HSW_SRD_CTL; 311 } 312 313 static i915_reg_t psr_debug_reg(struct intel_display *display, 314 enum transcoder cpu_transcoder) 315 { 316 if (DISPLAY_VER(display) >= 8) 317 return EDP_PSR_DEBUG(display, cpu_transcoder); 318 else 319 return HSW_SRD_DEBUG; 320 } 321 322 static i915_reg_t psr_perf_cnt_reg(struct intel_display *display, 323 enum transcoder cpu_transcoder) 324 { 325 if (DISPLAY_VER(display) >= 8) 326 return EDP_PSR_PERF_CNT(display, cpu_transcoder); 327 else 328 return HSW_SRD_PERF_CNT; 329 } 330 331 static i915_reg_t psr_status_reg(struct intel_display *display, 332 enum transcoder cpu_transcoder) 333 { 334 if (DISPLAY_VER(display) >= 8) 335 return EDP_PSR_STATUS(display, cpu_transcoder); 336 else 337 return HSW_SRD_STATUS; 338 } 339 340 static i915_reg_t psr_imr_reg(struct intel_display *display, 341 enum transcoder cpu_transcoder) 342 { 343 if (DISPLAY_VER(display) >= 12) 344 return TRANS_PSR_IMR(display, cpu_transcoder); 345 else 346 return EDP_PSR_IMR; 347 } 348 349 static i915_reg_t psr_iir_reg(struct intel_display *display, 350 enum transcoder cpu_transcoder) 351 { 352 if (DISPLAY_VER(display) >= 12) 353 return TRANS_PSR_IIR(display, cpu_transcoder); 354 else 355 return EDP_PSR_IIR; 356 } 357 358 static i915_reg_t psr_aux_ctl_reg(struct intel_display *display, 359 enum transcoder cpu_transcoder) 360 { 361 if (DISPLAY_VER(display) >= 8) 362 return EDP_PSR_AUX_CTL(display, cpu_transcoder); 363 else 364 return HSW_SRD_AUX_CTL; 365 } 366 367 static i915_reg_t psr_aux_data_reg(struct intel_display *display, 368 enum transcoder cpu_transcoder, int i) 369 { 370 if (DISPLAY_VER(display) >= 8) 371 return EDP_PSR_AUX_DATA(display, cpu_transcoder, i); 372 else 373 return HSW_SRD_AUX_DATA(i); 374 } 375 376 static void psr_irq_control(struct intel_dp *intel_dp) 377 { 378 struct intel_display *display = to_intel_display(intel_dp); 379 enum transcoder cpu_transcoder = intel_dp->psr.transcoder; 380 u32 mask; 381 382 if (intel_dp->psr.panel_replay_enabled) 383 return; 384 385 mask = psr_irq_psr_error_bit_get(intel_dp); 386 if (intel_dp->psr.debug & I915_PSR_DEBUG_IRQ) 387 mask |= psr_irq_post_exit_bit_get(intel_dp) | 388 psr_irq_pre_entry_bit_get(intel_dp); 389 390 intel_de_rmw(display, psr_imr_reg(display, cpu_transcoder), 391 psr_irq_mask_get(intel_dp), ~mask); 392 } 393 394 static void psr_event_print(struct intel_display *display, 395 u32 val, bool sel_update_enabled) 396 { 397 drm_dbg_kms(display->drm, "PSR exit events: 0x%x\n", val); 398 if (val & PSR_EVENT_PSR2_WD_TIMER_EXPIRE) 399 drm_dbg_kms(display->drm, "\tPSR2 watchdog timer expired\n"); 400 if ((val & PSR_EVENT_PSR2_DISABLED) && sel_update_enabled) 401 drm_dbg_kms(display->drm, "\tPSR2 disabled\n"); 402 if (val & PSR_EVENT_SU_DIRTY_FIFO_UNDERRUN) 403 drm_dbg_kms(display->drm, "\tSU dirty FIFO underrun\n"); 404 if (val & PSR_EVENT_SU_CRC_FIFO_UNDERRUN) 405 drm_dbg_kms(display->drm, "\tSU CRC FIFO underrun\n"); 406 if (val & PSR_EVENT_GRAPHICS_RESET) 407 drm_dbg_kms(display->drm, "\tGraphics reset\n"); 408 if (val & PSR_EVENT_PCH_INTERRUPT) 409 drm_dbg_kms(display->drm, "\tPCH interrupt\n"); 410 if (val & PSR_EVENT_MEMORY_UP) 411 drm_dbg_kms(display->drm, "\tMemory up\n"); 412 if (val & PSR_EVENT_FRONT_BUFFER_MODIFY) 413 drm_dbg_kms(display->drm, "\tFront buffer modification\n"); 414 if (val & PSR_EVENT_WD_TIMER_EXPIRE) 415 drm_dbg_kms(display->drm, "\tPSR watchdog timer expired\n"); 416 if (val & PSR_EVENT_PIPE_REGISTERS_UPDATE) 417 drm_dbg_kms(display->drm, "\tPIPE registers updated\n"); 418 if (val & PSR_EVENT_REGISTER_UPDATE) 419 drm_dbg_kms(display->drm, "\tRegister updated\n"); 420 if (val & PSR_EVENT_HDCP_ENABLE) 421 drm_dbg_kms(display->drm, "\tHDCP enabled\n"); 422 if (val & PSR_EVENT_KVMR_SESSION_ENABLE) 423 drm_dbg_kms(display->drm, "\tKVMR session enabled\n"); 424 if (val & PSR_EVENT_VBI_ENABLE) 425 drm_dbg_kms(display->drm, "\tVBI enabled\n"); 426 if (val & PSR_EVENT_LPSP_MODE_EXIT) 427 drm_dbg_kms(display->drm, "\tLPSP mode exited\n"); 428 if ((val & PSR_EVENT_PSR_DISABLE) && !sel_update_enabled) 429 drm_dbg_kms(display->drm, "\tPSR disabled\n"); 430 } 431 432 void intel_psr_irq_handler(struct intel_dp *intel_dp, u32 psr_iir) 433 { 434 struct intel_display *display = to_intel_display(intel_dp); 435 enum transcoder cpu_transcoder = intel_dp->psr.transcoder; 436 ktime_t time_ns = ktime_get(); 437 438 if (psr_iir & psr_irq_pre_entry_bit_get(intel_dp)) { 439 intel_dp->psr.last_entry_attempt = time_ns; 440 drm_dbg_kms(display->drm, 441 "[transcoder %s] PSR entry attempt in 2 vblanks\n", 442 transcoder_name(cpu_transcoder)); 443 } 444 445 if (psr_iir & psr_irq_post_exit_bit_get(intel_dp)) { 446 intel_dp->psr.last_exit = time_ns; 447 drm_dbg_kms(display->drm, 448 "[transcoder %s] PSR exit completed\n", 449 transcoder_name(cpu_transcoder)); 450 451 if (DISPLAY_VER(display) >= 9) { 452 u32 val; 453 454 val = intel_de_rmw(display, 455 PSR_EVENT(display, cpu_transcoder), 456 0, 0); 457 458 psr_event_print(display, val, intel_dp->psr.sel_update_enabled); 459 } 460 } 461 462 if (psr_iir & psr_irq_psr_error_bit_get(intel_dp)) { 463 drm_warn(display->drm, "[transcoder %s] PSR aux error\n", 464 transcoder_name(cpu_transcoder)); 465 466 intel_dp->psr.irq_aux_error = true; 467 468 /* 469 * If this interruption is not masked it will keep 470 * interrupting so fast that it prevents the scheduled 471 * work to run. 472 * Also after a PSR error, we don't want to arm PSR 473 * again so we don't care about unmask the interruption 474 * or unset irq_aux_error. 475 */ 476 intel_de_rmw(display, psr_imr_reg(display, cpu_transcoder), 477 0, psr_irq_psr_error_bit_get(intel_dp)); 478 479 queue_work(display->wq.unordered, &intel_dp->psr.work); 480 } 481 } 482 483 static u8 intel_dp_get_sink_sync_latency(struct intel_dp *intel_dp) 484 { 485 struct intel_display *display = to_intel_display(intel_dp); 486 u8 val = 8; /* assume the worst if we can't read the value */ 487 488 if (drm_dp_dpcd_readb(&intel_dp->aux, 489 DP_SYNCHRONIZATION_LATENCY_IN_SINK, &val) == 1) 490 val &= DP_MAX_RESYNC_FRAME_COUNT_MASK; 491 else 492 drm_dbg_kms(display->drm, 493 "Unable to get sink synchronization latency, assuming 8 frames\n"); 494 return val; 495 } 496 497 static u8 intel_dp_get_su_capability(struct intel_dp *intel_dp) 498 { 499 u8 su_capability = 0; 500 501 if (intel_dp->psr.sink_panel_replay_su_support) { 502 if (drm_dp_dpcd_read_byte(&intel_dp->aux, 503 DP_PANEL_REPLAY_CAP_CAPABILITY, 504 &su_capability) < 0) 505 return 0; 506 } else { 507 su_capability = intel_dp->psr_dpcd[1]; 508 } 509 510 return su_capability; 511 } 512 513 static unsigned int 514 intel_dp_get_su_x_granularity_offset(struct intel_dp *intel_dp) 515 { 516 return intel_dp->psr.sink_panel_replay_su_support ? 517 DP_PANEL_REPLAY_CAP_X_GRANULARITY : 518 DP_PSR2_SU_X_GRANULARITY; 519 } 520 521 static unsigned int 522 intel_dp_get_su_y_granularity_offset(struct intel_dp *intel_dp) 523 { 524 return intel_dp->psr.sink_panel_replay_su_support ? 525 DP_PANEL_REPLAY_CAP_Y_GRANULARITY : 526 DP_PSR2_SU_Y_GRANULARITY; 527 } 528 529 /* 530 * Note: Bits related to granularity are same in panel replay and psr 531 * registers. Rely on PSR definitions on these "common" bits. 532 */ 533 static void intel_dp_get_su_granularity(struct intel_dp *intel_dp) 534 { 535 struct intel_display *display = to_intel_display(intel_dp); 536 ssize_t r; 537 u16 w; 538 u8 y; 539 540 /* 541 * TODO: Do we need to take into account panel supporting both PSR and 542 * Panel replay? 543 */ 544 545 /* 546 * If sink don't have specific granularity requirements set legacy 547 * ones. 548 */ 549 if (!(intel_dp_get_su_capability(intel_dp) & 550 DP_PSR2_SU_GRANULARITY_REQUIRED)) { 551 /* As PSR2 HW sends full lines, we do not care about x granularity */ 552 w = 4; 553 y = 4; 554 goto exit; 555 } 556 557 r = drm_dp_dpcd_read(&intel_dp->aux, 558 intel_dp_get_su_x_granularity_offset(intel_dp), 559 &w, 2); 560 if (r != 2) 561 drm_dbg_kms(display->drm, 562 "Unable to read selective update x granularity\n"); 563 /* 564 * Spec says that if the value read is 0 the default granularity should 565 * be used instead. 566 */ 567 if (r != 2 || w == 0) 568 w = 4; 569 570 r = drm_dp_dpcd_read(&intel_dp->aux, 571 intel_dp_get_su_y_granularity_offset(intel_dp), 572 &y, 1); 573 if (r != 1) { 574 drm_dbg_kms(display->drm, 575 "Unable to read selective update y granularity\n"); 576 y = 4; 577 } 578 if (y == 0) 579 y = 1; 580 581 exit: 582 intel_dp->psr.su_w_granularity = w; 583 intel_dp->psr.su_y_granularity = y; 584 } 585 586 static enum intel_panel_replay_dsc_support 587 compute_pr_dsc_support(struct intel_dp *intel_dp) 588 { 589 u8 pr_dsc_mode; 590 u8 val; 591 592 val = intel_dp->pr_dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_CAPABILITY)]; 593 pr_dsc_mode = REG_FIELD_GET8(DP_PANEL_REPLAY_DSC_DECODE_CAPABILITY_IN_PR_MASK, val); 594 595 switch (pr_dsc_mode) { 596 case DP_DSC_DECODE_CAPABILITY_IN_PR_FULL_FRAME_ONLY: 597 return INTEL_DP_PANEL_REPLAY_DSC_FULL_FRAME_ONLY; 598 case DP_DSC_DECODE_CAPABILITY_IN_PR_SUPPORTED: 599 return INTEL_DP_PANEL_REPLAY_DSC_SELECTIVE_UPDATE; 600 default: 601 MISSING_CASE(pr_dsc_mode); 602 fallthrough; 603 case DP_DSC_DECODE_CAPABILITY_IN_PR_NOT_SUPPORTED: 604 case DP_DSC_DECODE_CAPABILITY_IN_PR_RESERVED: 605 return INTEL_DP_PANEL_REPLAY_DSC_NOT_SUPPORTED; 606 } 607 } 608 609 static const char *panel_replay_dsc_support_str(enum intel_panel_replay_dsc_support dsc_support) 610 { 611 switch (dsc_support) { 612 case INTEL_DP_PANEL_REPLAY_DSC_NOT_SUPPORTED: 613 return "not supported"; 614 case INTEL_DP_PANEL_REPLAY_DSC_FULL_FRAME_ONLY: 615 return "full frame only"; 616 case INTEL_DP_PANEL_REPLAY_DSC_SELECTIVE_UPDATE: 617 return "selective update"; 618 default: 619 MISSING_CASE(dsc_support); 620 return "n/a"; 621 }; 622 } 623 624 static void _panel_replay_init_dpcd(struct intel_dp *intel_dp) 625 { 626 struct intel_display *display = to_intel_display(intel_dp); 627 int ret; 628 629 /* TODO: Enable Panel Replay on MST once it's properly implemented. */ 630 if (intel_dp->mst_detect == DRM_DP_MST) 631 return; 632 633 ret = drm_dp_dpcd_read_data(&intel_dp->aux, DP_PANEL_REPLAY_CAP_SUPPORT, 634 &intel_dp->pr_dpcd, sizeof(intel_dp->pr_dpcd)); 635 if (ret < 0) 636 return; 637 638 if (!(intel_dp->pr_dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_SUPPORT)] & 639 DP_PANEL_REPLAY_SUPPORT)) 640 return; 641 642 if (intel_dp_is_edp(intel_dp)) { 643 if (!intel_alpm_aux_less_wake_supported(intel_dp)) { 644 drm_dbg_kms(display->drm, 645 "Panel doesn't support AUX-less ALPM, eDP Panel Replay not possible\n"); 646 return; 647 } 648 649 if (!(intel_dp->pr_dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_SUPPORT)] & 650 DP_PANEL_REPLAY_EARLY_TRANSPORT_SUPPORT)) { 651 drm_dbg_kms(display->drm, 652 "Panel doesn't support early transport, eDP Panel Replay not possible\n"); 653 return; 654 } 655 } 656 657 intel_dp->psr.sink_panel_replay_support = true; 658 659 if (intel_dp->pr_dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_SUPPORT)] & 660 DP_PANEL_REPLAY_SU_SUPPORT) 661 intel_dp->psr.sink_panel_replay_su_support = true; 662 663 intel_dp->psr.sink_panel_replay_dsc_support = compute_pr_dsc_support(intel_dp); 664 665 drm_dbg_kms(display->drm, 666 "Panel replay %sis supported by panel (in DSC mode: %s)\n", 667 intel_dp->psr.sink_panel_replay_su_support ? 668 "selective_update " : "", 669 panel_replay_dsc_support_str(intel_dp->psr.sink_panel_replay_dsc_support)); 670 } 671 672 static void _psr_init_dpcd(struct intel_dp *intel_dp) 673 { 674 struct intel_display *display = to_intel_display(intel_dp); 675 int ret; 676 677 ret = drm_dp_dpcd_read_data(&intel_dp->aux, DP_PSR_SUPPORT, intel_dp->psr_dpcd, 678 sizeof(intel_dp->psr_dpcd)); 679 if (ret < 0) 680 return; 681 682 if (!intel_dp->psr_dpcd[0]) 683 return; 684 685 drm_dbg_kms(display->drm, "eDP panel supports PSR version %x\n", 686 intel_dp->psr_dpcd[0]); 687 688 if (drm_dp_has_quirk(&intel_dp->desc, DP_DPCD_QUIRK_NO_PSR)) { 689 drm_dbg_kms(display->drm, 690 "PSR support not currently available for this panel\n"); 691 return; 692 } 693 694 if (!(intel_dp->edp_dpcd[1] & DP_EDP_SET_POWER_CAP)) { 695 drm_dbg_kms(display->drm, 696 "Panel lacks power state control, PSR cannot be enabled\n"); 697 return; 698 } 699 700 intel_dp->psr.sink_support = true; 701 intel_dp->psr.sink_sync_latency = 702 intel_dp_get_sink_sync_latency(intel_dp); 703 704 if (DISPLAY_VER(display) >= 9 && 705 intel_dp->psr_dpcd[0] >= DP_PSR2_WITH_Y_COORD_IS_SUPPORTED) { 706 bool y_req = intel_dp->psr_dpcd[1] & 707 DP_PSR2_SU_Y_COORDINATE_REQUIRED; 708 709 /* 710 * All panels that supports PSR version 03h (PSR2 + 711 * Y-coordinate) can handle Y-coordinates in VSC but we are 712 * only sure that it is going to be used when required by the 713 * panel. This way panel is capable to do selective update 714 * without a aux frame sync. 715 * 716 * To support PSR version 02h and PSR version 03h without 717 * Y-coordinate requirement panels we would need to enable 718 * GTC first. 719 */ 720 intel_dp->psr.sink_psr2_support = y_req && 721 intel_alpm_aux_wake_supported(intel_dp); 722 drm_dbg_kms(display->drm, "PSR2 %ssupported\n", 723 intel_dp->psr.sink_psr2_support ? "" : "not "); 724 } 725 } 726 727 void intel_psr_init_dpcd(struct intel_dp *intel_dp) 728 { 729 _psr_init_dpcd(intel_dp); 730 731 _panel_replay_init_dpcd(intel_dp); 732 733 if (intel_dp->psr.sink_psr2_support || 734 intel_dp->psr.sink_panel_replay_su_support) 735 intel_dp_get_su_granularity(intel_dp); 736 } 737 738 static void hsw_psr_setup_aux(struct intel_dp *intel_dp) 739 { 740 struct intel_display *display = to_intel_display(intel_dp); 741 enum transcoder cpu_transcoder = intel_dp->psr.transcoder; 742 u32 aux_clock_divider, aux_ctl; 743 /* write DP_SET_POWER=D0 */ 744 static const u8 aux_msg[] = { 745 [0] = (DP_AUX_NATIVE_WRITE << 4) | ((DP_SET_POWER >> 16) & 0xf), 746 [1] = (DP_SET_POWER >> 8) & 0xff, 747 [2] = DP_SET_POWER & 0xff, 748 [3] = 1 - 1, 749 [4] = DP_SET_POWER_D0, 750 }; 751 int i; 752 753 BUILD_BUG_ON(sizeof(aux_msg) > 20); 754 for (i = 0; i < sizeof(aux_msg); i += 4) 755 intel_de_write(display, 756 psr_aux_data_reg(display, cpu_transcoder, i >> 2), 757 intel_dp_aux_pack(&aux_msg[i], sizeof(aux_msg) - i)); 758 759 aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, 0); 760 761 /* Start with bits set for DDI_AUX_CTL register */ 762 aux_ctl = intel_dp->get_aux_send_ctl(intel_dp, sizeof(aux_msg), 763 aux_clock_divider); 764 765 /* Select only valid bits for SRD_AUX_CTL */ 766 aux_ctl &= EDP_PSR_AUX_CTL_TIME_OUT_MASK | 767 EDP_PSR_AUX_CTL_MESSAGE_SIZE_MASK | 768 EDP_PSR_AUX_CTL_PRECHARGE_2US_MASK | 769 EDP_PSR_AUX_CTL_BIT_CLOCK_2X_MASK; 770 771 intel_de_write(display, psr_aux_ctl_reg(display, cpu_transcoder), 772 aux_ctl); 773 } 774 775 static bool psr2_su_region_et_valid(struct intel_dp *intel_dp, bool panel_replay) 776 { 777 struct intel_display *display = to_intel_display(intel_dp); 778 779 if (DISPLAY_VER(display) < 20 || !intel_dp_is_edp(intel_dp) || 780 intel_dp->psr.debug & I915_PSR_DEBUG_SU_REGION_ET_DISABLE) 781 return false; 782 783 return panel_replay ? 784 intel_dp->pr_dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_SUPPORT)] & 785 DP_PANEL_REPLAY_EARLY_TRANSPORT_SUPPORT : 786 intel_dp->psr_dpcd[0] == DP_PSR2_WITH_Y_COORD_ET_SUPPORTED; 787 } 788 789 static void _panel_replay_enable_sink(struct intel_dp *intel_dp, 790 const struct intel_crtc_state *crtc_state) 791 { 792 u8 val = DP_PANEL_REPLAY_ENABLE | 793 DP_PANEL_REPLAY_VSC_SDP_CRC_EN | 794 DP_PANEL_REPLAY_UNRECOVERABLE_ERROR_EN | 795 DP_PANEL_REPLAY_RFB_STORAGE_ERROR_EN | 796 DP_PANEL_REPLAY_ACTIVE_FRAME_CRC_ERROR_EN; 797 u8 panel_replay_config2 = DP_PANEL_REPLAY_CRC_VERIFICATION; 798 799 if (crtc_state->has_sel_update) 800 val |= DP_PANEL_REPLAY_SU_ENABLE; 801 802 if (crtc_state->enable_psr2_su_region_et) 803 val |= DP_PANEL_REPLAY_ENABLE_SU_REGION_ET; 804 805 if (crtc_state->req_psr2_sdp_prior_scanline) 806 panel_replay_config2 |= 807 DP_PANEL_REPLAY_SU_REGION_SCANLINE_CAPTURE; 808 809 drm_dp_dpcd_writeb(&intel_dp->aux, PANEL_REPLAY_CONFIG, val); 810 811 drm_dp_dpcd_writeb(&intel_dp->aux, PANEL_REPLAY_CONFIG2, 812 panel_replay_config2); 813 } 814 815 static void _psr_enable_sink(struct intel_dp *intel_dp, 816 const struct intel_crtc_state *crtc_state) 817 { 818 struct intel_display *display = to_intel_display(intel_dp); 819 u8 val = 0; 820 821 if (crtc_state->has_sel_update) { 822 val |= DP_PSR_ENABLE_PSR2 | DP_PSR_IRQ_HPD_WITH_CRC_ERRORS; 823 } else { 824 if (intel_dp->psr.link_standby) 825 val |= DP_PSR_MAIN_LINK_ACTIVE; 826 827 if (DISPLAY_VER(display) >= 8) 828 val |= DP_PSR_CRC_VERIFICATION; 829 } 830 831 if (crtc_state->req_psr2_sdp_prior_scanline) 832 val |= DP_PSR_SU_REGION_SCANLINE_CAPTURE; 833 834 if (crtc_state->enable_psr2_su_region_et) 835 val |= DP_PANEL_REPLAY_ENABLE_SU_REGION_ET; 836 837 if (intel_dp->psr.entry_setup_frames > 0) 838 val |= DP_PSR_FRAME_CAPTURE; 839 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, val); 840 841 val |= DP_PSR_ENABLE; 842 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, val); 843 } 844 845 static void intel_psr_enable_sink(struct intel_dp *intel_dp, 846 const struct intel_crtc_state *crtc_state) 847 { 848 intel_alpm_enable_sink(intel_dp, crtc_state); 849 850 crtc_state->has_panel_replay ? 851 _panel_replay_enable_sink(intel_dp, crtc_state) : 852 _psr_enable_sink(intel_dp, crtc_state); 853 854 if (intel_dp_is_edp(intel_dp)) 855 drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, DP_SET_POWER_D0); 856 } 857 858 void intel_psr_panel_replay_enable_sink(struct intel_dp *intel_dp) 859 { 860 if (CAN_PANEL_REPLAY(intel_dp)) 861 drm_dp_dpcd_writeb(&intel_dp->aux, PANEL_REPLAY_CONFIG, 862 DP_PANEL_REPLAY_ENABLE); 863 } 864 865 static u32 intel_psr1_get_tp_time(struct intel_dp *intel_dp) 866 { 867 struct intel_display *display = to_intel_display(intel_dp); 868 struct intel_connector *connector = intel_dp->attached_connector; 869 u32 val = 0; 870 871 if (DISPLAY_VER(display) >= 11) 872 val |= EDP_PSR_TP4_TIME_0us; 873 874 if (display->params.psr_safest_params) { 875 val |= EDP_PSR_TP1_TIME_2500us; 876 val |= EDP_PSR_TP2_TP3_TIME_2500us; 877 goto check_tp3_sel; 878 } 879 880 if (connector->panel.vbt.psr.tp1_wakeup_time_us == 0) 881 val |= EDP_PSR_TP1_TIME_0us; 882 else if (connector->panel.vbt.psr.tp1_wakeup_time_us <= 100) 883 val |= EDP_PSR_TP1_TIME_100us; 884 else if (connector->panel.vbt.psr.tp1_wakeup_time_us <= 500) 885 val |= EDP_PSR_TP1_TIME_500us; 886 else 887 val |= EDP_PSR_TP1_TIME_2500us; 888 889 if (connector->panel.vbt.psr.tp2_tp3_wakeup_time_us == 0) 890 val |= EDP_PSR_TP2_TP3_TIME_0us; 891 else if (connector->panel.vbt.psr.tp2_tp3_wakeup_time_us <= 100) 892 val |= EDP_PSR_TP2_TP3_TIME_100us; 893 else if (connector->panel.vbt.psr.tp2_tp3_wakeup_time_us <= 500) 894 val |= EDP_PSR_TP2_TP3_TIME_500us; 895 else 896 val |= EDP_PSR_TP2_TP3_TIME_2500us; 897 898 /* 899 * WA 0479: hsw,bdw 900 * "Do not skip both TP1 and TP2/TP3" 901 */ 902 if (DISPLAY_VER(display) < 9 && 903 connector->panel.vbt.psr.tp1_wakeup_time_us == 0 && 904 connector->panel.vbt.psr.tp2_tp3_wakeup_time_us == 0) 905 val |= EDP_PSR_TP2_TP3_TIME_100us; 906 907 check_tp3_sel: 908 if (intel_dp_source_supports_tps3(display) && 909 drm_dp_tps3_supported(intel_dp->dpcd)) 910 val |= EDP_PSR_TP_TP1_TP3; 911 else 912 val |= EDP_PSR_TP_TP1_TP2; 913 914 return val; 915 } 916 917 static u8 psr_compute_idle_frames(struct intel_dp *intel_dp) 918 { 919 struct intel_display *display = to_intel_display(intel_dp); 920 struct intel_connector *connector = intel_dp->attached_connector; 921 int idle_frames; 922 923 /* Let's use 6 as the minimum to cover all known cases including the 924 * off-by-one issue that HW has in some cases. 925 */ 926 idle_frames = max(6, connector->panel.vbt.psr.idle_frames); 927 idle_frames = max(idle_frames, intel_dp->psr.sink_sync_latency + 1); 928 929 if (drm_WARN_ON(display->drm, idle_frames > 0xf)) 930 idle_frames = 0xf; 931 932 return idle_frames; 933 } 934 935 static bool is_dc5_dc6_blocked(struct intel_dp *intel_dp) 936 { 937 struct intel_display *display = to_intel_display(intel_dp); 938 u32 current_dc_state = intel_display_power_get_current_dc_state(display); 939 struct intel_crtc *crtc = intel_crtc_for_pipe(display, intel_dp->psr.pipe); 940 struct drm_vblank_crtc *vblank = drm_crtc_vblank_crtc(&crtc->base); 941 942 return (current_dc_state != DC_STATE_EN_UPTO_DC5 && 943 current_dc_state != DC_STATE_EN_UPTO_DC6) || 944 intel_dp->psr.active_non_psr_pipes || 945 READ_ONCE(vblank->enabled); 946 } 947 948 static void hsw_activate_psr1(struct intel_dp *intel_dp) 949 { 950 struct intel_display *display = to_intel_display(intel_dp); 951 enum transcoder cpu_transcoder = intel_dp->psr.transcoder; 952 u32 max_sleep_time = 0x1f; 953 u32 val = EDP_PSR_ENABLE; 954 955 val |= EDP_PSR_IDLE_FRAMES(psr_compute_idle_frames(intel_dp)); 956 957 if (DISPLAY_VER(display) < 20) 958 val |= EDP_PSR_MAX_SLEEP_TIME(max_sleep_time); 959 960 if (display->platform.haswell) 961 val |= EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES; 962 963 if (intel_dp->psr.link_standby) 964 val |= EDP_PSR_LINK_STANDBY; 965 966 val |= intel_psr1_get_tp_time(intel_dp); 967 968 if (DISPLAY_VER(display) >= 8) 969 val |= EDP_PSR_CRC_ENABLE; 970 971 if (DISPLAY_VER(display) >= 20) 972 val |= LNL_EDP_PSR_ENTRY_SETUP_FRAMES(intel_dp->psr.entry_setup_frames); 973 974 intel_de_rmw(display, psr_ctl_reg(display, cpu_transcoder), 975 ~EDP_PSR_RESTORE_PSR_ACTIVE_CTX_MASK, val); 976 977 /* Wa_16025596647 */ 978 if ((DISPLAY_VER(display) == 20 || 979 IS_DISPLAY_VERx100_STEP(display, 3000, STEP_A0, STEP_B0)) && 980 is_dc5_dc6_blocked(intel_dp) && intel_dp->psr.pkg_c_latency_used) 981 intel_dmc_start_pkgc_exit_at_start_of_undelayed_vblank(display, 982 intel_dp->psr.pipe, 983 true); 984 } 985 986 static u32 intel_psr2_get_tp_time(struct intel_dp *intel_dp) 987 { 988 struct intel_display *display = to_intel_display(intel_dp); 989 struct intel_connector *connector = intel_dp->attached_connector; 990 u32 val = 0; 991 992 if (display->params.psr_safest_params) 993 return EDP_PSR2_TP2_TIME_2500us; 994 995 if (connector->panel.vbt.psr.psr2_tp2_tp3_wakeup_time_us >= 0 && 996 connector->panel.vbt.psr.psr2_tp2_tp3_wakeup_time_us <= 50) 997 val |= EDP_PSR2_TP2_TIME_50us; 998 else if (connector->panel.vbt.psr.psr2_tp2_tp3_wakeup_time_us <= 100) 999 val |= EDP_PSR2_TP2_TIME_100us; 1000 else if (connector->panel.vbt.psr.psr2_tp2_tp3_wakeup_time_us <= 500) 1001 val |= EDP_PSR2_TP2_TIME_500us; 1002 else 1003 val |= EDP_PSR2_TP2_TIME_2500us; 1004 1005 return val; 1006 } 1007 1008 static int 1009 psr2_block_count_lines(u8 io_wake_lines, u8 fast_wake_lines) 1010 { 1011 return io_wake_lines < 9 && fast_wake_lines < 9 ? 8 : 12; 1012 } 1013 1014 static int psr2_block_count(struct intel_dp *intel_dp) 1015 { 1016 return psr2_block_count_lines(intel_dp->psr.io_wake_lines, 1017 intel_dp->psr.fast_wake_lines) / 4; 1018 } 1019 1020 static u8 frames_before_su_entry(struct intel_dp *intel_dp) 1021 { 1022 u8 frames_before_su_entry; 1023 1024 frames_before_su_entry = max_t(u8, 1025 intel_dp->psr.sink_sync_latency + 1, 1026 2); 1027 1028 /* Entry setup frames must be at least 1 less than frames before SU entry */ 1029 if (intel_dp->psr.entry_setup_frames >= frames_before_su_entry) 1030 frames_before_su_entry = intel_dp->psr.entry_setup_frames + 1; 1031 1032 return frames_before_su_entry; 1033 } 1034 1035 static void dg2_activate_panel_replay(struct intel_dp *intel_dp) 1036 { 1037 struct intel_display *display = to_intel_display(intel_dp); 1038 struct intel_psr *psr = &intel_dp->psr; 1039 enum transcoder cpu_transcoder = intel_dp->psr.transcoder; 1040 1041 if (intel_dp_is_edp(intel_dp) && psr->sel_update_enabled) { 1042 u32 val = psr->su_region_et_enabled ? 1043 LNL_EDP_PSR2_SU_REGION_ET_ENABLE : 0; 1044 1045 if (intel_dp->psr.req_psr2_sdp_prior_scanline) 1046 val |= EDP_PSR2_SU_SDP_SCANLINE; 1047 1048 intel_de_write(display, EDP_PSR2_CTL(display, cpu_transcoder), 1049 val); 1050 } 1051 1052 intel_de_rmw(display, 1053 PSR2_MAN_TRK_CTL(display, intel_dp->psr.transcoder), 1054 0, ADLP_PSR2_MAN_TRK_CTL_SF_CONTINUOS_FULL_FRAME); 1055 1056 intel_de_rmw(display, TRANS_DP2_CTL(intel_dp->psr.transcoder), 0, 1057 TRANS_DP2_PANEL_REPLAY_ENABLE); 1058 } 1059 1060 static void hsw_activate_psr2(struct intel_dp *intel_dp) 1061 { 1062 struct intel_display *display = to_intel_display(intel_dp); 1063 enum transcoder cpu_transcoder = intel_dp->psr.transcoder; 1064 u32 val = EDP_PSR2_ENABLE; 1065 u32 psr_val = 0; 1066 u8 idle_frames; 1067 1068 /* Wa_16025596647 */ 1069 if ((DISPLAY_VER(display) == 20 || 1070 IS_DISPLAY_VERx100_STEP(display, 3000, STEP_A0, STEP_B0)) && 1071 is_dc5_dc6_blocked(intel_dp) && intel_dp->psr.pkg_c_latency_used) 1072 idle_frames = 0; 1073 else 1074 idle_frames = psr_compute_idle_frames(intel_dp); 1075 val |= EDP_PSR2_IDLE_FRAMES(idle_frames); 1076 1077 if (DISPLAY_VER(display) < 14 && !display->platform.alderlake_p) 1078 val |= EDP_SU_TRACK_ENABLE; 1079 1080 if (DISPLAY_VER(display) >= 10 && DISPLAY_VER(display) < 13) 1081 val |= EDP_Y_COORDINATE_ENABLE; 1082 1083 val |= EDP_PSR2_FRAME_BEFORE_SU(frames_before_su_entry(intel_dp)); 1084 1085 val |= intel_psr2_get_tp_time(intel_dp); 1086 1087 if (DISPLAY_VER(display) >= 12 && DISPLAY_VER(display) < 20) { 1088 if (psr2_block_count(intel_dp) > 2) 1089 val |= TGL_EDP_PSR2_BLOCK_COUNT_NUM_3; 1090 else 1091 val |= TGL_EDP_PSR2_BLOCK_COUNT_NUM_2; 1092 } 1093 1094 /* Wa_22012278275:adl-p */ 1095 if (display->platform.alderlake_p && IS_DISPLAY_STEP(display, STEP_A0, STEP_E0)) { 1096 static const u8 map[] = { 1097 2, /* 5 lines */ 1098 1, /* 6 lines */ 1099 0, /* 7 lines */ 1100 3, /* 8 lines */ 1101 6, /* 9 lines */ 1102 5, /* 10 lines */ 1103 4, /* 11 lines */ 1104 7, /* 12 lines */ 1105 }; 1106 /* 1107 * Still using the default IO_BUFFER_WAKE and FAST_WAKE, see 1108 * comments below for more information 1109 */ 1110 int tmp; 1111 1112 tmp = map[intel_dp->psr.io_wake_lines - 1113 TGL_EDP_PSR2_IO_BUFFER_WAKE_MIN_LINES]; 1114 val |= TGL_EDP_PSR2_IO_BUFFER_WAKE(tmp + TGL_EDP_PSR2_IO_BUFFER_WAKE_MIN_LINES); 1115 1116 tmp = map[intel_dp->psr.fast_wake_lines - TGL_EDP_PSR2_FAST_WAKE_MIN_LINES]; 1117 val |= TGL_EDP_PSR2_FAST_WAKE(tmp + TGL_EDP_PSR2_FAST_WAKE_MIN_LINES); 1118 } else if (DISPLAY_VER(display) >= 20) { 1119 val |= LNL_EDP_PSR2_IO_BUFFER_WAKE(intel_dp->psr.io_wake_lines); 1120 } else if (DISPLAY_VER(display) >= 12) { 1121 val |= TGL_EDP_PSR2_IO_BUFFER_WAKE(intel_dp->psr.io_wake_lines); 1122 val |= TGL_EDP_PSR2_FAST_WAKE(intel_dp->psr.fast_wake_lines); 1123 } else if (DISPLAY_VER(display) >= 9) { 1124 val |= EDP_PSR2_IO_BUFFER_WAKE(intel_dp->psr.io_wake_lines); 1125 val |= EDP_PSR2_FAST_WAKE(intel_dp->psr.fast_wake_lines); 1126 } 1127 1128 if (intel_dp->psr.req_psr2_sdp_prior_scanline) 1129 val |= EDP_PSR2_SU_SDP_SCANLINE; 1130 1131 if (DISPLAY_VER(display) >= 20) 1132 psr_val |= LNL_EDP_PSR_ENTRY_SETUP_FRAMES(intel_dp->psr.entry_setup_frames); 1133 1134 if (intel_dp->psr.psr2_sel_fetch_enabled) { 1135 u32 tmp; 1136 1137 tmp = intel_de_read(display, 1138 PSR2_MAN_TRK_CTL(display, cpu_transcoder)); 1139 drm_WARN_ON(display->drm, !(tmp & PSR2_MAN_TRK_CTL_ENABLE)); 1140 } else if (HAS_PSR2_SEL_FETCH(display)) { 1141 intel_de_write(display, 1142 PSR2_MAN_TRK_CTL(display, cpu_transcoder), 0); 1143 } 1144 1145 if (intel_dp->psr.su_region_et_enabled) 1146 val |= LNL_EDP_PSR2_SU_REGION_ET_ENABLE; 1147 1148 /* 1149 * PSR2 HW is incorrectly using EDP_PSR_TP1_TP3_SEL and BSpec is 1150 * recommending keep this bit unset while PSR2 is enabled. 1151 */ 1152 intel_de_write(display, psr_ctl_reg(display, cpu_transcoder), psr_val); 1153 1154 intel_de_write(display, EDP_PSR2_CTL(display, cpu_transcoder), val); 1155 } 1156 1157 static bool 1158 transcoder_has_psr2(struct intel_display *display, enum transcoder cpu_transcoder) 1159 { 1160 if (display->platform.alderlake_p || DISPLAY_VER(display) >= 14) 1161 return cpu_transcoder == TRANSCODER_A || cpu_transcoder == TRANSCODER_B; 1162 else if (DISPLAY_VER(display) >= 12) 1163 return cpu_transcoder == TRANSCODER_A; 1164 else if (DISPLAY_VER(display) >= 9) 1165 return cpu_transcoder == TRANSCODER_EDP; 1166 else 1167 return false; 1168 } 1169 1170 static u32 intel_get_frame_time_us(const struct intel_crtc_state *crtc_state) 1171 { 1172 if (!crtc_state->hw.active) 1173 return 0; 1174 1175 return DIV_ROUND_UP(1000 * 1000, 1176 drm_mode_vrefresh(&crtc_state->hw.adjusted_mode)); 1177 } 1178 1179 static void psr2_program_idle_frames(struct intel_dp *intel_dp, 1180 u32 idle_frames) 1181 { 1182 struct intel_display *display = to_intel_display(intel_dp); 1183 enum transcoder cpu_transcoder = intel_dp->psr.transcoder; 1184 1185 intel_de_rmw(display, EDP_PSR2_CTL(display, cpu_transcoder), 1186 EDP_PSR2_IDLE_FRAMES_MASK, 1187 EDP_PSR2_IDLE_FRAMES(idle_frames)); 1188 } 1189 1190 static void tgl_psr2_enable_dc3co(struct intel_dp *intel_dp) 1191 { 1192 struct intel_display *display = to_intel_display(intel_dp); 1193 1194 psr2_program_idle_frames(intel_dp, 0); 1195 intel_display_power_set_target_dc_state(display, DC_STATE_EN_DC3CO); 1196 } 1197 1198 static void tgl_psr2_disable_dc3co(struct intel_dp *intel_dp) 1199 { 1200 struct intel_display *display = to_intel_display(intel_dp); 1201 1202 intel_display_power_set_target_dc_state(display, DC_STATE_EN_UPTO_DC6); 1203 psr2_program_idle_frames(intel_dp, psr_compute_idle_frames(intel_dp)); 1204 } 1205 1206 static void tgl_dc3co_disable_work(struct work_struct *work) 1207 { 1208 struct intel_dp *intel_dp = 1209 container_of(work, typeof(*intel_dp), psr.dc3co_work.work); 1210 1211 mutex_lock(&intel_dp->psr.lock); 1212 /* If delayed work is pending, it is not idle */ 1213 if (delayed_work_pending(&intel_dp->psr.dc3co_work)) 1214 goto unlock; 1215 1216 tgl_psr2_disable_dc3co(intel_dp); 1217 unlock: 1218 mutex_unlock(&intel_dp->psr.lock); 1219 } 1220 1221 static void tgl_disallow_dc3co_on_psr2_exit(struct intel_dp *intel_dp) 1222 { 1223 if (!intel_dp->psr.dc3co_exitline) 1224 return; 1225 1226 cancel_delayed_work(&intel_dp->psr.dc3co_work); 1227 /* Before PSR2 exit disallow dc3co*/ 1228 tgl_psr2_disable_dc3co(intel_dp); 1229 } 1230 1231 static bool 1232 dc3co_is_pipe_port_compatible(struct intel_dp *intel_dp, 1233 struct intel_crtc_state *crtc_state) 1234 { 1235 struct intel_display *display = to_intel_display(intel_dp); 1236 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 1237 enum pipe pipe = to_intel_crtc(crtc_state->uapi.crtc)->pipe; 1238 enum port port = dig_port->base.port; 1239 1240 if (display->platform.alderlake_p || DISPLAY_VER(display) >= 14) 1241 return pipe <= PIPE_B && port <= PORT_B; 1242 else 1243 return pipe == PIPE_A && port == PORT_A; 1244 } 1245 1246 static void 1247 tgl_dc3co_exitline_compute_config(struct intel_dp *intel_dp, 1248 struct intel_crtc_state *crtc_state) 1249 { 1250 struct intel_display *display = to_intel_display(intel_dp); 1251 const u32 crtc_vdisplay = crtc_state->uapi.adjusted_mode.crtc_vdisplay; 1252 struct i915_power_domains *power_domains = &display->power.domains; 1253 u32 exit_scanlines; 1254 1255 /* 1256 * FIXME: Due to the changed sequence of activating/deactivating DC3CO, 1257 * disable DC3CO until the changed dc3co activating/deactivating sequence 1258 * is applied. B.Specs:49196 1259 */ 1260 return; 1261 1262 /* 1263 * DMC's DC3CO exit mechanism has an issue with Selective Fecth 1264 * TODO: when the issue is addressed, this restriction should be removed. 1265 */ 1266 if (crtc_state->enable_psr2_sel_fetch) 1267 return; 1268 1269 if (!(power_domains->allowed_dc_mask & DC_STATE_EN_DC3CO)) 1270 return; 1271 1272 if (!dc3co_is_pipe_port_compatible(intel_dp, crtc_state)) 1273 return; 1274 1275 /* Wa_16011303918:adl-p */ 1276 if (display->platform.alderlake_p && IS_DISPLAY_STEP(display, STEP_A0, STEP_B0)) 1277 return; 1278 1279 /* 1280 * DC3CO Exit time 200us B.Spec 49196 1281 * PSR2 transcoder Early Exit scanlines = ROUNDUP(200 / line time) + 1 1282 */ 1283 exit_scanlines = 1284 intel_usecs_to_scanlines(&crtc_state->uapi.adjusted_mode, 200) + 1; 1285 1286 if (drm_WARN_ON(display->drm, exit_scanlines > crtc_vdisplay)) 1287 return; 1288 1289 crtc_state->dc3co_exitline = crtc_vdisplay - exit_scanlines; 1290 } 1291 1292 static bool intel_psr2_sel_fetch_config_valid(struct intel_dp *intel_dp, 1293 struct intel_crtc_state *crtc_state) 1294 { 1295 struct intel_display *display = to_intel_display(intel_dp); 1296 1297 if (!display->params.enable_psr2_sel_fetch && 1298 intel_dp->psr.debug != I915_PSR_DEBUG_ENABLE_SEL_FETCH) { 1299 drm_dbg_kms(display->drm, 1300 "PSR2 sel fetch not enabled, disabled by parameter\n"); 1301 return false; 1302 } 1303 1304 return crtc_state->enable_psr2_sel_fetch = true; 1305 } 1306 1307 static bool psr2_granularity_check(struct intel_dp *intel_dp, 1308 struct intel_crtc_state *crtc_state) 1309 { 1310 struct intel_display *display = to_intel_display(intel_dp); 1311 const struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config; 1312 const int crtc_hdisplay = crtc_state->hw.adjusted_mode.crtc_hdisplay; 1313 const int crtc_vdisplay = crtc_state->hw.adjusted_mode.crtc_vdisplay; 1314 u16 y_granularity = 0; 1315 1316 /* PSR2 HW only send full lines so we only need to validate the width */ 1317 if (crtc_hdisplay % intel_dp->psr.su_w_granularity) 1318 return false; 1319 1320 if (crtc_vdisplay % intel_dp->psr.su_y_granularity) 1321 return false; 1322 1323 /* HW tracking is only aligned to 4 lines */ 1324 if (!crtc_state->enable_psr2_sel_fetch) 1325 return intel_dp->psr.su_y_granularity == 4; 1326 1327 /* 1328 * adl_p and mtl platforms have 1 line granularity. 1329 * For other platforms with SW tracking we can adjust the y coordinates 1330 * to match sink requirement if multiple of 4. 1331 */ 1332 if (display->platform.alderlake_p || DISPLAY_VER(display) >= 14) 1333 y_granularity = intel_dp->psr.su_y_granularity; 1334 else if (intel_dp->psr.su_y_granularity <= 2) 1335 y_granularity = 4; 1336 else if ((intel_dp->psr.su_y_granularity % 4) == 0) 1337 y_granularity = intel_dp->psr.su_y_granularity; 1338 1339 if (y_granularity == 0 || crtc_vdisplay % y_granularity) 1340 return false; 1341 1342 if (crtc_state->dsc.compression_enable && 1343 vdsc_cfg->slice_height % y_granularity) 1344 return false; 1345 1346 crtc_state->su_y_granularity = y_granularity; 1347 return true; 1348 } 1349 1350 static bool _compute_psr2_sdp_prior_scanline_indication(struct intel_dp *intel_dp, 1351 struct intel_crtc_state *crtc_state) 1352 { 1353 struct intel_display *display = to_intel_display(intel_dp); 1354 const struct drm_display_mode *adjusted_mode = &crtc_state->uapi.adjusted_mode; 1355 u32 hblank_total, hblank_ns, req_ns; 1356 1357 hblank_total = adjusted_mode->crtc_hblank_end - adjusted_mode->crtc_hblank_start; 1358 hblank_ns = div_u64(1000000ULL * hblank_total, adjusted_mode->crtc_clock); 1359 1360 /* From spec: ((60 / number of lanes) + 11) * 1000 / symbol clock frequency MHz */ 1361 req_ns = ((60 / crtc_state->lane_count) + 11) * 1000 / (crtc_state->port_clock / 1000); 1362 1363 if ((hblank_ns - req_ns) > 100) 1364 return true; 1365 1366 /* Not supported <13 / Wa_22012279113:adl-p */ 1367 if (DISPLAY_VER(display) < 14 || intel_dp->edp_dpcd[0] < DP_EDP_14b) 1368 return false; 1369 1370 crtc_state->req_psr2_sdp_prior_scanline = true; 1371 return true; 1372 } 1373 1374 static int intel_psr_entry_setup_frames(struct intel_dp *intel_dp, 1375 const struct drm_display_mode *adjusted_mode) 1376 { 1377 struct intel_display *display = to_intel_display(intel_dp); 1378 int psr_setup_time = drm_dp_psr_setup_time(intel_dp->psr_dpcd); 1379 int entry_setup_frames = 0; 1380 1381 if (psr_setup_time < 0) { 1382 drm_dbg_kms(display->drm, 1383 "PSR condition failed: Invalid PSR setup time (0x%02x)\n", 1384 intel_dp->psr_dpcd[1]); 1385 return -ETIME; 1386 } 1387 1388 if (intel_usecs_to_scanlines(adjusted_mode, psr_setup_time) > 1389 adjusted_mode->crtc_vtotal - adjusted_mode->crtc_vdisplay - 1) { 1390 if (DISPLAY_VER(display) >= 20) { 1391 /* setup entry frames can be up to 3 frames */ 1392 entry_setup_frames = 1; 1393 drm_dbg_kms(display->drm, 1394 "PSR setup entry frames %d\n", 1395 entry_setup_frames); 1396 } else { 1397 drm_dbg_kms(display->drm, 1398 "PSR condition failed: PSR setup time (%d us) too long\n", 1399 psr_setup_time); 1400 return -ETIME; 1401 } 1402 } 1403 1404 return entry_setup_frames; 1405 } 1406 1407 static 1408 int _intel_psr_min_set_context_latency(const struct intel_crtc_state *crtc_state, 1409 bool needs_panel_replay, 1410 bool needs_sel_update) 1411 { 1412 struct intel_display *display = to_intel_display(crtc_state); 1413 1414 if (!crtc_state->has_psr) 1415 return 0; 1416 1417 /* Wa_14015401596 */ 1418 if (intel_vrr_possible(crtc_state) && IS_DISPLAY_VER(display, 13, 14)) 1419 return 1; 1420 1421 /* Rest is for SRD_STATUS needed on LunarLake and onwards */ 1422 if (DISPLAY_VER(display) < 20) 1423 return 0; 1424 1425 /* 1426 * Comment on SRD_STATUS register in Bspec for LunarLake and onwards: 1427 * 1428 * To deterministically capture the transition of the state machine 1429 * going from SRDOFFACK to IDLE, the delayed V. Blank should be at least 1430 * one line after the non-delayed V. Blank. 1431 * 1432 * Legacy TG: TRANS_SET_CONTEXT_LATENCY > 0 1433 * VRR TG: TRANS_VRR_CTL[ VRR Guardband ] < (TRANS_VRR_VMAX[ VRR Vmax ] 1434 * - TRANS_VTOTAL[ Vertical Active ]) 1435 * 1436 * SRD_STATUS is used only by PSR1 on PantherLake. 1437 * SRD_STATUS is used by PSR1 and Panel Replay DP on LunarLake. 1438 */ 1439 1440 if (DISPLAY_VER(display) >= 30 && (needs_panel_replay || 1441 needs_sel_update)) 1442 return 0; 1443 else if (DISPLAY_VER(display) < 30 && (needs_sel_update || 1444 intel_crtc_has_type(crtc_state, 1445 INTEL_OUTPUT_EDP))) 1446 return 0; 1447 else 1448 return 1; 1449 } 1450 1451 static bool _wake_lines_fit_into_vblank(const struct intel_crtc_state *crtc_state, 1452 int vblank, 1453 int wake_lines) 1454 { 1455 if (crtc_state->req_psr2_sdp_prior_scanline) 1456 vblank -= 1; 1457 1458 /* Vblank >= PSR2_CTL Block Count Number maximum line count */ 1459 if (vblank < wake_lines) 1460 return false; 1461 1462 return true; 1463 } 1464 1465 static bool wake_lines_fit_into_vblank(struct intel_dp *intel_dp, 1466 const struct intel_crtc_state *crtc_state, 1467 bool aux_less, 1468 bool needs_panel_replay, 1469 bool needs_sel_update) 1470 { 1471 struct intel_display *display = to_intel_display(intel_dp); 1472 int vblank = crtc_state->hw.adjusted_mode.crtc_vblank_end - 1473 crtc_state->hw.adjusted_mode.crtc_vblank_start; 1474 int wake_lines; 1475 int scl = _intel_psr_min_set_context_latency(crtc_state, 1476 needs_panel_replay, 1477 needs_sel_update); 1478 vblank -= scl; 1479 1480 if (aux_less) 1481 wake_lines = crtc_state->alpm_state.aux_less_wake_lines; 1482 else 1483 wake_lines = DISPLAY_VER(display) < 20 ? 1484 psr2_block_count_lines(crtc_state->alpm_state.io_wake_lines, 1485 crtc_state->alpm_state.fast_wake_lines) : 1486 crtc_state->alpm_state.io_wake_lines; 1487 1488 /* 1489 * Guardband has not been computed yet, so we conservatively check if the 1490 * full vblank duration is sufficient to accommodate wake line requirements 1491 * for PSR features like Panel Replay and Selective Update. 1492 * 1493 * Once the actual guardband is available, a more accurate validation is 1494 * performed in intel_psr_compute_config_late(), and PSR features are 1495 * disabled if wake lines exceed the available guardband. 1496 */ 1497 return _wake_lines_fit_into_vblank(crtc_state, vblank, wake_lines); 1498 } 1499 1500 static bool alpm_config_valid(struct intel_dp *intel_dp, 1501 struct intel_crtc_state *crtc_state, 1502 bool aux_less, 1503 bool needs_panel_replay, 1504 bool needs_sel_update) 1505 { 1506 struct intel_display *display = to_intel_display(intel_dp); 1507 1508 if (!intel_alpm_compute_params(intel_dp, crtc_state)) { 1509 drm_dbg_kms(display->drm, 1510 "PSR2/Panel Replay not enabled, Unable to use long enough wake times\n"); 1511 return false; 1512 } 1513 1514 if (!wake_lines_fit_into_vblank(intel_dp, crtc_state, aux_less, 1515 needs_panel_replay, needs_sel_update)) { 1516 drm_dbg_kms(display->drm, 1517 "PSR2/Panel Replay not enabled, too short vblank time\n"); 1518 return false; 1519 } 1520 1521 return true; 1522 } 1523 1524 static bool intel_psr2_config_valid(struct intel_dp *intel_dp, 1525 struct intel_crtc_state *crtc_state) 1526 { 1527 struct intel_display *display = to_intel_display(intel_dp); 1528 int crtc_hdisplay = crtc_state->hw.adjusted_mode.crtc_hdisplay; 1529 int crtc_vdisplay = crtc_state->hw.adjusted_mode.crtc_vdisplay; 1530 int psr_max_h = 0, psr_max_v = 0, max_bpp = 0; 1531 1532 if (!intel_dp->psr.sink_psr2_support || display->params.enable_psr == 1) 1533 return false; 1534 1535 /* JSL and EHL only supports eDP 1.3 */ 1536 if (display->platform.jasperlake || display->platform.elkhartlake) { 1537 drm_dbg_kms(display->drm, "PSR2 not supported by phy\n"); 1538 return false; 1539 } 1540 1541 /* Wa_16011181250 */ 1542 if (display->platform.rocketlake || display->platform.alderlake_s || 1543 display->platform.dg2) { 1544 drm_dbg_kms(display->drm, 1545 "PSR2 is defeatured for this platform\n"); 1546 return false; 1547 } 1548 1549 if (display->platform.alderlake_p && IS_DISPLAY_STEP(display, STEP_A0, STEP_B0)) { 1550 drm_dbg_kms(display->drm, 1551 "PSR2 not completely functional in this stepping\n"); 1552 return false; 1553 } 1554 1555 if (!transcoder_has_psr2(display, crtc_state->cpu_transcoder)) { 1556 drm_dbg_kms(display->drm, 1557 "PSR2 not supported in transcoder %s\n", 1558 transcoder_name(crtc_state->cpu_transcoder)); 1559 return false; 1560 } 1561 1562 /* 1563 * DSC and PSR2 cannot be enabled simultaneously. If a requested 1564 * resolution requires DSC to be enabled, priority is given to DSC 1565 * over PSR2. 1566 */ 1567 if (crtc_state->dsc.compression_enable && 1568 (DISPLAY_VER(display) < 14 && !display->platform.alderlake_p)) { 1569 drm_dbg_kms(display->drm, 1570 "PSR2 cannot be enabled since DSC is enabled\n"); 1571 return false; 1572 } 1573 1574 if (DISPLAY_VER(display) >= 20) { 1575 psr_max_h = crtc_hdisplay; 1576 psr_max_v = crtc_vdisplay; 1577 max_bpp = crtc_state->pipe_bpp; 1578 } else if (IS_DISPLAY_VER(display, 12, 14)) { 1579 psr_max_h = 5120; 1580 psr_max_v = 3200; 1581 max_bpp = 30; 1582 } else if (IS_DISPLAY_VER(display, 10, 11)) { 1583 psr_max_h = 4096; 1584 psr_max_v = 2304; 1585 max_bpp = 24; 1586 } else if (DISPLAY_VER(display) == 9) { 1587 psr_max_h = 3640; 1588 psr_max_v = 2304; 1589 max_bpp = 24; 1590 } 1591 1592 if (crtc_state->pipe_bpp > max_bpp) { 1593 drm_dbg_kms(display->drm, 1594 "PSR2 not enabled, pipe bpp %d > max supported %d\n", 1595 crtc_state->pipe_bpp, max_bpp); 1596 return false; 1597 } 1598 1599 /* Wa_16011303918:adl-p */ 1600 if (crtc_state->vrr.enable && 1601 display->platform.alderlake_p && IS_DISPLAY_STEP(display, STEP_A0, STEP_B0)) { 1602 drm_dbg_kms(display->drm, 1603 "PSR2 not enabled, not compatible with HW stepping + VRR\n"); 1604 return false; 1605 } 1606 1607 if (!alpm_config_valid(intel_dp, crtc_state, false, false, true)) 1608 return false; 1609 1610 if (!crtc_state->enable_psr2_sel_fetch && 1611 (crtc_hdisplay > psr_max_h || crtc_vdisplay > psr_max_v)) { 1612 drm_dbg_kms(display->drm, 1613 "PSR2 not enabled, resolution %dx%d > max supported %dx%d\n", 1614 crtc_hdisplay, crtc_vdisplay, 1615 psr_max_h, psr_max_v); 1616 return false; 1617 } 1618 1619 tgl_dc3co_exitline_compute_config(intel_dp, crtc_state); 1620 1621 return true; 1622 } 1623 1624 static bool intel_sel_update_config_valid(struct intel_dp *intel_dp, 1625 struct intel_crtc_state *crtc_state) 1626 { 1627 struct intel_display *display = to_intel_display(intel_dp); 1628 1629 if (HAS_PSR2_SEL_FETCH(display) && 1630 !intel_psr2_sel_fetch_config_valid(intel_dp, crtc_state) && 1631 !HAS_PSR_HW_TRACKING(display)) { 1632 drm_dbg_kms(display->drm, 1633 "Selective update not enabled, selective fetch not valid and no HW tracking available\n"); 1634 goto unsupported; 1635 } 1636 1637 if (!sel_update_global_enabled(intel_dp)) { 1638 drm_dbg_kms(display->drm, 1639 "Selective update disabled by flag\n"); 1640 goto unsupported; 1641 } 1642 1643 if (!crtc_state->has_panel_replay && !intel_psr2_config_valid(intel_dp, crtc_state)) 1644 goto unsupported; 1645 1646 if (!_compute_psr2_sdp_prior_scanline_indication(intel_dp, crtc_state)) { 1647 drm_dbg_kms(display->drm, 1648 "Selective update not enabled, SDP indication do not fit in hblank\n"); 1649 goto unsupported; 1650 } 1651 1652 if (crtc_state->has_panel_replay) { 1653 if (DISPLAY_VER(display) < 14) 1654 goto unsupported; 1655 1656 if (!intel_dp->psr.sink_panel_replay_su_support) 1657 goto unsupported; 1658 1659 if (intel_dsc_enabled_on_link(crtc_state) && 1660 intel_dp->psr.sink_panel_replay_dsc_support != 1661 INTEL_DP_PANEL_REPLAY_DSC_SELECTIVE_UPDATE) { 1662 drm_dbg_kms(display->drm, 1663 "Selective update with Panel Replay not enabled because it's not supported with DSC\n"); 1664 goto unsupported; 1665 } 1666 } 1667 1668 if (crtc_state->crc_enabled) { 1669 drm_dbg_kms(display->drm, 1670 "Selective update not enabled because it would inhibit pipe CRC calculation\n"); 1671 goto unsupported; 1672 } 1673 1674 if (!psr2_granularity_check(intel_dp, crtc_state)) { 1675 drm_dbg_kms(display->drm, 1676 "Selective update not enabled, SU granularity not compatible\n"); 1677 goto unsupported; 1678 } 1679 1680 crtc_state->enable_psr2_su_region_et = 1681 psr2_su_region_et_valid(intel_dp, crtc_state->has_panel_replay); 1682 1683 return true; 1684 1685 unsupported: 1686 crtc_state->enable_psr2_sel_fetch = false; 1687 return false; 1688 } 1689 1690 static bool _psr_compute_config(struct intel_dp *intel_dp, 1691 struct intel_crtc_state *crtc_state) 1692 { 1693 struct intel_display *display = to_intel_display(intel_dp); 1694 const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; 1695 int entry_setup_frames; 1696 1697 if (!CAN_PSR(intel_dp) || !display->params.enable_psr) 1698 return false; 1699 1700 /* 1701 * Currently PSR doesn't work reliably with VRR enabled. 1702 */ 1703 if (crtc_state->vrr.enable) 1704 return false; 1705 1706 entry_setup_frames = intel_psr_entry_setup_frames(intel_dp, adjusted_mode); 1707 1708 if (entry_setup_frames >= 0) { 1709 intel_dp->psr.entry_setup_frames = entry_setup_frames; 1710 } else { 1711 crtc_state->no_psr_reason = "PSR setup timing not met"; 1712 drm_dbg_kms(display->drm, 1713 "PSR condition failed: PSR setup timing not met\n"); 1714 return false; 1715 } 1716 1717 return true; 1718 } 1719 1720 static bool 1721 _panel_replay_compute_config(struct intel_dp *intel_dp, 1722 struct intel_crtc_state *crtc_state, 1723 const struct drm_connector_state *conn_state) 1724 { 1725 struct intel_display *display = to_intel_display(intel_dp); 1726 struct intel_connector *connector = 1727 to_intel_connector(conn_state->connector); 1728 struct intel_hdcp *hdcp = &connector->hdcp; 1729 1730 if (!CAN_PANEL_REPLAY(intel_dp)) 1731 return false; 1732 1733 if (!panel_replay_global_enabled(intel_dp)) { 1734 drm_dbg_kms(display->drm, "Panel Replay disabled by flag\n"); 1735 return false; 1736 } 1737 1738 if (crtc_state->crc_enabled) { 1739 drm_dbg_kms(display->drm, 1740 "Panel Replay not enabled because it would inhibit pipe CRC calculation\n"); 1741 return false; 1742 } 1743 1744 if (intel_dsc_enabled_on_link(crtc_state) && 1745 intel_dp->psr.sink_panel_replay_dsc_support == 1746 INTEL_DP_PANEL_REPLAY_DSC_NOT_SUPPORTED) { 1747 drm_dbg_kms(display->drm, 1748 "Panel Replay not enabled because it's not supported with DSC\n"); 1749 return false; 1750 } 1751 1752 if (!intel_dp_is_edp(intel_dp)) 1753 return true; 1754 1755 /* Remaining checks are for eDP only */ 1756 1757 if (to_intel_crtc(crtc_state->uapi.crtc)->pipe != PIPE_A && 1758 to_intel_crtc(crtc_state->uapi.crtc)->pipe != PIPE_B) 1759 return false; 1760 1761 /* 128b/132b Panel Replay is not supported on eDP */ 1762 if (intel_dp_is_uhbr(crtc_state)) { 1763 drm_dbg_kms(display->drm, 1764 "Panel Replay is not supported with 128b/132b\n"); 1765 return false; 1766 } 1767 1768 /* HW will not allow Panel Replay on eDP when HDCP enabled */ 1769 if (conn_state->content_protection == 1770 DRM_MODE_CONTENT_PROTECTION_DESIRED || 1771 (conn_state->content_protection == 1772 DRM_MODE_CONTENT_PROTECTION_ENABLED && hdcp->value == 1773 DRM_MODE_CONTENT_PROTECTION_UNDESIRED)) { 1774 drm_dbg_kms(display->drm, 1775 "Panel Replay is not supported with HDCP\n"); 1776 return false; 1777 } 1778 1779 if (!alpm_config_valid(intel_dp, crtc_state, true, true, false)) 1780 return false; 1781 1782 return true; 1783 } 1784 1785 static bool intel_psr_needs_wa_18037818876(struct intel_dp *intel_dp, 1786 struct intel_crtc_state *crtc_state) 1787 { 1788 struct intel_display *display = to_intel_display(intel_dp); 1789 1790 return (DISPLAY_VER(display) == 20 && intel_dp->psr.entry_setup_frames > 0 && 1791 !crtc_state->has_sel_update); 1792 } 1793 1794 static 1795 void intel_psr_set_non_psr_pipes(struct intel_dp *intel_dp, 1796 struct intel_crtc_state *crtc_state) 1797 { 1798 struct intel_display *display = to_intel_display(intel_dp); 1799 struct intel_atomic_state *state = to_intel_atomic_state(crtc_state->uapi.state); 1800 struct intel_crtc *crtc; 1801 u8 active_pipes = 0; 1802 1803 /* Wa_16025596647 */ 1804 if (DISPLAY_VER(display) != 20 && 1805 !IS_DISPLAY_VERx100_STEP(display, 3000, STEP_A0, STEP_B0)) 1806 return; 1807 1808 /* Not needed by Panel Replay */ 1809 if (crtc_state->has_panel_replay) 1810 return; 1811 1812 /* We ignore possible secondary PSR/Panel Replay capable eDP */ 1813 for_each_intel_crtc(display->drm, crtc) 1814 active_pipes |= crtc->active ? BIT(crtc->pipe) : 0; 1815 1816 active_pipes = intel_calc_active_pipes(state, active_pipes); 1817 1818 crtc_state->active_non_psr_pipes = active_pipes & 1819 ~BIT(to_intel_crtc(crtc_state->uapi.crtc)->pipe); 1820 } 1821 1822 void intel_psr_compute_config(struct intel_dp *intel_dp, 1823 struct intel_crtc_state *crtc_state, 1824 struct drm_connector_state *conn_state) 1825 { 1826 struct intel_display *display = to_intel_display(intel_dp); 1827 const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; 1828 1829 if (!psr_global_enabled(intel_dp)) { 1830 drm_dbg_kms(display->drm, "PSR disabled by flag\n"); 1831 return; 1832 } 1833 1834 if (intel_dp->psr.sink_not_reliable) { 1835 drm_dbg_kms(display->drm, 1836 "PSR sink implementation is not reliable\n"); 1837 return; 1838 } 1839 1840 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { 1841 drm_dbg_kms(display->drm, 1842 "PSR condition failed: Interlaced mode enabled\n"); 1843 return; 1844 } 1845 1846 /* 1847 * FIXME figure out what is wrong with PSR+joiner and 1848 * fix it. Presumably something related to the fact that 1849 * PSR is a transcoder level feature. 1850 */ 1851 if (crtc_state->joiner_pipes) { 1852 drm_dbg_kms(display->drm, 1853 "PSR disabled due to joiner\n"); 1854 return; 1855 } 1856 1857 /* Only used for state verification. */ 1858 crtc_state->panel_replay_dsc_support = intel_dp->psr.sink_panel_replay_dsc_support; 1859 crtc_state->has_panel_replay = _panel_replay_compute_config(intel_dp, 1860 crtc_state, 1861 conn_state); 1862 1863 crtc_state->has_psr = crtc_state->has_panel_replay ? true : 1864 _psr_compute_config(intel_dp, crtc_state); 1865 1866 if (!crtc_state->has_psr) 1867 return; 1868 1869 crtc_state->has_sel_update = intel_sel_update_config_valid(intel_dp, crtc_state); 1870 } 1871 1872 void intel_psr_get_config(struct intel_encoder *encoder, 1873 struct intel_crtc_state *pipe_config) 1874 { 1875 struct intel_display *display = to_intel_display(encoder); 1876 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 1877 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; 1878 struct intel_dp *intel_dp; 1879 u32 val; 1880 1881 if (!dig_port) 1882 return; 1883 1884 intel_dp = &dig_port->dp; 1885 if (!(CAN_PSR(intel_dp) || CAN_PANEL_REPLAY(intel_dp))) 1886 return; 1887 1888 mutex_lock(&intel_dp->psr.lock); 1889 if (!intel_dp->psr.enabled) 1890 goto unlock; 1891 1892 if (intel_dp->psr.panel_replay_enabled) { 1893 pipe_config->has_psr = pipe_config->has_panel_replay = true; 1894 } else { 1895 /* 1896 * Not possible to read EDP_PSR/PSR2_CTL registers as it is 1897 * enabled/disabled because of frontbuffer tracking and others. 1898 */ 1899 pipe_config->has_psr = true; 1900 } 1901 1902 pipe_config->has_sel_update = intel_dp->psr.sel_update_enabled; 1903 pipe_config->infoframes.enable |= intel_hdmi_infoframe_enable(DP_SDP_VSC); 1904 1905 if (!intel_dp->psr.sel_update_enabled) 1906 goto unlock; 1907 1908 if (HAS_PSR2_SEL_FETCH(display)) { 1909 val = intel_de_read(display, 1910 PSR2_MAN_TRK_CTL(display, cpu_transcoder)); 1911 if (val & PSR2_MAN_TRK_CTL_ENABLE) 1912 pipe_config->enable_psr2_sel_fetch = true; 1913 } 1914 1915 pipe_config->enable_psr2_su_region_et = intel_dp->psr.su_region_et_enabled; 1916 1917 if (DISPLAY_VER(display) >= 12) { 1918 val = intel_de_read(display, 1919 TRANS_EXITLINE(display, cpu_transcoder)); 1920 pipe_config->dc3co_exitline = REG_FIELD_GET(EXITLINE_MASK, val); 1921 } 1922 unlock: 1923 mutex_unlock(&intel_dp->psr.lock); 1924 } 1925 1926 static void intel_psr_activate(struct intel_dp *intel_dp) 1927 { 1928 struct intel_display *display = to_intel_display(intel_dp); 1929 enum transcoder cpu_transcoder = intel_dp->psr.transcoder; 1930 1931 drm_WARN_ON(display->drm, 1932 transcoder_has_psr2(display, cpu_transcoder) && 1933 intel_de_read(display, EDP_PSR2_CTL(display, cpu_transcoder)) & EDP_PSR2_ENABLE); 1934 1935 drm_WARN_ON(display->drm, 1936 intel_de_read(display, psr_ctl_reg(display, cpu_transcoder)) & EDP_PSR_ENABLE); 1937 1938 drm_WARN_ON(display->drm, intel_dp->psr.active); 1939 1940 drm_WARN_ON(display->drm, !intel_dp->psr.enabled); 1941 1942 lockdep_assert_held(&intel_dp->psr.lock); 1943 1944 /* psr1, psr2 and panel-replay are mutually exclusive.*/ 1945 if (intel_dp->psr.panel_replay_enabled) 1946 dg2_activate_panel_replay(intel_dp); 1947 else if (intel_dp->psr.sel_update_enabled) 1948 hsw_activate_psr2(intel_dp); 1949 else 1950 hsw_activate_psr1(intel_dp); 1951 1952 intel_dp->psr.active = true; 1953 intel_dp->psr.no_psr_reason = NULL; 1954 } 1955 1956 /* 1957 * Wa_16013835468 1958 * Wa_14015648006 1959 */ 1960 static void wm_optimization_wa(struct intel_dp *intel_dp, 1961 const struct intel_crtc_state *crtc_state) 1962 { 1963 struct intel_display *display = to_intel_display(intel_dp); 1964 enum pipe pipe = intel_dp->psr.pipe; 1965 bool activate = false; 1966 1967 /* Wa_14015648006 */ 1968 if (IS_DISPLAY_VER(display, 11, 14) && crtc_state->wm_level_disabled) 1969 activate = true; 1970 1971 /* Wa_16013835468 */ 1972 if (DISPLAY_VER(display) == 12 && 1973 crtc_state->hw.adjusted_mode.crtc_vblank_start != 1974 crtc_state->hw.adjusted_mode.crtc_vdisplay) 1975 activate = true; 1976 1977 if (activate) 1978 intel_de_rmw(display, GEN8_CHICKEN_DCPR_1, 1979 0, LATENCY_REPORTING_REMOVED(pipe)); 1980 else 1981 intel_de_rmw(display, GEN8_CHICKEN_DCPR_1, 1982 LATENCY_REPORTING_REMOVED(pipe), 0); 1983 } 1984 1985 static void intel_psr_enable_source(struct intel_dp *intel_dp, 1986 const struct intel_crtc_state *crtc_state) 1987 { 1988 struct intel_display *display = to_intel_display(intel_dp); 1989 enum transcoder cpu_transcoder = intel_dp->psr.transcoder; 1990 u32 mask = 0; 1991 1992 /* 1993 * Only HSW and BDW have PSR AUX registers that need to be setup. 1994 * SKL+ use hardcoded values PSR AUX transactions 1995 */ 1996 if (DISPLAY_VER(display) < 9) 1997 hsw_psr_setup_aux(intel_dp); 1998 1999 /* 2000 * Per Spec: Avoid continuous PSR exit by masking MEMUP and HPD also 2001 * mask LPSP to avoid dependency on other drivers that might block 2002 * runtime_pm besides preventing other hw tracking issues now we 2003 * can rely on frontbuffer tracking. 2004 * 2005 * From bspec prior LunarLake: 2006 * Only PSR_MASK[Mask FBC modify] and PSR_MASK[Mask Hotplug] are used in 2007 * panel replay mode. 2008 * 2009 * From bspec beyod LunarLake: 2010 * Panel Replay on DP: No bits are applicable 2011 * Panel Replay on eDP: All bits are applicable 2012 */ 2013 if (DISPLAY_VER(display) < 20 || intel_dp_is_edp(intel_dp)) 2014 mask = EDP_PSR_DEBUG_MASK_HPD; 2015 2016 if (intel_dp_is_edp(intel_dp)) { 2017 mask |= EDP_PSR_DEBUG_MASK_MEMUP; 2018 2019 /* 2020 * For some unknown reason on HSW non-ULT (or at least on 2021 * Dell Latitude E6540) external displays start to flicker 2022 * when PSR is enabled on the eDP. SR/PC6 residency is much 2023 * higher than should be possible with an external display. 2024 * As a workaround leave LPSP unmasked to prevent PSR entry 2025 * when external displays are active. 2026 */ 2027 if (DISPLAY_VER(display) >= 8 || display->platform.haswell_ult) 2028 mask |= EDP_PSR_DEBUG_MASK_LPSP; 2029 2030 if (DISPLAY_VER(display) < 20) 2031 mask |= EDP_PSR_DEBUG_MASK_MAX_SLEEP; 2032 2033 /* 2034 * No separate pipe reg write mask on hsw/bdw, so have to unmask all 2035 * registers in order to keep the CURSURFLIVE tricks working :( 2036 */ 2037 if (IS_DISPLAY_VER(display, 9, 10)) 2038 mask |= EDP_PSR_DEBUG_MASK_DISP_REG_WRITE; 2039 2040 /* allow PSR with sprite enabled */ 2041 if (display->platform.haswell) 2042 mask |= EDP_PSR_DEBUG_MASK_SPRITE_ENABLE; 2043 } 2044 2045 intel_de_write(display, psr_debug_reg(display, cpu_transcoder), mask); 2046 2047 psr_irq_control(intel_dp); 2048 2049 /* 2050 * TODO: if future platforms supports DC3CO in more than one 2051 * transcoder, EXITLINE will need to be unset when disabling PSR 2052 */ 2053 if (intel_dp->psr.dc3co_exitline) 2054 intel_de_rmw(display, 2055 TRANS_EXITLINE(display, cpu_transcoder), 2056 EXITLINE_MASK, 2057 intel_dp->psr.dc3co_exitline << EXITLINE_SHIFT | EXITLINE_ENABLE); 2058 2059 if (HAS_PSR_HW_TRACKING(display) && HAS_PSR2_SEL_FETCH(display)) 2060 intel_de_rmw(display, CHICKEN_PAR1_1, IGNORE_PSR2_HW_TRACKING, 2061 intel_dp->psr.psr2_sel_fetch_enabled ? 2062 IGNORE_PSR2_HW_TRACKING : 0); 2063 2064 /* 2065 * Wa_16013835468 2066 * Wa_14015648006 2067 */ 2068 wm_optimization_wa(intel_dp, crtc_state); 2069 2070 if (intel_dp->psr.sel_update_enabled) { 2071 if (DISPLAY_VER(display) == 9) 2072 intel_de_rmw(display, CHICKEN_TRANS(display, cpu_transcoder), 0, 2073 PSR2_VSC_ENABLE_PROG_HEADER | 2074 PSR2_ADD_VERTICAL_LINE_COUNT); 2075 2076 /* 2077 * Wa_16014451276:adlp,mtl[a0,b0] 2078 * All supported adlp panels have 1-based X granularity, this may 2079 * cause issues if non-supported panels are used. 2080 */ 2081 if (!intel_dp->psr.panel_replay_enabled && 2082 (IS_DISPLAY_VERx100_STEP(display, 1400, STEP_A0, STEP_B0) || 2083 display->platform.alderlake_p)) 2084 intel_de_rmw(display, CHICKEN_TRANS(display, cpu_transcoder), 2085 0, ADLP_1_BASED_X_GRANULARITY); 2086 2087 /* Wa_16012604467:adlp,mtl[a0,b0] */ 2088 if (!intel_dp->psr.panel_replay_enabled && 2089 IS_DISPLAY_VERx100_STEP(display, 1400, STEP_A0, STEP_B0)) 2090 intel_de_rmw(display, 2091 MTL_CLKGATE_DIS_TRANS(display, cpu_transcoder), 2092 0, 2093 MTL_CLKGATE_DIS_TRANS_DMASC_GATING_DIS); 2094 else if (display->platform.alderlake_p) 2095 intel_de_rmw(display, CLKGATE_DIS_MISC, 0, 2096 CLKGATE_DIS_MISC_DMASC_GATING_DIS); 2097 } 2098 2099 /* Wa_16025596647 */ 2100 if ((DISPLAY_VER(display) == 20 || 2101 IS_DISPLAY_VERx100_STEP(display, 3000, STEP_A0, STEP_B0)) && 2102 !intel_dp->psr.panel_replay_enabled) 2103 intel_dmc_block_pkgc(display, intel_dp->psr.pipe, true); 2104 2105 intel_alpm_configure(intel_dp, crtc_state); 2106 } 2107 2108 static bool psr_interrupt_error_check(struct intel_dp *intel_dp) 2109 { 2110 struct intel_display *display = to_intel_display(intel_dp); 2111 enum transcoder cpu_transcoder = intel_dp->psr.transcoder; 2112 u32 val; 2113 2114 if (intel_dp->psr.panel_replay_enabled) 2115 goto no_err; 2116 2117 /* 2118 * If a PSR error happened and the driver is reloaded, the EDP_PSR_IIR 2119 * will still keep the error set even after the reset done in the 2120 * irq_preinstall and irq_uninstall hooks. 2121 * And enabling in this situation cause the screen to freeze in the 2122 * first time that PSR HW tries to activate so lets keep PSR disabled 2123 * to avoid any rendering problems. 2124 */ 2125 val = intel_de_read(display, psr_iir_reg(display, cpu_transcoder)); 2126 val &= psr_irq_psr_error_bit_get(intel_dp); 2127 if (val) { 2128 intel_dp->psr.sink_not_reliable = true; 2129 drm_dbg_kms(display->drm, 2130 "PSR interruption error set, not enabling PSR\n"); 2131 return false; 2132 } 2133 2134 no_err: 2135 return true; 2136 } 2137 2138 static void intel_psr_enable_locked(struct intel_dp *intel_dp, 2139 const struct intel_crtc_state *crtc_state) 2140 { 2141 struct intel_display *display = to_intel_display(intel_dp); 2142 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 2143 u32 val; 2144 2145 drm_WARN_ON(display->drm, intel_dp->psr.enabled); 2146 2147 intel_dp->psr.sel_update_enabled = crtc_state->has_sel_update; 2148 intel_dp->psr.panel_replay_enabled = crtc_state->has_panel_replay; 2149 intel_dp->psr.busy_frontbuffer_bits = 0; 2150 intel_dp->psr.pipe = to_intel_crtc(crtc_state->uapi.crtc)->pipe; 2151 intel_dp->psr.transcoder = crtc_state->cpu_transcoder; 2152 /* DC5/DC6 requires at least 6 idle frames */ 2153 val = usecs_to_jiffies(intel_get_frame_time_us(crtc_state) * 6); 2154 intel_dp->psr.dc3co_exit_delay = val; 2155 intel_dp->psr.dc3co_exitline = crtc_state->dc3co_exitline; 2156 intel_dp->psr.psr2_sel_fetch_enabled = crtc_state->enable_psr2_sel_fetch; 2157 intel_dp->psr.su_region_et_enabled = crtc_state->enable_psr2_su_region_et; 2158 intel_dp->psr.psr2_sel_fetch_cff_enabled = false; 2159 intel_dp->psr.req_psr2_sdp_prior_scanline = 2160 crtc_state->req_psr2_sdp_prior_scanline; 2161 intel_dp->psr.active_non_psr_pipes = crtc_state->active_non_psr_pipes; 2162 intel_dp->psr.pkg_c_latency_used = crtc_state->pkg_c_latency_used; 2163 intel_dp->psr.io_wake_lines = crtc_state->alpm_state.io_wake_lines; 2164 intel_dp->psr.fast_wake_lines = crtc_state->alpm_state.fast_wake_lines; 2165 2166 if (!psr_interrupt_error_check(intel_dp)) 2167 return; 2168 2169 if (intel_dp->psr.panel_replay_enabled) 2170 drm_dbg_kms(display->drm, "Enabling Panel Replay\n"); 2171 else 2172 drm_dbg_kms(display->drm, "Enabling PSR%s\n", 2173 intel_dp->psr.sel_update_enabled ? "2" : "1"); 2174 2175 /* 2176 * Enabling sink PSR/Panel Replay here only for PSR. Panel Replay enable 2177 * bit is already written at this point. Sink ALPM is enabled here for 2178 * PSR and Panel Replay. See 2179 * intel_psr_panel_replay_enable_sink. Modifiers/options: 2180 * - Selective Update 2181 * - Region Early Transport 2182 * - Selective Update Region Scanline Capture 2183 * - VSC_SDP_CRC 2184 * - HPD on different Errors 2185 * - CRC verification 2186 * are written for PSR and Panel Replay here. 2187 */ 2188 intel_psr_enable_sink(intel_dp, crtc_state); 2189 2190 if (intel_dp_is_edp(intel_dp)) 2191 intel_snps_phy_update_psr_power_state(&dig_port->base, true); 2192 2193 intel_psr_enable_source(intel_dp, crtc_state); 2194 intel_dp->psr.enabled = true; 2195 intel_dp->psr.pause_counter = 0; 2196 2197 /* 2198 * Link_ok is sticky and set here on PSR enable. We can assume link 2199 * training is complete as we never continue to PSR enable with 2200 * untrained link. Link_ok is kept as set until first short pulse 2201 * interrupt. This is targeted to workaround panels stating bad link 2202 * after PSR is enabled. 2203 */ 2204 intel_dp->psr.link_ok = true; 2205 2206 intel_psr_activate(intel_dp); 2207 } 2208 2209 static void intel_psr_exit(struct intel_dp *intel_dp) 2210 { 2211 struct intel_display *display = to_intel_display(intel_dp); 2212 enum transcoder cpu_transcoder = intel_dp->psr.transcoder; 2213 u32 val; 2214 2215 if (!intel_dp->psr.active) { 2216 if (transcoder_has_psr2(display, cpu_transcoder)) { 2217 val = intel_de_read(display, 2218 EDP_PSR2_CTL(display, cpu_transcoder)); 2219 drm_WARN_ON(display->drm, val & EDP_PSR2_ENABLE); 2220 } 2221 2222 val = intel_de_read(display, 2223 psr_ctl_reg(display, cpu_transcoder)); 2224 drm_WARN_ON(display->drm, val & EDP_PSR_ENABLE); 2225 2226 return; 2227 } 2228 2229 if (intel_dp->psr.panel_replay_enabled) { 2230 intel_de_rmw(display, TRANS_DP2_CTL(intel_dp->psr.transcoder), 2231 TRANS_DP2_PANEL_REPLAY_ENABLE, 0); 2232 } else if (intel_dp->psr.sel_update_enabled) { 2233 tgl_disallow_dc3co_on_psr2_exit(intel_dp); 2234 2235 val = intel_de_rmw(display, 2236 EDP_PSR2_CTL(display, cpu_transcoder), 2237 EDP_PSR2_ENABLE, 0); 2238 2239 drm_WARN_ON(display->drm, !(val & EDP_PSR2_ENABLE)); 2240 } else { 2241 if ((DISPLAY_VER(display) == 20 || 2242 IS_DISPLAY_VERx100_STEP(display, 3000, STEP_A0, STEP_B0)) && 2243 intel_dp->psr.pkg_c_latency_used) 2244 intel_dmc_start_pkgc_exit_at_start_of_undelayed_vblank(display, 2245 intel_dp->psr.pipe, 2246 false); 2247 2248 val = intel_de_rmw(display, 2249 psr_ctl_reg(display, cpu_transcoder), 2250 EDP_PSR_ENABLE, 0); 2251 2252 drm_WARN_ON(display->drm, !(val & EDP_PSR_ENABLE)); 2253 } 2254 intel_dp->psr.active = false; 2255 } 2256 2257 static void intel_psr_wait_exit_locked(struct intel_dp *intel_dp) 2258 { 2259 struct intel_display *display = to_intel_display(intel_dp); 2260 enum transcoder cpu_transcoder = intel_dp->psr.transcoder; 2261 i915_reg_t psr_status; 2262 u32 psr_status_mask; 2263 2264 if (intel_dp_is_edp(intel_dp) && (intel_dp->psr.sel_update_enabled || 2265 intel_dp->psr.panel_replay_enabled)) { 2266 psr_status = EDP_PSR2_STATUS(display, cpu_transcoder); 2267 psr_status_mask = EDP_PSR2_STATUS_STATE_MASK; 2268 } else { 2269 psr_status = psr_status_reg(display, cpu_transcoder); 2270 psr_status_mask = EDP_PSR_STATUS_STATE_MASK; 2271 } 2272 2273 /* Wait till PSR is idle */ 2274 if (intel_de_wait_for_clear_ms(display, psr_status, 2275 psr_status_mask, 2000)) 2276 drm_err(display->drm, "Timed out waiting PSR idle state\n"); 2277 } 2278 2279 static void intel_psr_disable_locked(struct intel_dp *intel_dp) 2280 { 2281 struct intel_display *display = to_intel_display(intel_dp); 2282 enum transcoder cpu_transcoder = intel_dp->psr.transcoder; 2283 2284 lockdep_assert_held(&intel_dp->psr.lock); 2285 2286 if (!intel_dp->psr.enabled) 2287 return; 2288 2289 if (intel_dp->psr.panel_replay_enabled) 2290 drm_dbg_kms(display->drm, "Disabling Panel Replay\n"); 2291 else 2292 drm_dbg_kms(display->drm, "Disabling PSR%s\n", 2293 intel_dp->psr.sel_update_enabled ? "2" : "1"); 2294 2295 intel_psr_exit(intel_dp); 2296 intel_psr_wait_exit_locked(intel_dp); 2297 2298 /* 2299 * Wa_16013835468 2300 * Wa_14015648006 2301 */ 2302 if (DISPLAY_VER(display) >= 11) 2303 intel_de_rmw(display, GEN8_CHICKEN_DCPR_1, 2304 LATENCY_REPORTING_REMOVED(intel_dp->psr.pipe), 0); 2305 2306 if (intel_dp->psr.sel_update_enabled) { 2307 /* Wa_16012604467:adlp,mtl[a0,b0] */ 2308 if (!intel_dp->psr.panel_replay_enabled && 2309 IS_DISPLAY_VERx100_STEP(display, 1400, STEP_A0, STEP_B0)) 2310 intel_de_rmw(display, 2311 MTL_CLKGATE_DIS_TRANS(display, cpu_transcoder), 2312 MTL_CLKGATE_DIS_TRANS_DMASC_GATING_DIS, 0); 2313 else if (display->platform.alderlake_p) 2314 intel_de_rmw(display, CLKGATE_DIS_MISC, 2315 CLKGATE_DIS_MISC_DMASC_GATING_DIS, 0); 2316 } 2317 2318 if (intel_dp_is_edp(intel_dp)) 2319 intel_snps_phy_update_psr_power_state(&dp_to_dig_port(intel_dp)->base, false); 2320 2321 if (intel_dp->psr.panel_replay_enabled && intel_dp_is_edp(intel_dp)) 2322 intel_alpm_disable(intel_dp); 2323 2324 /* Disable PSR on Sink */ 2325 if (!intel_dp->psr.panel_replay_enabled) { 2326 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, 0); 2327 2328 if (intel_dp->psr.sel_update_enabled) 2329 drm_dp_dpcd_writeb(&intel_dp->aux, 2330 DP_RECEIVER_ALPM_CONFIG, 0); 2331 } 2332 2333 /* Wa_16025596647 */ 2334 if ((DISPLAY_VER(display) == 20 || 2335 IS_DISPLAY_VERx100_STEP(display, 3000, STEP_A0, STEP_B0)) && 2336 !intel_dp->psr.panel_replay_enabled) 2337 intel_dmc_block_pkgc(display, intel_dp->psr.pipe, false); 2338 2339 intel_dp->psr.enabled = false; 2340 intel_dp->psr.panel_replay_enabled = false; 2341 intel_dp->psr.sel_update_enabled = false; 2342 intel_dp->psr.psr2_sel_fetch_enabled = false; 2343 intel_dp->psr.su_region_et_enabled = false; 2344 intel_dp->psr.psr2_sel_fetch_cff_enabled = false; 2345 intel_dp->psr.active_non_psr_pipes = 0; 2346 intel_dp->psr.pkg_c_latency_used = 0; 2347 } 2348 2349 /** 2350 * intel_psr_disable - Disable PSR 2351 * @intel_dp: Intel DP 2352 * @old_crtc_state: old CRTC state 2353 * 2354 * This function needs to be called before disabling pipe. 2355 */ 2356 void intel_psr_disable(struct intel_dp *intel_dp, 2357 const struct intel_crtc_state *old_crtc_state) 2358 { 2359 struct intel_display *display = to_intel_display(intel_dp); 2360 2361 if (!old_crtc_state->has_psr) 2362 return; 2363 2364 if (drm_WARN_ON(display->drm, !CAN_PSR(intel_dp) && 2365 !CAN_PANEL_REPLAY(intel_dp))) 2366 return; 2367 2368 mutex_lock(&intel_dp->psr.lock); 2369 2370 intel_psr_disable_locked(intel_dp); 2371 2372 intel_dp->psr.link_ok = false; 2373 2374 mutex_unlock(&intel_dp->psr.lock); 2375 cancel_work_sync(&intel_dp->psr.work); 2376 cancel_delayed_work_sync(&intel_dp->psr.dc3co_work); 2377 } 2378 2379 /** 2380 * intel_psr_pause - Pause PSR 2381 * @intel_dp: Intel DP 2382 * 2383 * This function need to be called after enabling psr. 2384 */ 2385 void intel_psr_pause(struct intel_dp *intel_dp) 2386 { 2387 struct intel_psr *psr = &intel_dp->psr; 2388 2389 if (!CAN_PSR(intel_dp) && !CAN_PANEL_REPLAY(intel_dp)) 2390 return; 2391 2392 mutex_lock(&psr->lock); 2393 2394 if (!psr->enabled) { 2395 mutex_unlock(&psr->lock); 2396 return; 2397 } 2398 2399 if (intel_dp->psr.pause_counter++ == 0) { 2400 intel_psr_exit(intel_dp); 2401 intel_psr_wait_exit_locked(intel_dp); 2402 } 2403 2404 mutex_unlock(&psr->lock); 2405 2406 cancel_work_sync(&psr->work); 2407 cancel_delayed_work_sync(&psr->dc3co_work); 2408 } 2409 2410 /** 2411 * intel_psr_resume - Resume PSR 2412 * @intel_dp: Intel DP 2413 * 2414 * This function need to be called after pausing psr. 2415 */ 2416 void intel_psr_resume(struct intel_dp *intel_dp) 2417 { 2418 struct intel_display *display = to_intel_display(intel_dp); 2419 struct intel_psr *psr = &intel_dp->psr; 2420 2421 if (!CAN_PSR(intel_dp) && !CAN_PANEL_REPLAY(intel_dp)) 2422 return; 2423 2424 mutex_lock(&psr->lock); 2425 2426 if (!psr->enabled) 2427 goto out; 2428 2429 if (!psr->pause_counter) { 2430 drm_warn(display->drm, "Unbalanced PSR pause/resume!\n"); 2431 goto out; 2432 } 2433 2434 if (--intel_dp->psr.pause_counter == 0) 2435 intel_psr_activate(intel_dp); 2436 2437 out: 2438 mutex_unlock(&psr->lock); 2439 } 2440 2441 /** 2442 * intel_psr_needs_vblank_notification - Check if PSR need vblank enable/disable 2443 * notification. 2444 * @crtc_state: CRTC status 2445 * 2446 * We need to block DC6 entry in case of Panel Replay as enabling VBI doesn't 2447 * prevent it in case of Panel Replay. Panel Replay switches main link off on 2448 * DC entry. This means vblank interrupts are not fired and is a problem if 2449 * user-space is polling for vblank events. Also Wa_16025596647 needs 2450 * information when vblank is enabled/disabled. 2451 */ 2452 bool intel_psr_needs_vblank_notification(const struct intel_crtc_state *crtc_state) 2453 { 2454 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2455 struct intel_display *display = to_intel_display(crtc_state); 2456 struct intel_encoder *encoder; 2457 2458 for_each_encoder_on_crtc(crtc->base.dev, &crtc->base, encoder) { 2459 struct intel_dp *intel_dp; 2460 2461 if (!intel_encoder_is_dp(encoder)) 2462 continue; 2463 2464 intel_dp = enc_to_intel_dp(encoder); 2465 2466 if (!intel_dp_is_edp(intel_dp)) 2467 continue; 2468 2469 if (CAN_PANEL_REPLAY(intel_dp)) 2470 return true; 2471 2472 if ((DISPLAY_VER(display) == 20 || 2473 IS_DISPLAY_VERx100_STEP(display, 3000, STEP_A0, STEP_B0)) && 2474 CAN_PSR(intel_dp)) 2475 return true; 2476 } 2477 2478 return false; 2479 } 2480 2481 /** 2482 * intel_psr_trigger_frame_change_event - Trigger "Frame Change" event 2483 * @dsb: DSB context 2484 * @state: the atomic state 2485 * @crtc: the CRTC 2486 * 2487 * Generate PSR "Frame Change" event. 2488 */ 2489 void intel_psr_trigger_frame_change_event(struct intel_dsb *dsb, 2490 struct intel_atomic_state *state, 2491 struct intel_crtc *crtc) 2492 { 2493 const struct intel_crtc_state *crtc_state = 2494 intel_pre_commit_crtc_state(state, crtc); 2495 struct intel_display *display = to_intel_display(crtc); 2496 2497 if (crtc_state->has_psr) 2498 intel_de_write_dsb(display, dsb, 2499 CURSURFLIVE(display, crtc->pipe), 0); 2500 } 2501 2502 /** 2503 * intel_psr_min_set_context_latency - Minimum 'set context latency' lines needed by PSR 2504 * @crtc_state: the crtc state 2505 * 2506 * Return minimum SCL lines/delay needed by PSR. 2507 */ 2508 int intel_psr_min_set_context_latency(const struct intel_crtc_state *crtc_state) 2509 { 2510 2511 return _intel_psr_min_set_context_latency(crtc_state, 2512 crtc_state->has_panel_replay, 2513 crtc_state->has_sel_update); 2514 } 2515 2516 static u32 man_trk_ctl_enable_bit_get(struct intel_display *display) 2517 { 2518 return display->platform.alderlake_p || DISPLAY_VER(display) >= 14 ? 0 : 2519 PSR2_MAN_TRK_CTL_ENABLE; 2520 } 2521 2522 static u32 man_trk_ctl_single_full_frame_bit_get(struct intel_display *display) 2523 { 2524 return display->platform.alderlake_p || DISPLAY_VER(display) >= 14 ? 2525 ADLP_PSR2_MAN_TRK_CTL_SF_SINGLE_FULL_FRAME : 2526 PSR2_MAN_TRK_CTL_SF_SINGLE_FULL_FRAME; 2527 } 2528 2529 static u32 man_trk_ctl_partial_frame_bit_get(struct intel_display *display) 2530 { 2531 return display->platform.alderlake_p || DISPLAY_VER(display) >= 14 ? 2532 ADLP_PSR2_MAN_TRK_CTL_SF_PARTIAL_FRAME_UPDATE : 2533 PSR2_MAN_TRK_CTL_SF_PARTIAL_FRAME_UPDATE; 2534 } 2535 2536 static u32 man_trk_ctl_continuos_full_frame(struct intel_display *display) 2537 { 2538 return display->platform.alderlake_p || DISPLAY_VER(display) >= 14 ? 2539 ADLP_PSR2_MAN_TRK_CTL_SF_CONTINUOS_FULL_FRAME : 2540 PSR2_MAN_TRK_CTL_SF_CONTINUOS_FULL_FRAME; 2541 } 2542 2543 static void intel_psr_force_update(struct intel_dp *intel_dp) 2544 { 2545 struct intel_display *display = to_intel_display(intel_dp); 2546 2547 /* 2548 * Display WA #0884: skl+ 2549 * This documented WA for bxt can be safely applied 2550 * broadly so we can force HW tracking to exit PSR 2551 * instead of disabling and re-enabling. 2552 * Workaround tells us to write 0 to CUR_SURFLIVE_A, 2553 * but it makes more sense write to the current active 2554 * pipe. 2555 * 2556 * This workaround do not exist for platforms with display 10 or newer 2557 * but testing proved that it works for up display 13, for newer 2558 * than that testing will be needed. 2559 */ 2560 intel_de_write(display, CURSURFLIVE(display, intel_dp->psr.pipe), 0); 2561 } 2562 2563 void intel_psr2_program_trans_man_trk_ctl(struct intel_dsb *dsb, 2564 const struct intel_crtc_state *crtc_state) 2565 { 2566 struct intel_display *display = to_intel_display(crtc_state); 2567 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2568 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 2569 struct intel_encoder *encoder; 2570 2571 if (!crtc_state->enable_psr2_sel_fetch) 2572 return; 2573 2574 for_each_intel_encoder_mask_with_psr(display->drm, encoder, 2575 crtc_state->uapi.encoder_mask) { 2576 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2577 2578 if (!dsb) 2579 lockdep_assert_held(&intel_dp->psr.lock); 2580 2581 if (DISPLAY_VER(display) < 20 && intel_dp->psr.psr2_sel_fetch_cff_enabled) 2582 return; 2583 break; 2584 } 2585 2586 intel_de_write_dsb(display, dsb, 2587 PSR2_MAN_TRK_CTL(display, cpu_transcoder), 2588 crtc_state->psr2_man_track_ctl); 2589 2590 if (!crtc_state->enable_psr2_su_region_et) 2591 return; 2592 2593 intel_de_write_dsb(display, dsb, PIPE_SRCSZ_ERLY_TPT(crtc->pipe), 2594 crtc_state->pipe_srcsz_early_tpt); 2595 } 2596 2597 static void psr2_man_trk_ctl_calc(struct intel_crtc_state *crtc_state, 2598 bool full_update) 2599 { 2600 struct intel_display *display = to_intel_display(crtc_state); 2601 u32 val = man_trk_ctl_enable_bit_get(display); 2602 2603 /* SF partial frame enable has to be set even on full update */ 2604 val |= man_trk_ctl_partial_frame_bit_get(display); 2605 2606 if (full_update) { 2607 val |= man_trk_ctl_continuos_full_frame(display); 2608 goto exit; 2609 } 2610 2611 if (crtc_state->psr2_su_area.y1 == -1) 2612 goto exit; 2613 2614 if (display->platform.alderlake_p || DISPLAY_VER(display) >= 14) { 2615 val |= ADLP_PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR(crtc_state->psr2_su_area.y1); 2616 val |= ADLP_PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR(crtc_state->psr2_su_area.y2 - 1); 2617 } else { 2618 drm_WARN_ON(crtc_state->uapi.crtc->dev, 2619 crtc_state->psr2_su_area.y1 % 4 || 2620 crtc_state->psr2_su_area.y2 % 4); 2621 2622 val |= PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR( 2623 crtc_state->psr2_su_area.y1 / 4 + 1); 2624 val |= PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR( 2625 crtc_state->psr2_su_area.y2 / 4 + 1); 2626 } 2627 exit: 2628 crtc_state->psr2_man_track_ctl = val; 2629 } 2630 2631 static u32 psr2_pipe_srcsz_early_tpt_calc(struct intel_crtc_state *crtc_state, 2632 bool full_update) 2633 { 2634 int width, height; 2635 2636 if (!crtc_state->enable_psr2_su_region_et || full_update) 2637 return 0; 2638 2639 width = drm_rect_width(&crtc_state->psr2_su_area); 2640 height = drm_rect_height(&crtc_state->psr2_su_area); 2641 2642 return PIPESRC_WIDTH(width - 1) | PIPESRC_HEIGHT(height - 1); 2643 } 2644 2645 static void clip_area_update(struct drm_rect *overlap_damage_area, 2646 struct drm_rect *damage_area, 2647 struct drm_rect *pipe_src) 2648 { 2649 if (!drm_rect_intersect(damage_area, pipe_src)) 2650 return; 2651 2652 if (overlap_damage_area->y1 == -1) { 2653 overlap_damage_area->y1 = damage_area->y1; 2654 overlap_damage_area->y2 = damage_area->y2; 2655 return; 2656 } 2657 2658 if (damage_area->y1 < overlap_damage_area->y1) 2659 overlap_damage_area->y1 = damage_area->y1; 2660 2661 if (damage_area->y2 > overlap_damage_area->y2) 2662 overlap_damage_area->y2 = damage_area->y2; 2663 } 2664 2665 static void intel_psr2_sel_fetch_pipe_alignment(struct intel_crtc_state *crtc_state) 2666 { 2667 struct intel_display *display = to_intel_display(crtc_state); 2668 const struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config; 2669 u16 y_alignment; 2670 2671 /* ADLP aligns the SU region to vdsc slice height in case dsc is enabled */ 2672 if (crtc_state->dsc.compression_enable && 2673 (display->platform.alderlake_p || DISPLAY_VER(display) >= 14)) 2674 y_alignment = vdsc_cfg->slice_height; 2675 else 2676 y_alignment = crtc_state->su_y_granularity; 2677 2678 crtc_state->psr2_su_area.y1 -= crtc_state->psr2_su_area.y1 % y_alignment; 2679 if (crtc_state->psr2_su_area.y2 % y_alignment) 2680 crtc_state->psr2_su_area.y2 = ((crtc_state->psr2_su_area.y2 / 2681 y_alignment) + 1) * y_alignment; 2682 } 2683 2684 /* 2685 * When early transport is in use we need to extend SU area to cover 2686 * cursor fully when cursor is in SU area. 2687 */ 2688 static void 2689 intel_psr2_sel_fetch_et_alignment(struct intel_atomic_state *state, 2690 struct intel_crtc *crtc, 2691 bool *cursor_in_su_area) 2692 { 2693 struct intel_crtc_state *crtc_state = intel_atomic_get_new_crtc_state(state, crtc); 2694 struct intel_plane_state *new_plane_state; 2695 struct intel_plane *plane; 2696 int i; 2697 2698 if (!crtc_state->enable_psr2_su_region_et) 2699 return; 2700 2701 for_each_new_intel_plane_in_state(state, plane, new_plane_state, i) { 2702 struct drm_rect inter; 2703 2704 if (new_plane_state->uapi.crtc != crtc_state->uapi.crtc) 2705 continue; 2706 2707 if (plane->id != PLANE_CURSOR) 2708 continue; 2709 2710 if (!new_plane_state->uapi.visible) 2711 continue; 2712 2713 inter = crtc_state->psr2_su_area; 2714 if (!drm_rect_intersect(&inter, &new_plane_state->uapi.dst)) 2715 continue; 2716 2717 clip_area_update(&crtc_state->psr2_su_area, &new_plane_state->uapi.dst, 2718 &crtc_state->pipe_src); 2719 *cursor_in_su_area = true; 2720 } 2721 } 2722 2723 /* 2724 * TODO: Not clear how to handle planes with negative position, 2725 * also planes are not updated if they have a negative X 2726 * position so for now doing a full update in this cases 2727 * 2728 * Plane scaling and rotation is not supported by selective fetch and both 2729 * properties can change without a modeset, so need to be check at every 2730 * atomic commit. 2731 */ 2732 static bool psr2_sel_fetch_plane_state_supported(const struct intel_plane_state *plane_state) 2733 { 2734 if (plane_state->uapi.dst.y1 < 0 || 2735 plane_state->uapi.dst.x1 < 0 || 2736 plane_state->scaler_id >= 0 || 2737 plane_state->uapi.rotation != DRM_MODE_ROTATE_0) 2738 return false; 2739 2740 return true; 2741 } 2742 2743 /* 2744 * Check for pipe properties that is not supported by selective fetch. 2745 * 2746 * TODO: pipe scaling causes a modeset but skl_update_scaler_crtc() is executed 2747 * after intel_psr_compute_config(), so for now keeping PSR2 selective fetch 2748 * enabled and going to the full update path. 2749 */ 2750 static bool psr2_sel_fetch_pipe_state_supported(const struct intel_crtc_state *crtc_state) 2751 { 2752 if (crtc_state->scaler_state.scaler_id >= 0) 2753 return false; 2754 2755 return true; 2756 } 2757 2758 /* Wa 14019834836 */ 2759 static void intel_psr_apply_pr_link_on_su_wa(struct intel_crtc_state *crtc_state) 2760 { 2761 struct intel_display *display = to_intel_display(crtc_state); 2762 struct intel_encoder *encoder; 2763 int hactive_limit; 2764 2765 if (crtc_state->psr2_su_area.y1 != 0 || 2766 crtc_state->psr2_su_area.y2 != 0) 2767 return; 2768 2769 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) 2770 hactive_limit = intel_dp_is_uhbr(crtc_state) ? 1230 : 546; 2771 else 2772 hactive_limit = intel_dp_is_uhbr(crtc_state) ? 615 : 273; 2773 2774 if (crtc_state->hw.adjusted_mode.hdisplay < hactive_limit) 2775 return; 2776 2777 for_each_intel_encoder_mask_with_psr(display->drm, encoder, 2778 crtc_state->uapi.encoder_mask) { 2779 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2780 2781 if (!intel_dp_is_edp(intel_dp) && 2782 intel_dp->psr.panel_replay_enabled && 2783 intel_dp->psr.sel_update_enabled) { 2784 crtc_state->psr2_su_area.y2++; 2785 return; 2786 } 2787 } 2788 } 2789 2790 static void 2791 intel_psr_apply_su_area_workarounds(struct intel_crtc_state *crtc_state) 2792 { 2793 struct intel_display *display = to_intel_display(crtc_state); 2794 2795 /* Wa_14014971492 */ 2796 if (!crtc_state->has_panel_replay && 2797 ((IS_DISPLAY_VERx100_STEP(display, 1400, STEP_A0, STEP_B0) || 2798 display->platform.alderlake_p || display->platform.tigerlake)) && 2799 crtc_state->splitter.enable) 2800 crtc_state->psr2_su_area.y1 = 0; 2801 2802 /* Wa 14019834836 */ 2803 if (DISPLAY_VER(display) == 30) 2804 intel_psr_apply_pr_link_on_su_wa(crtc_state); 2805 } 2806 2807 int intel_psr2_sel_fetch_update(struct intel_atomic_state *state, 2808 struct intel_crtc *crtc) 2809 { 2810 struct intel_display *display = to_intel_display(state); 2811 struct intel_crtc_state *crtc_state = intel_atomic_get_new_crtc_state(state, crtc); 2812 struct intel_plane_state *new_plane_state, *old_plane_state; 2813 struct intel_plane *plane; 2814 bool full_update = false, cursor_in_su_area = false; 2815 int i, ret; 2816 2817 if (!crtc_state->enable_psr2_sel_fetch) 2818 return 0; 2819 2820 if (!psr2_sel_fetch_pipe_state_supported(crtc_state)) { 2821 full_update = true; 2822 goto skip_sel_fetch_set_loop; 2823 } 2824 2825 crtc_state->psr2_su_area.x1 = 0; 2826 crtc_state->psr2_su_area.y1 = -1; 2827 crtc_state->psr2_su_area.x2 = drm_rect_width(&crtc_state->pipe_src); 2828 crtc_state->psr2_su_area.y2 = -1; 2829 2830 /* 2831 * Calculate minimal selective fetch area of each plane and calculate 2832 * the pipe damaged area. 2833 * In the next loop the plane selective fetch area will actually be set 2834 * using whole pipe damaged area. 2835 */ 2836 for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state, 2837 new_plane_state, i) { 2838 struct drm_rect src, damaged_area = { .x1 = 0, .y1 = -1, 2839 .x2 = INT_MAX }; 2840 2841 if (new_plane_state->uapi.crtc != crtc_state->uapi.crtc) 2842 continue; 2843 2844 if (!new_plane_state->uapi.visible && 2845 !old_plane_state->uapi.visible) 2846 continue; 2847 2848 if (!psr2_sel_fetch_plane_state_supported(new_plane_state)) { 2849 full_update = true; 2850 break; 2851 } 2852 2853 /* 2854 * If visibility or plane moved, mark the whole plane area as 2855 * damaged as it needs to be complete redraw in the new and old 2856 * position. 2857 */ 2858 if (new_plane_state->uapi.visible != old_plane_state->uapi.visible || 2859 !drm_rect_equals(&new_plane_state->uapi.dst, 2860 &old_plane_state->uapi.dst)) { 2861 if (old_plane_state->uapi.visible) { 2862 damaged_area.y1 = old_plane_state->uapi.dst.y1; 2863 damaged_area.y2 = old_plane_state->uapi.dst.y2; 2864 clip_area_update(&crtc_state->psr2_su_area, &damaged_area, 2865 &crtc_state->pipe_src); 2866 } 2867 2868 if (new_plane_state->uapi.visible) { 2869 damaged_area.y1 = new_plane_state->uapi.dst.y1; 2870 damaged_area.y2 = new_plane_state->uapi.dst.y2; 2871 clip_area_update(&crtc_state->psr2_su_area, &damaged_area, 2872 &crtc_state->pipe_src); 2873 } 2874 continue; 2875 } else if (new_plane_state->uapi.alpha != old_plane_state->uapi.alpha) { 2876 /* If alpha changed mark the whole plane area as damaged */ 2877 damaged_area.y1 = new_plane_state->uapi.dst.y1; 2878 damaged_area.y2 = new_plane_state->uapi.dst.y2; 2879 clip_area_update(&crtc_state->psr2_su_area, &damaged_area, 2880 &crtc_state->pipe_src); 2881 continue; 2882 } 2883 2884 src = drm_plane_state_src(&new_plane_state->uapi); 2885 drm_rect_fp_to_int(&src, &src); 2886 2887 if (!drm_atomic_helper_damage_merged(&old_plane_state->uapi, 2888 &new_plane_state->uapi, &damaged_area)) 2889 continue; 2890 2891 damaged_area.y1 += new_plane_state->uapi.dst.y1 - src.y1; 2892 damaged_area.y2 += new_plane_state->uapi.dst.y1 - src.y1; 2893 damaged_area.x1 += new_plane_state->uapi.dst.x1 - src.x1; 2894 damaged_area.x2 += new_plane_state->uapi.dst.x1 - src.x1; 2895 2896 clip_area_update(&crtc_state->psr2_su_area, &damaged_area, &crtc_state->pipe_src); 2897 } 2898 2899 /* 2900 * TODO: For now we are just using full update in case 2901 * selective fetch area calculation fails. To optimize this we 2902 * should identify cases where this happens and fix the area 2903 * calculation for those. 2904 */ 2905 if (crtc_state->psr2_su_area.y1 == -1) { 2906 drm_info_once(display->drm, 2907 "Selective fetch area calculation failed in pipe %c\n", 2908 pipe_name(crtc->pipe)); 2909 full_update = true; 2910 } 2911 2912 if (full_update) 2913 goto skip_sel_fetch_set_loop; 2914 2915 intel_psr_apply_su_area_workarounds(crtc_state); 2916 2917 ret = drm_atomic_add_affected_planes(&state->base, &crtc->base); 2918 if (ret) 2919 return ret; 2920 2921 /* 2922 * Adjust su area to cover cursor fully as necessary (early 2923 * transport). This needs to be done after 2924 * drm_atomic_add_affected_planes to ensure visible cursor is added into 2925 * affected planes even when cursor is not updated by itself. 2926 */ 2927 intel_psr2_sel_fetch_et_alignment(state, crtc, &cursor_in_su_area); 2928 2929 intel_psr2_sel_fetch_pipe_alignment(crtc_state); 2930 2931 /* 2932 * Now that we have the pipe damaged area check if it intersect with 2933 * every plane, if it does set the plane selective fetch area. 2934 */ 2935 for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state, 2936 new_plane_state, i) { 2937 struct drm_rect *sel_fetch_area, inter; 2938 struct intel_plane *linked = new_plane_state->planar_linked_plane; 2939 2940 if (new_plane_state->uapi.crtc != crtc_state->uapi.crtc || 2941 !new_plane_state->uapi.visible) 2942 continue; 2943 2944 inter = crtc_state->psr2_su_area; 2945 sel_fetch_area = &new_plane_state->psr2_sel_fetch_area; 2946 if (!drm_rect_intersect(&inter, &new_plane_state->uapi.dst)) { 2947 sel_fetch_area->y1 = -1; 2948 sel_fetch_area->y2 = -1; 2949 /* 2950 * if plane sel fetch was previously enabled -> 2951 * disable it 2952 */ 2953 if (drm_rect_height(&old_plane_state->psr2_sel_fetch_area) > 0) 2954 crtc_state->update_planes |= BIT(plane->id); 2955 2956 continue; 2957 } 2958 2959 if (!psr2_sel_fetch_plane_state_supported(new_plane_state)) { 2960 full_update = true; 2961 break; 2962 } 2963 2964 sel_fetch_area = &new_plane_state->psr2_sel_fetch_area; 2965 sel_fetch_area->y1 = inter.y1 - new_plane_state->uapi.dst.y1; 2966 sel_fetch_area->y2 = inter.y2 - new_plane_state->uapi.dst.y1; 2967 crtc_state->update_planes |= BIT(plane->id); 2968 2969 /* 2970 * Sel_fetch_area is calculated for UV plane. Use 2971 * same area for Y plane as well. 2972 */ 2973 if (linked) { 2974 struct intel_plane_state *linked_new_plane_state; 2975 struct drm_rect *linked_sel_fetch_area; 2976 2977 linked_new_plane_state = intel_atomic_get_plane_state(state, linked); 2978 if (IS_ERR(linked_new_plane_state)) 2979 return PTR_ERR(linked_new_plane_state); 2980 2981 linked_sel_fetch_area = &linked_new_plane_state->psr2_sel_fetch_area; 2982 linked_sel_fetch_area->y1 = sel_fetch_area->y1; 2983 linked_sel_fetch_area->y2 = sel_fetch_area->y2; 2984 crtc_state->update_planes |= BIT(linked->id); 2985 } 2986 } 2987 2988 skip_sel_fetch_set_loop: 2989 psr2_man_trk_ctl_calc(crtc_state, full_update); 2990 crtc_state->pipe_srcsz_early_tpt = 2991 psr2_pipe_srcsz_early_tpt_calc(crtc_state, full_update); 2992 return 0; 2993 } 2994 2995 void intel_psr2_panic_force_full_update(struct intel_display *display, 2996 struct intel_crtc_state *crtc_state) 2997 { 2998 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2999 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 3000 u32 val = man_trk_ctl_enable_bit_get(display); 3001 3002 /* SF partial frame enable has to be set even on full update */ 3003 val |= man_trk_ctl_partial_frame_bit_get(display); 3004 val |= man_trk_ctl_continuos_full_frame(display); 3005 3006 /* Directly write the register */ 3007 intel_de_write_fw(display, PSR2_MAN_TRK_CTL(display, cpu_transcoder), val); 3008 3009 if (!crtc_state->enable_psr2_su_region_et) 3010 return; 3011 3012 intel_de_write_fw(display, PIPE_SRCSZ_ERLY_TPT(crtc->pipe), 0); 3013 } 3014 3015 void intel_psr_pre_plane_update(struct intel_atomic_state *state, 3016 struct intel_crtc *crtc) 3017 { 3018 struct intel_display *display = to_intel_display(state); 3019 const struct intel_crtc_state *old_crtc_state = 3020 intel_atomic_get_old_crtc_state(state, crtc); 3021 const struct intel_crtc_state *new_crtc_state = 3022 intel_atomic_get_new_crtc_state(state, crtc); 3023 struct intel_encoder *encoder; 3024 3025 if (!HAS_PSR(display)) 3026 return; 3027 3028 for_each_intel_encoder_mask_with_psr(state->base.dev, encoder, 3029 old_crtc_state->uapi.encoder_mask) { 3030 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 3031 struct intel_psr *psr = &intel_dp->psr; 3032 3033 mutex_lock(&psr->lock); 3034 3035 if (!new_crtc_state->has_psr) 3036 psr->no_psr_reason = new_crtc_state->no_psr_reason; 3037 3038 if (psr->enabled) { 3039 /* 3040 * Reasons to disable: 3041 * - PSR disabled in new state 3042 * - All planes will go inactive 3043 * - Changing between PSR versions 3044 * - Region Early Transport changing 3045 * - Display WA #1136: skl, bxt 3046 */ 3047 if (intel_crtc_needs_modeset(new_crtc_state) || 3048 !new_crtc_state->has_psr || 3049 !new_crtc_state->active_planes || 3050 new_crtc_state->has_sel_update != psr->sel_update_enabled || 3051 new_crtc_state->enable_psr2_su_region_et != psr->su_region_et_enabled || 3052 new_crtc_state->has_panel_replay != psr->panel_replay_enabled || 3053 (DISPLAY_VER(display) < 11 && new_crtc_state->wm_level_disabled)) 3054 intel_psr_disable_locked(intel_dp); 3055 else if (new_crtc_state->wm_level_disabled) 3056 /* Wa_14015648006 */ 3057 wm_optimization_wa(intel_dp, new_crtc_state); 3058 } 3059 3060 mutex_unlock(&psr->lock); 3061 } 3062 } 3063 3064 static void 3065 verify_panel_replay_dsc_state(const struct intel_crtc_state *crtc_state) 3066 { 3067 struct intel_display *display = to_intel_display(crtc_state); 3068 3069 if (!crtc_state->has_panel_replay) 3070 return; 3071 3072 drm_WARN_ON(display->drm, 3073 intel_dsc_enabled_on_link(crtc_state) && 3074 crtc_state->panel_replay_dsc_support == 3075 INTEL_DP_PANEL_REPLAY_DSC_NOT_SUPPORTED); 3076 } 3077 3078 void intel_psr_post_plane_update(struct intel_atomic_state *state, 3079 struct intel_crtc *crtc) 3080 { 3081 struct intel_display *display = to_intel_display(state); 3082 const struct intel_crtc_state *crtc_state = 3083 intel_atomic_get_new_crtc_state(state, crtc); 3084 struct intel_encoder *encoder; 3085 3086 if (!crtc_state->has_psr) 3087 return; 3088 3089 verify_panel_replay_dsc_state(crtc_state); 3090 3091 for_each_intel_encoder_mask_with_psr(state->base.dev, encoder, 3092 crtc_state->uapi.encoder_mask) { 3093 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 3094 struct intel_psr *psr = &intel_dp->psr; 3095 bool keep_disabled = false; 3096 3097 mutex_lock(&psr->lock); 3098 3099 drm_WARN_ON(display->drm, 3100 psr->enabled && !crtc_state->active_planes); 3101 3102 if (psr->sink_not_reliable) 3103 keep_disabled = true; 3104 3105 if (!crtc_state->active_planes) { 3106 psr->no_psr_reason = "All planes inactive"; 3107 keep_disabled = true; 3108 } 3109 3110 /* Display WA #1136: skl, bxt */ 3111 if (DISPLAY_VER(display) < 11 && crtc_state->wm_level_disabled) { 3112 psr->no_psr_reason = "Workaround #1136 for skl, bxt"; 3113 keep_disabled = true; 3114 } 3115 3116 if (!psr->enabled && !keep_disabled) 3117 intel_psr_enable_locked(intel_dp, crtc_state); 3118 else if (psr->enabled && !crtc_state->wm_level_disabled) 3119 /* Wa_14015648006 */ 3120 wm_optimization_wa(intel_dp, crtc_state); 3121 3122 /* Force a PSR exit when enabling CRC to avoid CRC timeouts */ 3123 if (crtc_state->crc_enabled && psr->enabled) 3124 intel_psr_force_update(intel_dp); 3125 3126 /* 3127 * Clear possible busy bits in case we have 3128 * invalidate -> flip -> flush sequence. 3129 */ 3130 intel_dp->psr.busy_frontbuffer_bits = 0; 3131 3132 mutex_unlock(&psr->lock); 3133 } 3134 } 3135 3136 /* 3137 * From bspec: Panel Self Refresh (BDW+) 3138 * Max. time for PSR to idle = Inverse of the refresh rate + 6 ms of 3139 * exit training time + 1.5 ms of aux channel handshake. 50 ms is 3140 * defensive enough to cover everything. 3141 */ 3142 #define PSR_IDLE_TIMEOUT_MS 50 3143 3144 static int 3145 _psr2_ready_for_pipe_update_locked(const struct intel_crtc_state *new_crtc_state, 3146 struct intel_dsb *dsb) 3147 { 3148 struct intel_display *display = to_intel_display(new_crtc_state); 3149 enum transcoder cpu_transcoder = new_crtc_state->cpu_transcoder; 3150 3151 /* 3152 * Any state lower than EDP_PSR2_STATUS_STATE_DEEP_SLEEP is enough. 3153 * As all higher states has bit 4 of PSR2 state set we can just wait for 3154 * EDP_PSR2_STATUS_STATE_DEEP_SLEEP to be cleared. 3155 */ 3156 if (dsb) { 3157 intel_dsb_poll(dsb, EDP_PSR2_STATUS(display, cpu_transcoder), 3158 EDP_PSR2_STATUS_STATE_DEEP_SLEEP, 0, 200, 3159 PSR_IDLE_TIMEOUT_MS * 1000 / 200); 3160 return true; 3161 } 3162 3163 return intel_de_wait_for_clear_ms(display, 3164 EDP_PSR2_STATUS(display, cpu_transcoder), 3165 EDP_PSR2_STATUS_STATE_DEEP_SLEEP, 3166 PSR_IDLE_TIMEOUT_MS); 3167 } 3168 3169 static int 3170 _psr1_ready_for_pipe_update_locked(const struct intel_crtc_state *new_crtc_state, 3171 struct intel_dsb *dsb) 3172 { 3173 struct intel_display *display = to_intel_display(new_crtc_state); 3174 enum transcoder cpu_transcoder = new_crtc_state->cpu_transcoder; 3175 3176 if (dsb) { 3177 intel_dsb_poll(dsb, psr_status_reg(display, cpu_transcoder), 3178 EDP_PSR_STATUS_STATE_MASK, 0, 200, 3179 PSR_IDLE_TIMEOUT_MS * 1000 / 200); 3180 return true; 3181 } 3182 3183 return intel_de_wait_for_clear_ms(display, 3184 psr_status_reg(display, cpu_transcoder), 3185 EDP_PSR_STATUS_STATE_MASK, 3186 PSR_IDLE_TIMEOUT_MS); 3187 } 3188 3189 /** 3190 * intel_psr_wait_for_idle_locked - wait for PSR be ready for a pipe update 3191 * @new_crtc_state: new CRTC state 3192 * 3193 * This function is expected to be called from pipe_update_start() where it is 3194 * not expected to race with PSR enable or disable. 3195 */ 3196 void intel_psr_wait_for_idle_locked(const struct intel_crtc_state *new_crtc_state) 3197 { 3198 struct intel_display *display = to_intel_display(new_crtc_state); 3199 struct intel_encoder *encoder; 3200 3201 if (!new_crtc_state->has_psr) 3202 return; 3203 3204 for_each_intel_encoder_mask_with_psr(display->drm, encoder, 3205 new_crtc_state->uapi.encoder_mask) { 3206 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 3207 int ret; 3208 3209 lockdep_assert_held(&intel_dp->psr.lock); 3210 3211 if (!intel_dp->psr.enabled || intel_dp->psr.panel_replay_enabled) 3212 continue; 3213 3214 if (intel_dp->psr.sel_update_enabled) 3215 ret = _psr2_ready_for_pipe_update_locked(new_crtc_state, 3216 NULL); 3217 else 3218 ret = _psr1_ready_for_pipe_update_locked(new_crtc_state, 3219 NULL); 3220 3221 if (ret) 3222 drm_err(display->drm, 3223 "PSR wait timed out, atomic update may fail\n"); 3224 } 3225 } 3226 3227 void intel_psr_wait_for_idle_dsb(struct intel_dsb *dsb, 3228 const struct intel_crtc_state *new_crtc_state) 3229 { 3230 if (!new_crtc_state->has_psr || new_crtc_state->has_panel_replay) 3231 return; 3232 3233 if (new_crtc_state->has_sel_update) 3234 _psr2_ready_for_pipe_update_locked(new_crtc_state, dsb); 3235 else 3236 _psr1_ready_for_pipe_update_locked(new_crtc_state, dsb); 3237 } 3238 3239 static bool __psr_wait_for_idle_locked(struct intel_dp *intel_dp) 3240 { 3241 struct intel_display *display = to_intel_display(intel_dp); 3242 enum transcoder cpu_transcoder = intel_dp->psr.transcoder; 3243 i915_reg_t reg; 3244 u32 mask; 3245 int err; 3246 3247 if (!intel_dp->psr.enabled) 3248 return false; 3249 3250 if (intel_dp_is_edp(intel_dp) && (intel_dp->psr.sel_update_enabled || 3251 intel_dp->psr.panel_replay_enabled)) { 3252 reg = EDP_PSR2_STATUS(display, cpu_transcoder); 3253 mask = EDP_PSR2_STATUS_STATE_MASK; 3254 } else { 3255 reg = psr_status_reg(display, cpu_transcoder); 3256 mask = EDP_PSR_STATUS_STATE_MASK; 3257 } 3258 3259 mutex_unlock(&intel_dp->psr.lock); 3260 3261 err = intel_de_wait_for_clear_ms(display, reg, mask, 50); 3262 if (err) 3263 drm_err(display->drm, 3264 "Timed out waiting for PSR Idle for re-enable\n"); 3265 3266 /* After the unlocked wait, verify that PSR is still wanted! */ 3267 mutex_lock(&intel_dp->psr.lock); 3268 return err == 0 && intel_dp->psr.enabled && !intel_dp->psr.pause_counter; 3269 } 3270 3271 static int intel_psr_fastset_force(struct intel_display *display) 3272 { 3273 struct drm_connector_list_iter conn_iter; 3274 struct drm_modeset_acquire_ctx ctx; 3275 struct drm_atomic_state *state; 3276 struct drm_connector *conn; 3277 int err = 0; 3278 3279 state = drm_atomic_state_alloc(display->drm); 3280 if (!state) 3281 return -ENOMEM; 3282 3283 drm_modeset_acquire_init(&ctx, DRM_MODESET_ACQUIRE_INTERRUPTIBLE); 3284 3285 state->acquire_ctx = &ctx; 3286 to_intel_atomic_state(state)->internal = true; 3287 3288 retry: 3289 drm_connector_list_iter_begin(display->drm, &conn_iter); 3290 drm_for_each_connector_iter(conn, &conn_iter) { 3291 struct drm_connector_state *conn_state; 3292 struct drm_crtc_state *crtc_state; 3293 3294 if (conn->connector_type != DRM_MODE_CONNECTOR_eDP) 3295 continue; 3296 3297 conn_state = drm_atomic_get_connector_state(state, conn); 3298 if (IS_ERR(conn_state)) { 3299 err = PTR_ERR(conn_state); 3300 break; 3301 } 3302 3303 if (!conn_state->crtc) 3304 continue; 3305 3306 crtc_state = drm_atomic_get_crtc_state(state, conn_state->crtc); 3307 if (IS_ERR(crtc_state)) { 3308 err = PTR_ERR(crtc_state); 3309 break; 3310 } 3311 3312 /* Mark mode as changed to trigger a pipe->update() */ 3313 crtc_state->mode_changed = true; 3314 } 3315 drm_connector_list_iter_end(&conn_iter); 3316 3317 if (err == 0) 3318 err = drm_atomic_commit(state); 3319 3320 if (err == -EDEADLK) { 3321 drm_atomic_state_clear(state); 3322 err = drm_modeset_backoff(&ctx); 3323 if (!err) 3324 goto retry; 3325 } 3326 3327 drm_modeset_drop_locks(&ctx); 3328 drm_modeset_acquire_fini(&ctx); 3329 drm_atomic_state_put(state); 3330 3331 return err; 3332 } 3333 3334 int intel_psr_debug_set(struct intel_dp *intel_dp, u64 val) 3335 { 3336 struct intel_display *display = to_intel_display(intel_dp); 3337 const u32 mode = val & I915_PSR_DEBUG_MODE_MASK; 3338 const u32 disable_bits = val & (I915_PSR_DEBUG_SU_REGION_ET_DISABLE | 3339 I915_PSR_DEBUG_PANEL_REPLAY_DISABLE); 3340 u32 old_mode, old_disable_bits; 3341 int ret; 3342 3343 if (val & ~(I915_PSR_DEBUG_IRQ | I915_PSR_DEBUG_SU_REGION_ET_DISABLE | 3344 I915_PSR_DEBUG_PANEL_REPLAY_DISABLE | 3345 I915_PSR_DEBUG_MODE_MASK) || 3346 mode > I915_PSR_DEBUG_ENABLE_SEL_FETCH) { 3347 drm_dbg_kms(display->drm, "Invalid debug mask %llx\n", val); 3348 return -EINVAL; 3349 } 3350 3351 ret = mutex_lock_interruptible(&intel_dp->psr.lock); 3352 if (ret) 3353 return ret; 3354 3355 old_mode = intel_dp->psr.debug & I915_PSR_DEBUG_MODE_MASK; 3356 old_disable_bits = intel_dp->psr.debug & 3357 (I915_PSR_DEBUG_SU_REGION_ET_DISABLE | 3358 I915_PSR_DEBUG_PANEL_REPLAY_DISABLE); 3359 3360 intel_dp->psr.debug = val; 3361 3362 /* 3363 * Do it right away if it's already enabled, otherwise it will be done 3364 * when enabling the source. 3365 */ 3366 if (intel_dp->psr.enabled) 3367 psr_irq_control(intel_dp); 3368 3369 mutex_unlock(&intel_dp->psr.lock); 3370 3371 if (old_mode != mode || old_disable_bits != disable_bits) 3372 ret = intel_psr_fastset_force(display); 3373 3374 return ret; 3375 } 3376 3377 static void intel_psr_handle_irq(struct intel_dp *intel_dp) 3378 { 3379 struct intel_psr *psr = &intel_dp->psr; 3380 3381 intel_psr_disable_locked(intel_dp); 3382 psr->sink_not_reliable = true; 3383 /* let's make sure that sink is awaken */ 3384 drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, DP_SET_POWER_D0); 3385 } 3386 3387 static void intel_psr_work(struct work_struct *work) 3388 { 3389 struct intel_dp *intel_dp = 3390 container_of(work, typeof(*intel_dp), psr.work); 3391 3392 mutex_lock(&intel_dp->psr.lock); 3393 3394 if (!intel_dp->psr.enabled) 3395 goto unlock; 3396 3397 if (READ_ONCE(intel_dp->psr.irq_aux_error)) { 3398 intel_psr_handle_irq(intel_dp); 3399 goto unlock; 3400 } 3401 3402 if (intel_dp->psr.pause_counter) 3403 goto unlock; 3404 3405 /* 3406 * We have to make sure PSR is ready for re-enable 3407 * otherwise it keeps disabled until next full enable/disable cycle. 3408 * PSR might take some time to get fully disabled 3409 * and be ready for re-enable. 3410 */ 3411 if (!__psr_wait_for_idle_locked(intel_dp)) 3412 goto unlock; 3413 3414 /* 3415 * The delayed work can race with an invalidate hence we need to 3416 * recheck. Since psr_flush first clears this and then reschedules we 3417 * won't ever miss a flush when bailing out here. 3418 */ 3419 if (intel_dp->psr.busy_frontbuffer_bits || intel_dp->psr.active) 3420 goto unlock; 3421 3422 intel_psr_activate(intel_dp); 3423 unlock: 3424 mutex_unlock(&intel_dp->psr.lock); 3425 } 3426 3427 static void intel_psr_configure_full_frame_update(struct intel_dp *intel_dp) 3428 { 3429 struct intel_display *display = to_intel_display(intel_dp); 3430 enum transcoder cpu_transcoder = intel_dp->psr.transcoder; 3431 3432 if (!intel_dp->psr.psr2_sel_fetch_enabled) 3433 return; 3434 3435 if (DISPLAY_VER(display) >= 20) 3436 intel_de_write(display, LNL_SFF_CTL(cpu_transcoder), 3437 LNL_SFF_CTL_SF_SINGLE_FULL_FRAME); 3438 else 3439 intel_de_write(display, 3440 PSR2_MAN_TRK_CTL(display, cpu_transcoder), 3441 man_trk_ctl_enable_bit_get(display) | 3442 man_trk_ctl_partial_frame_bit_get(display) | 3443 man_trk_ctl_single_full_frame_bit_get(display) | 3444 man_trk_ctl_continuos_full_frame(display)); 3445 } 3446 3447 static void _psr_invalidate_handle(struct intel_dp *intel_dp) 3448 { 3449 struct intel_display *display = to_intel_display(intel_dp); 3450 3451 if (DISPLAY_VER(display) < 20 && intel_dp->psr.psr2_sel_fetch_enabled) { 3452 if (!intel_dp->psr.psr2_sel_fetch_cff_enabled) { 3453 intel_dp->psr.psr2_sel_fetch_cff_enabled = true; 3454 intel_psr_configure_full_frame_update(intel_dp); 3455 } 3456 3457 intel_psr_force_update(intel_dp); 3458 } else { 3459 intel_psr_exit(intel_dp); 3460 } 3461 } 3462 3463 /** 3464 * intel_psr_invalidate - Invalidate PSR 3465 * @display: display device 3466 * @frontbuffer_bits: frontbuffer plane tracking bits 3467 * @origin: which operation caused the invalidate 3468 * 3469 * Since the hardware frontbuffer tracking has gaps we need to integrate 3470 * with the software frontbuffer tracking. This function gets called every 3471 * time frontbuffer rendering starts and a buffer gets dirtied. PSR must be 3472 * disabled if the frontbuffer mask contains a buffer relevant to PSR. 3473 * 3474 * Dirty frontbuffers relevant to PSR are tracked in busy_frontbuffer_bits." 3475 */ 3476 void intel_psr_invalidate(struct intel_display *display, 3477 unsigned frontbuffer_bits, enum fb_op_origin origin) 3478 { 3479 struct intel_encoder *encoder; 3480 3481 if (origin == ORIGIN_FLIP) 3482 return; 3483 3484 for_each_intel_encoder_with_psr(display->drm, encoder) { 3485 unsigned int pipe_frontbuffer_bits = frontbuffer_bits; 3486 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 3487 3488 mutex_lock(&intel_dp->psr.lock); 3489 if (!intel_dp->psr.enabled) { 3490 mutex_unlock(&intel_dp->psr.lock); 3491 continue; 3492 } 3493 3494 pipe_frontbuffer_bits &= 3495 INTEL_FRONTBUFFER_ALL_MASK(intel_dp->psr.pipe); 3496 intel_dp->psr.busy_frontbuffer_bits |= pipe_frontbuffer_bits; 3497 3498 if (pipe_frontbuffer_bits) 3499 _psr_invalidate_handle(intel_dp); 3500 3501 mutex_unlock(&intel_dp->psr.lock); 3502 } 3503 } 3504 /* 3505 * When we will be completely rely on PSR2 S/W tracking in future, 3506 * intel_psr_flush() will invalidate and flush the PSR for ORIGIN_FLIP 3507 * event also therefore tgl_dc3co_flush_locked() require to be changed 3508 * accordingly in future. 3509 */ 3510 static void 3511 tgl_dc3co_flush_locked(struct intel_dp *intel_dp, unsigned int frontbuffer_bits, 3512 enum fb_op_origin origin) 3513 { 3514 struct intel_display *display = to_intel_display(intel_dp); 3515 3516 if (!intel_dp->psr.dc3co_exitline || !intel_dp->psr.sel_update_enabled || 3517 !intel_dp->psr.active) 3518 return; 3519 3520 /* 3521 * At every frontbuffer flush flip event modified delay of delayed work, 3522 * when delayed work schedules that means display has been idle. 3523 */ 3524 if (!(frontbuffer_bits & 3525 INTEL_FRONTBUFFER_ALL_MASK(intel_dp->psr.pipe))) 3526 return; 3527 3528 tgl_psr2_enable_dc3co(intel_dp); 3529 mod_delayed_work(display->wq.unordered, &intel_dp->psr.dc3co_work, 3530 intel_dp->psr.dc3co_exit_delay); 3531 } 3532 3533 static void _psr_flush_handle(struct intel_dp *intel_dp) 3534 { 3535 struct intel_display *display = to_intel_display(intel_dp); 3536 3537 if (DISPLAY_VER(display) < 20 && intel_dp->psr.psr2_sel_fetch_enabled) { 3538 /* Selective fetch prior LNL */ 3539 if (intel_dp->psr.psr2_sel_fetch_cff_enabled) { 3540 /* can we turn CFF off? */ 3541 if (intel_dp->psr.busy_frontbuffer_bits == 0) 3542 intel_dp->psr.psr2_sel_fetch_cff_enabled = false; 3543 } 3544 3545 /* 3546 * Still keep cff bit enabled as we don't have proper SU 3547 * configuration in case update is sent for any reason after 3548 * sff bit gets cleared by the HW on next vblank. 3549 * 3550 * NOTE: Setting cff bit is not needed for LunarLake onwards as 3551 * we have own register for SFF bit and we are not overwriting 3552 * existing SU configuration 3553 */ 3554 intel_psr_configure_full_frame_update(intel_dp); 3555 3556 intel_psr_force_update(intel_dp); 3557 } else if (!intel_dp->psr.psr2_sel_fetch_enabled) { 3558 /* 3559 * PSR1 on all platforms 3560 * PSR2 HW tracking 3561 * Panel Replay Full frame update 3562 */ 3563 intel_psr_force_update(intel_dp); 3564 } else { 3565 /* Selective update LNL onwards */ 3566 intel_psr_exit(intel_dp); 3567 } 3568 3569 if (!intel_dp->psr.active && !intel_dp->psr.busy_frontbuffer_bits) 3570 queue_work(display->wq.unordered, &intel_dp->psr.work); 3571 } 3572 3573 /** 3574 * intel_psr_flush - Flush PSR 3575 * @display: display device 3576 * @frontbuffer_bits: frontbuffer plane tracking bits 3577 * @origin: which operation caused the flush 3578 * 3579 * Since the hardware frontbuffer tracking has gaps we need to integrate 3580 * with the software frontbuffer tracking. This function gets called every 3581 * time frontbuffer rendering has completed and flushed out to memory. PSR 3582 * can be enabled again if no other frontbuffer relevant to PSR is dirty. 3583 * 3584 * Dirty frontbuffers relevant to PSR are tracked in busy_frontbuffer_bits. 3585 */ 3586 void intel_psr_flush(struct intel_display *display, 3587 unsigned frontbuffer_bits, enum fb_op_origin origin) 3588 { 3589 struct intel_encoder *encoder; 3590 3591 for_each_intel_encoder_with_psr(display->drm, encoder) { 3592 unsigned int pipe_frontbuffer_bits = frontbuffer_bits; 3593 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 3594 3595 mutex_lock(&intel_dp->psr.lock); 3596 if (!intel_dp->psr.enabled) { 3597 mutex_unlock(&intel_dp->psr.lock); 3598 continue; 3599 } 3600 3601 pipe_frontbuffer_bits &= 3602 INTEL_FRONTBUFFER_ALL_MASK(intel_dp->psr.pipe); 3603 intel_dp->psr.busy_frontbuffer_bits &= ~pipe_frontbuffer_bits; 3604 3605 /* 3606 * If the PSR is paused by an explicit intel_psr_paused() call, 3607 * we have to ensure that the PSR is not activated until 3608 * intel_psr_resume() is called. 3609 */ 3610 if (intel_dp->psr.pause_counter) 3611 goto unlock; 3612 3613 if (origin == ORIGIN_FLIP || 3614 (origin == ORIGIN_CURSOR_UPDATE && 3615 !intel_dp->psr.psr2_sel_fetch_enabled)) { 3616 tgl_dc3co_flush_locked(intel_dp, frontbuffer_bits, origin); 3617 goto unlock; 3618 } 3619 3620 if (pipe_frontbuffer_bits == 0) 3621 goto unlock; 3622 3623 /* By definition flush = invalidate + flush */ 3624 _psr_flush_handle(intel_dp); 3625 unlock: 3626 mutex_unlock(&intel_dp->psr.lock); 3627 } 3628 } 3629 3630 /** 3631 * intel_psr_init - Init basic PSR work and mutex. 3632 * @intel_dp: Intel DP 3633 * 3634 * This function is called after the initializing connector. 3635 * (the initializing of connector treats the handling of connector capabilities) 3636 * And it initializes basic PSR stuff for each DP Encoder. 3637 */ 3638 void intel_psr_init(struct intel_dp *intel_dp) 3639 { 3640 struct intel_display *display = to_intel_display(intel_dp); 3641 struct intel_connector *connector = intel_dp->attached_connector; 3642 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 3643 3644 if (!(HAS_PSR(display) || HAS_DP20(display))) 3645 return; 3646 3647 /* 3648 * HSW spec explicitly says PSR is tied to port A. 3649 * BDW+ platforms have a instance of PSR registers per transcoder but 3650 * BDW, GEN9 and GEN11 are not validated by HW team in other transcoder 3651 * than eDP one. 3652 * For now it only supports one instance of PSR for BDW, GEN9 and GEN11. 3653 * So lets keep it hardcoded to PORT_A for BDW, GEN9 and GEN11. 3654 * But GEN12 supports a instance of PSR registers per transcoder. 3655 */ 3656 if (DISPLAY_VER(display) < 12 && dig_port->base.port != PORT_A) { 3657 drm_dbg_kms(display->drm, 3658 "PSR condition failed: Port not supported\n"); 3659 return; 3660 } 3661 3662 if ((HAS_DP20(display) && !intel_dp_is_edp(intel_dp)) || 3663 DISPLAY_VER(display) >= 20) 3664 intel_dp->psr.source_panel_replay_support = true; 3665 3666 if (HAS_PSR(display) && intel_dp_is_edp(intel_dp)) 3667 intel_dp->psr.source_support = true; 3668 3669 /* Set link_standby x link_off defaults */ 3670 if (DISPLAY_VER(display) < 12) 3671 /* For new platforms up to TGL let's respect VBT back again */ 3672 intel_dp->psr.link_standby = connector->panel.vbt.psr.full_link; 3673 3674 INIT_WORK(&intel_dp->psr.work, intel_psr_work); 3675 INIT_DELAYED_WORK(&intel_dp->psr.dc3co_work, tgl_dc3co_disable_work); 3676 mutex_init(&intel_dp->psr.lock); 3677 } 3678 3679 static int psr_get_status_and_error_status(struct intel_dp *intel_dp, 3680 u8 *status, u8 *error_status) 3681 { 3682 struct drm_dp_aux *aux = &intel_dp->aux; 3683 int ret; 3684 unsigned int offset; 3685 3686 offset = intel_dp->psr.panel_replay_enabled ? 3687 DP_SINK_DEVICE_PR_AND_FRAME_LOCK_STATUS : DP_PSR_STATUS; 3688 3689 ret = drm_dp_dpcd_readb(aux, offset, status); 3690 if (ret != 1) 3691 return ret; 3692 3693 offset = intel_dp->psr.panel_replay_enabled ? 3694 DP_PANEL_REPLAY_ERROR_STATUS : DP_PSR_ERROR_STATUS; 3695 3696 ret = drm_dp_dpcd_readb(aux, offset, error_status); 3697 if (ret != 1) 3698 return ret; 3699 3700 *status = *status & DP_PSR_SINK_STATE_MASK; 3701 3702 return 0; 3703 } 3704 3705 static void psr_alpm_check(struct intel_dp *intel_dp) 3706 { 3707 struct intel_psr *psr = &intel_dp->psr; 3708 3709 if (!psr->sel_update_enabled) 3710 return; 3711 3712 if (intel_alpm_get_error(intel_dp)) { 3713 intel_psr_disable_locked(intel_dp); 3714 psr->sink_not_reliable = true; 3715 } 3716 } 3717 3718 static void psr_capability_changed_check(struct intel_dp *intel_dp) 3719 { 3720 struct intel_display *display = to_intel_display(intel_dp); 3721 struct intel_psr *psr = &intel_dp->psr; 3722 u8 val; 3723 int r; 3724 3725 r = drm_dp_dpcd_readb(&intel_dp->aux, DP_PSR_ESI, &val); 3726 if (r != 1) { 3727 drm_err(display->drm, "Error reading DP_PSR_ESI\n"); 3728 return; 3729 } 3730 3731 if (val & DP_PSR_CAPS_CHANGE) { 3732 intel_psr_disable_locked(intel_dp); 3733 psr->sink_not_reliable = true; 3734 drm_dbg_kms(display->drm, 3735 "Sink PSR capability changed, disabling PSR\n"); 3736 3737 /* Clearing it */ 3738 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_ESI, val); 3739 } 3740 } 3741 3742 /* 3743 * On common bits: 3744 * DP_PSR_RFB_STORAGE_ERROR == DP_PANEL_REPLAY_RFB_STORAGE_ERROR 3745 * DP_PSR_VSC_SDP_UNCORRECTABLE_ERROR == DP_PANEL_REPLAY_VSC_SDP_UNCORRECTABLE_ERROR 3746 * DP_PSR_LINK_CRC_ERROR == DP_PANEL_REPLAY_LINK_CRC_ERROR 3747 * this function is relying on PSR definitions 3748 */ 3749 void intel_psr_short_pulse(struct intel_dp *intel_dp) 3750 { 3751 struct intel_display *display = to_intel_display(intel_dp); 3752 struct intel_psr *psr = &intel_dp->psr; 3753 u8 status, error_status; 3754 const u8 errors = DP_PSR_RFB_STORAGE_ERROR | 3755 DP_PSR_VSC_SDP_UNCORRECTABLE_ERROR | 3756 DP_PSR_LINK_CRC_ERROR; 3757 3758 if (!CAN_PSR(intel_dp) && !CAN_PANEL_REPLAY(intel_dp)) 3759 return; 3760 3761 mutex_lock(&psr->lock); 3762 3763 psr->link_ok = false; 3764 3765 if (!psr->enabled) 3766 goto exit; 3767 3768 if (psr_get_status_and_error_status(intel_dp, &status, &error_status)) { 3769 drm_err(display->drm, 3770 "Error reading PSR status or error status\n"); 3771 goto exit; 3772 } 3773 3774 if ((!psr->panel_replay_enabled && status == DP_PSR_SINK_INTERNAL_ERROR) || 3775 (error_status & errors)) { 3776 intel_psr_disable_locked(intel_dp); 3777 psr->sink_not_reliable = true; 3778 } 3779 3780 if (!psr->panel_replay_enabled && status == DP_PSR_SINK_INTERNAL_ERROR && 3781 !error_status) 3782 drm_dbg_kms(display->drm, 3783 "PSR sink internal error, disabling PSR\n"); 3784 if (error_status & DP_PSR_RFB_STORAGE_ERROR) 3785 drm_dbg_kms(display->drm, 3786 "PSR RFB storage error, disabling PSR\n"); 3787 if (error_status & DP_PSR_VSC_SDP_UNCORRECTABLE_ERROR) 3788 drm_dbg_kms(display->drm, 3789 "PSR VSC SDP uncorrectable error, disabling PSR\n"); 3790 if (error_status & DP_PSR_LINK_CRC_ERROR) 3791 drm_dbg_kms(display->drm, 3792 "PSR Link CRC error, disabling PSR\n"); 3793 3794 if (error_status & ~errors) 3795 drm_err(display->drm, 3796 "PSR_ERROR_STATUS unhandled errors %x\n", 3797 error_status & ~errors); 3798 /* clear status register */ 3799 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_ERROR_STATUS, error_status); 3800 3801 if (!psr->panel_replay_enabled) { 3802 psr_alpm_check(intel_dp); 3803 psr_capability_changed_check(intel_dp); 3804 } 3805 3806 exit: 3807 mutex_unlock(&psr->lock); 3808 } 3809 3810 bool intel_psr_enabled(struct intel_dp *intel_dp) 3811 { 3812 bool ret; 3813 3814 if (!CAN_PSR(intel_dp)) 3815 return false; 3816 3817 mutex_lock(&intel_dp->psr.lock); 3818 ret = intel_dp->psr.enabled; 3819 mutex_unlock(&intel_dp->psr.lock); 3820 3821 return ret; 3822 } 3823 3824 /** 3825 * intel_psr_link_ok - return psr->link_ok 3826 * @intel_dp: struct intel_dp 3827 * 3828 * We are seeing unexpected link re-trainings with some panels. This is caused 3829 * by panel stating bad link status after PSR is enabled. Code checking link 3830 * status can call this to ensure it can ignore bad link status stated by the 3831 * panel I.e. if panel is stating bad link and intel_psr_link_ok is stating link 3832 * is ok caller should rely on latter. 3833 * 3834 * Return value of link_ok 3835 */ 3836 bool intel_psr_link_ok(struct intel_dp *intel_dp) 3837 { 3838 bool ret; 3839 3840 if ((!CAN_PSR(intel_dp) && !CAN_PANEL_REPLAY(intel_dp)) || 3841 !intel_dp_is_edp(intel_dp)) 3842 return false; 3843 3844 mutex_lock(&intel_dp->psr.lock); 3845 ret = intel_dp->psr.link_ok; 3846 mutex_unlock(&intel_dp->psr.lock); 3847 3848 return ret; 3849 } 3850 3851 /** 3852 * intel_psr_lock - grab PSR lock 3853 * @crtc_state: the crtc state 3854 * 3855 * This is initially meant to be used by around CRTC update, when 3856 * vblank sensitive registers are updated and we need grab the lock 3857 * before it to avoid vblank evasion. 3858 */ 3859 void intel_psr_lock(const struct intel_crtc_state *crtc_state) 3860 { 3861 struct intel_display *display = to_intel_display(crtc_state); 3862 struct intel_encoder *encoder; 3863 3864 if (!crtc_state->has_psr) 3865 return; 3866 3867 for_each_intel_encoder_mask_with_psr(display->drm, encoder, 3868 crtc_state->uapi.encoder_mask) { 3869 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 3870 3871 mutex_lock(&intel_dp->psr.lock); 3872 break; 3873 } 3874 } 3875 3876 /** 3877 * intel_psr_unlock - release PSR lock 3878 * @crtc_state: the crtc state 3879 * 3880 * Release the PSR lock that was held during pipe update. 3881 */ 3882 void intel_psr_unlock(const struct intel_crtc_state *crtc_state) 3883 { 3884 struct intel_display *display = to_intel_display(crtc_state); 3885 struct intel_encoder *encoder; 3886 3887 if (!crtc_state->has_psr) 3888 return; 3889 3890 for_each_intel_encoder_mask_with_psr(display->drm, encoder, 3891 crtc_state->uapi.encoder_mask) { 3892 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 3893 3894 mutex_unlock(&intel_dp->psr.lock); 3895 break; 3896 } 3897 } 3898 3899 /* Wa_16025596647 */ 3900 static void intel_psr_apply_underrun_on_idle_wa_locked(struct intel_dp *intel_dp) 3901 { 3902 struct intel_display *display = to_intel_display(intel_dp); 3903 bool dc5_dc6_blocked; 3904 3905 if (!intel_dp->psr.active || !intel_dp->psr.pkg_c_latency_used) 3906 return; 3907 3908 dc5_dc6_blocked = is_dc5_dc6_blocked(intel_dp); 3909 3910 if (intel_dp->psr.sel_update_enabled) 3911 psr2_program_idle_frames(intel_dp, dc5_dc6_blocked ? 0 : 3912 psr_compute_idle_frames(intel_dp)); 3913 else 3914 intel_dmc_start_pkgc_exit_at_start_of_undelayed_vblank(display, 3915 intel_dp->psr.pipe, 3916 dc5_dc6_blocked); 3917 } 3918 3919 static void psr_dc5_dc6_wa_work(struct work_struct *work) 3920 { 3921 struct intel_display *display = container_of(work, typeof(*display), 3922 psr_dc5_dc6_wa_work); 3923 struct intel_encoder *encoder; 3924 3925 for_each_intel_encoder_with_psr(display->drm, encoder) { 3926 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 3927 3928 mutex_lock(&intel_dp->psr.lock); 3929 3930 if (intel_dp->psr.enabled && !intel_dp->psr.panel_replay_enabled && 3931 !intel_dp->psr.pkg_c_latency_used) 3932 intel_psr_apply_underrun_on_idle_wa_locked(intel_dp); 3933 3934 mutex_unlock(&intel_dp->psr.lock); 3935 } 3936 } 3937 3938 /** 3939 * intel_psr_notify_dc5_dc6 - Notify PSR about enable/disable dc5/dc6 3940 * @display: intel atomic state 3941 * 3942 * This is targeted for underrun on idle PSR HW bug (Wa_16025596647) to schedule 3943 * psr_dc5_dc6_wa_work used for applying/removing the workaround. 3944 */ 3945 void intel_psr_notify_dc5_dc6(struct intel_display *display) 3946 { 3947 if (DISPLAY_VER(display) != 20 && 3948 !IS_DISPLAY_VERx100_STEP(display, 3000, STEP_A0, STEP_B0)) 3949 return; 3950 3951 schedule_work(&display->psr_dc5_dc6_wa_work); 3952 } 3953 3954 /** 3955 * intel_psr_dc5_dc6_wa_init - Init work for underrun on idle PSR HW bug wa 3956 * @display: intel atomic state 3957 * 3958 * This is targeted for underrun on idle PSR HW bug (Wa_16025596647) to init 3959 * psr_dc5_dc6_wa_work used for applying the workaround. 3960 */ 3961 void intel_psr_dc5_dc6_wa_init(struct intel_display *display) 3962 { 3963 if (DISPLAY_VER(display) != 20 && 3964 !IS_DISPLAY_VERx100_STEP(display, 3000, STEP_A0, STEP_B0)) 3965 return; 3966 3967 INIT_WORK(&display->psr_dc5_dc6_wa_work, psr_dc5_dc6_wa_work); 3968 } 3969 3970 /** 3971 * intel_psr_notify_pipe_change - Notify PSR about enable/disable of a pipe 3972 * @state: intel atomic state 3973 * @crtc: intel crtc 3974 * @enable: enable/disable 3975 * 3976 * This is targeted for underrun on idle PSR HW bug (Wa_16025596647) to apply 3977 * remove the workaround when pipe is getting enabled/disabled 3978 */ 3979 void intel_psr_notify_pipe_change(struct intel_atomic_state *state, 3980 struct intel_crtc *crtc, bool enable) 3981 { 3982 struct intel_display *display = to_intel_display(state); 3983 struct intel_encoder *encoder; 3984 3985 if (DISPLAY_VER(display) != 20 && 3986 !IS_DISPLAY_VERx100_STEP(display, 3000, STEP_A0, STEP_B0)) 3987 return; 3988 3989 for_each_intel_encoder_with_psr(display->drm, encoder) { 3990 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 3991 u8 active_non_psr_pipes; 3992 3993 mutex_lock(&intel_dp->psr.lock); 3994 3995 if (!intel_dp->psr.enabled || intel_dp->psr.panel_replay_enabled) 3996 goto unlock; 3997 3998 active_non_psr_pipes = intel_dp->psr.active_non_psr_pipes; 3999 4000 if (enable) 4001 active_non_psr_pipes |= BIT(crtc->pipe); 4002 else 4003 active_non_psr_pipes &= ~BIT(crtc->pipe); 4004 4005 if (active_non_psr_pipes == intel_dp->psr.active_non_psr_pipes) 4006 goto unlock; 4007 4008 if ((enable && intel_dp->psr.active_non_psr_pipes) || 4009 (!enable && !intel_dp->psr.active_non_psr_pipes) || 4010 !intel_dp->psr.pkg_c_latency_used) { 4011 intel_dp->psr.active_non_psr_pipes = active_non_psr_pipes; 4012 goto unlock; 4013 } 4014 4015 intel_dp->psr.active_non_psr_pipes = active_non_psr_pipes; 4016 4017 intel_psr_apply_underrun_on_idle_wa_locked(intel_dp); 4018 unlock: 4019 mutex_unlock(&intel_dp->psr.lock); 4020 } 4021 } 4022 4023 /** 4024 * intel_psr_notify_vblank_enable_disable - Notify PSR about enable/disable of vblank 4025 * @display: intel display struct 4026 * @enable: enable/disable 4027 * 4028 * This is targeted for underrun on idle PSR HW bug (Wa_16025596647) to apply 4029 * remove the workaround when vblank is getting enabled/disabled 4030 */ 4031 void intel_psr_notify_vblank_enable_disable(struct intel_display *display, 4032 bool enable) 4033 { 4034 struct intel_encoder *encoder; 4035 4036 for_each_intel_encoder_with_psr(display->drm, encoder) { 4037 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 4038 4039 mutex_lock(&intel_dp->psr.lock); 4040 if (intel_dp->psr.panel_replay_enabled) { 4041 mutex_unlock(&intel_dp->psr.lock); 4042 break; 4043 } 4044 4045 if (intel_dp->psr.enabled && intel_dp->psr.pkg_c_latency_used) 4046 intel_psr_apply_underrun_on_idle_wa_locked(intel_dp); 4047 4048 mutex_unlock(&intel_dp->psr.lock); 4049 return; 4050 } 4051 4052 /* 4053 * NOTE: intel_display_power_set_target_dc_state is used 4054 * only by PSR * code for DC3CO handling. DC3CO target 4055 * state is currently disabled in * PSR code. If DC3CO 4056 * is taken into use we need take that into account here 4057 * as well. 4058 */ 4059 intel_display_power_set_target_dc_state(display, enable ? DC_STATE_DISABLE : 4060 DC_STATE_EN_UPTO_DC6); 4061 } 4062 4063 static void 4064 psr_source_status(struct intel_dp *intel_dp, struct seq_file *m) 4065 { 4066 struct intel_display *display = to_intel_display(intel_dp); 4067 enum transcoder cpu_transcoder = intel_dp->psr.transcoder; 4068 const char *status = "unknown"; 4069 u32 val, status_val; 4070 4071 if ((intel_dp_is_edp(intel_dp) || DISPLAY_VER(display) >= 30) && 4072 (intel_dp->psr.sel_update_enabled || intel_dp->psr.panel_replay_enabled)) { 4073 static const char * const live_status[] = { 4074 "IDLE", 4075 "CAPTURE", 4076 "CAPTURE_FS", 4077 "SLEEP", 4078 "BUFON_FW", 4079 "ML_UP", 4080 "SU_STANDBY", 4081 "FAST_SLEEP", 4082 "DEEP_SLEEP", 4083 "BUF_ON", 4084 "TG_ON" 4085 }; 4086 val = intel_de_read(display, 4087 EDP_PSR2_STATUS(display, cpu_transcoder)); 4088 status_val = REG_FIELD_GET(EDP_PSR2_STATUS_STATE_MASK, val); 4089 if (status_val < ARRAY_SIZE(live_status)) 4090 status = live_status[status_val]; 4091 } else { 4092 static const char * const live_status[] = { 4093 "IDLE", 4094 "SRDONACK", 4095 "SRDENT", 4096 "BUFOFF", 4097 "BUFON", 4098 "AUXACK", 4099 "SRDOFFACK", 4100 "SRDENT_ON", 4101 }; 4102 val = intel_de_read(display, 4103 psr_status_reg(display, cpu_transcoder)); 4104 status_val = REG_FIELD_GET(EDP_PSR_STATUS_STATE_MASK, val); 4105 if (status_val < ARRAY_SIZE(live_status)) 4106 status = live_status[status_val]; 4107 } 4108 4109 seq_printf(m, "Source PSR/PanelReplay status: %s [0x%08x]\n", status, val); 4110 } 4111 4112 static void intel_psr_sink_capability(struct intel_dp *intel_dp, 4113 struct seq_file *m) 4114 { 4115 struct intel_psr *psr = &intel_dp->psr; 4116 4117 seq_printf(m, "Sink support: PSR = %s", 4118 str_yes_no(psr->sink_support)); 4119 4120 if (psr->sink_support) 4121 seq_printf(m, " [0x%02x]", intel_dp->psr_dpcd[0]); 4122 if (intel_dp->psr_dpcd[0] == DP_PSR2_WITH_Y_COORD_ET_SUPPORTED) 4123 seq_printf(m, " (Early Transport)"); 4124 seq_printf(m, ", Panel Replay = %s", str_yes_no(psr->sink_panel_replay_support)); 4125 seq_printf(m, ", Panel Replay Selective Update = %s", 4126 str_yes_no(psr->sink_panel_replay_su_support)); 4127 seq_printf(m, ", Panel Replay DSC support = %s", 4128 panel_replay_dsc_support_str(psr->sink_panel_replay_dsc_support)); 4129 if (intel_dp->pr_dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_SUPPORT)] & 4130 DP_PANEL_REPLAY_EARLY_TRANSPORT_SUPPORT) 4131 seq_printf(m, " (Early Transport)"); 4132 seq_printf(m, "\n"); 4133 } 4134 4135 static void intel_psr_print_mode(struct intel_dp *intel_dp, 4136 struct seq_file *m) 4137 { 4138 struct intel_psr *psr = &intel_dp->psr; 4139 const char *status, *mode, *region_et; 4140 4141 if (psr->enabled) 4142 status = " enabled"; 4143 else 4144 status = "disabled"; 4145 4146 if (psr->panel_replay_enabled && psr->sel_update_enabled) 4147 mode = "Panel Replay Selective Update"; 4148 else if (psr->panel_replay_enabled) 4149 mode = "Panel Replay"; 4150 else if (psr->sel_update_enabled) 4151 mode = "PSR2"; 4152 else if (psr->enabled) 4153 mode = "PSR1"; 4154 else 4155 mode = ""; 4156 4157 if (psr->su_region_et_enabled) 4158 region_et = " (Early Transport)"; 4159 else 4160 region_et = ""; 4161 4162 seq_printf(m, "PSR mode: %s%s%s\n", mode, status, region_et); 4163 if (psr->no_psr_reason) 4164 seq_printf(m, " %s\n", psr->no_psr_reason); 4165 } 4166 4167 static int intel_psr_status(struct seq_file *m, struct intel_dp *intel_dp) 4168 { 4169 struct intel_display *display = to_intel_display(intel_dp); 4170 enum transcoder cpu_transcoder = intel_dp->psr.transcoder; 4171 struct intel_psr *psr = &intel_dp->psr; 4172 struct ref_tracker *wakeref; 4173 bool enabled; 4174 u32 val, psr2_ctl; 4175 4176 intel_psr_sink_capability(intel_dp, m); 4177 4178 if (!(psr->sink_support || psr->sink_panel_replay_support)) 4179 return 0; 4180 4181 wakeref = intel_display_rpm_get(display); 4182 mutex_lock(&psr->lock); 4183 4184 intel_psr_print_mode(intel_dp, m); 4185 4186 if (!psr->enabled) { 4187 seq_printf(m, "PSR sink not reliable: %s\n", 4188 str_yes_no(psr->sink_not_reliable)); 4189 4190 goto unlock; 4191 } 4192 4193 if (psr->panel_replay_enabled) { 4194 val = intel_de_read(display, TRANS_DP2_CTL(cpu_transcoder)); 4195 4196 if (intel_dp_is_edp(intel_dp)) 4197 psr2_ctl = intel_de_read(display, 4198 EDP_PSR2_CTL(display, 4199 cpu_transcoder)); 4200 4201 enabled = val & TRANS_DP2_PANEL_REPLAY_ENABLE; 4202 } else if (psr->sel_update_enabled) { 4203 val = intel_de_read(display, 4204 EDP_PSR2_CTL(display, cpu_transcoder)); 4205 enabled = val & EDP_PSR2_ENABLE; 4206 } else { 4207 val = intel_de_read(display, psr_ctl_reg(display, cpu_transcoder)); 4208 enabled = val & EDP_PSR_ENABLE; 4209 } 4210 seq_printf(m, "Source PSR/PanelReplay ctl: %s [0x%08x]\n", 4211 str_enabled_disabled(enabled), val); 4212 if (psr->panel_replay_enabled && intel_dp_is_edp(intel_dp)) 4213 seq_printf(m, "PSR2_CTL: 0x%08x\n", 4214 psr2_ctl); 4215 psr_source_status(intel_dp, m); 4216 seq_printf(m, "Busy frontbuffer bits: 0x%08x\n", 4217 psr->busy_frontbuffer_bits); 4218 4219 /* 4220 * SKL+ Perf counter is reset to 0 everytime DC state is entered 4221 */ 4222 val = intel_de_read(display, psr_perf_cnt_reg(display, cpu_transcoder)); 4223 seq_printf(m, "Performance counter: %u\n", 4224 REG_FIELD_GET(EDP_PSR_PERF_CNT_MASK, val)); 4225 4226 if (psr->debug & I915_PSR_DEBUG_IRQ) { 4227 seq_printf(m, "Last attempted entry at: %lld\n", 4228 psr->last_entry_attempt); 4229 seq_printf(m, "Last exit at: %lld\n", psr->last_exit); 4230 } 4231 4232 if (psr->sel_update_enabled) { 4233 u32 su_frames_val[3]; 4234 int frame; 4235 4236 /* 4237 * PSR2_SU_STATUS register has been tied-off since DG2/ADL-P 4238 * (it returns zeros only) and it has been removed on Xe2_LPD. 4239 */ 4240 if (DISPLAY_VER(display) < 13) { 4241 /* 4242 * Reading all 3 registers before hand to minimize crossing a 4243 * frame boundary between register reads 4244 */ 4245 for (frame = 0; frame < PSR2_SU_STATUS_FRAMES; frame += 3) { 4246 val = intel_de_read(display, 4247 PSR2_SU_STATUS(display, cpu_transcoder, frame)); 4248 su_frames_val[frame / 3] = val; 4249 } 4250 4251 seq_puts(m, "Frame:\tPSR2 SU blocks:\n"); 4252 4253 for (frame = 0; frame < PSR2_SU_STATUS_FRAMES; frame++) { 4254 u32 su_blocks; 4255 4256 su_blocks = su_frames_val[frame / 3] & 4257 PSR2_SU_STATUS_MASK(frame); 4258 su_blocks = su_blocks >> PSR2_SU_STATUS_SHIFT(frame); 4259 seq_printf(m, "%d\t%d\n", frame, su_blocks); 4260 } 4261 } 4262 4263 seq_printf(m, "PSR2 selective fetch: %s\n", 4264 str_enabled_disabled(psr->psr2_sel_fetch_enabled)); 4265 } 4266 4267 unlock: 4268 mutex_unlock(&psr->lock); 4269 intel_display_rpm_put(display, wakeref); 4270 4271 return 0; 4272 } 4273 4274 static int i915_edp_psr_status_show(struct seq_file *m, void *data) 4275 { 4276 struct intel_display *display = m->private; 4277 struct intel_dp *intel_dp = NULL; 4278 struct intel_encoder *encoder; 4279 4280 if (!HAS_PSR(display)) 4281 return -ENODEV; 4282 4283 /* Find the first EDP which supports PSR */ 4284 for_each_intel_encoder_with_psr(display->drm, encoder) { 4285 intel_dp = enc_to_intel_dp(encoder); 4286 break; 4287 } 4288 4289 if (!intel_dp) 4290 return -ENODEV; 4291 4292 return intel_psr_status(m, intel_dp); 4293 } 4294 DEFINE_SHOW_ATTRIBUTE(i915_edp_psr_status); 4295 4296 static int 4297 i915_edp_psr_debug_set(void *data, u64 val) 4298 { 4299 struct intel_display *display = data; 4300 struct intel_encoder *encoder; 4301 int ret = -ENODEV; 4302 4303 if (!HAS_PSR(display)) 4304 return ret; 4305 4306 for_each_intel_encoder_with_psr(display->drm, encoder) { 4307 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 4308 4309 drm_dbg_kms(display->drm, "Setting PSR debug to %llx\n", val); 4310 4311 // TODO: split to each transcoder's PSR debug state 4312 with_intel_display_rpm(display) 4313 ret = intel_psr_debug_set(intel_dp, val); 4314 } 4315 4316 return ret; 4317 } 4318 4319 static int 4320 i915_edp_psr_debug_get(void *data, u64 *val) 4321 { 4322 struct intel_display *display = data; 4323 struct intel_encoder *encoder; 4324 4325 if (!HAS_PSR(display)) 4326 return -ENODEV; 4327 4328 for_each_intel_encoder_with_psr(display->drm, encoder) { 4329 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 4330 4331 // TODO: split to each transcoder's PSR debug state 4332 *val = READ_ONCE(intel_dp->psr.debug); 4333 return 0; 4334 } 4335 4336 return -ENODEV; 4337 } 4338 4339 DEFINE_SIMPLE_ATTRIBUTE(i915_edp_psr_debug_fops, 4340 i915_edp_psr_debug_get, i915_edp_psr_debug_set, 4341 "%llu\n"); 4342 4343 void intel_psr_debugfs_register(struct intel_display *display) 4344 { 4345 struct dentry *debugfs_root = display->drm->debugfs_root; 4346 4347 debugfs_create_file("i915_edp_psr_debug", 0644, debugfs_root, 4348 display, &i915_edp_psr_debug_fops); 4349 4350 debugfs_create_file("i915_edp_psr_status", 0444, debugfs_root, 4351 display, &i915_edp_psr_status_fops); 4352 } 4353 4354 static const char *psr_mode_str(struct intel_dp *intel_dp) 4355 { 4356 if (intel_dp->psr.panel_replay_enabled) 4357 return "PANEL-REPLAY"; 4358 else if (intel_dp->psr.enabled) 4359 return "PSR"; 4360 4361 return "unknown"; 4362 } 4363 4364 static int i915_psr_sink_status_show(struct seq_file *m, void *data) 4365 { 4366 struct intel_connector *connector = m->private; 4367 struct intel_dp *intel_dp = intel_attached_dp(connector); 4368 static const char * const sink_status[] = { 4369 "inactive", 4370 "transition to active, capture and display", 4371 "active, display from RFB", 4372 "active, capture and display on sink device timings", 4373 "transition to inactive, capture and display, timing re-sync", 4374 "reserved", 4375 "reserved", 4376 "sink internal error", 4377 }; 4378 const char *str; 4379 int ret; 4380 u8 status, error_status; 4381 4382 if (!(CAN_PSR(intel_dp) || CAN_PANEL_REPLAY(intel_dp))) { 4383 seq_puts(m, "PSR/Panel-Replay Unsupported\n"); 4384 return -ENODEV; 4385 } 4386 4387 if (connector->base.status != connector_status_connected) 4388 return -ENODEV; 4389 4390 ret = psr_get_status_and_error_status(intel_dp, &status, &error_status); 4391 if (ret) 4392 return ret; 4393 4394 status &= DP_PSR_SINK_STATE_MASK; 4395 if (status < ARRAY_SIZE(sink_status)) 4396 str = sink_status[status]; 4397 else 4398 str = "unknown"; 4399 4400 seq_printf(m, "Sink %s status: 0x%x [%s]\n", psr_mode_str(intel_dp), status, str); 4401 4402 seq_printf(m, "Sink %s error status: 0x%x", psr_mode_str(intel_dp), error_status); 4403 4404 if (error_status & (DP_PSR_RFB_STORAGE_ERROR | 4405 DP_PSR_VSC_SDP_UNCORRECTABLE_ERROR | 4406 DP_PSR_LINK_CRC_ERROR)) 4407 seq_puts(m, ":\n"); 4408 else 4409 seq_puts(m, "\n"); 4410 if (error_status & DP_PSR_RFB_STORAGE_ERROR) 4411 seq_printf(m, "\t%s RFB storage error\n", psr_mode_str(intel_dp)); 4412 if (error_status & DP_PSR_VSC_SDP_UNCORRECTABLE_ERROR) 4413 seq_printf(m, "\t%s VSC SDP uncorrectable error\n", psr_mode_str(intel_dp)); 4414 if (error_status & DP_PSR_LINK_CRC_ERROR) 4415 seq_printf(m, "\t%s Link CRC error\n", psr_mode_str(intel_dp)); 4416 4417 return ret; 4418 } 4419 DEFINE_SHOW_ATTRIBUTE(i915_psr_sink_status); 4420 4421 static int i915_psr_status_show(struct seq_file *m, void *data) 4422 { 4423 struct intel_connector *connector = m->private; 4424 struct intel_dp *intel_dp = intel_attached_dp(connector); 4425 4426 return intel_psr_status(m, intel_dp); 4427 } 4428 DEFINE_SHOW_ATTRIBUTE(i915_psr_status); 4429 4430 void intel_psr_connector_debugfs_add(struct intel_connector *connector) 4431 { 4432 struct intel_display *display = to_intel_display(connector); 4433 struct dentry *root = connector->base.debugfs_entry; 4434 4435 if (connector->base.connector_type != DRM_MODE_CONNECTOR_eDP && 4436 connector->base.connector_type != DRM_MODE_CONNECTOR_DisplayPort) 4437 return; 4438 4439 debugfs_create_file("i915_psr_sink_status", 0444, root, 4440 connector, &i915_psr_sink_status_fops); 4441 4442 if (HAS_PSR(display) || HAS_DP20(display)) 4443 debugfs_create_file("i915_psr_status", 0444, root, 4444 connector, &i915_psr_status_fops); 4445 } 4446 4447 bool intel_psr_needs_alpm(struct intel_dp *intel_dp, const struct intel_crtc_state *crtc_state) 4448 { 4449 /* 4450 * eDP Panel Replay uses always ALPM 4451 * PSR2 uses ALPM but PSR1 doesn't 4452 */ 4453 return intel_dp_is_edp(intel_dp) && (crtc_state->has_sel_update || 4454 crtc_state->has_panel_replay); 4455 } 4456 4457 bool intel_psr_needs_alpm_aux_less(struct intel_dp *intel_dp, 4458 const struct intel_crtc_state *crtc_state) 4459 { 4460 return intel_dp_is_edp(intel_dp) && crtc_state->has_panel_replay; 4461 } 4462 4463 void intel_psr_compute_config_late(struct intel_dp *intel_dp, 4464 struct intel_crtc_state *crtc_state) 4465 { 4466 struct intel_display *display = to_intel_display(intel_dp); 4467 int vblank = intel_crtc_vblank_length(crtc_state); 4468 int wake_lines; 4469 4470 if (intel_psr_needs_alpm_aux_less(intel_dp, crtc_state)) 4471 wake_lines = crtc_state->alpm_state.aux_less_wake_lines; 4472 else if (intel_psr_needs_alpm(intel_dp, crtc_state)) 4473 wake_lines = DISPLAY_VER(display) < 20 ? 4474 psr2_block_count_lines(crtc_state->alpm_state.io_wake_lines, 4475 crtc_state->alpm_state.fast_wake_lines) : 4476 crtc_state->alpm_state.io_wake_lines; 4477 else 4478 wake_lines = 0; 4479 4480 /* 4481 * Disable the PSR features if wake lines exceed the available vblank. 4482 * Though SCL is computed based on these PSR features, it is not reset 4483 * even if the PSR features are disabled to avoid changing vblank start 4484 * at this stage. 4485 */ 4486 if (wake_lines && !_wake_lines_fit_into_vblank(crtc_state, vblank, wake_lines)) { 4487 drm_dbg_kms(display->drm, 4488 "Adjusting PSR/PR mode: vblank too short for wake lines = %d\n", 4489 wake_lines); 4490 4491 if (crtc_state->has_panel_replay) { 4492 crtc_state->has_panel_replay = false; 4493 /* 4494 * #TODO : Add fall back to PSR/PSR2 4495 * Since panel replay cannot be supported, we can fall back to PSR/PSR2. 4496 * This will require calling compute_config for psr and psr2 with check for 4497 * actual guardband instead of vblank_length. 4498 */ 4499 crtc_state->has_psr = false; 4500 } 4501 4502 crtc_state->has_sel_update = false; 4503 crtc_state->enable_psr2_su_region_et = false; 4504 crtc_state->enable_psr2_sel_fetch = false; 4505 } 4506 4507 /* Wa_18037818876 */ 4508 if (intel_psr_needs_wa_18037818876(intel_dp, crtc_state)) { 4509 crtc_state->has_psr = false; 4510 drm_dbg_kms(display->drm, 4511 "PSR disabled to workaround PSR FSM hang issue\n"); 4512 } 4513 4514 intel_psr_set_non_psr_pipes(intel_dp, crtc_state); 4515 } 4516 4517 int intel_psr_min_guardband(struct intel_crtc_state *crtc_state) 4518 { 4519 struct intel_display *display = to_intel_display(crtc_state); 4520 int psr_min_guardband; 4521 int wake_lines; 4522 4523 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) 4524 return 0; 4525 4526 if (crtc_state->has_panel_replay) 4527 wake_lines = crtc_state->alpm_state.aux_less_wake_lines; 4528 else if (crtc_state->has_sel_update) 4529 wake_lines = DISPLAY_VER(display) < 20 ? 4530 psr2_block_count_lines(crtc_state->alpm_state.io_wake_lines, 4531 crtc_state->alpm_state.fast_wake_lines) : 4532 crtc_state->alpm_state.io_wake_lines; 4533 else 4534 return 0; 4535 4536 psr_min_guardband = wake_lines + crtc_state->set_context_latency; 4537 4538 if (crtc_state->req_psr2_sdp_prior_scanline) 4539 psr_min_guardband++; 4540 4541 return psr_min_guardband; 4542 } 4543