1 /* 2 * Copyright © 2014 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 */ 23 24 #include <linux/debugfs.h> 25 26 #include <drm/drm_atomic_helper.h> 27 #include <drm/drm_damage_helper.h> 28 #include <drm/drm_debugfs.h> 29 #include <drm/drm_print.h> 30 #include <drm/drm_vblank.h> 31 #include <drm/intel/step.h> 32 33 #include "intel_alpm.h" 34 #include "intel_atomic.h" 35 #include "intel_crtc.h" 36 #include "intel_cursor_regs.h" 37 #include "intel_ddi.h" 38 #include "intel_de.h" 39 #include "intel_display_irq.h" 40 #include "intel_display_regs.h" 41 #include "intel_display_rpm.h" 42 #include "intel_display_types.h" 43 #include "intel_display_utils.h" 44 #include "intel_display_wa.h" 45 #include "intel_dmc.h" 46 #include "intel_dp.h" 47 #include "intel_dp_aux.h" 48 #include "intel_dp_tunnel.h" 49 #include "intel_dsb.h" 50 #include "intel_frontbuffer.h" 51 #include "intel_hdmi.h" 52 #include "intel_psr.h" 53 #include "intel_psr_regs.h" 54 #include "intel_quirks.h" 55 #include "intel_snps_phy.h" 56 #include "intel_vblank.h" 57 #include "intel_vdsc.h" 58 #include "intel_vrr.h" 59 #include "skl_universal_plane.h" 60 61 /** 62 * DOC: Panel Self Refresh (PSR/SRD) 63 * 64 * Since Haswell Display controller supports Panel Self-Refresh on display 65 * panels witch have a remote frame buffer (RFB) implemented according to PSR 66 * spec in eDP1.3. PSR feature allows the display to go to lower standby states 67 * when system is idle but display is on as it eliminates display refresh 68 * request to DDR memory completely as long as the frame buffer for that 69 * display is unchanged. 70 * 71 * Panel Self Refresh must be supported by both Hardware (source) and 72 * Panel (sink). 73 * 74 * PSR saves power by caching the framebuffer in the panel RFB, which allows us 75 * to power down the link and memory controller. For DSI panels the same idea 76 * is called "manual mode". 77 * 78 * The implementation uses the hardware-based PSR support which automatically 79 * enters/exits self-refresh mode. The hardware takes care of sending the 80 * required DP aux message and could even retrain the link (that part isn't 81 * enabled yet though). The hardware also keeps track of any frontbuffer 82 * changes to know when to exit self-refresh mode again. Unfortunately that 83 * part doesn't work too well, hence why the i915 PSR support uses the 84 * software frontbuffer tracking to make sure it doesn't miss a screen 85 * update. For this integration intel_psr_invalidate() and intel_psr_flush() 86 * get called by the frontbuffer tracking code. Note that because of locking 87 * issues the self-refresh re-enable code is done from a work queue, which 88 * must be correctly synchronized/cancelled when shutting down the pipe." 89 * 90 * DC3CO (DC3 clock off) 91 * 92 * On top of PSR2, GEN12 adds a intermediate power savings state that turns 93 * clock off automatically during PSR2 idle state. 94 * The smaller overhead of DC3co entry/exit vs. the overhead of PSR2 deep sleep 95 * entry/exit allows the HW to enter a low-power state even when page flipping 96 * periodically (for instance a 30fps video playback scenario). 97 * 98 * Every time a flips occurs PSR2 will get out of deep sleep state(if it was), 99 * so DC3CO is enabled and tgl_dc3co_disable_work is schedule to run after 6 100 * frames, if no other flip occurs and the function above is executed, DC3CO is 101 * disabled and PSR2 is configured to enter deep sleep, resetting again in case 102 * of another flip. 103 * Front buffer modifications do not trigger DC3CO activation on purpose as it 104 * would bring a lot of complexity and most of the moderns systems will only 105 * use page flips. 106 */ 107 108 /* 109 * Description of PSR mask bits: 110 * 111 * EDP_PSR_DEBUG[16]/EDP_PSR_DEBUG_MASK_DISP_REG_WRITE (hsw-skl): 112 * 113 * When unmasked (nearly) all display register writes (eg. even 114 * SWF) trigger a PSR exit. Some registers are excluded from this 115 * and they have a more specific mask (described below). On icl+ 116 * this bit no longer exists and is effectively always set. 117 * 118 * PIPE_MISC[21]/PIPE_MISC_PSR_MASK_PIPE_REG_WRITE (skl+): 119 * 120 * When unmasked (nearly) all pipe/plane register writes 121 * trigger a PSR exit. Some plane registers are excluded from this 122 * and they have a more specific mask (described below). 123 * 124 * CHICKEN_PIPESL_1[11]/SKL_PSR_MASK_PLANE_FLIP (skl+): 125 * PIPE_MISC[23]/PIPE_MISC_PSR_MASK_PRIMARY_FLIP (bdw): 126 * EDP_PSR_DEBUG[23]/EDP_PSR_DEBUG_MASK_PRIMARY_FLIP (hsw): 127 * 128 * When unmasked PRI_SURF/PLANE_SURF writes trigger a PSR exit. 129 * SPR_SURF/CURBASE are not included in this and instead are 130 * controlled by PIPE_MISC_PSR_MASK_PIPE_REG_WRITE (skl+) or 131 * EDP_PSR_DEBUG_MASK_DISP_REG_WRITE (hsw/bdw). 132 * 133 * PIPE_MISC[22]/PIPE_MISC_PSR_MASK_SPRITE_ENABLE (bdw): 134 * EDP_PSR_DEBUG[21]/EDP_PSR_DEBUG_MASK_SPRITE_ENABLE (hsw): 135 * 136 * When unmasked PSR is blocked as long as the sprite 137 * plane is enabled. skl+ with their universal planes no 138 * longer have a mask bit like this, and no plane being 139 * enabledb blocks PSR. 140 * 141 * PIPE_MISC[21]/PIPE_MISC_PSR_MASK_CURSOR_MOVE (bdw): 142 * EDP_PSR_DEBUG[20]/EDP_PSR_DEBUG_MASK_CURSOR_MOVE (hsw): 143 * 144 * When umasked CURPOS writes trigger a PSR exit. On skl+ 145 * this doesn't exit but CURPOS is included in the 146 * PIPE_MISC_PSR_MASK_PIPE_REG_WRITE mask. 147 * 148 * PIPE_MISC[20]/PIPE_MISC_PSR_MASK_VBLANK_VSYNC_INT (bdw+): 149 * EDP_PSR_DEBUG[19]/EDP_PSR_DEBUG_MASK_VBLANK_VSYNC_INT (hsw): 150 * 151 * When unmasked PSR is blocked as long as vblank and/or vsync 152 * interrupt is unmasked in IMR *and* enabled in IER. 153 * 154 * CHICKEN_TRANS[30]/SKL_UNMASK_VBL_TO_PIPE_IN_SRD (skl+): 155 * CHICKEN_PAR1_1[15]/HSW_MASK_VBL_TO_PIPE_IN_SRD (hsw/bdw): 156 * 157 * Selectcs whether PSR exit generates an extra vblank before 158 * the first frame is transmitted. Also note the opposite polarity 159 * if the bit on hsw/bdw vs. skl+ (masked==generate the extra vblank, 160 * unmasked==do not generate the extra vblank). 161 * 162 * With DC states enabled the extra vblank happens after link training, 163 * with DC states disabled it happens immediately upuon PSR exit trigger. 164 * No idea as of now why there is a difference. HSW/BDW (which don't 165 * even have DMC) always generate it after link training. Go figure. 166 * 167 * Unfortunately CHICKEN_TRANS itself seems to be double buffered 168 * and thus won't latch until the first vblank. So with DC states 169 * enabled the register effectively uses the reset value during DC5 170 * exit+PSR exit sequence, and thus the bit does nothing until 171 * latched by the vblank that it was trying to prevent from being 172 * generated in the first place. So we should probably call this 173 * one a chicken/egg bit instead on skl+. 174 * 175 * In standby mode (as opposed to link-off) this makes no difference 176 * as the timing generator keeps running the whole time generating 177 * normal periodic vblanks. 178 * 179 * WaPsrDPAMaskVBlankInSRD asks us to set the bit on hsw/bdw, 180 * and doing so makes the behaviour match the skl+ reset value. 181 * 182 * CHICKEN_PIPESL_1[0]/BDW_UNMASK_VBL_TO_REGS_IN_SRD (bdw): 183 * CHICKEN_PIPESL_1[15]/HSW_UNMASK_VBL_TO_REGS_IN_SRD (hsw): 184 * 185 * On BDW without this bit is no vblanks whatsoever are 186 * generated after PSR exit. On HSW this has no apparent effect. 187 * WaPsrDPRSUnmaskVBlankInSRD says to set this. 188 * 189 * The rest of the bits are more self-explanatory and/or 190 * irrelevant for normal operation. 191 * 192 * Description of intel_crtc_state variables. has_psr, has_panel_replay and 193 * has_sel_update: 194 * 195 * has_psr (alone): PSR1 196 * has_psr + has_sel_update: PSR2 197 * has_psr + has_panel_replay: Panel Replay 198 * has_psr + has_panel_replay + has_sel_update: Panel Replay Selective Update 199 * 200 * Description of some intel_psr variables. enabled, panel_replay_enabled, 201 * sel_update_enabled 202 * 203 * enabled (alone): PSR1 204 * enabled + sel_update_enabled: PSR2 205 * enabled + panel_replay_enabled: Panel Replay 206 * enabled + panel_replay_enabled + sel_update_enabled: Panel Replay SU 207 */ 208 209 #define CAN_PSR(intel_dp) ((intel_dp)->psr.sink_support && \ 210 (intel_dp)->psr.source_support) 211 212 bool intel_encoder_can_psr(struct intel_encoder *encoder) 213 { 214 if (intel_encoder_is_dp(encoder) || encoder->type == INTEL_OUTPUT_DP_MST) 215 return CAN_PSR(enc_to_intel_dp(encoder)) || 216 CAN_PANEL_REPLAY(enc_to_intel_dp(encoder)); 217 else 218 return false; 219 } 220 221 bool intel_psr_needs_aux_io_power(struct intel_encoder *encoder, 222 const struct intel_crtc_state *crtc_state) 223 { 224 /* 225 * For PSR/PR modes only eDP requires the AUX IO power to be enabled whenever 226 * the output is enabled. For non-eDP outputs the main link is always 227 * on, hence it doesn't require the HW initiated AUX wake-up signaling used 228 * for eDP. 229 * 230 * TODO: 231 * - Consider leaving AUX IO disabled for eDP / PR as well, in case 232 * the ALPM with main-link off mode is not enabled. 233 * - Leave AUX IO enabled for DP / PR, once support for ALPM with 234 * main-link off mode is added for it and this mode gets enabled. 235 */ 236 return intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP) && 237 intel_encoder_can_psr(encoder); 238 } 239 240 static bool psr_global_enabled(struct intel_dp *intel_dp) 241 { 242 struct intel_connector *connector = intel_dp->attached_connector; 243 244 switch (intel_dp->psr.debug & I915_PSR_DEBUG_MODE_MASK) { 245 case I915_PSR_DEBUG_DEFAULT: 246 return intel_dp_is_edp(intel_dp) ? 247 connector->panel.vbt.psr.enable : true; 248 case I915_PSR_DEBUG_DISABLE: 249 return false; 250 default: 251 return true; 252 } 253 } 254 255 static bool sel_update_global_enabled(struct intel_dp *intel_dp) 256 { 257 switch (intel_dp->psr.debug & I915_PSR_DEBUG_MODE_MASK) { 258 case I915_PSR_DEBUG_DISABLE: 259 case I915_PSR_DEBUG_FORCE_PSR1: 260 return false; 261 default: 262 return true; 263 } 264 } 265 266 static bool panel_replay_global_enabled(struct intel_dp *intel_dp) 267 { 268 struct intel_display *display = to_intel_display(intel_dp); 269 270 return !(intel_dp->psr.debug & I915_PSR_DEBUG_PANEL_REPLAY_DISABLE) && 271 display->params.enable_panel_replay; 272 } 273 274 static u32 psr_irq_psr_error_bit_get(struct intel_dp *intel_dp) 275 { 276 struct intel_display *display = to_intel_display(intel_dp); 277 278 return DISPLAY_VER(display) >= 12 ? TGL_PSR_ERROR : 279 EDP_PSR_ERROR(intel_dp->psr.transcoder); 280 } 281 282 static u32 psr_irq_post_exit_bit_get(struct intel_dp *intel_dp) 283 { 284 struct intel_display *display = to_intel_display(intel_dp); 285 286 return DISPLAY_VER(display) >= 12 ? TGL_PSR_POST_EXIT : 287 EDP_PSR_POST_EXIT(intel_dp->psr.transcoder); 288 } 289 290 static u32 psr_irq_pre_entry_bit_get(struct intel_dp *intel_dp) 291 { 292 struct intel_display *display = to_intel_display(intel_dp); 293 294 return DISPLAY_VER(display) >= 12 ? TGL_PSR_PRE_ENTRY : 295 EDP_PSR_PRE_ENTRY(intel_dp->psr.transcoder); 296 } 297 298 static u32 psr_irq_mask_get(struct intel_dp *intel_dp) 299 { 300 struct intel_display *display = to_intel_display(intel_dp); 301 302 return DISPLAY_VER(display) >= 12 ? TGL_PSR_MASK : 303 EDP_PSR_MASK(intel_dp->psr.transcoder); 304 } 305 306 static intel_reg_t psr_ctl_reg(struct intel_display *display, 307 enum transcoder cpu_transcoder) 308 { 309 if (DISPLAY_VER(display) >= 8) 310 return EDP_PSR_CTL(display, cpu_transcoder); 311 else 312 return HSW_SRD_CTL; 313 } 314 315 static intel_reg_t psr_debug_reg(struct intel_display *display, 316 enum transcoder cpu_transcoder) 317 { 318 if (DISPLAY_VER(display) >= 8) 319 return EDP_PSR_DEBUG(display, cpu_transcoder); 320 else 321 return HSW_SRD_DEBUG; 322 } 323 324 static intel_reg_t psr_perf_cnt_reg(struct intel_display *display, 325 enum transcoder cpu_transcoder) 326 { 327 if (DISPLAY_VER(display) >= 8) 328 return EDP_PSR_PERF_CNT(display, cpu_transcoder); 329 else 330 return HSW_SRD_PERF_CNT; 331 } 332 333 static intel_reg_t psr_status_reg(struct intel_display *display, 334 enum transcoder cpu_transcoder) 335 { 336 if (DISPLAY_VER(display) >= 8) 337 return EDP_PSR_STATUS(display, cpu_transcoder); 338 else 339 return HSW_SRD_STATUS; 340 } 341 342 static intel_reg_t psr_imr_reg(struct intel_display *display, 343 enum transcoder cpu_transcoder) 344 { 345 if (DISPLAY_VER(display) >= 12) 346 return TRANS_PSR_IMR(display, cpu_transcoder); 347 else 348 return EDP_PSR_IMR; 349 } 350 351 static intel_reg_t psr_iir_reg(struct intel_display *display, 352 enum transcoder cpu_transcoder) 353 { 354 if (DISPLAY_VER(display) >= 12) 355 return TRANS_PSR_IIR(display, cpu_transcoder); 356 else 357 return EDP_PSR_IIR; 358 } 359 360 static intel_reg_t psr_aux_ctl_reg(struct intel_display *display, 361 enum transcoder cpu_transcoder) 362 { 363 if (DISPLAY_VER(display) >= 8) 364 return EDP_PSR_AUX_CTL(display, cpu_transcoder); 365 else 366 return HSW_SRD_AUX_CTL; 367 } 368 369 static intel_reg_t psr_aux_data_reg(struct intel_display *display, 370 enum transcoder cpu_transcoder, int i) 371 { 372 if (DISPLAY_VER(display) >= 8) 373 return EDP_PSR_AUX_DATA(display, cpu_transcoder, i); 374 else 375 return HSW_SRD_AUX_DATA(i); 376 } 377 378 static void psr_irq_control(struct intel_dp *intel_dp) 379 { 380 struct intel_display *display = to_intel_display(intel_dp); 381 enum transcoder cpu_transcoder = intel_dp->psr.transcoder; 382 u32 mask; 383 384 if (intel_dp->psr.panel_replay_enabled) 385 return; 386 387 mask = psr_irq_psr_error_bit_get(intel_dp); 388 if (intel_dp->psr.debug & I915_PSR_DEBUG_IRQ) 389 mask |= psr_irq_post_exit_bit_get(intel_dp) | 390 psr_irq_pre_entry_bit_get(intel_dp); 391 392 intel_de_rmw(display, psr_imr_reg(display, cpu_transcoder), 393 psr_irq_mask_get(intel_dp), ~mask); 394 } 395 396 static void psr_event_print(struct intel_display *display, 397 u32 val, bool sel_update_enabled) 398 { 399 drm_dbg_kms(display->drm, "PSR exit events: 0x%x\n", val); 400 if (val & PSR_EVENT_PSR2_WD_TIMER_EXPIRE) 401 drm_dbg_kms(display->drm, "\tPSR2 watchdog timer expired\n"); 402 if ((val & PSR_EVENT_PSR2_DISABLED) && sel_update_enabled) 403 drm_dbg_kms(display->drm, "\tPSR2 disabled\n"); 404 if (val & PSR_EVENT_SU_DIRTY_FIFO_UNDERRUN) 405 drm_dbg_kms(display->drm, "\tSU dirty FIFO underrun\n"); 406 if (val & PSR_EVENT_SU_CRC_FIFO_UNDERRUN) 407 drm_dbg_kms(display->drm, "\tSU CRC FIFO underrun\n"); 408 if (val & PSR_EVENT_GRAPHICS_RESET) 409 drm_dbg_kms(display->drm, "\tGraphics reset\n"); 410 if (val & PSR_EVENT_PCH_INTERRUPT) 411 drm_dbg_kms(display->drm, "\tPCH interrupt\n"); 412 if (val & PSR_EVENT_MEMORY_UP) 413 drm_dbg_kms(display->drm, "\tMemory up\n"); 414 if (val & PSR_EVENT_FRONT_BUFFER_MODIFY) 415 drm_dbg_kms(display->drm, "\tFront buffer modification\n"); 416 if (val & PSR_EVENT_WD_TIMER_EXPIRE) 417 drm_dbg_kms(display->drm, "\tPSR watchdog timer expired\n"); 418 if (val & PSR_EVENT_PIPE_REGISTERS_UPDATE) 419 drm_dbg_kms(display->drm, "\tPIPE registers updated\n"); 420 if (val & PSR_EVENT_REGISTER_UPDATE) 421 drm_dbg_kms(display->drm, "\tRegister updated\n"); 422 if (val & PSR_EVENT_HDCP_ENABLE) 423 drm_dbg_kms(display->drm, "\tHDCP enabled\n"); 424 if (val & PSR_EVENT_KVMR_SESSION_ENABLE) 425 drm_dbg_kms(display->drm, "\tKVMR session enabled\n"); 426 if (val & PSR_EVENT_VBI_ENABLE) 427 drm_dbg_kms(display->drm, "\tVBI enabled\n"); 428 if (val & PSR_EVENT_LPSP_MODE_EXIT) 429 drm_dbg_kms(display->drm, "\tLPSP mode exited\n"); 430 if ((val & PSR_EVENT_PSR_DISABLE) && !sel_update_enabled) 431 drm_dbg_kms(display->drm, "\tPSR disabled\n"); 432 } 433 434 void intel_psr_irq_handler(struct intel_dp *intel_dp, u32 psr_iir) 435 { 436 struct intel_display *display = to_intel_display(intel_dp); 437 enum transcoder cpu_transcoder = intel_dp->psr.transcoder; 438 ktime_t time_ns = ktime_get(); 439 440 if (psr_iir & psr_irq_pre_entry_bit_get(intel_dp)) { 441 intel_dp->psr.last_entry_attempt = time_ns; 442 drm_dbg_kms(display->drm, 443 "[transcoder %s] PSR entry attempt in 2 vblanks\n", 444 transcoder_name(cpu_transcoder)); 445 } 446 447 if (psr_iir & psr_irq_post_exit_bit_get(intel_dp)) { 448 intel_dp->psr.last_exit = time_ns; 449 drm_dbg_kms(display->drm, 450 "[transcoder %s] PSR exit completed\n", 451 transcoder_name(cpu_transcoder)); 452 453 if (DISPLAY_VER(display) >= 9) { 454 u32 val; 455 456 val = intel_de_rmw(display, 457 PSR_EVENT(display, cpu_transcoder), 458 0, 0); 459 460 psr_event_print(display, val, intel_dp->psr.sel_update_enabled); 461 } 462 } 463 464 if (psr_iir & psr_irq_psr_error_bit_get(intel_dp)) { 465 drm_warn(display->drm, "[transcoder %s] PSR aux error\n", 466 transcoder_name(cpu_transcoder)); 467 468 intel_dp->psr.irq_aux_error = true; 469 470 /* 471 * If this interruption is not masked it will keep 472 * interrupting so fast that it prevents the scheduled 473 * work to run. 474 * Also after a PSR error, we don't want to arm PSR 475 * again so we don't care about unmask the interruption 476 * or unset irq_aux_error. 477 */ 478 intel_de_rmw(display, psr_imr_reg(display, cpu_transcoder), 479 0, psr_irq_psr_error_bit_get(intel_dp)); 480 481 queue_work(display->wq.unordered, &intel_dp->psr.work); 482 } 483 } 484 485 static u8 intel_dp_get_sink_sync_latency(struct intel_dp *intel_dp) 486 { 487 struct intel_display *display = to_intel_display(intel_dp); 488 u8 val = 8; /* assume the worst if we can't read the value */ 489 490 if (drm_dp_dpcd_readb(&intel_dp->aux, 491 DP_SYNCHRONIZATION_LATENCY_IN_SINK, &val) == 1) 492 val &= DP_MAX_RESYNC_FRAME_COUNT_MASK; 493 else 494 drm_dbg_kms(display->drm, 495 "Unable to get sink synchronization latency, assuming 8 frames\n"); 496 return val; 497 } 498 499 static void _psr_compute_su_granularity(struct intel_dp *intel_dp, 500 struct intel_connector *connector) 501 { 502 struct intel_display *display = to_intel_display(intel_dp); 503 ssize_t r; 504 __le16 w; 505 u8 y; 506 507 /* 508 * If sink don't have specific granularity requirements set legacy 509 * ones. 510 */ 511 if (!(connector->dp.psr_caps.dpcd[1] & DP_PSR2_SU_GRANULARITY_REQUIRED)) { 512 /* As PSR2 HW sends full lines, we do not care about x granularity */ 513 w = cpu_to_le16(4); 514 y = 4; 515 goto exit; 516 } 517 518 r = drm_dp_dpcd_read(&intel_dp->aux, DP_PSR2_SU_X_GRANULARITY, &w, sizeof(w)); 519 if (r != sizeof(w)) 520 drm_dbg_kms(display->drm, 521 "Unable to read selective update x granularity\n"); 522 /* 523 * Spec says that if the value read is 0 the default granularity should 524 * be used instead. 525 */ 526 if (r != sizeof(w) || w == 0) 527 w = cpu_to_le16(4); 528 529 r = drm_dp_dpcd_read(&intel_dp->aux, DP_PSR2_SU_Y_GRANULARITY, &y, 1); 530 if (r != 1) { 531 drm_dbg_kms(display->drm, 532 "Unable to read selective update y granularity\n"); 533 y = 4; 534 } 535 if (y == 0) 536 y = 1; 537 538 exit: 539 connector->dp.psr_caps.su_w_granularity = le16_to_cpu(w); 540 connector->dp.psr_caps.su_y_granularity = y; 541 } 542 543 static enum intel_panel_replay_dsc_support 544 compute_pr_dsc_support(struct intel_connector *connector) 545 { 546 u8 pr_dsc_mode; 547 u8 val; 548 549 val = connector->dp.panel_replay_caps.dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_CAPABILITY)]; 550 pr_dsc_mode = REG_FIELD_GET8(DP_PANEL_REPLAY_DSC_DECODE_CAPABILITY_IN_PR_MASK, val); 551 552 switch (pr_dsc_mode) { 553 case DP_DSC_DECODE_CAPABILITY_IN_PR_FULL_FRAME_ONLY: 554 return INTEL_DP_PANEL_REPLAY_DSC_FULL_FRAME_ONLY; 555 case DP_DSC_DECODE_CAPABILITY_IN_PR_SUPPORTED: 556 return INTEL_DP_PANEL_REPLAY_DSC_SELECTIVE_UPDATE; 557 default: 558 MISSING_CASE(pr_dsc_mode); 559 fallthrough; 560 case DP_DSC_DECODE_CAPABILITY_IN_PR_NOT_SUPPORTED: 561 case DP_DSC_DECODE_CAPABILITY_IN_PR_RESERVED: 562 return INTEL_DP_PANEL_REPLAY_DSC_NOT_SUPPORTED; 563 } 564 } 565 566 static const char *panel_replay_dsc_support_str(enum intel_panel_replay_dsc_support dsc_support) 567 { 568 switch (dsc_support) { 569 case INTEL_DP_PANEL_REPLAY_DSC_NOT_SUPPORTED: 570 return "not supported"; 571 case INTEL_DP_PANEL_REPLAY_DSC_FULL_FRAME_ONLY: 572 return "full frame only"; 573 case INTEL_DP_PANEL_REPLAY_DSC_SELECTIVE_UPDATE: 574 return "selective update"; 575 default: 576 MISSING_CASE(dsc_support); 577 return "n/a"; 578 }; 579 } 580 581 static void _panel_replay_compute_su_granularity(struct intel_connector *connector) 582 { 583 u16 w; 584 u8 y; 585 586 if (!(connector->dp.panel_replay_caps.dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_CAPABILITY)] & 587 DP_PANEL_REPLAY_SU_GRANULARITY_REQUIRED)) { 588 w = 4; 589 y = 4; 590 goto exit; 591 } 592 593 /* 594 * Spec says that if the value read is 0 the default granularity should 595 * be used instead. 596 */ 597 w = le16_to_cpu(*(__le16 *)&connector->dp.panel_replay_caps.dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_X_GRANULARITY)]) ? : 4; 598 y = connector->dp.panel_replay_caps.dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_Y_GRANULARITY)] ? : 1; 599 600 exit: 601 connector->dp.panel_replay_caps.su_w_granularity = w; 602 connector->dp.panel_replay_caps.su_y_granularity = y; 603 } 604 605 static void _panel_replay_init_dpcd(struct intel_dp *intel_dp, struct intel_connector *connector) 606 { 607 struct intel_display *display = to_intel_display(intel_dp); 608 int ret; 609 610 /* TODO: Enable Panel Replay on MST once it's properly implemented. */ 611 if (intel_dp->mst_detect == DRM_DP_MST) 612 return; 613 614 if (intel_dp_is_edp(intel_dp) && 615 intel_has_dpcd_quirk(intel_dp, QUIRK_DISABLE_EDP_PANEL_REPLAY)) { 616 drm_dbg_kms(display->drm, 617 "Panel Replay support not currently available for this setup\n"); 618 return; 619 } 620 621 ret = drm_dp_dpcd_read_data(&intel_dp->aux, DP_PANEL_REPLAY_CAP_SUPPORT, 622 &connector->dp.panel_replay_caps.dpcd, 623 sizeof(connector->dp.panel_replay_caps.dpcd)); 624 if (ret < 0) 625 return; 626 627 if (!(connector->dp.panel_replay_caps.dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_SUPPORT)] & 628 DP_PANEL_REPLAY_SUPPORT)) 629 return; 630 631 if (intel_dp_is_edp(intel_dp)) { 632 if (!intel_alpm_aux_less_wake_supported(intel_dp)) { 633 drm_dbg_kms(display->drm, 634 "Panel doesn't support AUX-less ALPM, eDP Panel Replay not possible\n"); 635 return; 636 } 637 638 if (!(connector->dp.panel_replay_caps.dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_SUPPORT)] & 639 DP_PANEL_REPLAY_EARLY_TRANSPORT_SUPPORT)) { 640 drm_dbg_kms(display->drm, 641 "Panel doesn't support early transport, eDP Panel Replay not possible\n"); 642 return; 643 } 644 } 645 646 connector->dp.panel_replay_caps.support = true; 647 intel_dp->psr.sink_panel_replay_support = true; 648 649 if (connector->dp.panel_replay_caps.dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_SUPPORT)] & 650 DP_PANEL_REPLAY_SU_SUPPORT) { 651 connector->dp.panel_replay_caps.su_support = true; 652 653 _panel_replay_compute_su_granularity(connector); 654 } 655 656 connector->dp.panel_replay_caps.dsc_support = compute_pr_dsc_support(connector); 657 658 drm_dbg_kms(display->drm, 659 "Panel replay %sis supported by panel (in DSC mode: %s)\n", 660 connector->dp.panel_replay_caps.su_support ? 661 "selective_update " : "", 662 panel_replay_dsc_support_str(connector->dp.panel_replay_caps.dsc_support)); 663 } 664 665 static void _psr_init_dpcd(struct intel_dp *intel_dp, struct intel_connector *connector) 666 { 667 struct intel_display *display = to_intel_display(intel_dp); 668 int ret; 669 670 ret = drm_dp_dpcd_read_data(&intel_dp->aux, DP_PSR_SUPPORT, connector->dp.psr_caps.dpcd, 671 sizeof(connector->dp.psr_caps.dpcd)); 672 if (ret < 0) 673 return; 674 675 if (!connector->dp.psr_caps.dpcd[0]) 676 return; 677 678 drm_dbg_kms(display->drm, "eDP panel supports PSR version %x\n", 679 connector->dp.psr_caps.dpcd[0]); 680 681 if (drm_dp_has_quirk(&intel_dp->desc, DP_DPCD_QUIRK_NO_PSR)) { 682 drm_dbg_kms(display->drm, 683 "PSR support not currently available for this panel\n"); 684 return; 685 } 686 687 if (!(intel_dp->edp_dpcd[1] & DP_EDP_SET_POWER_CAP)) { 688 drm_dbg_kms(display->drm, 689 "Panel lacks power state control, PSR cannot be enabled\n"); 690 return; 691 } 692 693 connector->dp.psr_caps.support = true; 694 intel_dp->psr.sink_support = true; 695 696 connector->dp.psr_caps.sync_latency = intel_dp_get_sink_sync_latency(intel_dp); 697 698 if (intel_has_quirk(display, QUIRK_DISABLE_PSR2)) 699 return; 700 701 if (DISPLAY_VER(display) >= 9 && 702 connector->dp.psr_caps.dpcd[0] >= DP_PSR2_WITH_Y_COORD_IS_SUPPORTED) { 703 bool y_req = connector->dp.psr_caps.dpcd[1] & 704 DP_PSR2_SU_Y_COORDINATE_REQUIRED; 705 706 /* 707 * All panels that supports PSR version 03h (PSR2 + 708 * Y-coordinate) can handle Y-coordinates in VSC but we are 709 * only sure that it is going to be used when required by the 710 * panel. This way panel is capable to do selective update 711 * without a aux frame sync. 712 * 713 * To support PSR version 02h and PSR version 03h without 714 * Y-coordinate requirement panels we would need to enable 715 * GTC first. 716 */ 717 connector->dp.psr_caps.su_support = y_req && 718 intel_alpm_aux_wake_supported(intel_dp); 719 drm_dbg_kms(display->drm, "PSR2 %ssupported\n", 720 connector->dp.psr_caps.su_support ? "" : "not "); 721 } 722 723 if (connector->dp.psr_caps.su_support) 724 _psr_compute_su_granularity(intel_dp, connector); 725 } 726 727 void intel_psr_init_dpcd(struct intel_dp *intel_dp, struct intel_connector *connector) 728 { 729 _psr_init_dpcd(intel_dp, connector); 730 731 _panel_replay_init_dpcd(intel_dp, connector); 732 } 733 734 static void hsw_psr_setup_aux(struct intel_dp *intel_dp) 735 { 736 struct intel_display *display = to_intel_display(intel_dp); 737 enum transcoder cpu_transcoder = intel_dp->psr.transcoder; 738 u32 aux_clock_divider, aux_ctl; 739 /* write DP_SET_POWER=D0 */ 740 static const u8 aux_msg[] = { 741 [0] = (DP_AUX_NATIVE_WRITE << 4) | ((DP_SET_POWER >> 16) & 0xf), 742 [1] = (DP_SET_POWER >> 8) & 0xff, 743 [2] = DP_SET_POWER & 0xff, 744 [3] = 1 - 1, 745 [4] = DP_SET_POWER_D0, 746 }; 747 int i; 748 749 BUILD_BUG_ON(sizeof(aux_msg) > 20); 750 for (i = 0; i < sizeof(aux_msg); i += 4) 751 intel_de_write(display, 752 psr_aux_data_reg(display, cpu_transcoder, i >> 2), 753 intel_dp_aux_pack(&aux_msg[i], sizeof(aux_msg) - i)); 754 755 aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, 0); 756 757 /* Start with bits set for DDI_AUX_CTL register */ 758 aux_ctl = intel_dp->get_aux_send_ctl(intel_dp, sizeof(aux_msg), 759 aux_clock_divider); 760 761 /* Select only valid bits for SRD_AUX_CTL */ 762 aux_ctl &= EDP_PSR_AUX_CTL_TIME_OUT_MASK | 763 EDP_PSR_AUX_CTL_MESSAGE_SIZE_MASK | 764 EDP_PSR_AUX_CTL_PRECHARGE_2US_MASK | 765 EDP_PSR_AUX_CTL_BIT_CLOCK_2X_MASK; 766 767 intel_de_write(display, psr_aux_ctl_reg(display, cpu_transcoder), 768 aux_ctl); 769 } 770 771 static bool psr2_su_region_et_valid(struct intel_connector *connector, bool panel_replay) 772 { 773 struct intel_dp *intel_dp = intel_attached_dp(connector); 774 struct intel_display *display = to_intel_display(intel_dp); 775 776 if (DISPLAY_VER(display) < 20 || !intel_dp_is_edp(intel_dp) || 777 intel_dp->psr.debug & I915_PSR_DEBUG_SU_REGION_ET_DISABLE) 778 return false; 779 780 return panel_replay ? 781 connector->dp.panel_replay_caps.dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_SUPPORT)] & 782 DP_PANEL_REPLAY_EARLY_TRANSPORT_SUPPORT : 783 connector->dp.psr_caps.dpcd[0] == DP_PSR2_WITH_Y_COORD_ET_SUPPORTED; 784 } 785 786 static void _panel_replay_enable_sink(struct intel_dp *intel_dp, 787 const struct intel_crtc_state *crtc_state) 788 { 789 u8 val = DP_PANEL_REPLAY_ENABLE | 790 DP_PANEL_REPLAY_VSC_SDP_CRC_EN | 791 DP_PANEL_REPLAY_UNRECOVERABLE_ERROR_EN | 792 DP_PANEL_REPLAY_RFB_STORAGE_ERROR_EN | 793 DP_PANEL_REPLAY_ACTIVE_FRAME_CRC_ERROR_EN; 794 u8 panel_replay_config2 = DP_PANEL_REPLAY_CRC_VERIFICATION; 795 796 if (crtc_state->has_sel_update) 797 val |= DP_PANEL_REPLAY_SU_ENABLE; 798 799 if (crtc_state->enable_psr2_su_region_et) 800 val |= DP_PANEL_REPLAY_ENABLE_SU_REGION_ET; 801 802 if (crtc_state->req_psr2_sdp_prior_scanline) 803 panel_replay_config2 |= 804 DP_PANEL_REPLAY_SU_REGION_SCANLINE_CAPTURE; 805 806 drm_dp_dpcd_writeb(&intel_dp->aux, PANEL_REPLAY_CONFIG, val); 807 808 drm_dp_dpcd_writeb(&intel_dp->aux, PANEL_REPLAY_CONFIG2, 809 panel_replay_config2); 810 } 811 812 static void _psr_enable_sink(struct intel_dp *intel_dp, 813 const struct intel_crtc_state *crtc_state) 814 { 815 struct intel_display *display = to_intel_display(intel_dp); 816 u8 val = 0; 817 818 if (crtc_state->has_sel_update) { 819 val |= DP_PSR_ENABLE_PSR2 | DP_PSR_IRQ_HPD_WITH_CRC_ERRORS; 820 } else { 821 if (intel_dp->psr.link_standby) 822 val |= DP_PSR_MAIN_LINK_ACTIVE; 823 824 if (DISPLAY_VER(display) >= 8) 825 val |= DP_PSR_CRC_VERIFICATION; 826 } 827 828 if (crtc_state->req_psr2_sdp_prior_scanline) 829 val |= DP_PSR_SU_REGION_SCANLINE_CAPTURE; 830 831 if (crtc_state->enable_psr2_su_region_et) 832 val |= DP_PANEL_REPLAY_ENABLE_SU_REGION_ET; 833 834 if (intel_dp->psr.entry_setup_frames > 0) 835 val |= DP_PSR_FRAME_CAPTURE; 836 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, val); 837 838 val |= DP_PSR_ENABLE; 839 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, val); 840 } 841 842 static void intel_psr_enable_sink(struct intel_dp *intel_dp, 843 const struct intel_crtc_state *crtc_state) 844 { 845 intel_alpm_enable_sink(intel_dp, crtc_state); 846 847 crtc_state->has_panel_replay ? 848 _panel_replay_enable_sink(intel_dp, crtc_state) : 849 _psr_enable_sink(intel_dp, crtc_state); 850 851 if (intel_dp_is_edp(intel_dp)) 852 drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, DP_SET_POWER_D0); 853 } 854 855 void intel_psr_panel_replay_enable_sink(struct intel_dp *intel_dp) 856 { 857 /* 858 * NOTE: We might want to trigger mode set when 859 * disabling/enabling Panel Replay via debugfs interface to 860 * ensure this bit is cleared/set accordingly. 861 */ 862 if (CAN_PANEL_REPLAY(intel_dp) && panel_replay_global_enabled(intel_dp)) 863 drm_dp_dpcd_writeb(&intel_dp->aux, PANEL_REPLAY_CONFIG, 864 DP_PANEL_REPLAY_ENABLE); 865 } 866 867 static u32 intel_psr1_get_tp_time(struct intel_dp *intel_dp) 868 { 869 struct intel_display *display = to_intel_display(intel_dp); 870 struct intel_connector *connector = intel_dp->attached_connector; 871 u32 val = 0; 872 873 if (DISPLAY_VER(display) >= 11) 874 val |= EDP_PSR_TP4_TIME_0us; 875 876 if (display->params.psr_safest_params) { 877 val |= EDP_PSR_TP1_TIME_2500us; 878 val |= EDP_PSR_TP2_TP3_TIME_2500us; 879 goto check_tp3_sel; 880 } 881 882 if (connector->panel.vbt.psr.tp1_wakeup_time_us == 0) 883 val |= EDP_PSR_TP1_TIME_0us; 884 else if (connector->panel.vbt.psr.tp1_wakeup_time_us <= 100) 885 val |= EDP_PSR_TP1_TIME_100us; 886 else if (connector->panel.vbt.psr.tp1_wakeup_time_us <= 500) 887 val |= EDP_PSR_TP1_TIME_500us; 888 else 889 val |= EDP_PSR_TP1_TIME_2500us; 890 891 if (connector->panel.vbt.psr.tp2_tp3_wakeup_time_us == 0) 892 val |= EDP_PSR_TP2_TP3_TIME_0us; 893 else if (connector->panel.vbt.psr.tp2_tp3_wakeup_time_us <= 100) 894 val |= EDP_PSR_TP2_TP3_TIME_100us; 895 else if (connector->panel.vbt.psr.tp2_tp3_wakeup_time_us <= 500) 896 val |= EDP_PSR_TP2_TP3_TIME_500us; 897 else 898 val |= EDP_PSR_TP2_TP3_TIME_2500us; 899 900 /* 901 * WA 0479: hsw,bdw 902 * "Do not skip both TP1 and TP2/TP3" 903 */ 904 if (DISPLAY_VER(display) < 9 && 905 connector->panel.vbt.psr.tp1_wakeup_time_us == 0 && 906 connector->panel.vbt.psr.tp2_tp3_wakeup_time_us == 0) 907 val |= EDP_PSR_TP2_TP3_TIME_100us; 908 909 check_tp3_sel: 910 if (intel_dp_source_supports_tps3(display) && 911 drm_dp_tps3_supported(intel_dp->dpcd)) 912 val |= EDP_PSR_TP_TP1_TP3; 913 else 914 val |= EDP_PSR_TP_TP1_TP2; 915 916 return val; 917 } 918 919 static u8 psr_compute_idle_frames(struct intel_dp *intel_dp) 920 { 921 struct intel_display *display = to_intel_display(intel_dp); 922 struct intel_connector *connector = intel_dp->attached_connector; 923 int idle_frames; 924 925 /* Let's use 6 as the minimum to cover all known cases including the 926 * off-by-one issue that HW has in some cases. 927 */ 928 idle_frames = max(6, connector->panel.vbt.psr.idle_frames); 929 idle_frames = max(idle_frames, connector->dp.psr_caps.sync_latency + 1); 930 931 if (drm_WARN_ON(display->drm, idle_frames > 0xf)) 932 idle_frames = 0xf; 933 934 return idle_frames; 935 } 936 937 static bool is_dc5_dc6_blocked(struct intel_dp *intel_dp) 938 { 939 struct intel_display *display = to_intel_display(intel_dp); 940 u32 current_dc_state = intel_display_power_get_current_dc_state(display); 941 struct intel_crtc *crtc = intel_crtc_for_pipe(display, intel_dp->psr.pipe); 942 struct drm_vblank_crtc *vblank = drm_crtc_vblank_crtc(&crtc->base); 943 944 return (current_dc_state != DC_STATE_EN_UPTO_DC5 && 945 current_dc_state != DC_STATE_EN_UPTO_DC6) || 946 intel_dp->psr.active_non_psr_pipes || 947 READ_ONCE(vblank->enabled); 948 } 949 950 static void hsw_activate_psr1(struct intel_dp *intel_dp) 951 { 952 struct intel_display *display = to_intel_display(intel_dp); 953 enum transcoder cpu_transcoder = intel_dp->psr.transcoder; 954 u32 max_sleep_time = 0x1f; 955 u32 val = EDP_PSR_ENABLE; 956 957 val |= EDP_PSR_IDLE_FRAMES(psr_compute_idle_frames(intel_dp)); 958 959 if (DISPLAY_VER(display) < 20) 960 val |= EDP_PSR_MAX_SLEEP_TIME(max_sleep_time); 961 962 if (display->platform.haswell) 963 val |= EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES; 964 965 if (intel_dp->psr.link_standby) 966 val |= EDP_PSR_LINK_STANDBY; 967 968 val |= intel_psr1_get_tp_time(intel_dp); 969 970 if (DISPLAY_VER(display) >= 8) 971 val |= EDP_PSR_CRC_ENABLE; 972 973 if (DISPLAY_VER(display) >= 20) 974 val |= LNL_EDP_PSR_ENTRY_SETUP_FRAMES(intel_dp->psr.entry_setup_frames); 975 976 intel_de_rmw(display, psr_ctl_reg(display, cpu_transcoder), 977 ~EDP_PSR_RESTORE_PSR_ACTIVE_CTX_MASK, val); 978 979 /* Wa_16025596647 */ 980 if ((DISPLAY_VER(display) == 20 || 981 IS_DISPLAY_VERx100_STEP(display, 3000, STEP_A0, STEP_B0)) && 982 is_dc5_dc6_blocked(intel_dp) && intel_dp->psr.pkg_c_latency_used) 983 intel_dmc_start_pkgc_exit_at_start_of_undelayed_vblank(display, 984 intel_dp->psr.pipe, 985 true); 986 } 987 988 static u32 intel_psr2_get_tp_time(struct intel_dp *intel_dp) 989 { 990 struct intel_display *display = to_intel_display(intel_dp); 991 struct intel_connector *connector = intel_dp->attached_connector; 992 u32 val = 0; 993 994 if (display->params.psr_safest_params) 995 return EDP_PSR2_TP2_TIME_2500us; 996 997 if (connector->panel.vbt.psr.psr2_tp2_tp3_wakeup_time_us >= 0 && 998 connector->panel.vbt.psr.psr2_tp2_tp3_wakeup_time_us <= 50) 999 val |= EDP_PSR2_TP2_TIME_50us; 1000 else if (connector->panel.vbt.psr.psr2_tp2_tp3_wakeup_time_us <= 100) 1001 val |= EDP_PSR2_TP2_TIME_100us; 1002 else if (connector->panel.vbt.psr.psr2_tp2_tp3_wakeup_time_us <= 500) 1003 val |= EDP_PSR2_TP2_TIME_500us; 1004 else 1005 val |= EDP_PSR2_TP2_TIME_2500us; 1006 1007 return val; 1008 } 1009 1010 static int 1011 psr2_block_count_lines(u8 io_wake_lines, u8 fast_wake_lines) 1012 { 1013 return io_wake_lines < 9 && fast_wake_lines < 9 ? 8 : 12; 1014 } 1015 1016 static int psr2_block_count(struct intel_dp *intel_dp) 1017 { 1018 return psr2_block_count_lines(intel_dp->psr.io_wake_lines, 1019 intel_dp->psr.fast_wake_lines) / 4; 1020 } 1021 1022 static u8 frames_before_su_entry(struct intel_dp *intel_dp) 1023 { 1024 struct intel_connector *connector = intel_dp->attached_connector; 1025 u8 frames_before_su_entry; 1026 1027 frames_before_su_entry = max_t(u8, 1028 connector->dp.psr_caps.sync_latency + 1, 1029 2); 1030 1031 /* Entry setup frames must be at least 1 less than frames before SU entry */ 1032 if (intel_dp->psr.entry_setup_frames >= frames_before_su_entry) 1033 frames_before_su_entry = intel_dp->psr.entry_setup_frames + 1; 1034 1035 return frames_before_su_entry; 1036 } 1037 1038 static bool intel_psr_allow_pr_bw_optimization(struct intel_dp *intel_dp) 1039 { 1040 if (intel_dp_is_edp(intel_dp)) 1041 return false; 1042 1043 if (!intel_dp_tunnel_bw_alloc_is_enabled(intel_dp)) 1044 return false; 1045 1046 if (!intel_dp_tunnel_pr_optimization_supported(intel_dp)) 1047 return false; 1048 1049 return true; 1050 } 1051 1052 static void dg2_activate_panel_replay(struct intel_dp *intel_dp) 1053 { 1054 struct intel_display *display = to_intel_display(intel_dp); 1055 struct intel_psr *psr = &intel_dp->psr; 1056 enum transcoder cpu_transcoder = intel_dp->psr.transcoder; 1057 u32 dp2_ctl_set = TRANS_DP2_PANEL_REPLAY_ENABLE; 1058 u32 dp2_ctl_clear = 0; 1059 1060 if (intel_dp_is_edp(intel_dp) && psr->sel_update_enabled) { 1061 u32 val = psr->su_region_et_enabled ? 1062 LNL_EDP_PSR2_SU_REGION_ET_ENABLE : 0; 1063 1064 if (intel_dp->psr.req_psr2_sdp_prior_scanline) 1065 val |= EDP_PSR2_SU_SDP_SCANLINE; 1066 1067 intel_de_write(display, EDP_PSR2_CTL(display, cpu_transcoder), 1068 val); 1069 } 1070 1071 if (intel_psr_allow_pr_bw_optimization(intel_dp)) 1072 dp2_ctl_set |= TRANS_DP2_PR_TUNNELING_ENABLE; 1073 else 1074 dp2_ctl_clear = TRANS_DP2_PR_TUNNELING_ENABLE; 1075 1076 intel_de_rmw(display, 1077 PSR2_MAN_TRK_CTL(display, intel_dp->psr.transcoder), 1078 0, ADLP_PSR2_MAN_TRK_CTL_SF_CONTINUOS_FULL_FRAME); 1079 1080 intel_de_rmw(display, TRANS_DP2_CTL(intel_dp->psr.transcoder), dp2_ctl_clear, dp2_ctl_set); 1081 } 1082 1083 static void hsw_activate_psr2(struct intel_dp *intel_dp) 1084 { 1085 struct intel_display *display = to_intel_display(intel_dp); 1086 enum transcoder cpu_transcoder = intel_dp->psr.transcoder; 1087 u32 val = EDP_PSR2_ENABLE; 1088 u32 psr_val = 0; 1089 u8 idle_frames; 1090 1091 /* Wa_16025596647 */ 1092 if ((DISPLAY_VER(display) == 20 || 1093 IS_DISPLAY_VERx100_STEP(display, 3000, STEP_A0, STEP_B0)) && 1094 is_dc5_dc6_blocked(intel_dp) && intel_dp->psr.pkg_c_latency_used) 1095 idle_frames = 0; 1096 else 1097 idle_frames = psr_compute_idle_frames(intel_dp); 1098 val |= EDP_PSR2_IDLE_FRAMES(idle_frames); 1099 1100 if (DISPLAY_VER(display) < 14 && !display->platform.alderlake_p) 1101 val |= EDP_SU_TRACK_ENABLE; 1102 1103 if (DISPLAY_VER(display) >= 10 && DISPLAY_VER(display) < 13) 1104 val |= EDP_Y_COORDINATE_ENABLE; 1105 1106 val |= EDP_PSR2_FRAME_BEFORE_SU(frames_before_su_entry(intel_dp)); 1107 1108 val |= intel_psr2_get_tp_time(intel_dp); 1109 1110 if (DISPLAY_VER(display) >= 12 && DISPLAY_VER(display) < 20) { 1111 if (psr2_block_count(intel_dp) > 2) 1112 val |= TGL_EDP_PSR2_BLOCK_COUNT_NUM_3; 1113 else 1114 val |= TGL_EDP_PSR2_BLOCK_COUNT_NUM_2; 1115 } 1116 1117 /* Wa_22012278275:adl-p */ 1118 if (intel_display_wa(display, INTEL_DISPLAY_WA_22012278275)) { 1119 static const u8 map[] = { 1120 2, /* 5 lines */ 1121 1, /* 6 lines */ 1122 0, /* 7 lines */ 1123 3, /* 8 lines */ 1124 6, /* 9 lines */ 1125 5, /* 10 lines */ 1126 4, /* 11 lines */ 1127 7, /* 12 lines */ 1128 }; 1129 /* 1130 * Still using the default IO_BUFFER_WAKE and FAST_WAKE, see 1131 * comments below for more information 1132 */ 1133 int tmp; 1134 1135 tmp = map[intel_dp->psr.io_wake_lines - 1136 TGL_EDP_PSR2_IO_BUFFER_WAKE_MIN_LINES]; 1137 val |= TGL_EDP_PSR2_IO_BUFFER_WAKE(tmp + TGL_EDP_PSR2_IO_BUFFER_WAKE_MIN_LINES); 1138 1139 tmp = map[intel_dp->psr.fast_wake_lines - TGL_EDP_PSR2_FAST_WAKE_MIN_LINES]; 1140 val |= TGL_EDP_PSR2_FAST_WAKE(tmp + TGL_EDP_PSR2_FAST_WAKE_MIN_LINES); 1141 } else if (DISPLAY_VER(display) >= 20) { 1142 val |= LNL_EDP_PSR2_IO_BUFFER_WAKE(intel_dp->psr.io_wake_lines); 1143 } else if (DISPLAY_VER(display) >= 12) { 1144 val |= TGL_EDP_PSR2_IO_BUFFER_WAKE(intel_dp->psr.io_wake_lines); 1145 val |= TGL_EDP_PSR2_FAST_WAKE(intel_dp->psr.fast_wake_lines); 1146 } else if (DISPLAY_VER(display) >= 9) { 1147 val |= EDP_PSR2_IO_BUFFER_WAKE(intel_dp->psr.io_wake_lines); 1148 val |= EDP_PSR2_FAST_WAKE(intel_dp->psr.fast_wake_lines); 1149 } 1150 1151 if (intel_dp->psr.req_psr2_sdp_prior_scanline) 1152 val |= EDP_PSR2_SU_SDP_SCANLINE; 1153 1154 if (DISPLAY_VER(display) >= 20) 1155 psr_val |= LNL_EDP_PSR_ENTRY_SETUP_FRAMES(intel_dp->psr.entry_setup_frames); 1156 1157 if (intel_dp->psr.psr2_sel_fetch_enabled) { 1158 u32 tmp; 1159 1160 tmp = intel_de_read(display, 1161 PSR2_MAN_TRK_CTL(display, cpu_transcoder)); 1162 drm_WARN_ON(display->drm, !(tmp & PSR2_MAN_TRK_CTL_ENABLE)); 1163 } else if (HAS_PSR2_SEL_FETCH(display)) { 1164 intel_de_write(display, 1165 PSR2_MAN_TRK_CTL(display, cpu_transcoder), 0); 1166 } 1167 1168 if (intel_dp->psr.su_region_et_enabled) 1169 val |= LNL_EDP_PSR2_SU_REGION_ET_ENABLE; 1170 1171 /* 1172 * PSR2 HW is incorrectly using EDP_PSR_TP1_TP3_SEL and BSpec is 1173 * recommending keep this bit unset while PSR2 is enabled. 1174 */ 1175 intel_de_write(display, psr_ctl_reg(display, cpu_transcoder), psr_val); 1176 1177 intel_de_write(display, EDP_PSR2_CTL(display, cpu_transcoder), val); 1178 } 1179 1180 static bool 1181 transcoder_has_psr2(struct intel_display *display, enum transcoder cpu_transcoder) 1182 { 1183 if (display->platform.alderlake_p || DISPLAY_VER(display) >= 14) 1184 return cpu_transcoder == TRANSCODER_A || cpu_transcoder == TRANSCODER_B; 1185 else if (DISPLAY_VER(display) >= 12) 1186 return cpu_transcoder == TRANSCODER_A; 1187 else if (DISPLAY_VER(display) >= 9) 1188 return cpu_transcoder == TRANSCODER_EDP; 1189 else 1190 return false; 1191 } 1192 1193 static u32 intel_get_frame_time_us(const struct intel_crtc_state *crtc_state) 1194 { 1195 if (!crtc_state->hw.active) 1196 return 0; 1197 1198 return DIV_ROUND_UP(1000 * 1000, 1199 drm_mode_vrefresh(&crtc_state->hw.adjusted_mode)); 1200 } 1201 1202 static void psr2_program_idle_frames(struct intel_dp *intel_dp, 1203 u32 idle_frames) 1204 { 1205 struct intel_display *display = to_intel_display(intel_dp); 1206 enum transcoder cpu_transcoder = intel_dp->psr.transcoder; 1207 1208 intel_de_rmw(display, EDP_PSR2_CTL(display, cpu_transcoder), 1209 EDP_PSR2_IDLE_FRAMES_MASK, 1210 EDP_PSR2_IDLE_FRAMES(idle_frames)); 1211 } 1212 1213 static void tgl_psr2_enable_dc3co(struct intel_dp *intel_dp) 1214 { 1215 struct intel_display *display = to_intel_display(intel_dp); 1216 1217 psr2_program_idle_frames(intel_dp, 0); 1218 intel_display_power_set_target_dc_state(display, DC_STATE_EN_DC3CO); 1219 } 1220 1221 static void tgl_psr2_disable_dc3co(struct intel_dp *intel_dp) 1222 { 1223 struct intel_display *display = to_intel_display(intel_dp); 1224 1225 intel_display_power_set_target_dc_state(display, DC_STATE_EN_UPTO_DC6); 1226 psr2_program_idle_frames(intel_dp, psr_compute_idle_frames(intel_dp)); 1227 } 1228 1229 static void tgl_dc3co_disable_work(struct work_struct *work) 1230 { 1231 struct intel_dp *intel_dp = 1232 container_of(work, typeof(*intel_dp), psr.dc3co_work.work); 1233 1234 mutex_lock(&intel_dp->psr.lock); 1235 /* If delayed work is pending, it is not idle */ 1236 if (delayed_work_pending(&intel_dp->psr.dc3co_work)) 1237 goto unlock; 1238 1239 tgl_psr2_disable_dc3co(intel_dp); 1240 unlock: 1241 mutex_unlock(&intel_dp->psr.lock); 1242 } 1243 1244 static void tgl_disallow_dc3co_on_psr2_exit(struct intel_dp *intel_dp) 1245 { 1246 if (!intel_dp->psr.dc3co_exitline) 1247 return; 1248 1249 cancel_delayed_work(&intel_dp->psr.dc3co_work); 1250 /* Before PSR2 exit disallow dc3co*/ 1251 tgl_psr2_disable_dc3co(intel_dp); 1252 } 1253 1254 static bool 1255 dc3co_is_pipe_port_compatible(struct intel_dp *intel_dp, 1256 struct intel_crtc_state *crtc_state) 1257 { 1258 struct intel_display *display = to_intel_display(intel_dp); 1259 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 1260 enum pipe pipe = to_intel_crtc(crtc_state->uapi.crtc)->pipe; 1261 enum port port = dig_port->base.port; 1262 1263 if (display->platform.alderlake_p || DISPLAY_VER(display) >= 14) 1264 return pipe <= PIPE_B && port <= PORT_B; 1265 else 1266 return pipe == PIPE_A && port == PORT_A; 1267 } 1268 1269 static void 1270 tgl_dc3co_exitline_compute_config(struct intel_dp *intel_dp, 1271 struct intel_crtc_state *crtc_state) 1272 { 1273 struct intel_display *display = to_intel_display(intel_dp); 1274 const u32 crtc_vdisplay = crtc_state->uapi.adjusted_mode.crtc_vdisplay; 1275 struct i915_power_domains *power_domains = &display->power.domains; 1276 u32 exit_scanlines; 1277 1278 /* 1279 * FIXME: Due to the changed sequence of activating/deactivating DC3CO, 1280 * disable DC3CO until the changed dc3co activating/deactivating sequence 1281 * is applied. B.Specs:49196 1282 */ 1283 return; 1284 1285 /* 1286 * DMC's DC3CO exit mechanism has an issue with Selective Fecth 1287 * TODO: when the issue is addressed, this restriction should be removed. 1288 */ 1289 if (crtc_state->enable_psr2_sel_fetch) 1290 return; 1291 1292 if (!(power_domains->allowed_dc_mask & DC_STATE_EN_DC3CO)) 1293 return; 1294 1295 if (!dc3co_is_pipe_port_compatible(intel_dp, crtc_state)) 1296 return; 1297 1298 /* Wa_16011303918:adl-p */ 1299 if (intel_display_wa(display, INTEL_DISPLAY_WA_16011303918)) 1300 return; 1301 1302 /* 1303 * DC3CO Exit time 200us B.Spec 49196 1304 * PSR2 transcoder Early Exit scanlines = ROUNDUP(200 / line time) + 1 1305 */ 1306 exit_scanlines = 1307 intel_usecs_to_scanlines(&crtc_state->uapi.adjusted_mode, 200) + 1; 1308 1309 if (drm_WARN_ON(display->drm, exit_scanlines > crtc_vdisplay)) 1310 return; 1311 1312 crtc_state->dc3co_exitline = crtc_vdisplay - exit_scanlines; 1313 } 1314 1315 static bool intel_psr2_sel_fetch_config_valid(struct intel_dp *intel_dp, 1316 struct intel_crtc_state *crtc_state) 1317 { 1318 struct intel_display *display = to_intel_display(intel_dp); 1319 1320 if (!display->params.enable_psr2_sel_fetch && 1321 intel_dp->psr.debug != I915_PSR_DEBUG_ENABLE_SEL_FETCH) { 1322 drm_dbg_kms(display->drm, 1323 "PSR2 sel fetch not enabled, disabled by parameter\n"); 1324 return false; 1325 } 1326 1327 return crtc_state->enable_psr2_sel_fetch = true; 1328 } 1329 1330 static bool psr2_granularity_check(struct intel_crtc_state *crtc_state, 1331 struct intel_connector *connector) 1332 { 1333 struct intel_dp *intel_dp = intel_attached_dp(connector); 1334 struct intel_display *display = to_intel_display(intel_dp); 1335 const struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config; 1336 const int crtc_hdisplay = crtc_state->hw.adjusted_mode.crtc_hdisplay; 1337 const int crtc_vdisplay = crtc_state->hw.adjusted_mode.crtc_vdisplay; 1338 u16 y_granularity = 0; 1339 u16 sink_y_granularity = crtc_state->has_panel_replay ? 1340 connector->dp.panel_replay_caps.su_y_granularity : 1341 connector->dp.psr_caps.su_y_granularity; 1342 u16 sink_w_granularity; 1343 1344 if (crtc_state->has_panel_replay) 1345 sink_w_granularity = connector->dp.panel_replay_caps.su_w_granularity == 1346 DP_PANEL_REPLAY_FULL_LINE_GRANULARITY ? 1347 crtc_hdisplay : connector->dp.panel_replay_caps.su_w_granularity; 1348 else 1349 sink_w_granularity = connector->dp.psr_caps.su_w_granularity; 1350 1351 /* PSR2 HW only send full lines so we only need to validate the width */ 1352 if (crtc_hdisplay % sink_w_granularity) 1353 return false; 1354 1355 if (crtc_vdisplay % sink_y_granularity) 1356 return false; 1357 1358 /* HW tracking is only aligned to 4 lines */ 1359 if (!crtc_state->enable_psr2_sel_fetch) 1360 return sink_y_granularity == 4; 1361 1362 /* 1363 * adl_p and mtl platforms have 1 line granularity. 1364 * For other platforms with SW tracking we can adjust the y coordinates 1365 * to match sink requirement if multiple of 4. 1366 */ 1367 if (display->platform.alderlake_p || DISPLAY_VER(display) >= 14) 1368 y_granularity = sink_y_granularity; 1369 else if (sink_y_granularity <= 2) 1370 y_granularity = 4; 1371 else if ((sink_y_granularity % 4) == 0) 1372 y_granularity = sink_y_granularity; 1373 1374 if (y_granularity == 0 || crtc_vdisplay % y_granularity) 1375 return false; 1376 1377 if (crtc_state->dsc.compression_enable && 1378 vdsc_cfg->slice_height % y_granularity) 1379 return false; 1380 1381 crtc_state->su_y_granularity = y_granularity; 1382 return true; 1383 } 1384 1385 static bool _compute_psr2_sdp_prior_scanline_indication(struct intel_dp *intel_dp, 1386 struct intel_crtc_state *crtc_state) 1387 { 1388 struct intel_display *display = to_intel_display(intel_dp); 1389 const struct drm_display_mode *adjusted_mode = &crtc_state->uapi.adjusted_mode; 1390 u32 hblank_total, hblank_ns, req_ns; 1391 1392 hblank_total = adjusted_mode->crtc_hblank_end - adjusted_mode->crtc_hblank_start; 1393 hblank_ns = div_u64(1000000ULL * hblank_total, adjusted_mode->crtc_clock); 1394 1395 /* From spec: ((60 / number of lanes) + 11) * 1000 / symbol clock frequency MHz */ 1396 req_ns = ((60 / crtc_state->lane_count) + 11) * 1000 / (crtc_state->port_clock / 1000); 1397 1398 if ((hblank_ns - req_ns) > 100) 1399 return true; 1400 1401 /* Not supported <13 / Wa_22012279113:adl-p */ 1402 if (DISPLAY_VER(display) < 14 || intel_dp->edp_dpcd[0] < DP_EDP_14b) 1403 return false; 1404 1405 crtc_state->req_psr2_sdp_prior_scanline = true; 1406 return true; 1407 } 1408 1409 static int intel_psr_entry_setup_frames(struct intel_dp *intel_dp, 1410 struct drm_connector_state *conn_state, 1411 const struct drm_display_mode *adjusted_mode) 1412 { 1413 struct intel_display *display = to_intel_display(intel_dp); 1414 struct intel_connector *connector = to_intel_connector(conn_state->connector); 1415 int psr_setup_time = drm_dp_psr_setup_time(connector->dp.psr_caps.dpcd); 1416 int entry_setup_frames = 0; 1417 1418 if (psr_setup_time < 0) { 1419 drm_dbg_kms(display->drm, 1420 "PSR condition failed: Invalid PSR setup time (0x%02x)\n", 1421 connector->dp.psr_caps.dpcd[1]); 1422 return -ETIME; 1423 } 1424 1425 if (intel_usecs_to_scanlines(adjusted_mode, psr_setup_time) > 1426 adjusted_mode->crtc_vtotal - adjusted_mode->crtc_vdisplay - 1) { 1427 if (DISPLAY_VER(display) >= 20) { 1428 /* setup entry frames can be up to 3 frames */ 1429 entry_setup_frames = 1; 1430 drm_dbg_kms(display->drm, 1431 "PSR setup entry frames %d\n", 1432 entry_setup_frames); 1433 } else { 1434 drm_dbg_kms(display->drm, 1435 "PSR condition failed: PSR setup time (%d us) too long\n", 1436 psr_setup_time); 1437 return -ETIME; 1438 } 1439 } 1440 1441 return entry_setup_frames; 1442 } 1443 1444 static 1445 int _intel_psr_min_set_context_latency(const struct intel_crtc_state *crtc_state, 1446 bool needs_panel_replay, 1447 bool needs_sel_update) 1448 { 1449 struct intel_display *display = to_intel_display(crtc_state); 1450 1451 if (!crtc_state->has_psr) 1452 return 0; 1453 1454 /* Wa_14015401596 */ 1455 if (intel_vrr_possible(crtc_state) && IS_DISPLAY_VER(display, 13, 14)) 1456 return 1; 1457 1458 /* Rest is for SRD_STATUS needed on LunarLake and onwards */ 1459 if (DISPLAY_VER(display) < 20) 1460 return 0; 1461 1462 /* 1463 * Comment on SRD_STATUS register in Bspec for LunarLake and onwards: 1464 * 1465 * To deterministically capture the transition of the state machine 1466 * going from SRDOFFACK to IDLE, the delayed V. Blank should be at least 1467 * one line after the non-delayed V. Blank. 1468 * 1469 * Legacy TG: TRANS_SET_CONTEXT_LATENCY > 0 1470 * VRR TG: TRANS_VRR_CTL[ VRR Guardband ] < (TRANS_VRR_VMAX[ VRR Vmax ] 1471 * - TRANS_VTOTAL[ Vertical Active ]) 1472 * 1473 * SRD_STATUS is used only by PSR1 on PantherLake. 1474 * SRD_STATUS is used by PSR1 and Panel Replay DP on LunarLake. 1475 */ 1476 1477 if (DISPLAY_VER(display) >= 30 && (needs_panel_replay || 1478 needs_sel_update)) 1479 return 0; 1480 else if (DISPLAY_VER(display) < 30 && (needs_sel_update || 1481 intel_crtc_has_type(crtc_state, 1482 INTEL_OUTPUT_EDP))) 1483 return 0; 1484 else 1485 return 1; 1486 } 1487 1488 static bool _wake_lines_fit_into_vblank(const struct intel_crtc_state *crtc_state, 1489 int vblank, 1490 int wake_lines) 1491 { 1492 if (crtc_state->req_psr2_sdp_prior_scanline) 1493 vblank -= 1; 1494 1495 /* Vblank >= PSR2_CTL Block Count Number maximum line count */ 1496 if (vblank < wake_lines) 1497 return false; 1498 1499 return true; 1500 } 1501 1502 static bool wake_lines_fit_into_vblank(struct intel_dp *intel_dp, 1503 const struct intel_crtc_state *crtc_state, 1504 bool aux_less, 1505 bool needs_panel_replay, 1506 bool needs_sel_update) 1507 { 1508 struct intel_display *display = to_intel_display(intel_dp); 1509 int vblank = crtc_state->hw.adjusted_mode.crtc_vblank_end - 1510 crtc_state->hw.adjusted_mode.crtc_vblank_start; 1511 int wake_lines; 1512 int scl = _intel_psr_min_set_context_latency(crtc_state, 1513 needs_panel_replay, 1514 needs_sel_update); 1515 vblank -= scl; 1516 1517 if (aux_less) 1518 wake_lines = crtc_state->alpm_state.aux_less_wake_lines; 1519 else 1520 wake_lines = DISPLAY_VER(display) < 20 ? 1521 psr2_block_count_lines(crtc_state->alpm_state.io_wake_lines, 1522 crtc_state->alpm_state.fast_wake_lines) : 1523 crtc_state->alpm_state.io_wake_lines; 1524 1525 /* 1526 * Guardband has not been computed yet, so we conservatively check if the 1527 * full vblank duration is sufficient to accommodate wake line requirements 1528 * for PSR features like Panel Replay and Selective Update. 1529 * 1530 * Once the actual guardband is available, a more accurate validation is 1531 * performed in intel_psr_compute_config_late(), and PSR features are 1532 * disabled if wake lines exceed the available guardband. 1533 */ 1534 return _wake_lines_fit_into_vblank(crtc_state, vblank, wake_lines); 1535 } 1536 1537 static bool alpm_config_valid(struct intel_dp *intel_dp, 1538 struct intel_crtc_state *crtc_state, 1539 bool aux_less, 1540 bool needs_panel_replay, 1541 bool needs_sel_update) 1542 { 1543 struct intel_display *display = to_intel_display(intel_dp); 1544 1545 if (!intel_alpm_compute_params(intel_dp, crtc_state)) { 1546 drm_dbg_kms(display->drm, 1547 "PSR2/Panel Replay not enabled, Unable to use long enough wake times\n"); 1548 return false; 1549 } 1550 1551 if (!wake_lines_fit_into_vblank(intel_dp, crtc_state, aux_less, 1552 needs_panel_replay, needs_sel_update)) { 1553 drm_dbg_kms(display->drm, 1554 "PSR2/Panel Replay not enabled, too short vblank time\n"); 1555 return false; 1556 } 1557 1558 return true; 1559 } 1560 1561 static bool intel_psr2_config_valid(struct intel_dp *intel_dp, 1562 struct intel_crtc_state *crtc_state, 1563 struct drm_connector_state *conn_state) 1564 { 1565 struct intel_display *display = to_intel_display(intel_dp); 1566 struct intel_connector *connector = to_intel_connector(conn_state->connector); 1567 int crtc_hdisplay = crtc_state->hw.adjusted_mode.crtc_hdisplay; 1568 int crtc_vdisplay = crtc_state->hw.adjusted_mode.crtc_vdisplay; 1569 int psr_max_h = 0, psr_max_v = 0, max_bpp = 0; 1570 1571 if (!connector->dp.psr_caps.su_support || display->params.enable_psr == 1) 1572 return false; 1573 1574 /* JSL and EHL only supports eDP 1.3 */ 1575 if (display->platform.jasperlake || display->platform.elkhartlake) { 1576 drm_dbg_kms(display->drm, "PSR2 not supported by phy\n"); 1577 return false; 1578 } 1579 1580 /* Wa_16011181250 */ 1581 if (intel_display_wa(display, INTEL_DISPLAY_WA_16011181250)) { 1582 drm_dbg_kms(display->drm, 1583 "PSR2 is defeatured for this platform\n"); 1584 return false; 1585 } 1586 1587 if (display->platform.alderlake_p && IS_DISPLAY_STEP(display, STEP_A0, STEP_B0)) { 1588 drm_dbg_kms(display->drm, 1589 "PSR2 not completely functional in this stepping\n"); 1590 return false; 1591 } 1592 1593 if (!transcoder_has_psr2(display, crtc_state->cpu_transcoder)) { 1594 drm_dbg_kms(display->drm, 1595 "PSR2 not supported in transcoder %s\n", 1596 transcoder_name(crtc_state->cpu_transcoder)); 1597 return false; 1598 } 1599 1600 /* 1601 * DSC and PSR2 cannot be enabled simultaneously. If a requested 1602 * resolution requires DSC to be enabled, priority is given to DSC 1603 * over PSR2. 1604 */ 1605 if (crtc_state->dsc.compression_enable && 1606 (DISPLAY_VER(display) < 14 && !display->platform.alderlake_p)) { 1607 drm_dbg_kms(display->drm, 1608 "PSR2 cannot be enabled since DSC is enabled\n"); 1609 return false; 1610 } 1611 1612 if (DISPLAY_VER(display) >= 20) { 1613 psr_max_h = crtc_hdisplay; 1614 psr_max_v = crtc_vdisplay; 1615 max_bpp = crtc_state->pipe_bpp; 1616 } else if (IS_DISPLAY_VER(display, 12, 14)) { 1617 psr_max_h = 5120; 1618 psr_max_v = 3200; 1619 max_bpp = 30; 1620 } else if (IS_DISPLAY_VER(display, 10, 11)) { 1621 psr_max_h = 4096; 1622 psr_max_v = 2304; 1623 max_bpp = 24; 1624 } else if (DISPLAY_VER(display) == 9) { 1625 psr_max_h = 3640; 1626 psr_max_v = 2304; 1627 max_bpp = 24; 1628 } 1629 1630 if (crtc_state->pipe_bpp > max_bpp) { 1631 drm_dbg_kms(display->drm, 1632 "PSR2 not enabled, pipe bpp %d > max supported %d\n", 1633 crtc_state->pipe_bpp, max_bpp); 1634 return false; 1635 } 1636 1637 /* Wa_16011303918:adl-p */ 1638 if (crtc_state->vrr.enable && 1639 display->platform.alderlake_p && IS_DISPLAY_STEP(display, STEP_A0, STEP_B0)) { 1640 drm_dbg_kms(display->drm, 1641 "PSR2 not enabled, not compatible with HW stepping + VRR\n"); 1642 return false; 1643 } 1644 1645 if (!alpm_config_valid(intel_dp, crtc_state, false, false, true)) 1646 return false; 1647 1648 if (!crtc_state->enable_psr2_sel_fetch && 1649 (crtc_hdisplay > psr_max_h || crtc_vdisplay > psr_max_v)) { 1650 drm_dbg_kms(display->drm, 1651 "PSR2 not enabled, resolution %dx%d > max supported %dx%d\n", 1652 crtc_hdisplay, crtc_vdisplay, 1653 psr_max_h, psr_max_v); 1654 return false; 1655 } 1656 1657 tgl_dc3co_exitline_compute_config(intel_dp, crtc_state); 1658 1659 return true; 1660 } 1661 1662 static bool intel_sel_update_config_valid(struct intel_crtc_state *crtc_state, 1663 struct drm_connector_state *conn_state) 1664 { 1665 struct intel_connector *connector = to_intel_connector(conn_state->connector); 1666 struct intel_dp *intel_dp = intel_attached_dp(connector); 1667 struct intel_display *display = to_intel_display(intel_dp); 1668 1669 if (HAS_PSR2_SEL_FETCH(display) && 1670 !intel_psr2_sel_fetch_config_valid(intel_dp, crtc_state) && 1671 !HAS_PSR_HW_TRACKING(display)) { 1672 drm_dbg_kms(display->drm, 1673 "Selective update not enabled, selective fetch not valid and no HW tracking available\n"); 1674 goto unsupported; 1675 } 1676 1677 if (!sel_update_global_enabled(intel_dp)) { 1678 drm_dbg_kms(display->drm, 1679 "Selective update disabled by flag\n"); 1680 goto unsupported; 1681 } 1682 1683 if (!crtc_state->has_panel_replay && !intel_psr2_config_valid(intel_dp, crtc_state, 1684 conn_state)) 1685 goto unsupported; 1686 1687 if (!_compute_psr2_sdp_prior_scanline_indication(intel_dp, crtc_state)) { 1688 drm_dbg_kms(display->drm, 1689 "Selective update not enabled, SDP indication do not fit in hblank\n"); 1690 goto unsupported; 1691 } 1692 1693 if (crtc_state->has_panel_replay) { 1694 if (DISPLAY_VER(display) < 14) 1695 goto unsupported; 1696 1697 if (!connector->dp.panel_replay_caps.su_support) 1698 goto unsupported; 1699 1700 if (intel_dsc_enabled_on_link(crtc_state) && 1701 connector->dp.panel_replay_caps.dsc_support != 1702 INTEL_DP_PANEL_REPLAY_DSC_SELECTIVE_UPDATE) { 1703 drm_dbg_kms(display->drm, 1704 "Selective update with Panel Replay not enabled because it's not supported with DSC\n"); 1705 goto unsupported; 1706 } 1707 } 1708 1709 if (crtc_state->crc_enabled) { 1710 drm_dbg_kms(display->drm, 1711 "Selective update not enabled because it would inhibit pipe CRC calculation\n"); 1712 goto unsupported; 1713 } 1714 1715 if (!psr2_granularity_check(crtc_state, connector)) { 1716 drm_dbg_kms(display->drm, 1717 "Selective update not enabled, SU granularity not compatible\n"); 1718 goto unsupported; 1719 } 1720 1721 crtc_state->enable_psr2_su_region_et = psr2_su_region_et_valid(connector, 1722 crtc_state->has_panel_replay); 1723 1724 return true; 1725 1726 unsupported: 1727 crtc_state->enable_psr2_sel_fetch = false; 1728 return false; 1729 } 1730 1731 static bool _psr_compute_config(struct intel_dp *intel_dp, 1732 struct intel_crtc_state *crtc_state, 1733 struct drm_connector_state *conn_state) 1734 { 1735 struct intel_display *display = to_intel_display(intel_dp); 1736 const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; 1737 int entry_setup_frames; 1738 1739 if (!CAN_PSR(intel_dp) || !display->params.enable_psr) 1740 return false; 1741 1742 /* 1743 * Currently PSR doesn't work reliably with VRR enabled. 1744 */ 1745 if (crtc_state->vrr.enable) 1746 return false; 1747 1748 entry_setup_frames = intel_psr_entry_setup_frames(intel_dp, conn_state, adjusted_mode); 1749 1750 if (entry_setup_frames >= 0) { 1751 crtc_state->entry_setup_frames = entry_setup_frames; 1752 } else { 1753 crtc_state->no_psr_reason = "PSR setup timing not met"; 1754 drm_dbg_kms(display->drm, 1755 "PSR condition failed: PSR setup timing not met\n"); 1756 return false; 1757 } 1758 1759 return true; 1760 } 1761 1762 static inline bool compute_link_off_after_as_sdp_when_pr_active(struct intel_connector *connector) 1763 { 1764 return (connector->dp.panel_replay_caps.dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_CAPABILITY)] & 1765 DP_PANEL_REPLAY_LINK_OFF_SUPPORTED_IN_PR_AFTER_ADAPTIVE_SYNC_SDP); 1766 } 1767 1768 static inline bool compute_disable_as_sdp_when_pr_active(struct intel_connector *connector) 1769 { 1770 return !(connector->dp.panel_replay_caps.dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_CAPABILITY)] & 1771 DP_PANEL_REPLAY_ASYNC_VIDEO_TIMING_NOT_SUPPORTED_IN_PR); 1772 } 1773 1774 static bool _panel_replay_compute_config(struct intel_crtc_state *crtc_state, 1775 const struct drm_connector_state *conn_state) 1776 { 1777 struct intel_connector *connector = 1778 to_intel_connector(conn_state->connector); 1779 struct intel_dp *intel_dp = intel_attached_dp(connector); 1780 struct intel_display *display = to_intel_display(intel_dp); 1781 struct intel_hdcp *hdcp = &connector->hdcp; 1782 1783 if (!CAN_PANEL_REPLAY(intel_dp)) 1784 return false; 1785 1786 if (!connector->dp.panel_replay_caps.support) 1787 return false; 1788 1789 if (!panel_replay_global_enabled(intel_dp)) { 1790 drm_dbg_kms(display->drm, "Panel Replay disabled by flag\n"); 1791 return false; 1792 } 1793 1794 if (crtc_state->crc_enabled) { 1795 drm_dbg_kms(display->drm, 1796 "Panel Replay not enabled because it would inhibit pipe CRC calculation\n"); 1797 return false; 1798 } 1799 1800 if (intel_dsc_enabled_on_link(crtc_state) && 1801 connector->dp.panel_replay_caps.dsc_support == 1802 INTEL_DP_PANEL_REPLAY_DSC_NOT_SUPPORTED) { 1803 drm_dbg_kms(display->drm, 1804 "Panel Replay not enabled because it's not supported with DSC\n"); 1805 return false; 1806 } 1807 1808 crtc_state->link_off_after_as_sdp_when_pr_active = compute_link_off_after_as_sdp_when_pr_active(connector); 1809 crtc_state->disable_as_sdp_when_pr_active = compute_disable_as_sdp_when_pr_active(connector); 1810 1811 if (!intel_dp_is_edp(intel_dp)) 1812 return true; 1813 1814 /* Remaining checks are for eDP only */ 1815 1816 if (to_intel_crtc(crtc_state->uapi.crtc)->pipe != PIPE_A && 1817 to_intel_crtc(crtc_state->uapi.crtc)->pipe != PIPE_B) 1818 return false; 1819 1820 /* 128b/132b Panel Replay is not supported on eDP */ 1821 if (intel_dp_is_uhbr(crtc_state)) { 1822 drm_dbg_kms(display->drm, 1823 "Panel Replay is not supported with 128b/132b\n"); 1824 return false; 1825 } 1826 1827 /* HW will not allow Panel Replay on eDP when HDCP enabled */ 1828 if (conn_state->content_protection == 1829 DRM_MODE_CONTENT_PROTECTION_DESIRED || 1830 (conn_state->content_protection == 1831 DRM_MODE_CONTENT_PROTECTION_ENABLED && hdcp->value == 1832 DRM_MODE_CONTENT_PROTECTION_UNDESIRED)) { 1833 drm_dbg_kms(display->drm, 1834 "Panel Replay is not supported with HDCP\n"); 1835 return false; 1836 } 1837 1838 if (!alpm_config_valid(intel_dp, crtc_state, true, true, false)) 1839 return false; 1840 1841 return true; 1842 } 1843 1844 static bool intel_psr_needs_wa_18037818876(struct intel_dp *intel_dp, 1845 struct intel_crtc_state *crtc_state) 1846 { 1847 struct intel_display *display = to_intel_display(intel_dp); 1848 1849 return (DISPLAY_VER(display) == 20 && crtc_state->entry_setup_frames > 0 && 1850 !crtc_state->has_sel_update); 1851 } 1852 1853 static 1854 void intel_psr_set_non_psr_pipes(struct intel_dp *intel_dp, 1855 struct intel_crtc_state *crtc_state) 1856 { 1857 struct intel_display *display = to_intel_display(intel_dp); 1858 struct intel_atomic_state *state = to_intel_atomic_state(crtc_state->uapi.state); 1859 struct intel_crtc *crtc; 1860 u8 active_pipes = 0; 1861 1862 /* Wa_16025596647 */ 1863 if (!intel_display_wa(display, INTEL_DISPLAY_WA_16025596647)) 1864 return; 1865 1866 /* Not needed by Panel Replay */ 1867 if (crtc_state->has_panel_replay) 1868 return; 1869 1870 /* We ignore possible secondary PSR/Panel Replay capable eDP */ 1871 for_each_intel_crtc(display->drm, crtc) 1872 active_pipes |= crtc->active ? BIT(crtc->pipe) : 0; 1873 1874 active_pipes = intel_calc_active_pipes(state, active_pipes); 1875 1876 crtc_state->active_non_psr_pipes = active_pipes & 1877 ~BIT(to_intel_crtc(crtc_state->uapi.crtc)->pipe); 1878 } 1879 1880 void intel_psr_compute_config(struct intel_dp *intel_dp, 1881 struct intel_crtc_state *crtc_state, 1882 struct drm_connector_state *conn_state) 1883 { 1884 struct intel_display *display = to_intel_display(intel_dp); 1885 struct intel_connector *connector = to_intel_connector(conn_state->connector); 1886 const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; 1887 1888 if (!psr_global_enabled(intel_dp)) { 1889 drm_dbg_kms(display->drm, "PSR disabled by flag\n"); 1890 return; 1891 } 1892 1893 if (intel_dp->psr.sink_not_reliable) { 1894 drm_dbg_kms(display->drm, 1895 "PSR sink implementation is not reliable\n"); 1896 return; 1897 } 1898 1899 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { 1900 drm_dbg_kms(display->drm, 1901 "PSR condition failed: Interlaced mode enabled\n"); 1902 return; 1903 } 1904 1905 /* 1906 * FIXME figure out what is wrong with PSR+joiner and 1907 * fix it. Presumably something related to the fact that 1908 * PSR is a transcoder level feature. 1909 */ 1910 if (crtc_state->joiner_pipes) { 1911 drm_dbg_kms(display->drm, 1912 "PSR disabled due to joiner\n"); 1913 return; 1914 } 1915 1916 /* Only used for state verification. */ 1917 crtc_state->panel_replay_dsc_support = connector->dp.panel_replay_caps.dsc_support; 1918 crtc_state->has_panel_replay = _panel_replay_compute_config(crtc_state, conn_state); 1919 1920 crtc_state->has_psr = crtc_state->has_panel_replay ? true : 1921 _psr_compute_config(intel_dp, crtc_state, conn_state); 1922 1923 if (!crtc_state->has_psr) 1924 return; 1925 1926 crtc_state->has_sel_update = intel_sel_update_config_valid(crtc_state, conn_state); 1927 } 1928 1929 void intel_psr_get_config(struct intel_encoder *encoder, 1930 struct intel_crtc_state *pipe_config) 1931 { 1932 struct intel_display *display = to_intel_display(encoder); 1933 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 1934 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; 1935 struct intel_dp *intel_dp; 1936 u32 val; 1937 1938 if (!dig_port) 1939 return; 1940 1941 intel_dp = &dig_port->dp; 1942 if (!(CAN_PSR(intel_dp) || CAN_PANEL_REPLAY(intel_dp))) 1943 return; 1944 1945 mutex_lock(&intel_dp->psr.lock); 1946 if (!intel_dp->psr.enabled) 1947 goto unlock; 1948 1949 if (intel_dp->psr.panel_replay_enabled) { 1950 pipe_config->has_psr = pipe_config->has_panel_replay = true; 1951 } else { 1952 /* 1953 * Not possible to read EDP_PSR/PSR2_CTL registers as it is 1954 * enabled/disabled because of frontbuffer tracking and others. 1955 */ 1956 pipe_config->has_psr = true; 1957 } 1958 1959 pipe_config->has_sel_update = intel_dp->psr.sel_update_enabled; 1960 pipe_config->infoframes.enable |= intel_hdmi_infoframe_enable(DP_SDP_VSC); 1961 1962 if (!intel_dp->psr.sel_update_enabled) 1963 goto unlock; 1964 1965 if (HAS_PSR2_SEL_FETCH(display)) { 1966 val = intel_de_read(display, 1967 PSR2_MAN_TRK_CTL(display, cpu_transcoder)); 1968 if (val & PSR2_MAN_TRK_CTL_ENABLE) 1969 pipe_config->enable_psr2_sel_fetch = true; 1970 } 1971 1972 pipe_config->enable_psr2_su_region_et = intel_dp->psr.su_region_et_enabled; 1973 1974 if (DISPLAY_VER(display) >= 12) { 1975 val = intel_de_read(display, 1976 TRANS_EXITLINE(display, cpu_transcoder)); 1977 pipe_config->dc3co_exitline = REG_FIELD_GET(EXITLINE_MASK, val); 1978 } 1979 unlock: 1980 mutex_unlock(&intel_dp->psr.lock); 1981 } 1982 1983 static void intel_psr_activate(struct intel_dp *intel_dp) 1984 { 1985 struct intel_display *display = to_intel_display(intel_dp); 1986 enum transcoder cpu_transcoder = intel_dp->psr.transcoder; 1987 1988 drm_WARN_ON(display->drm, 1989 transcoder_has_psr2(display, cpu_transcoder) && 1990 intel_de_read(display, EDP_PSR2_CTL(display, cpu_transcoder)) & EDP_PSR2_ENABLE); 1991 1992 drm_WARN_ON(display->drm, 1993 intel_de_read(display, psr_ctl_reg(display, cpu_transcoder)) & EDP_PSR_ENABLE); 1994 1995 drm_WARN_ON(display->drm, intel_dp->psr.active); 1996 1997 drm_WARN_ON(display->drm, !intel_dp->psr.enabled); 1998 1999 lockdep_assert_held(&intel_dp->psr.lock); 2000 2001 /* psr1, psr2 and panel-replay are mutually exclusive.*/ 2002 if (intel_dp->psr.panel_replay_enabled) 2003 dg2_activate_panel_replay(intel_dp); 2004 else if (intel_dp->psr.sel_update_enabled) 2005 hsw_activate_psr2(intel_dp); 2006 else 2007 hsw_activate_psr1(intel_dp); 2008 2009 intel_dp->psr.active = true; 2010 intel_dp->psr.no_psr_reason = NULL; 2011 } 2012 2013 /* 2014 * Wa_16013835468 2015 * Wa_14015648006 2016 */ 2017 static void wm_optimization_wa(struct intel_dp *intel_dp, 2018 const struct intel_crtc_state *crtc_state) 2019 { 2020 struct intel_display *display = to_intel_display(intel_dp); 2021 enum pipe pipe = intel_dp->psr.pipe; 2022 bool activate = false; 2023 2024 /* Wa_14015648006 */ 2025 if (IS_DISPLAY_VER(display, 11, 14) && crtc_state->wm_level_disabled) 2026 activate = true; 2027 2028 /* Wa_16013835468 */ 2029 if (DISPLAY_VER(display) == 12 && 2030 crtc_state->hw.adjusted_mode.crtc_vblank_start != 2031 crtc_state->hw.adjusted_mode.crtc_vdisplay) 2032 activate = true; 2033 2034 if (activate) 2035 intel_de_rmw(display, GEN8_CHICKEN_DCPR_1, 2036 0, LATENCY_REPORTING_REMOVED(pipe)); 2037 else 2038 intel_de_rmw(display, GEN8_CHICKEN_DCPR_1, 2039 LATENCY_REPORTING_REMOVED(pipe), 0); 2040 } 2041 2042 static void intel_psr_enable_source(struct intel_dp *intel_dp, 2043 const struct intel_crtc_state *crtc_state) 2044 { 2045 struct intel_display *display = to_intel_display(intel_dp); 2046 enum transcoder cpu_transcoder = intel_dp->psr.transcoder; 2047 u32 mask = 0; 2048 2049 /* 2050 * Only HSW and BDW have PSR AUX registers that need to be setup. 2051 * SKL+ use hardcoded values PSR AUX transactions 2052 */ 2053 if (DISPLAY_VER(display) < 9) 2054 hsw_psr_setup_aux(intel_dp); 2055 2056 /* 2057 * Per Spec: Avoid continuous PSR exit by masking MEMUP and HPD also 2058 * mask LPSP to avoid dependency on other drivers that might block 2059 * runtime_pm besides preventing other hw tracking issues now we 2060 * can rely on frontbuffer tracking. 2061 * 2062 * From bspec prior LunarLake: 2063 * Only PSR_MASK[Mask FBC modify] and PSR_MASK[Mask Hotplug] are used in 2064 * panel replay mode. 2065 * 2066 * From bspec beyod LunarLake: 2067 * Panel Replay on DP: No bits are applicable 2068 * Panel Replay on eDP: All bits are applicable 2069 */ 2070 if (DISPLAY_VER(display) < 20 || intel_dp_is_edp(intel_dp)) 2071 mask = EDP_PSR_DEBUG_MASK_HPD; 2072 2073 if (intel_dp_is_edp(intel_dp)) { 2074 mask |= EDP_PSR_DEBUG_MASK_MEMUP; 2075 2076 /* 2077 * For some unknown reason on HSW non-ULT (or at least on 2078 * Dell Latitude E6540) external displays start to flicker 2079 * when PSR is enabled on the eDP. SR/PC6 residency is much 2080 * higher than should be possible with an external display. 2081 * As a workaround leave LPSP unmasked to prevent PSR entry 2082 * when external displays are active. 2083 */ 2084 if (DISPLAY_VER(display) >= 8 || display->platform.haswell_ult) 2085 mask |= EDP_PSR_DEBUG_MASK_LPSP; 2086 2087 if (DISPLAY_VER(display) < 20) 2088 mask |= EDP_PSR_DEBUG_MASK_MAX_SLEEP; 2089 2090 /* 2091 * No separate pipe reg write mask on hsw/bdw, so have to unmask all 2092 * registers in order to keep the CURSURFLIVE tricks working :( 2093 */ 2094 if (IS_DISPLAY_VER(display, 9, 10)) 2095 mask |= EDP_PSR_DEBUG_MASK_DISP_REG_WRITE; 2096 2097 /* allow PSR with sprite enabled */ 2098 if (display->platform.haswell) 2099 mask |= EDP_PSR_DEBUG_MASK_SPRITE_ENABLE; 2100 } 2101 2102 intel_de_write(display, psr_debug_reg(display, cpu_transcoder), mask); 2103 2104 psr_irq_control(intel_dp); 2105 2106 /* 2107 * TODO: if future platforms supports DC3CO in more than one 2108 * transcoder, EXITLINE will need to be unset when disabling PSR 2109 */ 2110 if (intel_dp->psr.dc3co_exitline) 2111 intel_de_rmw(display, 2112 TRANS_EXITLINE(display, cpu_transcoder), 2113 EXITLINE_MASK, 2114 intel_dp->psr.dc3co_exitline << EXITLINE_SHIFT | EXITLINE_ENABLE); 2115 2116 if (HAS_PSR_HW_TRACKING(display) && HAS_PSR2_SEL_FETCH(display)) 2117 intel_de_rmw(display, CHICKEN_PAR1_1, IGNORE_PSR2_HW_TRACKING, 2118 intel_dp->psr.psr2_sel_fetch_enabled ? 2119 IGNORE_PSR2_HW_TRACKING : 0); 2120 2121 /* 2122 * Wa_16013835468 2123 * Wa_14015648006 2124 */ 2125 wm_optimization_wa(intel_dp, crtc_state); 2126 2127 if (intel_dp->psr.sel_update_enabled) { 2128 if (DISPLAY_VER(display) == 9) 2129 intel_de_rmw(display, CHICKEN_TRANS(display, cpu_transcoder), 0, 2130 PSR2_VSC_ENABLE_PROG_HEADER | 2131 PSR2_ADD_VERTICAL_LINE_COUNT); 2132 2133 /* 2134 * Wa_16014451276:adlp,mtl[a0,b0] 2135 * All supported adlp panels have 1-based X granularity, this may 2136 * cause issues if non-supported panels are used. 2137 */ 2138 if (!intel_dp->psr.panel_replay_enabled && 2139 (IS_DISPLAY_VERx100_STEP(display, 1400, STEP_A0, STEP_B0) || 2140 display->platform.alderlake_p)) 2141 intel_de_rmw(display, CHICKEN_TRANS(display, cpu_transcoder), 2142 0, ADLP_1_BASED_X_GRANULARITY); 2143 2144 /* Wa_16012604467:adlp,mtl[a0,b0] */ 2145 if (!intel_dp->psr.panel_replay_enabled && 2146 IS_DISPLAY_VERx100_STEP(display, 1400, STEP_A0, STEP_B0)) 2147 intel_de_rmw(display, 2148 MTL_CLKGATE_DIS_TRANS(display, cpu_transcoder), 2149 0, 2150 MTL_CLKGATE_DIS_TRANS_DMASC_GATING_DIS); 2151 else if (display->platform.alderlake_p) 2152 intel_de_rmw(display, CLKGATE_DIS_MISC, 0, 2153 CLKGATE_DIS_MISC_DMASC_GATING_DIS); 2154 } 2155 2156 /* Wa_16025596647 */ 2157 if ((DISPLAY_VER(display) == 20 || 2158 IS_DISPLAY_VERx100_STEP(display, 3000, STEP_A0, STEP_B0)) && 2159 !intel_dp->psr.panel_replay_enabled) 2160 intel_dmc_block_pkgc(display, intel_dp->psr.pipe, true); 2161 2162 intel_alpm_configure(intel_dp, crtc_state); 2163 2164 if (HAS_PSR_TRANS_PUSH_FRAME_CHANGE(display)) 2165 intel_vrr_psr_frame_change_enable(crtc_state); 2166 } 2167 2168 static bool psr_interrupt_error_check(struct intel_dp *intel_dp) 2169 { 2170 struct intel_display *display = to_intel_display(intel_dp); 2171 enum transcoder cpu_transcoder = intel_dp->psr.transcoder; 2172 u32 val; 2173 2174 if (intel_dp->psr.panel_replay_enabled) 2175 goto no_err; 2176 2177 /* 2178 * If a PSR error happened and the driver is reloaded, the EDP_PSR_IIR 2179 * will still keep the error set even after the reset done in the 2180 * irq_preinstall and irq_uninstall hooks. 2181 * And enabling in this situation cause the screen to freeze in the 2182 * first time that PSR HW tries to activate so lets keep PSR disabled 2183 * to avoid any rendering problems. 2184 */ 2185 val = intel_de_read(display, psr_iir_reg(display, cpu_transcoder)); 2186 val &= psr_irq_psr_error_bit_get(intel_dp); 2187 if (val) { 2188 intel_dp->psr.sink_not_reliable = true; 2189 drm_dbg_kms(display->drm, 2190 "PSR interruption error set, not enabling PSR\n"); 2191 return false; 2192 } 2193 2194 no_err: 2195 return true; 2196 } 2197 2198 static void intel_psr_enable_locked(struct intel_dp *intel_dp, 2199 const struct intel_crtc_state *crtc_state) 2200 { 2201 struct intel_display *display = to_intel_display(intel_dp); 2202 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 2203 u32 val; 2204 2205 drm_WARN_ON(display->drm, intel_dp->psr.enabled); 2206 2207 intel_dp->psr.sel_update_enabled = crtc_state->has_sel_update; 2208 intel_dp->psr.panel_replay_enabled = crtc_state->has_panel_replay; 2209 intel_dp->psr.busy_frontbuffer_bits = 0; 2210 intel_dp->psr.pipe = to_intel_crtc(crtc_state->uapi.crtc)->pipe; 2211 intel_dp->psr.transcoder = crtc_state->cpu_transcoder; 2212 /* DC5/DC6 requires at least 6 idle frames */ 2213 val = usecs_to_jiffies(intel_get_frame_time_us(crtc_state) * 6); 2214 intel_dp->psr.dc3co_exit_delay = val; 2215 intel_dp->psr.dc3co_exitline = crtc_state->dc3co_exitline; 2216 intel_dp->psr.psr2_sel_fetch_enabled = crtc_state->enable_psr2_sel_fetch; 2217 intel_dp->psr.su_region_et_enabled = crtc_state->enable_psr2_su_region_et; 2218 intel_dp->psr.psr2_sel_fetch_cff_enabled = false; 2219 intel_dp->psr.req_psr2_sdp_prior_scanline = 2220 crtc_state->req_psr2_sdp_prior_scanline; 2221 intel_dp->psr.active_non_psr_pipes = crtc_state->active_non_psr_pipes; 2222 intel_dp->psr.pkg_c_latency_used = crtc_state->pkg_c_latency_used; 2223 intel_dp->psr.io_wake_lines = crtc_state->alpm_state.io_wake_lines; 2224 intel_dp->psr.fast_wake_lines = crtc_state->alpm_state.fast_wake_lines; 2225 intel_dp->psr.entry_setup_frames = crtc_state->entry_setup_frames; 2226 2227 if (!psr_interrupt_error_check(intel_dp)) 2228 return; 2229 2230 if (intel_dp->psr.panel_replay_enabled) 2231 drm_dbg_kms(display->drm, "Enabling Panel Replay\n"); 2232 else 2233 drm_dbg_kms(display->drm, "Enabling PSR%s\n", 2234 intel_dp->psr.sel_update_enabled ? "2" : "1"); 2235 2236 /* 2237 * Enabling sink PSR/Panel Replay here only for PSR. Panel Replay enable 2238 * bit is already written at this point. Sink ALPM is enabled here for 2239 * PSR and Panel Replay. See 2240 * intel_psr_panel_replay_enable_sink. Modifiers/options: 2241 * - Selective Update 2242 * - Region Early Transport 2243 * - Selective Update Region Scanline Capture 2244 * - VSC_SDP_CRC 2245 * - HPD on different Errors 2246 * - CRC verification 2247 * are written for PSR and Panel Replay here. 2248 */ 2249 intel_psr_enable_sink(intel_dp, crtc_state); 2250 2251 if (intel_dp_is_edp(intel_dp)) 2252 intel_snps_phy_update_psr_power_state(&dig_port->base, true); 2253 2254 intel_psr_enable_source(intel_dp, crtc_state); 2255 intel_dp->psr.enabled = true; 2256 intel_dp->psr.pause_counter = 0; 2257 2258 /* 2259 * Link_ok is sticky and set here on PSR enable. We can assume link 2260 * training is complete as we never continue to PSR enable with 2261 * untrained link. Link_ok is kept as set until first short pulse 2262 * interrupt. This is targeted to workaround panels stating bad link 2263 * after PSR is enabled. 2264 */ 2265 intel_dp->psr.link_ok = true; 2266 2267 intel_psr_activate(intel_dp); 2268 } 2269 2270 static void intel_psr_exit(struct intel_dp *intel_dp) 2271 { 2272 struct intel_display *display = to_intel_display(intel_dp); 2273 enum transcoder cpu_transcoder = intel_dp->psr.transcoder; 2274 u32 val; 2275 2276 if (!intel_dp->psr.active) { 2277 if (transcoder_has_psr2(display, cpu_transcoder)) { 2278 val = intel_de_read(display, 2279 EDP_PSR2_CTL(display, cpu_transcoder)); 2280 drm_WARN_ON(display->drm, val & EDP_PSR2_ENABLE); 2281 } 2282 2283 val = intel_de_read(display, 2284 psr_ctl_reg(display, cpu_transcoder)); 2285 drm_WARN_ON(display->drm, val & EDP_PSR_ENABLE); 2286 2287 return; 2288 } 2289 2290 if (intel_dp->psr.panel_replay_enabled) { 2291 intel_de_rmw(display, TRANS_DP2_CTL(intel_dp->psr.transcoder), 2292 TRANS_DP2_PANEL_REPLAY_ENABLE, 0); 2293 } else if (intel_dp->psr.sel_update_enabled) { 2294 tgl_disallow_dc3co_on_psr2_exit(intel_dp); 2295 2296 val = intel_de_rmw(display, 2297 EDP_PSR2_CTL(display, cpu_transcoder), 2298 EDP_PSR2_ENABLE, 0); 2299 2300 drm_WARN_ON(display->drm, !(val & EDP_PSR2_ENABLE)); 2301 } else { 2302 if ((DISPLAY_VER(display) == 20 || 2303 IS_DISPLAY_VERx100_STEP(display, 3000, STEP_A0, STEP_B0)) && 2304 intel_dp->psr.pkg_c_latency_used) 2305 intel_dmc_start_pkgc_exit_at_start_of_undelayed_vblank(display, 2306 intel_dp->psr.pipe, 2307 false); 2308 2309 val = intel_de_rmw(display, 2310 psr_ctl_reg(display, cpu_transcoder), 2311 EDP_PSR_ENABLE, 0); 2312 2313 drm_WARN_ON(display->drm, !(val & EDP_PSR_ENABLE)); 2314 } 2315 intel_dp->psr.active = false; 2316 } 2317 2318 static void intel_psr_wait_exit_locked(struct intel_dp *intel_dp) 2319 { 2320 struct intel_display *display = to_intel_display(intel_dp); 2321 enum transcoder cpu_transcoder = intel_dp->psr.transcoder; 2322 intel_reg_t psr_status; 2323 u32 psr_status_mask; 2324 2325 if (intel_dp_is_edp(intel_dp) && (intel_dp->psr.sel_update_enabled || 2326 intel_dp->psr.panel_replay_enabled)) { 2327 psr_status = EDP_PSR2_STATUS(display, cpu_transcoder); 2328 psr_status_mask = EDP_PSR2_STATUS_STATE_MASK; 2329 } else { 2330 psr_status = psr_status_reg(display, cpu_transcoder); 2331 psr_status_mask = EDP_PSR_STATUS_STATE_MASK; 2332 } 2333 2334 /* Wait till PSR is idle */ 2335 if (intel_de_wait_for_clear_ms(display, psr_status, 2336 psr_status_mask, 2000)) 2337 drm_err(display->drm, "Timed out waiting PSR idle state\n"); 2338 } 2339 2340 static void intel_psr_disable_locked(struct intel_dp *intel_dp) 2341 { 2342 struct intel_display *display = to_intel_display(intel_dp); 2343 enum transcoder cpu_transcoder = intel_dp->psr.transcoder; 2344 2345 lockdep_assert_held(&intel_dp->psr.lock); 2346 2347 if (!intel_dp->psr.enabled) 2348 return; 2349 2350 if (intel_dp->psr.panel_replay_enabled) 2351 drm_dbg_kms(display->drm, "Disabling Panel Replay\n"); 2352 else 2353 drm_dbg_kms(display->drm, "Disabling PSR%s\n", 2354 intel_dp->psr.sel_update_enabled ? "2" : "1"); 2355 2356 intel_psr_exit(intel_dp); 2357 intel_psr_wait_exit_locked(intel_dp); 2358 2359 /* 2360 * Wa_16013835468 2361 * Wa_14015648006 2362 */ 2363 if (DISPLAY_VER(display) >= 11) 2364 intel_de_rmw(display, GEN8_CHICKEN_DCPR_1, 2365 LATENCY_REPORTING_REMOVED(intel_dp->psr.pipe), 0); 2366 2367 if (intel_dp->psr.sel_update_enabled) { 2368 /* Wa_16012604467:adlp,mtl[a0,b0] */ 2369 if (!intel_dp->psr.panel_replay_enabled && 2370 IS_DISPLAY_VERx100_STEP(display, 1400, STEP_A0, STEP_B0)) 2371 intel_de_rmw(display, 2372 MTL_CLKGATE_DIS_TRANS(display, cpu_transcoder), 2373 MTL_CLKGATE_DIS_TRANS_DMASC_GATING_DIS, 0); 2374 else if (display->platform.alderlake_p) 2375 intel_de_rmw(display, CLKGATE_DIS_MISC, 2376 CLKGATE_DIS_MISC_DMASC_GATING_DIS, 0); 2377 } 2378 2379 if (intel_dp_is_edp(intel_dp)) 2380 intel_snps_phy_update_psr_power_state(&dp_to_dig_port(intel_dp)->base, false); 2381 2382 if (intel_dp->psr.panel_replay_enabled && intel_dp_is_edp(intel_dp)) 2383 intel_alpm_disable(intel_dp); 2384 2385 /* Disable PSR on Sink */ 2386 if (!intel_dp->psr.panel_replay_enabled) { 2387 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, 0); 2388 2389 if (intel_dp->psr.sel_update_enabled) 2390 drm_dp_dpcd_writeb(&intel_dp->aux, 2391 DP_RECEIVER_ALPM_CONFIG, 0); 2392 } 2393 2394 /* Wa_16025596647 */ 2395 if ((DISPLAY_VER(display) == 20 || 2396 IS_DISPLAY_VERx100_STEP(display, 3000, STEP_A0, STEP_B0)) && 2397 !intel_dp->psr.panel_replay_enabled) 2398 intel_dmc_block_pkgc(display, intel_dp->psr.pipe, false); 2399 2400 intel_dp->psr.enabled = false; 2401 intel_dp->psr.panel_replay_enabled = false; 2402 intel_dp->psr.sel_update_enabled = false; 2403 intel_dp->psr.psr2_sel_fetch_enabled = false; 2404 intel_dp->psr.su_region_et_enabled = false; 2405 intel_dp->psr.psr2_sel_fetch_cff_enabled = false; 2406 intel_dp->psr.active_non_psr_pipes = 0; 2407 intel_dp->psr.pkg_c_latency_used = 0; 2408 } 2409 2410 /** 2411 * intel_psr_disable - Disable PSR 2412 * @intel_dp: Intel DP 2413 * @old_crtc_state: old CRTC state 2414 * 2415 * This function needs to be called before disabling pipe. 2416 */ 2417 void intel_psr_disable(struct intel_dp *intel_dp, 2418 const struct intel_crtc_state *old_crtc_state) 2419 { 2420 struct intel_display *display = to_intel_display(intel_dp); 2421 2422 if (!old_crtc_state->has_psr) 2423 return; 2424 2425 if (drm_WARN_ON(display->drm, !CAN_PSR(intel_dp) && 2426 !CAN_PANEL_REPLAY(intel_dp))) 2427 return; 2428 2429 mutex_lock(&intel_dp->psr.lock); 2430 2431 intel_psr_disable_locked(intel_dp); 2432 2433 intel_dp->psr.link_ok = false; 2434 2435 mutex_unlock(&intel_dp->psr.lock); 2436 cancel_work_sync(&intel_dp->psr.work); 2437 cancel_delayed_work_sync(&intel_dp->psr.dc3co_work); 2438 } 2439 2440 /** 2441 * intel_psr_pause - Pause PSR 2442 * @intel_dp: Intel DP 2443 * 2444 * This function need to be called after enabling psr. 2445 */ 2446 void intel_psr_pause(struct intel_dp *intel_dp) 2447 { 2448 struct intel_psr *psr = &intel_dp->psr; 2449 2450 if (!CAN_PSR(intel_dp) && !CAN_PANEL_REPLAY(intel_dp)) 2451 return; 2452 2453 mutex_lock(&psr->lock); 2454 2455 if (!psr->enabled) { 2456 mutex_unlock(&psr->lock); 2457 return; 2458 } 2459 2460 if (intel_dp->psr.pause_counter++ == 0) { 2461 intel_psr_exit(intel_dp); 2462 intel_psr_wait_exit_locked(intel_dp); 2463 } 2464 2465 mutex_unlock(&psr->lock); 2466 2467 cancel_work_sync(&psr->work); 2468 cancel_delayed_work_sync(&psr->dc3co_work); 2469 } 2470 2471 /** 2472 * intel_psr_resume - Resume PSR 2473 * @intel_dp: Intel DP 2474 * 2475 * This function need to be called after pausing psr. 2476 */ 2477 void intel_psr_resume(struct intel_dp *intel_dp) 2478 { 2479 struct intel_display *display = to_intel_display(intel_dp); 2480 struct intel_psr *psr = &intel_dp->psr; 2481 2482 if (!CAN_PSR(intel_dp) && !CAN_PANEL_REPLAY(intel_dp)) 2483 return; 2484 2485 mutex_lock(&psr->lock); 2486 2487 if (!psr->enabled) 2488 goto out; 2489 2490 if (!psr->pause_counter) { 2491 drm_warn(display->drm, "Unbalanced PSR pause/resume!\n"); 2492 goto out; 2493 } 2494 2495 if (--intel_dp->psr.pause_counter == 0) 2496 intel_psr_activate(intel_dp); 2497 2498 out: 2499 mutex_unlock(&psr->lock); 2500 } 2501 2502 /** 2503 * intel_psr_needs_vblank_notification - Check if PSR need vblank enable/disable 2504 * notification. 2505 * @crtc_state: CRTC status 2506 * 2507 * We need to block DC6 entry in case of Panel Replay as enabling VBI doesn't 2508 * prevent it in case of Panel Replay. Panel Replay switches main link off on 2509 * DC entry. This means vblank interrupts are not fired and is a problem if 2510 * user-space is polling for vblank events. Also Wa_16025596647 needs 2511 * information when vblank is enabled/disabled. 2512 */ 2513 bool intel_psr_needs_vblank_notification(const struct intel_crtc_state *crtc_state) 2514 { 2515 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2516 struct intel_display *display = to_intel_display(crtc_state); 2517 struct intel_encoder *encoder; 2518 2519 for_each_encoder_on_crtc(crtc->base.dev, &crtc->base, encoder) { 2520 struct intel_dp *intel_dp; 2521 2522 if (!intel_encoder_is_dp(encoder)) 2523 continue; 2524 2525 intel_dp = enc_to_intel_dp(encoder); 2526 2527 if (!intel_dp_is_edp(intel_dp)) 2528 continue; 2529 2530 if (CAN_PANEL_REPLAY(intel_dp)) 2531 return true; 2532 2533 if ((DISPLAY_VER(display) == 20 || 2534 IS_DISPLAY_VERx100_STEP(display, 3000, STEP_A0, STEP_B0)) && 2535 CAN_PSR(intel_dp)) 2536 return true; 2537 } 2538 2539 return false; 2540 } 2541 2542 /** 2543 * intel_psr_trigger_frame_change_event - Trigger "Frame Change" event 2544 * @dsb: DSB context 2545 * @state: the atomic state 2546 * @crtc: the CRTC 2547 * 2548 * Generate PSR "Frame Change" event. 2549 */ 2550 void intel_psr_trigger_frame_change_event(struct intel_dsb *dsb, 2551 struct intel_atomic_state *state, 2552 struct intel_crtc *crtc) 2553 { 2554 const struct intel_crtc_state *crtc_state = 2555 intel_pre_commit_crtc_state(state, crtc); 2556 struct intel_display *display = to_intel_display(crtc); 2557 2558 if (!crtc_state->has_psr || intel_psr_use_trans_push(crtc_state)) 2559 return; 2560 2561 intel_de_write_dsb(display, dsb, 2562 CURSURFLIVE(display, crtc->pipe), 0); 2563 } 2564 2565 /** 2566 * intel_psr_min_set_context_latency - Minimum 'set context latency' lines needed by PSR 2567 * @crtc_state: the crtc state 2568 * 2569 * Return minimum SCL lines/delay needed by PSR. 2570 */ 2571 int intel_psr_min_set_context_latency(const struct intel_crtc_state *crtc_state) 2572 { 2573 2574 return _intel_psr_min_set_context_latency(crtc_state, 2575 crtc_state->has_panel_replay, 2576 crtc_state->has_sel_update); 2577 } 2578 2579 static u32 man_trk_ctl_enable_bit_get(struct intel_display *display) 2580 { 2581 return display->platform.alderlake_p || DISPLAY_VER(display) >= 14 ? 0 : 2582 PSR2_MAN_TRK_CTL_ENABLE; 2583 } 2584 2585 static u32 man_trk_ctl_single_full_frame_bit_get(struct intel_display *display) 2586 { 2587 return display->platform.alderlake_p || DISPLAY_VER(display) >= 14 ? 2588 ADLP_PSR2_MAN_TRK_CTL_SF_SINGLE_FULL_FRAME : 2589 PSR2_MAN_TRK_CTL_SF_SINGLE_FULL_FRAME; 2590 } 2591 2592 static u32 man_trk_ctl_partial_frame_bit_get(struct intel_display *display) 2593 { 2594 return display->platform.alderlake_p || DISPLAY_VER(display) >= 14 ? 2595 ADLP_PSR2_MAN_TRK_CTL_SF_PARTIAL_FRAME_UPDATE : 2596 PSR2_MAN_TRK_CTL_SF_PARTIAL_FRAME_UPDATE; 2597 } 2598 2599 static u32 man_trk_ctl_continuos_full_frame(struct intel_display *display) 2600 { 2601 return display->platform.alderlake_p || DISPLAY_VER(display) >= 14 ? 2602 ADLP_PSR2_MAN_TRK_CTL_SF_CONTINUOS_FULL_FRAME : 2603 PSR2_MAN_TRK_CTL_SF_CONTINUOS_FULL_FRAME; 2604 } 2605 2606 static void intel_psr_force_update(struct intel_dp *intel_dp) 2607 { 2608 struct intel_display *display = to_intel_display(intel_dp); 2609 2610 /* 2611 * Display WA #0884: skl+ 2612 * This documented WA for bxt can be safely applied 2613 * broadly so we can force HW tracking to exit PSR 2614 * instead of disabling and re-enabling. 2615 * Workaround tells us to write 0 to CUR_SURFLIVE_A, 2616 * but it makes more sense write to the current active 2617 * pipe. 2618 * 2619 * This workaround do not exist for platforms with display 10 or newer 2620 * but testing proved that it works for up display 13, for newer 2621 * than that testing will be needed. 2622 */ 2623 intel_de_write(display, CURSURFLIVE(display, intel_dp->psr.pipe), 0); 2624 } 2625 2626 void intel_psr2_program_trans_man_trk_ctl(struct intel_dsb *dsb, 2627 const struct intel_crtc_state *crtc_state) 2628 { 2629 struct intel_display *display = to_intel_display(crtc_state); 2630 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2631 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 2632 struct intel_encoder *encoder; 2633 2634 if (!crtc_state->enable_psr2_sel_fetch) 2635 return; 2636 2637 for_each_intel_encoder_mask_with_psr(display->drm, encoder, 2638 crtc_state->uapi.encoder_mask) { 2639 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2640 2641 if (!dsb) 2642 lockdep_assert_held(&intel_dp->psr.lock); 2643 2644 if (DISPLAY_VER(display) < 20 && intel_dp->psr.psr2_sel_fetch_cff_enabled) 2645 return; 2646 break; 2647 } 2648 2649 intel_de_write_dsb(display, dsb, 2650 PSR2_MAN_TRK_CTL(display, cpu_transcoder), 2651 crtc_state->psr2_man_track_ctl); 2652 2653 if (!crtc_state->enable_psr2_su_region_et) 2654 return; 2655 2656 intel_de_write_dsb(display, dsb, PIPE_SRCSZ_ERLY_TPT(crtc->pipe), 2657 crtc_state->pipe_srcsz_early_tpt); 2658 2659 if (!crtc_state->dsc.compression_enable) 2660 return; 2661 2662 intel_dsc_su_et_parameters_configure(dsb, encoder, crtc_state, 2663 drm_rect_height(&crtc_state->psr2_su_area)); 2664 } 2665 2666 static void psr2_man_trk_ctl_calc(struct intel_crtc_state *crtc_state, 2667 bool full_update) 2668 { 2669 struct intel_display *display = to_intel_display(crtc_state); 2670 u32 val = man_trk_ctl_enable_bit_get(display); 2671 2672 /* SF partial frame enable has to be set even on full update */ 2673 val |= man_trk_ctl_partial_frame_bit_get(display); 2674 2675 if (full_update) { 2676 val |= man_trk_ctl_continuos_full_frame(display); 2677 goto exit; 2678 } 2679 2680 if (crtc_state->psr2_su_area.y1 == -1) 2681 goto exit; 2682 2683 if (display->platform.alderlake_p || DISPLAY_VER(display) >= 14) { 2684 val |= ADLP_PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR(crtc_state->psr2_su_area.y1); 2685 val |= ADLP_PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR(crtc_state->psr2_su_area.y2 - 1); 2686 } else { 2687 drm_WARN_ON(crtc_state->uapi.crtc->dev, 2688 crtc_state->psr2_su_area.y1 % 4 || 2689 crtc_state->psr2_su_area.y2 % 4); 2690 2691 val |= PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR( 2692 crtc_state->psr2_su_area.y1 / 4 + 1); 2693 val |= PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR( 2694 crtc_state->psr2_su_area.y2 / 4 + 1); 2695 } 2696 exit: 2697 crtc_state->psr2_man_track_ctl = val; 2698 } 2699 2700 static u32 psr2_pipe_srcsz_early_tpt_calc(struct intel_crtc_state *crtc_state, 2701 bool full_update) 2702 { 2703 int width, height; 2704 2705 if (!crtc_state->enable_psr2_su_region_et || full_update) 2706 return 0; 2707 2708 width = drm_rect_width(&crtc_state->psr2_su_area); 2709 height = drm_rect_height(&crtc_state->psr2_su_area); 2710 2711 return PIPESRC_WIDTH(width - 1) | PIPESRC_HEIGHT(height - 1); 2712 } 2713 2714 static void clip_area_update(struct drm_rect *overlap_damage_area, 2715 struct drm_rect *damage_area, 2716 struct drm_rect *display_area) 2717 { 2718 if (!drm_rect_intersect(damage_area, display_area)) 2719 return; 2720 2721 if (overlap_damage_area->y1 == -1) { 2722 overlap_damage_area->y1 = damage_area->y1; 2723 overlap_damage_area->y2 = damage_area->y2; 2724 return; 2725 } 2726 2727 if (damage_area->y1 < overlap_damage_area->y1) 2728 overlap_damage_area->y1 = damage_area->y1; 2729 2730 if (damage_area->y2 > overlap_damage_area->y2) 2731 overlap_damage_area->y2 = damage_area->y2; 2732 } 2733 2734 static bool intel_psr2_sel_fetch_pipe_alignment(struct intel_crtc_state *crtc_state) 2735 { 2736 struct intel_display *display = to_intel_display(crtc_state); 2737 const struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config; 2738 u16 y_alignment; 2739 bool su_area_changed = false; 2740 2741 /* ADLP aligns the SU region to vdsc slice height in case dsc is enabled */ 2742 if (crtc_state->dsc.compression_enable && 2743 (display->platform.alderlake_p || DISPLAY_VER(display) >= 14)) 2744 y_alignment = vdsc_cfg->slice_height; 2745 else 2746 y_alignment = crtc_state->su_y_granularity; 2747 2748 if (crtc_state->psr2_su_area.y1 % y_alignment) { 2749 crtc_state->psr2_su_area.y1 -= crtc_state->psr2_su_area.y1 % y_alignment; 2750 su_area_changed = true; 2751 } 2752 2753 if (crtc_state->psr2_su_area.y2 % y_alignment) { 2754 crtc_state->psr2_su_area.y2 = ((crtc_state->psr2_su_area.y2 / 2755 y_alignment) + 1) * y_alignment; 2756 su_area_changed = true; 2757 } 2758 2759 return su_area_changed; 2760 } 2761 2762 /* 2763 * When early transport is in use we need to extend SU area to cover 2764 * cursor fully when cursor is in SU area. 2765 */ 2766 static void 2767 intel_psr2_sel_fetch_et_alignment(struct intel_atomic_state *state, 2768 struct intel_crtc *crtc, 2769 struct drm_rect *display_area, 2770 bool *cursor_in_su_area) 2771 { 2772 struct intel_crtc_state *crtc_state = intel_atomic_get_new_crtc_state(state, crtc); 2773 struct intel_plane_state *new_plane_state; 2774 struct intel_plane *plane; 2775 int i; 2776 2777 if (!crtc_state->enable_psr2_su_region_et) 2778 return; 2779 2780 for_each_new_intel_plane_in_state(state, plane, new_plane_state, i) { 2781 struct drm_rect inter; 2782 2783 if (new_plane_state->hw.crtc != crtc_state->uapi.crtc) 2784 continue; 2785 2786 if (plane->id != PLANE_CURSOR) 2787 continue; 2788 2789 if (!new_plane_state->uapi.visible) 2790 continue; 2791 2792 inter = crtc_state->psr2_su_area; 2793 if (!drm_rect_intersect(&inter, &new_plane_state->uapi.dst)) 2794 continue; 2795 2796 clip_area_update(&crtc_state->psr2_su_area, &new_plane_state->uapi.dst, 2797 display_area); 2798 *cursor_in_su_area = true; 2799 } 2800 } 2801 2802 /* 2803 * TODO: Not clear how to handle planes with negative position, 2804 * also planes are not updated if they have a negative X 2805 * position so for now doing a full update in this cases 2806 * 2807 * Plane scaling and rotation is not supported by selective fetch and both 2808 * properties can change without a modeset, so need to be check at every 2809 * atomic commit. 2810 */ 2811 static bool psr2_sel_fetch_plane_state_supported(const struct intel_plane_state *plane_state) 2812 { 2813 if (plane_state->uapi.dst.y1 < 0 || 2814 plane_state->uapi.dst.x1 < 0 || 2815 plane_state->scaler_id >= 0 || 2816 plane_state->hw.rotation != DRM_MODE_ROTATE_0) 2817 return false; 2818 2819 return true; 2820 } 2821 2822 /* 2823 * Check for pipe properties that is not supported by selective fetch. 2824 * 2825 * TODO: pipe scaling causes a modeset but skl_update_scaler_crtc() is executed 2826 * after intel_psr_compute_config(), so for now keeping PSR2 selective fetch 2827 * enabled and going to the full update path. 2828 */ 2829 static bool psr2_sel_fetch_pipe_state_supported(const struct intel_crtc_state *crtc_state) 2830 { 2831 if (crtc_state->scaler_state.scaler_id >= 0 || 2832 crtc_state->async_flip_planes) 2833 return false; 2834 2835 return true; 2836 } 2837 2838 /* Wa 14019834836 */ 2839 static void intel_psr_apply_pr_link_on_su_wa(struct intel_crtc_state *crtc_state) 2840 { 2841 struct intel_display *display = to_intel_display(crtc_state); 2842 struct intel_encoder *encoder; 2843 int hactive_limit; 2844 2845 if (crtc_state->psr2_su_area.y1 != 0 || 2846 crtc_state->psr2_su_area.y2 != 0) 2847 return; 2848 2849 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) 2850 hactive_limit = intel_dp_is_uhbr(crtc_state) ? 1230 : 546; 2851 else 2852 hactive_limit = intel_dp_is_uhbr(crtc_state) ? 615 : 273; 2853 2854 if (crtc_state->hw.adjusted_mode.hdisplay < hactive_limit) 2855 return; 2856 2857 for_each_intel_encoder_mask_with_psr(display->drm, encoder, 2858 crtc_state->uapi.encoder_mask) { 2859 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2860 2861 if (!intel_dp_is_edp(intel_dp) && 2862 intel_dp->psr.panel_replay_enabled && 2863 intel_dp->psr.sel_update_enabled) { 2864 crtc_state->psr2_su_area.y2++; 2865 return; 2866 } 2867 } 2868 } 2869 2870 static void 2871 intel_psr_apply_su_area_workarounds(struct intel_crtc_state *crtc_state) 2872 { 2873 struct intel_display *display = to_intel_display(crtc_state); 2874 2875 /* Wa_14014971492 */ 2876 if (!crtc_state->has_panel_replay && 2877 ((IS_DISPLAY_VERx100_STEP(display, 1400, STEP_A0, STEP_B0) || 2878 display->platform.alderlake_p || display->platform.tigerlake)) && 2879 crtc_state->splitter.enable) 2880 crtc_state->psr2_su_area.y1 = 0; 2881 2882 /* Wa 14019834836 */ 2883 if (DISPLAY_VER(display) == 30) 2884 intel_psr_apply_pr_link_on_su_wa(crtc_state); 2885 } 2886 2887 int intel_psr2_sel_fetch_update(struct intel_atomic_state *state, 2888 struct intel_crtc *crtc) 2889 { 2890 struct intel_display *display = to_intel_display(state); 2891 struct intel_crtc_state *crtc_state = intel_atomic_get_new_crtc_state(state, crtc); 2892 struct intel_plane_state *new_plane_state, *old_plane_state; 2893 struct intel_plane *plane; 2894 struct drm_rect display_area = { 2895 .x1 = 0, 2896 .y1 = 0, 2897 .x2 = crtc_state->hw.adjusted_mode.crtc_hdisplay, 2898 .y2 = crtc_state->hw.adjusted_mode.crtc_vdisplay, 2899 }; 2900 bool full_update = false, su_area_changed; 2901 int i, ret; 2902 2903 if (!crtc_state->enable_psr2_sel_fetch) 2904 return 0; 2905 2906 if (!psr2_sel_fetch_pipe_state_supported(crtc_state)) { 2907 full_update = true; 2908 goto skip_sel_fetch_set_loop; 2909 } 2910 2911 crtc_state->psr2_su_area.x1 = 0; 2912 crtc_state->psr2_su_area.y1 = -1; 2913 crtc_state->psr2_su_area.x2 = drm_rect_width(&display_area); 2914 crtc_state->psr2_su_area.y2 = -1; 2915 2916 /* 2917 * Calculate minimal selective fetch area of each plane and calculate 2918 * the pipe damaged area. 2919 * In the next loop the plane selective fetch area will actually be set 2920 * using whole pipe damaged area. 2921 */ 2922 for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state, 2923 new_plane_state, i) { 2924 struct drm_rect src, damaged_area = { .x1 = 0, .y1 = -1, 2925 .x2 = INT_MAX }; 2926 2927 if (new_plane_state->hw.crtc != crtc_state->uapi.crtc) 2928 continue; 2929 2930 if (!new_plane_state->uapi.visible && 2931 !old_plane_state->uapi.visible) 2932 continue; 2933 2934 if (!psr2_sel_fetch_plane_state_supported(new_plane_state)) { 2935 full_update = true; 2936 break; 2937 } 2938 2939 /* 2940 * If visibility or plane moved, mark the whole plane area as 2941 * damaged as it needs to be complete redraw in the new and old 2942 * position. 2943 */ 2944 if (new_plane_state->uapi.visible != old_plane_state->uapi.visible || 2945 !drm_rect_equals(&new_plane_state->uapi.dst, 2946 &old_plane_state->uapi.dst)) { 2947 if (old_plane_state->uapi.visible) { 2948 damaged_area.y1 = old_plane_state->uapi.dst.y1; 2949 damaged_area.y2 = old_plane_state->uapi.dst.y2; 2950 clip_area_update(&crtc_state->psr2_su_area, &damaged_area, 2951 &display_area); 2952 } 2953 2954 if (new_plane_state->uapi.visible) { 2955 damaged_area.y1 = new_plane_state->uapi.dst.y1; 2956 damaged_area.y2 = new_plane_state->uapi.dst.y2; 2957 clip_area_update(&crtc_state->psr2_su_area, &damaged_area, 2958 &display_area); 2959 } 2960 continue; 2961 } else if (new_plane_state->uapi.alpha != old_plane_state->uapi.alpha) { 2962 /* If alpha changed mark the whole plane area as damaged */ 2963 damaged_area.y1 = new_plane_state->uapi.dst.y1; 2964 damaged_area.y2 = new_plane_state->uapi.dst.y2; 2965 clip_area_update(&crtc_state->psr2_su_area, &damaged_area, 2966 &display_area); 2967 continue; 2968 } 2969 2970 src = drm_plane_state_src(&new_plane_state->uapi); 2971 drm_rect_fp_to_int(&src, &src); 2972 2973 if (!drm_atomic_helper_damage_merged(&old_plane_state->uapi, 2974 &new_plane_state->uapi, &damaged_area)) 2975 continue; 2976 2977 damaged_area.y1 += new_plane_state->uapi.dst.y1 - src.y1; 2978 damaged_area.y2 += new_plane_state->uapi.dst.y1 - src.y1; 2979 damaged_area.x1 += new_plane_state->uapi.dst.x1 - src.x1; 2980 damaged_area.x2 += new_plane_state->uapi.dst.x1 - src.x1; 2981 2982 clip_area_update(&crtc_state->psr2_su_area, &damaged_area, &display_area); 2983 } 2984 2985 /* 2986 * TODO: For now we are just using full update in case 2987 * selective fetch area calculation fails. To optimize this we 2988 * should identify cases where this happens and fix the area 2989 * calculation for those. 2990 */ 2991 if (crtc_state->psr2_su_area.y1 == -1) { 2992 drm_info_once(display->drm, 2993 "Selective fetch area calculation failed in pipe %c\n", 2994 pipe_name(crtc->pipe)); 2995 full_update = true; 2996 } 2997 2998 if (full_update) 2999 goto skip_sel_fetch_set_loop; 3000 3001 intel_psr_apply_su_area_workarounds(crtc_state); 3002 3003 ret = drm_atomic_add_affected_planes(&state->base, &crtc->base); 3004 if (ret) 3005 return ret; 3006 3007 do { 3008 bool cursor_in_su_area = false; 3009 3010 /* 3011 * Adjust su area to cover cursor fully as necessary 3012 * (early transport). This needs to be done after 3013 * drm_atomic_add_affected_planes to ensure visible 3014 * cursor is added into affected planes even when 3015 * cursor is not updated by itself. 3016 */ 3017 intel_psr2_sel_fetch_et_alignment(state, crtc, &display_area, 3018 &cursor_in_su_area); 3019 3020 su_area_changed = intel_psr2_sel_fetch_pipe_alignment(crtc_state); 3021 3022 /* 3023 * If the cursor was outside the SU area before 3024 * alignment, the alignment step (which only expands 3025 * SU) may pull the cursor partially inside, so we 3026 * must run ET alignment again to fully cover it. But 3027 * if the cursor was already fully inside before 3028 * alignment, expanding the SU area won't change that, 3029 * so no further work is needed. 3030 */ 3031 if (cursor_in_su_area) 3032 break; 3033 } while (su_area_changed); 3034 3035 /* 3036 * Now that we have the pipe damaged area check if it intersect with 3037 * every plane, if it does set the plane selective fetch area. 3038 */ 3039 for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state, 3040 new_plane_state, i) { 3041 struct drm_rect *sel_fetch_area, inter; 3042 struct intel_plane *linked = new_plane_state->planar_linked_plane; 3043 3044 if (new_plane_state->hw.crtc != crtc_state->uapi.crtc || 3045 !new_plane_state->uapi.visible) 3046 continue; 3047 3048 inter = crtc_state->psr2_su_area; 3049 sel_fetch_area = &new_plane_state->psr2_sel_fetch_area; 3050 if (!drm_rect_intersect(&inter, &new_plane_state->uapi.dst)) { 3051 sel_fetch_area->y1 = -1; 3052 sel_fetch_area->y2 = -1; 3053 /* 3054 * if plane sel fetch was previously enabled -> 3055 * disable it 3056 */ 3057 if (drm_rect_height(&old_plane_state->psr2_sel_fetch_area) > 0) 3058 crtc_state->update_planes |= BIT(plane->id); 3059 3060 continue; 3061 } 3062 3063 if (!psr2_sel_fetch_plane_state_supported(new_plane_state)) { 3064 full_update = true; 3065 break; 3066 } 3067 3068 sel_fetch_area = &new_plane_state->psr2_sel_fetch_area; 3069 sel_fetch_area->y1 = inter.y1 - new_plane_state->uapi.dst.y1; 3070 sel_fetch_area->y2 = inter.y2 - new_plane_state->uapi.dst.y1; 3071 crtc_state->update_planes |= BIT(plane->id); 3072 3073 /* 3074 * Sel_fetch_area is calculated for UV plane. Use 3075 * same area for Y plane as well. 3076 */ 3077 if (linked) { 3078 struct intel_plane_state *linked_new_plane_state; 3079 struct drm_rect *linked_sel_fetch_area; 3080 3081 linked_new_plane_state = intel_atomic_get_plane_state(state, linked); 3082 if (IS_ERR(linked_new_plane_state)) 3083 return PTR_ERR(linked_new_plane_state); 3084 3085 linked_sel_fetch_area = &linked_new_plane_state->psr2_sel_fetch_area; 3086 linked_sel_fetch_area->y1 = sel_fetch_area->y1; 3087 linked_sel_fetch_area->y2 = sel_fetch_area->y2; 3088 crtc_state->update_planes |= BIT(linked->id); 3089 } 3090 } 3091 3092 skip_sel_fetch_set_loop: 3093 if (full_update) 3094 clip_area_update(&crtc_state->psr2_su_area, &display_area, 3095 &display_area); 3096 3097 psr2_man_trk_ctl_calc(crtc_state, full_update); 3098 crtc_state->pipe_srcsz_early_tpt = 3099 psr2_pipe_srcsz_early_tpt_calc(crtc_state, full_update); 3100 return 0; 3101 } 3102 3103 void intel_psr2_panic_force_full_update(const struct intel_crtc_state *crtc_state) 3104 { 3105 struct intel_display *display = to_intel_display(crtc_state); 3106 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 3107 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 3108 u32 val = man_trk_ctl_enable_bit_get(display); 3109 3110 /* SF partial frame enable has to be set even on full update */ 3111 val |= man_trk_ctl_partial_frame_bit_get(display); 3112 val |= man_trk_ctl_continuos_full_frame(display); 3113 3114 /* Directly write the register */ 3115 intel_de_write_fw(display, PSR2_MAN_TRK_CTL(display, cpu_transcoder), val); 3116 3117 if (!crtc_state->enable_psr2_su_region_et) 3118 return; 3119 3120 intel_de_write_fw(display, PIPE_SRCSZ_ERLY_TPT(crtc->pipe), 0); 3121 } 3122 3123 void intel_psr_pre_plane_update(struct intel_atomic_state *state, 3124 struct intel_crtc *crtc) 3125 { 3126 struct intel_display *display = to_intel_display(state); 3127 const struct intel_crtc_state *old_crtc_state = 3128 intel_atomic_get_old_crtc_state(state, crtc); 3129 const struct intel_crtc_state *new_crtc_state = 3130 intel_atomic_get_new_crtc_state(state, crtc); 3131 struct intel_encoder *encoder; 3132 3133 if (!HAS_PSR(display)) 3134 return; 3135 3136 for_each_intel_encoder_mask_with_psr(state->base.dev, encoder, 3137 old_crtc_state->uapi.encoder_mask) { 3138 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 3139 struct intel_psr *psr = &intel_dp->psr; 3140 3141 mutex_lock(&psr->lock); 3142 3143 if (!new_crtc_state->has_psr) 3144 psr->no_psr_reason = new_crtc_state->no_psr_reason; 3145 3146 if (psr->enabled) { 3147 /* 3148 * Reasons to disable: 3149 * - PSR disabled in new state 3150 * - All planes will go inactive 3151 * - Changing between PSR versions 3152 * - Region Early Transport changing 3153 * - Display WA #1136: skl, bxt 3154 */ 3155 if (intel_crtc_needs_modeset(new_crtc_state) || 3156 new_crtc_state->update_m_n || 3157 new_crtc_state->update_lrr || 3158 !new_crtc_state->has_psr || 3159 !new_crtc_state->active_planes || 3160 new_crtc_state->has_sel_update != psr->sel_update_enabled || 3161 new_crtc_state->enable_psr2_su_region_et != psr->su_region_et_enabled || 3162 new_crtc_state->has_panel_replay != psr->panel_replay_enabled || 3163 (DISPLAY_VER(display) < 11 && new_crtc_state->wm_level_disabled)) 3164 intel_psr_disable_locked(intel_dp); 3165 else if (new_crtc_state->wm_level_disabled) 3166 /* Wa_14015648006 */ 3167 wm_optimization_wa(intel_dp, new_crtc_state); 3168 } 3169 3170 mutex_unlock(&psr->lock); 3171 } 3172 } 3173 3174 static void 3175 verify_panel_replay_dsc_state(const struct intel_crtc_state *crtc_state) 3176 { 3177 struct intel_display *display = to_intel_display(crtc_state); 3178 3179 if (!crtc_state->has_panel_replay) 3180 return; 3181 3182 drm_WARN_ON(display->drm, 3183 intel_dsc_enabled_on_link(crtc_state) && 3184 crtc_state->panel_replay_dsc_support == 3185 INTEL_DP_PANEL_REPLAY_DSC_NOT_SUPPORTED); 3186 } 3187 3188 void intel_psr_post_plane_update(struct intel_atomic_state *state, 3189 struct intel_crtc *crtc) 3190 { 3191 struct intel_display *display = to_intel_display(state); 3192 const struct intel_crtc_state *crtc_state = 3193 intel_atomic_get_new_crtc_state(state, crtc); 3194 struct intel_encoder *encoder; 3195 3196 if (!crtc_state->has_psr) 3197 return; 3198 3199 verify_panel_replay_dsc_state(crtc_state); 3200 3201 for_each_intel_encoder_mask_with_psr(state->base.dev, encoder, 3202 crtc_state->uapi.encoder_mask) { 3203 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 3204 struct intel_psr *psr = &intel_dp->psr; 3205 bool keep_disabled = false; 3206 3207 mutex_lock(&psr->lock); 3208 3209 drm_WARN_ON(display->drm, 3210 psr->enabled && !crtc_state->active_planes); 3211 3212 if (psr->sink_not_reliable) 3213 keep_disabled = true; 3214 3215 if (!crtc_state->active_planes) { 3216 psr->no_psr_reason = "All planes inactive"; 3217 keep_disabled = true; 3218 } 3219 3220 /* Display WA #1136: skl, bxt */ 3221 if (DISPLAY_VER(display) < 11 && crtc_state->wm_level_disabled) { 3222 psr->no_psr_reason = "Workaround #1136 for skl, bxt"; 3223 keep_disabled = true; 3224 } 3225 3226 if (!psr->enabled && !keep_disabled) 3227 intel_psr_enable_locked(intel_dp, crtc_state); 3228 else if (psr->enabled && !crtc_state->wm_level_disabled) 3229 /* Wa_14015648006 */ 3230 wm_optimization_wa(intel_dp, crtc_state); 3231 3232 /* Force a PSR exit when enabling CRC to avoid CRC timeouts */ 3233 if (crtc_state->crc_enabled && psr->enabled) 3234 intel_psr_force_update(intel_dp); 3235 3236 /* 3237 * Clear possible busy bits in case we have 3238 * invalidate -> flip -> flush sequence. 3239 */ 3240 intel_dp->psr.busy_frontbuffer_bits = 0; 3241 3242 mutex_unlock(&psr->lock); 3243 } 3244 } 3245 3246 /* 3247 * From bspec: Panel Self Refresh (BDW+) 3248 * Max. time for PSR to idle = Inverse of the refresh rate + 6 ms of 3249 * exit training time + 1.5 ms of aux channel handshake. 50 ms is 3250 * defensive enough to cover everything. 3251 */ 3252 #define PSR_IDLE_TIMEOUT_MS 50 3253 3254 static int 3255 _psr2_ready_for_pipe_update_locked(const struct intel_crtc_state *new_crtc_state, 3256 struct intel_dsb *dsb) 3257 { 3258 struct intel_display *display = to_intel_display(new_crtc_state); 3259 enum transcoder cpu_transcoder = new_crtc_state->cpu_transcoder; 3260 3261 /* 3262 * Any state lower than EDP_PSR2_STATUS_STATE_DEEP_SLEEP is enough. 3263 * As all higher states has bit 4 of PSR2 state set we can just wait for 3264 * EDP_PSR2_STATUS_STATE_DEEP_SLEEP to be cleared. 3265 */ 3266 if (dsb) { 3267 intel_dsb_poll(dsb, EDP_PSR2_STATUS(display, cpu_transcoder), 3268 EDP_PSR2_STATUS_STATE_DEEP_SLEEP, 0, 200, 3269 PSR_IDLE_TIMEOUT_MS * 1000 / 200); 3270 return true; 3271 } 3272 3273 return intel_de_wait_for_clear_ms(display, 3274 EDP_PSR2_STATUS(display, cpu_transcoder), 3275 EDP_PSR2_STATUS_STATE_DEEP_SLEEP, 3276 PSR_IDLE_TIMEOUT_MS); 3277 } 3278 3279 static int 3280 _psr1_ready_for_pipe_update_locked(const struct intel_crtc_state *new_crtc_state, 3281 struct intel_dsb *dsb) 3282 { 3283 struct intel_display *display = to_intel_display(new_crtc_state); 3284 enum transcoder cpu_transcoder = new_crtc_state->cpu_transcoder; 3285 3286 if (dsb) { 3287 intel_dsb_poll(dsb, psr_status_reg(display, cpu_transcoder), 3288 EDP_PSR_STATUS_STATE_MASK, 0, 200, 3289 PSR_IDLE_TIMEOUT_MS * 1000 / 200); 3290 return true; 3291 } 3292 3293 return intel_de_wait_for_clear_ms(display, 3294 psr_status_reg(display, cpu_transcoder), 3295 EDP_PSR_STATUS_STATE_MASK, 3296 PSR_IDLE_TIMEOUT_MS); 3297 } 3298 3299 /** 3300 * intel_psr_wait_for_idle_locked - wait for PSR be ready for a pipe update 3301 * @new_crtc_state: new CRTC state 3302 * 3303 * This function is expected to be called from pipe_update_start() where it is 3304 * not expected to race with PSR enable or disable. 3305 */ 3306 void intel_psr_wait_for_idle_locked(const struct intel_crtc_state *new_crtc_state) 3307 { 3308 struct intel_display *display = to_intel_display(new_crtc_state); 3309 struct intel_encoder *encoder; 3310 3311 if (!new_crtc_state->has_psr) 3312 return; 3313 3314 for_each_intel_encoder_mask_with_psr(display->drm, encoder, 3315 new_crtc_state->uapi.encoder_mask) { 3316 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 3317 int ret; 3318 3319 lockdep_assert_held(&intel_dp->psr.lock); 3320 3321 if (!intel_dp->psr.enabled || intel_dp->psr.panel_replay_enabled) 3322 continue; 3323 3324 if (intel_dp->psr.sel_update_enabled) 3325 ret = _psr2_ready_for_pipe_update_locked(new_crtc_state, 3326 NULL); 3327 else 3328 ret = _psr1_ready_for_pipe_update_locked(new_crtc_state, 3329 NULL); 3330 3331 if (ret) 3332 drm_err(display->drm, 3333 "PSR wait timed out, atomic update may fail\n"); 3334 } 3335 } 3336 3337 void intel_psr_wait_for_idle_dsb(struct intel_dsb *dsb, 3338 const struct intel_crtc_state *new_crtc_state) 3339 { 3340 if (!new_crtc_state->has_psr || new_crtc_state->has_panel_replay) 3341 return; 3342 3343 if (new_crtc_state->has_sel_update) 3344 _psr2_ready_for_pipe_update_locked(new_crtc_state, dsb); 3345 else 3346 _psr1_ready_for_pipe_update_locked(new_crtc_state, dsb); 3347 } 3348 3349 static bool __psr_wait_for_idle_locked(struct intel_dp *intel_dp) 3350 { 3351 struct intel_display *display = to_intel_display(intel_dp); 3352 enum transcoder cpu_transcoder = intel_dp->psr.transcoder; 3353 intel_reg_t reg; 3354 u32 mask; 3355 int err; 3356 3357 if (!intel_dp->psr.enabled) 3358 return false; 3359 3360 if (intel_dp_is_edp(intel_dp) && (intel_dp->psr.sel_update_enabled || 3361 intel_dp->psr.panel_replay_enabled)) { 3362 reg = EDP_PSR2_STATUS(display, cpu_transcoder); 3363 mask = EDP_PSR2_STATUS_STATE_MASK; 3364 } else { 3365 reg = psr_status_reg(display, cpu_transcoder); 3366 mask = EDP_PSR_STATUS_STATE_MASK; 3367 } 3368 3369 mutex_unlock(&intel_dp->psr.lock); 3370 3371 err = intel_de_wait_for_clear_ms(display, reg, mask, 50); 3372 if (err) 3373 drm_err(display->drm, 3374 "Timed out waiting for PSR Idle for re-enable\n"); 3375 3376 /* After the unlocked wait, verify that PSR is still wanted! */ 3377 mutex_lock(&intel_dp->psr.lock); 3378 return err == 0 && intel_dp->psr.enabled && !intel_dp->psr.pause_counter; 3379 } 3380 3381 static int intel_psr_fastset_force(struct intel_display *display) 3382 { 3383 struct drm_connector_list_iter conn_iter; 3384 struct drm_modeset_acquire_ctx ctx; 3385 struct drm_atomic_commit *state; 3386 struct drm_connector *conn; 3387 int err = 0; 3388 3389 state = drm_atomic_commit_alloc(display->drm); 3390 if (!state) 3391 return -ENOMEM; 3392 3393 drm_modeset_acquire_init(&ctx, DRM_MODESET_ACQUIRE_INTERRUPTIBLE); 3394 3395 state->acquire_ctx = &ctx; 3396 to_intel_atomic_state(state)->internal = true; 3397 3398 retry: 3399 drm_connector_list_iter_begin(display->drm, &conn_iter); 3400 drm_for_each_connector_iter(conn, &conn_iter) { 3401 struct drm_connector_state *conn_state; 3402 struct drm_crtc_state *crtc_state; 3403 3404 if (conn->connector_type != DRM_MODE_CONNECTOR_eDP) 3405 continue; 3406 3407 conn_state = drm_atomic_get_connector_state(state, conn); 3408 if (IS_ERR(conn_state)) { 3409 err = PTR_ERR(conn_state); 3410 break; 3411 } 3412 3413 if (!conn_state->crtc) 3414 continue; 3415 3416 crtc_state = drm_atomic_get_crtc_state(state, conn_state->crtc); 3417 if (IS_ERR(crtc_state)) { 3418 err = PTR_ERR(crtc_state); 3419 break; 3420 } 3421 3422 /* Mark mode as changed to trigger a pipe->update() */ 3423 crtc_state->mode_changed = true; 3424 } 3425 drm_connector_list_iter_end(&conn_iter); 3426 3427 if (err == 0) 3428 err = drm_atomic_commit(state); 3429 3430 if (err == -EDEADLK) { 3431 drm_atomic_commit_clear(state); 3432 err = drm_modeset_backoff(&ctx); 3433 if (!err) 3434 goto retry; 3435 } 3436 3437 drm_modeset_drop_locks(&ctx); 3438 drm_modeset_acquire_fini(&ctx); 3439 drm_atomic_commit_put(state); 3440 3441 return err; 3442 } 3443 3444 int intel_psr_debug_set(struct intel_dp *intel_dp, u64 val) 3445 { 3446 struct intel_display *display = to_intel_display(intel_dp); 3447 const u32 mode = val & I915_PSR_DEBUG_MODE_MASK; 3448 const u32 disable_bits = val & (I915_PSR_DEBUG_SU_REGION_ET_DISABLE | 3449 I915_PSR_DEBUG_PANEL_REPLAY_DISABLE); 3450 u32 old_mode, old_disable_bits; 3451 int ret; 3452 3453 if (val & ~(I915_PSR_DEBUG_IRQ | I915_PSR_DEBUG_SU_REGION_ET_DISABLE | 3454 I915_PSR_DEBUG_PANEL_REPLAY_DISABLE | 3455 I915_PSR_DEBUG_MODE_MASK) || 3456 mode > I915_PSR_DEBUG_ENABLE_SEL_FETCH) { 3457 drm_dbg_kms(display->drm, "Invalid debug mask %llx\n", val); 3458 return -EINVAL; 3459 } 3460 3461 ret = mutex_lock_interruptible(&intel_dp->psr.lock); 3462 if (ret) 3463 return ret; 3464 3465 old_mode = intel_dp->psr.debug & I915_PSR_DEBUG_MODE_MASK; 3466 old_disable_bits = intel_dp->psr.debug & 3467 (I915_PSR_DEBUG_SU_REGION_ET_DISABLE | 3468 I915_PSR_DEBUG_PANEL_REPLAY_DISABLE); 3469 3470 intel_dp->psr.debug = val; 3471 3472 /* 3473 * Do it right away if it's already enabled, otherwise it will be done 3474 * when enabling the source. 3475 */ 3476 if (intel_dp->psr.enabled) 3477 psr_irq_control(intel_dp); 3478 3479 mutex_unlock(&intel_dp->psr.lock); 3480 3481 if (old_mode != mode || old_disable_bits != disable_bits) 3482 ret = intel_psr_fastset_force(display); 3483 3484 return ret; 3485 } 3486 3487 static void intel_psr_handle_irq(struct intel_dp *intel_dp) 3488 { 3489 struct intel_psr *psr = &intel_dp->psr; 3490 3491 intel_psr_disable_locked(intel_dp); 3492 psr->sink_not_reliable = true; 3493 /* let's make sure that sink is awaken */ 3494 drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, DP_SET_POWER_D0); 3495 } 3496 3497 static void intel_psr_work(struct work_struct *work) 3498 { 3499 struct intel_dp *intel_dp = 3500 container_of(work, typeof(*intel_dp), psr.work); 3501 3502 mutex_lock(&intel_dp->psr.lock); 3503 3504 if (!intel_dp->psr.enabled) 3505 goto unlock; 3506 3507 if (READ_ONCE(intel_dp->psr.irq_aux_error)) { 3508 intel_psr_handle_irq(intel_dp); 3509 goto unlock; 3510 } 3511 3512 if (intel_dp->psr.pause_counter) 3513 goto unlock; 3514 3515 /* 3516 * We have to make sure PSR is ready for re-enable 3517 * otherwise it keeps disabled until next full enable/disable cycle. 3518 * PSR might take some time to get fully disabled 3519 * and be ready for re-enable. 3520 */ 3521 if (!__psr_wait_for_idle_locked(intel_dp)) 3522 goto unlock; 3523 3524 /* 3525 * The delayed work can race with an invalidate hence we need to 3526 * recheck. Since psr_flush first clears this and then reschedules we 3527 * won't ever miss a flush when bailing out here. 3528 */ 3529 if (intel_dp->psr.busy_frontbuffer_bits || intel_dp->psr.active) 3530 goto unlock; 3531 3532 intel_psr_activate(intel_dp); 3533 unlock: 3534 mutex_unlock(&intel_dp->psr.lock); 3535 } 3536 3537 static void intel_psr_configure_full_frame_update(struct intel_dp *intel_dp) 3538 { 3539 struct intel_display *display = to_intel_display(intel_dp); 3540 enum transcoder cpu_transcoder = intel_dp->psr.transcoder; 3541 3542 if (!intel_dp->psr.psr2_sel_fetch_enabled) 3543 return; 3544 3545 if (DISPLAY_VER(display) >= 20) 3546 intel_de_write(display, LNL_SFF_CTL(cpu_transcoder), 3547 LNL_SFF_CTL_SF_SINGLE_FULL_FRAME); 3548 else 3549 intel_de_write(display, 3550 PSR2_MAN_TRK_CTL(display, cpu_transcoder), 3551 man_trk_ctl_enable_bit_get(display) | 3552 man_trk_ctl_partial_frame_bit_get(display) | 3553 man_trk_ctl_single_full_frame_bit_get(display) | 3554 man_trk_ctl_continuos_full_frame(display)); 3555 } 3556 3557 static void _psr_invalidate_handle(struct intel_dp *intel_dp) 3558 { 3559 struct intel_display *display = to_intel_display(intel_dp); 3560 3561 if (DISPLAY_VER(display) < 20 && intel_dp->psr.psr2_sel_fetch_enabled) { 3562 if (!intel_dp->psr.psr2_sel_fetch_cff_enabled) { 3563 intel_dp->psr.psr2_sel_fetch_cff_enabled = true; 3564 intel_psr_configure_full_frame_update(intel_dp); 3565 } 3566 3567 intel_psr_force_update(intel_dp); 3568 } else { 3569 intel_psr_exit(intel_dp); 3570 } 3571 } 3572 3573 /** 3574 * intel_psr_invalidate - Invalidate PSR 3575 * @display: display device 3576 * @frontbuffer_bits: frontbuffer plane tracking bits 3577 * @origin: which operation caused the invalidate 3578 * 3579 * Since the hardware frontbuffer tracking has gaps we need to integrate 3580 * with the software frontbuffer tracking. This function gets called every 3581 * time frontbuffer rendering starts and a buffer gets dirtied. PSR must be 3582 * disabled if the frontbuffer mask contains a buffer relevant to PSR. 3583 * 3584 * Dirty frontbuffers relevant to PSR are tracked in busy_frontbuffer_bits." 3585 */ 3586 void intel_psr_invalidate(struct intel_display *display, 3587 unsigned frontbuffer_bits, enum fb_op_origin origin) 3588 { 3589 struct intel_encoder *encoder; 3590 3591 if (origin == ORIGIN_FLIP) 3592 return; 3593 3594 for_each_intel_encoder_with_psr(display->drm, encoder) { 3595 unsigned int pipe_frontbuffer_bits = frontbuffer_bits; 3596 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 3597 3598 mutex_lock(&intel_dp->psr.lock); 3599 if (!intel_dp->psr.enabled) { 3600 mutex_unlock(&intel_dp->psr.lock); 3601 continue; 3602 } 3603 3604 pipe_frontbuffer_bits &= 3605 INTEL_FRONTBUFFER_ALL_MASK(intel_dp->psr.pipe); 3606 intel_dp->psr.busy_frontbuffer_bits |= pipe_frontbuffer_bits; 3607 3608 if (pipe_frontbuffer_bits) 3609 _psr_invalidate_handle(intel_dp); 3610 3611 mutex_unlock(&intel_dp->psr.lock); 3612 } 3613 } 3614 /* 3615 * When we will be completely rely on PSR2 S/W tracking in future, 3616 * intel_psr_flush() will invalidate and flush the PSR for ORIGIN_FLIP 3617 * event also therefore tgl_dc3co_flush_locked() require to be changed 3618 * accordingly in future. 3619 */ 3620 static void 3621 tgl_dc3co_flush_locked(struct intel_dp *intel_dp, unsigned int frontbuffer_bits, 3622 enum fb_op_origin origin) 3623 { 3624 struct intel_display *display = to_intel_display(intel_dp); 3625 3626 if (!intel_dp->psr.dc3co_exitline || !intel_dp->psr.sel_update_enabled || 3627 !intel_dp->psr.active) 3628 return; 3629 3630 /* 3631 * At every frontbuffer flush flip event modified delay of delayed work, 3632 * when delayed work schedules that means display has been idle. 3633 */ 3634 if (!(frontbuffer_bits & 3635 INTEL_FRONTBUFFER_ALL_MASK(intel_dp->psr.pipe))) 3636 return; 3637 3638 tgl_psr2_enable_dc3co(intel_dp); 3639 mod_delayed_work(display->wq.unordered, &intel_dp->psr.dc3co_work, 3640 intel_dp->psr.dc3co_exit_delay); 3641 } 3642 3643 static void _psr_flush_handle(struct intel_dp *intel_dp) 3644 { 3645 struct intel_display *display = to_intel_display(intel_dp); 3646 3647 if (DISPLAY_VER(display) >= 20) { 3648 /* 3649 * We can use PSR exit on LunarLake onwards. Also 3650 * using trans push mechanism to trigger Frame Change 3651 * event requires using PSR exit. 3652 */ 3653 intel_psr_exit(intel_dp); 3654 } else if (intel_dp->psr.psr2_sel_fetch_enabled) { 3655 /* Selective fetch prior LNL */ 3656 if (intel_dp->psr.psr2_sel_fetch_cff_enabled) { 3657 /* can we turn CFF off? */ 3658 if (intel_dp->psr.busy_frontbuffer_bits == 0) 3659 intel_dp->psr.psr2_sel_fetch_cff_enabled = false; 3660 } 3661 3662 /* 3663 * Still keep cff bit enabled as we don't have proper SU 3664 * configuration in case update is sent for any reason after 3665 * sff bit gets cleared by the HW on next vblank. 3666 * 3667 * NOTE: Setting cff bit is not needed for LunarLake onwards as 3668 * we have own register for SFF bit and we are not overwriting 3669 * existing SU configuration 3670 */ 3671 intel_psr_configure_full_frame_update(intel_dp); 3672 3673 intel_psr_force_update(intel_dp); 3674 } else { 3675 /* 3676 * On older platforms using PSR exit was seen causing problems 3677 */ 3678 intel_psr_force_update(intel_dp); 3679 } 3680 3681 if (!intel_dp->psr.active && !intel_dp->psr.busy_frontbuffer_bits) 3682 queue_work(display->wq.unordered, &intel_dp->psr.work); 3683 } 3684 3685 /** 3686 * intel_psr_flush - Flush PSR 3687 * @display: display device 3688 * @frontbuffer_bits: frontbuffer plane tracking bits 3689 * @origin: which operation caused the flush 3690 * 3691 * Since the hardware frontbuffer tracking has gaps we need to integrate 3692 * with the software frontbuffer tracking. This function gets called every 3693 * time frontbuffer rendering has completed and flushed out to memory. PSR 3694 * can be enabled again if no other frontbuffer relevant to PSR is dirty. 3695 * 3696 * Dirty frontbuffers relevant to PSR are tracked in busy_frontbuffer_bits. 3697 */ 3698 void intel_psr_flush(struct intel_display *display, 3699 unsigned frontbuffer_bits, enum fb_op_origin origin) 3700 { 3701 struct intel_encoder *encoder; 3702 3703 for_each_intel_encoder_with_psr(display->drm, encoder) { 3704 unsigned int pipe_frontbuffer_bits = frontbuffer_bits; 3705 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 3706 3707 mutex_lock(&intel_dp->psr.lock); 3708 if (!intel_dp->psr.enabled) { 3709 mutex_unlock(&intel_dp->psr.lock); 3710 continue; 3711 } 3712 3713 pipe_frontbuffer_bits &= 3714 INTEL_FRONTBUFFER_ALL_MASK(intel_dp->psr.pipe); 3715 intel_dp->psr.busy_frontbuffer_bits &= ~pipe_frontbuffer_bits; 3716 3717 /* 3718 * If the PSR is paused by an explicit intel_psr_paused() call, 3719 * we have to ensure that the PSR is not activated until 3720 * intel_psr_resume() is called. 3721 */ 3722 if (intel_dp->psr.pause_counter) 3723 goto unlock; 3724 3725 if (origin == ORIGIN_FLIP || 3726 (origin == ORIGIN_CURSOR_UPDATE && 3727 !intel_dp->psr.psr2_sel_fetch_enabled)) { 3728 tgl_dc3co_flush_locked(intel_dp, frontbuffer_bits, origin); 3729 goto unlock; 3730 } 3731 3732 if (pipe_frontbuffer_bits == 0) 3733 goto unlock; 3734 3735 /* By definition flush = invalidate + flush */ 3736 _psr_flush_handle(intel_dp); 3737 unlock: 3738 mutex_unlock(&intel_dp->psr.lock); 3739 } 3740 } 3741 3742 /** 3743 * intel_psr_init - Init basic PSR work and mutex. 3744 * @intel_dp: Intel DP 3745 * 3746 * This function is called after the initializing connector. 3747 * (the initializing of connector treats the handling of connector capabilities) 3748 * And it initializes basic PSR stuff for each DP Encoder. 3749 */ 3750 void intel_psr_init(struct intel_dp *intel_dp) 3751 { 3752 struct intel_display *display = to_intel_display(intel_dp); 3753 struct intel_connector *connector = intel_dp->attached_connector; 3754 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 3755 3756 if (!(HAS_PSR(display) || HAS_DP20(display))) 3757 return; 3758 3759 /* 3760 * HSW spec explicitly says PSR is tied to port A. 3761 * BDW+ platforms have a instance of PSR registers per transcoder but 3762 * BDW, GEN9 and GEN11 are not validated by HW team in other transcoder 3763 * than eDP one. 3764 * For now it only supports one instance of PSR for BDW, GEN9 and GEN11. 3765 * So lets keep it hardcoded to PORT_A for BDW, GEN9 and GEN11. 3766 * But GEN12 supports a instance of PSR registers per transcoder. 3767 */ 3768 if (DISPLAY_VER(display) < 12 && dig_port->base.port != PORT_A) { 3769 drm_dbg_kms(display->drm, 3770 "PSR condition failed: Port not supported\n"); 3771 return; 3772 } 3773 3774 if ((HAS_DP20(display) && !intel_dp_is_edp(intel_dp)) || 3775 DISPLAY_VER(display) >= 20) 3776 intel_dp->psr.source_panel_replay_support = true; 3777 3778 if (HAS_PSR(display) && intel_dp_is_edp(intel_dp)) 3779 intel_dp->psr.source_support = true; 3780 3781 /* Set link_standby x link_off defaults */ 3782 if (DISPLAY_VER(display) < 12) 3783 /* For new platforms up to TGL let's respect VBT back again */ 3784 intel_dp->psr.link_standby = connector->panel.vbt.psr.full_link; 3785 3786 INIT_WORK(&intel_dp->psr.work, intel_psr_work); 3787 INIT_DELAYED_WORK(&intel_dp->psr.dc3co_work, tgl_dc3co_disable_work); 3788 mutex_init(&intel_dp->psr.lock); 3789 } 3790 3791 static int psr_get_status_and_error_status(struct intel_dp *intel_dp, 3792 u8 *status, u8 *error_status) 3793 { 3794 struct drm_dp_aux *aux = &intel_dp->aux; 3795 int ret; 3796 unsigned int offset; 3797 3798 offset = intel_dp->psr.panel_replay_enabled ? 3799 DP_SINK_DEVICE_PR_AND_FRAME_LOCK_STATUS : DP_PSR_STATUS; 3800 3801 ret = drm_dp_dpcd_readb(aux, offset, status); 3802 if (ret != 1) 3803 return ret; 3804 3805 offset = intel_dp->psr.panel_replay_enabled ? 3806 DP_PANEL_REPLAY_ERROR_STATUS : DP_PSR_ERROR_STATUS; 3807 3808 ret = drm_dp_dpcd_readb(aux, offset, error_status); 3809 if (ret != 1) 3810 return ret; 3811 3812 *status = *status & DP_PSR_SINK_STATE_MASK; 3813 3814 return 0; 3815 } 3816 3817 static void psr_alpm_check(struct intel_dp *intel_dp) 3818 { 3819 struct intel_psr *psr = &intel_dp->psr; 3820 3821 if (!psr->sel_update_enabled) 3822 return; 3823 3824 if (intel_alpm_get_error(intel_dp)) { 3825 intel_psr_disable_locked(intel_dp); 3826 psr->sink_not_reliable = true; 3827 } 3828 } 3829 3830 static void psr_capability_changed_check(struct intel_dp *intel_dp) 3831 { 3832 struct intel_display *display = to_intel_display(intel_dp); 3833 struct intel_psr *psr = &intel_dp->psr; 3834 u8 val; 3835 int r; 3836 3837 r = drm_dp_dpcd_readb(&intel_dp->aux, DP_PSR_ESI, &val); 3838 if (r != 1) { 3839 drm_err(display->drm, "Error reading DP_PSR_ESI\n"); 3840 return; 3841 } 3842 3843 if (val & DP_PSR_CAPS_CHANGE) { 3844 intel_psr_disable_locked(intel_dp); 3845 psr->sink_not_reliable = true; 3846 drm_dbg_kms(display->drm, 3847 "Sink PSR capability changed, disabling PSR\n"); 3848 3849 /* Clearing it */ 3850 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_ESI, val); 3851 } 3852 } 3853 3854 /* 3855 * On common bits: 3856 * DP_PSR_RFB_STORAGE_ERROR == DP_PANEL_REPLAY_RFB_STORAGE_ERROR 3857 * DP_PSR_VSC_SDP_UNCORRECTABLE_ERROR == DP_PANEL_REPLAY_VSC_SDP_UNCORRECTABLE_ERROR 3858 * DP_PSR_LINK_CRC_ERROR == DP_PANEL_REPLAY_LINK_CRC_ERROR 3859 * this function is relying on PSR definitions 3860 */ 3861 void intel_psr_short_pulse(struct intel_dp *intel_dp) 3862 { 3863 struct intel_display *display = to_intel_display(intel_dp); 3864 struct intel_psr *psr = &intel_dp->psr; 3865 u8 status, error_status; 3866 const u8 errors = DP_PSR_RFB_STORAGE_ERROR | 3867 DP_PSR_VSC_SDP_UNCORRECTABLE_ERROR | 3868 DP_PSR_LINK_CRC_ERROR; 3869 3870 if (!CAN_PSR(intel_dp) && !CAN_PANEL_REPLAY(intel_dp)) 3871 return; 3872 3873 mutex_lock(&psr->lock); 3874 3875 psr->link_ok = false; 3876 3877 if (!psr->enabled) 3878 goto exit; 3879 3880 if (psr_get_status_and_error_status(intel_dp, &status, &error_status)) { 3881 drm_err(display->drm, 3882 "Error reading PSR status or error status\n"); 3883 goto exit; 3884 } 3885 3886 if ((!psr->panel_replay_enabled && status == DP_PSR_SINK_INTERNAL_ERROR) || 3887 (error_status & errors)) { 3888 intel_psr_disable_locked(intel_dp); 3889 psr->sink_not_reliable = true; 3890 } 3891 3892 if (!psr->panel_replay_enabled && status == DP_PSR_SINK_INTERNAL_ERROR && 3893 !error_status) 3894 drm_dbg_kms(display->drm, 3895 "PSR sink internal error, disabling PSR\n"); 3896 if (error_status & DP_PSR_RFB_STORAGE_ERROR) 3897 drm_dbg_kms(display->drm, 3898 "PSR RFB storage error, disabling PSR\n"); 3899 if (error_status & DP_PSR_VSC_SDP_UNCORRECTABLE_ERROR) 3900 drm_dbg_kms(display->drm, 3901 "PSR VSC SDP uncorrectable error, disabling PSR\n"); 3902 if (error_status & DP_PSR_LINK_CRC_ERROR) 3903 drm_dbg_kms(display->drm, 3904 "PSR Link CRC error, disabling PSR\n"); 3905 3906 if (error_status & ~errors) 3907 drm_err(display->drm, 3908 "PSR_ERROR_STATUS unhandled errors %x\n", 3909 error_status & ~errors); 3910 /* clear status register */ 3911 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_ERROR_STATUS, error_status); 3912 3913 if (!psr->panel_replay_enabled) { 3914 psr_alpm_check(intel_dp); 3915 psr_capability_changed_check(intel_dp); 3916 } 3917 3918 exit: 3919 mutex_unlock(&psr->lock); 3920 } 3921 3922 bool intel_psr_enabled(struct intel_dp *intel_dp) 3923 { 3924 bool ret; 3925 3926 if (!CAN_PSR(intel_dp)) 3927 return false; 3928 3929 mutex_lock(&intel_dp->psr.lock); 3930 ret = intel_dp->psr.enabled; 3931 mutex_unlock(&intel_dp->psr.lock); 3932 3933 return ret; 3934 } 3935 3936 /** 3937 * intel_psr_link_ok - return psr->link_ok 3938 * @intel_dp: struct intel_dp 3939 * 3940 * We are seeing unexpected link re-trainings with some panels. This is caused 3941 * by panel stating bad link status after PSR is enabled. Code checking link 3942 * status can call this to ensure it can ignore bad link status stated by the 3943 * panel I.e. if panel is stating bad link and intel_psr_link_ok is stating link 3944 * is ok caller should rely on latter. 3945 * 3946 * Return value of link_ok 3947 */ 3948 bool intel_psr_link_ok(struct intel_dp *intel_dp) 3949 { 3950 bool ret; 3951 3952 if ((!CAN_PSR(intel_dp) && !CAN_PANEL_REPLAY(intel_dp)) || 3953 !intel_dp_is_edp(intel_dp)) 3954 return false; 3955 3956 mutex_lock(&intel_dp->psr.lock); 3957 ret = intel_dp->psr.link_ok; 3958 mutex_unlock(&intel_dp->psr.lock); 3959 3960 return ret; 3961 } 3962 3963 /** 3964 * intel_psr_lock - grab PSR lock 3965 * @crtc_state: the crtc state 3966 * 3967 * This is initially meant to be used by around CRTC update, when 3968 * vblank sensitive registers are updated and we need grab the lock 3969 * before it to avoid vblank evasion. 3970 */ 3971 void intel_psr_lock(const struct intel_crtc_state *crtc_state) 3972 { 3973 struct intel_display *display = to_intel_display(crtc_state); 3974 struct intel_encoder *encoder; 3975 3976 if (!crtc_state->has_psr) 3977 return; 3978 3979 for_each_intel_encoder_mask_with_psr(display->drm, encoder, 3980 crtc_state->uapi.encoder_mask) { 3981 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 3982 3983 mutex_lock(&intel_dp->psr.lock); 3984 break; 3985 } 3986 } 3987 3988 /** 3989 * intel_psr_unlock - release PSR lock 3990 * @crtc_state: the crtc state 3991 * 3992 * Release the PSR lock that was held during pipe update. 3993 */ 3994 void intel_psr_unlock(const struct intel_crtc_state *crtc_state) 3995 { 3996 struct intel_display *display = to_intel_display(crtc_state); 3997 struct intel_encoder *encoder; 3998 3999 if (!crtc_state->has_psr) 4000 return; 4001 4002 for_each_intel_encoder_mask_with_psr(display->drm, encoder, 4003 crtc_state->uapi.encoder_mask) { 4004 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 4005 4006 mutex_unlock(&intel_dp->psr.lock); 4007 break; 4008 } 4009 } 4010 4011 /* Wa_16025596647 */ 4012 static void intel_psr_apply_underrun_on_idle_wa_locked(struct intel_dp *intel_dp) 4013 { 4014 struct intel_display *display = to_intel_display(intel_dp); 4015 bool dc5_dc6_blocked; 4016 4017 if (!intel_dp->psr.active || !intel_dp->psr.pkg_c_latency_used) 4018 return; 4019 4020 dc5_dc6_blocked = is_dc5_dc6_blocked(intel_dp); 4021 4022 if (intel_dp->psr.sel_update_enabled) 4023 psr2_program_idle_frames(intel_dp, dc5_dc6_blocked ? 0 : 4024 psr_compute_idle_frames(intel_dp)); 4025 else 4026 intel_dmc_start_pkgc_exit_at_start_of_undelayed_vblank(display, 4027 intel_dp->psr.pipe, 4028 dc5_dc6_blocked); 4029 } 4030 4031 static void psr_dc5_dc6_wa_work(struct work_struct *work) 4032 { 4033 struct intel_display *display = container_of(work, typeof(*display), 4034 psr_dc5_dc6_wa_work); 4035 struct intel_encoder *encoder; 4036 4037 for_each_intel_encoder_with_psr(display->drm, encoder) { 4038 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 4039 4040 mutex_lock(&intel_dp->psr.lock); 4041 4042 if (intel_dp->psr.enabled && !intel_dp->psr.panel_replay_enabled && 4043 !intel_dp->psr.pkg_c_latency_used) 4044 intel_psr_apply_underrun_on_idle_wa_locked(intel_dp); 4045 4046 mutex_unlock(&intel_dp->psr.lock); 4047 } 4048 } 4049 4050 /** 4051 * intel_psr_notify_dc5_dc6 - Notify PSR about enable/disable dc5/dc6 4052 * @display: intel atomic state 4053 * 4054 * This is targeted for underrun on idle PSR HW bug (Wa_16025596647) to schedule 4055 * psr_dc5_dc6_wa_work used for applying/removing the workaround. 4056 */ 4057 void intel_psr_notify_dc5_dc6(struct intel_display *display) 4058 { 4059 if (!intel_display_wa(display, INTEL_DISPLAY_WA_16025596647)) 4060 return; 4061 4062 schedule_work(&display->psr_dc5_dc6_wa_work); 4063 } 4064 4065 /** 4066 * intel_psr_dc5_dc6_wa_init - Init work for underrun on idle PSR HW bug wa 4067 * @display: intel atomic state 4068 * 4069 * This is targeted for underrun on idle PSR HW bug (Wa_16025596647) to init 4070 * psr_dc5_dc6_wa_work used for applying the workaround. 4071 */ 4072 void intel_psr_dc5_dc6_wa_init(struct intel_display *display) 4073 { 4074 if (!intel_display_wa(display, INTEL_DISPLAY_WA_16025596647)) 4075 return; 4076 4077 INIT_WORK(&display->psr_dc5_dc6_wa_work, psr_dc5_dc6_wa_work); 4078 } 4079 4080 /** 4081 * intel_psr_notify_pipe_change - Notify PSR about enable/disable of a pipe 4082 * @state: intel atomic state 4083 * @crtc: intel crtc 4084 * @enable: enable/disable 4085 * 4086 * This is targeted for underrun on idle PSR HW bug (Wa_16025596647) to apply 4087 * remove the workaround when pipe is getting enabled/disabled 4088 */ 4089 void intel_psr_notify_pipe_change(struct intel_atomic_state *state, 4090 struct intel_crtc *crtc, bool enable) 4091 { 4092 struct intel_display *display = to_intel_display(state); 4093 struct intel_encoder *encoder; 4094 4095 if (!intel_display_wa(display, INTEL_DISPLAY_WA_16025596647)) 4096 return; 4097 4098 for_each_intel_encoder_with_psr(display->drm, encoder) { 4099 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 4100 u8 active_non_psr_pipes; 4101 4102 mutex_lock(&intel_dp->psr.lock); 4103 4104 if (!intel_dp->psr.enabled || intel_dp->psr.panel_replay_enabled) 4105 goto unlock; 4106 4107 active_non_psr_pipes = intel_dp->psr.active_non_psr_pipes; 4108 4109 if (enable) 4110 active_non_psr_pipes |= BIT(crtc->pipe); 4111 else 4112 active_non_psr_pipes &= ~BIT(crtc->pipe); 4113 4114 if (active_non_psr_pipes == intel_dp->psr.active_non_psr_pipes) 4115 goto unlock; 4116 4117 if ((enable && intel_dp->psr.active_non_psr_pipes) || 4118 (!enable && !intel_dp->psr.active_non_psr_pipes) || 4119 !intel_dp->psr.pkg_c_latency_used) { 4120 intel_dp->psr.active_non_psr_pipes = active_non_psr_pipes; 4121 goto unlock; 4122 } 4123 4124 intel_dp->psr.active_non_psr_pipes = active_non_psr_pipes; 4125 4126 intel_psr_apply_underrun_on_idle_wa_locked(intel_dp); 4127 unlock: 4128 mutex_unlock(&intel_dp->psr.lock); 4129 } 4130 } 4131 4132 /** 4133 * intel_psr_notify_vblank_enable_disable - Notify PSR about enable/disable of vblank 4134 * @display: intel display struct 4135 * @enable: enable/disable 4136 * 4137 * This is targeted for underrun on idle PSR HW bug (Wa_16025596647) to apply 4138 * remove the workaround when vblank is getting enabled/disabled 4139 */ 4140 void intel_psr_notify_vblank_enable_disable(struct intel_display *display, 4141 bool enable) 4142 { 4143 struct intel_encoder *encoder; 4144 4145 for_each_intel_encoder_with_psr(display->drm, encoder) { 4146 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 4147 4148 mutex_lock(&intel_dp->psr.lock); 4149 if (intel_dp->psr.panel_replay_enabled) { 4150 mutex_unlock(&intel_dp->psr.lock); 4151 break; 4152 } 4153 4154 if (intel_dp->psr.enabled && intel_dp->psr.pkg_c_latency_used) 4155 intel_psr_apply_underrun_on_idle_wa_locked(intel_dp); 4156 4157 mutex_unlock(&intel_dp->psr.lock); 4158 return; 4159 } 4160 4161 /* 4162 * NOTE: intel_display_power_set_target_dc_state is used 4163 * only by PSR * code for DC3CO handling. DC3CO target 4164 * state is currently disabled in * PSR code. If DC3CO 4165 * is taken into use we need take that into account here 4166 * as well. 4167 */ 4168 intel_display_power_set_target_dc_state(display, enable ? DC_STATE_DISABLE : 4169 DC_STATE_EN_UPTO_DC6); 4170 } 4171 4172 static void 4173 psr_source_status(struct intel_dp *intel_dp, struct seq_file *m) 4174 { 4175 struct intel_display *display = to_intel_display(intel_dp); 4176 enum transcoder cpu_transcoder = intel_dp->psr.transcoder; 4177 const char *status = "unknown"; 4178 u32 val, status_val; 4179 4180 if ((intel_dp_is_edp(intel_dp) || DISPLAY_VER(display) >= 30) && 4181 (intel_dp->psr.sel_update_enabled || intel_dp->psr.panel_replay_enabled)) { 4182 static const char * const live_status[] = { 4183 "IDLE", 4184 "CAPTURE", 4185 "CAPTURE_FS", 4186 "SLEEP", 4187 "BUFON_FW", 4188 "ML_UP", 4189 "SU_STANDBY", 4190 "FAST_SLEEP", 4191 "DEEP_SLEEP", 4192 "BUF_ON", 4193 "TG_ON" 4194 }; 4195 val = intel_de_read(display, 4196 EDP_PSR2_STATUS(display, cpu_transcoder)); 4197 status_val = REG_FIELD_GET(EDP_PSR2_STATUS_STATE_MASK, val); 4198 if (status_val < ARRAY_SIZE(live_status)) 4199 status = live_status[status_val]; 4200 } else { 4201 static const char * const live_status[] = { 4202 "IDLE", 4203 "SRDONACK", 4204 "SRDENT", 4205 "BUFOFF", 4206 "BUFON", 4207 "AUXACK", 4208 "SRDOFFACK", 4209 "SRDENT_ON", 4210 }; 4211 val = intel_de_read(display, 4212 psr_status_reg(display, cpu_transcoder)); 4213 status_val = REG_FIELD_GET(EDP_PSR_STATUS_STATE_MASK, val); 4214 if (status_val < ARRAY_SIZE(live_status)) 4215 status = live_status[status_val]; 4216 } 4217 4218 seq_printf(m, "Source PSR/PanelReplay status: %s [0x%08x]\n", status, val); 4219 } 4220 4221 static void intel_psr_sink_capability(struct intel_connector *connector, 4222 struct seq_file *m) 4223 { 4224 seq_printf(m, "Sink support: PSR = %s", 4225 str_yes_no(connector->dp.psr_caps.support)); 4226 4227 if (connector->dp.psr_caps.support) 4228 seq_printf(m, " [0x%02x]", connector->dp.psr_caps.dpcd[0]); 4229 if (connector->dp.psr_caps.dpcd[0] == DP_PSR2_WITH_Y_COORD_ET_SUPPORTED) 4230 seq_printf(m, " (Early Transport)"); 4231 seq_printf(m, ", Panel Replay = %s", str_yes_no(connector->dp.panel_replay_caps.support)); 4232 seq_printf(m, ", Panel Replay Selective Update = %s", 4233 str_yes_no(connector->dp.panel_replay_caps.su_support)); 4234 seq_printf(m, ", Panel Replay DSC support = %s", 4235 panel_replay_dsc_support_str(connector->dp.panel_replay_caps.dsc_support)); 4236 if (connector->dp.panel_replay_caps.dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_SUPPORT)] & 4237 DP_PANEL_REPLAY_EARLY_TRANSPORT_SUPPORT) 4238 seq_printf(m, " (Early Transport)"); 4239 seq_printf(m, "\n"); 4240 } 4241 4242 static void intel_psr_print_mode(struct intel_dp *intel_dp, 4243 struct seq_file *m) 4244 { 4245 struct intel_psr *psr = &intel_dp->psr; 4246 const char *status, *mode, *region_et; 4247 4248 if (psr->enabled) 4249 status = " enabled"; 4250 else 4251 status = "disabled"; 4252 4253 if (psr->panel_replay_enabled && psr->sel_update_enabled) 4254 mode = "Panel Replay Selective Update"; 4255 else if (psr->panel_replay_enabled) 4256 mode = "Panel Replay"; 4257 else if (psr->sel_update_enabled) 4258 mode = "PSR2"; 4259 else if (psr->enabled) 4260 mode = "PSR1"; 4261 else 4262 mode = ""; 4263 4264 if (psr->su_region_et_enabled) 4265 region_et = " (Early Transport)"; 4266 else 4267 region_et = ""; 4268 4269 seq_printf(m, "PSR mode: %s%s%s\n", mode, status, region_et); 4270 if (psr->no_psr_reason) 4271 seq_printf(m, " %s\n", psr->no_psr_reason); 4272 } 4273 4274 static int intel_psr_status(struct seq_file *m, struct intel_dp *intel_dp, 4275 struct intel_connector *connector) 4276 { 4277 struct intel_display *display = to_intel_display(intel_dp); 4278 enum transcoder cpu_transcoder = intel_dp->psr.transcoder; 4279 struct intel_psr *psr = &intel_dp->psr; 4280 struct ref_tracker *wakeref; 4281 bool enabled; 4282 u32 val, psr2_ctl; 4283 4284 intel_psr_sink_capability(connector, m); 4285 4286 if (!(connector->dp.psr_caps.support || connector->dp.panel_replay_caps.support)) 4287 return 0; 4288 4289 wakeref = intel_display_rpm_get(display); 4290 mutex_lock(&psr->lock); 4291 4292 intel_psr_print_mode(intel_dp, m); 4293 4294 if (!psr->enabled) { 4295 seq_printf(m, "PSR sink not reliable: %s\n", 4296 str_yes_no(psr->sink_not_reliable)); 4297 4298 goto unlock; 4299 } 4300 4301 if (psr->panel_replay_enabled) { 4302 val = intel_de_read(display, TRANS_DP2_CTL(cpu_transcoder)); 4303 4304 if (intel_dp_is_edp(intel_dp)) 4305 psr2_ctl = intel_de_read(display, 4306 EDP_PSR2_CTL(display, 4307 cpu_transcoder)); 4308 4309 enabled = val & TRANS_DP2_PANEL_REPLAY_ENABLE; 4310 } else if (psr->sel_update_enabled) { 4311 val = intel_de_read(display, 4312 EDP_PSR2_CTL(display, cpu_transcoder)); 4313 enabled = val & EDP_PSR2_ENABLE; 4314 } else { 4315 val = intel_de_read(display, psr_ctl_reg(display, cpu_transcoder)); 4316 enabled = val & EDP_PSR_ENABLE; 4317 } 4318 seq_printf(m, "Source PSR/PanelReplay ctl: %s [0x%08x]\n", 4319 str_enabled_disabled(enabled), val); 4320 if (psr->panel_replay_enabled && intel_dp_is_edp(intel_dp)) 4321 seq_printf(m, "PSR2_CTL: 0x%08x\n", 4322 psr2_ctl); 4323 psr_source_status(intel_dp, m); 4324 seq_printf(m, "Busy frontbuffer bits: 0x%08x\n", 4325 psr->busy_frontbuffer_bits); 4326 4327 /* 4328 * SKL+ Perf counter is reset to 0 everytime DC state is entered 4329 */ 4330 val = intel_de_read(display, psr_perf_cnt_reg(display, cpu_transcoder)); 4331 seq_printf(m, "Performance counter: %u\n", 4332 REG_FIELD_GET(EDP_PSR_PERF_CNT_MASK, val)); 4333 4334 if (psr->debug & I915_PSR_DEBUG_IRQ) { 4335 seq_printf(m, "Last attempted entry at: %lld\n", 4336 psr->last_entry_attempt); 4337 seq_printf(m, "Last exit at: %lld\n", psr->last_exit); 4338 } 4339 4340 if (psr->sel_update_enabled) { 4341 u32 su_frames_val[3]; 4342 int frame; 4343 4344 /* 4345 * PSR2_SU_STATUS register has been tied-off since DG2/ADL-P 4346 * (it returns zeros only) and it has been removed on Xe2_LPD. 4347 */ 4348 if (DISPLAY_VER(display) < 13) { 4349 /* 4350 * Reading all 3 registers before hand to minimize crossing a 4351 * frame boundary between register reads 4352 */ 4353 for (frame = 0; frame < PSR2_SU_STATUS_FRAMES; frame += 3) { 4354 val = intel_de_read(display, 4355 PSR2_SU_STATUS(display, cpu_transcoder, frame)); 4356 su_frames_val[frame / 3] = val; 4357 } 4358 4359 seq_puts(m, "Frame:\tPSR2 SU blocks:\n"); 4360 4361 for (frame = 0; frame < PSR2_SU_STATUS_FRAMES; frame++) { 4362 u32 su_blocks; 4363 4364 su_blocks = su_frames_val[frame / 3] & 4365 PSR2_SU_STATUS_MASK(frame); 4366 su_blocks = su_blocks >> PSR2_SU_STATUS_SHIFT(frame); 4367 seq_printf(m, "%d\t%d\n", frame, su_blocks); 4368 } 4369 } 4370 4371 seq_printf(m, "PSR2 selective fetch: %s\n", 4372 str_enabled_disabled(psr->psr2_sel_fetch_enabled)); 4373 } 4374 4375 unlock: 4376 mutex_unlock(&psr->lock); 4377 intel_display_rpm_put(display, wakeref); 4378 4379 return 0; 4380 } 4381 4382 static int i915_edp_psr_status_show(struct seq_file *m, void *data) 4383 { 4384 struct intel_display *display = m->private; 4385 struct intel_dp *intel_dp = NULL; 4386 struct intel_encoder *encoder; 4387 4388 if (!HAS_PSR(display)) 4389 return -ENODEV; 4390 4391 /* Find the first EDP which supports PSR */ 4392 for_each_intel_encoder_with_psr(display->drm, encoder) { 4393 intel_dp = enc_to_intel_dp(encoder); 4394 break; 4395 } 4396 4397 if (!intel_dp) 4398 return -ENODEV; 4399 4400 return intel_psr_status(m, intel_dp, intel_dp->attached_connector); 4401 } 4402 DEFINE_SHOW_ATTRIBUTE(i915_edp_psr_status); 4403 4404 static int 4405 i915_edp_psr_debug_set(void *data, u64 val) 4406 { 4407 struct intel_display *display = data; 4408 struct intel_encoder *encoder; 4409 int ret = -ENODEV; 4410 4411 if (!HAS_PSR(display)) 4412 return ret; 4413 4414 for_each_intel_encoder_with_psr(display->drm, encoder) { 4415 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 4416 4417 drm_dbg_kms(display->drm, "Setting PSR debug to %llx\n", val); 4418 4419 // TODO: split to each transcoder's PSR debug state 4420 with_intel_display_rpm(display) 4421 ret = intel_psr_debug_set(intel_dp, val); 4422 } 4423 4424 return ret; 4425 } 4426 4427 static int 4428 i915_edp_psr_debug_get(void *data, u64 *val) 4429 { 4430 struct intel_display *display = data; 4431 struct intel_encoder *encoder; 4432 4433 if (!HAS_PSR(display)) 4434 return -ENODEV; 4435 4436 for_each_intel_encoder_with_psr(display->drm, encoder) { 4437 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 4438 4439 // TODO: split to each transcoder's PSR debug state 4440 *val = READ_ONCE(intel_dp->psr.debug); 4441 return 0; 4442 } 4443 4444 return -ENODEV; 4445 } 4446 4447 DEFINE_SIMPLE_ATTRIBUTE(i915_edp_psr_debug_fops, 4448 i915_edp_psr_debug_get, i915_edp_psr_debug_set, 4449 "%llu\n"); 4450 4451 void intel_psr_debugfs_register(struct intel_display *display) 4452 { 4453 struct dentry *debugfs_root = display->drm->debugfs_root; 4454 4455 debugfs_create_file("i915_edp_psr_debug", 0644, debugfs_root, 4456 display, &i915_edp_psr_debug_fops); 4457 4458 debugfs_create_file("i915_edp_psr_status", 0444, debugfs_root, 4459 display, &i915_edp_psr_status_fops); 4460 } 4461 4462 static const char *psr_mode_str(struct intel_dp *intel_dp) 4463 { 4464 if (intel_dp->psr.panel_replay_enabled) 4465 return "PANEL-REPLAY"; 4466 else if (intel_dp->psr.enabled) 4467 return "PSR"; 4468 4469 return "unknown"; 4470 } 4471 4472 static int i915_psr_sink_status_show(struct seq_file *m, void *data) 4473 { 4474 struct intel_connector *connector = m->private; 4475 struct intel_dp *intel_dp = intel_attached_dp(connector); 4476 static const char * const sink_status[] = { 4477 "inactive", 4478 "transition to active, capture and display", 4479 "active, display from RFB", 4480 "active, capture and display on sink device timings", 4481 "transition to inactive, capture and display, timing re-sync", 4482 "reserved", 4483 "reserved", 4484 "sink internal error", 4485 }; 4486 const char *str; 4487 int ret; 4488 u8 status, error_status; 4489 4490 if (!(CAN_PSR(intel_dp) || CAN_PANEL_REPLAY(intel_dp))) { 4491 seq_puts(m, "PSR/Panel-Replay Unsupported\n"); 4492 return -ENODEV; 4493 } 4494 4495 if (connector->base.status != connector_status_connected) 4496 return -ENODEV; 4497 4498 ret = psr_get_status_and_error_status(intel_dp, &status, &error_status); 4499 if (ret) 4500 return ret; 4501 4502 status &= DP_PSR_SINK_STATE_MASK; 4503 if (status < ARRAY_SIZE(sink_status)) 4504 str = sink_status[status]; 4505 else 4506 str = "unknown"; 4507 4508 seq_printf(m, "Sink %s status: 0x%x [%s]\n", psr_mode_str(intel_dp), status, str); 4509 4510 seq_printf(m, "Sink %s error status: 0x%x", psr_mode_str(intel_dp), error_status); 4511 4512 if (error_status & (DP_PSR_RFB_STORAGE_ERROR | 4513 DP_PSR_VSC_SDP_UNCORRECTABLE_ERROR | 4514 DP_PSR_LINK_CRC_ERROR)) 4515 seq_puts(m, ":\n"); 4516 else 4517 seq_puts(m, "\n"); 4518 if (error_status & DP_PSR_RFB_STORAGE_ERROR) 4519 seq_printf(m, "\t%s RFB storage error\n", psr_mode_str(intel_dp)); 4520 if (error_status & DP_PSR_VSC_SDP_UNCORRECTABLE_ERROR) 4521 seq_printf(m, "\t%s VSC SDP uncorrectable error\n", psr_mode_str(intel_dp)); 4522 if (error_status & DP_PSR_LINK_CRC_ERROR) 4523 seq_printf(m, "\t%s Link CRC error\n", psr_mode_str(intel_dp)); 4524 4525 return ret; 4526 } 4527 DEFINE_SHOW_ATTRIBUTE(i915_psr_sink_status); 4528 4529 static int i915_psr_status_show(struct seq_file *m, void *data) 4530 { 4531 struct intel_connector *connector = m->private; 4532 struct intel_dp *intel_dp = intel_attached_dp(connector); 4533 4534 return intel_psr_status(m, intel_dp, connector); 4535 } 4536 DEFINE_SHOW_ATTRIBUTE(i915_psr_status); 4537 4538 void intel_psr_connector_debugfs_add(struct intel_connector *connector) 4539 { 4540 struct intel_display *display = to_intel_display(connector); 4541 struct dentry *root = connector->base.debugfs_entry; 4542 4543 if (connector->base.connector_type != DRM_MODE_CONNECTOR_eDP && 4544 connector->base.connector_type != DRM_MODE_CONNECTOR_DisplayPort) 4545 return; 4546 4547 debugfs_create_file("i915_psr_sink_status", 0444, root, 4548 connector, &i915_psr_sink_status_fops); 4549 4550 if (HAS_PSR(display) || HAS_DP20(display)) 4551 debugfs_create_file("i915_psr_status", 0444, root, 4552 connector, &i915_psr_status_fops); 4553 } 4554 4555 bool intel_psr_needs_alpm(struct intel_dp *intel_dp, const struct intel_crtc_state *crtc_state) 4556 { 4557 /* 4558 * eDP Panel Replay uses always ALPM 4559 * PSR2 uses ALPM but PSR1 doesn't 4560 */ 4561 return intel_dp_is_edp(intel_dp) && (crtc_state->has_sel_update || 4562 crtc_state->has_panel_replay); 4563 } 4564 4565 bool intel_psr_needs_alpm_aux_less(struct intel_dp *intel_dp, 4566 const struct intel_crtc_state *crtc_state) 4567 { 4568 return intel_dp_is_edp(intel_dp) && crtc_state->has_panel_replay; 4569 } 4570 4571 void intel_psr_compute_config_late(struct intel_dp *intel_dp, 4572 struct intel_crtc_state *crtc_state) 4573 { 4574 struct intel_display *display = to_intel_display(intel_dp); 4575 int vblank = intel_crtc_vblank_length(crtc_state); 4576 int wake_lines; 4577 4578 if (intel_psr_needs_alpm_aux_less(intel_dp, crtc_state)) 4579 wake_lines = crtc_state->alpm_state.aux_less_wake_lines; 4580 else if (intel_psr_needs_alpm(intel_dp, crtc_state)) 4581 wake_lines = DISPLAY_VER(display) < 20 ? 4582 psr2_block_count_lines(crtc_state->alpm_state.io_wake_lines, 4583 crtc_state->alpm_state.fast_wake_lines) : 4584 crtc_state->alpm_state.io_wake_lines; 4585 else 4586 wake_lines = 0; 4587 4588 /* 4589 * Disable the PSR features if wake lines exceed the available vblank. 4590 * Though SCL is computed based on these PSR features, it is not reset 4591 * even if the PSR features are disabled to avoid changing vblank start 4592 * at this stage. 4593 */ 4594 if (wake_lines && !_wake_lines_fit_into_vblank(crtc_state, vblank, wake_lines)) { 4595 drm_dbg_kms(display->drm, 4596 "Adjusting PSR/PR mode: vblank too short for wake lines = %d\n", 4597 wake_lines); 4598 4599 if (crtc_state->has_panel_replay) { 4600 crtc_state->has_panel_replay = false; 4601 /* 4602 * #TODO : Add fall back to PSR/PSR2 4603 * Since panel replay cannot be supported, we can fall back to PSR/PSR2. 4604 * This will require calling compute_config for psr and psr2 with check for 4605 * actual guardband instead of vblank_length. 4606 */ 4607 crtc_state->has_psr = false; 4608 } 4609 4610 crtc_state->has_sel_update = false; 4611 crtc_state->enable_psr2_su_region_et = false; 4612 crtc_state->enable_psr2_sel_fetch = false; 4613 } 4614 4615 /* Wa_18037818876 */ 4616 if (intel_psr_needs_wa_18037818876(intel_dp, crtc_state)) { 4617 crtc_state->has_psr = false; 4618 drm_dbg_kms(display->drm, 4619 "PSR disabled to workaround PSR FSM hang issue\n"); 4620 } 4621 4622 intel_psr_set_non_psr_pipes(intel_dp, crtc_state); 4623 } 4624 4625 int intel_psr_min_guardband(struct intel_crtc_state *crtc_state) 4626 { 4627 struct intel_display *display = to_intel_display(crtc_state); 4628 int psr_min_guardband; 4629 int wake_lines; 4630 4631 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) 4632 return 0; 4633 4634 if (crtc_state->has_panel_replay) 4635 wake_lines = crtc_state->alpm_state.aux_less_wake_lines; 4636 else if (crtc_state->has_sel_update) 4637 wake_lines = DISPLAY_VER(display) < 20 ? 4638 psr2_block_count_lines(crtc_state->alpm_state.io_wake_lines, 4639 crtc_state->alpm_state.fast_wake_lines) : 4640 crtc_state->alpm_state.io_wake_lines; 4641 else 4642 return 0; 4643 4644 psr_min_guardband = wake_lines + crtc_state->set_context_latency; 4645 4646 if (crtc_state->req_psr2_sdp_prior_scanline) 4647 psr_min_guardband++; 4648 4649 return psr_min_guardband; 4650 } 4651 4652 bool intel_psr_use_trans_push(const struct intel_crtc_state *crtc_state) 4653 { 4654 struct intel_display *display = to_intel_display(crtc_state); 4655 4656 return HAS_PSR_TRANS_PUSH_FRAME_CHANGE(display) && crtc_state->has_psr; 4657 } 4658