1 /* 2 * Copyright © 2014 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 */ 23 24 #include <linux/debugfs.h> 25 26 #include <drm/drm_atomic_helper.h> 27 #include <drm/drm_damage_helper.h> 28 #include <drm/drm_debugfs.h> 29 #include <drm/drm_print.h> 30 #include <drm/drm_vblank.h> 31 32 #include "intel_alpm.h" 33 #include "intel_atomic.h" 34 #include "intel_crtc.h" 35 #include "intel_cursor_regs.h" 36 #include "intel_ddi.h" 37 #include "intel_de.h" 38 #include "intel_display_irq.h" 39 #include "intel_display_regs.h" 40 #include "intel_display_rpm.h" 41 #include "intel_display_types.h" 42 #include "intel_display_utils.h" 43 #include "intel_display_wa.h" 44 #include "intel_dmc.h" 45 #include "intel_dp.h" 46 #include "intel_dp_aux.h" 47 #include "intel_dsb.h" 48 #include "intel_frontbuffer.h" 49 #include "intel_hdmi.h" 50 #include "intel_psr.h" 51 #include "intel_psr_regs.h" 52 #include "intel_snps_phy.h" 53 #include "intel_step.h" 54 #include "intel_vblank.h" 55 #include "intel_vdsc.h" 56 #include "intel_vrr.h" 57 #include "skl_universal_plane.h" 58 59 /** 60 * DOC: Panel Self Refresh (PSR/SRD) 61 * 62 * Since Haswell Display controller supports Panel Self-Refresh on display 63 * panels witch have a remote frame buffer (RFB) implemented according to PSR 64 * spec in eDP1.3. PSR feature allows the display to go to lower standby states 65 * when system is idle but display is on as it eliminates display refresh 66 * request to DDR memory completely as long as the frame buffer for that 67 * display is unchanged. 68 * 69 * Panel Self Refresh must be supported by both Hardware (source) and 70 * Panel (sink). 71 * 72 * PSR saves power by caching the framebuffer in the panel RFB, which allows us 73 * to power down the link and memory controller. For DSI panels the same idea 74 * is called "manual mode". 75 * 76 * The implementation uses the hardware-based PSR support which automatically 77 * enters/exits self-refresh mode. The hardware takes care of sending the 78 * required DP aux message and could even retrain the link (that part isn't 79 * enabled yet though). The hardware also keeps track of any frontbuffer 80 * changes to know when to exit self-refresh mode again. Unfortunately that 81 * part doesn't work too well, hence why the i915 PSR support uses the 82 * software frontbuffer tracking to make sure it doesn't miss a screen 83 * update. For this integration intel_psr_invalidate() and intel_psr_flush() 84 * get called by the frontbuffer tracking code. Note that because of locking 85 * issues the self-refresh re-enable code is done from a work queue, which 86 * must be correctly synchronized/cancelled when shutting down the pipe." 87 * 88 * DC3CO (DC3 clock off) 89 * 90 * On top of PSR2, GEN12 adds a intermediate power savings state that turns 91 * clock off automatically during PSR2 idle state. 92 * The smaller overhead of DC3co entry/exit vs. the overhead of PSR2 deep sleep 93 * entry/exit allows the HW to enter a low-power state even when page flipping 94 * periodically (for instance a 30fps video playback scenario). 95 * 96 * Every time a flips occurs PSR2 will get out of deep sleep state(if it was), 97 * so DC3CO is enabled and tgl_dc3co_disable_work is schedule to run after 6 98 * frames, if no other flip occurs and the function above is executed, DC3CO is 99 * disabled and PSR2 is configured to enter deep sleep, resetting again in case 100 * of another flip. 101 * Front buffer modifications do not trigger DC3CO activation on purpose as it 102 * would bring a lot of complexity and most of the moderns systems will only 103 * use page flips. 104 */ 105 106 /* 107 * Description of PSR mask bits: 108 * 109 * EDP_PSR_DEBUG[16]/EDP_PSR_DEBUG_MASK_DISP_REG_WRITE (hsw-skl): 110 * 111 * When unmasked (nearly) all display register writes (eg. even 112 * SWF) trigger a PSR exit. Some registers are excluded from this 113 * and they have a more specific mask (described below). On icl+ 114 * this bit no longer exists and is effectively always set. 115 * 116 * PIPE_MISC[21]/PIPE_MISC_PSR_MASK_PIPE_REG_WRITE (skl+): 117 * 118 * When unmasked (nearly) all pipe/plane register writes 119 * trigger a PSR exit. Some plane registers are excluded from this 120 * and they have a more specific mask (described below). 121 * 122 * CHICKEN_PIPESL_1[11]/SKL_PSR_MASK_PLANE_FLIP (skl+): 123 * PIPE_MISC[23]/PIPE_MISC_PSR_MASK_PRIMARY_FLIP (bdw): 124 * EDP_PSR_DEBUG[23]/EDP_PSR_DEBUG_MASK_PRIMARY_FLIP (hsw): 125 * 126 * When unmasked PRI_SURF/PLANE_SURF writes trigger a PSR exit. 127 * SPR_SURF/CURBASE are not included in this and instead are 128 * controlled by PIPE_MISC_PSR_MASK_PIPE_REG_WRITE (skl+) or 129 * EDP_PSR_DEBUG_MASK_DISP_REG_WRITE (hsw/bdw). 130 * 131 * PIPE_MISC[22]/PIPE_MISC_PSR_MASK_SPRITE_ENABLE (bdw): 132 * EDP_PSR_DEBUG[21]/EDP_PSR_DEBUG_MASK_SPRITE_ENABLE (hsw): 133 * 134 * When unmasked PSR is blocked as long as the sprite 135 * plane is enabled. skl+ with their universal planes no 136 * longer have a mask bit like this, and no plane being 137 * enabledb blocks PSR. 138 * 139 * PIPE_MISC[21]/PIPE_MISC_PSR_MASK_CURSOR_MOVE (bdw): 140 * EDP_PSR_DEBUG[20]/EDP_PSR_DEBUG_MASK_CURSOR_MOVE (hsw): 141 * 142 * When umasked CURPOS writes trigger a PSR exit. On skl+ 143 * this doesn't exit but CURPOS is included in the 144 * PIPE_MISC_PSR_MASK_PIPE_REG_WRITE mask. 145 * 146 * PIPE_MISC[20]/PIPE_MISC_PSR_MASK_VBLANK_VSYNC_INT (bdw+): 147 * EDP_PSR_DEBUG[19]/EDP_PSR_DEBUG_MASK_VBLANK_VSYNC_INT (hsw): 148 * 149 * When unmasked PSR is blocked as long as vblank and/or vsync 150 * interrupt is unmasked in IMR *and* enabled in IER. 151 * 152 * CHICKEN_TRANS[30]/SKL_UNMASK_VBL_TO_PIPE_IN_SRD (skl+): 153 * CHICKEN_PAR1_1[15]/HSW_MASK_VBL_TO_PIPE_IN_SRD (hsw/bdw): 154 * 155 * Selectcs whether PSR exit generates an extra vblank before 156 * the first frame is transmitted. Also note the opposite polarity 157 * if the bit on hsw/bdw vs. skl+ (masked==generate the extra vblank, 158 * unmasked==do not generate the extra vblank). 159 * 160 * With DC states enabled the extra vblank happens after link training, 161 * with DC states disabled it happens immediately upuon PSR exit trigger. 162 * No idea as of now why there is a difference. HSW/BDW (which don't 163 * even have DMC) always generate it after link training. Go figure. 164 * 165 * Unfortunately CHICKEN_TRANS itself seems to be double buffered 166 * and thus won't latch until the first vblank. So with DC states 167 * enabled the register effectively uses the reset value during DC5 168 * exit+PSR exit sequence, and thus the bit does nothing until 169 * latched by the vblank that it was trying to prevent from being 170 * generated in the first place. So we should probably call this 171 * one a chicken/egg bit instead on skl+. 172 * 173 * In standby mode (as opposed to link-off) this makes no difference 174 * as the timing generator keeps running the whole time generating 175 * normal periodic vblanks. 176 * 177 * WaPsrDPAMaskVBlankInSRD asks us to set the bit on hsw/bdw, 178 * and doing so makes the behaviour match the skl+ reset value. 179 * 180 * CHICKEN_PIPESL_1[0]/BDW_UNMASK_VBL_TO_REGS_IN_SRD (bdw): 181 * CHICKEN_PIPESL_1[15]/HSW_UNMASK_VBL_TO_REGS_IN_SRD (hsw): 182 * 183 * On BDW without this bit is no vblanks whatsoever are 184 * generated after PSR exit. On HSW this has no apparent effect. 185 * WaPsrDPRSUnmaskVBlankInSRD says to set this. 186 * 187 * The rest of the bits are more self-explanatory and/or 188 * irrelevant for normal operation. 189 * 190 * Description of intel_crtc_state variables. has_psr, has_panel_replay and 191 * has_sel_update: 192 * 193 * has_psr (alone): PSR1 194 * has_psr + has_sel_update: PSR2 195 * has_psr + has_panel_replay: Panel Replay 196 * has_psr + has_panel_replay + has_sel_update: Panel Replay Selective Update 197 * 198 * Description of some intel_psr variables. enabled, panel_replay_enabled, 199 * sel_update_enabled 200 * 201 * enabled (alone): PSR1 202 * enabled + sel_update_enabled: PSR2 203 * enabled + panel_replay_enabled: Panel Replay 204 * enabled + panel_replay_enabled + sel_update_enabled: Panel Replay SU 205 */ 206 207 #define CAN_PSR(intel_dp) ((intel_dp)->psr.sink_support && \ 208 (intel_dp)->psr.source_support) 209 210 bool intel_encoder_can_psr(struct intel_encoder *encoder) 211 { 212 if (intel_encoder_is_dp(encoder) || encoder->type == INTEL_OUTPUT_DP_MST) 213 return CAN_PSR(enc_to_intel_dp(encoder)) || 214 CAN_PANEL_REPLAY(enc_to_intel_dp(encoder)); 215 else 216 return false; 217 } 218 219 bool intel_psr_needs_aux_io_power(struct intel_encoder *encoder, 220 const struct intel_crtc_state *crtc_state) 221 { 222 /* 223 * For PSR/PR modes only eDP requires the AUX IO power to be enabled whenever 224 * the output is enabled. For non-eDP outputs the main link is always 225 * on, hence it doesn't require the HW initiated AUX wake-up signaling used 226 * for eDP. 227 * 228 * TODO: 229 * - Consider leaving AUX IO disabled for eDP / PR as well, in case 230 * the ALPM with main-link off mode is not enabled. 231 * - Leave AUX IO enabled for DP / PR, once support for ALPM with 232 * main-link off mode is added for it and this mode gets enabled. 233 */ 234 return intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP) && 235 intel_encoder_can_psr(encoder); 236 } 237 238 static bool psr_global_enabled(struct intel_dp *intel_dp) 239 { 240 struct intel_connector *connector = intel_dp->attached_connector; 241 242 switch (intel_dp->psr.debug & I915_PSR_DEBUG_MODE_MASK) { 243 case I915_PSR_DEBUG_DEFAULT: 244 return intel_dp_is_edp(intel_dp) ? 245 connector->panel.vbt.psr.enable : true; 246 case I915_PSR_DEBUG_DISABLE: 247 return false; 248 default: 249 return true; 250 } 251 } 252 253 static bool sel_update_global_enabled(struct intel_dp *intel_dp) 254 { 255 switch (intel_dp->psr.debug & I915_PSR_DEBUG_MODE_MASK) { 256 case I915_PSR_DEBUG_DISABLE: 257 case I915_PSR_DEBUG_FORCE_PSR1: 258 return false; 259 default: 260 return true; 261 } 262 } 263 264 static bool panel_replay_global_enabled(struct intel_dp *intel_dp) 265 { 266 struct intel_display *display = to_intel_display(intel_dp); 267 268 return !(intel_dp->psr.debug & I915_PSR_DEBUG_PANEL_REPLAY_DISABLE) && 269 display->params.enable_panel_replay; 270 } 271 272 static u32 psr_irq_psr_error_bit_get(struct intel_dp *intel_dp) 273 { 274 struct intel_display *display = to_intel_display(intel_dp); 275 276 return DISPLAY_VER(display) >= 12 ? TGL_PSR_ERROR : 277 EDP_PSR_ERROR(intel_dp->psr.transcoder); 278 } 279 280 static u32 psr_irq_post_exit_bit_get(struct intel_dp *intel_dp) 281 { 282 struct intel_display *display = to_intel_display(intel_dp); 283 284 return DISPLAY_VER(display) >= 12 ? TGL_PSR_POST_EXIT : 285 EDP_PSR_POST_EXIT(intel_dp->psr.transcoder); 286 } 287 288 static u32 psr_irq_pre_entry_bit_get(struct intel_dp *intel_dp) 289 { 290 struct intel_display *display = to_intel_display(intel_dp); 291 292 return DISPLAY_VER(display) >= 12 ? TGL_PSR_PRE_ENTRY : 293 EDP_PSR_PRE_ENTRY(intel_dp->psr.transcoder); 294 } 295 296 static u32 psr_irq_mask_get(struct intel_dp *intel_dp) 297 { 298 struct intel_display *display = to_intel_display(intel_dp); 299 300 return DISPLAY_VER(display) >= 12 ? TGL_PSR_MASK : 301 EDP_PSR_MASK(intel_dp->psr.transcoder); 302 } 303 304 static i915_reg_t psr_ctl_reg(struct intel_display *display, 305 enum transcoder cpu_transcoder) 306 { 307 if (DISPLAY_VER(display) >= 8) 308 return EDP_PSR_CTL(display, cpu_transcoder); 309 else 310 return HSW_SRD_CTL; 311 } 312 313 static i915_reg_t psr_debug_reg(struct intel_display *display, 314 enum transcoder cpu_transcoder) 315 { 316 if (DISPLAY_VER(display) >= 8) 317 return EDP_PSR_DEBUG(display, cpu_transcoder); 318 else 319 return HSW_SRD_DEBUG; 320 } 321 322 static i915_reg_t psr_perf_cnt_reg(struct intel_display *display, 323 enum transcoder cpu_transcoder) 324 { 325 if (DISPLAY_VER(display) >= 8) 326 return EDP_PSR_PERF_CNT(display, cpu_transcoder); 327 else 328 return HSW_SRD_PERF_CNT; 329 } 330 331 static i915_reg_t psr_status_reg(struct intel_display *display, 332 enum transcoder cpu_transcoder) 333 { 334 if (DISPLAY_VER(display) >= 8) 335 return EDP_PSR_STATUS(display, cpu_transcoder); 336 else 337 return HSW_SRD_STATUS; 338 } 339 340 static i915_reg_t psr_imr_reg(struct intel_display *display, 341 enum transcoder cpu_transcoder) 342 { 343 if (DISPLAY_VER(display) >= 12) 344 return TRANS_PSR_IMR(display, cpu_transcoder); 345 else 346 return EDP_PSR_IMR; 347 } 348 349 static i915_reg_t psr_iir_reg(struct intel_display *display, 350 enum transcoder cpu_transcoder) 351 { 352 if (DISPLAY_VER(display) >= 12) 353 return TRANS_PSR_IIR(display, cpu_transcoder); 354 else 355 return EDP_PSR_IIR; 356 } 357 358 static i915_reg_t psr_aux_ctl_reg(struct intel_display *display, 359 enum transcoder cpu_transcoder) 360 { 361 if (DISPLAY_VER(display) >= 8) 362 return EDP_PSR_AUX_CTL(display, cpu_transcoder); 363 else 364 return HSW_SRD_AUX_CTL; 365 } 366 367 static i915_reg_t psr_aux_data_reg(struct intel_display *display, 368 enum transcoder cpu_transcoder, int i) 369 { 370 if (DISPLAY_VER(display) >= 8) 371 return EDP_PSR_AUX_DATA(display, cpu_transcoder, i); 372 else 373 return HSW_SRD_AUX_DATA(i); 374 } 375 376 static void psr_irq_control(struct intel_dp *intel_dp) 377 { 378 struct intel_display *display = to_intel_display(intel_dp); 379 enum transcoder cpu_transcoder = intel_dp->psr.transcoder; 380 u32 mask; 381 382 if (intel_dp->psr.panel_replay_enabled) 383 return; 384 385 mask = psr_irq_psr_error_bit_get(intel_dp); 386 if (intel_dp->psr.debug & I915_PSR_DEBUG_IRQ) 387 mask |= psr_irq_post_exit_bit_get(intel_dp) | 388 psr_irq_pre_entry_bit_get(intel_dp); 389 390 intel_de_rmw(display, psr_imr_reg(display, cpu_transcoder), 391 psr_irq_mask_get(intel_dp), ~mask); 392 } 393 394 static void psr_event_print(struct intel_display *display, 395 u32 val, bool sel_update_enabled) 396 { 397 drm_dbg_kms(display->drm, "PSR exit events: 0x%x\n", val); 398 if (val & PSR_EVENT_PSR2_WD_TIMER_EXPIRE) 399 drm_dbg_kms(display->drm, "\tPSR2 watchdog timer expired\n"); 400 if ((val & PSR_EVENT_PSR2_DISABLED) && sel_update_enabled) 401 drm_dbg_kms(display->drm, "\tPSR2 disabled\n"); 402 if (val & PSR_EVENT_SU_DIRTY_FIFO_UNDERRUN) 403 drm_dbg_kms(display->drm, "\tSU dirty FIFO underrun\n"); 404 if (val & PSR_EVENT_SU_CRC_FIFO_UNDERRUN) 405 drm_dbg_kms(display->drm, "\tSU CRC FIFO underrun\n"); 406 if (val & PSR_EVENT_GRAPHICS_RESET) 407 drm_dbg_kms(display->drm, "\tGraphics reset\n"); 408 if (val & PSR_EVENT_PCH_INTERRUPT) 409 drm_dbg_kms(display->drm, "\tPCH interrupt\n"); 410 if (val & PSR_EVENT_MEMORY_UP) 411 drm_dbg_kms(display->drm, "\tMemory up\n"); 412 if (val & PSR_EVENT_FRONT_BUFFER_MODIFY) 413 drm_dbg_kms(display->drm, "\tFront buffer modification\n"); 414 if (val & PSR_EVENT_WD_TIMER_EXPIRE) 415 drm_dbg_kms(display->drm, "\tPSR watchdog timer expired\n"); 416 if (val & PSR_EVENT_PIPE_REGISTERS_UPDATE) 417 drm_dbg_kms(display->drm, "\tPIPE registers updated\n"); 418 if (val & PSR_EVENT_REGISTER_UPDATE) 419 drm_dbg_kms(display->drm, "\tRegister updated\n"); 420 if (val & PSR_EVENT_HDCP_ENABLE) 421 drm_dbg_kms(display->drm, "\tHDCP enabled\n"); 422 if (val & PSR_EVENT_KVMR_SESSION_ENABLE) 423 drm_dbg_kms(display->drm, "\tKVMR session enabled\n"); 424 if (val & PSR_EVENT_VBI_ENABLE) 425 drm_dbg_kms(display->drm, "\tVBI enabled\n"); 426 if (val & PSR_EVENT_LPSP_MODE_EXIT) 427 drm_dbg_kms(display->drm, "\tLPSP mode exited\n"); 428 if ((val & PSR_EVENT_PSR_DISABLE) && !sel_update_enabled) 429 drm_dbg_kms(display->drm, "\tPSR disabled\n"); 430 } 431 432 void intel_psr_irq_handler(struct intel_dp *intel_dp, u32 psr_iir) 433 { 434 struct intel_display *display = to_intel_display(intel_dp); 435 enum transcoder cpu_transcoder = intel_dp->psr.transcoder; 436 ktime_t time_ns = ktime_get(); 437 438 if (psr_iir & psr_irq_pre_entry_bit_get(intel_dp)) { 439 intel_dp->psr.last_entry_attempt = time_ns; 440 drm_dbg_kms(display->drm, 441 "[transcoder %s] PSR entry attempt in 2 vblanks\n", 442 transcoder_name(cpu_transcoder)); 443 } 444 445 if (psr_iir & psr_irq_post_exit_bit_get(intel_dp)) { 446 intel_dp->psr.last_exit = time_ns; 447 drm_dbg_kms(display->drm, 448 "[transcoder %s] PSR exit completed\n", 449 transcoder_name(cpu_transcoder)); 450 451 if (DISPLAY_VER(display) >= 9) { 452 u32 val; 453 454 val = intel_de_rmw(display, 455 PSR_EVENT(display, cpu_transcoder), 456 0, 0); 457 458 psr_event_print(display, val, intel_dp->psr.sel_update_enabled); 459 } 460 } 461 462 if (psr_iir & psr_irq_psr_error_bit_get(intel_dp)) { 463 drm_warn(display->drm, "[transcoder %s] PSR aux error\n", 464 transcoder_name(cpu_transcoder)); 465 466 intel_dp->psr.irq_aux_error = true; 467 468 /* 469 * If this interruption is not masked it will keep 470 * interrupting so fast that it prevents the scheduled 471 * work to run. 472 * Also after a PSR error, we don't want to arm PSR 473 * again so we don't care about unmask the interruption 474 * or unset irq_aux_error. 475 */ 476 intel_de_rmw(display, psr_imr_reg(display, cpu_transcoder), 477 0, psr_irq_psr_error_bit_get(intel_dp)); 478 479 queue_work(display->wq.unordered, &intel_dp->psr.work); 480 } 481 } 482 483 static u8 intel_dp_get_sink_sync_latency(struct intel_dp *intel_dp) 484 { 485 struct intel_display *display = to_intel_display(intel_dp); 486 u8 val = 8; /* assume the worst if we can't read the value */ 487 488 if (drm_dp_dpcd_readb(&intel_dp->aux, 489 DP_SYNCHRONIZATION_LATENCY_IN_SINK, &val) == 1) 490 val &= DP_MAX_RESYNC_FRAME_COUNT_MASK; 491 else 492 drm_dbg_kms(display->drm, 493 "Unable to get sink synchronization latency, assuming 8 frames\n"); 494 return val; 495 } 496 497 static void _psr_compute_su_granularity(struct intel_dp *intel_dp, 498 struct intel_connector *connector) 499 { 500 struct intel_display *display = to_intel_display(intel_dp); 501 ssize_t r; 502 __le16 w; 503 u8 y; 504 505 /* 506 * If sink don't have specific granularity requirements set legacy 507 * ones. 508 */ 509 if (!(connector->dp.psr_caps.dpcd[1] & DP_PSR2_SU_GRANULARITY_REQUIRED)) { 510 /* As PSR2 HW sends full lines, we do not care about x granularity */ 511 w = cpu_to_le16(4); 512 y = 4; 513 goto exit; 514 } 515 516 r = drm_dp_dpcd_read(&intel_dp->aux, DP_PSR2_SU_X_GRANULARITY, &w, sizeof(w)); 517 if (r != sizeof(w)) 518 drm_dbg_kms(display->drm, 519 "Unable to read selective update x granularity\n"); 520 /* 521 * Spec says that if the value read is 0 the default granularity should 522 * be used instead. 523 */ 524 if (r != sizeof(w) || w == 0) 525 w = cpu_to_le16(4); 526 527 r = drm_dp_dpcd_read(&intel_dp->aux, DP_PSR2_SU_Y_GRANULARITY, &y, 1); 528 if (r != 1) { 529 drm_dbg_kms(display->drm, 530 "Unable to read selective update y granularity\n"); 531 y = 4; 532 } 533 if (y == 0) 534 y = 1; 535 536 exit: 537 connector->dp.psr_caps.su_w_granularity = le16_to_cpu(w); 538 connector->dp.psr_caps.su_y_granularity = y; 539 } 540 541 static enum intel_panel_replay_dsc_support 542 compute_pr_dsc_support(struct intel_connector *connector) 543 { 544 u8 pr_dsc_mode; 545 u8 val; 546 547 val = connector->dp.panel_replay_caps.dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_CAPABILITY)]; 548 pr_dsc_mode = REG_FIELD_GET8(DP_PANEL_REPLAY_DSC_DECODE_CAPABILITY_IN_PR_MASK, val); 549 550 switch (pr_dsc_mode) { 551 case DP_DSC_DECODE_CAPABILITY_IN_PR_FULL_FRAME_ONLY: 552 return INTEL_DP_PANEL_REPLAY_DSC_FULL_FRAME_ONLY; 553 case DP_DSC_DECODE_CAPABILITY_IN_PR_SUPPORTED: 554 return INTEL_DP_PANEL_REPLAY_DSC_SELECTIVE_UPDATE; 555 default: 556 MISSING_CASE(pr_dsc_mode); 557 fallthrough; 558 case DP_DSC_DECODE_CAPABILITY_IN_PR_NOT_SUPPORTED: 559 case DP_DSC_DECODE_CAPABILITY_IN_PR_RESERVED: 560 return INTEL_DP_PANEL_REPLAY_DSC_NOT_SUPPORTED; 561 } 562 } 563 564 static const char *panel_replay_dsc_support_str(enum intel_panel_replay_dsc_support dsc_support) 565 { 566 switch (dsc_support) { 567 case INTEL_DP_PANEL_REPLAY_DSC_NOT_SUPPORTED: 568 return "not supported"; 569 case INTEL_DP_PANEL_REPLAY_DSC_FULL_FRAME_ONLY: 570 return "full frame only"; 571 case INTEL_DP_PANEL_REPLAY_DSC_SELECTIVE_UPDATE: 572 return "selective update"; 573 default: 574 MISSING_CASE(dsc_support); 575 return "n/a"; 576 }; 577 } 578 579 static void _panel_replay_compute_su_granularity(struct intel_connector *connector) 580 { 581 u16 w; 582 u8 y; 583 584 if (!(connector->dp.panel_replay_caps.dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_CAPABILITY)] & 585 DP_PANEL_REPLAY_SU_GRANULARITY_REQUIRED)) { 586 w = 4; 587 y = 4; 588 goto exit; 589 } 590 591 /* 592 * Spec says that if the value read is 0 the default granularity should 593 * be used instead. 594 */ 595 w = le16_to_cpu(*(__le16 *)&connector->dp.panel_replay_caps.dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_X_GRANULARITY)]) ? : 4; 596 y = connector->dp.panel_replay_caps.dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_Y_GRANULARITY)] ? : 1; 597 598 exit: 599 connector->dp.panel_replay_caps.su_w_granularity = w; 600 connector->dp.panel_replay_caps.su_y_granularity = y; 601 } 602 603 static void _panel_replay_init_dpcd(struct intel_dp *intel_dp, struct intel_connector *connector) 604 { 605 struct intel_display *display = to_intel_display(intel_dp); 606 int ret; 607 608 /* TODO: Enable Panel Replay on MST once it's properly implemented. */ 609 if (intel_dp->mst_detect == DRM_DP_MST) 610 return; 611 612 ret = drm_dp_dpcd_read_data(&intel_dp->aux, DP_PANEL_REPLAY_CAP_SUPPORT, 613 &connector->dp.panel_replay_caps.dpcd, 614 sizeof(connector->dp.panel_replay_caps.dpcd)); 615 if (ret < 0) 616 return; 617 618 if (!(connector->dp.panel_replay_caps.dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_SUPPORT)] & 619 DP_PANEL_REPLAY_SUPPORT)) 620 return; 621 622 if (intel_dp_is_edp(intel_dp)) { 623 if (!intel_alpm_aux_less_wake_supported(intel_dp)) { 624 drm_dbg_kms(display->drm, 625 "Panel doesn't support AUX-less ALPM, eDP Panel Replay not possible\n"); 626 return; 627 } 628 629 if (!(connector->dp.panel_replay_caps.dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_SUPPORT)] & 630 DP_PANEL_REPLAY_EARLY_TRANSPORT_SUPPORT)) { 631 drm_dbg_kms(display->drm, 632 "Panel doesn't support early transport, eDP Panel Replay not possible\n"); 633 return; 634 } 635 } 636 637 connector->dp.panel_replay_caps.support = true; 638 intel_dp->psr.sink_panel_replay_support = true; 639 640 if (connector->dp.panel_replay_caps.dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_SUPPORT)] & 641 DP_PANEL_REPLAY_SU_SUPPORT) { 642 connector->dp.panel_replay_caps.su_support = true; 643 644 _panel_replay_compute_su_granularity(connector); 645 } 646 647 connector->dp.panel_replay_caps.dsc_support = compute_pr_dsc_support(connector); 648 649 drm_dbg_kms(display->drm, 650 "Panel replay %sis supported by panel (in DSC mode: %s)\n", 651 connector->dp.panel_replay_caps.su_support ? 652 "selective_update " : "", 653 panel_replay_dsc_support_str(connector->dp.panel_replay_caps.dsc_support)); 654 } 655 656 static void _psr_init_dpcd(struct intel_dp *intel_dp, struct intel_connector *connector) 657 { 658 struct intel_display *display = to_intel_display(intel_dp); 659 int ret; 660 661 ret = drm_dp_dpcd_read_data(&intel_dp->aux, DP_PSR_SUPPORT, connector->dp.psr_caps.dpcd, 662 sizeof(connector->dp.psr_caps.dpcd)); 663 if (ret < 0) 664 return; 665 666 if (!connector->dp.psr_caps.dpcd[0]) 667 return; 668 669 drm_dbg_kms(display->drm, "eDP panel supports PSR version %x\n", 670 connector->dp.psr_caps.dpcd[0]); 671 672 if (drm_dp_has_quirk(&intel_dp->desc, DP_DPCD_QUIRK_NO_PSR)) { 673 drm_dbg_kms(display->drm, 674 "PSR support not currently available for this panel\n"); 675 return; 676 } 677 678 if (!(intel_dp->edp_dpcd[1] & DP_EDP_SET_POWER_CAP)) { 679 drm_dbg_kms(display->drm, 680 "Panel lacks power state control, PSR cannot be enabled\n"); 681 return; 682 } 683 684 connector->dp.psr_caps.support = true; 685 intel_dp->psr.sink_support = true; 686 687 connector->dp.psr_caps.sync_latency = intel_dp_get_sink_sync_latency(intel_dp); 688 689 if (DISPLAY_VER(display) >= 9 && 690 connector->dp.psr_caps.dpcd[0] >= DP_PSR2_WITH_Y_COORD_IS_SUPPORTED) { 691 bool y_req = connector->dp.psr_caps.dpcd[1] & 692 DP_PSR2_SU_Y_COORDINATE_REQUIRED; 693 694 /* 695 * All panels that supports PSR version 03h (PSR2 + 696 * Y-coordinate) can handle Y-coordinates in VSC but we are 697 * only sure that it is going to be used when required by the 698 * panel. This way panel is capable to do selective update 699 * without a aux frame sync. 700 * 701 * To support PSR version 02h and PSR version 03h without 702 * Y-coordinate requirement panels we would need to enable 703 * GTC first. 704 */ 705 connector->dp.psr_caps.su_support = y_req && 706 intel_alpm_aux_wake_supported(intel_dp); 707 drm_dbg_kms(display->drm, "PSR2 %ssupported\n", 708 connector->dp.psr_caps.su_support ? "" : "not "); 709 } 710 711 if (connector->dp.psr_caps.su_support) 712 _psr_compute_su_granularity(intel_dp, connector); 713 } 714 715 void intel_psr_init_dpcd(struct intel_dp *intel_dp, struct intel_connector *connector) 716 { 717 _psr_init_dpcd(intel_dp, connector); 718 719 _panel_replay_init_dpcd(intel_dp, connector); 720 } 721 722 static void hsw_psr_setup_aux(struct intel_dp *intel_dp) 723 { 724 struct intel_display *display = to_intel_display(intel_dp); 725 enum transcoder cpu_transcoder = intel_dp->psr.transcoder; 726 u32 aux_clock_divider, aux_ctl; 727 /* write DP_SET_POWER=D0 */ 728 static const u8 aux_msg[] = { 729 [0] = (DP_AUX_NATIVE_WRITE << 4) | ((DP_SET_POWER >> 16) & 0xf), 730 [1] = (DP_SET_POWER >> 8) & 0xff, 731 [2] = DP_SET_POWER & 0xff, 732 [3] = 1 - 1, 733 [4] = DP_SET_POWER_D0, 734 }; 735 int i; 736 737 BUILD_BUG_ON(sizeof(aux_msg) > 20); 738 for (i = 0; i < sizeof(aux_msg); i += 4) 739 intel_de_write(display, 740 psr_aux_data_reg(display, cpu_transcoder, i >> 2), 741 intel_dp_aux_pack(&aux_msg[i], sizeof(aux_msg) - i)); 742 743 aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, 0); 744 745 /* Start with bits set for DDI_AUX_CTL register */ 746 aux_ctl = intel_dp->get_aux_send_ctl(intel_dp, sizeof(aux_msg), 747 aux_clock_divider); 748 749 /* Select only valid bits for SRD_AUX_CTL */ 750 aux_ctl &= EDP_PSR_AUX_CTL_TIME_OUT_MASK | 751 EDP_PSR_AUX_CTL_MESSAGE_SIZE_MASK | 752 EDP_PSR_AUX_CTL_PRECHARGE_2US_MASK | 753 EDP_PSR_AUX_CTL_BIT_CLOCK_2X_MASK; 754 755 intel_de_write(display, psr_aux_ctl_reg(display, cpu_transcoder), 756 aux_ctl); 757 } 758 759 static bool psr2_su_region_et_valid(struct intel_connector *connector, bool panel_replay) 760 { 761 struct intel_dp *intel_dp = intel_attached_dp(connector); 762 struct intel_display *display = to_intel_display(intel_dp); 763 764 if (DISPLAY_VER(display) < 20 || !intel_dp_is_edp(intel_dp) || 765 intel_dp->psr.debug & I915_PSR_DEBUG_SU_REGION_ET_DISABLE) 766 return false; 767 768 return panel_replay ? 769 connector->dp.panel_replay_caps.dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_SUPPORT)] & 770 DP_PANEL_REPLAY_EARLY_TRANSPORT_SUPPORT : 771 connector->dp.psr_caps.dpcd[0] == DP_PSR2_WITH_Y_COORD_ET_SUPPORTED; 772 } 773 774 static void _panel_replay_enable_sink(struct intel_dp *intel_dp, 775 const struct intel_crtc_state *crtc_state) 776 { 777 u8 val = DP_PANEL_REPLAY_ENABLE | 778 DP_PANEL_REPLAY_VSC_SDP_CRC_EN | 779 DP_PANEL_REPLAY_UNRECOVERABLE_ERROR_EN | 780 DP_PANEL_REPLAY_RFB_STORAGE_ERROR_EN | 781 DP_PANEL_REPLAY_ACTIVE_FRAME_CRC_ERROR_EN; 782 u8 panel_replay_config2 = DP_PANEL_REPLAY_CRC_VERIFICATION; 783 784 if (crtc_state->has_sel_update) 785 val |= DP_PANEL_REPLAY_SU_ENABLE; 786 787 if (crtc_state->enable_psr2_su_region_et) 788 val |= DP_PANEL_REPLAY_ENABLE_SU_REGION_ET; 789 790 if (crtc_state->req_psr2_sdp_prior_scanline) 791 panel_replay_config2 |= 792 DP_PANEL_REPLAY_SU_REGION_SCANLINE_CAPTURE; 793 794 drm_dp_dpcd_writeb(&intel_dp->aux, PANEL_REPLAY_CONFIG, val); 795 796 drm_dp_dpcd_writeb(&intel_dp->aux, PANEL_REPLAY_CONFIG2, 797 panel_replay_config2); 798 } 799 800 static void _psr_enable_sink(struct intel_dp *intel_dp, 801 const struct intel_crtc_state *crtc_state) 802 { 803 struct intel_display *display = to_intel_display(intel_dp); 804 u8 val = 0; 805 806 if (crtc_state->has_sel_update) { 807 val |= DP_PSR_ENABLE_PSR2 | DP_PSR_IRQ_HPD_WITH_CRC_ERRORS; 808 } else { 809 if (intel_dp->psr.link_standby) 810 val |= DP_PSR_MAIN_LINK_ACTIVE; 811 812 if (DISPLAY_VER(display) >= 8) 813 val |= DP_PSR_CRC_VERIFICATION; 814 } 815 816 if (crtc_state->req_psr2_sdp_prior_scanline) 817 val |= DP_PSR_SU_REGION_SCANLINE_CAPTURE; 818 819 if (crtc_state->enable_psr2_su_region_et) 820 val |= DP_PANEL_REPLAY_ENABLE_SU_REGION_ET; 821 822 if (intel_dp->psr.entry_setup_frames > 0) 823 val |= DP_PSR_FRAME_CAPTURE; 824 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, val); 825 826 val |= DP_PSR_ENABLE; 827 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, val); 828 } 829 830 static void intel_psr_enable_sink(struct intel_dp *intel_dp, 831 const struct intel_crtc_state *crtc_state) 832 { 833 intel_alpm_enable_sink(intel_dp, crtc_state); 834 835 crtc_state->has_panel_replay ? 836 _panel_replay_enable_sink(intel_dp, crtc_state) : 837 _psr_enable_sink(intel_dp, crtc_state); 838 839 if (intel_dp_is_edp(intel_dp)) 840 drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, DP_SET_POWER_D0); 841 } 842 843 void intel_psr_panel_replay_enable_sink(struct intel_dp *intel_dp) 844 { 845 /* 846 * NOTE: We might want to trigger mode set when 847 * disabling/enabling Panel Replay via debugfs interface to 848 * ensure this bit is cleared/set accordingly. 849 */ 850 if (CAN_PANEL_REPLAY(intel_dp) && panel_replay_global_enabled(intel_dp)) 851 drm_dp_dpcd_writeb(&intel_dp->aux, PANEL_REPLAY_CONFIG, 852 DP_PANEL_REPLAY_ENABLE); 853 } 854 855 static u32 intel_psr1_get_tp_time(struct intel_dp *intel_dp) 856 { 857 struct intel_display *display = to_intel_display(intel_dp); 858 struct intel_connector *connector = intel_dp->attached_connector; 859 u32 val = 0; 860 861 if (DISPLAY_VER(display) >= 11) 862 val |= EDP_PSR_TP4_TIME_0us; 863 864 if (display->params.psr_safest_params) { 865 val |= EDP_PSR_TP1_TIME_2500us; 866 val |= EDP_PSR_TP2_TP3_TIME_2500us; 867 goto check_tp3_sel; 868 } 869 870 if (connector->panel.vbt.psr.tp1_wakeup_time_us == 0) 871 val |= EDP_PSR_TP1_TIME_0us; 872 else if (connector->panel.vbt.psr.tp1_wakeup_time_us <= 100) 873 val |= EDP_PSR_TP1_TIME_100us; 874 else if (connector->panel.vbt.psr.tp1_wakeup_time_us <= 500) 875 val |= EDP_PSR_TP1_TIME_500us; 876 else 877 val |= EDP_PSR_TP1_TIME_2500us; 878 879 if (connector->panel.vbt.psr.tp2_tp3_wakeup_time_us == 0) 880 val |= EDP_PSR_TP2_TP3_TIME_0us; 881 else if (connector->panel.vbt.psr.tp2_tp3_wakeup_time_us <= 100) 882 val |= EDP_PSR_TP2_TP3_TIME_100us; 883 else if (connector->panel.vbt.psr.tp2_tp3_wakeup_time_us <= 500) 884 val |= EDP_PSR_TP2_TP3_TIME_500us; 885 else 886 val |= EDP_PSR_TP2_TP3_TIME_2500us; 887 888 /* 889 * WA 0479: hsw,bdw 890 * "Do not skip both TP1 and TP2/TP3" 891 */ 892 if (DISPLAY_VER(display) < 9 && 893 connector->panel.vbt.psr.tp1_wakeup_time_us == 0 && 894 connector->panel.vbt.psr.tp2_tp3_wakeup_time_us == 0) 895 val |= EDP_PSR_TP2_TP3_TIME_100us; 896 897 check_tp3_sel: 898 if (intel_dp_source_supports_tps3(display) && 899 drm_dp_tps3_supported(intel_dp->dpcd)) 900 val |= EDP_PSR_TP_TP1_TP3; 901 else 902 val |= EDP_PSR_TP_TP1_TP2; 903 904 return val; 905 } 906 907 static u8 psr_compute_idle_frames(struct intel_dp *intel_dp) 908 { 909 struct intel_display *display = to_intel_display(intel_dp); 910 struct intel_connector *connector = intel_dp->attached_connector; 911 int idle_frames; 912 913 /* Let's use 6 as the minimum to cover all known cases including the 914 * off-by-one issue that HW has in some cases. 915 */ 916 idle_frames = max(6, connector->panel.vbt.psr.idle_frames); 917 idle_frames = max(idle_frames, connector->dp.psr_caps.sync_latency + 1); 918 919 if (drm_WARN_ON(display->drm, idle_frames > 0xf)) 920 idle_frames = 0xf; 921 922 return idle_frames; 923 } 924 925 static bool is_dc5_dc6_blocked(struct intel_dp *intel_dp) 926 { 927 struct intel_display *display = to_intel_display(intel_dp); 928 u32 current_dc_state = intel_display_power_get_current_dc_state(display); 929 struct intel_crtc *crtc = intel_crtc_for_pipe(display, intel_dp->psr.pipe); 930 struct drm_vblank_crtc *vblank = drm_crtc_vblank_crtc(&crtc->base); 931 932 return (current_dc_state != DC_STATE_EN_UPTO_DC5 && 933 current_dc_state != DC_STATE_EN_UPTO_DC6) || 934 intel_dp->psr.active_non_psr_pipes || 935 READ_ONCE(vblank->enabled); 936 } 937 938 static void hsw_activate_psr1(struct intel_dp *intel_dp) 939 { 940 struct intel_display *display = to_intel_display(intel_dp); 941 enum transcoder cpu_transcoder = intel_dp->psr.transcoder; 942 u32 max_sleep_time = 0x1f; 943 u32 val = EDP_PSR_ENABLE; 944 945 val |= EDP_PSR_IDLE_FRAMES(psr_compute_idle_frames(intel_dp)); 946 947 if (DISPLAY_VER(display) < 20) 948 val |= EDP_PSR_MAX_SLEEP_TIME(max_sleep_time); 949 950 if (display->platform.haswell) 951 val |= EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES; 952 953 if (intel_dp->psr.link_standby) 954 val |= EDP_PSR_LINK_STANDBY; 955 956 val |= intel_psr1_get_tp_time(intel_dp); 957 958 if (DISPLAY_VER(display) >= 8) 959 val |= EDP_PSR_CRC_ENABLE; 960 961 if (DISPLAY_VER(display) >= 20) 962 val |= LNL_EDP_PSR_ENTRY_SETUP_FRAMES(intel_dp->psr.entry_setup_frames); 963 964 intel_de_rmw(display, psr_ctl_reg(display, cpu_transcoder), 965 ~EDP_PSR_RESTORE_PSR_ACTIVE_CTX_MASK, val); 966 967 /* Wa_16025596647 */ 968 if ((DISPLAY_VER(display) == 20 || 969 IS_DISPLAY_VERx100_STEP(display, 3000, STEP_A0, STEP_B0)) && 970 is_dc5_dc6_blocked(intel_dp) && intel_dp->psr.pkg_c_latency_used) 971 intel_dmc_start_pkgc_exit_at_start_of_undelayed_vblank(display, 972 intel_dp->psr.pipe, 973 true); 974 } 975 976 static u32 intel_psr2_get_tp_time(struct intel_dp *intel_dp) 977 { 978 struct intel_display *display = to_intel_display(intel_dp); 979 struct intel_connector *connector = intel_dp->attached_connector; 980 u32 val = 0; 981 982 if (display->params.psr_safest_params) 983 return EDP_PSR2_TP2_TIME_2500us; 984 985 if (connector->panel.vbt.psr.psr2_tp2_tp3_wakeup_time_us >= 0 && 986 connector->panel.vbt.psr.psr2_tp2_tp3_wakeup_time_us <= 50) 987 val |= EDP_PSR2_TP2_TIME_50us; 988 else if (connector->panel.vbt.psr.psr2_tp2_tp3_wakeup_time_us <= 100) 989 val |= EDP_PSR2_TP2_TIME_100us; 990 else if (connector->panel.vbt.psr.psr2_tp2_tp3_wakeup_time_us <= 500) 991 val |= EDP_PSR2_TP2_TIME_500us; 992 else 993 val |= EDP_PSR2_TP2_TIME_2500us; 994 995 return val; 996 } 997 998 static int 999 psr2_block_count_lines(u8 io_wake_lines, u8 fast_wake_lines) 1000 { 1001 return io_wake_lines < 9 && fast_wake_lines < 9 ? 8 : 12; 1002 } 1003 1004 static int psr2_block_count(struct intel_dp *intel_dp) 1005 { 1006 return psr2_block_count_lines(intel_dp->psr.io_wake_lines, 1007 intel_dp->psr.fast_wake_lines) / 4; 1008 } 1009 1010 static u8 frames_before_su_entry(struct intel_dp *intel_dp) 1011 { 1012 struct intel_connector *connector = intel_dp->attached_connector; 1013 u8 frames_before_su_entry; 1014 1015 frames_before_su_entry = max_t(u8, 1016 connector->dp.psr_caps.sync_latency + 1, 1017 2); 1018 1019 /* Entry setup frames must be at least 1 less than frames before SU entry */ 1020 if (intel_dp->psr.entry_setup_frames >= frames_before_su_entry) 1021 frames_before_su_entry = intel_dp->psr.entry_setup_frames + 1; 1022 1023 return frames_before_su_entry; 1024 } 1025 1026 static void dg2_activate_panel_replay(struct intel_dp *intel_dp) 1027 { 1028 struct intel_display *display = to_intel_display(intel_dp); 1029 struct intel_psr *psr = &intel_dp->psr; 1030 enum transcoder cpu_transcoder = intel_dp->psr.transcoder; 1031 1032 if (intel_dp_is_edp(intel_dp) && psr->sel_update_enabled) { 1033 u32 val = psr->su_region_et_enabled ? 1034 LNL_EDP_PSR2_SU_REGION_ET_ENABLE : 0; 1035 1036 if (intel_dp->psr.req_psr2_sdp_prior_scanline) 1037 val |= EDP_PSR2_SU_SDP_SCANLINE; 1038 1039 intel_de_write(display, EDP_PSR2_CTL(display, cpu_transcoder), 1040 val); 1041 } 1042 1043 intel_de_rmw(display, 1044 PSR2_MAN_TRK_CTL(display, intel_dp->psr.transcoder), 1045 0, ADLP_PSR2_MAN_TRK_CTL_SF_CONTINUOS_FULL_FRAME); 1046 1047 intel_de_rmw(display, TRANS_DP2_CTL(intel_dp->psr.transcoder), 0, 1048 TRANS_DP2_PANEL_REPLAY_ENABLE); 1049 } 1050 1051 static void hsw_activate_psr2(struct intel_dp *intel_dp) 1052 { 1053 struct intel_display *display = to_intel_display(intel_dp); 1054 enum transcoder cpu_transcoder = intel_dp->psr.transcoder; 1055 u32 val = EDP_PSR2_ENABLE; 1056 u32 psr_val = 0; 1057 u8 idle_frames; 1058 1059 /* Wa_16025596647 */ 1060 if ((DISPLAY_VER(display) == 20 || 1061 IS_DISPLAY_VERx100_STEP(display, 3000, STEP_A0, STEP_B0)) && 1062 is_dc5_dc6_blocked(intel_dp) && intel_dp->psr.pkg_c_latency_used) 1063 idle_frames = 0; 1064 else 1065 idle_frames = psr_compute_idle_frames(intel_dp); 1066 val |= EDP_PSR2_IDLE_FRAMES(idle_frames); 1067 1068 if (DISPLAY_VER(display) < 14 && !display->platform.alderlake_p) 1069 val |= EDP_SU_TRACK_ENABLE; 1070 1071 if (DISPLAY_VER(display) >= 10 && DISPLAY_VER(display) < 13) 1072 val |= EDP_Y_COORDINATE_ENABLE; 1073 1074 val |= EDP_PSR2_FRAME_BEFORE_SU(frames_before_su_entry(intel_dp)); 1075 1076 val |= intel_psr2_get_tp_time(intel_dp); 1077 1078 if (DISPLAY_VER(display) >= 12 && DISPLAY_VER(display) < 20) { 1079 if (psr2_block_count(intel_dp) > 2) 1080 val |= TGL_EDP_PSR2_BLOCK_COUNT_NUM_3; 1081 else 1082 val |= TGL_EDP_PSR2_BLOCK_COUNT_NUM_2; 1083 } 1084 1085 /* Wa_22012278275:adl-p */ 1086 if (intel_display_wa(display, INTEL_DISPLAY_WA_22012278275)) { 1087 static const u8 map[] = { 1088 2, /* 5 lines */ 1089 1, /* 6 lines */ 1090 0, /* 7 lines */ 1091 3, /* 8 lines */ 1092 6, /* 9 lines */ 1093 5, /* 10 lines */ 1094 4, /* 11 lines */ 1095 7, /* 12 lines */ 1096 }; 1097 /* 1098 * Still using the default IO_BUFFER_WAKE and FAST_WAKE, see 1099 * comments below for more information 1100 */ 1101 int tmp; 1102 1103 tmp = map[intel_dp->psr.io_wake_lines - 1104 TGL_EDP_PSR2_IO_BUFFER_WAKE_MIN_LINES]; 1105 val |= TGL_EDP_PSR2_IO_BUFFER_WAKE(tmp + TGL_EDP_PSR2_IO_BUFFER_WAKE_MIN_LINES); 1106 1107 tmp = map[intel_dp->psr.fast_wake_lines - TGL_EDP_PSR2_FAST_WAKE_MIN_LINES]; 1108 val |= TGL_EDP_PSR2_FAST_WAKE(tmp + TGL_EDP_PSR2_FAST_WAKE_MIN_LINES); 1109 } else if (DISPLAY_VER(display) >= 20) { 1110 val |= LNL_EDP_PSR2_IO_BUFFER_WAKE(intel_dp->psr.io_wake_lines); 1111 } else if (DISPLAY_VER(display) >= 12) { 1112 val |= TGL_EDP_PSR2_IO_BUFFER_WAKE(intel_dp->psr.io_wake_lines); 1113 val |= TGL_EDP_PSR2_FAST_WAKE(intel_dp->psr.fast_wake_lines); 1114 } else if (DISPLAY_VER(display) >= 9) { 1115 val |= EDP_PSR2_IO_BUFFER_WAKE(intel_dp->psr.io_wake_lines); 1116 val |= EDP_PSR2_FAST_WAKE(intel_dp->psr.fast_wake_lines); 1117 } 1118 1119 if (intel_dp->psr.req_psr2_sdp_prior_scanline) 1120 val |= EDP_PSR2_SU_SDP_SCANLINE; 1121 1122 if (DISPLAY_VER(display) >= 20) 1123 psr_val |= LNL_EDP_PSR_ENTRY_SETUP_FRAMES(intel_dp->psr.entry_setup_frames); 1124 1125 if (intel_dp->psr.psr2_sel_fetch_enabled) { 1126 u32 tmp; 1127 1128 tmp = intel_de_read(display, 1129 PSR2_MAN_TRK_CTL(display, cpu_transcoder)); 1130 drm_WARN_ON(display->drm, !(tmp & PSR2_MAN_TRK_CTL_ENABLE)); 1131 } else if (HAS_PSR2_SEL_FETCH(display)) { 1132 intel_de_write(display, 1133 PSR2_MAN_TRK_CTL(display, cpu_transcoder), 0); 1134 } 1135 1136 if (intel_dp->psr.su_region_et_enabled) 1137 val |= LNL_EDP_PSR2_SU_REGION_ET_ENABLE; 1138 1139 /* 1140 * PSR2 HW is incorrectly using EDP_PSR_TP1_TP3_SEL and BSpec is 1141 * recommending keep this bit unset while PSR2 is enabled. 1142 */ 1143 intel_de_write(display, psr_ctl_reg(display, cpu_transcoder), psr_val); 1144 1145 intel_de_write(display, EDP_PSR2_CTL(display, cpu_transcoder), val); 1146 } 1147 1148 static bool 1149 transcoder_has_psr2(struct intel_display *display, enum transcoder cpu_transcoder) 1150 { 1151 if (display->platform.alderlake_p || DISPLAY_VER(display) >= 14) 1152 return cpu_transcoder == TRANSCODER_A || cpu_transcoder == TRANSCODER_B; 1153 else if (DISPLAY_VER(display) >= 12) 1154 return cpu_transcoder == TRANSCODER_A; 1155 else if (DISPLAY_VER(display) >= 9) 1156 return cpu_transcoder == TRANSCODER_EDP; 1157 else 1158 return false; 1159 } 1160 1161 static u32 intel_get_frame_time_us(const struct intel_crtc_state *crtc_state) 1162 { 1163 if (!crtc_state->hw.active) 1164 return 0; 1165 1166 return DIV_ROUND_UP(1000 * 1000, 1167 drm_mode_vrefresh(&crtc_state->hw.adjusted_mode)); 1168 } 1169 1170 static void psr2_program_idle_frames(struct intel_dp *intel_dp, 1171 u32 idle_frames) 1172 { 1173 struct intel_display *display = to_intel_display(intel_dp); 1174 enum transcoder cpu_transcoder = intel_dp->psr.transcoder; 1175 1176 intel_de_rmw(display, EDP_PSR2_CTL(display, cpu_transcoder), 1177 EDP_PSR2_IDLE_FRAMES_MASK, 1178 EDP_PSR2_IDLE_FRAMES(idle_frames)); 1179 } 1180 1181 static void tgl_psr2_enable_dc3co(struct intel_dp *intel_dp) 1182 { 1183 struct intel_display *display = to_intel_display(intel_dp); 1184 1185 psr2_program_idle_frames(intel_dp, 0); 1186 intel_display_power_set_target_dc_state(display, DC_STATE_EN_DC3CO); 1187 } 1188 1189 static void tgl_psr2_disable_dc3co(struct intel_dp *intel_dp) 1190 { 1191 struct intel_display *display = to_intel_display(intel_dp); 1192 1193 intel_display_power_set_target_dc_state(display, DC_STATE_EN_UPTO_DC6); 1194 psr2_program_idle_frames(intel_dp, psr_compute_idle_frames(intel_dp)); 1195 } 1196 1197 static void tgl_dc3co_disable_work(struct work_struct *work) 1198 { 1199 struct intel_dp *intel_dp = 1200 container_of(work, typeof(*intel_dp), psr.dc3co_work.work); 1201 1202 mutex_lock(&intel_dp->psr.lock); 1203 /* If delayed work is pending, it is not idle */ 1204 if (delayed_work_pending(&intel_dp->psr.dc3co_work)) 1205 goto unlock; 1206 1207 tgl_psr2_disable_dc3co(intel_dp); 1208 unlock: 1209 mutex_unlock(&intel_dp->psr.lock); 1210 } 1211 1212 static void tgl_disallow_dc3co_on_psr2_exit(struct intel_dp *intel_dp) 1213 { 1214 if (!intel_dp->psr.dc3co_exitline) 1215 return; 1216 1217 cancel_delayed_work(&intel_dp->psr.dc3co_work); 1218 /* Before PSR2 exit disallow dc3co*/ 1219 tgl_psr2_disable_dc3co(intel_dp); 1220 } 1221 1222 static bool 1223 dc3co_is_pipe_port_compatible(struct intel_dp *intel_dp, 1224 struct intel_crtc_state *crtc_state) 1225 { 1226 struct intel_display *display = to_intel_display(intel_dp); 1227 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 1228 enum pipe pipe = to_intel_crtc(crtc_state->uapi.crtc)->pipe; 1229 enum port port = dig_port->base.port; 1230 1231 if (display->platform.alderlake_p || DISPLAY_VER(display) >= 14) 1232 return pipe <= PIPE_B && port <= PORT_B; 1233 else 1234 return pipe == PIPE_A && port == PORT_A; 1235 } 1236 1237 static void 1238 tgl_dc3co_exitline_compute_config(struct intel_dp *intel_dp, 1239 struct intel_crtc_state *crtc_state) 1240 { 1241 struct intel_display *display = to_intel_display(intel_dp); 1242 const u32 crtc_vdisplay = crtc_state->uapi.adjusted_mode.crtc_vdisplay; 1243 struct i915_power_domains *power_domains = &display->power.domains; 1244 u32 exit_scanlines; 1245 1246 /* 1247 * FIXME: Due to the changed sequence of activating/deactivating DC3CO, 1248 * disable DC3CO until the changed dc3co activating/deactivating sequence 1249 * is applied. B.Specs:49196 1250 */ 1251 return; 1252 1253 /* 1254 * DMC's DC3CO exit mechanism has an issue with Selective Fecth 1255 * TODO: when the issue is addressed, this restriction should be removed. 1256 */ 1257 if (crtc_state->enable_psr2_sel_fetch) 1258 return; 1259 1260 if (!(power_domains->allowed_dc_mask & DC_STATE_EN_DC3CO)) 1261 return; 1262 1263 if (!dc3co_is_pipe_port_compatible(intel_dp, crtc_state)) 1264 return; 1265 1266 /* Wa_16011303918:adl-p */ 1267 if (intel_display_wa(display, INTEL_DISPLAY_WA_16011303918)) 1268 return; 1269 1270 /* 1271 * DC3CO Exit time 200us B.Spec 49196 1272 * PSR2 transcoder Early Exit scanlines = ROUNDUP(200 / line time) + 1 1273 */ 1274 exit_scanlines = 1275 intel_usecs_to_scanlines(&crtc_state->uapi.adjusted_mode, 200) + 1; 1276 1277 if (drm_WARN_ON(display->drm, exit_scanlines > crtc_vdisplay)) 1278 return; 1279 1280 crtc_state->dc3co_exitline = crtc_vdisplay - exit_scanlines; 1281 } 1282 1283 static bool intel_psr2_sel_fetch_config_valid(struct intel_dp *intel_dp, 1284 struct intel_crtc_state *crtc_state) 1285 { 1286 struct intel_display *display = to_intel_display(intel_dp); 1287 1288 if (!display->params.enable_psr2_sel_fetch && 1289 intel_dp->psr.debug != I915_PSR_DEBUG_ENABLE_SEL_FETCH) { 1290 drm_dbg_kms(display->drm, 1291 "PSR2 sel fetch not enabled, disabled by parameter\n"); 1292 return false; 1293 } 1294 1295 return crtc_state->enable_psr2_sel_fetch = true; 1296 } 1297 1298 static bool psr2_granularity_check(struct intel_crtc_state *crtc_state, 1299 struct intel_connector *connector) 1300 { 1301 struct intel_dp *intel_dp = intel_attached_dp(connector); 1302 struct intel_display *display = to_intel_display(intel_dp); 1303 const struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config; 1304 const int crtc_hdisplay = crtc_state->hw.adjusted_mode.crtc_hdisplay; 1305 const int crtc_vdisplay = crtc_state->hw.adjusted_mode.crtc_vdisplay; 1306 u16 y_granularity = 0; 1307 u16 sink_y_granularity = crtc_state->has_panel_replay ? 1308 connector->dp.panel_replay_caps.su_y_granularity : 1309 connector->dp.psr_caps.su_y_granularity; 1310 u16 sink_w_granularity; 1311 1312 if (crtc_state->has_panel_replay) 1313 sink_w_granularity = connector->dp.panel_replay_caps.su_w_granularity == 1314 DP_PANEL_REPLAY_FULL_LINE_GRANULARITY ? 1315 crtc_hdisplay : connector->dp.panel_replay_caps.su_w_granularity; 1316 else 1317 sink_w_granularity = connector->dp.psr_caps.su_w_granularity; 1318 1319 /* PSR2 HW only send full lines so we only need to validate the width */ 1320 if (crtc_hdisplay % sink_w_granularity) 1321 return false; 1322 1323 if (crtc_vdisplay % sink_y_granularity) 1324 return false; 1325 1326 /* HW tracking is only aligned to 4 lines */ 1327 if (!crtc_state->enable_psr2_sel_fetch) 1328 return sink_y_granularity == 4; 1329 1330 /* 1331 * adl_p and mtl platforms have 1 line granularity. 1332 * For other platforms with SW tracking we can adjust the y coordinates 1333 * to match sink requirement if multiple of 4. 1334 */ 1335 if (display->platform.alderlake_p || DISPLAY_VER(display) >= 14) 1336 y_granularity = sink_y_granularity; 1337 else if (sink_y_granularity <= 2) 1338 y_granularity = 4; 1339 else if ((sink_y_granularity % 4) == 0) 1340 y_granularity = sink_y_granularity; 1341 1342 if (y_granularity == 0 || crtc_vdisplay % y_granularity) 1343 return false; 1344 1345 if (crtc_state->dsc.compression_enable && 1346 vdsc_cfg->slice_height % y_granularity) 1347 return false; 1348 1349 crtc_state->su_y_granularity = y_granularity; 1350 return true; 1351 } 1352 1353 static bool _compute_psr2_sdp_prior_scanline_indication(struct intel_dp *intel_dp, 1354 struct intel_crtc_state *crtc_state) 1355 { 1356 struct intel_display *display = to_intel_display(intel_dp); 1357 const struct drm_display_mode *adjusted_mode = &crtc_state->uapi.adjusted_mode; 1358 u32 hblank_total, hblank_ns, req_ns; 1359 1360 hblank_total = adjusted_mode->crtc_hblank_end - adjusted_mode->crtc_hblank_start; 1361 hblank_ns = div_u64(1000000ULL * hblank_total, adjusted_mode->crtc_clock); 1362 1363 /* From spec: ((60 / number of lanes) + 11) * 1000 / symbol clock frequency MHz */ 1364 req_ns = ((60 / crtc_state->lane_count) + 11) * 1000 / (crtc_state->port_clock / 1000); 1365 1366 if ((hblank_ns - req_ns) > 100) 1367 return true; 1368 1369 /* Not supported <13 / Wa_22012279113:adl-p */ 1370 if (DISPLAY_VER(display) < 14 || intel_dp->edp_dpcd[0] < DP_EDP_14b) 1371 return false; 1372 1373 crtc_state->req_psr2_sdp_prior_scanline = true; 1374 return true; 1375 } 1376 1377 static int intel_psr_entry_setup_frames(struct intel_dp *intel_dp, 1378 struct drm_connector_state *conn_state, 1379 const struct drm_display_mode *adjusted_mode) 1380 { 1381 struct intel_display *display = to_intel_display(intel_dp); 1382 struct intel_connector *connector = to_intel_connector(conn_state->connector); 1383 int psr_setup_time = drm_dp_psr_setup_time(connector->dp.psr_caps.dpcd); 1384 int entry_setup_frames = 0; 1385 1386 if (psr_setup_time < 0) { 1387 drm_dbg_kms(display->drm, 1388 "PSR condition failed: Invalid PSR setup time (0x%02x)\n", 1389 connector->dp.psr_caps.dpcd[1]); 1390 return -ETIME; 1391 } 1392 1393 if (intel_usecs_to_scanlines(adjusted_mode, psr_setup_time) > 1394 adjusted_mode->crtc_vtotal - adjusted_mode->crtc_vdisplay - 1) { 1395 if (DISPLAY_VER(display) >= 20) { 1396 /* setup entry frames can be up to 3 frames */ 1397 entry_setup_frames = 1; 1398 drm_dbg_kms(display->drm, 1399 "PSR setup entry frames %d\n", 1400 entry_setup_frames); 1401 } else { 1402 drm_dbg_kms(display->drm, 1403 "PSR condition failed: PSR setup time (%d us) too long\n", 1404 psr_setup_time); 1405 return -ETIME; 1406 } 1407 } 1408 1409 return entry_setup_frames; 1410 } 1411 1412 static 1413 int _intel_psr_min_set_context_latency(const struct intel_crtc_state *crtc_state, 1414 bool needs_panel_replay, 1415 bool needs_sel_update) 1416 { 1417 struct intel_display *display = to_intel_display(crtc_state); 1418 1419 if (!crtc_state->has_psr) 1420 return 0; 1421 1422 /* Wa_14015401596 */ 1423 if (intel_vrr_possible(crtc_state) && IS_DISPLAY_VER(display, 13, 14)) 1424 return 1; 1425 1426 /* Rest is for SRD_STATUS needed on LunarLake and onwards */ 1427 if (DISPLAY_VER(display) < 20) 1428 return 0; 1429 1430 /* 1431 * Comment on SRD_STATUS register in Bspec for LunarLake and onwards: 1432 * 1433 * To deterministically capture the transition of the state machine 1434 * going from SRDOFFACK to IDLE, the delayed V. Blank should be at least 1435 * one line after the non-delayed V. Blank. 1436 * 1437 * Legacy TG: TRANS_SET_CONTEXT_LATENCY > 0 1438 * VRR TG: TRANS_VRR_CTL[ VRR Guardband ] < (TRANS_VRR_VMAX[ VRR Vmax ] 1439 * - TRANS_VTOTAL[ Vertical Active ]) 1440 * 1441 * SRD_STATUS is used only by PSR1 on PantherLake. 1442 * SRD_STATUS is used by PSR1 and Panel Replay DP on LunarLake. 1443 */ 1444 1445 if (DISPLAY_VER(display) >= 30 && (needs_panel_replay || 1446 needs_sel_update)) 1447 return 0; 1448 else if (DISPLAY_VER(display) < 30 && (needs_sel_update || 1449 intel_crtc_has_type(crtc_state, 1450 INTEL_OUTPUT_EDP))) 1451 return 0; 1452 else 1453 return 1; 1454 } 1455 1456 static bool _wake_lines_fit_into_vblank(const struct intel_crtc_state *crtc_state, 1457 int vblank, 1458 int wake_lines) 1459 { 1460 if (crtc_state->req_psr2_sdp_prior_scanline) 1461 vblank -= 1; 1462 1463 /* Vblank >= PSR2_CTL Block Count Number maximum line count */ 1464 if (vblank < wake_lines) 1465 return false; 1466 1467 return true; 1468 } 1469 1470 static bool wake_lines_fit_into_vblank(struct intel_dp *intel_dp, 1471 const struct intel_crtc_state *crtc_state, 1472 bool aux_less, 1473 bool needs_panel_replay, 1474 bool needs_sel_update) 1475 { 1476 struct intel_display *display = to_intel_display(intel_dp); 1477 int vblank = crtc_state->hw.adjusted_mode.crtc_vblank_end - 1478 crtc_state->hw.adjusted_mode.crtc_vblank_start; 1479 int wake_lines; 1480 int scl = _intel_psr_min_set_context_latency(crtc_state, 1481 needs_panel_replay, 1482 needs_sel_update); 1483 vblank -= scl; 1484 1485 if (aux_less) 1486 wake_lines = crtc_state->alpm_state.aux_less_wake_lines; 1487 else 1488 wake_lines = DISPLAY_VER(display) < 20 ? 1489 psr2_block_count_lines(crtc_state->alpm_state.io_wake_lines, 1490 crtc_state->alpm_state.fast_wake_lines) : 1491 crtc_state->alpm_state.io_wake_lines; 1492 1493 /* 1494 * Guardband has not been computed yet, so we conservatively check if the 1495 * full vblank duration is sufficient to accommodate wake line requirements 1496 * for PSR features like Panel Replay and Selective Update. 1497 * 1498 * Once the actual guardband is available, a more accurate validation is 1499 * performed in intel_psr_compute_config_late(), and PSR features are 1500 * disabled if wake lines exceed the available guardband. 1501 */ 1502 return _wake_lines_fit_into_vblank(crtc_state, vblank, wake_lines); 1503 } 1504 1505 static bool alpm_config_valid(struct intel_dp *intel_dp, 1506 struct intel_crtc_state *crtc_state, 1507 bool aux_less, 1508 bool needs_panel_replay, 1509 bool needs_sel_update) 1510 { 1511 struct intel_display *display = to_intel_display(intel_dp); 1512 1513 if (!intel_alpm_compute_params(intel_dp, crtc_state)) { 1514 drm_dbg_kms(display->drm, 1515 "PSR2/Panel Replay not enabled, Unable to use long enough wake times\n"); 1516 return false; 1517 } 1518 1519 if (!wake_lines_fit_into_vblank(intel_dp, crtc_state, aux_less, 1520 needs_panel_replay, needs_sel_update)) { 1521 drm_dbg_kms(display->drm, 1522 "PSR2/Panel Replay not enabled, too short vblank time\n"); 1523 return false; 1524 } 1525 1526 return true; 1527 } 1528 1529 static bool intel_psr2_config_valid(struct intel_dp *intel_dp, 1530 struct intel_crtc_state *crtc_state, 1531 struct drm_connector_state *conn_state) 1532 { 1533 struct intel_display *display = to_intel_display(intel_dp); 1534 struct intel_connector *connector = to_intel_connector(conn_state->connector); 1535 int crtc_hdisplay = crtc_state->hw.adjusted_mode.crtc_hdisplay; 1536 int crtc_vdisplay = crtc_state->hw.adjusted_mode.crtc_vdisplay; 1537 int psr_max_h = 0, psr_max_v = 0, max_bpp = 0; 1538 1539 if (!connector->dp.psr_caps.su_support || display->params.enable_psr == 1) 1540 return false; 1541 1542 /* JSL and EHL only supports eDP 1.3 */ 1543 if (display->platform.jasperlake || display->platform.elkhartlake) { 1544 drm_dbg_kms(display->drm, "PSR2 not supported by phy\n"); 1545 return false; 1546 } 1547 1548 /* Wa_16011181250 */ 1549 if (intel_display_wa(display, INTEL_DISPLAY_WA_16011181250)) { 1550 drm_dbg_kms(display->drm, 1551 "PSR2 is defeatured for this platform\n"); 1552 return false; 1553 } 1554 1555 if (display->platform.alderlake_p && IS_DISPLAY_STEP(display, STEP_A0, STEP_B0)) { 1556 drm_dbg_kms(display->drm, 1557 "PSR2 not completely functional in this stepping\n"); 1558 return false; 1559 } 1560 1561 if (!transcoder_has_psr2(display, crtc_state->cpu_transcoder)) { 1562 drm_dbg_kms(display->drm, 1563 "PSR2 not supported in transcoder %s\n", 1564 transcoder_name(crtc_state->cpu_transcoder)); 1565 return false; 1566 } 1567 1568 /* 1569 * DSC and PSR2 cannot be enabled simultaneously. If a requested 1570 * resolution requires DSC to be enabled, priority is given to DSC 1571 * over PSR2. 1572 */ 1573 if (crtc_state->dsc.compression_enable && 1574 (DISPLAY_VER(display) < 14 && !display->platform.alderlake_p)) { 1575 drm_dbg_kms(display->drm, 1576 "PSR2 cannot be enabled since DSC is enabled\n"); 1577 return false; 1578 } 1579 1580 if (DISPLAY_VER(display) >= 20) { 1581 psr_max_h = crtc_hdisplay; 1582 psr_max_v = crtc_vdisplay; 1583 max_bpp = crtc_state->pipe_bpp; 1584 } else if (IS_DISPLAY_VER(display, 12, 14)) { 1585 psr_max_h = 5120; 1586 psr_max_v = 3200; 1587 max_bpp = 30; 1588 } else if (IS_DISPLAY_VER(display, 10, 11)) { 1589 psr_max_h = 4096; 1590 psr_max_v = 2304; 1591 max_bpp = 24; 1592 } else if (DISPLAY_VER(display) == 9) { 1593 psr_max_h = 3640; 1594 psr_max_v = 2304; 1595 max_bpp = 24; 1596 } 1597 1598 if (crtc_state->pipe_bpp > max_bpp) { 1599 drm_dbg_kms(display->drm, 1600 "PSR2 not enabled, pipe bpp %d > max supported %d\n", 1601 crtc_state->pipe_bpp, max_bpp); 1602 return false; 1603 } 1604 1605 /* Wa_16011303918:adl-p */ 1606 if (crtc_state->vrr.enable && 1607 display->platform.alderlake_p && IS_DISPLAY_STEP(display, STEP_A0, STEP_B0)) { 1608 drm_dbg_kms(display->drm, 1609 "PSR2 not enabled, not compatible with HW stepping + VRR\n"); 1610 return false; 1611 } 1612 1613 if (!alpm_config_valid(intel_dp, crtc_state, false, false, true)) 1614 return false; 1615 1616 if (!crtc_state->enable_psr2_sel_fetch && 1617 (crtc_hdisplay > psr_max_h || crtc_vdisplay > psr_max_v)) { 1618 drm_dbg_kms(display->drm, 1619 "PSR2 not enabled, resolution %dx%d > max supported %dx%d\n", 1620 crtc_hdisplay, crtc_vdisplay, 1621 psr_max_h, psr_max_v); 1622 return false; 1623 } 1624 1625 tgl_dc3co_exitline_compute_config(intel_dp, crtc_state); 1626 1627 return true; 1628 } 1629 1630 static bool intel_sel_update_config_valid(struct intel_crtc_state *crtc_state, 1631 struct drm_connector_state *conn_state) 1632 { 1633 struct intel_connector *connector = to_intel_connector(conn_state->connector); 1634 struct intel_dp *intel_dp = intel_attached_dp(connector); 1635 struct intel_display *display = to_intel_display(intel_dp); 1636 1637 if (HAS_PSR2_SEL_FETCH(display) && 1638 !intel_psr2_sel_fetch_config_valid(intel_dp, crtc_state) && 1639 !HAS_PSR_HW_TRACKING(display)) { 1640 drm_dbg_kms(display->drm, 1641 "Selective update not enabled, selective fetch not valid and no HW tracking available\n"); 1642 goto unsupported; 1643 } 1644 1645 if (!sel_update_global_enabled(intel_dp)) { 1646 drm_dbg_kms(display->drm, 1647 "Selective update disabled by flag\n"); 1648 goto unsupported; 1649 } 1650 1651 if (!crtc_state->has_panel_replay && !intel_psr2_config_valid(intel_dp, crtc_state, 1652 conn_state)) 1653 goto unsupported; 1654 1655 if (!_compute_psr2_sdp_prior_scanline_indication(intel_dp, crtc_state)) { 1656 drm_dbg_kms(display->drm, 1657 "Selective update not enabled, SDP indication do not fit in hblank\n"); 1658 goto unsupported; 1659 } 1660 1661 if (crtc_state->has_panel_replay) { 1662 if (DISPLAY_VER(display) < 14) 1663 goto unsupported; 1664 1665 if (!connector->dp.panel_replay_caps.su_support) 1666 goto unsupported; 1667 1668 if (intel_dsc_enabled_on_link(crtc_state) && 1669 connector->dp.panel_replay_caps.dsc_support != 1670 INTEL_DP_PANEL_REPLAY_DSC_SELECTIVE_UPDATE) { 1671 drm_dbg_kms(display->drm, 1672 "Selective update with Panel Replay not enabled because it's not supported with DSC\n"); 1673 goto unsupported; 1674 } 1675 } 1676 1677 if (crtc_state->crc_enabled) { 1678 drm_dbg_kms(display->drm, 1679 "Selective update not enabled because it would inhibit pipe CRC calculation\n"); 1680 goto unsupported; 1681 } 1682 1683 if (!psr2_granularity_check(crtc_state, connector)) { 1684 drm_dbg_kms(display->drm, 1685 "Selective update not enabled, SU granularity not compatible\n"); 1686 goto unsupported; 1687 } 1688 1689 crtc_state->enable_psr2_su_region_et = psr2_su_region_et_valid(connector, 1690 crtc_state->has_panel_replay); 1691 1692 return true; 1693 1694 unsupported: 1695 crtc_state->enable_psr2_sel_fetch = false; 1696 return false; 1697 } 1698 1699 static bool _psr_compute_config(struct intel_dp *intel_dp, 1700 struct intel_crtc_state *crtc_state, 1701 struct drm_connector_state *conn_state) 1702 { 1703 struct intel_display *display = to_intel_display(intel_dp); 1704 const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; 1705 int entry_setup_frames; 1706 1707 if (!CAN_PSR(intel_dp) || !display->params.enable_psr) 1708 return false; 1709 1710 /* 1711 * Currently PSR doesn't work reliably with VRR enabled. 1712 */ 1713 if (crtc_state->vrr.enable) 1714 return false; 1715 1716 entry_setup_frames = intel_psr_entry_setup_frames(intel_dp, conn_state, adjusted_mode); 1717 1718 if (entry_setup_frames >= 0) { 1719 intel_dp->psr.entry_setup_frames = entry_setup_frames; 1720 } else { 1721 crtc_state->no_psr_reason = "PSR setup timing not met"; 1722 drm_dbg_kms(display->drm, 1723 "PSR condition failed: PSR setup timing not met\n"); 1724 return false; 1725 } 1726 1727 return true; 1728 } 1729 1730 static inline bool compute_link_off_after_as_sdp_when_pr_active(struct intel_connector *connector) 1731 { 1732 return (connector->dp.panel_replay_caps.dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_CAPABILITY)] & 1733 DP_PANEL_REPLAY_LINK_OFF_SUPPORTED_IN_PR_AFTER_ADAPTIVE_SYNC_SDP); 1734 } 1735 1736 static inline bool compute_disable_as_sdp_when_pr_active(struct intel_connector *connector) 1737 { 1738 return !(connector->dp.panel_replay_caps.dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_CAPABILITY)] & 1739 DP_PANEL_REPLAY_ASYNC_VIDEO_TIMING_NOT_SUPPORTED_IN_PR); 1740 } 1741 1742 static bool _panel_replay_compute_config(struct intel_crtc_state *crtc_state, 1743 const struct drm_connector_state *conn_state) 1744 { 1745 struct intel_connector *connector = 1746 to_intel_connector(conn_state->connector); 1747 struct intel_dp *intel_dp = intel_attached_dp(connector); 1748 struct intel_display *display = to_intel_display(intel_dp); 1749 struct intel_hdcp *hdcp = &connector->hdcp; 1750 1751 if (!CAN_PANEL_REPLAY(intel_dp)) 1752 return false; 1753 1754 if (!connector->dp.panel_replay_caps.support) 1755 return false; 1756 1757 if (!panel_replay_global_enabled(intel_dp)) { 1758 drm_dbg_kms(display->drm, "Panel Replay disabled by flag\n"); 1759 return false; 1760 } 1761 1762 if (crtc_state->crc_enabled) { 1763 drm_dbg_kms(display->drm, 1764 "Panel Replay not enabled because it would inhibit pipe CRC calculation\n"); 1765 return false; 1766 } 1767 1768 if (intel_dsc_enabled_on_link(crtc_state) && 1769 connector->dp.panel_replay_caps.dsc_support == 1770 INTEL_DP_PANEL_REPLAY_DSC_NOT_SUPPORTED) { 1771 drm_dbg_kms(display->drm, 1772 "Panel Replay not enabled because it's not supported with DSC\n"); 1773 return false; 1774 } 1775 1776 crtc_state->link_off_after_as_sdp_when_pr_active = compute_link_off_after_as_sdp_when_pr_active(connector); 1777 crtc_state->disable_as_sdp_when_pr_active = compute_disable_as_sdp_when_pr_active(connector); 1778 1779 if (!intel_dp_is_edp(intel_dp)) 1780 return true; 1781 1782 /* Remaining checks are for eDP only */ 1783 1784 if (to_intel_crtc(crtc_state->uapi.crtc)->pipe != PIPE_A && 1785 to_intel_crtc(crtc_state->uapi.crtc)->pipe != PIPE_B) 1786 return false; 1787 1788 /* 128b/132b Panel Replay is not supported on eDP */ 1789 if (intel_dp_is_uhbr(crtc_state)) { 1790 drm_dbg_kms(display->drm, 1791 "Panel Replay is not supported with 128b/132b\n"); 1792 return false; 1793 } 1794 1795 /* HW will not allow Panel Replay on eDP when HDCP enabled */ 1796 if (conn_state->content_protection == 1797 DRM_MODE_CONTENT_PROTECTION_DESIRED || 1798 (conn_state->content_protection == 1799 DRM_MODE_CONTENT_PROTECTION_ENABLED && hdcp->value == 1800 DRM_MODE_CONTENT_PROTECTION_UNDESIRED)) { 1801 drm_dbg_kms(display->drm, 1802 "Panel Replay is not supported with HDCP\n"); 1803 return false; 1804 } 1805 1806 if (!alpm_config_valid(intel_dp, crtc_state, true, true, false)) 1807 return false; 1808 1809 return true; 1810 } 1811 1812 static bool intel_psr_needs_wa_18037818876(struct intel_dp *intel_dp, 1813 struct intel_crtc_state *crtc_state) 1814 { 1815 struct intel_display *display = to_intel_display(intel_dp); 1816 1817 return (DISPLAY_VER(display) == 20 && intel_dp->psr.entry_setup_frames > 0 && 1818 !crtc_state->has_sel_update); 1819 } 1820 1821 static 1822 void intel_psr_set_non_psr_pipes(struct intel_dp *intel_dp, 1823 struct intel_crtc_state *crtc_state) 1824 { 1825 struct intel_display *display = to_intel_display(intel_dp); 1826 struct intel_atomic_state *state = to_intel_atomic_state(crtc_state->uapi.state); 1827 struct intel_crtc *crtc; 1828 u8 active_pipes = 0; 1829 1830 /* Wa_16025596647 */ 1831 if (!intel_display_wa(display, INTEL_DISPLAY_WA_16025596647)) 1832 return; 1833 1834 /* Not needed by Panel Replay */ 1835 if (crtc_state->has_panel_replay) 1836 return; 1837 1838 /* We ignore possible secondary PSR/Panel Replay capable eDP */ 1839 for_each_intel_crtc(display->drm, crtc) 1840 active_pipes |= crtc->active ? BIT(crtc->pipe) : 0; 1841 1842 active_pipes = intel_calc_active_pipes(state, active_pipes); 1843 1844 crtc_state->active_non_psr_pipes = active_pipes & 1845 ~BIT(to_intel_crtc(crtc_state->uapi.crtc)->pipe); 1846 } 1847 1848 void intel_psr_compute_config(struct intel_dp *intel_dp, 1849 struct intel_crtc_state *crtc_state, 1850 struct drm_connector_state *conn_state) 1851 { 1852 struct intel_display *display = to_intel_display(intel_dp); 1853 struct intel_connector *connector = to_intel_connector(conn_state->connector); 1854 const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; 1855 1856 if (!psr_global_enabled(intel_dp)) { 1857 drm_dbg_kms(display->drm, "PSR disabled by flag\n"); 1858 return; 1859 } 1860 1861 if (intel_dp->psr.sink_not_reliable) { 1862 drm_dbg_kms(display->drm, 1863 "PSR sink implementation is not reliable\n"); 1864 return; 1865 } 1866 1867 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { 1868 drm_dbg_kms(display->drm, 1869 "PSR condition failed: Interlaced mode enabled\n"); 1870 return; 1871 } 1872 1873 /* 1874 * FIXME figure out what is wrong with PSR+joiner and 1875 * fix it. Presumably something related to the fact that 1876 * PSR is a transcoder level feature. 1877 */ 1878 if (crtc_state->joiner_pipes) { 1879 drm_dbg_kms(display->drm, 1880 "PSR disabled due to joiner\n"); 1881 return; 1882 } 1883 1884 /* Only used for state verification. */ 1885 crtc_state->panel_replay_dsc_support = connector->dp.panel_replay_caps.dsc_support; 1886 crtc_state->has_panel_replay = _panel_replay_compute_config(crtc_state, conn_state); 1887 1888 crtc_state->has_psr = crtc_state->has_panel_replay ? true : 1889 _psr_compute_config(intel_dp, crtc_state, conn_state); 1890 1891 if (!crtc_state->has_psr) 1892 return; 1893 1894 crtc_state->has_sel_update = intel_sel_update_config_valid(crtc_state, conn_state); 1895 } 1896 1897 void intel_psr_get_config(struct intel_encoder *encoder, 1898 struct intel_crtc_state *pipe_config) 1899 { 1900 struct intel_display *display = to_intel_display(encoder); 1901 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 1902 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; 1903 struct intel_dp *intel_dp; 1904 u32 val; 1905 1906 if (!dig_port) 1907 return; 1908 1909 intel_dp = &dig_port->dp; 1910 if (!(CAN_PSR(intel_dp) || CAN_PANEL_REPLAY(intel_dp))) 1911 return; 1912 1913 mutex_lock(&intel_dp->psr.lock); 1914 if (!intel_dp->psr.enabled) 1915 goto unlock; 1916 1917 if (intel_dp->psr.panel_replay_enabled) { 1918 pipe_config->has_psr = pipe_config->has_panel_replay = true; 1919 } else { 1920 /* 1921 * Not possible to read EDP_PSR/PSR2_CTL registers as it is 1922 * enabled/disabled because of frontbuffer tracking and others. 1923 */ 1924 pipe_config->has_psr = true; 1925 } 1926 1927 pipe_config->has_sel_update = intel_dp->psr.sel_update_enabled; 1928 pipe_config->infoframes.enable |= intel_hdmi_infoframe_enable(DP_SDP_VSC); 1929 1930 if (!intel_dp->psr.sel_update_enabled) 1931 goto unlock; 1932 1933 if (HAS_PSR2_SEL_FETCH(display)) { 1934 val = intel_de_read(display, 1935 PSR2_MAN_TRK_CTL(display, cpu_transcoder)); 1936 if (val & PSR2_MAN_TRK_CTL_ENABLE) 1937 pipe_config->enable_psr2_sel_fetch = true; 1938 } 1939 1940 pipe_config->enable_psr2_su_region_et = intel_dp->psr.su_region_et_enabled; 1941 1942 if (DISPLAY_VER(display) >= 12) { 1943 val = intel_de_read(display, 1944 TRANS_EXITLINE(display, cpu_transcoder)); 1945 pipe_config->dc3co_exitline = REG_FIELD_GET(EXITLINE_MASK, val); 1946 } 1947 unlock: 1948 mutex_unlock(&intel_dp->psr.lock); 1949 } 1950 1951 static void intel_psr_activate(struct intel_dp *intel_dp) 1952 { 1953 struct intel_display *display = to_intel_display(intel_dp); 1954 enum transcoder cpu_transcoder = intel_dp->psr.transcoder; 1955 1956 drm_WARN_ON(display->drm, 1957 transcoder_has_psr2(display, cpu_transcoder) && 1958 intel_de_read(display, EDP_PSR2_CTL(display, cpu_transcoder)) & EDP_PSR2_ENABLE); 1959 1960 drm_WARN_ON(display->drm, 1961 intel_de_read(display, psr_ctl_reg(display, cpu_transcoder)) & EDP_PSR_ENABLE); 1962 1963 drm_WARN_ON(display->drm, intel_dp->psr.active); 1964 1965 drm_WARN_ON(display->drm, !intel_dp->psr.enabled); 1966 1967 lockdep_assert_held(&intel_dp->psr.lock); 1968 1969 /* psr1, psr2 and panel-replay are mutually exclusive.*/ 1970 if (intel_dp->psr.panel_replay_enabled) 1971 dg2_activate_panel_replay(intel_dp); 1972 else if (intel_dp->psr.sel_update_enabled) 1973 hsw_activate_psr2(intel_dp); 1974 else 1975 hsw_activate_psr1(intel_dp); 1976 1977 intel_dp->psr.active = true; 1978 intel_dp->psr.no_psr_reason = NULL; 1979 } 1980 1981 /* 1982 * Wa_16013835468 1983 * Wa_14015648006 1984 */ 1985 static void wm_optimization_wa(struct intel_dp *intel_dp, 1986 const struct intel_crtc_state *crtc_state) 1987 { 1988 struct intel_display *display = to_intel_display(intel_dp); 1989 enum pipe pipe = intel_dp->psr.pipe; 1990 bool activate = false; 1991 1992 /* Wa_14015648006 */ 1993 if (IS_DISPLAY_VER(display, 11, 14) && crtc_state->wm_level_disabled) 1994 activate = true; 1995 1996 /* Wa_16013835468 */ 1997 if (DISPLAY_VER(display) == 12 && 1998 crtc_state->hw.adjusted_mode.crtc_vblank_start != 1999 crtc_state->hw.adjusted_mode.crtc_vdisplay) 2000 activate = true; 2001 2002 if (activate) 2003 intel_de_rmw(display, GEN8_CHICKEN_DCPR_1, 2004 0, LATENCY_REPORTING_REMOVED(pipe)); 2005 else 2006 intel_de_rmw(display, GEN8_CHICKEN_DCPR_1, 2007 LATENCY_REPORTING_REMOVED(pipe), 0); 2008 } 2009 2010 static void intel_psr_enable_source(struct intel_dp *intel_dp, 2011 const struct intel_crtc_state *crtc_state) 2012 { 2013 struct intel_display *display = to_intel_display(intel_dp); 2014 enum transcoder cpu_transcoder = intel_dp->psr.transcoder; 2015 u32 mask = 0; 2016 2017 /* 2018 * Only HSW and BDW have PSR AUX registers that need to be setup. 2019 * SKL+ use hardcoded values PSR AUX transactions 2020 */ 2021 if (DISPLAY_VER(display) < 9) 2022 hsw_psr_setup_aux(intel_dp); 2023 2024 /* 2025 * Per Spec: Avoid continuous PSR exit by masking MEMUP and HPD also 2026 * mask LPSP to avoid dependency on other drivers that might block 2027 * runtime_pm besides preventing other hw tracking issues now we 2028 * can rely on frontbuffer tracking. 2029 * 2030 * From bspec prior LunarLake: 2031 * Only PSR_MASK[Mask FBC modify] and PSR_MASK[Mask Hotplug] are used in 2032 * panel replay mode. 2033 * 2034 * From bspec beyod LunarLake: 2035 * Panel Replay on DP: No bits are applicable 2036 * Panel Replay on eDP: All bits are applicable 2037 */ 2038 if (DISPLAY_VER(display) < 20 || intel_dp_is_edp(intel_dp)) 2039 mask = EDP_PSR_DEBUG_MASK_HPD; 2040 2041 if (intel_dp_is_edp(intel_dp)) { 2042 mask |= EDP_PSR_DEBUG_MASK_MEMUP; 2043 2044 /* 2045 * For some unknown reason on HSW non-ULT (or at least on 2046 * Dell Latitude E6540) external displays start to flicker 2047 * when PSR is enabled on the eDP. SR/PC6 residency is much 2048 * higher than should be possible with an external display. 2049 * As a workaround leave LPSP unmasked to prevent PSR entry 2050 * when external displays are active. 2051 */ 2052 if (DISPLAY_VER(display) >= 8 || display->platform.haswell_ult) 2053 mask |= EDP_PSR_DEBUG_MASK_LPSP; 2054 2055 if (DISPLAY_VER(display) < 20) 2056 mask |= EDP_PSR_DEBUG_MASK_MAX_SLEEP; 2057 2058 /* 2059 * No separate pipe reg write mask on hsw/bdw, so have to unmask all 2060 * registers in order to keep the CURSURFLIVE tricks working :( 2061 */ 2062 if (IS_DISPLAY_VER(display, 9, 10)) 2063 mask |= EDP_PSR_DEBUG_MASK_DISP_REG_WRITE; 2064 2065 /* allow PSR with sprite enabled */ 2066 if (display->platform.haswell) 2067 mask |= EDP_PSR_DEBUG_MASK_SPRITE_ENABLE; 2068 } 2069 2070 intel_de_write(display, psr_debug_reg(display, cpu_transcoder), mask); 2071 2072 psr_irq_control(intel_dp); 2073 2074 /* 2075 * TODO: if future platforms supports DC3CO in more than one 2076 * transcoder, EXITLINE will need to be unset when disabling PSR 2077 */ 2078 if (intel_dp->psr.dc3co_exitline) 2079 intel_de_rmw(display, 2080 TRANS_EXITLINE(display, cpu_transcoder), 2081 EXITLINE_MASK, 2082 intel_dp->psr.dc3co_exitline << EXITLINE_SHIFT | EXITLINE_ENABLE); 2083 2084 if (HAS_PSR_HW_TRACKING(display) && HAS_PSR2_SEL_FETCH(display)) 2085 intel_de_rmw(display, CHICKEN_PAR1_1, IGNORE_PSR2_HW_TRACKING, 2086 intel_dp->psr.psr2_sel_fetch_enabled ? 2087 IGNORE_PSR2_HW_TRACKING : 0); 2088 2089 /* 2090 * Wa_16013835468 2091 * Wa_14015648006 2092 */ 2093 wm_optimization_wa(intel_dp, crtc_state); 2094 2095 if (intel_dp->psr.sel_update_enabled) { 2096 if (DISPLAY_VER(display) == 9) 2097 intel_de_rmw(display, CHICKEN_TRANS(display, cpu_transcoder), 0, 2098 PSR2_VSC_ENABLE_PROG_HEADER | 2099 PSR2_ADD_VERTICAL_LINE_COUNT); 2100 2101 /* 2102 * Wa_16014451276:adlp,mtl[a0,b0] 2103 * All supported adlp panels have 1-based X granularity, this may 2104 * cause issues if non-supported panels are used. 2105 */ 2106 if (!intel_dp->psr.panel_replay_enabled && 2107 (IS_DISPLAY_VERx100_STEP(display, 1400, STEP_A0, STEP_B0) || 2108 display->platform.alderlake_p)) 2109 intel_de_rmw(display, CHICKEN_TRANS(display, cpu_transcoder), 2110 0, ADLP_1_BASED_X_GRANULARITY); 2111 2112 /* Wa_16012604467:adlp,mtl[a0,b0] */ 2113 if (!intel_dp->psr.panel_replay_enabled && 2114 IS_DISPLAY_VERx100_STEP(display, 1400, STEP_A0, STEP_B0)) 2115 intel_de_rmw(display, 2116 MTL_CLKGATE_DIS_TRANS(display, cpu_transcoder), 2117 0, 2118 MTL_CLKGATE_DIS_TRANS_DMASC_GATING_DIS); 2119 else if (display->platform.alderlake_p) 2120 intel_de_rmw(display, CLKGATE_DIS_MISC, 0, 2121 CLKGATE_DIS_MISC_DMASC_GATING_DIS); 2122 } 2123 2124 /* Wa_16025596647 */ 2125 if ((DISPLAY_VER(display) == 20 || 2126 IS_DISPLAY_VERx100_STEP(display, 3000, STEP_A0, STEP_B0)) && 2127 !intel_dp->psr.panel_replay_enabled) 2128 intel_dmc_block_pkgc(display, intel_dp->psr.pipe, true); 2129 2130 intel_alpm_configure(intel_dp, crtc_state); 2131 2132 if (HAS_PSR_TRANS_PUSH_FRAME_CHANGE(display)) 2133 intel_vrr_psr_frame_change_enable(crtc_state); 2134 } 2135 2136 static bool psr_interrupt_error_check(struct intel_dp *intel_dp) 2137 { 2138 struct intel_display *display = to_intel_display(intel_dp); 2139 enum transcoder cpu_transcoder = intel_dp->psr.transcoder; 2140 u32 val; 2141 2142 if (intel_dp->psr.panel_replay_enabled) 2143 goto no_err; 2144 2145 /* 2146 * If a PSR error happened and the driver is reloaded, the EDP_PSR_IIR 2147 * will still keep the error set even after the reset done in the 2148 * irq_preinstall and irq_uninstall hooks. 2149 * And enabling in this situation cause the screen to freeze in the 2150 * first time that PSR HW tries to activate so lets keep PSR disabled 2151 * to avoid any rendering problems. 2152 */ 2153 val = intel_de_read(display, psr_iir_reg(display, cpu_transcoder)); 2154 val &= psr_irq_psr_error_bit_get(intel_dp); 2155 if (val) { 2156 intel_dp->psr.sink_not_reliable = true; 2157 drm_dbg_kms(display->drm, 2158 "PSR interruption error set, not enabling PSR\n"); 2159 return false; 2160 } 2161 2162 no_err: 2163 return true; 2164 } 2165 2166 static void intel_psr_enable_locked(struct intel_dp *intel_dp, 2167 const struct intel_crtc_state *crtc_state) 2168 { 2169 struct intel_display *display = to_intel_display(intel_dp); 2170 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 2171 u32 val; 2172 2173 drm_WARN_ON(display->drm, intel_dp->psr.enabled); 2174 2175 intel_dp->psr.sel_update_enabled = crtc_state->has_sel_update; 2176 intel_dp->psr.panel_replay_enabled = crtc_state->has_panel_replay; 2177 intel_dp->psr.busy_frontbuffer_bits = 0; 2178 intel_dp->psr.pipe = to_intel_crtc(crtc_state->uapi.crtc)->pipe; 2179 intel_dp->psr.transcoder = crtc_state->cpu_transcoder; 2180 /* DC5/DC6 requires at least 6 idle frames */ 2181 val = usecs_to_jiffies(intel_get_frame_time_us(crtc_state) * 6); 2182 intel_dp->psr.dc3co_exit_delay = val; 2183 intel_dp->psr.dc3co_exitline = crtc_state->dc3co_exitline; 2184 intel_dp->psr.psr2_sel_fetch_enabled = crtc_state->enable_psr2_sel_fetch; 2185 intel_dp->psr.su_region_et_enabled = crtc_state->enable_psr2_su_region_et; 2186 intel_dp->psr.psr2_sel_fetch_cff_enabled = false; 2187 intel_dp->psr.req_psr2_sdp_prior_scanline = 2188 crtc_state->req_psr2_sdp_prior_scanline; 2189 intel_dp->psr.active_non_psr_pipes = crtc_state->active_non_psr_pipes; 2190 intel_dp->psr.pkg_c_latency_used = crtc_state->pkg_c_latency_used; 2191 intel_dp->psr.io_wake_lines = crtc_state->alpm_state.io_wake_lines; 2192 intel_dp->psr.fast_wake_lines = crtc_state->alpm_state.fast_wake_lines; 2193 2194 if (!psr_interrupt_error_check(intel_dp)) 2195 return; 2196 2197 if (intel_dp->psr.panel_replay_enabled) 2198 drm_dbg_kms(display->drm, "Enabling Panel Replay\n"); 2199 else 2200 drm_dbg_kms(display->drm, "Enabling PSR%s\n", 2201 intel_dp->psr.sel_update_enabled ? "2" : "1"); 2202 2203 /* 2204 * Enabling sink PSR/Panel Replay here only for PSR. Panel Replay enable 2205 * bit is already written at this point. Sink ALPM is enabled here for 2206 * PSR and Panel Replay. See 2207 * intel_psr_panel_replay_enable_sink. Modifiers/options: 2208 * - Selective Update 2209 * - Region Early Transport 2210 * - Selective Update Region Scanline Capture 2211 * - VSC_SDP_CRC 2212 * - HPD on different Errors 2213 * - CRC verification 2214 * are written for PSR and Panel Replay here. 2215 */ 2216 intel_psr_enable_sink(intel_dp, crtc_state); 2217 2218 if (intel_dp_is_edp(intel_dp)) 2219 intel_snps_phy_update_psr_power_state(&dig_port->base, true); 2220 2221 intel_psr_enable_source(intel_dp, crtc_state); 2222 intel_dp->psr.enabled = true; 2223 intel_dp->psr.pause_counter = 0; 2224 2225 /* 2226 * Link_ok is sticky and set here on PSR enable. We can assume link 2227 * training is complete as we never continue to PSR enable with 2228 * untrained link. Link_ok is kept as set until first short pulse 2229 * interrupt. This is targeted to workaround panels stating bad link 2230 * after PSR is enabled. 2231 */ 2232 intel_dp->psr.link_ok = true; 2233 2234 intel_psr_activate(intel_dp); 2235 } 2236 2237 static void intel_psr_exit(struct intel_dp *intel_dp) 2238 { 2239 struct intel_display *display = to_intel_display(intel_dp); 2240 enum transcoder cpu_transcoder = intel_dp->psr.transcoder; 2241 u32 val; 2242 2243 if (!intel_dp->psr.active) { 2244 if (transcoder_has_psr2(display, cpu_transcoder)) { 2245 val = intel_de_read(display, 2246 EDP_PSR2_CTL(display, cpu_transcoder)); 2247 drm_WARN_ON(display->drm, val & EDP_PSR2_ENABLE); 2248 } 2249 2250 val = intel_de_read(display, 2251 psr_ctl_reg(display, cpu_transcoder)); 2252 drm_WARN_ON(display->drm, val & EDP_PSR_ENABLE); 2253 2254 return; 2255 } 2256 2257 if (intel_dp->psr.panel_replay_enabled) { 2258 intel_de_rmw(display, TRANS_DP2_CTL(intel_dp->psr.transcoder), 2259 TRANS_DP2_PANEL_REPLAY_ENABLE, 0); 2260 } else if (intel_dp->psr.sel_update_enabled) { 2261 tgl_disallow_dc3co_on_psr2_exit(intel_dp); 2262 2263 val = intel_de_rmw(display, 2264 EDP_PSR2_CTL(display, cpu_transcoder), 2265 EDP_PSR2_ENABLE, 0); 2266 2267 drm_WARN_ON(display->drm, !(val & EDP_PSR2_ENABLE)); 2268 } else { 2269 if ((DISPLAY_VER(display) == 20 || 2270 IS_DISPLAY_VERx100_STEP(display, 3000, STEP_A0, STEP_B0)) && 2271 intel_dp->psr.pkg_c_latency_used) 2272 intel_dmc_start_pkgc_exit_at_start_of_undelayed_vblank(display, 2273 intel_dp->psr.pipe, 2274 false); 2275 2276 val = intel_de_rmw(display, 2277 psr_ctl_reg(display, cpu_transcoder), 2278 EDP_PSR_ENABLE, 0); 2279 2280 drm_WARN_ON(display->drm, !(val & EDP_PSR_ENABLE)); 2281 } 2282 intel_dp->psr.active = false; 2283 } 2284 2285 static void intel_psr_wait_exit_locked(struct intel_dp *intel_dp) 2286 { 2287 struct intel_display *display = to_intel_display(intel_dp); 2288 enum transcoder cpu_transcoder = intel_dp->psr.transcoder; 2289 i915_reg_t psr_status; 2290 u32 psr_status_mask; 2291 2292 if (intel_dp_is_edp(intel_dp) && (intel_dp->psr.sel_update_enabled || 2293 intel_dp->psr.panel_replay_enabled)) { 2294 psr_status = EDP_PSR2_STATUS(display, cpu_transcoder); 2295 psr_status_mask = EDP_PSR2_STATUS_STATE_MASK; 2296 } else { 2297 psr_status = psr_status_reg(display, cpu_transcoder); 2298 psr_status_mask = EDP_PSR_STATUS_STATE_MASK; 2299 } 2300 2301 /* Wait till PSR is idle */ 2302 if (intel_de_wait_for_clear_ms(display, psr_status, 2303 psr_status_mask, 2000)) 2304 drm_err(display->drm, "Timed out waiting PSR idle state\n"); 2305 } 2306 2307 static void intel_psr_disable_locked(struct intel_dp *intel_dp) 2308 { 2309 struct intel_display *display = to_intel_display(intel_dp); 2310 enum transcoder cpu_transcoder = intel_dp->psr.transcoder; 2311 2312 lockdep_assert_held(&intel_dp->psr.lock); 2313 2314 if (!intel_dp->psr.enabled) 2315 return; 2316 2317 if (intel_dp->psr.panel_replay_enabled) 2318 drm_dbg_kms(display->drm, "Disabling Panel Replay\n"); 2319 else 2320 drm_dbg_kms(display->drm, "Disabling PSR%s\n", 2321 intel_dp->psr.sel_update_enabled ? "2" : "1"); 2322 2323 intel_psr_exit(intel_dp); 2324 intel_psr_wait_exit_locked(intel_dp); 2325 2326 /* 2327 * Wa_16013835468 2328 * Wa_14015648006 2329 */ 2330 if (DISPLAY_VER(display) >= 11) 2331 intel_de_rmw(display, GEN8_CHICKEN_DCPR_1, 2332 LATENCY_REPORTING_REMOVED(intel_dp->psr.pipe), 0); 2333 2334 if (intel_dp->psr.sel_update_enabled) { 2335 /* Wa_16012604467:adlp,mtl[a0,b0] */ 2336 if (!intel_dp->psr.panel_replay_enabled && 2337 IS_DISPLAY_VERx100_STEP(display, 1400, STEP_A0, STEP_B0)) 2338 intel_de_rmw(display, 2339 MTL_CLKGATE_DIS_TRANS(display, cpu_transcoder), 2340 MTL_CLKGATE_DIS_TRANS_DMASC_GATING_DIS, 0); 2341 else if (display->platform.alderlake_p) 2342 intel_de_rmw(display, CLKGATE_DIS_MISC, 2343 CLKGATE_DIS_MISC_DMASC_GATING_DIS, 0); 2344 } 2345 2346 if (intel_dp_is_edp(intel_dp)) 2347 intel_snps_phy_update_psr_power_state(&dp_to_dig_port(intel_dp)->base, false); 2348 2349 if (intel_dp->psr.panel_replay_enabled && intel_dp_is_edp(intel_dp)) 2350 intel_alpm_disable(intel_dp); 2351 2352 /* Disable PSR on Sink */ 2353 if (!intel_dp->psr.panel_replay_enabled) { 2354 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, 0); 2355 2356 if (intel_dp->psr.sel_update_enabled) 2357 drm_dp_dpcd_writeb(&intel_dp->aux, 2358 DP_RECEIVER_ALPM_CONFIG, 0); 2359 } 2360 2361 /* Wa_16025596647 */ 2362 if ((DISPLAY_VER(display) == 20 || 2363 IS_DISPLAY_VERx100_STEP(display, 3000, STEP_A0, STEP_B0)) && 2364 !intel_dp->psr.panel_replay_enabled) 2365 intel_dmc_block_pkgc(display, intel_dp->psr.pipe, false); 2366 2367 intel_dp->psr.enabled = false; 2368 intel_dp->psr.panel_replay_enabled = false; 2369 intel_dp->psr.sel_update_enabled = false; 2370 intel_dp->psr.psr2_sel_fetch_enabled = false; 2371 intel_dp->psr.su_region_et_enabled = false; 2372 intel_dp->psr.psr2_sel_fetch_cff_enabled = false; 2373 intel_dp->psr.active_non_psr_pipes = 0; 2374 intel_dp->psr.pkg_c_latency_used = 0; 2375 } 2376 2377 /** 2378 * intel_psr_disable - Disable PSR 2379 * @intel_dp: Intel DP 2380 * @old_crtc_state: old CRTC state 2381 * 2382 * This function needs to be called before disabling pipe. 2383 */ 2384 void intel_psr_disable(struct intel_dp *intel_dp, 2385 const struct intel_crtc_state *old_crtc_state) 2386 { 2387 struct intel_display *display = to_intel_display(intel_dp); 2388 2389 if (!old_crtc_state->has_psr) 2390 return; 2391 2392 if (drm_WARN_ON(display->drm, !CAN_PSR(intel_dp) && 2393 !CAN_PANEL_REPLAY(intel_dp))) 2394 return; 2395 2396 mutex_lock(&intel_dp->psr.lock); 2397 2398 intel_psr_disable_locked(intel_dp); 2399 2400 intel_dp->psr.link_ok = false; 2401 2402 mutex_unlock(&intel_dp->psr.lock); 2403 cancel_work_sync(&intel_dp->psr.work); 2404 cancel_delayed_work_sync(&intel_dp->psr.dc3co_work); 2405 } 2406 2407 /** 2408 * intel_psr_pause - Pause PSR 2409 * @intel_dp: Intel DP 2410 * 2411 * This function need to be called after enabling psr. 2412 */ 2413 void intel_psr_pause(struct intel_dp *intel_dp) 2414 { 2415 struct intel_psr *psr = &intel_dp->psr; 2416 2417 if (!CAN_PSR(intel_dp) && !CAN_PANEL_REPLAY(intel_dp)) 2418 return; 2419 2420 mutex_lock(&psr->lock); 2421 2422 if (!psr->enabled) { 2423 mutex_unlock(&psr->lock); 2424 return; 2425 } 2426 2427 if (intel_dp->psr.pause_counter++ == 0) { 2428 intel_psr_exit(intel_dp); 2429 intel_psr_wait_exit_locked(intel_dp); 2430 } 2431 2432 mutex_unlock(&psr->lock); 2433 2434 cancel_work_sync(&psr->work); 2435 cancel_delayed_work_sync(&psr->dc3co_work); 2436 } 2437 2438 /** 2439 * intel_psr_resume - Resume PSR 2440 * @intel_dp: Intel DP 2441 * 2442 * This function need to be called after pausing psr. 2443 */ 2444 void intel_psr_resume(struct intel_dp *intel_dp) 2445 { 2446 struct intel_display *display = to_intel_display(intel_dp); 2447 struct intel_psr *psr = &intel_dp->psr; 2448 2449 if (!CAN_PSR(intel_dp) && !CAN_PANEL_REPLAY(intel_dp)) 2450 return; 2451 2452 mutex_lock(&psr->lock); 2453 2454 if (!psr->enabled) 2455 goto out; 2456 2457 if (!psr->pause_counter) { 2458 drm_warn(display->drm, "Unbalanced PSR pause/resume!\n"); 2459 goto out; 2460 } 2461 2462 if (--intel_dp->psr.pause_counter == 0) 2463 intel_psr_activate(intel_dp); 2464 2465 out: 2466 mutex_unlock(&psr->lock); 2467 } 2468 2469 /** 2470 * intel_psr_needs_vblank_notification - Check if PSR need vblank enable/disable 2471 * notification. 2472 * @crtc_state: CRTC status 2473 * 2474 * We need to block DC6 entry in case of Panel Replay as enabling VBI doesn't 2475 * prevent it in case of Panel Replay. Panel Replay switches main link off on 2476 * DC entry. This means vblank interrupts are not fired and is a problem if 2477 * user-space is polling for vblank events. Also Wa_16025596647 needs 2478 * information when vblank is enabled/disabled. 2479 */ 2480 bool intel_psr_needs_vblank_notification(const struct intel_crtc_state *crtc_state) 2481 { 2482 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2483 struct intel_display *display = to_intel_display(crtc_state); 2484 struct intel_encoder *encoder; 2485 2486 for_each_encoder_on_crtc(crtc->base.dev, &crtc->base, encoder) { 2487 struct intel_dp *intel_dp; 2488 2489 if (!intel_encoder_is_dp(encoder)) 2490 continue; 2491 2492 intel_dp = enc_to_intel_dp(encoder); 2493 2494 if (!intel_dp_is_edp(intel_dp)) 2495 continue; 2496 2497 if (CAN_PANEL_REPLAY(intel_dp)) 2498 return true; 2499 2500 if ((DISPLAY_VER(display) == 20 || 2501 IS_DISPLAY_VERx100_STEP(display, 3000, STEP_A0, STEP_B0)) && 2502 CAN_PSR(intel_dp)) 2503 return true; 2504 } 2505 2506 return false; 2507 } 2508 2509 /** 2510 * intel_psr_trigger_frame_change_event - Trigger "Frame Change" event 2511 * @dsb: DSB context 2512 * @state: the atomic state 2513 * @crtc: the CRTC 2514 * 2515 * Generate PSR "Frame Change" event. 2516 */ 2517 void intel_psr_trigger_frame_change_event(struct intel_dsb *dsb, 2518 struct intel_atomic_state *state, 2519 struct intel_crtc *crtc) 2520 { 2521 const struct intel_crtc_state *crtc_state = 2522 intel_pre_commit_crtc_state(state, crtc); 2523 struct intel_display *display = to_intel_display(crtc); 2524 2525 if (!crtc_state->has_psr || intel_psr_use_trans_push(crtc_state)) 2526 return; 2527 2528 intel_de_write_dsb(display, dsb, 2529 CURSURFLIVE(display, crtc->pipe), 0); 2530 } 2531 2532 /** 2533 * intel_psr_min_set_context_latency - Minimum 'set context latency' lines needed by PSR 2534 * @crtc_state: the crtc state 2535 * 2536 * Return minimum SCL lines/delay needed by PSR. 2537 */ 2538 int intel_psr_min_set_context_latency(const struct intel_crtc_state *crtc_state) 2539 { 2540 2541 return _intel_psr_min_set_context_latency(crtc_state, 2542 crtc_state->has_panel_replay, 2543 crtc_state->has_sel_update); 2544 } 2545 2546 static u32 man_trk_ctl_enable_bit_get(struct intel_display *display) 2547 { 2548 return display->platform.alderlake_p || DISPLAY_VER(display) >= 14 ? 0 : 2549 PSR2_MAN_TRK_CTL_ENABLE; 2550 } 2551 2552 static u32 man_trk_ctl_single_full_frame_bit_get(struct intel_display *display) 2553 { 2554 return display->platform.alderlake_p || DISPLAY_VER(display) >= 14 ? 2555 ADLP_PSR2_MAN_TRK_CTL_SF_SINGLE_FULL_FRAME : 2556 PSR2_MAN_TRK_CTL_SF_SINGLE_FULL_FRAME; 2557 } 2558 2559 static u32 man_trk_ctl_partial_frame_bit_get(struct intel_display *display) 2560 { 2561 return display->platform.alderlake_p || DISPLAY_VER(display) >= 14 ? 2562 ADLP_PSR2_MAN_TRK_CTL_SF_PARTIAL_FRAME_UPDATE : 2563 PSR2_MAN_TRK_CTL_SF_PARTIAL_FRAME_UPDATE; 2564 } 2565 2566 static u32 man_trk_ctl_continuos_full_frame(struct intel_display *display) 2567 { 2568 return display->platform.alderlake_p || DISPLAY_VER(display) >= 14 ? 2569 ADLP_PSR2_MAN_TRK_CTL_SF_CONTINUOS_FULL_FRAME : 2570 PSR2_MAN_TRK_CTL_SF_CONTINUOS_FULL_FRAME; 2571 } 2572 2573 static void intel_psr_force_update(struct intel_dp *intel_dp) 2574 { 2575 struct intel_display *display = to_intel_display(intel_dp); 2576 2577 /* 2578 * Display WA #0884: skl+ 2579 * This documented WA for bxt can be safely applied 2580 * broadly so we can force HW tracking to exit PSR 2581 * instead of disabling and re-enabling. 2582 * Workaround tells us to write 0 to CUR_SURFLIVE_A, 2583 * but it makes more sense write to the current active 2584 * pipe. 2585 * 2586 * This workaround do not exist for platforms with display 10 or newer 2587 * but testing proved that it works for up display 13, for newer 2588 * than that testing will be needed. 2589 */ 2590 intel_de_write(display, CURSURFLIVE(display, intel_dp->psr.pipe), 0); 2591 } 2592 2593 void intel_psr2_program_trans_man_trk_ctl(struct intel_dsb *dsb, 2594 const struct intel_crtc_state *crtc_state) 2595 { 2596 struct intel_display *display = to_intel_display(crtc_state); 2597 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2598 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 2599 struct intel_encoder *encoder; 2600 2601 if (!crtc_state->enable_psr2_sel_fetch) 2602 return; 2603 2604 for_each_intel_encoder_mask_with_psr(display->drm, encoder, 2605 crtc_state->uapi.encoder_mask) { 2606 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2607 2608 if (!dsb) 2609 lockdep_assert_held(&intel_dp->psr.lock); 2610 2611 if (DISPLAY_VER(display) < 20 && intel_dp->psr.psr2_sel_fetch_cff_enabled) 2612 return; 2613 break; 2614 } 2615 2616 intel_de_write_dsb(display, dsb, 2617 PSR2_MAN_TRK_CTL(display, cpu_transcoder), 2618 crtc_state->psr2_man_track_ctl); 2619 2620 if (!crtc_state->enable_psr2_su_region_et) 2621 return; 2622 2623 intel_de_write_dsb(display, dsb, PIPE_SRCSZ_ERLY_TPT(crtc->pipe), 2624 crtc_state->pipe_srcsz_early_tpt); 2625 2626 if (!crtc_state->dsc.compression_enable) 2627 return; 2628 2629 intel_dsc_su_et_parameters_configure(dsb, encoder, crtc_state, 2630 drm_rect_height(&crtc_state->psr2_su_area)); 2631 } 2632 2633 static void psr2_man_trk_ctl_calc(struct intel_crtc_state *crtc_state, 2634 bool full_update) 2635 { 2636 struct intel_display *display = to_intel_display(crtc_state); 2637 u32 val = man_trk_ctl_enable_bit_get(display); 2638 2639 /* SF partial frame enable has to be set even on full update */ 2640 val |= man_trk_ctl_partial_frame_bit_get(display); 2641 2642 if (full_update) { 2643 val |= man_trk_ctl_continuos_full_frame(display); 2644 goto exit; 2645 } 2646 2647 if (crtc_state->psr2_su_area.y1 == -1) 2648 goto exit; 2649 2650 if (display->platform.alderlake_p || DISPLAY_VER(display) >= 14) { 2651 val |= ADLP_PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR(crtc_state->psr2_su_area.y1); 2652 val |= ADLP_PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR(crtc_state->psr2_su_area.y2 - 1); 2653 } else { 2654 drm_WARN_ON(crtc_state->uapi.crtc->dev, 2655 crtc_state->psr2_su_area.y1 % 4 || 2656 crtc_state->psr2_su_area.y2 % 4); 2657 2658 val |= PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR( 2659 crtc_state->psr2_su_area.y1 / 4 + 1); 2660 val |= PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR( 2661 crtc_state->psr2_su_area.y2 / 4 + 1); 2662 } 2663 exit: 2664 crtc_state->psr2_man_track_ctl = val; 2665 } 2666 2667 static u32 psr2_pipe_srcsz_early_tpt_calc(struct intel_crtc_state *crtc_state, 2668 bool full_update) 2669 { 2670 int width, height; 2671 2672 if (!crtc_state->enable_psr2_su_region_et || full_update) 2673 return 0; 2674 2675 width = drm_rect_width(&crtc_state->psr2_su_area); 2676 height = drm_rect_height(&crtc_state->psr2_su_area); 2677 2678 return PIPESRC_WIDTH(width - 1) | PIPESRC_HEIGHT(height - 1); 2679 } 2680 2681 static void clip_area_update(struct drm_rect *overlap_damage_area, 2682 struct drm_rect *damage_area, 2683 struct drm_rect *pipe_src) 2684 { 2685 if (!drm_rect_intersect(damage_area, pipe_src)) 2686 return; 2687 2688 if (overlap_damage_area->y1 == -1) { 2689 overlap_damage_area->y1 = damage_area->y1; 2690 overlap_damage_area->y2 = damage_area->y2; 2691 return; 2692 } 2693 2694 if (damage_area->y1 < overlap_damage_area->y1) 2695 overlap_damage_area->y1 = damage_area->y1; 2696 2697 if (damage_area->y2 > overlap_damage_area->y2) 2698 overlap_damage_area->y2 = damage_area->y2; 2699 } 2700 2701 static bool intel_psr2_sel_fetch_pipe_alignment(struct intel_crtc_state *crtc_state) 2702 { 2703 struct intel_display *display = to_intel_display(crtc_state); 2704 const struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config; 2705 u16 y_alignment; 2706 bool su_area_changed = false; 2707 2708 /* ADLP aligns the SU region to vdsc slice height in case dsc is enabled */ 2709 if (crtc_state->dsc.compression_enable && 2710 (display->platform.alderlake_p || DISPLAY_VER(display) >= 14)) 2711 y_alignment = vdsc_cfg->slice_height; 2712 else 2713 y_alignment = crtc_state->su_y_granularity; 2714 2715 if (crtc_state->psr2_su_area.y1 % y_alignment) { 2716 crtc_state->psr2_su_area.y1 -= crtc_state->psr2_su_area.y1 % y_alignment; 2717 su_area_changed = true; 2718 } 2719 2720 if (crtc_state->psr2_su_area.y2 % y_alignment) { 2721 crtc_state->psr2_su_area.y2 = ((crtc_state->psr2_su_area.y2 / 2722 y_alignment) + 1) * y_alignment; 2723 su_area_changed = true; 2724 } 2725 2726 return su_area_changed; 2727 } 2728 2729 /* 2730 * When early transport is in use we need to extend SU area to cover 2731 * cursor fully when cursor is in SU area. 2732 */ 2733 static void 2734 intel_psr2_sel_fetch_et_alignment(struct intel_atomic_state *state, 2735 struct intel_crtc *crtc, 2736 bool *cursor_in_su_area) 2737 { 2738 struct intel_crtc_state *crtc_state = intel_atomic_get_new_crtc_state(state, crtc); 2739 struct intel_plane_state *new_plane_state; 2740 struct intel_plane *plane; 2741 int i; 2742 2743 if (!crtc_state->enable_psr2_su_region_et) 2744 return; 2745 2746 for_each_new_intel_plane_in_state(state, plane, new_plane_state, i) { 2747 struct drm_rect inter; 2748 2749 if (new_plane_state->hw.crtc != crtc_state->uapi.crtc) 2750 continue; 2751 2752 if (plane->id != PLANE_CURSOR) 2753 continue; 2754 2755 if (!new_plane_state->uapi.visible) 2756 continue; 2757 2758 inter = crtc_state->psr2_su_area; 2759 if (!drm_rect_intersect(&inter, &new_plane_state->uapi.dst)) 2760 continue; 2761 2762 clip_area_update(&crtc_state->psr2_su_area, &new_plane_state->uapi.dst, 2763 &crtc_state->pipe_src); 2764 *cursor_in_su_area = true; 2765 } 2766 } 2767 2768 /* 2769 * TODO: Not clear how to handle planes with negative position, 2770 * also planes are not updated if they have a negative X 2771 * position so for now doing a full update in this cases 2772 * 2773 * Plane scaling and rotation is not supported by selective fetch and both 2774 * properties can change without a modeset, so need to be check at every 2775 * atomic commit. 2776 */ 2777 static bool psr2_sel_fetch_plane_state_supported(const struct intel_plane_state *plane_state) 2778 { 2779 if (plane_state->uapi.dst.y1 < 0 || 2780 plane_state->uapi.dst.x1 < 0 || 2781 plane_state->scaler_id >= 0 || 2782 plane_state->hw.rotation != DRM_MODE_ROTATE_0) 2783 return false; 2784 2785 return true; 2786 } 2787 2788 /* 2789 * Check for pipe properties that is not supported by selective fetch. 2790 * 2791 * TODO: pipe scaling causes a modeset but skl_update_scaler_crtc() is executed 2792 * after intel_psr_compute_config(), so for now keeping PSR2 selective fetch 2793 * enabled and going to the full update path. 2794 */ 2795 static bool psr2_sel_fetch_pipe_state_supported(const struct intel_crtc_state *crtc_state) 2796 { 2797 if (crtc_state->scaler_state.scaler_id >= 0 || 2798 crtc_state->async_flip_planes) 2799 return false; 2800 2801 return true; 2802 } 2803 2804 /* Wa 14019834836 */ 2805 static void intel_psr_apply_pr_link_on_su_wa(struct intel_crtc_state *crtc_state) 2806 { 2807 struct intel_display *display = to_intel_display(crtc_state); 2808 struct intel_encoder *encoder; 2809 int hactive_limit; 2810 2811 if (crtc_state->psr2_su_area.y1 != 0 || 2812 crtc_state->psr2_su_area.y2 != 0) 2813 return; 2814 2815 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) 2816 hactive_limit = intel_dp_is_uhbr(crtc_state) ? 1230 : 546; 2817 else 2818 hactive_limit = intel_dp_is_uhbr(crtc_state) ? 615 : 273; 2819 2820 if (crtc_state->hw.adjusted_mode.hdisplay < hactive_limit) 2821 return; 2822 2823 for_each_intel_encoder_mask_with_psr(display->drm, encoder, 2824 crtc_state->uapi.encoder_mask) { 2825 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2826 2827 if (!intel_dp_is_edp(intel_dp) && 2828 intel_dp->psr.panel_replay_enabled && 2829 intel_dp->psr.sel_update_enabled) { 2830 crtc_state->psr2_su_area.y2++; 2831 return; 2832 } 2833 } 2834 } 2835 2836 static void 2837 intel_psr_apply_su_area_workarounds(struct intel_crtc_state *crtc_state) 2838 { 2839 struct intel_display *display = to_intel_display(crtc_state); 2840 2841 /* Wa_14014971492 */ 2842 if (!crtc_state->has_panel_replay && 2843 ((IS_DISPLAY_VERx100_STEP(display, 1400, STEP_A0, STEP_B0) || 2844 display->platform.alderlake_p || display->platform.tigerlake)) && 2845 crtc_state->splitter.enable) 2846 crtc_state->psr2_su_area.y1 = 0; 2847 2848 /* Wa 14019834836 */ 2849 if (DISPLAY_VER(display) == 30) 2850 intel_psr_apply_pr_link_on_su_wa(crtc_state); 2851 } 2852 2853 int intel_psr2_sel_fetch_update(struct intel_atomic_state *state, 2854 struct intel_crtc *crtc) 2855 { 2856 struct intel_display *display = to_intel_display(state); 2857 struct intel_crtc_state *crtc_state = intel_atomic_get_new_crtc_state(state, crtc); 2858 struct intel_plane_state *new_plane_state, *old_plane_state; 2859 struct intel_plane *plane; 2860 bool full_update = false, su_area_changed; 2861 int i, ret; 2862 2863 if (!crtc_state->enable_psr2_sel_fetch) 2864 return 0; 2865 2866 if (!psr2_sel_fetch_pipe_state_supported(crtc_state)) { 2867 full_update = true; 2868 goto skip_sel_fetch_set_loop; 2869 } 2870 2871 crtc_state->psr2_su_area.x1 = 0; 2872 crtc_state->psr2_su_area.y1 = -1; 2873 crtc_state->psr2_su_area.x2 = drm_rect_width(&crtc_state->pipe_src); 2874 crtc_state->psr2_su_area.y2 = -1; 2875 2876 /* 2877 * Calculate minimal selective fetch area of each plane and calculate 2878 * the pipe damaged area. 2879 * In the next loop the plane selective fetch area will actually be set 2880 * using whole pipe damaged area. 2881 */ 2882 for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state, 2883 new_plane_state, i) { 2884 struct drm_rect src, damaged_area = { .x1 = 0, .y1 = -1, 2885 .x2 = INT_MAX }; 2886 2887 if (new_plane_state->hw.crtc != crtc_state->uapi.crtc) 2888 continue; 2889 2890 if (!new_plane_state->uapi.visible && 2891 !old_plane_state->uapi.visible) 2892 continue; 2893 2894 if (!psr2_sel_fetch_plane_state_supported(new_plane_state)) { 2895 full_update = true; 2896 break; 2897 } 2898 2899 /* 2900 * If visibility or plane moved, mark the whole plane area as 2901 * damaged as it needs to be complete redraw in the new and old 2902 * position. 2903 */ 2904 if (new_plane_state->uapi.visible != old_plane_state->uapi.visible || 2905 !drm_rect_equals(&new_plane_state->uapi.dst, 2906 &old_plane_state->uapi.dst)) { 2907 if (old_plane_state->uapi.visible) { 2908 damaged_area.y1 = old_plane_state->uapi.dst.y1; 2909 damaged_area.y2 = old_plane_state->uapi.dst.y2; 2910 clip_area_update(&crtc_state->psr2_su_area, &damaged_area, 2911 &crtc_state->pipe_src); 2912 } 2913 2914 if (new_plane_state->uapi.visible) { 2915 damaged_area.y1 = new_plane_state->uapi.dst.y1; 2916 damaged_area.y2 = new_plane_state->uapi.dst.y2; 2917 clip_area_update(&crtc_state->psr2_su_area, &damaged_area, 2918 &crtc_state->pipe_src); 2919 } 2920 continue; 2921 } else if (new_plane_state->uapi.alpha != old_plane_state->uapi.alpha) { 2922 /* If alpha changed mark the whole plane area as damaged */ 2923 damaged_area.y1 = new_plane_state->uapi.dst.y1; 2924 damaged_area.y2 = new_plane_state->uapi.dst.y2; 2925 clip_area_update(&crtc_state->psr2_su_area, &damaged_area, 2926 &crtc_state->pipe_src); 2927 continue; 2928 } 2929 2930 src = drm_plane_state_src(&new_plane_state->uapi); 2931 drm_rect_fp_to_int(&src, &src); 2932 2933 if (!drm_atomic_helper_damage_merged(&old_plane_state->uapi, 2934 &new_plane_state->uapi, &damaged_area)) 2935 continue; 2936 2937 damaged_area.y1 += new_plane_state->uapi.dst.y1 - src.y1; 2938 damaged_area.y2 += new_plane_state->uapi.dst.y1 - src.y1; 2939 damaged_area.x1 += new_plane_state->uapi.dst.x1 - src.x1; 2940 damaged_area.x2 += new_plane_state->uapi.dst.x1 - src.x1; 2941 2942 clip_area_update(&crtc_state->psr2_su_area, &damaged_area, &crtc_state->pipe_src); 2943 } 2944 2945 /* 2946 * TODO: For now we are just using full update in case 2947 * selective fetch area calculation fails. To optimize this we 2948 * should identify cases where this happens and fix the area 2949 * calculation for those. 2950 */ 2951 if (crtc_state->psr2_su_area.y1 == -1) { 2952 drm_info_once(display->drm, 2953 "Selective fetch area calculation failed in pipe %c\n", 2954 pipe_name(crtc->pipe)); 2955 full_update = true; 2956 } 2957 2958 if (full_update) 2959 goto skip_sel_fetch_set_loop; 2960 2961 intel_psr_apply_su_area_workarounds(crtc_state); 2962 2963 ret = drm_atomic_add_affected_planes(&state->base, &crtc->base); 2964 if (ret) 2965 return ret; 2966 2967 do { 2968 bool cursor_in_su_area; 2969 2970 /* 2971 * Adjust su area to cover cursor fully as necessary 2972 * (early transport). This needs to be done after 2973 * drm_atomic_add_affected_planes to ensure visible 2974 * cursor is added into affected planes even when 2975 * cursor is not updated by itself. 2976 */ 2977 intel_psr2_sel_fetch_et_alignment(state, crtc, &cursor_in_su_area); 2978 2979 su_area_changed = intel_psr2_sel_fetch_pipe_alignment(crtc_state); 2980 2981 /* 2982 * If the cursor was outside the SU area before 2983 * alignment, the alignment step (which only expands 2984 * SU) may pull the cursor partially inside, so we 2985 * must run ET alignment again to fully cover it. But 2986 * if the cursor was already fully inside before 2987 * alignment, expanding the SU area won't change that, 2988 * so no further work is needed. 2989 */ 2990 if (cursor_in_su_area) 2991 break; 2992 } while (su_area_changed); 2993 2994 /* 2995 * Now that we have the pipe damaged area check if it intersect with 2996 * every plane, if it does set the plane selective fetch area. 2997 */ 2998 for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state, 2999 new_plane_state, i) { 3000 struct drm_rect *sel_fetch_area, inter; 3001 struct intel_plane *linked = new_plane_state->planar_linked_plane; 3002 3003 if (new_plane_state->hw.crtc != crtc_state->uapi.crtc || 3004 !new_plane_state->uapi.visible) 3005 continue; 3006 3007 inter = crtc_state->psr2_su_area; 3008 sel_fetch_area = &new_plane_state->psr2_sel_fetch_area; 3009 if (!drm_rect_intersect(&inter, &new_plane_state->uapi.dst)) { 3010 sel_fetch_area->y1 = -1; 3011 sel_fetch_area->y2 = -1; 3012 /* 3013 * if plane sel fetch was previously enabled -> 3014 * disable it 3015 */ 3016 if (drm_rect_height(&old_plane_state->psr2_sel_fetch_area) > 0) 3017 crtc_state->update_planes |= BIT(plane->id); 3018 3019 continue; 3020 } 3021 3022 if (!psr2_sel_fetch_plane_state_supported(new_plane_state)) { 3023 full_update = true; 3024 break; 3025 } 3026 3027 sel_fetch_area = &new_plane_state->psr2_sel_fetch_area; 3028 sel_fetch_area->y1 = inter.y1 - new_plane_state->uapi.dst.y1; 3029 sel_fetch_area->y2 = inter.y2 - new_plane_state->uapi.dst.y1; 3030 crtc_state->update_planes |= BIT(plane->id); 3031 3032 /* 3033 * Sel_fetch_area is calculated for UV plane. Use 3034 * same area for Y plane as well. 3035 */ 3036 if (linked) { 3037 struct intel_plane_state *linked_new_plane_state; 3038 struct drm_rect *linked_sel_fetch_area; 3039 3040 linked_new_plane_state = intel_atomic_get_plane_state(state, linked); 3041 if (IS_ERR(linked_new_plane_state)) 3042 return PTR_ERR(linked_new_plane_state); 3043 3044 linked_sel_fetch_area = &linked_new_plane_state->psr2_sel_fetch_area; 3045 linked_sel_fetch_area->y1 = sel_fetch_area->y1; 3046 linked_sel_fetch_area->y2 = sel_fetch_area->y2; 3047 crtc_state->update_planes |= BIT(linked->id); 3048 } 3049 } 3050 3051 skip_sel_fetch_set_loop: 3052 if (full_update) 3053 clip_area_update(&crtc_state->psr2_su_area, &crtc_state->pipe_src, 3054 &crtc_state->pipe_src); 3055 3056 psr2_man_trk_ctl_calc(crtc_state, full_update); 3057 crtc_state->pipe_srcsz_early_tpt = 3058 psr2_pipe_srcsz_early_tpt_calc(crtc_state, full_update); 3059 return 0; 3060 } 3061 3062 void intel_psr2_panic_force_full_update(const struct intel_crtc_state *crtc_state) 3063 { 3064 struct intel_display *display = to_intel_display(crtc_state); 3065 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 3066 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 3067 u32 val = man_trk_ctl_enable_bit_get(display); 3068 3069 /* SF partial frame enable has to be set even on full update */ 3070 val |= man_trk_ctl_partial_frame_bit_get(display); 3071 val |= man_trk_ctl_continuos_full_frame(display); 3072 3073 /* Directly write the register */ 3074 intel_de_write_fw(display, PSR2_MAN_TRK_CTL(display, cpu_transcoder), val); 3075 3076 if (!crtc_state->enable_psr2_su_region_et) 3077 return; 3078 3079 intel_de_write_fw(display, PIPE_SRCSZ_ERLY_TPT(crtc->pipe), 0); 3080 } 3081 3082 void intel_psr_pre_plane_update(struct intel_atomic_state *state, 3083 struct intel_crtc *crtc) 3084 { 3085 struct intel_display *display = to_intel_display(state); 3086 const struct intel_crtc_state *old_crtc_state = 3087 intel_atomic_get_old_crtc_state(state, crtc); 3088 const struct intel_crtc_state *new_crtc_state = 3089 intel_atomic_get_new_crtc_state(state, crtc); 3090 struct intel_encoder *encoder; 3091 3092 if (!HAS_PSR(display)) 3093 return; 3094 3095 for_each_intel_encoder_mask_with_psr(state->base.dev, encoder, 3096 old_crtc_state->uapi.encoder_mask) { 3097 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 3098 struct intel_psr *psr = &intel_dp->psr; 3099 3100 mutex_lock(&psr->lock); 3101 3102 if (!new_crtc_state->has_psr) 3103 psr->no_psr_reason = new_crtc_state->no_psr_reason; 3104 3105 if (psr->enabled) { 3106 /* 3107 * Reasons to disable: 3108 * - PSR disabled in new state 3109 * - All planes will go inactive 3110 * - Changing between PSR versions 3111 * - Region Early Transport changing 3112 * - Display WA #1136: skl, bxt 3113 */ 3114 if (intel_crtc_needs_modeset(new_crtc_state) || 3115 !new_crtc_state->has_psr || 3116 !new_crtc_state->active_planes || 3117 new_crtc_state->has_sel_update != psr->sel_update_enabled || 3118 new_crtc_state->enable_psr2_su_region_et != psr->su_region_et_enabled || 3119 new_crtc_state->has_panel_replay != psr->panel_replay_enabled || 3120 (DISPLAY_VER(display) < 11 && new_crtc_state->wm_level_disabled)) 3121 intel_psr_disable_locked(intel_dp); 3122 else if (new_crtc_state->wm_level_disabled) 3123 /* Wa_14015648006 */ 3124 wm_optimization_wa(intel_dp, new_crtc_state); 3125 } 3126 3127 mutex_unlock(&psr->lock); 3128 } 3129 } 3130 3131 static void 3132 verify_panel_replay_dsc_state(const struct intel_crtc_state *crtc_state) 3133 { 3134 struct intel_display *display = to_intel_display(crtc_state); 3135 3136 if (!crtc_state->has_panel_replay) 3137 return; 3138 3139 drm_WARN_ON(display->drm, 3140 intel_dsc_enabled_on_link(crtc_state) && 3141 crtc_state->panel_replay_dsc_support == 3142 INTEL_DP_PANEL_REPLAY_DSC_NOT_SUPPORTED); 3143 } 3144 3145 void intel_psr_post_plane_update(struct intel_atomic_state *state, 3146 struct intel_crtc *crtc) 3147 { 3148 struct intel_display *display = to_intel_display(state); 3149 const struct intel_crtc_state *crtc_state = 3150 intel_atomic_get_new_crtc_state(state, crtc); 3151 struct intel_encoder *encoder; 3152 3153 if (!crtc_state->has_psr) 3154 return; 3155 3156 verify_panel_replay_dsc_state(crtc_state); 3157 3158 for_each_intel_encoder_mask_with_psr(state->base.dev, encoder, 3159 crtc_state->uapi.encoder_mask) { 3160 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 3161 struct intel_psr *psr = &intel_dp->psr; 3162 bool keep_disabled = false; 3163 3164 mutex_lock(&psr->lock); 3165 3166 drm_WARN_ON(display->drm, 3167 psr->enabled && !crtc_state->active_planes); 3168 3169 if (psr->sink_not_reliable) 3170 keep_disabled = true; 3171 3172 if (!crtc_state->active_planes) { 3173 psr->no_psr_reason = "All planes inactive"; 3174 keep_disabled = true; 3175 } 3176 3177 /* Display WA #1136: skl, bxt */ 3178 if (DISPLAY_VER(display) < 11 && crtc_state->wm_level_disabled) { 3179 psr->no_psr_reason = "Workaround #1136 for skl, bxt"; 3180 keep_disabled = true; 3181 } 3182 3183 if (!psr->enabled && !keep_disabled) 3184 intel_psr_enable_locked(intel_dp, crtc_state); 3185 else if (psr->enabled && !crtc_state->wm_level_disabled) 3186 /* Wa_14015648006 */ 3187 wm_optimization_wa(intel_dp, crtc_state); 3188 3189 /* Force a PSR exit when enabling CRC to avoid CRC timeouts */ 3190 if (crtc_state->crc_enabled && psr->enabled) 3191 intel_psr_force_update(intel_dp); 3192 3193 /* 3194 * Clear possible busy bits in case we have 3195 * invalidate -> flip -> flush sequence. 3196 */ 3197 intel_dp->psr.busy_frontbuffer_bits = 0; 3198 3199 mutex_unlock(&psr->lock); 3200 } 3201 } 3202 3203 /* 3204 * From bspec: Panel Self Refresh (BDW+) 3205 * Max. time for PSR to idle = Inverse of the refresh rate + 6 ms of 3206 * exit training time + 1.5 ms of aux channel handshake. 50 ms is 3207 * defensive enough to cover everything. 3208 */ 3209 #define PSR_IDLE_TIMEOUT_MS 50 3210 3211 static int 3212 _psr2_ready_for_pipe_update_locked(const struct intel_crtc_state *new_crtc_state, 3213 struct intel_dsb *dsb) 3214 { 3215 struct intel_display *display = to_intel_display(new_crtc_state); 3216 enum transcoder cpu_transcoder = new_crtc_state->cpu_transcoder; 3217 3218 /* 3219 * Any state lower than EDP_PSR2_STATUS_STATE_DEEP_SLEEP is enough. 3220 * As all higher states has bit 4 of PSR2 state set we can just wait for 3221 * EDP_PSR2_STATUS_STATE_DEEP_SLEEP to be cleared. 3222 */ 3223 if (dsb) { 3224 intel_dsb_poll(dsb, EDP_PSR2_STATUS(display, cpu_transcoder), 3225 EDP_PSR2_STATUS_STATE_DEEP_SLEEP, 0, 200, 3226 PSR_IDLE_TIMEOUT_MS * 1000 / 200); 3227 return true; 3228 } 3229 3230 return intel_de_wait_for_clear_ms(display, 3231 EDP_PSR2_STATUS(display, cpu_transcoder), 3232 EDP_PSR2_STATUS_STATE_DEEP_SLEEP, 3233 PSR_IDLE_TIMEOUT_MS); 3234 } 3235 3236 static int 3237 _psr1_ready_for_pipe_update_locked(const struct intel_crtc_state *new_crtc_state, 3238 struct intel_dsb *dsb) 3239 { 3240 struct intel_display *display = to_intel_display(new_crtc_state); 3241 enum transcoder cpu_transcoder = new_crtc_state->cpu_transcoder; 3242 3243 if (dsb) { 3244 intel_dsb_poll(dsb, psr_status_reg(display, cpu_transcoder), 3245 EDP_PSR_STATUS_STATE_MASK, 0, 200, 3246 PSR_IDLE_TIMEOUT_MS * 1000 / 200); 3247 return true; 3248 } 3249 3250 return intel_de_wait_for_clear_ms(display, 3251 psr_status_reg(display, cpu_transcoder), 3252 EDP_PSR_STATUS_STATE_MASK, 3253 PSR_IDLE_TIMEOUT_MS); 3254 } 3255 3256 /** 3257 * intel_psr_wait_for_idle_locked - wait for PSR be ready for a pipe update 3258 * @new_crtc_state: new CRTC state 3259 * 3260 * This function is expected to be called from pipe_update_start() where it is 3261 * not expected to race with PSR enable or disable. 3262 */ 3263 void intel_psr_wait_for_idle_locked(const struct intel_crtc_state *new_crtc_state) 3264 { 3265 struct intel_display *display = to_intel_display(new_crtc_state); 3266 struct intel_encoder *encoder; 3267 3268 if (!new_crtc_state->has_psr) 3269 return; 3270 3271 for_each_intel_encoder_mask_with_psr(display->drm, encoder, 3272 new_crtc_state->uapi.encoder_mask) { 3273 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 3274 int ret; 3275 3276 lockdep_assert_held(&intel_dp->psr.lock); 3277 3278 if (!intel_dp->psr.enabled || intel_dp->psr.panel_replay_enabled) 3279 continue; 3280 3281 if (intel_dp->psr.sel_update_enabled) 3282 ret = _psr2_ready_for_pipe_update_locked(new_crtc_state, 3283 NULL); 3284 else 3285 ret = _psr1_ready_for_pipe_update_locked(new_crtc_state, 3286 NULL); 3287 3288 if (ret) 3289 drm_err(display->drm, 3290 "PSR wait timed out, atomic update may fail\n"); 3291 } 3292 } 3293 3294 void intel_psr_wait_for_idle_dsb(struct intel_dsb *dsb, 3295 const struct intel_crtc_state *new_crtc_state) 3296 { 3297 if (!new_crtc_state->has_psr || new_crtc_state->has_panel_replay) 3298 return; 3299 3300 if (new_crtc_state->has_sel_update) 3301 _psr2_ready_for_pipe_update_locked(new_crtc_state, dsb); 3302 else 3303 _psr1_ready_for_pipe_update_locked(new_crtc_state, dsb); 3304 } 3305 3306 static bool __psr_wait_for_idle_locked(struct intel_dp *intel_dp) 3307 { 3308 struct intel_display *display = to_intel_display(intel_dp); 3309 enum transcoder cpu_transcoder = intel_dp->psr.transcoder; 3310 i915_reg_t reg; 3311 u32 mask; 3312 int err; 3313 3314 if (!intel_dp->psr.enabled) 3315 return false; 3316 3317 if (intel_dp_is_edp(intel_dp) && (intel_dp->psr.sel_update_enabled || 3318 intel_dp->psr.panel_replay_enabled)) { 3319 reg = EDP_PSR2_STATUS(display, cpu_transcoder); 3320 mask = EDP_PSR2_STATUS_STATE_MASK; 3321 } else { 3322 reg = psr_status_reg(display, cpu_transcoder); 3323 mask = EDP_PSR_STATUS_STATE_MASK; 3324 } 3325 3326 mutex_unlock(&intel_dp->psr.lock); 3327 3328 err = intel_de_wait_for_clear_ms(display, reg, mask, 50); 3329 if (err) 3330 drm_err(display->drm, 3331 "Timed out waiting for PSR Idle for re-enable\n"); 3332 3333 /* After the unlocked wait, verify that PSR is still wanted! */ 3334 mutex_lock(&intel_dp->psr.lock); 3335 return err == 0 && intel_dp->psr.enabled && !intel_dp->psr.pause_counter; 3336 } 3337 3338 static int intel_psr_fastset_force(struct intel_display *display) 3339 { 3340 struct drm_connector_list_iter conn_iter; 3341 struct drm_modeset_acquire_ctx ctx; 3342 struct drm_atomic_state *state; 3343 struct drm_connector *conn; 3344 int err = 0; 3345 3346 state = drm_atomic_state_alloc(display->drm); 3347 if (!state) 3348 return -ENOMEM; 3349 3350 drm_modeset_acquire_init(&ctx, DRM_MODESET_ACQUIRE_INTERRUPTIBLE); 3351 3352 state->acquire_ctx = &ctx; 3353 to_intel_atomic_state(state)->internal = true; 3354 3355 retry: 3356 drm_connector_list_iter_begin(display->drm, &conn_iter); 3357 drm_for_each_connector_iter(conn, &conn_iter) { 3358 struct drm_connector_state *conn_state; 3359 struct drm_crtc_state *crtc_state; 3360 3361 if (conn->connector_type != DRM_MODE_CONNECTOR_eDP) 3362 continue; 3363 3364 conn_state = drm_atomic_get_connector_state(state, conn); 3365 if (IS_ERR(conn_state)) { 3366 err = PTR_ERR(conn_state); 3367 break; 3368 } 3369 3370 if (!conn_state->crtc) 3371 continue; 3372 3373 crtc_state = drm_atomic_get_crtc_state(state, conn_state->crtc); 3374 if (IS_ERR(crtc_state)) { 3375 err = PTR_ERR(crtc_state); 3376 break; 3377 } 3378 3379 /* Mark mode as changed to trigger a pipe->update() */ 3380 crtc_state->mode_changed = true; 3381 } 3382 drm_connector_list_iter_end(&conn_iter); 3383 3384 if (err == 0) 3385 err = drm_atomic_commit(state); 3386 3387 if (err == -EDEADLK) { 3388 drm_atomic_state_clear(state); 3389 err = drm_modeset_backoff(&ctx); 3390 if (!err) 3391 goto retry; 3392 } 3393 3394 drm_modeset_drop_locks(&ctx); 3395 drm_modeset_acquire_fini(&ctx); 3396 drm_atomic_state_put(state); 3397 3398 return err; 3399 } 3400 3401 int intel_psr_debug_set(struct intel_dp *intel_dp, u64 val) 3402 { 3403 struct intel_display *display = to_intel_display(intel_dp); 3404 const u32 mode = val & I915_PSR_DEBUG_MODE_MASK; 3405 const u32 disable_bits = val & (I915_PSR_DEBUG_SU_REGION_ET_DISABLE | 3406 I915_PSR_DEBUG_PANEL_REPLAY_DISABLE); 3407 u32 old_mode, old_disable_bits; 3408 int ret; 3409 3410 if (val & ~(I915_PSR_DEBUG_IRQ | I915_PSR_DEBUG_SU_REGION_ET_DISABLE | 3411 I915_PSR_DEBUG_PANEL_REPLAY_DISABLE | 3412 I915_PSR_DEBUG_MODE_MASK) || 3413 mode > I915_PSR_DEBUG_ENABLE_SEL_FETCH) { 3414 drm_dbg_kms(display->drm, "Invalid debug mask %llx\n", val); 3415 return -EINVAL; 3416 } 3417 3418 ret = mutex_lock_interruptible(&intel_dp->psr.lock); 3419 if (ret) 3420 return ret; 3421 3422 old_mode = intel_dp->psr.debug & I915_PSR_DEBUG_MODE_MASK; 3423 old_disable_bits = intel_dp->psr.debug & 3424 (I915_PSR_DEBUG_SU_REGION_ET_DISABLE | 3425 I915_PSR_DEBUG_PANEL_REPLAY_DISABLE); 3426 3427 intel_dp->psr.debug = val; 3428 3429 /* 3430 * Do it right away if it's already enabled, otherwise it will be done 3431 * when enabling the source. 3432 */ 3433 if (intel_dp->psr.enabled) 3434 psr_irq_control(intel_dp); 3435 3436 mutex_unlock(&intel_dp->psr.lock); 3437 3438 if (old_mode != mode || old_disable_bits != disable_bits) 3439 ret = intel_psr_fastset_force(display); 3440 3441 return ret; 3442 } 3443 3444 static void intel_psr_handle_irq(struct intel_dp *intel_dp) 3445 { 3446 struct intel_psr *psr = &intel_dp->psr; 3447 3448 intel_psr_disable_locked(intel_dp); 3449 psr->sink_not_reliable = true; 3450 /* let's make sure that sink is awaken */ 3451 drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, DP_SET_POWER_D0); 3452 } 3453 3454 static void intel_psr_work(struct work_struct *work) 3455 { 3456 struct intel_dp *intel_dp = 3457 container_of(work, typeof(*intel_dp), psr.work); 3458 3459 mutex_lock(&intel_dp->psr.lock); 3460 3461 if (!intel_dp->psr.enabled) 3462 goto unlock; 3463 3464 if (READ_ONCE(intel_dp->psr.irq_aux_error)) { 3465 intel_psr_handle_irq(intel_dp); 3466 goto unlock; 3467 } 3468 3469 if (intel_dp->psr.pause_counter) 3470 goto unlock; 3471 3472 /* 3473 * We have to make sure PSR is ready for re-enable 3474 * otherwise it keeps disabled until next full enable/disable cycle. 3475 * PSR might take some time to get fully disabled 3476 * and be ready for re-enable. 3477 */ 3478 if (!__psr_wait_for_idle_locked(intel_dp)) 3479 goto unlock; 3480 3481 /* 3482 * The delayed work can race with an invalidate hence we need to 3483 * recheck. Since psr_flush first clears this and then reschedules we 3484 * won't ever miss a flush when bailing out here. 3485 */ 3486 if (intel_dp->psr.busy_frontbuffer_bits || intel_dp->psr.active) 3487 goto unlock; 3488 3489 intel_psr_activate(intel_dp); 3490 unlock: 3491 mutex_unlock(&intel_dp->psr.lock); 3492 } 3493 3494 static void intel_psr_configure_full_frame_update(struct intel_dp *intel_dp) 3495 { 3496 struct intel_display *display = to_intel_display(intel_dp); 3497 enum transcoder cpu_transcoder = intel_dp->psr.transcoder; 3498 3499 if (!intel_dp->psr.psr2_sel_fetch_enabled) 3500 return; 3501 3502 if (DISPLAY_VER(display) >= 20) 3503 intel_de_write(display, LNL_SFF_CTL(cpu_transcoder), 3504 LNL_SFF_CTL_SF_SINGLE_FULL_FRAME); 3505 else 3506 intel_de_write(display, 3507 PSR2_MAN_TRK_CTL(display, cpu_transcoder), 3508 man_trk_ctl_enable_bit_get(display) | 3509 man_trk_ctl_partial_frame_bit_get(display) | 3510 man_trk_ctl_single_full_frame_bit_get(display) | 3511 man_trk_ctl_continuos_full_frame(display)); 3512 } 3513 3514 static void _psr_invalidate_handle(struct intel_dp *intel_dp) 3515 { 3516 struct intel_display *display = to_intel_display(intel_dp); 3517 3518 if (DISPLAY_VER(display) < 20 && intel_dp->psr.psr2_sel_fetch_enabled) { 3519 if (!intel_dp->psr.psr2_sel_fetch_cff_enabled) { 3520 intel_dp->psr.psr2_sel_fetch_cff_enabled = true; 3521 intel_psr_configure_full_frame_update(intel_dp); 3522 } 3523 3524 intel_psr_force_update(intel_dp); 3525 } else { 3526 intel_psr_exit(intel_dp); 3527 } 3528 } 3529 3530 /** 3531 * intel_psr_invalidate - Invalidate PSR 3532 * @display: display device 3533 * @frontbuffer_bits: frontbuffer plane tracking bits 3534 * @origin: which operation caused the invalidate 3535 * 3536 * Since the hardware frontbuffer tracking has gaps we need to integrate 3537 * with the software frontbuffer tracking. This function gets called every 3538 * time frontbuffer rendering starts and a buffer gets dirtied. PSR must be 3539 * disabled if the frontbuffer mask contains a buffer relevant to PSR. 3540 * 3541 * Dirty frontbuffers relevant to PSR are tracked in busy_frontbuffer_bits." 3542 */ 3543 void intel_psr_invalidate(struct intel_display *display, 3544 unsigned frontbuffer_bits, enum fb_op_origin origin) 3545 { 3546 struct intel_encoder *encoder; 3547 3548 if (origin == ORIGIN_FLIP) 3549 return; 3550 3551 for_each_intel_encoder_with_psr(display->drm, encoder) { 3552 unsigned int pipe_frontbuffer_bits = frontbuffer_bits; 3553 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 3554 3555 mutex_lock(&intel_dp->psr.lock); 3556 if (!intel_dp->psr.enabled) { 3557 mutex_unlock(&intel_dp->psr.lock); 3558 continue; 3559 } 3560 3561 pipe_frontbuffer_bits &= 3562 INTEL_FRONTBUFFER_ALL_MASK(intel_dp->psr.pipe); 3563 intel_dp->psr.busy_frontbuffer_bits |= pipe_frontbuffer_bits; 3564 3565 if (pipe_frontbuffer_bits) 3566 _psr_invalidate_handle(intel_dp); 3567 3568 mutex_unlock(&intel_dp->psr.lock); 3569 } 3570 } 3571 /* 3572 * When we will be completely rely on PSR2 S/W tracking in future, 3573 * intel_psr_flush() will invalidate and flush the PSR for ORIGIN_FLIP 3574 * event also therefore tgl_dc3co_flush_locked() require to be changed 3575 * accordingly in future. 3576 */ 3577 static void 3578 tgl_dc3co_flush_locked(struct intel_dp *intel_dp, unsigned int frontbuffer_bits, 3579 enum fb_op_origin origin) 3580 { 3581 struct intel_display *display = to_intel_display(intel_dp); 3582 3583 if (!intel_dp->psr.dc3co_exitline || !intel_dp->psr.sel_update_enabled || 3584 !intel_dp->psr.active) 3585 return; 3586 3587 /* 3588 * At every frontbuffer flush flip event modified delay of delayed work, 3589 * when delayed work schedules that means display has been idle. 3590 */ 3591 if (!(frontbuffer_bits & 3592 INTEL_FRONTBUFFER_ALL_MASK(intel_dp->psr.pipe))) 3593 return; 3594 3595 tgl_psr2_enable_dc3co(intel_dp); 3596 mod_delayed_work(display->wq.unordered, &intel_dp->psr.dc3co_work, 3597 intel_dp->psr.dc3co_exit_delay); 3598 } 3599 3600 static void _psr_flush_handle(struct intel_dp *intel_dp) 3601 { 3602 struct intel_display *display = to_intel_display(intel_dp); 3603 3604 if (DISPLAY_VER(display) >= 20) { 3605 /* 3606 * We can use PSR exit on LunarLake onwards. Also 3607 * using trans push mechanism to trigger Frame Change 3608 * event requires using PSR exit. 3609 */ 3610 intel_psr_exit(intel_dp); 3611 } else if (intel_dp->psr.psr2_sel_fetch_enabled) { 3612 /* Selective fetch prior LNL */ 3613 if (intel_dp->psr.psr2_sel_fetch_cff_enabled) { 3614 /* can we turn CFF off? */ 3615 if (intel_dp->psr.busy_frontbuffer_bits == 0) 3616 intel_dp->psr.psr2_sel_fetch_cff_enabled = false; 3617 } 3618 3619 /* 3620 * Still keep cff bit enabled as we don't have proper SU 3621 * configuration in case update is sent for any reason after 3622 * sff bit gets cleared by the HW on next vblank. 3623 * 3624 * NOTE: Setting cff bit is not needed for LunarLake onwards as 3625 * we have own register for SFF bit and we are not overwriting 3626 * existing SU configuration 3627 */ 3628 intel_psr_configure_full_frame_update(intel_dp); 3629 3630 intel_psr_force_update(intel_dp); 3631 } else { 3632 /* 3633 * On older platforms using PSR exit was seen causing problems 3634 */ 3635 intel_psr_force_update(intel_dp); 3636 } 3637 3638 if (!intel_dp->psr.active && !intel_dp->psr.busy_frontbuffer_bits) 3639 queue_work(display->wq.unordered, &intel_dp->psr.work); 3640 } 3641 3642 /** 3643 * intel_psr_flush - Flush PSR 3644 * @display: display device 3645 * @frontbuffer_bits: frontbuffer plane tracking bits 3646 * @origin: which operation caused the flush 3647 * 3648 * Since the hardware frontbuffer tracking has gaps we need to integrate 3649 * with the software frontbuffer tracking. This function gets called every 3650 * time frontbuffer rendering has completed and flushed out to memory. PSR 3651 * can be enabled again if no other frontbuffer relevant to PSR is dirty. 3652 * 3653 * Dirty frontbuffers relevant to PSR are tracked in busy_frontbuffer_bits. 3654 */ 3655 void intel_psr_flush(struct intel_display *display, 3656 unsigned frontbuffer_bits, enum fb_op_origin origin) 3657 { 3658 struct intel_encoder *encoder; 3659 3660 for_each_intel_encoder_with_psr(display->drm, encoder) { 3661 unsigned int pipe_frontbuffer_bits = frontbuffer_bits; 3662 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 3663 3664 mutex_lock(&intel_dp->psr.lock); 3665 if (!intel_dp->psr.enabled) { 3666 mutex_unlock(&intel_dp->psr.lock); 3667 continue; 3668 } 3669 3670 pipe_frontbuffer_bits &= 3671 INTEL_FRONTBUFFER_ALL_MASK(intel_dp->psr.pipe); 3672 intel_dp->psr.busy_frontbuffer_bits &= ~pipe_frontbuffer_bits; 3673 3674 /* 3675 * If the PSR is paused by an explicit intel_psr_paused() call, 3676 * we have to ensure that the PSR is not activated until 3677 * intel_psr_resume() is called. 3678 */ 3679 if (intel_dp->psr.pause_counter) 3680 goto unlock; 3681 3682 if (origin == ORIGIN_FLIP || 3683 (origin == ORIGIN_CURSOR_UPDATE && 3684 !intel_dp->psr.psr2_sel_fetch_enabled)) { 3685 tgl_dc3co_flush_locked(intel_dp, frontbuffer_bits, origin); 3686 goto unlock; 3687 } 3688 3689 if (pipe_frontbuffer_bits == 0) 3690 goto unlock; 3691 3692 /* By definition flush = invalidate + flush */ 3693 _psr_flush_handle(intel_dp); 3694 unlock: 3695 mutex_unlock(&intel_dp->psr.lock); 3696 } 3697 } 3698 3699 /** 3700 * intel_psr_init - Init basic PSR work and mutex. 3701 * @intel_dp: Intel DP 3702 * 3703 * This function is called after the initializing connector. 3704 * (the initializing of connector treats the handling of connector capabilities) 3705 * And it initializes basic PSR stuff for each DP Encoder. 3706 */ 3707 void intel_psr_init(struct intel_dp *intel_dp) 3708 { 3709 struct intel_display *display = to_intel_display(intel_dp); 3710 struct intel_connector *connector = intel_dp->attached_connector; 3711 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 3712 3713 if (!(HAS_PSR(display) || HAS_DP20(display))) 3714 return; 3715 3716 /* 3717 * HSW spec explicitly says PSR is tied to port A. 3718 * BDW+ platforms have a instance of PSR registers per transcoder but 3719 * BDW, GEN9 and GEN11 are not validated by HW team in other transcoder 3720 * than eDP one. 3721 * For now it only supports one instance of PSR for BDW, GEN9 and GEN11. 3722 * So lets keep it hardcoded to PORT_A for BDW, GEN9 and GEN11. 3723 * But GEN12 supports a instance of PSR registers per transcoder. 3724 */ 3725 if (DISPLAY_VER(display) < 12 && dig_port->base.port != PORT_A) { 3726 drm_dbg_kms(display->drm, 3727 "PSR condition failed: Port not supported\n"); 3728 return; 3729 } 3730 3731 if ((HAS_DP20(display) && !intel_dp_is_edp(intel_dp)) || 3732 DISPLAY_VER(display) >= 20) 3733 intel_dp->psr.source_panel_replay_support = true; 3734 3735 if (HAS_PSR(display) && intel_dp_is_edp(intel_dp)) 3736 intel_dp->psr.source_support = true; 3737 3738 /* Set link_standby x link_off defaults */ 3739 if (DISPLAY_VER(display) < 12) 3740 /* For new platforms up to TGL let's respect VBT back again */ 3741 intel_dp->psr.link_standby = connector->panel.vbt.psr.full_link; 3742 3743 INIT_WORK(&intel_dp->psr.work, intel_psr_work); 3744 INIT_DELAYED_WORK(&intel_dp->psr.dc3co_work, tgl_dc3co_disable_work); 3745 mutex_init(&intel_dp->psr.lock); 3746 } 3747 3748 static int psr_get_status_and_error_status(struct intel_dp *intel_dp, 3749 u8 *status, u8 *error_status) 3750 { 3751 struct drm_dp_aux *aux = &intel_dp->aux; 3752 int ret; 3753 unsigned int offset; 3754 3755 offset = intel_dp->psr.panel_replay_enabled ? 3756 DP_SINK_DEVICE_PR_AND_FRAME_LOCK_STATUS : DP_PSR_STATUS; 3757 3758 ret = drm_dp_dpcd_readb(aux, offset, status); 3759 if (ret != 1) 3760 return ret; 3761 3762 offset = intel_dp->psr.panel_replay_enabled ? 3763 DP_PANEL_REPLAY_ERROR_STATUS : DP_PSR_ERROR_STATUS; 3764 3765 ret = drm_dp_dpcd_readb(aux, offset, error_status); 3766 if (ret != 1) 3767 return ret; 3768 3769 *status = *status & DP_PSR_SINK_STATE_MASK; 3770 3771 return 0; 3772 } 3773 3774 static void psr_alpm_check(struct intel_dp *intel_dp) 3775 { 3776 struct intel_psr *psr = &intel_dp->psr; 3777 3778 if (!psr->sel_update_enabled) 3779 return; 3780 3781 if (intel_alpm_get_error(intel_dp)) { 3782 intel_psr_disable_locked(intel_dp); 3783 psr->sink_not_reliable = true; 3784 } 3785 } 3786 3787 static void psr_capability_changed_check(struct intel_dp *intel_dp) 3788 { 3789 struct intel_display *display = to_intel_display(intel_dp); 3790 struct intel_psr *psr = &intel_dp->psr; 3791 u8 val; 3792 int r; 3793 3794 r = drm_dp_dpcd_readb(&intel_dp->aux, DP_PSR_ESI, &val); 3795 if (r != 1) { 3796 drm_err(display->drm, "Error reading DP_PSR_ESI\n"); 3797 return; 3798 } 3799 3800 if (val & DP_PSR_CAPS_CHANGE) { 3801 intel_psr_disable_locked(intel_dp); 3802 psr->sink_not_reliable = true; 3803 drm_dbg_kms(display->drm, 3804 "Sink PSR capability changed, disabling PSR\n"); 3805 3806 /* Clearing it */ 3807 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_ESI, val); 3808 } 3809 } 3810 3811 /* 3812 * On common bits: 3813 * DP_PSR_RFB_STORAGE_ERROR == DP_PANEL_REPLAY_RFB_STORAGE_ERROR 3814 * DP_PSR_VSC_SDP_UNCORRECTABLE_ERROR == DP_PANEL_REPLAY_VSC_SDP_UNCORRECTABLE_ERROR 3815 * DP_PSR_LINK_CRC_ERROR == DP_PANEL_REPLAY_LINK_CRC_ERROR 3816 * this function is relying on PSR definitions 3817 */ 3818 void intel_psr_short_pulse(struct intel_dp *intel_dp) 3819 { 3820 struct intel_display *display = to_intel_display(intel_dp); 3821 struct intel_psr *psr = &intel_dp->psr; 3822 u8 status, error_status; 3823 const u8 errors = DP_PSR_RFB_STORAGE_ERROR | 3824 DP_PSR_VSC_SDP_UNCORRECTABLE_ERROR | 3825 DP_PSR_LINK_CRC_ERROR; 3826 3827 if (!CAN_PSR(intel_dp) && !CAN_PANEL_REPLAY(intel_dp)) 3828 return; 3829 3830 mutex_lock(&psr->lock); 3831 3832 psr->link_ok = false; 3833 3834 if (!psr->enabled) 3835 goto exit; 3836 3837 if (psr_get_status_and_error_status(intel_dp, &status, &error_status)) { 3838 drm_err(display->drm, 3839 "Error reading PSR status or error status\n"); 3840 goto exit; 3841 } 3842 3843 if ((!psr->panel_replay_enabled && status == DP_PSR_SINK_INTERNAL_ERROR) || 3844 (error_status & errors)) { 3845 intel_psr_disable_locked(intel_dp); 3846 psr->sink_not_reliable = true; 3847 } 3848 3849 if (!psr->panel_replay_enabled && status == DP_PSR_SINK_INTERNAL_ERROR && 3850 !error_status) 3851 drm_dbg_kms(display->drm, 3852 "PSR sink internal error, disabling PSR\n"); 3853 if (error_status & DP_PSR_RFB_STORAGE_ERROR) 3854 drm_dbg_kms(display->drm, 3855 "PSR RFB storage error, disabling PSR\n"); 3856 if (error_status & DP_PSR_VSC_SDP_UNCORRECTABLE_ERROR) 3857 drm_dbg_kms(display->drm, 3858 "PSR VSC SDP uncorrectable error, disabling PSR\n"); 3859 if (error_status & DP_PSR_LINK_CRC_ERROR) 3860 drm_dbg_kms(display->drm, 3861 "PSR Link CRC error, disabling PSR\n"); 3862 3863 if (error_status & ~errors) 3864 drm_err(display->drm, 3865 "PSR_ERROR_STATUS unhandled errors %x\n", 3866 error_status & ~errors); 3867 /* clear status register */ 3868 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_ERROR_STATUS, error_status); 3869 3870 if (!psr->panel_replay_enabled) { 3871 psr_alpm_check(intel_dp); 3872 psr_capability_changed_check(intel_dp); 3873 } 3874 3875 exit: 3876 mutex_unlock(&psr->lock); 3877 } 3878 3879 bool intel_psr_enabled(struct intel_dp *intel_dp) 3880 { 3881 bool ret; 3882 3883 if (!CAN_PSR(intel_dp)) 3884 return false; 3885 3886 mutex_lock(&intel_dp->psr.lock); 3887 ret = intel_dp->psr.enabled; 3888 mutex_unlock(&intel_dp->psr.lock); 3889 3890 return ret; 3891 } 3892 3893 /** 3894 * intel_psr_link_ok - return psr->link_ok 3895 * @intel_dp: struct intel_dp 3896 * 3897 * We are seeing unexpected link re-trainings with some panels. This is caused 3898 * by panel stating bad link status after PSR is enabled. Code checking link 3899 * status can call this to ensure it can ignore bad link status stated by the 3900 * panel I.e. if panel is stating bad link and intel_psr_link_ok is stating link 3901 * is ok caller should rely on latter. 3902 * 3903 * Return value of link_ok 3904 */ 3905 bool intel_psr_link_ok(struct intel_dp *intel_dp) 3906 { 3907 bool ret; 3908 3909 if ((!CAN_PSR(intel_dp) && !CAN_PANEL_REPLAY(intel_dp)) || 3910 !intel_dp_is_edp(intel_dp)) 3911 return false; 3912 3913 mutex_lock(&intel_dp->psr.lock); 3914 ret = intel_dp->psr.link_ok; 3915 mutex_unlock(&intel_dp->psr.lock); 3916 3917 return ret; 3918 } 3919 3920 /** 3921 * intel_psr_lock - grab PSR lock 3922 * @crtc_state: the crtc state 3923 * 3924 * This is initially meant to be used by around CRTC update, when 3925 * vblank sensitive registers are updated and we need grab the lock 3926 * before it to avoid vblank evasion. 3927 */ 3928 void intel_psr_lock(const struct intel_crtc_state *crtc_state) 3929 { 3930 struct intel_display *display = to_intel_display(crtc_state); 3931 struct intel_encoder *encoder; 3932 3933 if (!crtc_state->has_psr) 3934 return; 3935 3936 for_each_intel_encoder_mask_with_psr(display->drm, encoder, 3937 crtc_state->uapi.encoder_mask) { 3938 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 3939 3940 mutex_lock(&intel_dp->psr.lock); 3941 break; 3942 } 3943 } 3944 3945 /** 3946 * intel_psr_unlock - release PSR lock 3947 * @crtc_state: the crtc state 3948 * 3949 * Release the PSR lock that was held during pipe update. 3950 */ 3951 void intel_psr_unlock(const struct intel_crtc_state *crtc_state) 3952 { 3953 struct intel_display *display = to_intel_display(crtc_state); 3954 struct intel_encoder *encoder; 3955 3956 if (!crtc_state->has_psr) 3957 return; 3958 3959 for_each_intel_encoder_mask_with_psr(display->drm, encoder, 3960 crtc_state->uapi.encoder_mask) { 3961 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 3962 3963 mutex_unlock(&intel_dp->psr.lock); 3964 break; 3965 } 3966 } 3967 3968 /* Wa_16025596647 */ 3969 static void intel_psr_apply_underrun_on_idle_wa_locked(struct intel_dp *intel_dp) 3970 { 3971 struct intel_display *display = to_intel_display(intel_dp); 3972 bool dc5_dc6_blocked; 3973 3974 if (!intel_dp->psr.active || !intel_dp->psr.pkg_c_latency_used) 3975 return; 3976 3977 dc5_dc6_blocked = is_dc5_dc6_blocked(intel_dp); 3978 3979 if (intel_dp->psr.sel_update_enabled) 3980 psr2_program_idle_frames(intel_dp, dc5_dc6_blocked ? 0 : 3981 psr_compute_idle_frames(intel_dp)); 3982 else 3983 intel_dmc_start_pkgc_exit_at_start_of_undelayed_vblank(display, 3984 intel_dp->psr.pipe, 3985 dc5_dc6_blocked); 3986 } 3987 3988 static void psr_dc5_dc6_wa_work(struct work_struct *work) 3989 { 3990 struct intel_display *display = container_of(work, typeof(*display), 3991 psr_dc5_dc6_wa_work); 3992 struct intel_encoder *encoder; 3993 3994 for_each_intel_encoder_with_psr(display->drm, encoder) { 3995 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 3996 3997 mutex_lock(&intel_dp->psr.lock); 3998 3999 if (intel_dp->psr.enabled && !intel_dp->psr.panel_replay_enabled && 4000 !intel_dp->psr.pkg_c_latency_used) 4001 intel_psr_apply_underrun_on_idle_wa_locked(intel_dp); 4002 4003 mutex_unlock(&intel_dp->psr.lock); 4004 } 4005 } 4006 4007 /** 4008 * intel_psr_notify_dc5_dc6 - Notify PSR about enable/disable dc5/dc6 4009 * @display: intel atomic state 4010 * 4011 * This is targeted for underrun on idle PSR HW bug (Wa_16025596647) to schedule 4012 * psr_dc5_dc6_wa_work used for applying/removing the workaround. 4013 */ 4014 void intel_psr_notify_dc5_dc6(struct intel_display *display) 4015 { 4016 if (!intel_display_wa(display, INTEL_DISPLAY_WA_16025596647)) 4017 return; 4018 4019 schedule_work(&display->psr_dc5_dc6_wa_work); 4020 } 4021 4022 /** 4023 * intel_psr_dc5_dc6_wa_init - Init work for underrun on idle PSR HW bug wa 4024 * @display: intel atomic state 4025 * 4026 * This is targeted for underrun on idle PSR HW bug (Wa_16025596647) to init 4027 * psr_dc5_dc6_wa_work used for applying the workaround. 4028 */ 4029 void intel_psr_dc5_dc6_wa_init(struct intel_display *display) 4030 { 4031 if (!intel_display_wa(display, INTEL_DISPLAY_WA_16025596647)) 4032 return; 4033 4034 INIT_WORK(&display->psr_dc5_dc6_wa_work, psr_dc5_dc6_wa_work); 4035 } 4036 4037 /** 4038 * intel_psr_notify_pipe_change - Notify PSR about enable/disable of a pipe 4039 * @state: intel atomic state 4040 * @crtc: intel crtc 4041 * @enable: enable/disable 4042 * 4043 * This is targeted for underrun on idle PSR HW bug (Wa_16025596647) to apply 4044 * remove the workaround when pipe is getting enabled/disabled 4045 */ 4046 void intel_psr_notify_pipe_change(struct intel_atomic_state *state, 4047 struct intel_crtc *crtc, bool enable) 4048 { 4049 struct intel_display *display = to_intel_display(state); 4050 struct intel_encoder *encoder; 4051 4052 if (!intel_display_wa(display, INTEL_DISPLAY_WA_16025596647)) 4053 return; 4054 4055 for_each_intel_encoder_with_psr(display->drm, encoder) { 4056 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 4057 u8 active_non_psr_pipes; 4058 4059 mutex_lock(&intel_dp->psr.lock); 4060 4061 if (!intel_dp->psr.enabled || intel_dp->psr.panel_replay_enabled) 4062 goto unlock; 4063 4064 active_non_psr_pipes = intel_dp->psr.active_non_psr_pipes; 4065 4066 if (enable) 4067 active_non_psr_pipes |= BIT(crtc->pipe); 4068 else 4069 active_non_psr_pipes &= ~BIT(crtc->pipe); 4070 4071 if (active_non_psr_pipes == intel_dp->psr.active_non_psr_pipes) 4072 goto unlock; 4073 4074 if ((enable && intel_dp->psr.active_non_psr_pipes) || 4075 (!enable && !intel_dp->psr.active_non_psr_pipes) || 4076 !intel_dp->psr.pkg_c_latency_used) { 4077 intel_dp->psr.active_non_psr_pipes = active_non_psr_pipes; 4078 goto unlock; 4079 } 4080 4081 intel_dp->psr.active_non_psr_pipes = active_non_psr_pipes; 4082 4083 intel_psr_apply_underrun_on_idle_wa_locked(intel_dp); 4084 unlock: 4085 mutex_unlock(&intel_dp->psr.lock); 4086 } 4087 } 4088 4089 /** 4090 * intel_psr_notify_vblank_enable_disable - Notify PSR about enable/disable of vblank 4091 * @display: intel display struct 4092 * @enable: enable/disable 4093 * 4094 * This is targeted for underrun on idle PSR HW bug (Wa_16025596647) to apply 4095 * remove the workaround when vblank is getting enabled/disabled 4096 */ 4097 void intel_psr_notify_vblank_enable_disable(struct intel_display *display, 4098 bool enable) 4099 { 4100 struct intel_encoder *encoder; 4101 4102 for_each_intel_encoder_with_psr(display->drm, encoder) { 4103 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 4104 4105 mutex_lock(&intel_dp->psr.lock); 4106 if (intel_dp->psr.panel_replay_enabled) { 4107 mutex_unlock(&intel_dp->psr.lock); 4108 break; 4109 } 4110 4111 if (intel_dp->psr.enabled && intel_dp->psr.pkg_c_latency_used) 4112 intel_psr_apply_underrun_on_idle_wa_locked(intel_dp); 4113 4114 mutex_unlock(&intel_dp->psr.lock); 4115 return; 4116 } 4117 4118 /* 4119 * NOTE: intel_display_power_set_target_dc_state is used 4120 * only by PSR * code for DC3CO handling. DC3CO target 4121 * state is currently disabled in * PSR code. If DC3CO 4122 * is taken into use we need take that into account here 4123 * as well. 4124 */ 4125 intel_display_power_set_target_dc_state(display, enable ? DC_STATE_DISABLE : 4126 DC_STATE_EN_UPTO_DC6); 4127 } 4128 4129 static void 4130 psr_source_status(struct intel_dp *intel_dp, struct seq_file *m) 4131 { 4132 struct intel_display *display = to_intel_display(intel_dp); 4133 enum transcoder cpu_transcoder = intel_dp->psr.transcoder; 4134 const char *status = "unknown"; 4135 u32 val, status_val; 4136 4137 if ((intel_dp_is_edp(intel_dp) || DISPLAY_VER(display) >= 30) && 4138 (intel_dp->psr.sel_update_enabled || intel_dp->psr.panel_replay_enabled)) { 4139 static const char * const live_status[] = { 4140 "IDLE", 4141 "CAPTURE", 4142 "CAPTURE_FS", 4143 "SLEEP", 4144 "BUFON_FW", 4145 "ML_UP", 4146 "SU_STANDBY", 4147 "FAST_SLEEP", 4148 "DEEP_SLEEP", 4149 "BUF_ON", 4150 "TG_ON" 4151 }; 4152 val = intel_de_read(display, 4153 EDP_PSR2_STATUS(display, cpu_transcoder)); 4154 status_val = REG_FIELD_GET(EDP_PSR2_STATUS_STATE_MASK, val); 4155 if (status_val < ARRAY_SIZE(live_status)) 4156 status = live_status[status_val]; 4157 } else { 4158 static const char * const live_status[] = { 4159 "IDLE", 4160 "SRDONACK", 4161 "SRDENT", 4162 "BUFOFF", 4163 "BUFON", 4164 "AUXACK", 4165 "SRDOFFACK", 4166 "SRDENT_ON", 4167 }; 4168 val = intel_de_read(display, 4169 psr_status_reg(display, cpu_transcoder)); 4170 status_val = REG_FIELD_GET(EDP_PSR_STATUS_STATE_MASK, val); 4171 if (status_val < ARRAY_SIZE(live_status)) 4172 status = live_status[status_val]; 4173 } 4174 4175 seq_printf(m, "Source PSR/PanelReplay status: %s [0x%08x]\n", status, val); 4176 } 4177 4178 static void intel_psr_sink_capability(struct intel_connector *connector, 4179 struct seq_file *m) 4180 { 4181 seq_printf(m, "Sink support: PSR = %s", 4182 str_yes_no(connector->dp.psr_caps.support)); 4183 4184 if (connector->dp.psr_caps.support) 4185 seq_printf(m, " [0x%02x]", connector->dp.psr_caps.dpcd[0]); 4186 if (connector->dp.psr_caps.dpcd[0] == DP_PSR2_WITH_Y_COORD_ET_SUPPORTED) 4187 seq_printf(m, " (Early Transport)"); 4188 seq_printf(m, ", Panel Replay = %s", str_yes_no(connector->dp.panel_replay_caps.support)); 4189 seq_printf(m, ", Panel Replay Selective Update = %s", 4190 str_yes_no(connector->dp.panel_replay_caps.su_support)); 4191 seq_printf(m, ", Panel Replay DSC support = %s", 4192 panel_replay_dsc_support_str(connector->dp.panel_replay_caps.dsc_support)); 4193 if (connector->dp.panel_replay_caps.dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_SUPPORT)] & 4194 DP_PANEL_REPLAY_EARLY_TRANSPORT_SUPPORT) 4195 seq_printf(m, " (Early Transport)"); 4196 seq_printf(m, "\n"); 4197 } 4198 4199 static void intel_psr_print_mode(struct intel_dp *intel_dp, 4200 struct seq_file *m) 4201 { 4202 struct intel_psr *psr = &intel_dp->psr; 4203 const char *status, *mode, *region_et; 4204 4205 if (psr->enabled) 4206 status = " enabled"; 4207 else 4208 status = "disabled"; 4209 4210 if (psr->panel_replay_enabled && psr->sel_update_enabled) 4211 mode = "Panel Replay Selective Update"; 4212 else if (psr->panel_replay_enabled) 4213 mode = "Panel Replay"; 4214 else if (psr->sel_update_enabled) 4215 mode = "PSR2"; 4216 else if (psr->enabled) 4217 mode = "PSR1"; 4218 else 4219 mode = ""; 4220 4221 if (psr->su_region_et_enabled) 4222 region_et = " (Early Transport)"; 4223 else 4224 region_et = ""; 4225 4226 seq_printf(m, "PSR mode: %s%s%s\n", mode, status, region_et); 4227 if (psr->no_psr_reason) 4228 seq_printf(m, " %s\n", psr->no_psr_reason); 4229 } 4230 4231 static int intel_psr_status(struct seq_file *m, struct intel_dp *intel_dp, 4232 struct intel_connector *connector) 4233 { 4234 struct intel_display *display = to_intel_display(intel_dp); 4235 enum transcoder cpu_transcoder = intel_dp->psr.transcoder; 4236 struct intel_psr *psr = &intel_dp->psr; 4237 struct ref_tracker *wakeref; 4238 bool enabled; 4239 u32 val, psr2_ctl; 4240 4241 intel_psr_sink_capability(connector, m); 4242 4243 if (!(connector->dp.psr_caps.support || connector->dp.panel_replay_caps.support)) 4244 return 0; 4245 4246 wakeref = intel_display_rpm_get(display); 4247 mutex_lock(&psr->lock); 4248 4249 intel_psr_print_mode(intel_dp, m); 4250 4251 if (!psr->enabled) { 4252 seq_printf(m, "PSR sink not reliable: %s\n", 4253 str_yes_no(psr->sink_not_reliable)); 4254 4255 goto unlock; 4256 } 4257 4258 if (psr->panel_replay_enabled) { 4259 val = intel_de_read(display, TRANS_DP2_CTL(cpu_transcoder)); 4260 4261 if (intel_dp_is_edp(intel_dp)) 4262 psr2_ctl = intel_de_read(display, 4263 EDP_PSR2_CTL(display, 4264 cpu_transcoder)); 4265 4266 enabled = val & TRANS_DP2_PANEL_REPLAY_ENABLE; 4267 } else if (psr->sel_update_enabled) { 4268 val = intel_de_read(display, 4269 EDP_PSR2_CTL(display, cpu_transcoder)); 4270 enabled = val & EDP_PSR2_ENABLE; 4271 } else { 4272 val = intel_de_read(display, psr_ctl_reg(display, cpu_transcoder)); 4273 enabled = val & EDP_PSR_ENABLE; 4274 } 4275 seq_printf(m, "Source PSR/PanelReplay ctl: %s [0x%08x]\n", 4276 str_enabled_disabled(enabled), val); 4277 if (psr->panel_replay_enabled && intel_dp_is_edp(intel_dp)) 4278 seq_printf(m, "PSR2_CTL: 0x%08x\n", 4279 psr2_ctl); 4280 psr_source_status(intel_dp, m); 4281 seq_printf(m, "Busy frontbuffer bits: 0x%08x\n", 4282 psr->busy_frontbuffer_bits); 4283 4284 /* 4285 * SKL+ Perf counter is reset to 0 everytime DC state is entered 4286 */ 4287 val = intel_de_read(display, psr_perf_cnt_reg(display, cpu_transcoder)); 4288 seq_printf(m, "Performance counter: %u\n", 4289 REG_FIELD_GET(EDP_PSR_PERF_CNT_MASK, val)); 4290 4291 if (psr->debug & I915_PSR_DEBUG_IRQ) { 4292 seq_printf(m, "Last attempted entry at: %lld\n", 4293 psr->last_entry_attempt); 4294 seq_printf(m, "Last exit at: %lld\n", psr->last_exit); 4295 } 4296 4297 if (psr->sel_update_enabled) { 4298 u32 su_frames_val[3]; 4299 int frame; 4300 4301 /* 4302 * PSR2_SU_STATUS register has been tied-off since DG2/ADL-P 4303 * (it returns zeros only) and it has been removed on Xe2_LPD. 4304 */ 4305 if (DISPLAY_VER(display) < 13) { 4306 /* 4307 * Reading all 3 registers before hand to minimize crossing a 4308 * frame boundary between register reads 4309 */ 4310 for (frame = 0; frame < PSR2_SU_STATUS_FRAMES; frame += 3) { 4311 val = intel_de_read(display, 4312 PSR2_SU_STATUS(display, cpu_transcoder, frame)); 4313 su_frames_val[frame / 3] = val; 4314 } 4315 4316 seq_puts(m, "Frame:\tPSR2 SU blocks:\n"); 4317 4318 for (frame = 0; frame < PSR2_SU_STATUS_FRAMES; frame++) { 4319 u32 su_blocks; 4320 4321 su_blocks = su_frames_val[frame / 3] & 4322 PSR2_SU_STATUS_MASK(frame); 4323 su_blocks = su_blocks >> PSR2_SU_STATUS_SHIFT(frame); 4324 seq_printf(m, "%d\t%d\n", frame, su_blocks); 4325 } 4326 } 4327 4328 seq_printf(m, "PSR2 selective fetch: %s\n", 4329 str_enabled_disabled(psr->psr2_sel_fetch_enabled)); 4330 } 4331 4332 unlock: 4333 mutex_unlock(&psr->lock); 4334 intel_display_rpm_put(display, wakeref); 4335 4336 return 0; 4337 } 4338 4339 static int i915_edp_psr_status_show(struct seq_file *m, void *data) 4340 { 4341 struct intel_display *display = m->private; 4342 struct intel_dp *intel_dp = NULL; 4343 struct intel_encoder *encoder; 4344 4345 if (!HAS_PSR(display)) 4346 return -ENODEV; 4347 4348 /* Find the first EDP which supports PSR */ 4349 for_each_intel_encoder_with_psr(display->drm, encoder) { 4350 intel_dp = enc_to_intel_dp(encoder); 4351 break; 4352 } 4353 4354 if (!intel_dp) 4355 return -ENODEV; 4356 4357 return intel_psr_status(m, intel_dp, intel_dp->attached_connector); 4358 } 4359 DEFINE_SHOW_ATTRIBUTE(i915_edp_psr_status); 4360 4361 static int 4362 i915_edp_psr_debug_set(void *data, u64 val) 4363 { 4364 struct intel_display *display = data; 4365 struct intel_encoder *encoder; 4366 int ret = -ENODEV; 4367 4368 if (!HAS_PSR(display)) 4369 return ret; 4370 4371 for_each_intel_encoder_with_psr(display->drm, encoder) { 4372 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 4373 4374 drm_dbg_kms(display->drm, "Setting PSR debug to %llx\n", val); 4375 4376 // TODO: split to each transcoder's PSR debug state 4377 with_intel_display_rpm(display) 4378 ret = intel_psr_debug_set(intel_dp, val); 4379 } 4380 4381 return ret; 4382 } 4383 4384 static int 4385 i915_edp_psr_debug_get(void *data, u64 *val) 4386 { 4387 struct intel_display *display = data; 4388 struct intel_encoder *encoder; 4389 4390 if (!HAS_PSR(display)) 4391 return -ENODEV; 4392 4393 for_each_intel_encoder_with_psr(display->drm, encoder) { 4394 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 4395 4396 // TODO: split to each transcoder's PSR debug state 4397 *val = READ_ONCE(intel_dp->psr.debug); 4398 return 0; 4399 } 4400 4401 return -ENODEV; 4402 } 4403 4404 DEFINE_SIMPLE_ATTRIBUTE(i915_edp_psr_debug_fops, 4405 i915_edp_psr_debug_get, i915_edp_psr_debug_set, 4406 "%llu\n"); 4407 4408 void intel_psr_debugfs_register(struct intel_display *display) 4409 { 4410 struct dentry *debugfs_root = display->drm->debugfs_root; 4411 4412 debugfs_create_file("i915_edp_psr_debug", 0644, debugfs_root, 4413 display, &i915_edp_psr_debug_fops); 4414 4415 debugfs_create_file("i915_edp_psr_status", 0444, debugfs_root, 4416 display, &i915_edp_psr_status_fops); 4417 } 4418 4419 static const char *psr_mode_str(struct intel_dp *intel_dp) 4420 { 4421 if (intel_dp->psr.panel_replay_enabled) 4422 return "PANEL-REPLAY"; 4423 else if (intel_dp->psr.enabled) 4424 return "PSR"; 4425 4426 return "unknown"; 4427 } 4428 4429 static int i915_psr_sink_status_show(struct seq_file *m, void *data) 4430 { 4431 struct intel_connector *connector = m->private; 4432 struct intel_dp *intel_dp = intel_attached_dp(connector); 4433 static const char * const sink_status[] = { 4434 "inactive", 4435 "transition to active, capture and display", 4436 "active, display from RFB", 4437 "active, capture and display on sink device timings", 4438 "transition to inactive, capture and display, timing re-sync", 4439 "reserved", 4440 "reserved", 4441 "sink internal error", 4442 }; 4443 const char *str; 4444 int ret; 4445 u8 status, error_status; 4446 4447 if (!(CAN_PSR(intel_dp) || CAN_PANEL_REPLAY(intel_dp))) { 4448 seq_puts(m, "PSR/Panel-Replay Unsupported\n"); 4449 return -ENODEV; 4450 } 4451 4452 if (connector->base.status != connector_status_connected) 4453 return -ENODEV; 4454 4455 ret = psr_get_status_and_error_status(intel_dp, &status, &error_status); 4456 if (ret) 4457 return ret; 4458 4459 status &= DP_PSR_SINK_STATE_MASK; 4460 if (status < ARRAY_SIZE(sink_status)) 4461 str = sink_status[status]; 4462 else 4463 str = "unknown"; 4464 4465 seq_printf(m, "Sink %s status: 0x%x [%s]\n", psr_mode_str(intel_dp), status, str); 4466 4467 seq_printf(m, "Sink %s error status: 0x%x", psr_mode_str(intel_dp), error_status); 4468 4469 if (error_status & (DP_PSR_RFB_STORAGE_ERROR | 4470 DP_PSR_VSC_SDP_UNCORRECTABLE_ERROR | 4471 DP_PSR_LINK_CRC_ERROR)) 4472 seq_puts(m, ":\n"); 4473 else 4474 seq_puts(m, "\n"); 4475 if (error_status & DP_PSR_RFB_STORAGE_ERROR) 4476 seq_printf(m, "\t%s RFB storage error\n", psr_mode_str(intel_dp)); 4477 if (error_status & DP_PSR_VSC_SDP_UNCORRECTABLE_ERROR) 4478 seq_printf(m, "\t%s VSC SDP uncorrectable error\n", psr_mode_str(intel_dp)); 4479 if (error_status & DP_PSR_LINK_CRC_ERROR) 4480 seq_printf(m, "\t%s Link CRC error\n", psr_mode_str(intel_dp)); 4481 4482 return ret; 4483 } 4484 DEFINE_SHOW_ATTRIBUTE(i915_psr_sink_status); 4485 4486 static int i915_psr_status_show(struct seq_file *m, void *data) 4487 { 4488 struct intel_connector *connector = m->private; 4489 struct intel_dp *intel_dp = intel_attached_dp(connector); 4490 4491 return intel_psr_status(m, intel_dp, connector); 4492 } 4493 DEFINE_SHOW_ATTRIBUTE(i915_psr_status); 4494 4495 void intel_psr_connector_debugfs_add(struct intel_connector *connector) 4496 { 4497 struct intel_display *display = to_intel_display(connector); 4498 struct dentry *root = connector->base.debugfs_entry; 4499 4500 if (connector->base.connector_type != DRM_MODE_CONNECTOR_eDP && 4501 connector->base.connector_type != DRM_MODE_CONNECTOR_DisplayPort) 4502 return; 4503 4504 debugfs_create_file("i915_psr_sink_status", 0444, root, 4505 connector, &i915_psr_sink_status_fops); 4506 4507 if (HAS_PSR(display) || HAS_DP20(display)) 4508 debugfs_create_file("i915_psr_status", 0444, root, 4509 connector, &i915_psr_status_fops); 4510 } 4511 4512 bool intel_psr_needs_alpm(struct intel_dp *intel_dp, const struct intel_crtc_state *crtc_state) 4513 { 4514 /* 4515 * eDP Panel Replay uses always ALPM 4516 * PSR2 uses ALPM but PSR1 doesn't 4517 */ 4518 return intel_dp_is_edp(intel_dp) && (crtc_state->has_sel_update || 4519 crtc_state->has_panel_replay); 4520 } 4521 4522 bool intel_psr_needs_alpm_aux_less(struct intel_dp *intel_dp, 4523 const struct intel_crtc_state *crtc_state) 4524 { 4525 return intel_dp_is_edp(intel_dp) && crtc_state->has_panel_replay; 4526 } 4527 4528 void intel_psr_compute_config_late(struct intel_dp *intel_dp, 4529 struct intel_crtc_state *crtc_state) 4530 { 4531 struct intel_display *display = to_intel_display(intel_dp); 4532 int vblank = intel_crtc_vblank_length(crtc_state); 4533 int wake_lines; 4534 4535 if (intel_psr_needs_alpm_aux_less(intel_dp, crtc_state)) 4536 wake_lines = crtc_state->alpm_state.aux_less_wake_lines; 4537 else if (intel_psr_needs_alpm(intel_dp, crtc_state)) 4538 wake_lines = DISPLAY_VER(display) < 20 ? 4539 psr2_block_count_lines(crtc_state->alpm_state.io_wake_lines, 4540 crtc_state->alpm_state.fast_wake_lines) : 4541 crtc_state->alpm_state.io_wake_lines; 4542 else 4543 wake_lines = 0; 4544 4545 /* 4546 * Disable the PSR features if wake lines exceed the available vblank. 4547 * Though SCL is computed based on these PSR features, it is not reset 4548 * even if the PSR features are disabled to avoid changing vblank start 4549 * at this stage. 4550 */ 4551 if (wake_lines && !_wake_lines_fit_into_vblank(crtc_state, vblank, wake_lines)) { 4552 drm_dbg_kms(display->drm, 4553 "Adjusting PSR/PR mode: vblank too short for wake lines = %d\n", 4554 wake_lines); 4555 4556 if (crtc_state->has_panel_replay) { 4557 crtc_state->has_panel_replay = false; 4558 /* 4559 * #TODO : Add fall back to PSR/PSR2 4560 * Since panel replay cannot be supported, we can fall back to PSR/PSR2. 4561 * This will require calling compute_config for psr and psr2 with check for 4562 * actual guardband instead of vblank_length. 4563 */ 4564 crtc_state->has_psr = false; 4565 } 4566 4567 crtc_state->has_sel_update = false; 4568 crtc_state->enable_psr2_su_region_et = false; 4569 crtc_state->enable_psr2_sel_fetch = false; 4570 } 4571 4572 /* Wa_18037818876 */ 4573 if (intel_psr_needs_wa_18037818876(intel_dp, crtc_state)) { 4574 crtc_state->has_psr = false; 4575 drm_dbg_kms(display->drm, 4576 "PSR disabled to workaround PSR FSM hang issue\n"); 4577 } 4578 4579 intel_psr_set_non_psr_pipes(intel_dp, crtc_state); 4580 } 4581 4582 int intel_psr_min_guardband(struct intel_crtc_state *crtc_state) 4583 { 4584 struct intel_display *display = to_intel_display(crtc_state); 4585 int psr_min_guardband; 4586 int wake_lines; 4587 4588 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) 4589 return 0; 4590 4591 if (crtc_state->has_panel_replay) 4592 wake_lines = crtc_state->alpm_state.aux_less_wake_lines; 4593 else if (crtc_state->has_sel_update) 4594 wake_lines = DISPLAY_VER(display) < 20 ? 4595 psr2_block_count_lines(crtc_state->alpm_state.io_wake_lines, 4596 crtc_state->alpm_state.fast_wake_lines) : 4597 crtc_state->alpm_state.io_wake_lines; 4598 else 4599 return 0; 4600 4601 psr_min_guardband = wake_lines + crtc_state->set_context_latency; 4602 4603 if (crtc_state->req_psr2_sdp_prior_scanline) 4604 psr_min_guardband++; 4605 4606 return psr_min_guardband; 4607 } 4608 4609 bool intel_psr_use_trans_push(const struct intel_crtc_state *crtc_state) 4610 { 4611 struct intel_display *display = to_intel_display(crtc_state); 4612 4613 return HAS_PSR_TRANS_PUSH_FRAME_CHANGE(display) && crtc_state->has_psr; 4614 } 4615