1 /* 2 * Copyright © 2014 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 */ 23 24 #include <linux/debugfs.h> 25 26 #include <drm/drm_atomic_helper.h> 27 #include <drm/drm_damage_helper.h> 28 #include <drm/drm_debugfs.h> 29 #include <drm/drm_print.h> 30 #include <drm/drm_vblank.h> 31 32 #include "intel_alpm.h" 33 #include "intel_atomic.h" 34 #include "intel_crtc.h" 35 #include "intel_cursor_regs.h" 36 #include "intel_ddi.h" 37 #include "intel_de.h" 38 #include "intel_display_irq.h" 39 #include "intel_display_regs.h" 40 #include "intel_display_rpm.h" 41 #include "intel_display_types.h" 42 #include "intel_display_utils.h" 43 #include "intel_display_wa.h" 44 #include "intel_dmc.h" 45 #include "intel_dp.h" 46 #include "intel_dp_aux.h" 47 #include "intel_dsb.h" 48 #include "intel_frontbuffer.h" 49 #include "intel_hdmi.h" 50 #include "intel_psr.h" 51 #include "intel_psr_regs.h" 52 #include "intel_quirks.h" 53 #include "intel_snps_phy.h" 54 #include "intel_step.h" 55 #include "intel_vblank.h" 56 #include "intel_vdsc.h" 57 #include "intel_vrr.h" 58 #include "skl_universal_plane.h" 59 60 /** 61 * DOC: Panel Self Refresh (PSR/SRD) 62 * 63 * Since Haswell Display controller supports Panel Self-Refresh on display 64 * panels witch have a remote frame buffer (RFB) implemented according to PSR 65 * spec in eDP1.3. PSR feature allows the display to go to lower standby states 66 * when system is idle but display is on as it eliminates display refresh 67 * request to DDR memory completely as long as the frame buffer for that 68 * display is unchanged. 69 * 70 * Panel Self Refresh must be supported by both Hardware (source) and 71 * Panel (sink). 72 * 73 * PSR saves power by caching the framebuffer in the panel RFB, which allows us 74 * to power down the link and memory controller. For DSI panels the same idea 75 * is called "manual mode". 76 * 77 * The implementation uses the hardware-based PSR support which automatically 78 * enters/exits self-refresh mode. The hardware takes care of sending the 79 * required DP aux message and could even retrain the link (that part isn't 80 * enabled yet though). The hardware also keeps track of any frontbuffer 81 * changes to know when to exit self-refresh mode again. Unfortunately that 82 * part doesn't work too well, hence why the i915 PSR support uses the 83 * software frontbuffer tracking to make sure it doesn't miss a screen 84 * update. For this integration intel_psr_invalidate() and intel_psr_flush() 85 * get called by the frontbuffer tracking code. Note that because of locking 86 * issues the self-refresh re-enable code is done from a work queue, which 87 * must be correctly synchronized/cancelled when shutting down the pipe." 88 * 89 * DC3CO (DC3 clock off) 90 * 91 * On top of PSR2, GEN12 adds a intermediate power savings state that turns 92 * clock off automatically during PSR2 idle state. 93 * The smaller overhead of DC3co entry/exit vs. the overhead of PSR2 deep sleep 94 * entry/exit allows the HW to enter a low-power state even when page flipping 95 * periodically (for instance a 30fps video playback scenario). 96 * 97 * Every time a flips occurs PSR2 will get out of deep sleep state(if it was), 98 * so DC3CO is enabled and tgl_dc3co_disable_work is schedule to run after 6 99 * frames, if no other flip occurs and the function above is executed, DC3CO is 100 * disabled and PSR2 is configured to enter deep sleep, resetting again in case 101 * of another flip. 102 * Front buffer modifications do not trigger DC3CO activation on purpose as it 103 * would bring a lot of complexity and most of the moderns systems will only 104 * use page flips. 105 */ 106 107 /* 108 * Description of PSR mask bits: 109 * 110 * EDP_PSR_DEBUG[16]/EDP_PSR_DEBUG_MASK_DISP_REG_WRITE (hsw-skl): 111 * 112 * When unmasked (nearly) all display register writes (eg. even 113 * SWF) trigger a PSR exit. Some registers are excluded from this 114 * and they have a more specific mask (described below). On icl+ 115 * this bit no longer exists and is effectively always set. 116 * 117 * PIPE_MISC[21]/PIPE_MISC_PSR_MASK_PIPE_REG_WRITE (skl+): 118 * 119 * When unmasked (nearly) all pipe/plane register writes 120 * trigger a PSR exit. Some plane registers are excluded from this 121 * and they have a more specific mask (described below). 122 * 123 * CHICKEN_PIPESL_1[11]/SKL_PSR_MASK_PLANE_FLIP (skl+): 124 * PIPE_MISC[23]/PIPE_MISC_PSR_MASK_PRIMARY_FLIP (bdw): 125 * EDP_PSR_DEBUG[23]/EDP_PSR_DEBUG_MASK_PRIMARY_FLIP (hsw): 126 * 127 * When unmasked PRI_SURF/PLANE_SURF writes trigger a PSR exit. 128 * SPR_SURF/CURBASE are not included in this and instead are 129 * controlled by PIPE_MISC_PSR_MASK_PIPE_REG_WRITE (skl+) or 130 * EDP_PSR_DEBUG_MASK_DISP_REG_WRITE (hsw/bdw). 131 * 132 * PIPE_MISC[22]/PIPE_MISC_PSR_MASK_SPRITE_ENABLE (bdw): 133 * EDP_PSR_DEBUG[21]/EDP_PSR_DEBUG_MASK_SPRITE_ENABLE (hsw): 134 * 135 * When unmasked PSR is blocked as long as the sprite 136 * plane is enabled. skl+ with their universal planes no 137 * longer have a mask bit like this, and no plane being 138 * enabledb blocks PSR. 139 * 140 * PIPE_MISC[21]/PIPE_MISC_PSR_MASK_CURSOR_MOVE (bdw): 141 * EDP_PSR_DEBUG[20]/EDP_PSR_DEBUG_MASK_CURSOR_MOVE (hsw): 142 * 143 * When umasked CURPOS writes trigger a PSR exit. On skl+ 144 * this doesn't exit but CURPOS is included in the 145 * PIPE_MISC_PSR_MASK_PIPE_REG_WRITE mask. 146 * 147 * PIPE_MISC[20]/PIPE_MISC_PSR_MASK_VBLANK_VSYNC_INT (bdw+): 148 * EDP_PSR_DEBUG[19]/EDP_PSR_DEBUG_MASK_VBLANK_VSYNC_INT (hsw): 149 * 150 * When unmasked PSR is blocked as long as vblank and/or vsync 151 * interrupt is unmasked in IMR *and* enabled in IER. 152 * 153 * CHICKEN_TRANS[30]/SKL_UNMASK_VBL_TO_PIPE_IN_SRD (skl+): 154 * CHICKEN_PAR1_1[15]/HSW_MASK_VBL_TO_PIPE_IN_SRD (hsw/bdw): 155 * 156 * Selectcs whether PSR exit generates an extra vblank before 157 * the first frame is transmitted. Also note the opposite polarity 158 * if the bit on hsw/bdw vs. skl+ (masked==generate the extra vblank, 159 * unmasked==do not generate the extra vblank). 160 * 161 * With DC states enabled the extra vblank happens after link training, 162 * with DC states disabled it happens immediately upuon PSR exit trigger. 163 * No idea as of now why there is a difference. HSW/BDW (which don't 164 * even have DMC) always generate it after link training. Go figure. 165 * 166 * Unfortunately CHICKEN_TRANS itself seems to be double buffered 167 * and thus won't latch until the first vblank. So with DC states 168 * enabled the register effectively uses the reset value during DC5 169 * exit+PSR exit sequence, and thus the bit does nothing until 170 * latched by the vblank that it was trying to prevent from being 171 * generated in the first place. So we should probably call this 172 * one a chicken/egg bit instead on skl+. 173 * 174 * In standby mode (as opposed to link-off) this makes no difference 175 * as the timing generator keeps running the whole time generating 176 * normal periodic vblanks. 177 * 178 * WaPsrDPAMaskVBlankInSRD asks us to set the bit on hsw/bdw, 179 * and doing so makes the behaviour match the skl+ reset value. 180 * 181 * CHICKEN_PIPESL_1[0]/BDW_UNMASK_VBL_TO_REGS_IN_SRD (bdw): 182 * CHICKEN_PIPESL_1[15]/HSW_UNMASK_VBL_TO_REGS_IN_SRD (hsw): 183 * 184 * On BDW without this bit is no vblanks whatsoever are 185 * generated after PSR exit. On HSW this has no apparent effect. 186 * WaPsrDPRSUnmaskVBlankInSRD says to set this. 187 * 188 * The rest of the bits are more self-explanatory and/or 189 * irrelevant for normal operation. 190 * 191 * Description of intel_crtc_state variables. has_psr, has_panel_replay and 192 * has_sel_update: 193 * 194 * has_psr (alone): PSR1 195 * has_psr + has_sel_update: PSR2 196 * has_psr + has_panel_replay: Panel Replay 197 * has_psr + has_panel_replay + has_sel_update: Panel Replay Selective Update 198 * 199 * Description of some intel_psr variables. enabled, panel_replay_enabled, 200 * sel_update_enabled 201 * 202 * enabled (alone): PSR1 203 * enabled + sel_update_enabled: PSR2 204 * enabled + panel_replay_enabled: Panel Replay 205 * enabled + panel_replay_enabled + sel_update_enabled: Panel Replay SU 206 */ 207 208 #define CAN_PSR(intel_dp) ((intel_dp)->psr.sink_support && \ 209 (intel_dp)->psr.source_support) 210 211 bool intel_encoder_can_psr(struct intel_encoder *encoder) 212 { 213 if (intel_encoder_is_dp(encoder) || encoder->type == INTEL_OUTPUT_DP_MST) 214 return CAN_PSR(enc_to_intel_dp(encoder)) || 215 CAN_PANEL_REPLAY(enc_to_intel_dp(encoder)); 216 else 217 return false; 218 } 219 220 bool intel_psr_needs_aux_io_power(struct intel_encoder *encoder, 221 const struct intel_crtc_state *crtc_state) 222 { 223 /* 224 * For PSR/PR modes only eDP requires the AUX IO power to be enabled whenever 225 * the output is enabled. For non-eDP outputs the main link is always 226 * on, hence it doesn't require the HW initiated AUX wake-up signaling used 227 * for eDP. 228 * 229 * TODO: 230 * - Consider leaving AUX IO disabled for eDP / PR as well, in case 231 * the ALPM with main-link off mode is not enabled. 232 * - Leave AUX IO enabled for DP / PR, once support for ALPM with 233 * main-link off mode is added for it and this mode gets enabled. 234 */ 235 return intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP) && 236 intel_encoder_can_psr(encoder); 237 } 238 239 static bool psr_global_enabled(struct intel_dp *intel_dp) 240 { 241 struct intel_connector *connector = intel_dp->attached_connector; 242 243 switch (intel_dp->psr.debug & I915_PSR_DEBUG_MODE_MASK) { 244 case I915_PSR_DEBUG_DEFAULT: 245 return intel_dp_is_edp(intel_dp) ? 246 connector->panel.vbt.psr.enable : true; 247 case I915_PSR_DEBUG_DISABLE: 248 return false; 249 default: 250 return true; 251 } 252 } 253 254 static bool sel_update_global_enabled(struct intel_dp *intel_dp) 255 { 256 switch (intel_dp->psr.debug & I915_PSR_DEBUG_MODE_MASK) { 257 case I915_PSR_DEBUG_DISABLE: 258 case I915_PSR_DEBUG_FORCE_PSR1: 259 return false; 260 default: 261 return true; 262 } 263 } 264 265 static bool panel_replay_global_enabled(struct intel_dp *intel_dp) 266 { 267 struct intel_display *display = to_intel_display(intel_dp); 268 269 return !(intel_dp->psr.debug & I915_PSR_DEBUG_PANEL_REPLAY_DISABLE) && 270 display->params.enable_panel_replay; 271 } 272 273 static u32 psr_irq_psr_error_bit_get(struct intel_dp *intel_dp) 274 { 275 struct intel_display *display = to_intel_display(intel_dp); 276 277 return DISPLAY_VER(display) >= 12 ? TGL_PSR_ERROR : 278 EDP_PSR_ERROR(intel_dp->psr.transcoder); 279 } 280 281 static u32 psr_irq_post_exit_bit_get(struct intel_dp *intel_dp) 282 { 283 struct intel_display *display = to_intel_display(intel_dp); 284 285 return DISPLAY_VER(display) >= 12 ? TGL_PSR_POST_EXIT : 286 EDP_PSR_POST_EXIT(intel_dp->psr.transcoder); 287 } 288 289 static u32 psr_irq_pre_entry_bit_get(struct intel_dp *intel_dp) 290 { 291 struct intel_display *display = to_intel_display(intel_dp); 292 293 return DISPLAY_VER(display) >= 12 ? TGL_PSR_PRE_ENTRY : 294 EDP_PSR_PRE_ENTRY(intel_dp->psr.transcoder); 295 } 296 297 static u32 psr_irq_mask_get(struct intel_dp *intel_dp) 298 { 299 struct intel_display *display = to_intel_display(intel_dp); 300 301 return DISPLAY_VER(display) >= 12 ? TGL_PSR_MASK : 302 EDP_PSR_MASK(intel_dp->psr.transcoder); 303 } 304 305 static i915_reg_t psr_ctl_reg(struct intel_display *display, 306 enum transcoder cpu_transcoder) 307 { 308 if (DISPLAY_VER(display) >= 8) 309 return EDP_PSR_CTL(display, cpu_transcoder); 310 else 311 return HSW_SRD_CTL; 312 } 313 314 static i915_reg_t psr_debug_reg(struct intel_display *display, 315 enum transcoder cpu_transcoder) 316 { 317 if (DISPLAY_VER(display) >= 8) 318 return EDP_PSR_DEBUG(display, cpu_transcoder); 319 else 320 return HSW_SRD_DEBUG; 321 } 322 323 static i915_reg_t psr_perf_cnt_reg(struct intel_display *display, 324 enum transcoder cpu_transcoder) 325 { 326 if (DISPLAY_VER(display) >= 8) 327 return EDP_PSR_PERF_CNT(display, cpu_transcoder); 328 else 329 return HSW_SRD_PERF_CNT; 330 } 331 332 static i915_reg_t psr_status_reg(struct intel_display *display, 333 enum transcoder cpu_transcoder) 334 { 335 if (DISPLAY_VER(display) >= 8) 336 return EDP_PSR_STATUS(display, cpu_transcoder); 337 else 338 return HSW_SRD_STATUS; 339 } 340 341 static i915_reg_t psr_imr_reg(struct intel_display *display, 342 enum transcoder cpu_transcoder) 343 { 344 if (DISPLAY_VER(display) >= 12) 345 return TRANS_PSR_IMR(display, cpu_transcoder); 346 else 347 return EDP_PSR_IMR; 348 } 349 350 static i915_reg_t psr_iir_reg(struct intel_display *display, 351 enum transcoder cpu_transcoder) 352 { 353 if (DISPLAY_VER(display) >= 12) 354 return TRANS_PSR_IIR(display, cpu_transcoder); 355 else 356 return EDP_PSR_IIR; 357 } 358 359 static i915_reg_t psr_aux_ctl_reg(struct intel_display *display, 360 enum transcoder cpu_transcoder) 361 { 362 if (DISPLAY_VER(display) >= 8) 363 return EDP_PSR_AUX_CTL(display, cpu_transcoder); 364 else 365 return HSW_SRD_AUX_CTL; 366 } 367 368 static i915_reg_t psr_aux_data_reg(struct intel_display *display, 369 enum transcoder cpu_transcoder, int i) 370 { 371 if (DISPLAY_VER(display) >= 8) 372 return EDP_PSR_AUX_DATA(display, cpu_transcoder, i); 373 else 374 return HSW_SRD_AUX_DATA(i); 375 } 376 377 static void psr_irq_control(struct intel_dp *intel_dp) 378 { 379 struct intel_display *display = to_intel_display(intel_dp); 380 enum transcoder cpu_transcoder = intel_dp->psr.transcoder; 381 u32 mask; 382 383 if (intel_dp->psr.panel_replay_enabled) 384 return; 385 386 mask = psr_irq_psr_error_bit_get(intel_dp); 387 if (intel_dp->psr.debug & I915_PSR_DEBUG_IRQ) 388 mask |= psr_irq_post_exit_bit_get(intel_dp) | 389 psr_irq_pre_entry_bit_get(intel_dp); 390 391 intel_de_rmw(display, psr_imr_reg(display, cpu_transcoder), 392 psr_irq_mask_get(intel_dp), ~mask); 393 } 394 395 static void psr_event_print(struct intel_display *display, 396 u32 val, bool sel_update_enabled) 397 { 398 drm_dbg_kms(display->drm, "PSR exit events: 0x%x\n", val); 399 if (val & PSR_EVENT_PSR2_WD_TIMER_EXPIRE) 400 drm_dbg_kms(display->drm, "\tPSR2 watchdog timer expired\n"); 401 if ((val & PSR_EVENT_PSR2_DISABLED) && sel_update_enabled) 402 drm_dbg_kms(display->drm, "\tPSR2 disabled\n"); 403 if (val & PSR_EVENT_SU_DIRTY_FIFO_UNDERRUN) 404 drm_dbg_kms(display->drm, "\tSU dirty FIFO underrun\n"); 405 if (val & PSR_EVENT_SU_CRC_FIFO_UNDERRUN) 406 drm_dbg_kms(display->drm, "\tSU CRC FIFO underrun\n"); 407 if (val & PSR_EVENT_GRAPHICS_RESET) 408 drm_dbg_kms(display->drm, "\tGraphics reset\n"); 409 if (val & PSR_EVENT_PCH_INTERRUPT) 410 drm_dbg_kms(display->drm, "\tPCH interrupt\n"); 411 if (val & PSR_EVENT_MEMORY_UP) 412 drm_dbg_kms(display->drm, "\tMemory up\n"); 413 if (val & PSR_EVENT_FRONT_BUFFER_MODIFY) 414 drm_dbg_kms(display->drm, "\tFront buffer modification\n"); 415 if (val & PSR_EVENT_WD_TIMER_EXPIRE) 416 drm_dbg_kms(display->drm, "\tPSR watchdog timer expired\n"); 417 if (val & PSR_EVENT_PIPE_REGISTERS_UPDATE) 418 drm_dbg_kms(display->drm, "\tPIPE registers updated\n"); 419 if (val & PSR_EVENT_REGISTER_UPDATE) 420 drm_dbg_kms(display->drm, "\tRegister updated\n"); 421 if (val & PSR_EVENT_HDCP_ENABLE) 422 drm_dbg_kms(display->drm, "\tHDCP enabled\n"); 423 if (val & PSR_EVENT_KVMR_SESSION_ENABLE) 424 drm_dbg_kms(display->drm, "\tKVMR session enabled\n"); 425 if (val & PSR_EVENT_VBI_ENABLE) 426 drm_dbg_kms(display->drm, "\tVBI enabled\n"); 427 if (val & PSR_EVENT_LPSP_MODE_EXIT) 428 drm_dbg_kms(display->drm, "\tLPSP mode exited\n"); 429 if ((val & PSR_EVENT_PSR_DISABLE) && !sel_update_enabled) 430 drm_dbg_kms(display->drm, "\tPSR disabled\n"); 431 } 432 433 void intel_psr_irq_handler(struct intel_dp *intel_dp, u32 psr_iir) 434 { 435 struct intel_display *display = to_intel_display(intel_dp); 436 enum transcoder cpu_transcoder = intel_dp->psr.transcoder; 437 ktime_t time_ns = ktime_get(); 438 439 if (psr_iir & psr_irq_pre_entry_bit_get(intel_dp)) { 440 intel_dp->psr.last_entry_attempt = time_ns; 441 drm_dbg_kms(display->drm, 442 "[transcoder %s] PSR entry attempt in 2 vblanks\n", 443 transcoder_name(cpu_transcoder)); 444 } 445 446 if (psr_iir & psr_irq_post_exit_bit_get(intel_dp)) { 447 intel_dp->psr.last_exit = time_ns; 448 drm_dbg_kms(display->drm, 449 "[transcoder %s] PSR exit completed\n", 450 transcoder_name(cpu_transcoder)); 451 452 if (DISPLAY_VER(display) >= 9) { 453 u32 val; 454 455 val = intel_de_rmw(display, 456 PSR_EVENT(display, cpu_transcoder), 457 0, 0); 458 459 psr_event_print(display, val, intel_dp->psr.sel_update_enabled); 460 } 461 } 462 463 if (psr_iir & psr_irq_psr_error_bit_get(intel_dp)) { 464 drm_warn(display->drm, "[transcoder %s] PSR aux error\n", 465 transcoder_name(cpu_transcoder)); 466 467 intel_dp->psr.irq_aux_error = true; 468 469 /* 470 * If this interruption is not masked it will keep 471 * interrupting so fast that it prevents the scheduled 472 * work to run. 473 * Also after a PSR error, we don't want to arm PSR 474 * again so we don't care about unmask the interruption 475 * or unset irq_aux_error. 476 */ 477 intel_de_rmw(display, psr_imr_reg(display, cpu_transcoder), 478 0, psr_irq_psr_error_bit_get(intel_dp)); 479 480 queue_work(display->wq.unordered, &intel_dp->psr.work); 481 } 482 } 483 484 static u8 intel_dp_get_sink_sync_latency(struct intel_dp *intel_dp) 485 { 486 struct intel_display *display = to_intel_display(intel_dp); 487 u8 val = 8; /* assume the worst if we can't read the value */ 488 489 if (drm_dp_dpcd_readb(&intel_dp->aux, 490 DP_SYNCHRONIZATION_LATENCY_IN_SINK, &val) == 1) 491 val &= DP_MAX_RESYNC_FRAME_COUNT_MASK; 492 else 493 drm_dbg_kms(display->drm, 494 "Unable to get sink synchronization latency, assuming 8 frames\n"); 495 return val; 496 } 497 498 static void _psr_compute_su_granularity(struct intel_dp *intel_dp, 499 struct intel_connector *connector) 500 { 501 struct intel_display *display = to_intel_display(intel_dp); 502 ssize_t r; 503 __le16 w; 504 u8 y; 505 506 /* 507 * If sink don't have specific granularity requirements set legacy 508 * ones. 509 */ 510 if (!(connector->dp.psr_caps.dpcd[1] & DP_PSR2_SU_GRANULARITY_REQUIRED)) { 511 /* As PSR2 HW sends full lines, we do not care about x granularity */ 512 w = cpu_to_le16(4); 513 y = 4; 514 goto exit; 515 } 516 517 r = drm_dp_dpcd_read(&intel_dp->aux, DP_PSR2_SU_X_GRANULARITY, &w, sizeof(w)); 518 if (r != sizeof(w)) 519 drm_dbg_kms(display->drm, 520 "Unable to read selective update x granularity\n"); 521 /* 522 * Spec says that if the value read is 0 the default granularity should 523 * be used instead. 524 */ 525 if (r != sizeof(w) || w == 0) 526 w = cpu_to_le16(4); 527 528 r = drm_dp_dpcd_read(&intel_dp->aux, DP_PSR2_SU_Y_GRANULARITY, &y, 1); 529 if (r != 1) { 530 drm_dbg_kms(display->drm, 531 "Unable to read selective update y granularity\n"); 532 y = 4; 533 } 534 if (y == 0) 535 y = 1; 536 537 exit: 538 connector->dp.psr_caps.su_w_granularity = le16_to_cpu(w); 539 connector->dp.psr_caps.su_y_granularity = y; 540 } 541 542 static enum intel_panel_replay_dsc_support 543 compute_pr_dsc_support(struct intel_connector *connector) 544 { 545 u8 pr_dsc_mode; 546 u8 val; 547 548 val = connector->dp.panel_replay_caps.dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_CAPABILITY)]; 549 pr_dsc_mode = REG_FIELD_GET8(DP_PANEL_REPLAY_DSC_DECODE_CAPABILITY_IN_PR_MASK, val); 550 551 switch (pr_dsc_mode) { 552 case DP_DSC_DECODE_CAPABILITY_IN_PR_FULL_FRAME_ONLY: 553 return INTEL_DP_PANEL_REPLAY_DSC_FULL_FRAME_ONLY; 554 case DP_DSC_DECODE_CAPABILITY_IN_PR_SUPPORTED: 555 return INTEL_DP_PANEL_REPLAY_DSC_SELECTIVE_UPDATE; 556 default: 557 MISSING_CASE(pr_dsc_mode); 558 fallthrough; 559 case DP_DSC_DECODE_CAPABILITY_IN_PR_NOT_SUPPORTED: 560 case DP_DSC_DECODE_CAPABILITY_IN_PR_RESERVED: 561 return INTEL_DP_PANEL_REPLAY_DSC_NOT_SUPPORTED; 562 } 563 } 564 565 static const char *panel_replay_dsc_support_str(enum intel_panel_replay_dsc_support dsc_support) 566 { 567 switch (dsc_support) { 568 case INTEL_DP_PANEL_REPLAY_DSC_NOT_SUPPORTED: 569 return "not supported"; 570 case INTEL_DP_PANEL_REPLAY_DSC_FULL_FRAME_ONLY: 571 return "full frame only"; 572 case INTEL_DP_PANEL_REPLAY_DSC_SELECTIVE_UPDATE: 573 return "selective update"; 574 default: 575 MISSING_CASE(dsc_support); 576 return "n/a"; 577 }; 578 } 579 580 static void _panel_replay_compute_su_granularity(struct intel_connector *connector) 581 { 582 u16 w; 583 u8 y; 584 585 if (!(connector->dp.panel_replay_caps.dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_CAPABILITY)] & 586 DP_PANEL_REPLAY_SU_GRANULARITY_REQUIRED)) { 587 w = 4; 588 y = 4; 589 goto exit; 590 } 591 592 /* 593 * Spec says that if the value read is 0 the default granularity should 594 * be used instead. 595 */ 596 w = le16_to_cpu(*(__le16 *)&connector->dp.panel_replay_caps.dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_X_GRANULARITY)]) ? : 4; 597 y = connector->dp.panel_replay_caps.dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_Y_GRANULARITY)] ? : 1; 598 599 exit: 600 connector->dp.panel_replay_caps.su_w_granularity = w; 601 connector->dp.panel_replay_caps.su_y_granularity = y; 602 } 603 604 static void _panel_replay_init_dpcd(struct intel_dp *intel_dp, struct intel_connector *connector) 605 { 606 struct intel_display *display = to_intel_display(intel_dp); 607 int ret; 608 609 /* TODO: Enable Panel Replay on MST once it's properly implemented. */ 610 if (intel_dp->mst_detect == DRM_DP_MST) 611 return; 612 613 if (intel_dp_is_edp(intel_dp) && 614 intel_has_dpcd_quirk(intel_dp, QUIRK_DISABLE_EDP_PANEL_REPLAY)) { 615 drm_dbg_kms(display->drm, 616 "Panel Replay support not currently available for this setup\n"); 617 return; 618 } 619 620 ret = drm_dp_dpcd_read_data(&intel_dp->aux, DP_PANEL_REPLAY_CAP_SUPPORT, 621 &connector->dp.panel_replay_caps.dpcd, 622 sizeof(connector->dp.panel_replay_caps.dpcd)); 623 if (ret < 0) 624 return; 625 626 if (!(connector->dp.panel_replay_caps.dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_SUPPORT)] & 627 DP_PANEL_REPLAY_SUPPORT)) 628 return; 629 630 if (intel_dp_is_edp(intel_dp)) { 631 if (!intel_alpm_aux_less_wake_supported(intel_dp)) { 632 drm_dbg_kms(display->drm, 633 "Panel doesn't support AUX-less ALPM, eDP Panel Replay not possible\n"); 634 return; 635 } 636 637 if (!(connector->dp.panel_replay_caps.dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_SUPPORT)] & 638 DP_PANEL_REPLAY_EARLY_TRANSPORT_SUPPORT)) { 639 drm_dbg_kms(display->drm, 640 "Panel doesn't support early transport, eDP Panel Replay not possible\n"); 641 return; 642 } 643 } 644 645 connector->dp.panel_replay_caps.support = true; 646 intel_dp->psr.sink_panel_replay_support = true; 647 648 if (connector->dp.panel_replay_caps.dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_SUPPORT)] & 649 DP_PANEL_REPLAY_SU_SUPPORT) { 650 connector->dp.panel_replay_caps.su_support = true; 651 652 _panel_replay_compute_su_granularity(connector); 653 } 654 655 connector->dp.panel_replay_caps.dsc_support = compute_pr_dsc_support(connector); 656 657 drm_dbg_kms(display->drm, 658 "Panel replay %sis supported by panel (in DSC mode: %s)\n", 659 connector->dp.panel_replay_caps.su_support ? 660 "selective_update " : "", 661 panel_replay_dsc_support_str(connector->dp.panel_replay_caps.dsc_support)); 662 } 663 664 static void _psr_init_dpcd(struct intel_dp *intel_dp, struct intel_connector *connector) 665 { 666 struct intel_display *display = to_intel_display(intel_dp); 667 int ret; 668 669 ret = drm_dp_dpcd_read_data(&intel_dp->aux, DP_PSR_SUPPORT, connector->dp.psr_caps.dpcd, 670 sizeof(connector->dp.psr_caps.dpcd)); 671 if (ret < 0) 672 return; 673 674 if (!connector->dp.psr_caps.dpcd[0]) 675 return; 676 677 drm_dbg_kms(display->drm, "eDP panel supports PSR version %x\n", 678 connector->dp.psr_caps.dpcd[0]); 679 680 if (drm_dp_has_quirk(&intel_dp->desc, DP_DPCD_QUIRK_NO_PSR)) { 681 drm_dbg_kms(display->drm, 682 "PSR support not currently available for this panel\n"); 683 return; 684 } 685 686 if (!(intel_dp->edp_dpcd[1] & DP_EDP_SET_POWER_CAP)) { 687 drm_dbg_kms(display->drm, 688 "Panel lacks power state control, PSR cannot be enabled\n"); 689 return; 690 } 691 692 connector->dp.psr_caps.support = true; 693 intel_dp->psr.sink_support = true; 694 695 connector->dp.psr_caps.sync_latency = intel_dp_get_sink_sync_latency(intel_dp); 696 697 if (DISPLAY_VER(display) >= 9 && 698 connector->dp.psr_caps.dpcd[0] >= DP_PSR2_WITH_Y_COORD_IS_SUPPORTED) { 699 bool y_req = connector->dp.psr_caps.dpcd[1] & 700 DP_PSR2_SU_Y_COORDINATE_REQUIRED; 701 702 /* 703 * All panels that supports PSR version 03h (PSR2 + 704 * Y-coordinate) can handle Y-coordinates in VSC but we are 705 * only sure that it is going to be used when required by the 706 * panel. This way panel is capable to do selective update 707 * without a aux frame sync. 708 * 709 * To support PSR version 02h and PSR version 03h without 710 * Y-coordinate requirement panels we would need to enable 711 * GTC first. 712 */ 713 connector->dp.psr_caps.su_support = y_req && 714 intel_alpm_aux_wake_supported(intel_dp); 715 drm_dbg_kms(display->drm, "PSR2 %ssupported\n", 716 connector->dp.psr_caps.su_support ? "" : "not "); 717 } 718 719 if (connector->dp.psr_caps.su_support) 720 _psr_compute_su_granularity(intel_dp, connector); 721 } 722 723 void intel_psr_init_dpcd(struct intel_dp *intel_dp, struct intel_connector *connector) 724 { 725 _psr_init_dpcd(intel_dp, connector); 726 727 _panel_replay_init_dpcd(intel_dp, connector); 728 } 729 730 static void hsw_psr_setup_aux(struct intel_dp *intel_dp) 731 { 732 struct intel_display *display = to_intel_display(intel_dp); 733 enum transcoder cpu_transcoder = intel_dp->psr.transcoder; 734 u32 aux_clock_divider, aux_ctl; 735 /* write DP_SET_POWER=D0 */ 736 static const u8 aux_msg[] = { 737 [0] = (DP_AUX_NATIVE_WRITE << 4) | ((DP_SET_POWER >> 16) & 0xf), 738 [1] = (DP_SET_POWER >> 8) & 0xff, 739 [2] = DP_SET_POWER & 0xff, 740 [3] = 1 - 1, 741 [4] = DP_SET_POWER_D0, 742 }; 743 int i; 744 745 BUILD_BUG_ON(sizeof(aux_msg) > 20); 746 for (i = 0; i < sizeof(aux_msg); i += 4) 747 intel_de_write(display, 748 psr_aux_data_reg(display, cpu_transcoder, i >> 2), 749 intel_dp_aux_pack(&aux_msg[i], sizeof(aux_msg) - i)); 750 751 aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, 0); 752 753 /* Start with bits set for DDI_AUX_CTL register */ 754 aux_ctl = intel_dp->get_aux_send_ctl(intel_dp, sizeof(aux_msg), 755 aux_clock_divider); 756 757 /* Select only valid bits for SRD_AUX_CTL */ 758 aux_ctl &= EDP_PSR_AUX_CTL_TIME_OUT_MASK | 759 EDP_PSR_AUX_CTL_MESSAGE_SIZE_MASK | 760 EDP_PSR_AUX_CTL_PRECHARGE_2US_MASK | 761 EDP_PSR_AUX_CTL_BIT_CLOCK_2X_MASK; 762 763 intel_de_write(display, psr_aux_ctl_reg(display, cpu_transcoder), 764 aux_ctl); 765 } 766 767 static bool psr2_su_region_et_valid(struct intel_connector *connector, bool panel_replay) 768 { 769 struct intel_dp *intel_dp = intel_attached_dp(connector); 770 struct intel_display *display = to_intel_display(intel_dp); 771 772 if (DISPLAY_VER(display) < 20 || !intel_dp_is_edp(intel_dp) || 773 intel_dp->psr.debug & I915_PSR_DEBUG_SU_REGION_ET_DISABLE) 774 return false; 775 776 return panel_replay ? 777 connector->dp.panel_replay_caps.dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_SUPPORT)] & 778 DP_PANEL_REPLAY_EARLY_TRANSPORT_SUPPORT : 779 connector->dp.psr_caps.dpcd[0] == DP_PSR2_WITH_Y_COORD_ET_SUPPORTED; 780 } 781 782 static void _panel_replay_enable_sink(struct intel_dp *intel_dp, 783 const struct intel_crtc_state *crtc_state) 784 { 785 u8 val = DP_PANEL_REPLAY_ENABLE | 786 DP_PANEL_REPLAY_VSC_SDP_CRC_EN | 787 DP_PANEL_REPLAY_UNRECOVERABLE_ERROR_EN | 788 DP_PANEL_REPLAY_RFB_STORAGE_ERROR_EN | 789 DP_PANEL_REPLAY_ACTIVE_FRAME_CRC_ERROR_EN; 790 u8 panel_replay_config2 = DP_PANEL_REPLAY_CRC_VERIFICATION; 791 792 if (crtc_state->has_sel_update) 793 val |= DP_PANEL_REPLAY_SU_ENABLE; 794 795 if (crtc_state->enable_psr2_su_region_et) 796 val |= DP_PANEL_REPLAY_ENABLE_SU_REGION_ET; 797 798 if (crtc_state->req_psr2_sdp_prior_scanline) 799 panel_replay_config2 |= 800 DP_PANEL_REPLAY_SU_REGION_SCANLINE_CAPTURE; 801 802 drm_dp_dpcd_writeb(&intel_dp->aux, PANEL_REPLAY_CONFIG, val); 803 804 drm_dp_dpcd_writeb(&intel_dp->aux, PANEL_REPLAY_CONFIG2, 805 panel_replay_config2); 806 } 807 808 static void _psr_enable_sink(struct intel_dp *intel_dp, 809 const struct intel_crtc_state *crtc_state) 810 { 811 struct intel_display *display = to_intel_display(intel_dp); 812 u8 val = 0; 813 814 if (crtc_state->has_sel_update) { 815 val |= DP_PSR_ENABLE_PSR2 | DP_PSR_IRQ_HPD_WITH_CRC_ERRORS; 816 } else { 817 if (intel_dp->psr.link_standby) 818 val |= DP_PSR_MAIN_LINK_ACTIVE; 819 820 if (DISPLAY_VER(display) >= 8) 821 val |= DP_PSR_CRC_VERIFICATION; 822 } 823 824 if (crtc_state->req_psr2_sdp_prior_scanline) 825 val |= DP_PSR_SU_REGION_SCANLINE_CAPTURE; 826 827 if (crtc_state->enable_psr2_su_region_et) 828 val |= DP_PANEL_REPLAY_ENABLE_SU_REGION_ET; 829 830 if (intel_dp->psr.entry_setup_frames > 0) 831 val |= DP_PSR_FRAME_CAPTURE; 832 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, val); 833 834 val |= DP_PSR_ENABLE; 835 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, val); 836 } 837 838 static void intel_psr_enable_sink(struct intel_dp *intel_dp, 839 const struct intel_crtc_state *crtc_state) 840 { 841 intel_alpm_enable_sink(intel_dp, crtc_state); 842 843 crtc_state->has_panel_replay ? 844 _panel_replay_enable_sink(intel_dp, crtc_state) : 845 _psr_enable_sink(intel_dp, crtc_state); 846 847 if (intel_dp_is_edp(intel_dp)) 848 drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, DP_SET_POWER_D0); 849 } 850 851 void intel_psr_panel_replay_enable_sink(struct intel_dp *intel_dp) 852 { 853 /* 854 * NOTE: We might want to trigger mode set when 855 * disabling/enabling Panel Replay via debugfs interface to 856 * ensure this bit is cleared/set accordingly. 857 */ 858 if (CAN_PANEL_REPLAY(intel_dp) && panel_replay_global_enabled(intel_dp)) 859 drm_dp_dpcd_writeb(&intel_dp->aux, PANEL_REPLAY_CONFIG, 860 DP_PANEL_REPLAY_ENABLE); 861 } 862 863 static u32 intel_psr1_get_tp_time(struct intel_dp *intel_dp) 864 { 865 struct intel_display *display = to_intel_display(intel_dp); 866 struct intel_connector *connector = intel_dp->attached_connector; 867 u32 val = 0; 868 869 if (DISPLAY_VER(display) >= 11) 870 val |= EDP_PSR_TP4_TIME_0us; 871 872 if (display->params.psr_safest_params) { 873 val |= EDP_PSR_TP1_TIME_2500us; 874 val |= EDP_PSR_TP2_TP3_TIME_2500us; 875 goto check_tp3_sel; 876 } 877 878 if (connector->panel.vbt.psr.tp1_wakeup_time_us == 0) 879 val |= EDP_PSR_TP1_TIME_0us; 880 else if (connector->panel.vbt.psr.tp1_wakeup_time_us <= 100) 881 val |= EDP_PSR_TP1_TIME_100us; 882 else if (connector->panel.vbt.psr.tp1_wakeup_time_us <= 500) 883 val |= EDP_PSR_TP1_TIME_500us; 884 else 885 val |= EDP_PSR_TP1_TIME_2500us; 886 887 if (connector->panel.vbt.psr.tp2_tp3_wakeup_time_us == 0) 888 val |= EDP_PSR_TP2_TP3_TIME_0us; 889 else if (connector->panel.vbt.psr.tp2_tp3_wakeup_time_us <= 100) 890 val |= EDP_PSR_TP2_TP3_TIME_100us; 891 else if (connector->panel.vbt.psr.tp2_tp3_wakeup_time_us <= 500) 892 val |= EDP_PSR_TP2_TP3_TIME_500us; 893 else 894 val |= EDP_PSR_TP2_TP3_TIME_2500us; 895 896 /* 897 * WA 0479: hsw,bdw 898 * "Do not skip both TP1 and TP2/TP3" 899 */ 900 if (DISPLAY_VER(display) < 9 && 901 connector->panel.vbt.psr.tp1_wakeup_time_us == 0 && 902 connector->panel.vbt.psr.tp2_tp3_wakeup_time_us == 0) 903 val |= EDP_PSR_TP2_TP3_TIME_100us; 904 905 check_tp3_sel: 906 if (intel_dp_source_supports_tps3(display) && 907 drm_dp_tps3_supported(intel_dp->dpcd)) 908 val |= EDP_PSR_TP_TP1_TP3; 909 else 910 val |= EDP_PSR_TP_TP1_TP2; 911 912 return val; 913 } 914 915 static u8 psr_compute_idle_frames(struct intel_dp *intel_dp) 916 { 917 struct intel_display *display = to_intel_display(intel_dp); 918 struct intel_connector *connector = intel_dp->attached_connector; 919 int idle_frames; 920 921 /* Let's use 6 as the minimum to cover all known cases including the 922 * off-by-one issue that HW has in some cases. 923 */ 924 idle_frames = max(6, connector->panel.vbt.psr.idle_frames); 925 idle_frames = max(idle_frames, connector->dp.psr_caps.sync_latency + 1); 926 927 if (drm_WARN_ON(display->drm, idle_frames > 0xf)) 928 idle_frames = 0xf; 929 930 return idle_frames; 931 } 932 933 static bool is_dc5_dc6_blocked(struct intel_dp *intel_dp) 934 { 935 struct intel_display *display = to_intel_display(intel_dp); 936 u32 current_dc_state = intel_display_power_get_current_dc_state(display); 937 struct intel_crtc *crtc = intel_crtc_for_pipe(display, intel_dp->psr.pipe); 938 struct drm_vblank_crtc *vblank = drm_crtc_vblank_crtc(&crtc->base); 939 940 return (current_dc_state != DC_STATE_EN_UPTO_DC5 && 941 current_dc_state != DC_STATE_EN_UPTO_DC6) || 942 intel_dp->psr.active_non_psr_pipes || 943 READ_ONCE(vblank->enabled); 944 } 945 946 static void hsw_activate_psr1(struct intel_dp *intel_dp) 947 { 948 struct intel_display *display = to_intel_display(intel_dp); 949 enum transcoder cpu_transcoder = intel_dp->psr.transcoder; 950 u32 max_sleep_time = 0x1f; 951 u32 val = EDP_PSR_ENABLE; 952 953 val |= EDP_PSR_IDLE_FRAMES(psr_compute_idle_frames(intel_dp)); 954 955 if (DISPLAY_VER(display) < 20) 956 val |= EDP_PSR_MAX_SLEEP_TIME(max_sleep_time); 957 958 if (display->platform.haswell) 959 val |= EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES; 960 961 if (intel_dp->psr.link_standby) 962 val |= EDP_PSR_LINK_STANDBY; 963 964 val |= intel_psr1_get_tp_time(intel_dp); 965 966 if (DISPLAY_VER(display) >= 8) 967 val |= EDP_PSR_CRC_ENABLE; 968 969 if (DISPLAY_VER(display) >= 20) 970 val |= LNL_EDP_PSR_ENTRY_SETUP_FRAMES(intel_dp->psr.entry_setup_frames); 971 972 intel_de_rmw(display, psr_ctl_reg(display, cpu_transcoder), 973 ~EDP_PSR_RESTORE_PSR_ACTIVE_CTX_MASK, val); 974 975 /* Wa_16025596647 */ 976 if ((DISPLAY_VER(display) == 20 || 977 IS_DISPLAY_VERx100_STEP(display, 3000, STEP_A0, STEP_B0)) && 978 is_dc5_dc6_blocked(intel_dp) && intel_dp->psr.pkg_c_latency_used) 979 intel_dmc_start_pkgc_exit_at_start_of_undelayed_vblank(display, 980 intel_dp->psr.pipe, 981 true); 982 } 983 984 static u32 intel_psr2_get_tp_time(struct intel_dp *intel_dp) 985 { 986 struct intel_display *display = to_intel_display(intel_dp); 987 struct intel_connector *connector = intel_dp->attached_connector; 988 u32 val = 0; 989 990 if (display->params.psr_safest_params) 991 return EDP_PSR2_TP2_TIME_2500us; 992 993 if (connector->panel.vbt.psr.psr2_tp2_tp3_wakeup_time_us >= 0 && 994 connector->panel.vbt.psr.psr2_tp2_tp3_wakeup_time_us <= 50) 995 val |= EDP_PSR2_TP2_TIME_50us; 996 else if (connector->panel.vbt.psr.psr2_tp2_tp3_wakeup_time_us <= 100) 997 val |= EDP_PSR2_TP2_TIME_100us; 998 else if (connector->panel.vbt.psr.psr2_tp2_tp3_wakeup_time_us <= 500) 999 val |= EDP_PSR2_TP2_TIME_500us; 1000 else 1001 val |= EDP_PSR2_TP2_TIME_2500us; 1002 1003 return val; 1004 } 1005 1006 static int 1007 psr2_block_count_lines(u8 io_wake_lines, u8 fast_wake_lines) 1008 { 1009 return io_wake_lines < 9 && fast_wake_lines < 9 ? 8 : 12; 1010 } 1011 1012 static int psr2_block_count(struct intel_dp *intel_dp) 1013 { 1014 return psr2_block_count_lines(intel_dp->psr.io_wake_lines, 1015 intel_dp->psr.fast_wake_lines) / 4; 1016 } 1017 1018 static u8 frames_before_su_entry(struct intel_dp *intel_dp) 1019 { 1020 struct intel_connector *connector = intel_dp->attached_connector; 1021 u8 frames_before_su_entry; 1022 1023 frames_before_su_entry = max_t(u8, 1024 connector->dp.psr_caps.sync_latency + 1, 1025 2); 1026 1027 /* Entry setup frames must be at least 1 less than frames before SU entry */ 1028 if (intel_dp->psr.entry_setup_frames >= frames_before_su_entry) 1029 frames_before_su_entry = intel_dp->psr.entry_setup_frames + 1; 1030 1031 return frames_before_su_entry; 1032 } 1033 1034 static void dg2_activate_panel_replay(struct intel_dp *intel_dp) 1035 { 1036 struct intel_display *display = to_intel_display(intel_dp); 1037 struct intel_psr *psr = &intel_dp->psr; 1038 enum transcoder cpu_transcoder = intel_dp->psr.transcoder; 1039 1040 if (intel_dp_is_edp(intel_dp) && psr->sel_update_enabled) { 1041 u32 val = psr->su_region_et_enabled ? 1042 LNL_EDP_PSR2_SU_REGION_ET_ENABLE : 0; 1043 1044 if (intel_dp->psr.req_psr2_sdp_prior_scanline) 1045 val |= EDP_PSR2_SU_SDP_SCANLINE; 1046 1047 intel_de_write(display, EDP_PSR2_CTL(display, cpu_transcoder), 1048 val); 1049 } 1050 1051 intel_de_rmw(display, 1052 PSR2_MAN_TRK_CTL(display, intel_dp->psr.transcoder), 1053 0, ADLP_PSR2_MAN_TRK_CTL_SF_CONTINUOS_FULL_FRAME); 1054 1055 intel_de_rmw(display, TRANS_DP2_CTL(intel_dp->psr.transcoder), 0, 1056 TRANS_DP2_PANEL_REPLAY_ENABLE); 1057 } 1058 1059 static void hsw_activate_psr2(struct intel_dp *intel_dp) 1060 { 1061 struct intel_display *display = to_intel_display(intel_dp); 1062 enum transcoder cpu_transcoder = intel_dp->psr.transcoder; 1063 u32 val = EDP_PSR2_ENABLE; 1064 u32 psr_val = 0; 1065 u8 idle_frames; 1066 1067 /* Wa_16025596647 */ 1068 if ((DISPLAY_VER(display) == 20 || 1069 IS_DISPLAY_VERx100_STEP(display, 3000, STEP_A0, STEP_B0)) && 1070 is_dc5_dc6_blocked(intel_dp) && intel_dp->psr.pkg_c_latency_used) 1071 idle_frames = 0; 1072 else 1073 idle_frames = psr_compute_idle_frames(intel_dp); 1074 val |= EDP_PSR2_IDLE_FRAMES(idle_frames); 1075 1076 if (DISPLAY_VER(display) < 14 && !display->platform.alderlake_p) 1077 val |= EDP_SU_TRACK_ENABLE; 1078 1079 if (DISPLAY_VER(display) >= 10 && DISPLAY_VER(display) < 13) 1080 val |= EDP_Y_COORDINATE_ENABLE; 1081 1082 val |= EDP_PSR2_FRAME_BEFORE_SU(frames_before_su_entry(intel_dp)); 1083 1084 val |= intel_psr2_get_tp_time(intel_dp); 1085 1086 if (DISPLAY_VER(display) >= 12 && DISPLAY_VER(display) < 20) { 1087 if (psr2_block_count(intel_dp) > 2) 1088 val |= TGL_EDP_PSR2_BLOCK_COUNT_NUM_3; 1089 else 1090 val |= TGL_EDP_PSR2_BLOCK_COUNT_NUM_2; 1091 } 1092 1093 /* Wa_22012278275:adl-p */ 1094 if (intel_display_wa(display, INTEL_DISPLAY_WA_22012278275)) { 1095 static const u8 map[] = { 1096 2, /* 5 lines */ 1097 1, /* 6 lines */ 1098 0, /* 7 lines */ 1099 3, /* 8 lines */ 1100 6, /* 9 lines */ 1101 5, /* 10 lines */ 1102 4, /* 11 lines */ 1103 7, /* 12 lines */ 1104 }; 1105 /* 1106 * Still using the default IO_BUFFER_WAKE and FAST_WAKE, see 1107 * comments below for more information 1108 */ 1109 int tmp; 1110 1111 tmp = map[intel_dp->psr.io_wake_lines - 1112 TGL_EDP_PSR2_IO_BUFFER_WAKE_MIN_LINES]; 1113 val |= TGL_EDP_PSR2_IO_BUFFER_WAKE(tmp + TGL_EDP_PSR2_IO_BUFFER_WAKE_MIN_LINES); 1114 1115 tmp = map[intel_dp->psr.fast_wake_lines - TGL_EDP_PSR2_FAST_WAKE_MIN_LINES]; 1116 val |= TGL_EDP_PSR2_FAST_WAKE(tmp + TGL_EDP_PSR2_FAST_WAKE_MIN_LINES); 1117 } else if (DISPLAY_VER(display) >= 20) { 1118 val |= LNL_EDP_PSR2_IO_BUFFER_WAKE(intel_dp->psr.io_wake_lines); 1119 } else if (DISPLAY_VER(display) >= 12) { 1120 val |= TGL_EDP_PSR2_IO_BUFFER_WAKE(intel_dp->psr.io_wake_lines); 1121 val |= TGL_EDP_PSR2_FAST_WAKE(intel_dp->psr.fast_wake_lines); 1122 } else if (DISPLAY_VER(display) >= 9) { 1123 val |= EDP_PSR2_IO_BUFFER_WAKE(intel_dp->psr.io_wake_lines); 1124 val |= EDP_PSR2_FAST_WAKE(intel_dp->psr.fast_wake_lines); 1125 } 1126 1127 if (intel_dp->psr.req_psr2_sdp_prior_scanline) 1128 val |= EDP_PSR2_SU_SDP_SCANLINE; 1129 1130 if (DISPLAY_VER(display) >= 20) 1131 psr_val |= LNL_EDP_PSR_ENTRY_SETUP_FRAMES(intel_dp->psr.entry_setup_frames); 1132 1133 if (intel_dp->psr.psr2_sel_fetch_enabled) { 1134 u32 tmp; 1135 1136 tmp = intel_de_read(display, 1137 PSR2_MAN_TRK_CTL(display, cpu_transcoder)); 1138 drm_WARN_ON(display->drm, !(tmp & PSR2_MAN_TRK_CTL_ENABLE)); 1139 } else if (HAS_PSR2_SEL_FETCH(display)) { 1140 intel_de_write(display, 1141 PSR2_MAN_TRK_CTL(display, cpu_transcoder), 0); 1142 } 1143 1144 if (intel_dp->psr.su_region_et_enabled) 1145 val |= LNL_EDP_PSR2_SU_REGION_ET_ENABLE; 1146 1147 /* 1148 * PSR2 HW is incorrectly using EDP_PSR_TP1_TP3_SEL and BSpec is 1149 * recommending keep this bit unset while PSR2 is enabled. 1150 */ 1151 intel_de_write(display, psr_ctl_reg(display, cpu_transcoder), psr_val); 1152 1153 intel_de_write(display, EDP_PSR2_CTL(display, cpu_transcoder), val); 1154 } 1155 1156 static bool 1157 transcoder_has_psr2(struct intel_display *display, enum transcoder cpu_transcoder) 1158 { 1159 if (display->platform.alderlake_p || DISPLAY_VER(display) >= 14) 1160 return cpu_transcoder == TRANSCODER_A || cpu_transcoder == TRANSCODER_B; 1161 else if (DISPLAY_VER(display) >= 12) 1162 return cpu_transcoder == TRANSCODER_A; 1163 else if (DISPLAY_VER(display) >= 9) 1164 return cpu_transcoder == TRANSCODER_EDP; 1165 else 1166 return false; 1167 } 1168 1169 static u32 intel_get_frame_time_us(const struct intel_crtc_state *crtc_state) 1170 { 1171 if (!crtc_state->hw.active) 1172 return 0; 1173 1174 return DIV_ROUND_UP(1000 * 1000, 1175 drm_mode_vrefresh(&crtc_state->hw.adjusted_mode)); 1176 } 1177 1178 static void psr2_program_idle_frames(struct intel_dp *intel_dp, 1179 u32 idle_frames) 1180 { 1181 struct intel_display *display = to_intel_display(intel_dp); 1182 enum transcoder cpu_transcoder = intel_dp->psr.transcoder; 1183 1184 intel_de_rmw(display, EDP_PSR2_CTL(display, cpu_transcoder), 1185 EDP_PSR2_IDLE_FRAMES_MASK, 1186 EDP_PSR2_IDLE_FRAMES(idle_frames)); 1187 } 1188 1189 static void tgl_psr2_enable_dc3co(struct intel_dp *intel_dp) 1190 { 1191 struct intel_display *display = to_intel_display(intel_dp); 1192 1193 psr2_program_idle_frames(intel_dp, 0); 1194 intel_display_power_set_target_dc_state(display, DC_STATE_EN_DC3CO); 1195 } 1196 1197 static void tgl_psr2_disable_dc3co(struct intel_dp *intel_dp) 1198 { 1199 struct intel_display *display = to_intel_display(intel_dp); 1200 1201 intel_display_power_set_target_dc_state(display, DC_STATE_EN_UPTO_DC6); 1202 psr2_program_idle_frames(intel_dp, psr_compute_idle_frames(intel_dp)); 1203 } 1204 1205 static void tgl_dc3co_disable_work(struct work_struct *work) 1206 { 1207 struct intel_dp *intel_dp = 1208 container_of(work, typeof(*intel_dp), psr.dc3co_work.work); 1209 1210 mutex_lock(&intel_dp->psr.lock); 1211 /* If delayed work is pending, it is not idle */ 1212 if (delayed_work_pending(&intel_dp->psr.dc3co_work)) 1213 goto unlock; 1214 1215 tgl_psr2_disable_dc3co(intel_dp); 1216 unlock: 1217 mutex_unlock(&intel_dp->psr.lock); 1218 } 1219 1220 static void tgl_disallow_dc3co_on_psr2_exit(struct intel_dp *intel_dp) 1221 { 1222 if (!intel_dp->psr.dc3co_exitline) 1223 return; 1224 1225 cancel_delayed_work(&intel_dp->psr.dc3co_work); 1226 /* Before PSR2 exit disallow dc3co*/ 1227 tgl_psr2_disable_dc3co(intel_dp); 1228 } 1229 1230 static bool 1231 dc3co_is_pipe_port_compatible(struct intel_dp *intel_dp, 1232 struct intel_crtc_state *crtc_state) 1233 { 1234 struct intel_display *display = to_intel_display(intel_dp); 1235 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 1236 enum pipe pipe = to_intel_crtc(crtc_state->uapi.crtc)->pipe; 1237 enum port port = dig_port->base.port; 1238 1239 if (display->platform.alderlake_p || DISPLAY_VER(display) >= 14) 1240 return pipe <= PIPE_B && port <= PORT_B; 1241 else 1242 return pipe == PIPE_A && port == PORT_A; 1243 } 1244 1245 static void 1246 tgl_dc3co_exitline_compute_config(struct intel_dp *intel_dp, 1247 struct intel_crtc_state *crtc_state) 1248 { 1249 struct intel_display *display = to_intel_display(intel_dp); 1250 const u32 crtc_vdisplay = crtc_state->uapi.adjusted_mode.crtc_vdisplay; 1251 struct i915_power_domains *power_domains = &display->power.domains; 1252 u32 exit_scanlines; 1253 1254 /* 1255 * FIXME: Due to the changed sequence of activating/deactivating DC3CO, 1256 * disable DC3CO until the changed dc3co activating/deactivating sequence 1257 * is applied. B.Specs:49196 1258 */ 1259 return; 1260 1261 /* 1262 * DMC's DC3CO exit mechanism has an issue with Selective Fecth 1263 * TODO: when the issue is addressed, this restriction should be removed. 1264 */ 1265 if (crtc_state->enable_psr2_sel_fetch) 1266 return; 1267 1268 if (!(power_domains->allowed_dc_mask & DC_STATE_EN_DC3CO)) 1269 return; 1270 1271 if (!dc3co_is_pipe_port_compatible(intel_dp, crtc_state)) 1272 return; 1273 1274 /* Wa_16011303918:adl-p */ 1275 if (intel_display_wa(display, INTEL_DISPLAY_WA_16011303918)) 1276 return; 1277 1278 /* 1279 * DC3CO Exit time 200us B.Spec 49196 1280 * PSR2 transcoder Early Exit scanlines = ROUNDUP(200 / line time) + 1 1281 */ 1282 exit_scanlines = 1283 intel_usecs_to_scanlines(&crtc_state->uapi.adjusted_mode, 200) + 1; 1284 1285 if (drm_WARN_ON(display->drm, exit_scanlines > crtc_vdisplay)) 1286 return; 1287 1288 crtc_state->dc3co_exitline = crtc_vdisplay - exit_scanlines; 1289 } 1290 1291 static bool intel_psr2_sel_fetch_config_valid(struct intel_dp *intel_dp, 1292 struct intel_crtc_state *crtc_state) 1293 { 1294 struct intel_display *display = to_intel_display(intel_dp); 1295 1296 if (!display->params.enable_psr2_sel_fetch && 1297 intel_dp->psr.debug != I915_PSR_DEBUG_ENABLE_SEL_FETCH) { 1298 drm_dbg_kms(display->drm, 1299 "PSR2 sel fetch not enabled, disabled by parameter\n"); 1300 return false; 1301 } 1302 1303 return crtc_state->enable_psr2_sel_fetch = true; 1304 } 1305 1306 static bool psr2_granularity_check(struct intel_crtc_state *crtc_state, 1307 struct intel_connector *connector) 1308 { 1309 struct intel_dp *intel_dp = intel_attached_dp(connector); 1310 struct intel_display *display = to_intel_display(intel_dp); 1311 const struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config; 1312 const int crtc_hdisplay = crtc_state->hw.adjusted_mode.crtc_hdisplay; 1313 const int crtc_vdisplay = crtc_state->hw.adjusted_mode.crtc_vdisplay; 1314 u16 y_granularity = 0; 1315 u16 sink_y_granularity = crtc_state->has_panel_replay ? 1316 connector->dp.panel_replay_caps.su_y_granularity : 1317 connector->dp.psr_caps.su_y_granularity; 1318 u16 sink_w_granularity; 1319 1320 if (crtc_state->has_panel_replay) 1321 sink_w_granularity = connector->dp.panel_replay_caps.su_w_granularity == 1322 DP_PANEL_REPLAY_FULL_LINE_GRANULARITY ? 1323 crtc_hdisplay : connector->dp.panel_replay_caps.su_w_granularity; 1324 else 1325 sink_w_granularity = connector->dp.psr_caps.su_w_granularity; 1326 1327 /* PSR2 HW only send full lines so we only need to validate the width */ 1328 if (crtc_hdisplay % sink_w_granularity) 1329 return false; 1330 1331 if (crtc_vdisplay % sink_y_granularity) 1332 return false; 1333 1334 /* HW tracking is only aligned to 4 lines */ 1335 if (!crtc_state->enable_psr2_sel_fetch) 1336 return sink_y_granularity == 4; 1337 1338 /* 1339 * adl_p and mtl platforms have 1 line granularity. 1340 * For other platforms with SW tracking we can adjust the y coordinates 1341 * to match sink requirement if multiple of 4. 1342 */ 1343 if (display->platform.alderlake_p || DISPLAY_VER(display) >= 14) 1344 y_granularity = sink_y_granularity; 1345 else if (sink_y_granularity <= 2) 1346 y_granularity = 4; 1347 else if ((sink_y_granularity % 4) == 0) 1348 y_granularity = sink_y_granularity; 1349 1350 if (y_granularity == 0 || crtc_vdisplay % y_granularity) 1351 return false; 1352 1353 if (crtc_state->dsc.compression_enable && 1354 vdsc_cfg->slice_height % y_granularity) 1355 return false; 1356 1357 crtc_state->su_y_granularity = y_granularity; 1358 return true; 1359 } 1360 1361 static bool _compute_psr2_sdp_prior_scanline_indication(struct intel_dp *intel_dp, 1362 struct intel_crtc_state *crtc_state) 1363 { 1364 struct intel_display *display = to_intel_display(intel_dp); 1365 const struct drm_display_mode *adjusted_mode = &crtc_state->uapi.adjusted_mode; 1366 u32 hblank_total, hblank_ns, req_ns; 1367 1368 hblank_total = adjusted_mode->crtc_hblank_end - adjusted_mode->crtc_hblank_start; 1369 hblank_ns = div_u64(1000000ULL * hblank_total, adjusted_mode->crtc_clock); 1370 1371 /* From spec: ((60 / number of lanes) + 11) * 1000 / symbol clock frequency MHz */ 1372 req_ns = ((60 / crtc_state->lane_count) + 11) * 1000 / (crtc_state->port_clock / 1000); 1373 1374 if ((hblank_ns - req_ns) > 100) 1375 return true; 1376 1377 /* Not supported <13 / Wa_22012279113:adl-p */ 1378 if (DISPLAY_VER(display) < 14 || intel_dp->edp_dpcd[0] < DP_EDP_14b) 1379 return false; 1380 1381 crtc_state->req_psr2_sdp_prior_scanline = true; 1382 return true; 1383 } 1384 1385 static int intel_psr_entry_setup_frames(struct intel_dp *intel_dp, 1386 struct drm_connector_state *conn_state, 1387 const struct drm_display_mode *adjusted_mode) 1388 { 1389 struct intel_display *display = to_intel_display(intel_dp); 1390 struct intel_connector *connector = to_intel_connector(conn_state->connector); 1391 int psr_setup_time = drm_dp_psr_setup_time(connector->dp.psr_caps.dpcd); 1392 int entry_setup_frames = 0; 1393 1394 if (psr_setup_time < 0) { 1395 drm_dbg_kms(display->drm, 1396 "PSR condition failed: Invalid PSR setup time (0x%02x)\n", 1397 connector->dp.psr_caps.dpcd[1]); 1398 return -ETIME; 1399 } 1400 1401 if (intel_usecs_to_scanlines(adjusted_mode, psr_setup_time) > 1402 adjusted_mode->crtc_vtotal - adjusted_mode->crtc_vdisplay - 1) { 1403 if (DISPLAY_VER(display) >= 20) { 1404 /* setup entry frames can be up to 3 frames */ 1405 entry_setup_frames = 1; 1406 drm_dbg_kms(display->drm, 1407 "PSR setup entry frames %d\n", 1408 entry_setup_frames); 1409 } else { 1410 drm_dbg_kms(display->drm, 1411 "PSR condition failed: PSR setup time (%d us) too long\n", 1412 psr_setup_time); 1413 return -ETIME; 1414 } 1415 } 1416 1417 return entry_setup_frames; 1418 } 1419 1420 static 1421 int _intel_psr_min_set_context_latency(const struct intel_crtc_state *crtc_state, 1422 bool needs_panel_replay, 1423 bool needs_sel_update) 1424 { 1425 struct intel_display *display = to_intel_display(crtc_state); 1426 1427 if (!crtc_state->has_psr) 1428 return 0; 1429 1430 /* Wa_14015401596 */ 1431 if (intel_vrr_possible(crtc_state) && IS_DISPLAY_VER(display, 13, 14)) 1432 return 1; 1433 1434 /* Rest is for SRD_STATUS needed on LunarLake and onwards */ 1435 if (DISPLAY_VER(display) < 20) 1436 return 0; 1437 1438 /* 1439 * Comment on SRD_STATUS register in Bspec for LunarLake and onwards: 1440 * 1441 * To deterministically capture the transition of the state machine 1442 * going from SRDOFFACK to IDLE, the delayed V. Blank should be at least 1443 * one line after the non-delayed V. Blank. 1444 * 1445 * Legacy TG: TRANS_SET_CONTEXT_LATENCY > 0 1446 * VRR TG: TRANS_VRR_CTL[ VRR Guardband ] < (TRANS_VRR_VMAX[ VRR Vmax ] 1447 * - TRANS_VTOTAL[ Vertical Active ]) 1448 * 1449 * SRD_STATUS is used only by PSR1 on PantherLake. 1450 * SRD_STATUS is used by PSR1 and Panel Replay DP on LunarLake. 1451 */ 1452 1453 if (DISPLAY_VER(display) >= 30 && (needs_panel_replay || 1454 needs_sel_update)) 1455 return 0; 1456 else if (DISPLAY_VER(display) < 30 && (needs_sel_update || 1457 intel_crtc_has_type(crtc_state, 1458 INTEL_OUTPUT_EDP))) 1459 return 0; 1460 else 1461 return 1; 1462 } 1463 1464 static bool _wake_lines_fit_into_vblank(const struct intel_crtc_state *crtc_state, 1465 int vblank, 1466 int wake_lines) 1467 { 1468 if (crtc_state->req_psr2_sdp_prior_scanline) 1469 vblank -= 1; 1470 1471 /* Vblank >= PSR2_CTL Block Count Number maximum line count */ 1472 if (vblank < wake_lines) 1473 return false; 1474 1475 return true; 1476 } 1477 1478 static bool wake_lines_fit_into_vblank(struct intel_dp *intel_dp, 1479 const struct intel_crtc_state *crtc_state, 1480 bool aux_less, 1481 bool needs_panel_replay, 1482 bool needs_sel_update) 1483 { 1484 struct intel_display *display = to_intel_display(intel_dp); 1485 int vblank = crtc_state->hw.adjusted_mode.crtc_vblank_end - 1486 crtc_state->hw.adjusted_mode.crtc_vblank_start; 1487 int wake_lines; 1488 int scl = _intel_psr_min_set_context_latency(crtc_state, 1489 needs_panel_replay, 1490 needs_sel_update); 1491 vblank -= scl; 1492 1493 if (aux_less) 1494 wake_lines = crtc_state->alpm_state.aux_less_wake_lines; 1495 else 1496 wake_lines = DISPLAY_VER(display) < 20 ? 1497 psr2_block_count_lines(crtc_state->alpm_state.io_wake_lines, 1498 crtc_state->alpm_state.fast_wake_lines) : 1499 crtc_state->alpm_state.io_wake_lines; 1500 1501 /* 1502 * Guardband has not been computed yet, so we conservatively check if the 1503 * full vblank duration is sufficient to accommodate wake line requirements 1504 * for PSR features like Panel Replay and Selective Update. 1505 * 1506 * Once the actual guardband is available, a more accurate validation is 1507 * performed in intel_psr_compute_config_late(), and PSR features are 1508 * disabled if wake lines exceed the available guardband. 1509 */ 1510 return _wake_lines_fit_into_vblank(crtc_state, vblank, wake_lines); 1511 } 1512 1513 static bool alpm_config_valid(struct intel_dp *intel_dp, 1514 struct intel_crtc_state *crtc_state, 1515 bool aux_less, 1516 bool needs_panel_replay, 1517 bool needs_sel_update) 1518 { 1519 struct intel_display *display = to_intel_display(intel_dp); 1520 1521 if (!intel_alpm_compute_params(intel_dp, crtc_state)) { 1522 drm_dbg_kms(display->drm, 1523 "PSR2/Panel Replay not enabled, Unable to use long enough wake times\n"); 1524 return false; 1525 } 1526 1527 if (!wake_lines_fit_into_vblank(intel_dp, crtc_state, aux_less, 1528 needs_panel_replay, needs_sel_update)) { 1529 drm_dbg_kms(display->drm, 1530 "PSR2/Panel Replay not enabled, too short vblank time\n"); 1531 return false; 1532 } 1533 1534 return true; 1535 } 1536 1537 static bool intel_psr2_config_valid(struct intel_dp *intel_dp, 1538 struct intel_crtc_state *crtc_state, 1539 struct drm_connector_state *conn_state) 1540 { 1541 struct intel_display *display = to_intel_display(intel_dp); 1542 struct intel_connector *connector = to_intel_connector(conn_state->connector); 1543 int crtc_hdisplay = crtc_state->hw.adjusted_mode.crtc_hdisplay; 1544 int crtc_vdisplay = crtc_state->hw.adjusted_mode.crtc_vdisplay; 1545 int psr_max_h = 0, psr_max_v = 0, max_bpp = 0; 1546 1547 if (!connector->dp.psr_caps.su_support || display->params.enable_psr == 1) 1548 return false; 1549 1550 /* JSL and EHL only supports eDP 1.3 */ 1551 if (display->platform.jasperlake || display->platform.elkhartlake) { 1552 drm_dbg_kms(display->drm, "PSR2 not supported by phy\n"); 1553 return false; 1554 } 1555 1556 /* Wa_16011181250 */ 1557 if (intel_display_wa(display, INTEL_DISPLAY_WA_16011181250)) { 1558 drm_dbg_kms(display->drm, 1559 "PSR2 is defeatured for this platform\n"); 1560 return false; 1561 } 1562 1563 if (display->platform.alderlake_p && IS_DISPLAY_STEP(display, STEP_A0, STEP_B0)) { 1564 drm_dbg_kms(display->drm, 1565 "PSR2 not completely functional in this stepping\n"); 1566 return false; 1567 } 1568 1569 if (!transcoder_has_psr2(display, crtc_state->cpu_transcoder)) { 1570 drm_dbg_kms(display->drm, 1571 "PSR2 not supported in transcoder %s\n", 1572 transcoder_name(crtc_state->cpu_transcoder)); 1573 return false; 1574 } 1575 1576 /* 1577 * DSC and PSR2 cannot be enabled simultaneously. If a requested 1578 * resolution requires DSC to be enabled, priority is given to DSC 1579 * over PSR2. 1580 */ 1581 if (crtc_state->dsc.compression_enable && 1582 (DISPLAY_VER(display) < 14 && !display->platform.alderlake_p)) { 1583 drm_dbg_kms(display->drm, 1584 "PSR2 cannot be enabled since DSC is enabled\n"); 1585 return false; 1586 } 1587 1588 if (DISPLAY_VER(display) >= 20) { 1589 psr_max_h = crtc_hdisplay; 1590 psr_max_v = crtc_vdisplay; 1591 max_bpp = crtc_state->pipe_bpp; 1592 } else if (IS_DISPLAY_VER(display, 12, 14)) { 1593 psr_max_h = 5120; 1594 psr_max_v = 3200; 1595 max_bpp = 30; 1596 } else if (IS_DISPLAY_VER(display, 10, 11)) { 1597 psr_max_h = 4096; 1598 psr_max_v = 2304; 1599 max_bpp = 24; 1600 } else if (DISPLAY_VER(display) == 9) { 1601 psr_max_h = 3640; 1602 psr_max_v = 2304; 1603 max_bpp = 24; 1604 } 1605 1606 if (crtc_state->pipe_bpp > max_bpp) { 1607 drm_dbg_kms(display->drm, 1608 "PSR2 not enabled, pipe bpp %d > max supported %d\n", 1609 crtc_state->pipe_bpp, max_bpp); 1610 return false; 1611 } 1612 1613 /* Wa_16011303918:adl-p */ 1614 if (crtc_state->vrr.enable && 1615 display->platform.alderlake_p && IS_DISPLAY_STEP(display, STEP_A0, STEP_B0)) { 1616 drm_dbg_kms(display->drm, 1617 "PSR2 not enabled, not compatible with HW stepping + VRR\n"); 1618 return false; 1619 } 1620 1621 if (!alpm_config_valid(intel_dp, crtc_state, false, false, true)) 1622 return false; 1623 1624 if (!crtc_state->enable_psr2_sel_fetch && 1625 (crtc_hdisplay > psr_max_h || crtc_vdisplay > psr_max_v)) { 1626 drm_dbg_kms(display->drm, 1627 "PSR2 not enabled, resolution %dx%d > max supported %dx%d\n", 1628 crtc_hdisplay, crtc_vdisplay, 1629 psr_max_h, psr_max_v); 1630 return false; 1631 } 1632 1633 tgl_dc3co_exitline_compute_config(intel_dp, crtc_state); 1634 1635 return true; 1636 } 1637 1638 static bool intel_sel_update_config_valid(struct intel_crtc_state *crtc_state, 1639 struct drm_connector_state *conn_state) 1640 { 1641 struct intel_connector *connector = to_intel_connector(conn_state->connector); 1642 struct intel_dp *intel_dp = intel_attached_dp(connector); 1643 struct intel_display *display = to_intel_display(intel_dp); 1644 1645 if (HAS_PSR2_SEL_FETCH(display) && 1646 !intel_psr2_sel_fetch_config_valid(intel_dp, crtc_state) && 1647 !HAS_PSR_HW_TRACKING(display)) { 1648 drm_dbg_kms(display->drm, 1649 "Selective update not enabled, selective fetch not valid and no HW tracking available\n"); 1650 goto unsupported; 1651 } 1652 1653 if (!sel_update_global_enabled(intel_dp)) { 1654 drm_dbg_kms(display->drm, 1655 "Selective update disabled by flag\n"); 1656 goto unsupported; 1657 } 1658 1659 if (!crtc_state->has_panel_replay && !intel_psr2_config_valid(intel_dp, crtc_state, 1660 conn_state)) 1661 goto unsupported; 1662 1663 if (!_compute_psr2_sdp_prior_scanline_indication(intel_dp, crtc_state)) { 1664 drm_dbg_kms(display->drm, 1665 "Selective update not enabled, SDP indication do not fit in hblank\n"); 1666 goto unsupported; 1667 } 1668 1669 if (crtc_state->has_panel_replay) { 1670 if (DISPLAY_VER(display) < 14) 1671 goto unsupported; 1672 1673 if (!connector->dp.panel_replay_caps.su_support) 1674 goto unsupported; 1675 1676 if (intel_dsc_enabled_on_link(crtc_state) && 1677 connector->dp.panel_replay_caps.dsc_support != 1678 INTEL_DP_PANEL_REPLAY_DSC_SELECTIVE_UPDATE) { 1679 drm_dbg_kms(display->drm, 1680 "Selective update with Panel Replay not enabled because it's not supported with DSC\n"); 1681 goto unsupported; 1682 } 1683 } 1684 1685 if (crtc_state->crc_enabled) { 1686 drm_dbg_kms(display->drm, 1687 "Selective update not enabled because it would inhibit pipe CRC calculation\n"); 1688 goto unsupported; 1689 } 1690 1691 if (!psr2_granularity_check(crtc_state, connector)) { 1692 drm_dbg_kms(display->drm, 1693 "Selective update not enabled, SU granularity not compatible\n"); 1694 goto unsupported; 1695 } 1696 1697 crtc_state->enable_psr2_su_region_et = psr2_su_region_et_valid(connector, 1698 crtc_state->has_panel_replay); 1699 1700 return true; 1701 1702 unsupported: 1703 crtc_state->enable_psr2_sel_fetch = false; 1704 return false; 1705 } 1706 1707 static bool _psr_compute_config(struct intel_dp *intel_dp, 1708 struct intel_crtc_state *crtc_state, 1709 struct drm_connector_state *conn_state) 1710 { 1711 struct intel_display *display = to_intel_display(intel_dp); 1712 const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; 1713 int entry_setup_frames; 1714 1715 if (!CAN_PSR(intel_dp) || !display->params.enable_psr) 1716 return false; 1717 1718 /* 1719 * Currently PSR doesn't work reliably with VRR enabled. 1720 */ 1721 if (crtc_state->vrr.enable) 1722 return false; 1723 1724 entry_setup_frames = intel_psr_entry_setup_frames(intel_dp, conn_state, adjusted_mode); 1725 1726 if (entry_setup_frames >= 0) { 1727 crtc_state->entry_setup_frames = entry_setup_frames; 1728 } else { 1729 crtc_state->no_psr_reason = "PSR setup timing not met"; 1730 drm_dbg_kms(display->drm, 1731 "PSR condition failed: PSR setup timing not met\n"); 1732 return false; 1733 } 1734 1735 return true; 1736 } 1737 1738 static inline bool compute_link_off_after_as_sdp_when_pr_active(struct intel_connector *connector) 1739 { 1740 return (connector->dp.panel_replay_caps.dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_CAPABILITY)] & 1741 DP_PANEL_REPLAY_LINK_OFF_SUPPORTED_IN_PR_AFTER_ADAPTIVE_SYNC_SDP); 1742 } 1743 1744 static inline bool compute_disable_as_sdp_when_pr_active(struct intel_connector *connector) 1745 { 1746 return !(connector->dp.panel_replay_caps.dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_CAPABILITY)] & 1747 DP_PANEL_REPLAY_ASYNC_VIDEO_TIMING_NOT_SUPPORTED_IN_PR); 1748 } 1749 1750 static bool _panel_replay_compute_config(struct intel_crtc_state *crtc_state, 1751 const struct drm_connector_state *conn_state) 1752 { 1753 struct intel_connector *connector = 1754 to_intel_connector(conn_state->connector); 1755 struct intel_dp *intel_dp = intel_attached_dp(connector); 1756 struct intel_display *display = to_intel_display(intel_dp); 1757 struct intel_hdcp *hdcp = &connector->hdcp; 1758 1759 if (!CAN_PANEL_REPLAY(intel_dp)) 1760 return false; 1761 1762 if (!connector->dp.panel_replay_caps.support) 1763 return false; 1764 1765 if (!panel_replay_global_enabled(intel_dp)) { 1766 drm_dbg_kms(display->drm, "Panel Replay disabled by flag\n"); 1767 return false; 1768 } 1769 1770 if (crtc_state->crc_enabled) { 1771 drm_dbg_kms(display->drm, 1772 "Panel Replay not enabled because it would inhibit pipe CRC calculation\n"); 1773 return false; 1774 } 1775 1776 if (intel_dsc_enabled_on_link(crtc_state) && 1777 connector->dp.panel_replay_caps.dsc_support == 1778 INTEL_DP_PANEL_REPLAY_DSC_NOT_SUPPORTED) { 1779 drm_dbg_kms(display->drm, 1780 "Panel Replay not enabled because it's not supported with DSC\n"); 1781 return false; 1782 } 1783 1784 crtc_state->link_off_after_as_sdp_when_pr_active = compute_link_off_after_as_sdp_when_pr_active(connector); 1785 crtc_state->disable_as_sdp_when_pr_active = compute_disable_as_sdp_when_pr_active(connector); 1786 1787 if (!intel_dp_is_edp(intel_dp)) 1788 return true; 1789 1790 /* Remaining checks are for eDP only */ 1791 1792 if (to_intel_crtc(crtc_state->uapi.crtc)->pipe != PIPE_A && 1793 to_intel_crtc(crtc_state->uapi.crtc)->pipe != PIPE_B) 1794 return false; 1795 1796 /* 128b/132b Panel Replay is not supported on eDP */ 1797 if (intel_dp_is_uhbr(crtc_state)) { 1798 drm_dbg_kms(display->drm, 1799 "Panel Replay is not supported with 128b/132b\n"); 1800 return false; 1801 } 1802 1803 /* HW will not allow Panel Replay on eDP when HDCP enabled */ 1804 if (conn_state->content_protection == 1805 DRM_MODE_CONTENT_PROTECTION_DESIRED || 1806 (conn_state->content_protection == 1807 DRM_MODE_CONTENT_PROTECTION_ENABLED && hdcp->value == 1808 DRM_MODE_CONTENT_PROTECTION_UNDESIRED)) { 1809 drm_dbg_kms(display->drm, 1810 "Panel Replay is not supported with HDCP\n"); 1811 return false; 1812 } 1813 1814 if (!alpm_config_valid(intel_dp, crtc_state, true, true, false)) 1815 return false; 1816 1817 return true; 1818 } 1819 1820 static bool intel_psr_needs_wa_18037818876(struct intel_dp *intel_dp, 1821 struct intel_crtc_state *crtc_state) 1822 { 1823 struct intel_display *display = to_intel_display(intel_dp); 1824 1825 return (DISPLAY_VER(display) == 20 && crtc_state->entry_setup_frames > 0 && 1826 !crtc_state->has_sel_update); 1827 } 1828 1829 static 1830 void intel_psr_set_non_psr_pipes(struct intel_dp *intel_dp, 1831 struct intel_crtc_state *crtc_state) 1832 { 1833 struct intel_display *display = to_intel_display(intel_dp); 1834 struct intel_atomic_state *state = to_intel_atomic_state(crtc_state->uapi.state); 1835 struct intel_crtc *crtc; 1836 u8 active_pipes = 0; 1837 1838 /* Wa_16025596647 */ 1839 if (!intel_display_wa(display, INTEL_DISPLAY_WA_16025596647)) 1840 return; 1841 1842 /* Not needed by Panel Replay */ 1843 if (crtc_state->has_panel_replay) 1844 return; 1845 1846 /* We ignore possible secondary PSR/Panel Replay capable eDP */ 1847 for_each_intel_crtc(display->drm, crtc) 1848 active_pipes |= crtc->active ? BIT(crtc->pipe) : 0; 1849 1850 active_pipes = intel_calc_active_pipes(state, active_pipes); 1851 1852 crtc_state->active_non_psr_pipes = active_pipes & 1853 ~BIT(to_intel_crtc(crtc_state->uapi.crtc)->pipe); 1854 } 1855 1856 void intel_psr_compute_config(struct intel_dp *intel_dp, 1857 struct intel_crtc_state *crtc_state, 1858 struct drm_connector_state *conn_state) 1859 { 1860 struct intel_display *display = to_intel_display(intel_dp); 1861 struct intel_connector *connector = to_intel_connector(conn_state->connector); 1862 const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; 1863 1864 if (!psr_global_enabled(intel_dp)) { 1865 drm_dbg_kms(display->drm, "PSR disabled by flag\n"); 1866 return; 1867 } 1868 1869 if (intel_dp->psr.sink_not_reliable) { 1870 drm_dbg_kms(display->drm, 1871 "PSR sink implementation is not reliable\n"); 1872 return; 1873 } 1874 1875 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { 1876 drm_dbg_kms(display->drm, 1877 "PSR condition failed: Interlaced mode enabled\n"); 1878 return; 1879 } 1880 1881 /* 1882 * FIXME figure out what is wrong with PSR+joiner and 1883 * fix it. Presumably something related to the fact that 1884 * PSR is a transcoder level feature. 1885 */ 1886 if (crtc_state->joiner_pipes) { 1887 drm_dbg_kms(display->drm, 1888 "PSR disabled due to joiner\n"); 1889 return; 1890 } 1891 1892 /* Only used for state verification. */ 1893 crtc_state->panel_replay_dsc_support = connector->dp.panel_replay_caps.dsc_support; 1894 crtc_state->has_panel_replay = _panel_replay_compute_config(crtc_state, conn_state); 1895 1896 crtc_state->has_psr = crtc_state->has_panel_replay ? true : 1897 _psr_compute_config(intel_dp, crtc_state, conn_state); 1898 1899 if (!crtc_state->has_psr) 1900 return; 1901 1902 crtc_state->has_sel_update = intel_sel_update_config_valid(crtc_state, conn_state); 1903 } 1904 1905 void intel_psr_get_config(struct intel_encoder *encoder, 1906 struct intel_crtc_state *pipe_config) 1907 { 1908 struct intel_display *display = to_intel_display(encoder); 1909 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 1910 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; 1911 struct intel_dp *intel_dp; 1912 u32 val; 1913 1914 if (!dig_port) 1915 return; 1916 1917 intel_dp = &dig_port->dp; 1918 if (!(CAN_PSR(intel_dp) || CAN_PANEL_REPLAY(intel_dp))) 1919 return; 1920 1921 mutex_lock(&intel_dp->psr.lock); 1922 if (!intel_dp->psr.enabled) 1923 goto unlock; 1924 1925 if (intel_dp->psr.panel_replay_enabled) { 1926 pipe_config->has_psr = pipe_config->has_panel_replay = true; 1927 } else { 1928 /* 1929 * Not possible to read EDP_PSR/PSR2_CTL registers as it is 1930 * enabled/disabled because of frontbuffer tracking and others. 1931 */ 1932 pipe_config->has_psr = true; 1933 } 1934 1935 pipe_config->has_sel_update = intel_dp->psr.sel_update_enabled; 1936 pipe_config->infoframes.enable |= intel_hdmi_infoframe_enable(DP_SDP_VSC); 1937 1938 if (!intel_dp->psr.sel_update_enabled) 1939 goto unlock; 1940 1941 if (HAS_PSR2_SEL_FETCH(display)) { 1942 val = intel_de_read(display, 1943 PSR2_MAN_TRK_CTL(display, cpu_transcoder)); 1944 if (val & PSR2_MAN_TRK_CTL_ENABLE) 1945 pipe_config->enable_psr2_sel_fetch = true; 1946 } 1947 1948 pipe_config->enable_psr2_su_region_et = intel_dp->psr.su_region_et_enabled; 1949 1950 if (DISPLAY_VER(display) >= 12) { 1951 val = intel_de_read(display, 1952 TRANS_EXITLINE(display, cpu_transcoder)); 1953 pipe_config->dc3co_exitline = REG_FIELD_GET(EXITLINE_MASK, val); 1954 } 1955 unlock: 1956 mutex_unlock(&intel_dp->psr.lock); 1957 } 1958 1959 static void intel_psr_activate(struct intel_dp *intel_dp) 1960 { 1961 struct intel_display *display = to_intel_display(intel_dp); 1962 enum transcoder cpu_transcoder = intel_dp->psr.transcoder; 1963 1964 drm_WARN_ON(display->drm, 1965 transcoder_has_psr2(display, cpu_transcoder) && 1966 intel_de_read(display, EDP_PSR2_CTL(display, cpu_transcoder)) & EDP_PSR2_ENABLE); 1967 1968 drm_WARN_ON(display->drm, 1969 intel_de_read(display, psr_ctl_reg(display, cpu_transcoder)) & EDP_PSR_ENABLE); 1970 1971 drm_WARN_ON(display->drm, intel_dp->psr.active); 1972 1973 drm_WARN_ON(display->drm, !intel_dp->psr.enabled); 1974 1975 lockdep_assert_held(&intel_dp->psr.lock); 1976 1977 /* psr1, psr2 and panel-replay are mutually exclusive.*/ 1978 if (intel_dp->psr.panel_replay_enabled) 1979 dg2_activate_panel_replay(intel_dp); 1980 else if (intel_dp->psr.sel_update_enabled) 1981 hsw_activate_psr2(intel_dp); 1982 else 1983 hsw_activate_psr1(intel_dp); 1984 1985 intel_dp->psr.active = true; 1986 intel_dp->psr.no_psr_reason = NULL; 1987 } 1988 1989 /* 1990 * Wa_16013835468 1991 * Wa_14015648006 1992 */ 1993 static void wm_optimization_wa(struct intel_dp *intel_dp, 1994 const struct intel_crtc_state *crtc_state) 1995 { 1996 struct intel_display *display = to_intel_display(intel_dp); 1997 enum pipe pipe = intel_dp->psr.pipe; 1998 bool activate = false; 1999 2000 /* Wa_14015648006 */ 2001 if (IS_DISPLAY_VER(display, 11, 14) && crtc_state->wm_level_disabled) 2002 activate = true; 2003 2004 /* Wa_16013835468 */ 2005 if (DISPLAY_VER(display) == 12 && 2006 crtc_state->hw.adjusted_mode.crtc_vblank_start != 2007 crtc_state->hw.adjusted_mode.crtc_vdisplay) 2008 activate = true; 2009 2010 if (activate) 2011 intel_de_rmw(display, GEN8_CHICKEN_DCPR_1, 2012 0, LATENCY_REPORTING_REMOVED(pipe)); 2013 else 2014 intel_de_rmw(display, GEN8_CHICKEN_DCPR_1, 2015 LATENCY_REPORTING_REMOVED(pipe), 0); 2016 } 2017 2018 static void intel_psr_enable_source(struct intel_dp *intel_dp, 2019 const struct intel_crtc_state *crtc_state) 2020 { 2021 struct intel_display *display = to_intel_display(intel_dp); 2022 enum transcoder cpu_transcoder = intel_dp->psr.transcoder; 2023 u32 mask = 0; 2024 2025 /* 2026 * Only HSW and BDW have PSR AUX registers that need to be setup. 2027 * SKL+ use hardcoded values PSR AUX transactions 2028 */ 2029 if (DISPLAY_VER(display) < 9) 2030 hsw_psr_setup_aux(intel_dp); 2031 2032 /* 2033 * Per Spec: Avoid continuous PSR exit by masking MEMUP and HPD also 2034 * mask LPSP to avoid dependency on other drivers that might block 2035 * runtime_pm besides preventing other hw tracking issues now we 2036 * can rely on frontbuffer tracking. 2037 * 2038 * From bspec prior LunarLake: 2039 * Only PSR_MASK[Mask FBC modify] and PSR_MASK[Mask Hotplug] are used in 2040 * panel replay mode. 2041 * 2042 * From bspec beyod LunarLake: 2043 * Panel Replay on DP: No bits are applicable 2044 * Panel Replay on eDP: All bits are applicable 2045 */ 2046 if (DISPLAY_VER(display) < 20 || intel_dp_is_edp(intel_dp)) 2047 mask = EDP_PSR_DEBUG_MASK_HPD; 2048 2049 if (intel_dp_is_edp(intel_dp)) { 2050 mask |= EDP_PSR_DEBUG_MASK_MEMUP; 2051 2052 /* 2053 * For some unknown reason on HSW non-ULT (or at least on 2054 * Dell Latitude E6540) external displays start to flicker 2055 * when PSR is enabled on the eDP. SR/PC6 residency is much 2056 * higher than should be possible with an external display. 2057 * As a workaround leave LPSP unmasked to prevent PSR entry 2058 * when external displays are active. 2059 */ 2060 if (DISPLAY_VER(display) >= 8 || display->platform.haswell_ult) 2061 mask |= EDP_PSR_DEBUG_MASK_LPSP; 2062 2063 if (DISPLAY_VER(display) < 20) 2064 mask |= EDP_PSR_DEBUG_MASK_MAX_SLEEP; 2065 2066 /* 2067 * No separate pipe reg write mask on hsw/bdw, so have to unmask all 2068 * registers in order to keep the CURSURFLIVE tricks working :( 2069 */ 2070 if (IS_DISPLAY_VER(display, 9, 10)) 2071 mask |= EDP_PSR_DEBUG_MASK_DISP_REG_WRITE; 2072 2073 /* allow PSR with sprite enabled */ 2074 if (display->platform.haswell) 2075 mask |= EDP_PSR_DEBUG_MASK_SPRITE_ENABLE; 2076 } 2077 2078 intel_de_write(display, psr_debug_reg(display, cpu_transcoder), mask); 2079 2080 psr_irq_control(intel_dp); 2081 2082 /* 2083 * TODO: if future platforms supports DC3CO in more than one 2084 * transcoder, EXITLINE will need to be unset when disabling PSR 2085 */ 2086 if (intel_dp->psr.dc3co_exitline) 2087 intel_de_rmw(display, 2088 TRANS_EXITLINE(display, cpu_transcoder), 2089 EXITLINE_MASK, 2090 intel_dp->psr.dc3co_exitline << EXITLINE_SHIFT | EXITLINE_ENABLE); 2091 2092 if (HAS_PSR_HW_TRACKING(display) && HAS_PSR2_SEL_FETCH(display)) 2093 intel_de_rmw(display, CHICKEN_PAR1_1, IGNORE_PSR2_HW_TRACKING, 2094 intel_dp->psr.psr2_sel_fetch_enabled ? 2095 IGNORE_PSR2_HW_TRACKING : 0); 2096 2097 /* 2098 * Wa_16013835468 2099 * Wa_14015648006 2100 */ 2101 wm_optimization_wa(intel_dp, crtc_state); 2102 2103 if (intel_dp->psr.sel_update_enabled) { 2104 if (DISPLAY_VER(display) == 9) 2105 intel_de_rmw(display, CHICKEN_TRANS(display, cpu_transcoder), 0, 2106 PSR2_VSC_ENABLE_PROG_HEADER | 2107 PSR2_ADD_VERTICAL_LINE_COUNT); 2108 2109 /* 2110 * Wa_16014451276:adlp,mtl[a0,b0] 2111 * All supported adlp panels have 1-based X granularity, this may 2112 * cause issues if non-supported panels are used. 2113 */ 2114 if (!intel_dp->psr.panel_replay_enabled && 2115 (IS_DISPLAY_VERx100_STEP(display, 1400, STEP_A0, STEP_B0) || 2116 display->platform.alderlake_p)) 2117 intel_de_rmw(display, CHICKEN_TRANS(display, cpu_transcoder), 2118 0, ADLP_1_BASED_X_GRANULARITY); 2119 2120 /* Wa_16012604467:adlp,mtl[a0,b0] */ 2121 if (!intel_dp->psr.panel_replay_enabled && 2122 IS_DISPLAY_VERx100_STEP(display, 1400, STEP_A0, STEP_B0)) 2123 intel_de_rmw(display, 2124 MTL_CLKGATE_DIS_TRANS(display, cpu_transcoder), 2125 0, 2126 MTL_CLKGATE_DIS_TRANS_DMASC_GATING_DIS); 2127 else if (display->platform.alderlake_p) 2128 intel_de_rmw(display, CLKGATE_DIS_MISC, 0, 2129 CLKGATE_DIS_MISC_DMASC_GATING_DIS); 2130 } 2131 2132 /* Wa_16025596647 */ 2133 if ((DISPLAY_VER(display) == 20 || 2134 IS_DISPLAY_VERx100_STEP(display, 3000, STEP_A0, STEP_B0)) && 2135 !intel_dp->psr.panel_replay_enabled) 2136 intel_dmc_block_pkgc(display, intel_dp->psr.pipe, true); 2137 2138 intel_alpm_configure(intel_dp, crtc_state); 2139 2140 if (HAS_PSR_TRANS_PUSH_FRAME_CHANGE(display)) 2141 intel_vrr_psr_frame_change_enable(crtc_state); 2142 } 2143 2144 static bool psr_interrupt_error_check(struct intel_dp *intel_dp) 2145 { 2146 struct intel_display *display = to_intel_display(intel_dp); 2147 enum transcoder cpu_transcoder = intel_dp->psr.transcoder; 2148 u32 val; 2149 2150 if (intel_dp->psr.panel_replay_enabled) 2151 goto no_err; 2152 2153 /* 2154 * If a PSR error happened and the driver is reloaded, the EDP_PSR_IIR 2155 * will still keep the error set even after the reset done in the 2156 * irq_preinstall and irq_uninstall hooks. 2157 * And enabling in this situation cause the screen to freeze in the 2158 * first time that PSR HW tries to activate so lets keep PSR disabled 2159 * to avoid any rendering problems. 2160 */ 2161 val = intel_de_read(display, psr_iir_reg(display, cpu_transcoder)); 2162 val &= psr_irq_psr_error_bit_get(intel_dp); 2163 if (val) { 2164 intel_dp->psr.sink_not_reliable = true; 2165 drm_dbg_kms(display->drm, 2166 "PSR interruption error set, not enabling PSR\n"); 2167 return false; 2168 } 2169 2170 no_err: 2171 return true; 2172 } 2173 2174 static void intel_psr_enable_locked(struct intel_dp *intel_dp, 2175 const struct intel_crtc_state *crtc_state) 2176 { 2177 struct intel_display *display = to_intel_display(intel_dp); 2178 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 2179 u32 val; 2180 2181 drm_WARN_ON(display->drm, intel_dp->psr.enabled); 2182 2183 intel_dp->psr.sel_update_enabled = crtc_state->has_sel_update; 2184 intel_dp->psr.panel_replay_enabled = crtc_state->has_panel_replay; 2185 intel_dp->psr.busy_frontbuffer_bits = 0; 2186 intel_dp->psr.pipe = to_intel_crtc(crtc_state->uapi.crtc)->pipe; 2187 intel_dp->psr.transcoder = crtc_state->cpu_transcoder; 2188 /* DC5/DC6 requires at least 6 idle frames */ 2189 val = usecs_to_jiffies(intel_get_frame_time_us(crtc_state) * 6); 2190 intel_dp->psr.dc3co_exit_delay = val; 2191 intel_dp->psr.dc3co_exitline = crtc_state->dc3co_exitline; 2192 intel_dp->psr.psr2_sel_fetch_enabled = crtc_state->enable_psr2_sel_fetch; 2193 intel_dp->psr.su_region_et_enabled = crtc_state->enable_psr2_su_region_et; 2194 intel_dp->psr.psr2_sel_fetch_cff_enabled = false; 2195 intel_dp->psr.req_psr2_sdp_prior_scanline = 2196 crtc_state->req_psr2_sdp_prior_scanline; 2197 intel_dp->psr.active_non_psr_pipes = crtc_state->active_non_psr_pipes; 2198 intel_dp->psr.pkg_c_latency_used = crtc_state->pkg_c_latency_used; 2199 intel_dp->psr.io_wake_lines = crtc_state->alpm_state.io_wake_lines; 2200 intel_dp->psr.fast_wake_lines = crtc_state->alpm_state.fast_wake_lines; 2201 intel_dp->psr.entry_setup_frames = crtc_state->entry_setup_frames; 2202 2203 if (!psr_interrupt_error_check(intel_dp)) 2204 return; 2205 2206 if (intel_dp->psr.panel_replay_enabled) 2207 drm_dbg_kms(display->drm, "Enabling Panel Replay\n"); 2208 else 2209 drm_dbg_kms(display->drm, "Enabling PSR%s\n", 2210 intel_dp->psr.sel_update_enabled ? "2" : "1"); 2211 2212 /* 2213 * Enabling sink PSR/Panel Replay here only for PSR. Panel Replay enable 2214 * bit is already written at this point. Sink ALPM is enabled here for 2215 * PSR and Panel Replay. See 2216 * intel_psr_panel_replay_enable_sink. Modifiers/options: 2217 * - Selective Update 2218 * - Region Early Transport 2219 * - Selective Update Region Scanline Capture 2220 * - VSC_SDP_CRC 2221 * - HPD on different Errors 2222 * - CRC verification 2223 * are written for PSR and Panel Replay here. 2224 */ 2225 intel_psr_enable_sink(intel_dp, crtc_state); 2226 2227 if (intel_dp_is_edp(intel_dp)) 2228 intel_snps_phy_update_psr_power_state(&dig_port->base, true); 2229 2230 intel_psr_enable_source(intel_dp, crtc_state); 2231 intel_dp->psr.enabled = true; 2232 intel_dp->psr.pause_counter = 0; 2233 2234 /* 2235 * Link_ok is sticky and set here on PSR enable. We can assume link 2236 * training is complete as we never continue to PSR enable with 2237 * untrained link. Link_ok is kept as set until first short pulse 2238 * interrupt. This is targeted to workaround panels stating bad link 2239 * after PSR is enabled. 2240 */ 2241 intel_dp->psr.link_ok = true; 2242 2243 intel_psr_activate(intel_dp); 2244 } 2245 2246 static void intel_psr_exit(struct intel_dp *intel_dp) 2247 { 2248 struct intel_display *display = to_intel_display(intel_dp); 2249 enum transcoder cpu_transcoder = intel_dp->psr.transcoder; 2250 u32 val; 2251 2252 if (!intel_dp->psr.active) { 2253 if (transcoder_has_psr2(display, cpu_transcoder)) { 2254 val = intel_de_read(display, 2255 EDP_PSR2_CTL(display, cpu_transcoder)); 2256 drm_WARN_ON(display->drm, val & EDP_PSR2_ENABLE); 2257 } 2258 2259 val = intel_de_read(display, 2260 psr_ctl_reg(display, cpu_transcoder)); 2261 drm_WARN_ON(display->drm, val & EDP_PSR_ENABLE); 2262 2263 return; 2264 } 2265 2266 if (intel_dp->psr.panel_replay_enabled) { 2267 intel_de_rmw(display, TRANS_DP2_CTL(intel_dp->psr.transcoder), 2268 TRANS_DP2_PANEL_REPLAY_ENABLE, 0); 2269 } else if (intel_dp->psr.sel_update_enabled) { 2270 tgl_disallow_dc3co_on_psr2_exit(intel_dp); 2271 2272 val = intel_de_rmw(display, 2273 EDP_PSR2_CTL(display, cpu_transcoder), 2274 EDP_PSR2_ENABLE, 0); 2275 2276 drm_WARN_ON(display->drm, !(val & EDP_PSR2_ENABLE)); 2277 } else { 2278 if ((DISPLAY_VER(display) == 20 || 2279 IS_DISPLAY_VERx100_STEP(display, 3000, STEP_A0, STEP_B0)) && 2280 intel_dp->psr.pkg_c_latency_used) 2281 intel_dmc_start_pkgc_exit_at_start_of_undelayed_vblank(display, 2282 intel_dp->psr.pipe, 2283 false); 2284 2285 val = intel_de_rmw(display, 2286 psr_ctl_reg(display, cpu_transcoder), 2287 EDP_PSR_ENABLE, 0); 2288 2289 drm_WARN_ON(display->drm, !(val & EDP_PSR_ENABLE)); 2290 } 2291 intel_dp->psr.active = false; 2292 } 2293 2294 static void intel_psr_wait_exit_locked(struct intel_dp *intel_dp) 2295 { 2296 struct intel_display *display = to_intel_display(intel_dp); 2297 enum transcoder cpu_transcoder = intel_dp->psr.transcoder; 2298 i915_reg_t psr_status; 2299 u32 psr_status_mask; 2300 2301 if (intel_dp_is_edp(intel_dp) && (intel_dp->psr.sel_update_enabled || 2302 intel_dp->psr.panel_replay_enabled)) { 2303 psr_status = EDP_PSR2_STATUS(display, cpu_transcoder); 2304 psr_status_mask = EDP_PSR2_STATUS_STATE_MASK; 2305 } else { 2306 psr_status = psr_status_reg(display, cpu_transcoder); 2307 psr_status_mask = EDP_PSR_STATUS_STATE_MASK; 2308 } 2309 2310 /* Wait till PSR is idle */ 2311 if (intel_de_wait_for_clear_ms(display, psr_status, 2312 psr_status_mask, 2000)) 2313 drm_err(display->drm, "Timed out waiting PSR idle state\n"); 2314 } 2315 2316 static void intel_psr_disable_locked(struct intel_dp *intel_dp) 2317 { 2318 struct intel_display *display = to_intel_display(intel_dp); 2319 enum transcoder cpu_transcoder = intel_dp->psr.transcoder; 2320 2321 lockdep_assert_held(&intel_dp->psr.lock); 2322 2323 if (!intel_dp->psr.enabled) 2324 return; 2325 2326 if (intel_dp->psr.panel_replay_enabled) 2327 drm_dbg_kms(display->drm, "Disabling Panel Replay\n"); 2328 else 2329 drm_dbg_kms(display->drm, "Disabling PSR%s\n", 2330 intel_dp->psr.sel_update_enabled ? "2" : "1"); 2331 2332 intel_psr_exit(intel_dp); 2333 intel_psr_wait_exit_locked(intel_dp); 2334 2335 /* 2336 * Wa_16013835468 2337 * Wa_14015648006 2338 */ 2339 if (DISPLAY_VER(display) >= 11) 2340 intel_de_rmw(display, GEN8_CHICKEN_DCPR_1, 2341 LATENCY_REPORTING_REMOVED(intel_dp->psr.pipe), 0); 2342 2343 if (intel_dp->psr.sel_update_enabled) { 2344 /* Wa_16012604467:adlp,mtl[a0,b0] */ 2345 if (!intel_dp->psr.panel_replay_enabled && 2346 IS_DISPLAY_VERx100_STEP(display, 1400, STEP_A0, STEP_B0)) 2347 intel_de_rmw(display, 2348 MTL_CLKGATE_DIS_TRANS(display, cpu_transcoder), 2349 MTL_CLKGATE_DIS_TRANS_DMASC_GATING_DIS, 0); 2350 else if (display->platform.alderlake_p) 2351 intel_de_rmw(display, CLKGATE_DIS_MISC, 2352 CLKGATE_DIS_MISC_DMASC_GATING_DIS, 0); 2353 } 2354 2355 if (intel_dp_is_edp(intel_dp)) 2356 intel_snps_phy_update_psr_power_state(&dp_to_dig_port(intel_dp)->base, false); 2357 2358 if (intel_dp->psr.panel_replay_enabled && intel_dp_is_edp(intel_dp)) 2359 intel_alpm_disable(intel_dp); 2360 2361 /* Disable PSR on Sink */ 2362 if (!intel_dp->psr.panel_replay_enabled) { 2363 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, 0); 2364 2365 if (intel_dp->psr.sel_update_enabled) 2366 drm_dp_dpcd_writeb(&intel_dp->aux, 2367 DP_RECEIVER_ALPM_CONFIG, 0); 2368 } 2369 2370 /* Wa_16025596647 */ 2371 if ((DISPLAY_VER(display) == 20 || 2372 IS_DISPLAY_VERx100_STEP(display, 3000, STEP_A0, STEP_B0)) && 2373 !intel_dp->psr.panel_replay_enabled) 2374 intel_dmc_block_pkgc(display, intel_dp->psr.pipe, false); 2375 2376 intel_dp->psr.enabled = false; 2377 intel_dp->psr.panel_replay_enabled = false; 2378 intel_dp->psr.sel_update_enabled = false; 2379 intel_dp->psr.psr2_sel_fetch_enabled = false; 2380 intel_dp->psr.su_region_et_enabled = false; 2381 intel_dp->psr.psr2_sel_fetch_cff_enabled = false; 2382 intel_dp->psr.active_non_psr_pipes = 0; 2383 intel_dp->psr.pkg_c_latency_used = 0; 2384 } 2385 2386 /** 2387 * intel_psr_disable - Disable PSR 2388 * @intel_dp: Intel DP 2389 * @old_crtc_state: old CRTC state 2390 * 2391 * This function needs to be called before disabling pipe. 2392 */ 2393 void intel_psr_disable(struct intel_dp *intel_dp, 2394 const struct intel_crtc_state *old_crtc_state) 2395 { 2396 struct intel_display *display = to_intel_display(intel_dp); 2397 2398 if (!old_crtc_state->has_psr) 2399 return; 2400 2401 if (drm_WARN_ON(display->drm, !CAN_PSR(intel_dp) && 2402 !CAN_PANEL_REPLAY(intel_dp))) 2403 return; 2404 2405 mutex_lock(&intel_dp->psr.lock); 2406 2407 intel_psr_disable_locked(intel_dp); 2408 2409 intel_dp->psr.link_ok = false; 2410 2411 mutex_unlock(&intel_dp->psr.lock); 2412 cancel_work_sync(&intel_dp->psr.work); 2413 cancel_delayed_work_sync(&intel_dp->psr.dc3co_work); 2414 } 2415 2416 /** 2417 * intel_psr_pause - Pause PSR 2418 * @intel_dp: Intel DP 2419 * 2420 * This function need to be called after enabling psr. 2421 */ 2422 void intel_psr_pause(struct intel_dp *intel_dp) 2423 { 2424 struct intel_psr *psr = &intel_dp->psr; 2425 2426 if (!CAN_PSR(intel_dp) && !CAN_PANEL_REPLAY(intel_dp)) 2427 return; 2428 2429 mutex_lock(&psr->lock); 2430 2431 if (!psr->enabled) { 2432 mutex_unlock(&psr->lock); 2433 return; 2434 } 2435 2436 if (intel_dp->psr.pause_counter++ == 0) { 2437 intel_psr_exit(intel_dp); 2438 intel_psr_wait_exit_locked(intel_dp); 2439 } 2440 2441 mutex_unlock(&psr->lock); 2442 2443 cancel_work_sync(&psr->work); 2444 cancel_delayed_work_sync(&psr->dc3co_work); 2445 } 2446 2447 /** 2448 * intel_psr_resume - Resume PSR 2449 * @intel_dp: Intel DP 2450 * 2451 * This function need to be called after pausing psr. 2452 */ 2453 void intel_psr_resume(struct intel_dp *intel_dp) 2454 { 2455 struct intel_display *display = to_intel_display(intel_dp); 2456 struct intel_psr *psr = &intel_dp->psr; 2457 2458 if (!CAN_PSR(intel_dp) && !CAN_PANEL_REPLAY(intel_dp)) 2459 return; 2460 2461 mutex_lock(&psr->lock); 2462 2463 if (!psr->enabled) 2464 goto out; 2465 2466 if (!psr->pause_counter) { 2467 drm_warn(display->drm, "Unbalanced PSR pause/resume!\n"); 2468 goto out; 2469 } 2470 2471 if (--intel_dp->psr.pause_counter == 0) 2472 intel_psr_activate(intel_dp); 2473 2474 out: 2475 mutex_unlock(&psr->lock); 2476 } 2477 2478 /** 2479 * intel_psr_needs_vblank_notification - Check if PSR need vblank enable/disable 2480 * notification. 2481 * @crtc_state: CRTC status 2482 * 2483 * We need to block DC6 entry in case of Panel Replay as enabling VBI doesn't 2484 * prevent it in case of Panel Replay. Panel Replay switches main link off on 2485 * DC entry. This means vblank interrupts are not fired and is a problem if 2486 * user-space is polling for vblank events. Also Wa_16025596647 needs 2487 * information when vblank is enabled/disabled. 2488 */ 2489 bool intel_psr_needs_vblank_notification(const struct intel_crtc_state *crtc_state) 2490 { 2491 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2492 struct intel_display *display = to_intel_display(crtc_state); 2493 struct intel_encoder *encoder; 2494 2495 for_each_encoder_on_crtc(crtc->base.dev, &crtc->base, encoder) { 2496 struct intel_dp *intel_dp; 2497 2498 if (!intel_encoder_is_dp(encoder)) 2499 continue; 2500 2501 intel_dp = enc_to_intel_dp(encoder); 2502 2503 if (!intel_dp_is_edp(intel_dp)) 2504 continue; 2505 2506 if (CAN_PANEL_REPLAY(intel_dp)) 2507 return true; 2508 2509 if ((DISPLAY_VER(display) == 20 || 2510 IS_DISPLAY_VERx100_STEP(display, 3000, STEP_A0, STEP_B0)) && 2511 CAN_PSR(intel_dp)) 2512 return true; 2513 } 2514 2515 return false; 2516 } 2517 2518 /** 2519 * intel_psr_trigger_frame_change_event - Trigger "Frame Change" event 2520 * @dsb: DSB context 2521 * @state: the atomic state 2522 * @crtc: the CRTC 2523 * 2524 * Generate PSR "Frame Change" event. 2525 */ 2526 void intel_psr_trigger_frame_change_event(struct intel_dsb *dsb, 2527 struct intel_atomic_state *state, 2528 struct intel_crtc *crtc) 2529 { 2530 const struct intel_crtc_state *crtc_state = 2531 intel_pre_commit_crtc_state(state, crtc); 2532 struct intel_display *display = to_intel_display(crtc); 2533 2534 if (!crtc_state->has_psr || intel_psr_use_trans_push(crtc_state)) 2535 return; 2536 2537 intel_de_write_dsb(display, dsb, 2538 CURSURFLIVE(display, crtc->pipe), 0); 2539 } 2540 2541 /** 2542 * intel_psr_min_set_context_latency - Minimum 'set context latency' lines needed by PSR 2543 * @crtc_state: the crtc state 2544 * 2545 * Return minimum SCL lines/delay needed by PSR. 2546 */ 2547 int intel_psr_min_set_context_latency(const struct intel_crtc_state *crtc_state) 2548 { 2549 2550 return _intel_psr_min_set_context_latency(crtc_state, 2551 crtc_state->has_panel_replay, 2552 crtc_state->has_sel_update); 2553 } 2554 2555 static u32 man_trk_ctl_enable_bit_get(struct intel_display *display) 2556 { 2557 return display->platform.alderlake_p || DISPLAY_VER(display) >= 14 ? 0 : 2558 PSR2_MAN_TRK_CTL_ENABLE; 2559 } 2560 2561 static u32 man_trk_ctl_single_full_frame_bit_get(struct intel_display *display) 2562 { 2563 return display->platform.alderlake_p || DISPLAY_VER(display) >= 14 ? 2564 ADLP_PSR2_MAN_TRK_CTL_SF_SINGLE_FULL_FRAME : 2565 PSR2_MAN_TRK_CTL_SF_SINGLE_FULL_FRAME; 2566 } 2567 2568 static u32 man_trk_ctl_partial_frame_bit_get(struct intel_display *display) 2569 { 2570 return display->platform.alderlake_p || DISPLAY_VER(display) >= 14 ? 2571 ADLP_PSR2_MAN_TRK_CTL_SF_PARTIAL_FRAME_UPDATE : 2572 PSR2_MAN_TRK_CTL_SF_PARTIAL_FRAME_UPDATE; 2573 } 2574 2575 static u32 man_trk_ctl_continuos_full_frame(struct intel_display *display) 2576 { 2577 return display->platform.alderlake_p || DISPLAY_VER(display) >= 14 ? 2578 ADLP_PSR2_MAN_TRK_CTL_SF_CONTINUOS_FULL_FRAME : 2579 PSR2_MAN_TRK_CTL_SF_CONTINUOS_FULL_FRAME; 2580 } 2581 2582 static void intel_psr_force_update(struct intel_dp *intel_dp) 2583 { 2584 struct intel_display *display = to_intel_display(intel_dp); 2585 2586 /* 2587 * Display WA #0884: skl+ 2588 * This documented WA for bxt can be safely applied 2589 * broadly so we can force HW tracking to exit PSR 2590 * instead of disabling and re-enabling. 2591 * Workaround tells us to write 0 to CUR_SURFLIVE_A, 2592 * but it makes more sense write to the current active 2593 * pipe. 2594 * 2595 * This workaround do not exist for platforms with display 10 or newer 2596 * but testing proved that it works for up display 13, for newer 2597 * than that testing will be needed. 2598 */ 2599 intel_de_write(display, CURSURFLIVE(display, intel_dp->psr.pipe), 0); 2600 } 2601 2602 void intel_psr2_program_trans_man_trk_ctl(struct intel_dsb *dsb, 2603 const struct intel_crtc_state *crtc_state) 2604 { 2605 struct intel_display *display = to_intel_display(crtc_state); 2606 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2607 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 2608 struct intel_encoder *encoder; 2609 2610 if (!crtc_state->enable_psr2_sel_fetch) 2611 return; 2612 2613 for_each_intel_encoder_mask_with_psr(display->drm, encoder, 2614 crtc_state->uapi.encoder_mask) { 2615 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2616 2617 if (!dsb) 2618 lockdep_assert_held(&intel_dp->psr.lock); 2619 2620 if (DISPLAY_VER(display) < 20 && intel_dp->psr.psr2_sel_fetch_cff_enabled) 2621 return; 2622 break; 2623 } 2624 2625 intel_de_write_dsb(display, dsb, 2626 PSR2_MAN_TRK_CTL(display, cpu_transcoder), 2627 crtc_state->psr2_man_track_ctl); 2628 2629 if (!crtc_state->enable_psr2_su_region_et) 2630 return; 2631 2632 intel_de_write_dsb(display, dsb, PIPE_SRCSZ_ERLY_TPT(crtc->pipe), 2633 crtc_state->pipe_srcsz_early_tpt); 2634 2635 if (!crtc_state->dsc.compression_enable) 2636 return; 2637 2638 intel_dsc_su_et_parameters_configure(dsb, encoder, crtc_state, 2639 drm_rect_height(&crtc_state->psr2_su_area)); 2640 } 2641 2642 static void psr2_man_trk_ctl_calc(struct intel_crtc_state *crtc_state, 2643 bool full_update) 2644 { 2645 struct intel_display *display = to_intel_display(crtc_state); 2646 u32 val = man_trk_ctl_enable_bit_get(display); 2647 2648 /* SF partial frame enable has to be set even on full update */ 2649 val |= man_trk_ctl_partial_frame_bit_get(display); 2650 2651 if (full_update) { 2652 val |= man_trk_ctl_continuos_full_frame(display); 2653 goto exit; 2654 } 2655 2656 if (crtc_state->psr2_su_area.y1 == -1) 2657 goto exit; 2658 2659 if (display->platform.alderlake_p || DISPLAY_VER(display) >= 14) { 2660 val |= ADLP_PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR(crtc_state->psr2_su_area.y1); 2661 val |= ADLP_PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR(crtc_state->psr2_su_area.y2 - 1); 2662 } else { 2663 drm_WARN_ON(crtc_state->uapi.crtc->dev, 2664 crtc_state->psr2_su_area.y1 % 4 || 2665 crtc_state->psr2_su_area.y2 % 4); 2666 2667 val |= PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR( 2668 crtc_state->psr2_su_area.y1 / 4 + 1); 2669 val |= PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR( 2670 crtc_state->psr2_su_area.y2 / 4 + 1); 2671 } 2672 exit: 2673 crtc_state->psr2_man_track_ctl = val; 2674 } 2675 2676 static u32 psr2_pipe_srcsz_early_tpt_calc(struct intel_crtc_state *crtc_state, 2677 bool full_update) 2678 { 2679 int width, height; 2680 2681 if (!crtc_state->enable_psr2_su_region_et || full_update) 2682 return 0; 2683 2684 width = drm_rect_width(&crtc_state->psr2_su_area); 2685 height = drm_rect_height(&crtc_state->psr2_su_area); 2686 2687 return PIPESRC_WIDTH(width - 1) | PIPESRC_HEIGHT(height - 1); 2688 } 2689 2690 static void clip_area_update(struct drm_rect *overlap_damage_area, 2691 struct drm_rect *damage_area, 2692 struct drm_rect *pipe_src) 2693 { 2694 if (!drm_rect_intersect(damage_area, pipe_src)) 2695 return; 2696 2697 if (overlap_damage_area->y1 == -1) { 2698 overlap_damage_area->y1 = damage_area->y1; 2699 overlap_damage_area->y2 = damage_area->y2; 2700 return; 2701 } 2702 2703 if (damage_area->y1 < overlap_damage_area->y1) 2704 overlap_damage_area->y1 = damage_area->y1; 2705 2706 if (damage_area->y2 > overlap_damage_area->y2) 2707 overlap_damage_area->y2 = damage_area->y2; 2708 } 2709 2710 static bool intel_psr2_sel_fetch_pipe_alignment(struct intel_crtc_state *crtc_state) 2711 { 2712 struct intel_display *display = to_intel_display(crtc_state); 2713 const struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config; 2714 u16 y_alignment; 2715 bool su_area_changed = false; 2716 2717 /* ADLP aligns the SU region to vdsc slice height in case dsc is enabled */ 2718 if (crtc_state->dsc.compression_enable && 2719 (display->platform.alderlake_p || DISPLAY_VER(display) >= 14)) 2720 y_alignment = vdsc_cfg->slice_height; 2721 else 2722 y_alignment = crtc_state->su_y_granularity; 2723 2724 if (crtc_state->psr2_su_area.y1 % y_alignment) { 2725 crtc_state->psr2_su_area.y1 -= crtc_state->psr2_su_area.y1 % y_alignment; 2726 su_area_changed = true; 2727 } 2728 2729 if (crtc_state->psr2_su_area.y2 % y_alignment) { 2730 crtc_state->psr2_su_area.y2 = ((crtc_state->psr2_su_area.y2 / 2731 y_alignment) + 1) * y_alignment; 2732 su_area_changed = true; 2733 } 2734 2735 return su_area_changed; 2736 } 2737 2738 /* 2739 * When early transport is in use we need to extend SU area to cover 2740 * cursor fully when cursor is in SU area. 2741 */ 2742 static void 2743 intel_psr2_sel_fetch_et_alignment(struct intel_atomic_state *state, 2744 struct intel_crtc *crtc, 2745 bool *cursor_in_su_area) 2746 { 2747 struct intel_crtc_state *crtc_state = intel_atomic_get_new_crtc_state(state, crtc); 2748 struct intel_plane_state *new_plane_state; 2749 struct intel_plane *plane; 2750 int i; 2751 2752 if (!crtc_state->enable_psr2_su_region_et) 2753 return; 2754 2755 for_each_new_intel_plane_in_state(state, plane, new_plane_state, i) { 2756 struct drm_rect inter; 2757 2758 if (new_plane_state->hw.crtc != crtc_state->uapi.crtc) 2759 continue; 2760 2761 if (plane->id != PLANE_CURSOR) 2762 continue; 2763 2764 if (!new_plane_state->uapi.visible) 2765 continue; 2766 2767 inter = crtc_state->psr2_su_area; 2768 if (!drm_rect_intersect(&inter, &new_plane_state->uapi.dst)) 2769 continue; 2770 2771 clip_area_update(&crtc_state->psr2_su_area, &new_plane_state->uapi.dst, 2772 &crtc_state->pipe_src); 2773 *cursor_in_su_area = true; 2774 } 2775 } 2776 2777 /* 2778 * TODO: Not clear how to handle planes with negative position, 2779 * also planes are not updated if they have a negative X 2780 * position so for now doing a full update in this cases 2781 * 2782 * Plane scaling and rotation is not supported by selective fetch and both 2783 * properties can change without a modeset, so need to be check at every 2784 * atomic commit. 2785 */ 2786 static bool psr2_sel_fetch_plane_state_supported(const struct intel_plane_state *plane_state) 2787 { 2788 if (plane_state->uapi.dst.y1 < 0 || 2789 plane_state->uapi.dst.x1 < 0 || 2790 plane_state->scaler_id >= 0 || 2791 plane_state->hw.rotation != DRM_MODE_ROTATE_0) 2792 return false; 2793 2794 return true; 2795 } 2796 2797 /* 2798 * Check for pipe properties that is not supported by selective fetch. 2799 * 2800 * TODO: pipe scaling causes a modeset but skl_update_scaler_crtc() is executed 2801 * after intel_psr_compute_config(), so for now keeping PSR2 selective fetch 2802 * enabled and going to the full update path. 2803 */ 2804 static bool psr2_sel_fetch_pipe_state_supported(const struct intel_crtc_state *crtc_state) 2805 { 2806 if (crtc_state->scaler_state.scaler_id >= 0 || 2807 crtc_state->async_flip_planes) 2808 return false; 2809 2810 return true; 2811 } 2812 2813 /* Wa 14019834836 */ 2814 static void intel_psr_apply_pr_link_on_su_wa(struct intel_crtc_state *crtc_state) 2815 { 2816 struct intel_display *display = to_intel_display(crtc_state); 2817 struct intel_encoder *encoder; 2818 int hactive_limit; 2819 2820 if (crtc_state->psr2_su_area.y1 != 0 || 2821 crtc_state->psr2_su_area.y2 != 0) 2822 return; 2823 2824 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) 2825 hactive_limit = intel_dp_is_uhbr(crtc_state) ? 1230 : 546; 2826 else 2827 hactive_limit = intel_dp_is_uhbr(crtc_state) ? 615 : 273; 2828 2829 if (crtc_state->hw.adjusted_mode.hdisplay < hactive_limit) 2830 return; 2831 2832 for_each_intel_encoder_mask_with_psr(display->drm, encoder, 2833 crtc_state->uapi.encoder_mask) { 2834 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2835 2836 if (!intel_dp_is_edp(intel_dp) && 2837 intel_dp->psr.panel_replay_enabled && 2838 intel_dp->psr.sel_update_enabled) { 2839 crtc_state->psr2_su_area.y2++; 2840 return; 2841 } 2842 } 2843 } 2844 2845 static void 2846 intel_psr_apply_su_area_workarounds(struct intel_crtc_state *crtc_state) 2847 { 2848 struct intel_display *display = to_intel_display(crtc_state); 2849 2850 /* Wa_14014971492 */ 2851 if (!crtc_state->has_panel_replay && 2852 ((IS_DISPLAY_VERx100_STEP(display, 1400, STEP_A0, STEP_B0) || 2853 display->platform.alderlake_p || display->platform.tigerlake)) && 2854 crtc_state->splitter.enable) 2855 crtc_state->psr2_su_area.y1 = 0; 2856 2857 /* Wa 14019834836 */ 2858 if (DISPLAY_VER(display) == 30) 2859 intel_psr_apply_pr_link_on_su_wa(crtc_state); 2860 } 2861 2862 int intel_psr2_sel_fetch_update(struct intel_atomic_state *state, 2863 struct intel_crtc *crtc) 2864 { 2865 struct intel_display *display = to_intel_display(state); 2866 struct intel_crtc_state *crtc_state = intel_atomic_get_new_crtc_state(state, crtc); 2867 struct intel_plane_state *new_plane_state, *old_plane_state; 2868 struct intel_plane *plane; 2869 bool full_update = false, su_area_changed; 2870 int i, ret; 2871 2872 if (!crtc_state->enable_psr2_sel_fetch) 2873 return 0; 2874 2875 if (!psr2_sel_fetch_pipe_state_supported(crtc_state)) { 2876 full_update = true; 2877 goto skip_sel_fetch_set_loop; 2878 } 2879 2880 crtc_state->psr2_su_area.x1 = 0; 2881 crtc_state->psr2_su_area.y1 = -1; 2882 crtc_state->psr2_su_area.x2 = drm_rect_width(&crtc_state->pipe_src); 2883 crtc_state->psr2_su_area.y2 = -1; 2884 2885 /* 2886 * Calculate minimal selective fetch area of each plane and calculate 2887 * the pipe damaged area. 2888 * In the next loop the plane selective fetch area will actually be set 2889 * using whole pipe damaged area. 2890 */ 2891 for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state, 2892 new_plane_state, i) { 2893 struct drm_rect src, damaged_area = { .x1 = 0, .y1 = -1, 2894 .x2 = INT_MAX }; 2895 2896 if (new_plane_state->hw.crtc != crtc_state->uapi.crtc) 2897 continue; 2898 2899 if (!new_plane_state->uapi.visible && 2900 !old_plane_state->uapi.visible) 2901 continue; 2902 2903 if (!psr2_sel_fetch_plane_state_supported(new_plane_state)) { 2904 full_update = true; 2905 break; 2906 } 2907 2908 /* 2909 * If visibility or plane moved, mark the whole plane area as 2910 * damaged as it needs to be complete redraw in the new and old 2911 * position. 2912 */ 2913 if (new_plane_state->uapi.visible != old_plane_state->uapi.visible || 2914 !drm_rect_equals(&new_plane_state->uapi.dst, 2915 &old_plane_state->uapi.dst)) { 2916 if (old_plane_state->uapi.visible) { 2917 damaged_area.y1 = old_plane_state->uapi.dst.y1; 2918 damaged_area.y2 = old_plane_state->uapi.dst.y2; 2919 clip_area_update(&crtc_state->psr2_su_area, &damaged_area, 2920 &crtc_state->pipe_src); 2921 } 2922 2923 if (new_plane_state->uapi.visible) { 2924 damaged_area.y1 = new_plane_state->uapi.dst.y1; 2925 damaged_area.y2 = new_plane_state->uapi.dst.y2; 2926 clip_area_update(&crtc_state->psr2_su_area, &damaged_area, 2927 &crtc_state->pipe_src); 2928 } 2929 continue; 2930 } else if (new_plane_state->uapi.alpha != old_plane_state->uapi.alpha) { 2931 /* If alpha changed mark the whole plane area as damaged */ 2932 damaged_area.y1 = new_plane_state->uapi.dst.y1; 2933 damaged_area.y2 = new_plane_state->uapi.dst.y2; 2934 clip_area_update(&crtc_state->psr2_su_area, &damaged_area, 2935 &crtc_state->pipe_src); 2936 continue; 2937 } 2938 2939 src = drm_plane_state_src(&new_plane_state->uapi); 2940 drm_rect_fp_to_int(&src, &src); 2941 2942 if (!drm_atomic_helper_damage_merged(&old_plane_state->uapi, 2943 &new_plane_state->uapi, &damaged_area)) 2944 continue; 2945 2946 damaged_area.y1 += new_plane_state->uapi.dst.y1 - src.y1; 2947 damaged_area.y2 += new_plane_state->uapi.dst.y1 - src.y1; 2948 damaged_area.x1 += new_plane_state->uapi.dst.x1 - src.x1; 2949 damaged_area.x2 += new_plane_state->uapi.dst.x1 - src.x1; 2950 2951 clip_area_update(&crtc_state->psr2_su_area, &damaged_area, &crtc_state->pipe_src); 2952 } 2953 2954 /* 2955 * TODO: For now we are just using full update in case 2956 * selective fetch area calculation fails. To optimize this we 2957 * should identify cases where this happens and fix the area 2958 * calculation for those. 2959 */ 2960 if (crtc_state->psr2_su_area.y1 == -1) { 2961 drm_info_once(display->drm, 2962 "Selective fetch area calculation failed in pipe %c\n", 2963 pipe_name(crtc->pipe)); 2964 full_update = true; 2965 } 2966 2967 if (full_update) 2968 goto skip_sel_fetch_set_loop; 2969 2970 intel_psr_apply_su_area_workarounds(crtc_state); 2971 2972 ret = drm_atomic_add_affected_planes(&state->base, &crtc->base); 2973 if (ret) 2974 return ret; 2975 2976 do { 2977 bool cursor_in_su_area; 2978 2979 /* 2980 * Adjust su area to cover cursor fully as necessary 2981 * (early transport). This needs to be done after 2982 * drm_atomic_add_affected_planes to ensure visible 2983 * cursor is added into affected planes even when 2984 * cursor is not updated by itself. 2985 */ 2986 intel_psr2_sel_fetch_et_alignment(state, crtc, &cursor_in_su_area); 2987 2988 su_area_changed = intel_psr2_sel_fetch_pipe_alignment(crtc_state); 2989 2990 /* 2991 * If the cursor was outside the SU area before 2992 * alignment, the alignment step (which only expands 2993 * SU) may pull the cursor partially inside, so we 2994 * must run ET alignment again to fully cover it. But 2995 * if the cursor was already fully inside before 2996 * alignment, expanding the SU area won't change that, 2997 * so no further work is needed. 2998 */ 2999 if (cursor_in_su_area) 3000 break; 3001 } while (su_area_changed); 3002 3003 /* 3004 * Now that we have the pipe damaged area check if it intersect with 3005 * every plane, if it does set the plane selective fetch area. 3006 */ 3007 for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state, 3008 new_plane_state, i) { 3009 struct drm_rect *sel_fetch_area, inter; 3010 struct intel_plane *linked = new_plane_state->planar_linked_plane; 3011 3012 if (new_plane_state->hw.crtc != crtc_state->uapi.crtc || 3013 !new_plane_state->uapi.visible) 3014 continue; 3015 3016 inter = crtc_state->psr2_su_area; 3017 sel_fetch_area = &new_plane_state->psr2_sel_fetch_area; 3018 if (!drm_rect_intersect(&inter, &new_plane_state->uapi.dst)) { 3019 sel_fetch_area->y1 = -1; 3020 sel_fetch_area->y2 = -1; 3021 /* 3022 * if plane sel fetch was previously enabled -> 3023 * disable it 3024 */ 3025 if (drm_rect_height(&old_plane_state->psr2_sel_fetch_area) > 0) 3026 crtc_state->update_planes |= BIT(plane->id); 3027 3028 continue; 3029 } 3030 3031 if (!psr2_sel_fetch_plane_state_supported(new_plane_state)) { 3032 full_update = true; 3033 break; 3034 } 3035 3036 sel_fetch_area = &new_plane_state->psr2_sel_fetch_area; 3037 sel_fetch_area->y1 = inter.y1 - new_plane_state->uapi.dst.y1; 3038 sel_fetch_area->y2 = inter.y2 - new_plane_state->uapi.dst.y1; 3039 crtc_state->update_planes |= BIT(plane->id); 3040 3041 /* 3042 * Sel_fetch_area is calculated for UV plane. Use 3043 * same area for Y plane as well. 3044 */ 3045 if (linked) { 3046 struct intel_plane_state *linked_new_plane_state; 3047 struct drm_rect *linked_sel_fetch_area; 3048 3049 linked_new_plane_state = intel_atomic_get_plane_state(state, linked); 3050 if (IS_ERR(linked_new_plane_state)) 3051 return PTR_ERR(linked_new_plane_state); 3052 3053 linked_sel_fetch_area = &linked_new_plane_state->psr2_sel_fetch_area; 3054 linked_sel_fetch_area->y1 = sel_fetch_area->y1; 3055 linked_sel_fetch_area->y2 = sel_fetch_area->y2; 3056 crtc_state->update_planes |= BIT(linked->id); 3057 } 3058 } 3059 3060 skip_sel_fetch_set_loop: 3061 if (full_update) 3062 clip_area_update(&crtc_state->psr2_su_area, &crtc_state->pipe_src, 3063 &crtc_state->pipe_src); 3064 3065 psr2_man_trk_ctl_calc(crtc_state, full_update); 3066 crtc_state->pipe_srcsz_early_tpt = 3067 psr2_pipe_srcsz_early_tpt_calc(crtc_state, full_update); 3068 return 0; 3069 } 3070 3071 void intel_psr2_panic_force_full_update(const struct intel_crtc_state *crtc_state) 3072 { 3073 struct intel_display *display = to_intel_display(crtc_state); 3074 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 3075 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 3076 u32 val = man_trk_ctl_enable_bit_get(display); 3077 3078 /* SF partial frame enable has to be set even on full update */ 3079 val |= man_trk_ctl_partial_frame_bit_get(display); 3080 val |= man_trk_ctl_continuos_full_frame(display); 3081 3082 /* Directly write the register */ 3083 intel_de_write_fw(display, PSR2_MAN_TRK_CTL(display, cpu_transcoder), val); 3084 3085 if (!crtc_state->enable_psr2_su_region_et) 3086 return; 3087 3088 intel_de_write_fw(display, PIPE_SRCSZ_ERLY_TPT(crtc->pipe), 0); 3089 } 3090 3091 void intel_psr_pre_plane_update(struct intel_atomic_state *state, 3092 struct intel_crtc *crtc) 3093 { 3094 struct intel_display *display = to_intel_display(state); 3095 const struct intel_crtc_state *old_crtc_state = 3096 intel_atomic_get_old_crtc_state(state, crtc); 3097 const struct intel_crtc_state *new_crtc_state = 3098 intel_atomic_get_new_crtc_state(state, crtc); 3099 struct intel_encoder *encoder; 3100 3101 if (!HAS_PSR(display)) 3102 return; 3103 3104 for_each_intel_encoder_mask_with_psr(state->base.dev, encoder, 3105 old_crtc_state->uapi.encoder_mask) { 3106 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 3107 struct intel_psr *psr = &intel_dp->psr; 3108 3109 mutex_lock(&psr->lock); 3110 3111 if (!new_crtc_state->has_psr) 3112 psr->no_psr_reason = new_crtc_state->no_psr_reason; 3113 3114 if (psr->enabled) { 3115 /* 3116 * Reasons to disable: 3117 * - PSR disabled in new state 3118 * - All planes will go inactive 3119 * - Changing between PSR versions 3120 * - Region Early Transport changing 3121 * - Display WA #1136: skl, bxt 3122 */ 3123 if (intel_crtc_needs_modeset(new_crtc_state) || 3124 new_crtc_state->update_m_n || 3125 new_crtc_state->update_lrr || 3126 !new_crtc_state->has_psr || 3127 !new_crtc_state->active_planes || 3128 new_crtc_state->has_sel_update != psr->sel_update_enabled || 3129 new_crtc_state->enable_psr2_su_region_et != psr->su_region_et_enabled || 3130 new_crtc_state->has_panel_replay != psr->panel_replay_enabled || 3131 (DISPLAY_VER(display) < 11 && new_crtc_state->wm_level_disabled)) 3132 intel_psr_disable_locked(intel_dp); 3133 else if (new_crtc_state->wm_level_disabled) 3134 /* Wa_14015648006 */ 3135 wm_optimization_wa(intel_dp, new_crtc_state); 3136 } 3137 3138 mutex_unlock(&psr->lock); 3139 } 3140 } 3141 3142 static void 3143 verify_panel_replay_dsc_state(const struct intel_crtc_state *crtc_state) 3144 { 3145 struct intel_display *display = to_intel_display(crtc_state); 3146 3147 if (!crtc_state->has_panel_replay) 3148 return; 3149 3150 drm_WARN_ON(display->drm, 3151 intel_dsc_enabled_on_link(crtc_state) && 3152 crtc_state->panel_replay_dsc_support == 3153 INTEL_DP_PANEL_REPLAY_DSC_NOT_SUPPORTED); 3154 } 3155 3156 void intel_psr_post_plane_update(struct intel_atomic_state *state, 3157 struct intel_crtc *crtc) 3158 { 3159 struct intel_display *display = to_intel_display(state); 3160 const struct intel_crtc_state *crtc_state = 3161 intel_atomic_get_new_crtc_state(state, crtc); 3162 struct intel_encoder *encoder; 3163 3164 if (!crtc_state->has_psr) 3165 return; 3166 3167 verify_panel_replay_dsc_state(crtc_state); 3168 3169 for_each_intel_encoder_mask_with_psr(state->base.dev, encoder, 3170 crtc_state->uapi.encoder_mask) { 3171 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 3172 struct intel_psr *psr = &intel_dp->psr; 3173 bool keep_disabled = false; 3174 3175 mutex_lock(&psr->lock); 3176 3177 drm_WARN_ON(display->drm, 3178 psr->enabled && !crtc_state->active_planes); 3179 3180 if (psr->sink_not_reliable) 3181 keep_disabled = true; 3182 3183 if (!crtc_state->active_planes) { 3184 psr->no_psr_reason = "All planes inactive"; 3185 keep_disabled = true; 3186 } 3187 3188 /* Display WA #1136: skl, bxt */ 3189 if (DISPLAY_VER(display) < 11 && crtc_state->wm_level_disabled) { 3190 psr->no_psr_reason = "Workaround #1136 for skl, bxt"; 3191 keep_disabled = true; 3192 } 3193 3194 if (!psr->enabled && !keep_disabled) 3195 intel_psr_enable_locked(intel_dp, crtc_state); 3196 else if (psr->enabled && !crtc_state->wm_level_disabled) 3197 /* Wa_14015648006 */ 3198 wm_optimization_wa(intel_dp, crtc_state); 3199 3200 /* Force a PSR exit when enabling CRC to avoid CRC timeouts */ 3201 if (crtc_state->crc_enabled && psr->enabled) 3202 intel_psr_force_update(intel_dp); 3203 3204 /* 3205 * Clear possible busy bits in case we have 3206 * invalidate -> flip -> flush sequence. 3207 */ 3208 intel_dp->psr.busy_frontbuffer_bits = 0; 3209 3210 mutex_unlock(&psr->lock); 3211 } 3212 } 3213 3214 /* 3215 * From bspec: Panel Self Refresh (BDW+) 3216 * Max. time for PSR to idle = Inverse of the refresh rate + 6 ms of 3217 * exit training time + 1.5 ms of aux channel handshake. 50 ms is 3218 * defensive enough to cover everything. 3219 */ 3220 #define PSR_IDLE_TIMEOUT_MS 50 3221 3222 static int 3223 _psr2_ready_for_pipe_update_locked(const struct intel_crtc_state *new_crtc_state, 3224 struct intel_dsb *dsb) 3225 { 3226 struct intel_display *display = to_intel_display(new_crtc_state); 3227 enum transcoder cpu_transcoder = new_crtc_state->cpu_transcoder; 3228 3229 /* 3230 * Any state lower than EDP_PSR2_STATUS_STATE_DEEP_SLEEP is enough. 3231 * As all higher states has bit 4 of PSR2 state set we can just wait for 3232 * EDP_PSR2_STATUS_STATE_DEEP_SLEEP to be cleared. 3233 */ 3234 if (dsb) { 3235 intel_dsb_poll(dsb, EDP_PSR2_STATUS(display, cpu_transcoder), 3236 EDP_PSR2_STATUS_STATE_DEEP_SLEEP, 0, 200, 3237 PSR_IDLE_TIMEOUT_MS * 1000 / 200); 3238 return true; 3239 } 3240 3241 return intel_de_wait_for_clear_ms(display, 3242 EDP_PSR2_STATUS(display, cpu_transcoder), 3243 EDP_PSR2_STATUS_STATE_DEEP_SLEEP, 3244 PSR_IDLE_TIMEOUT_MS); 3245 } 3246 3247 static int 3248 _psr1_ready_for_pipe_update_locked(const struct intel_crtc_state *new_crtc_state, 3249 struct intel_dsb *dsb) 3250 { 3251 struct intel_display *display = to_intel_display(new_crtc_state); 3252 enum transcoder cpu_transcoder = new_crtc_state->cpu_transcoder; 3253 3254 if (dsb) { 3255 intel_dsb_poll(dsb, psr_status_reg(display, cpu_transcoder), 3256 EDP_PSR_STATUS_STATE_MASK, 0, 200, 3257 PSR_IDLE_TIMEOUT_MS * 1000 / 200); 3258 return true; 3259 } 3260 3261 return intel_de_wait_for_clear_ms(display, 3262 psr_status_reg(display, cpu_transcoder), 3263 EDP_PSR_STATUS_STATE_MASK, 3264 PSR_IDLE_TIMEOUT_MS); 3265 } 3266 3267 /** 3268 * intel_psr_wait_for_idle_locked - wait for PSR be ready for a pipe update 3269 * @new_crtc_state: new CRTC state 3270 * 3271 * This function is expected to be called from pipe_update_start() where it is 3272 * not expected to race with PSR enable or disable. 3273 */ 3274 void intel_psr_wait_for_idle_locked(const struct intel_crtc_state *new_crtc_state) 3275 { 3276 struct intel_display *display = to_intel_display(new_crtc_state); 3277 struct intel_encoder *encoder; 3278 3279 if (!new_crtc_state->has_psr) 3280 return; 3281 3282 for_each_intel_encoder_mask_with_psr(display->drm, encoder, 3283 new_crtc_state->uapi.encoder_mask) { 3284 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 3285 int ret; 3286 3287 lockdep_assert_held(&intel_dp->psr.lock); 3288 3289 if (!intel_dp->psr.enabled || intel_dp->psr.panel_replay_enabled) 3290 continue; 3291 3292 if (intel_dp->psr.sel_update_enabled) 3293 ret = _psr2_ready_for_pipe_update_locked(new_crtc_state, 3294 NULL); 3295 else 3296 ret = _psr1_ready_for_pipe_update_locked(new_crtc_state, 3297 NULL); 3298 3299 if (ret) 3300 drm_err(display->drm, 3301 "PSR wait timed out, atomic update may fail\n"); 3302 } 3303 } 3304 3305 void intel_psr_wait_for_idle_dsb(struct intel_dsb *dsb, 3306 const struct intel_crtc_state *new_crtc_state) 3307 { 3308 if (!new_crtc_state->has_psr || new_crtc_state->has_panel_replay) 3309 return; 3310 3311 if (new_crtc_state->has_sel_update) 3312 _psr2_ready_for_pipe_update_locked(new_crtc_state, dsb); 3313 else 3314 _psr1_ready_for_pipe_update_locked(new_crtc_state, dsb); 3315 } 3316 3317 static bool __psr_wait_for_idle_locked(struct intel_dp *intel_dp) 3318 { 3319 struct intel_display *display = to_intel_display(intel_dp); 3320 enum transcoder cpu_transcoder = intel_dp->psr.transcoder; 3321 i915_reg_t reg; 3322 u32 mask; 3323 int err; 3324 3325 if (!intel_dp->psr.enabled) 3326 return false; 3327 3328 if (intel_dp_is_edp(intel_dp) && (intel_dp->psr.sel_update_enabled || 3329 intel_dp->psr.panel_replay_enabled)) { 3330 reg = EDP_PSR2_STATUS(display, cpu_transcoder); 3331 mask = EDP_PSR2_STATUS_STATE_MASK; 3332 } else { 3333 reg = psr_status_reg(display, cpu_transcoder); 3334 mask = EDP_PSR_STATUS_STATE_MASK; 3335 } 3336 3337 mutex_unlock(&intel_dp->psr.lock); 3338 3339 err = intel_de_wait_for_clear_ms(display, reg, mask, 50); 3340 if (err) 3341 drm_err(display->drm, 3342 "Timed out waiting for PSR Idle for re-enable\n"); 3343 3344 /* After the unlocked wait, verify that PSR is still wanted! */ 3345 mutex_lock(&intel_dp->psr.lock); 3346 return err == 0 && intel_dp->psr.enabled && !intel_dp->psr.pause_counter; 3347 } 3348 3349 static int intel_psr_fastset_force(struct intel_display *display) 3350 { 3351 struct drm_connector_list_iter conn_iter; 3352 struct drm_modeset_acquire_ctx ctx; 3353 struct drm_atomic_state *state; 3354 struct drm_connector *conn; 3355 int err = 0; 3356 3357 state = drm_atomic_state_alloc(display->drm); 3358 if (!state) 3359 return -ENOMEM; 3360 3361 drm_modeset_acquire_init(&ctx, DRM_MODESET_ACQUIRE_INTERRUPTIBLE); 3362 3363 state->acquire_ctx = &ctx; 3364 to_intel_atomic_state(state)->internal = true; 3365 3366 retry: 3367 drm_connector_list_iter_begin(display->drm, &conn_iter); 3368 drm_for_each_connector_iter(conn, &conn_iter) { 3369 struct drm_connector_state *conn_state; 3370 struct drm_crtc_state *crtc_state; 3371 3372 if (conn->connector_type != DRM_MODE_CONNECTOR_eDP) 3373 continue; 3374 3375 conn_state = drm_atomic_get_connector_state(state, conn); 3376 if (IS_ERR(conn_state)) { 3377 err = PTR_ERR(conn_state); 3378 break; 3379 } 3380 3381 if (!conn_state->crtc) 3382 continue; 3383 3384 crtc_state = drm_atomic_get_crtc_state(state, conn_state->crtc); 3385 if (IS_ERR(crtc_state)) { 3386 err = PTR_ERR(crtc_state); 3387 break; 3388 } 3389 3390 /* Mark mode as changed to trigger a pipe->update() */ 3391 crtc_state->mode_changed = true; 3392 } 3393 drm_connector_list_iter_end(&conn_iter); 3394 3395 if (err == 0) 3396 err = drm_atomic_commit(state); 3397 3398 if (err == -EDEADLK) { 3399 drm_atomic_state_clear(state); 3400 err = drm_modeset_backoff(&ctx); 3401 if (!err) 3402 goto retry; 3403 } 3404 3405 drm_modeset_drop_locks(&ctx); 3406 drm_modeset_acquire_fini(&ctx); 3407 drm_atomic_state_put(state); 3408 3409 return err; 3410 } 3411 3412 int intel_psr_debug_set(struct intel_dp *intel_dp, u64 val) 3413 { 3414 struct intel_display *display = to_intel_display(intel_dp); 3415 const u32 mode = val & I915_PSR_DEBUG_MODE_MASK; 3416 const u32 disable_bits = val & (I915_PSR_DEBUG_SU_REGION_ET_DISABLE | 3417 I915_PSR_DEBUG_PANEL_REPLAY_DISABLE); 3418 u32 old_mode, old_disable_bits; 3419 int ret; 3420 3421 if (val & ~(I915_PSR_DEBUG_IRQ | I915_PSR_DEBUG_SU_REGION_ET_DISABLE | 3422 I915_PSR_DEBUG_PANEL_REPLAY_DISABLE | 3423 I915_PSR_DEBUG_MODE_MASK) || 3424 mode > I915_PSR_DEBUG_ENABLE_SEL_FETCH) { 3425 drm_dbg_kms(display->drm, "Invalid debug mask %llx\n", val); 3426 return -EINVAL; 3427 } 3428 3429 ret = mutex_lock_interruptible(&intel_dp->psr.lock); 3430 if (ret) 3431 return ret; 3432 3433 old_mode = intel_dp->psr.debug & I915_PSR_DEBUG_MODE_MASK; 3434 old_disable_bits = intel_dp->psr.debug & 3435 (I915_PSR_DEBUG_SU_REGION_ET_DISABLE | 3436 I915_PSR_DEBUG_PANEL_REPLAY_DISABLE); 3437 3438 intel_dp->psr.debug = val; 3439 3440 /* 3441 * Do it right away if it's already enabled, otherwise it will be done 3442 * when enabling the source. 3443 */ 3444 if (intel_dp->psr.enabled) 3445 psr_irq_control(intel_dp); 3446 3447 mutex_unlock(&intel_dp->psr.lock); 3448 3449 if (old_mode != mode || old_disable_bits != disable_bits) 3450 ret = intel_psr_fastset_force(display); 3451 3452 return ret; 3453 } 3454 3455 static void intel_psr_handle_irq(struct intel_dp *intel_dp) 3456 { 3457 struct intel_psr *psr = &intel_dp->psr; 3458 3459 intel_psr_disable_locked(intel_dp); 3460 psr->sink_not_reliable = true; 3461 /* let's make sure that sink is awaken */ 3462 drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, DP_SET_POWER_D0); 3463 } 3464 3465 static void intel_psr_work(struct work_struct *work) 3466 { 3467 struct intel_dp *intel_dp = 3468 container_of(work, typeof(*intel_dp), psr.work); 3469 3470 mutex_lock(&intel_dp->psr.lock); 3471 3472 if (!intel_dp->psr.enabled) 3473 goto unlock; 3474 3475 if (READ_ONCE(intel_dp->psr.irq_aux_error)) { 3476 intel_psr_handle_irq(intel_dp); 3477 goto unlock; 3478 } 3479 3480 if (intel_dp->psr.pause_counter) 3481 goto unlock; 3482 3483 /* 3484 * We have to make sure PSR is ready for re-enable 3485 * otherwise it keeps disabled until next full enable/disable cycle. 3486 * PSR might take some time to get fully disabled 3487 * and be ready for re-enable. 3488 */ 3489 if (!__psr_wait_for_idle_locked(intel_dp)) 3490 goto unlock; 3491 3492 /* 3493 * The delayed work can race with an invalidate hence we need to 3494 * recheck. Since psr_flush first clears this and then reschedules we 3495 * won't ever miss a flush when bailing out here. 3496 */ 3497 if (intel_dp->psr.busy_frontbuffer_bits || intel_dp->psr.active) 3498 goto unlock; 3499 3500 intel_psr_activate(intel_dp); 3501 unlock: 3502 mutex_unlock(&intel_dp->psr.lock); 3503 } 3504 3505 static void intel_psr_configure_full_frame_update(struct intel_dp *intel_dp) 3506 { 3507 struct intel_display *display = to_intel_display(intel_dp); 3508 enum transcoder cpu_transcoder = intel_dp->psr.transcoder; 3509 3510 if (!intel_dp->psr.psr2_sel_fetch_enabled) 3511 return; 3512 3513 if (DISPLAY_VER(display) >= 20) 3514 intel_de_write(display, LNL_SFF_CTL(cpu_transcoder), 3515 LNL_SFF_CTL_SF_SINGLE_FULL_FRAME); 3516 else 3517 intel_de_write(display, 3518 PSR2_MAN_TRK_CTL(display, cpu_transcoder), 3519 man_trk_ctl_enable_bit_get(display) | 3520 man_trk_ctl_partial_frame_bit_get(display) | 3521 man_trk_ctl_single_full_frame_bit_get(display) | 3522 man_trk_ctl_continuos_full_frame(display)); 3523 } 3524 3525 static void _psr_invalidate_handle(struct intel_dp *intel_dp) 3526 { 3527 struct intel_display *display = to_intel_display(intel_dp); 3528 3529 if (DISPLAY_VER(display) < 20 && intel_dp->psr.psr2_sel_fetch_enabled) { 3530 if (!intel_dp->psr.psr2_sel_fetch_cff_enabled) { 3531 intel_dp->psr.psr2_sel_fetch_cff_enabled = true; 3532 intel_psr_configure_full_frame_update(intel_dp); 3533 } 3534 3535 intel_psr_force_update(intel_dp); 3536 } else { 3537 intel_psr_exit(intel_dp); 3538 } 3539 } 3540 3541 /** 3542 * intel_psr_invalidate - Invalidate PSR 3543 * @display: display device 3544 * @frontbuffer_bits: frontbuffer plane tracking bits 3545 * @origin: which operation caused the invalidate 3546 * 3547 * Since the hardware frontbuffer tracking has gaps we need to integrate 3548 * with the software frontbuffer tracking. This function gets called every 3549 * time frontbuffer rendering starts and a buffer gets dirtied. PSR must be 3550 * disabled if the frontbuffer mask contains a buffer relevant to PSR. 3551 * 3552 * Dirty frontbuffers relevant to PSR are tracked in busy_frontbuffer_bits." 3553 */ 3554 void intel_psr_invalidate(struct intel_display *display, 3555 unsigned frontbuffer_bits, enum fb_op_origin origin) 3556 { 3557 struct intel_encoder *encoder; 3558 3559 if (origin == ORIGIN_FLIP) 3560 return; 3561 3562 for_each_intel_encoder_with_psr(display->drm, encoder) { 3563 unsigned int pipe_frontbuffer_bits = frontbuffer_bits; 3564 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 3565 3566 mutex_lock(&intel_dp->psr.lock); 3567 if (!intel_dp->psr.enabled) { 3568 mutex_unlock(&intel_dp->psr.lock); 3569 continue; 3570 } 3571 3572 pipe_frontbuffer_bits &= 3573 INTEL_FRONTBUFFER_ALL_MASK(intel_dp->psr.pipe); 3574 intel_dp->psr.busy_frontbuffer_bits |= pipe_frontbuffer_bits; 3575 3576 if (pipe_frontbuffer_bits) 3577 _psr_invalidate_handle(intel_dp); 3578 3579 mutex_unlock(&intel_dp->psr.lock); 3580 } 3581 } 3582 /* 3583 * When we will be completely rely on PSR2 S/W tracking in future, 3584 * intel_psr_flush() will invalidate and flush the PSR for ORIGIN_FLIP 3585 * event also therefore tgl_dc3co_flush_locked() require to be changed 3586 * accordingly in future. 3587 */ 3588 static void 3589 tgl_dc3co_flush_locked(struct intel_dp *intel_dp, unsigned int frontbuffer_bits, 3590 enum fb_op_origin origin) 3591 { 3592 struct intel_display *display = to_intel_display(intel_dp); 3593 3594 if (!intel_dp->psr.dc3co_exitline || !intel_dp->psr.sel_update_enabled || 3595 !intel_dp->psr.active) 3596 return; 3597 3598 /* 3599 * At every frontbuffer flush flip event modified delay of delayed work, 3600 * when delayed work schedules that means display has been idle. 3601 */ 3602 if (!(frontbuffer_bits & 3603 INTEL_FRONTBUFFER_ALL_MASK(intel_dp->psr.pipe))) 3604 return; 3605 3606 tgl_psr2_enable_dc3co(intel_dp); 3607 mod_delayed_work(display->wq.unordered, &intel_dp->psr.dc3co_work, 3608 intel_dp->psr.dc3co_exit_delay); 3609 } 3610 3611 static void _psr_flush_handle(struct intel_dp *intel_dp) 3612 { 3613 struct intel_display *display = to_intel_display(intel_dp); 3614 3615 if (DISPLAY_VER(display) >= 20) { 3616 /* 3617 * We can use PSR exit on LunarLake onwards. Also 3618 * using trans push mechanism to trigger Frame Change 3619 * event requires using PSR exit. 3620 */ 3621 intel_psr_exit(intel_dp); 3622 } else if (intel_dp->psr.psr2_sel_fetch_enabled) { 3623 /* Selective fetch prior LNL */ 3624 if (intel_dp->psr.psr2_sel_fetch_cff_enabled) { 3625 /* can we turn CFF off? */ 3626 if (intel_dp->psr.busy_frontbuffer_bits == 0) 3627 intel_dp->psr.psr2_sel_fetch_cff_enabled = false; 3628 } 3629 3630 /* 3631 * Still keep cff bit enabled as we don't have proper SU 3632 * configuration in case update is sent for any reason after 3633 * sff bit gets cleared by the HW on next vblank. 3634 * 3635 * NOTE: Setting cff bit is not needed for LunarLake onwards as 3636 * we have own register for SFF bit and we are not overwriting 3637 * existing SU configuration 3638 */ 3639 intel_psr_configure_full_frame_update(intel_dp); 3640 3641 intel_psr_force_update(intel_dp); 3642 } else { 3643 /* 3644 * On older platforms using PSR exit was seen causing problems 3645 */ 3646 intel_psr_force_update(intel_dp); 3647 } 3648 3649 if (!intel_dp->psr.active && !intel_dp->psr.busy_frontbuffer_bits) 3650 queue_work(display->wq.unordered, &intel_dp->psr.work); 3651 } 3652 3653 /** 3654 * intel_psr_flush - Flush PSR 3655 * @display: display device 3656 * @frontbuffer_bits: frontbuffer plane tracking bits 3657 * @origin: which operation caused the flush 3658 * 3659 * Since the hardware frontbuffer tracking has gaps we need to integrate 3660 * with the software frontbuffer tracking. This function gets called every 3661 * time frontbuffer rendering has completed and flushed out to memory. PSR 3662 * can be enabled again if no other frontbuffer relevant to PSR is dirty. 3663 * 3664 * Dirty frontbuffers relevant to PSR are tracked in busy_frontbuffer_bits. 3665 */ 3666 void intel_psr_flush(struct intel_display *display, 3667 unsigned frontbuffer_bits, enum fb_op_origin origin) 3668 { 3669 struct intel_encoder *encoder; 3670 3671 for_each_intel_encoder_with_psr(display->drm, encoder) { 3672 unsigned int pipe_frontbuffer_bits = frontbuffer_bits; 3673 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 3674 3675 mutex_lock(&intel_dp->psr.lock); 3676 if (!intel_dp->psr.enabled) { 3677 mutex_unlock(&intel_dp->psr.lock); 3678 continue; 3679 } 3680 3681 pipe_frontbuffer_bits &= 3682 INTEL_FRONTBUFFER_ALL_MASK(intel_dp->psr.pipe); 3683 intel_dp->psr.busy_frontbuffer_bits &= ~pipe_frontbuffer_bits; 3684 3685 /* 3686 * If the PSR is paused by an explicit intel_psr_paused() call, 3687 * we have to ensure that the PSR is not activated until 3688 * intel_psr_resume() is called. 3689 */ 3690 if (intel_dp->psr.pause_counter) 3691 goto unlock; 3692 3693 if (origin == ORIGIN_FLIP || 3694 (origin == ORIGIN_CURSOR_UPDATE && 3695 !intel_dp->psr.psr2_sel_fetch_enabled)) { 3696 tgl_dc3co_flush_locked(intel_dp, frontbuffer_bits, origin); 3697 goto unlock; 3698 } 3699 3700 if (pipe_frontbuffer_bits == 0) 3701 goto unlock; 3702 3703 /* By definition flush = invalidate + flush */ 3704 _psr_flush_handle(intel_dp); 3705 unlock: 3706 mutex_unlock(&intel_dp->psr.lock); 3707 } 3708 } 3709 3710 /** 3711 * intel_psr_init - Init basic PSR work and mutex. 3712 * @intel_dp: Intel DP 3713 * 3714 * This function is called after the initializing connector. 3715 * (the initializing of connector treats the handling of connector capabilities) 3716 * And it initializes basic PSR stuff for each DP Encoder. 3717 */ 3718 void intel_psr_init(struct intel_dp *intel_dp) 3719 { 3720 struct intel_display *display = to_intel_display(intel_dp); 3721 struct intel_connector *connector = intel_dp->attached_connector; 3722 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 3723 3724 if (!(HAS_PSR(display) || HAS_DP20(display))) 3725 return; 3726 3727 /* 3728 * HSW spec explicitly says PSR is tied to port A. 3729 * BDW+ platforms have a instance of PSR registers per transcoder but 3730 * BDW, GEN9 and GEN11 are not validated by HW team in other transcoder 3731 * than eDP one. 3732 * For now it only supports one instance of PSR for BDW, GEN9 and GEN11. 3733 * So lets keep it hardcoded to PORT_A for BDW, GEN9 and GEN11. 3734 * But GEN12 supports a instance of PSR registers per transcoder. 3735 */ 3736 if (DISPLAY_VER(display) < 12 && dig_port->base.port != PORT_A) { 3737 drm_dbg_kms(display->drm, 3738 "PSR condition failed: Port not supported\n"); 3739 return; 3740 } 3741 3742 if ((HAS_DP20(display) && !intel_dp_is_edp(intel_dp)) || 3743 DISPLAY_VER(display) >= 20) 3744 intel_dp->psr.source_panel_replay_support = true; 3745 3746 if (HAS_PSR(display) && intel_dp_is_edp(intel_dp)) 3747 intel_dp->psr.source_support = true; 3748 3749 /* Set link_standby x link_off defaults */ 3750 if (DISPLAY_VER(display) < 12) 3751 /* For new platforms up to TGL let's respect VBT back again */ 3752 intel_dp->psr.link_standby = connector->panel.vbt.psr.full_link; 3753 3754 INIT_WORK(&intel_dp->psr.work, intel_psr_work); 3755 INIT_DELAYED_WORK(&intel_dp->psr.dc3co_work, tgl_dc3co_disable_work); 3756 mutex_init(&intel_dp->psr.lock); 3757 } 3758 3759 static int psr_get_status_and_error_status(struct intel_dp *intel_dp, 3760 u8 *status, u8 *error_status) 3761 { 3762 struct drm_dp_aux *aux = &intel_dp->aux; 3763 int ret; 3764 unsigned int offset; 3765 3766 offset = intel_dp->psr.panel_replay_enabled ? 3767 DP_SINK_DEVICE_PR_AND_FRAME_LOCK_STATUS : DP_PSR_STATUS; 3768 3769 ret = drm_dp_dpcd_readb(aux, offset, status); 3770 if (ret != 1) 3771 return ret; 3772 3773 offset = intel_dp->psr.panel_replay_enabled ? 3774 DP_PANEL_REPLAY_ERROR_STATUS : DP_PSR_ERROR_STATUS; 3775 3776 ret = drm_dp_dpcd_readb(aux, offset, error_status); 3777 if (ret != 1) 3778 return ret; 3779 3780 *status = *status & DP_PSR_SINK_STATE_MASK; 3781 3782 return 0; 3783 } 3784 3785 static void psr_alpm_check(struct intel_dp *intel_dp) 3786 { 3787 struct intel_psr *psr = &intel_dp->psr; 3788 3789 if (!psr->sel_update_enabled) 3790 return; 3791 3792 if (intel_alpm_get_error(intel_dp)) { 3793 intel_psr_disable_locked(intel_dp); 3794 psr->sink_not_reliable = true; 3795 } 3796 } 3797 3798 static void psr_capability_changed_check(struct intel_dp *intel_dp) 3799 { 3800 struct intel_display *display = to_intel_display(intel_dp); 3801 struct intel_psr *psr = &intel_dp->psr; 3802 u8 val; 3803 int r; 3804 3805 r = drm_dp_dpcd_readb(&intel_dp->aux, DP_PSR_ESI, &val); 3806 if (r != 1) { 3807 drm_err(display->drm, "Error reading DP_PSR_ESI\n"); 3808 return; 3809 } 3810 3811 if (val & DP_PSR_CAPS_CHANGE) { 3812 intel_psr_disable_locked(intel_dp); 3813 psr->sink_not_reliable = true; 3814 drm_dbg_kms(display->drm, 3815 "Sink PSR capability changed, disabling PSR\n"); 3816 3817 /* Clearing it */ 3818 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_ESI, val); 3819 } 3820 } 3821 3822 /* 3823 * On common bits: 3824 * DP_PSR_RFB_STORAGE_ERROR == DP_PANEL_REPLAY_RFB_STORAGE_ERROR 3825 * DP_PSR_VSC_SDP_UNCORRECTABLE_ERROR == DP_PANEL_REPLAY_VSC_SDP_UNCORRECTABLE_ERROR 3826 * DP_PSR_LINK_CRC_ERROR == DP_PANEL_REPLAY_LINK_CRC_ERROR 3827 * this function is relying on PSR definitions 3828 */ 3829 void intel_psr_short_pulse(struct intel_dp *intel_dp) 3830 { 3831 struct intel_display *display = to_intel_display(intel_dp); 3832 struct intel_psr *psr = &intel_dp->psr; 3833 u8 status, error_status; 3834 const u8 errors = DP_PSR_RFB_STORAGE_ERROR | 3835 DP_PSR_VSC_SDP_UNCORRECTABLE_ERROR | 3836 DP_PSR_LINK_CRC_ERROR; 3837 3838 if (!CAN_PSR(intel_dp) && !CAN_PANEL_REPLAY(intel_dp)) 3839 return; 3840 3841 mutex_lock(&psr->lock); 3842 3843 psr->link_ok = false; 3844 3845 if (!psr->enabled) 3846 goto exit; 3847 3848 if (psr_get_status_and_error_status(intel_dp, &status, &error_status)) { 3849 drm_err(display->drm, 3850 "Error reading PSR status or error status\n"); 3851 goto exit; 3852 } 3853 3854 if ((!psr->panel_replay_enabled && status == DP_PSR_SINK_INTERNAL_ERROR) || 3855 (error_status & errors)) { 3856 intel_psr_disable_locked(intel_dp); 3857 psr->sink_not_reliable = true; 3858 } 3859 3860 if (!psr->panel_replay_enabled && status == DP_PSR_SINK_INTERNAL_ERROR && 3861 !error_status) 3862 drm_dbg_kms(display->drm, 3863 "PSR sink internal error, disabling PSR\n"); 3864 if (error_status & DP_PSR_RFB_STORAGE_ERROR) 3865 drm_dbg_kms(display->drm, 3866 "PSR RFB storage error, disabling PSR\n"); 3867 if (error_status & DP_PSR_VSC_SDP_UNCORRECTABLE_ERROR) 3868 drm_dbg_kms(display->drm, 3869 "PSR VSC SDP uncorrectable error, disabling PSR\n"); 3870 if (error_status & DP_PSR_LINK_CRC_ERROR) 3871 drm_dbg_kms(display->drm, 3872 "PSR Link CRC error, disabling PSR\n"); 3873 3874 if (error_status & ~errors) 3875 drm_err(display->drm, 3876 "PSR_ERROR_STATUS unhandled errors %x\n", 3877 error_status & ~errors); 3878 /* clear status register */ 3879 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_ERROR_STATUS, error_status); 3880 3881 if (!psr->panel_replay_enabled) { 3882 psr_alpm_check(intel_dp); 3883 psr_capability_changed_check(intel_dp); 3884 } 3885 3886 exit: 3887 mutex_unlock(&psr->lock); 3888 } 3889 3890 bool intel_psr_enabled(struct intel_dp *intel_dp) 3891 { 3892 bool ret; 3893 3894 if (!CAN_PSR(intel_dp)) 3895 return false; 3896 3897 mutex_lock(&intel_dp->psr.lock); 3898 ret = intel_dp->psr.enabled; 3899 mutex_unlock(&intel_dp->psr.lock); 3900 3901 return ret; 3902 } 3903 3904 /** 3905 * intel_psr_link_ok - return psr->link_ok 3906 * @intel_dp: struct intel_dp 3907 * 3908 * We are seeing unexpected link re-trainings with some panels. This is caused 3909 * by panel stating bad link status after PSR is enabled. Code checking link 3910 * status can call this to ensure it can ignore bad link status stated by the 3911 * panel I.e. if panel is stating bad link and intel_psr_link_ok is stating link 3912 * is ok caller should rely on latter. 3913 * 3914 * Return value of link_ok 3915 */ 3916 bool intel_psr_link_ok(struct intel_dp *intel_dp) 3917 { 3918 bool ret; 3919 3920 if ((!CAN_PSR(intel_dp) && !CAN_PANEL_REPLAY(intel_dp)) || 3921 !intel_dp_is_edp(intel_dp)) 3922 return false; 3923 3924 mutex_lock(&intel_dp->psr.lock); 3925 ret = intel_dp->psr.link_ok; 3926 mutex_unlock(&intel_dp->psr.lock); 3927 3928 return ret; 3929 } 3930 3931 /** 3932 * intel_psr_lock - grab PSR lock 3933 * @crtc_state: the crtc state 3934 * 3935 * This is initially meant to be used by around CRTC update, when 3936 * vblank sensitive registers are updated and we need grab the lock 3937 * before it to avoid vblank evasion. 3938 */ 3939 void intel_psr_lock(const struct intel_crtc_state *crtc_state) 3940 { 3941 struct intel_display *display = to_intel_display(crtc_state); 3942 struct intel_encoder *encoder; 3943 3944 if (!crtc_state->has_psr) 3945 return; 3946 3947 for_each_intel_encoder_mask_with_psr(display->drm, encoder, 3948 crtc_state->uapi.encoder_mask) { 3949 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 3950 3951 mutex_lock(&intel_dp->psr.lock); 3952 break; 3953 } 3954 } 3955 3956 /** 3957 * intel_psr_unlock - release PSR lock 3958 * @crtc_state: the crtc state 3959 * 3960 * Release the PSR lock that was held during pipe update. 3961 */ 3962 void intel_psr_unlock(const struct intel_crtc_state *crtc_state) 3963 { 3964 struct intel_display *display = to_intel_display(crtc_state); 3965 struct intel_encoder *encoder; 3966 3967 if (!crtc_state->has_psr) 3968 return; 3969 3970 for_each_intel_encoder_mask_with_psr(display->drm, encoder, 3971 crtc_state->uapi.encoder_mask) { 3972 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 3973 3974 mutex_unlock(&intel_dp->psr.lock); 3975 break; 3976 } 3977 } 3978 3979 /* Wa_16025596647 */ 3980 static void intel_psr_apply_underrun_on_idle_wa_locked(struct intel_dp *intel_dp) 3981 { 3982 struct intel_display *display = to_intel_display(intel_dp); 3983 bool dc5_dc6_blocked; 3984 3985 if (!intel_dp->psr.active || !intel_dp->psr.pkg_c_latency_used) 3986 return; 3987 3988 dc5_dc6_blocked = is_dc5_dc6_blocked(intel_dp); 3989 3990 if (intel_dp->psr.sel_update_enabled) 3991 psr2_program_idle_frames(intel_dp, dc5_dc6_blocked ? 0 : 3992 psr_compute_idle_frames(intel_dp)); 3993 else 3994 intel_dmc_start_pkgc_exit_at_start_of_undelayed_vblank(display, 3995 intel_dp->psr.pipe, 3996 dc5_dc6_blocked); 3997 } 3998 3999 static void psr_dc5_dc6_wa_work(struct work_struct *work) 4000 { 4001 struct intel_display *display = container_of(work, typeof(*display), 4002 psr_dc5_dc6_wa_work); 4003 struct intel_encoder *encoder; 4004 4005 for_each_intel_encoder_with_psr(display->drm, encoder) { 4006 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 4007 4008 mutex_lock(&intel_dp->psr.lock); 4009 4010 if (intel_dp->psr.enabled && !intel_dp->psr.panel_replay_enabled && 4011 !intel_dp->psr.pkg_c_latency_used) 4012 intel_psr_apply_underrun_on_idle_wa_locked(intel_dp); 4013 4014 mutex_unlock(&intel_dp->psr.lock); 4015 } 4016 } 4017 4018 /** 4019 * intel_psr_notify_dc5_dc6 - Notify PSR about enable/disable dc5/dc6 4020 * @display: intel atomic state 4021 * 4022 * This is targeted for underrun on idle PSR HW bug (Wa_16025596647) to schedule 4023 * psr_dc5_dc6_wa_work used for applying/removing the workaround. 4024 */ 4025 void intel_psr_notify_dc5_dc6(struct intel_display *display) 4026 { 4027 if (!intel_display_wa(display, INTEL_DISPLAY_WA_16025596647)) 4028 return; 4029 4030 schedule_work(&display->psr_dc5_dc6_wa_work); 4031 } 4032 4033 /** 4034 * intel_psr_dc5_dc6_wa_init - Init work for underrun on idle PSR HW bug wa 4035 * @display: intel atomic state 4036 * 4037 * This is targeted for underrun on idle PSR HW bug (Wa_16025596647) to init 4038 * psr_dc5_dc6_wa_work used for applying the workaround. 4039 */ 4040 void intel_psr_dc5_dc6_wa_init(struct intel_display *display) 4041 { 4042 if (!intel_display_wa(display, INTEL_DISPLAY_WA_16025596647)) 4043 return; 4044 4045 INIT_WORK(&display->psr_dc5_dc6_wa_work, psr_dc5_dc6_wa_work); 4046 } 4047 4048 /** 4049 * intel_psr_notify_pipe_change - Notify PSR about enable/disable of a pipe 4050 * @state: intel atomic state 4051 * @crtc: intel crtc 4052 * @enable: enable/disable 4053 * 4054 * This is targeted for underrun on idle PSR HW bug (Wa_16025596647) to apply 4055 * remove the workaround when pipe is getting enabled/disabled 4056 */ 4057 void intel_psr_notify_pipe_change(struct intel_atomic_state *state, 4058 struct intel_crtc *crtc, bool enable) 4059 { 4060 struct intel_display *display = to_intel_display(state); 4061 struct intel_encoder *encoder; 4062 4063 if (!intel_display_wa(display, INTEL_DISPLAY_WA_16025596647)) 4064 return; 4065 4066 for_each_intel_encoder_with_psr(display->drm, encoder) { 4067 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 4068 u8 active_non_psr_pipes; 4069 4070 mutex_lock(&intel_dp->psr.lock); 4071 4072 if (!intel_dp->psr.enabled || intel_dp->psr.panel_replay_enabled) 4073 goto unlock; 4074 4075 active_non_psr_pipes = intel_dp->psr.active_non_psr_pipes; 4076 4077 if (enable) 4078 active_non_psr_pipes |= BIT(crtc->pipe); 4079 else 4080 active_non_psr_pipes &= ~BIT(crtc->pipe); 4081 4082 if (active_non_psr_pipes == intel_dp->psr.active_non_psr_pipes) 4083 goto unlock; 4084 4085 if ((enable && intel_dp->psr.active_non_psr_pipes) || 4086 (!enable && !intel_dp->psr.active_non_psr_pipes) || 4087 !intel_dp->psr.pkg_c_latency_used) { 4088 intel_dp->psr.active_non_psr_pipes = active_non_psr_pipes; 4089 goto unlock; 4090 } 4091 4092 intel_dp->psr.active_non_psr_pipes = active_non_psr_pipes; 4093 4094 intel_psr_apply_underrun_on_idle_wa_locked(intel_dp); 4095 unlock: 4096 mutex_unlock(&intel_dp->psr.lock); 4097 } 4098 } 4099 4100 /** 4101 * intel_psr_notify_vblank_enable_disable - Notify PSR about enable/disable of vblank 4102 * @display: intel display struct 4103 * @enable: enable/disable 4104 * 4105 * This is targeted for underrun on idle PSR HW bug (Wa_16025596647) to apply 4106 * remove the workaround when vblank is getting enabled/disabled 4107 */ 4108 void intel_psr_notify_vblank_enable_disable(struct intel_display *display, 4109 bool enable) 4110 { 4111 struct intel_encoder *encoder; 4112 4113 for_each_intel_encoder_with_psr(display->drm, encoder) { 4114 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 4115 4116 mutex_lock(&intel_dp->psr.lock); 4117 if (intel_dp->psr.panel_replay_enabled) { 4118 mutex_unlock(&intel_dp->psr.lock); 4119 break; 4120 } 4121 4122 if (intel_dp->psr.enabled && intel_dp->psr.pkg_c_latency_used) 4123 intel_psr_apply_underrun_on_idle_wa_locked(intel_dp); 4124 4125 mutex_unlock(&intel_dp->psr.lock); 4126 return; 4127 } 4128 4129 /* 4130 * NOTE: intel_display_power_set_target_dc_state is used 4131 * only by PSR * code for DC3CO handling. DC3CO target 4132 * state is currently disabled in * PSR code. If DC3CO 4133 * is taken into use we need take that into account here 4134 * as well. 4135 */ 4136 intel_display_power_set_target_dc_state(display, enable ? DC_STATE_DISABLE : 4137 DC_STATE_EN_UPTO_DC6); 4138 } 4139 4140 static void 4141 psr_source_status(struct intel_dp *intel_dp, struct seq_file *m) 4142 { 4143 struct intel_display *display = to_intel_display(intel_dp); 4144 enum transcoder cpu_transcoder = intel_dp->psr.transcoder; 4145 const char *status = "unknown"; 4146 u32 val, status_val; 4147 4148 if ((intel_dp_is_edp(intel_dp) || DISPLAY_VER(display) >= 30) && 4149 (intel_dp->psr.sel_update_enabled || intel_dp->psr.panel_replay_enabled)) { 4150 static const char * const live_status[] = { 4151 "IDLE", 4152 "CAPTURE", 4153 "CAPTURE_FS", 4154 "SLEEP", 4155 "BUFON_FW", 4156 "ML_UP", 4157 "SU_STANDBY", 4158 "FAST_SLEEP", 4159 "DEEP_SLEEP", 4160 "BUF_ON", 4161 "TG_ON" 4162 }; 4163 val = intel_de_read(display, 4164 EDP_PSR2_STATUS(display, cpu_transcoder)); 4165 status_val = REG_FIELD_GET(EDP_PSR2_STATUS_STATE_MASK, val); 4166 if (status_val < ARRAY_SIZE(live_status)) 4167 status = live_status[status_val]; 4168 } else { 4169 static const char * const live_status[] = { 4170 "IDLE", 4171 "SRDONACK", 4172 "SRDENT", 4173 "BUFOFF", 4174 "BUFON", 4175 "AUXACK", 4176 "SRDOFFACK", 4177 "SRDENT_ON", 4178 }; 4179 val = intel_de_read(display, 4180 psr_status_reg(display, cpu_transcoder)); 4181 status_val = REG_FIELD_GET(EDP_PSR_STATUS_STATE_MASK, val); 4182 if (status_val < ARRAY_SIZE(live_status)) 4183 status = live_status[status_val]; 4184 } 4185 4186 seq_printf(m, "Source PSR/PanelReplay status: %s [0x%08x]\n", status, val); 4187 } 4188 4189 static void intel_psr_sink_capability(struct intel_connector *connector, 4190 struct seq_file *m) 4191 { 4192 seq_printf(m, "Sink support: PSR = %s", 4193 str_yes_no(connector->dp.psr_caps.support)); 4194 4195 if (connector->dp.psr_caps.support) 4196 seq_printf(m, " [0x%02x]", connector->dp.psr_caps.dpcd[0]); 4197 if (connector->dp.psr_caps.dpcd[0] == DP_PSR2_WITH_Y_COORD_ET_SUPPORTED) 4198 seq_printf(m, " (Early Transport)"); 4199 seq_printf(m, ", Panel Replay = %s", str_yes_no(connector->dp.panel_replay_caps.support)); 4200 seq_printf(m, ", Panel Replay Selective Update = %s", 4201 str_yes_no(connector->dp.panel_replay_caps.su_support)); 4202 seq_printf(m, ", Panel Replay DSC support = %s", 4203 panel_replay_dsc_support_str(connector->dp.panel_replay_caps.dsc_support)); 4204 if (connector->dp.panel_replay_caps.dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_SUPPORT)] & 4205 DP_PANEL_REPLAY_EARLY_TRANSPORT_SUPPORT) 4206 seq_printf(m, " (Early Transport)"); 4207 seq_printf(m, "\n"); 4208 } 4209 4210 static void intel_psr_print_mode(struct intel_dp *intel_dp, 4211 struct seq_file *m) 4212 { 4213 struct intel_psr *psr = &intel_dp->psr; 4214 const char *status, *mode, *region_et; 4215 4216 if (psr->enabled) 4217 status = " enabled"; 4218 else 4219 status = "disabled"; 4220 4221 if (psr->panel_replay_enabled && psr->sel_update_enabled) 4222 mode = "Panel Replay Selective Update"; 4223 else if (psr->panel_replay_enabled) 4224 mode = "Panel Replay"; 4225 else if (psr->sel_update_enabled) 4226 mode = "PSR2"; 4227 else if (psr->enabled) 4228 mode = "PSR1"; 4229 else 4230 mode = ""; 4231 4232 if (psr->su_region_et_enabled) 4233 region_et = " (Early Transport)"; 4234 else 4235 region_et = ""; 4236 4237 seq_printf(m, "PSR mode: %s%s%s\n", mode, status, region_et); 4238 if (psr->no_psr_reason) 4239 seq_printf(m, " %s\n", psr->no_psr_reason); 4240 } 4241 4242 static int intel_psr_status(struct seq_file *m, struct intel_dp *intel_dp, 4243 struct intel_connector *connector) 4244 { 4245 struct intel_display *display = to_intel_display(intel_dp); 4246 enum transcoder cpu_transcoder = intel_dp->psr.transcoder; 4247 struct intel_psr *psr = &intel_dp->psr; 4248 struct ref_tracker *wakeref; 4249 bool enabled; 4250 u32 val, psr2_ctl; 4251 4252 intel_psr_sink_capability(connector, m); 4253 4254 if (!(connector->dp.psr_caps.support || connector->dp.panel_replay_caps.support)) 4255 return 0; 4256 4257 wakeref = intel_display_rpm_get(display); 4258 mutex_lock(&psr->lock); 4259 4260 intel_psr_print_mode(intel_dp, m); 4261 4262 if (!psr->enabled) { 4263 seq_printf(m, "PSR sink not reliable: %s\n", 4264 str_yes_no(psr->sink_not_reliable)); 4265 4266 goto unlock; 4267 } 4268 4269 if (psr->panel_replay_enabled) { 4270 val = intel_de_read(display, TRANS_DP2_CTL(cpu_transcoder)); 4271 4272 if (intel_dp_is_edp(intel_dp)) 4273 psr2_ctl = intel_de_read(display, 4274 EDP_PSR2_CTL(display, 4275 cpu_transcoder)); 4276 4277 enabled = val & TRANS_DP2_PANEL_REPLAY_ENABLE; 4278 } else if (psr->sel_update_enabled) { 4279 val = intel_de_read(display, 4280 EDP_PSR2_CTL(display, cpu_transcoder)); 4281 enabled = val & EDP_PSR2_ENABLE; 4282 } else { 4283 val = intel_de_read(display, psr_ctl_reg(display, cpu_transcoder)); 4284 enabled = val & EDP_PSR_ENABLE; 4285 } 4286 seq_printf(m, "Source PSR/PanelReplay ctl: %s [0x%08x]\n", 4287 str_enabled_disabled(enabled), val); 4288 if (psr->panel_replay_enabled && intel_dp_is_edp(intel_dp)) 4289 seq_printf(m, "PSR2_CTL: 0x%08x\n", 4290 psr2_ctl); 4291 psr_source_status(intel_dp, m); 4292 seq_printf(m, "Busy frontbuffer bits: 0x%08x\n", 4293 psr->busy_frontbuffer_bits); 4294 4295 /* 4296 * SKL+ Perf counter is reset to 0 everytime DC state is entered 4297 */ 4298 val = intel_de_read(display, psr_perf_cnt_reg(display, cpu_transcoder)); 4299 seq_printf(m, "Performance counter: %u\n", 4300 REG_FIELD_GET(EDP_PSR_PERF_CNT_MASK, val)); 4301 4302 if (psr->debug & I915_PSR_DEBUG_IRQ) { 4303 seq_printf(m, "Last attempted entry at: %lld\n", 4304 psr->last_entry_attempt); 4305 seq_printf(m, "Last exit at: %lld\n", psr->last_exit); 4306 } 4307 4308 if (psr->sel_update_enabled) { 4309 u32 su_frames_val[3]; 4310 int frame; 4311 4312 /* 4313 * PSR2_SU_STATUS register has been tied-off since DG2/ADL-P 4314 * (it returns zeros only) and it has been removed on Xe2_LPD. 4315 */ 4316 if (DISPLAY_VER(display) < 13) { 4317 /* 4318 * Reading all 3 registers before hand to minimize crossing a 4319 * frame boundary between register reads 4320 */ 4321 for (frame = 0; frame < PSR2_SU_STATUS_FRAMES; frame += 3) { 4322 val = intel_de_read(display, 4323 PSR2_SU_STATUS(display, cpu_transcoder, frame)); 4324 su_frames_val[frame / 3] = val; 4325 } 4326 4327 seq_puts(m, "Frame:\tPSR2 SU blocks:\n"); 4328 4329 for (frame = 0; frame < PSR2_SU_STATUS_FRAMES; frame++) { 4330 u32 su_blocks; 4331 4332 su_blocks = su_frames_val[frame / 3] & 4333 PSR2_SU_STATUS_MASK(frame); 4334 su_blocks = su_blocks >> PSR2_SU_STATUS_SHIFT(frame); 4335 seq_printf(m, "%d\t%d\n", frame, su_blocks); 4336 } 4337 } 4338 4339 seq_printf(m, "PSR2 selective fetch: %s\n", 4340 str_enabled_disabled(psr->psr2_sel_fetch_enabled)); 4341 } 4342 4343 unlock: 4344 mutex_unlock(&psr->lock); 4345 intel_display_rpm_put(display, wakeref); 4346 4347 return 0; 4348 } 4349 4350 static int i915_edp_psr_status_show(struct seq_file *m, void *data) 4351 { 4352 struct intel_display *display = m->private; 4353 struct intel_dp *intel_dp = NULL; 4354 struct intel_encoder *encoder; 4355 4356 if (!HAS_PSR(display)) 4357 return -ENODEV; 4358 4359 /* Find the first EDP which supports PSR */ 4360 for_each_intel_encoder_with_psr(display->drm, encoder) { 4361 intel_dp = enc_to_intel_dp(encoder); 4362 break; 4363 } 4364 4365 if (!intel_dp) 4366 return -ENODEV; 4367 4368 return intel_psr_status(m, intel_dp, intel_dp->attached_connector); 4369 } 4370 DEFINE_SHOW_ATTRIBUTE(i915_edp_psr_status); 4371 4372 static int 4373 i915_edp_psr_debug_set(void *data, u64 val) 4374 { 4375 struct intel_display *display = data; 4376 struct intel_encoder *encoder; 4377 int ret = -ENODEV; 4378 4379 if (!HAS_PSR(display)) 4380 return ret; 4381 4382 for_each_intel_encoder_with_psr(display->drm, encoder) { 4383 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 4384 4385 drm_dbg_kms(display->drm, "Setting PSR debug to %llx\n", val); 4386 4387 // TODO: split to each transcoder's PSR debug state 4388 with_intel_display_rpm(display) 4389 ret = intel_psr_debug_set(intel_dp, val); 4390 } 4391 4392 return ret; 4393 } 4394 4395 static int 4396 i915_edp_psr_debug_get(void *data, u64 *val) 4397 { 4398 struct intel_display *display = data; 4399 struct intel_encoder *encoder; 4400 4401 if (!HAS_PSR(display)) 4402 return -ENODEV; 4403 4404 for_each_intel_encoder_with_psr(display->drm, encoder) { 4405 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 4406 4407 // TODO: split to each transcoder's PSR debug state 4408 *val = READ_ONCE(intel_dp->psr.debug); 4409 return 0; 4410 } 4411 4412 return -ENODEV; 4413 } 4414 4415 DEFINE_SIMPLE_ATTRIBUTE(i915_edp_psr_debug_fops, 4416 i915_edp_psr_debug_get, i915_edp_psr_debug_set, 4417 "%llu\n"); 4418 4419 void intel_psr_debugfs_register(struct intel_display *display) 4420 { 4421 struct dentry *debugfs_root = display->drm->debugfs_root; 4422 4423 debugfs_create_file("i915_edp_psr_debug", 0644, debugfs_root, 4424 display, &i915_edp_psr_debug_fops); 4425 4426 debugfs_create_file("i915_edp_psr_status", 0444, debugfs_root, 4427 display, &i915_edp_psr_status_fops); 4428 } 4429 4430 static const char *psr_mode_str(struct intel_dp *intel_dp) 4431 { 4432 if (intel_dp->psr.panel_replay_enabled) 4433 return "PANEL-REPLAY"; 4434 else if (intel_dp->psr.enabled) 4435 return "PSR"; 4436 4437 return "unknown"; 4438 } 4439 4440 static int i915_psr_sink_status_show(struct seq_file *m, void *data) 4441 { 4442 struct intel_connector *connector = m->private; 4443 struct intel_dp *intel_dp = intel_attached_dp(connector); 4444 static const char * const sink_status[] = { 4445 "inactive", 4446 "transition to active, capture and display", 4447 "active, display from RFB", 4448 "active, capture and display on sink device timings", 4449 "transition to inactive, capture and display, timing re-sync", 4450 "reserved", 4451 "reserved", 4452 "sink internal error", 4453 }; 4454 const char *str; 4455 int ret; 4456 u8 status, error_status; 4457 4458 if (!(CAN_PSR(intel_dp) || CAN_PANEL_REPLAY(intel_dp))) { 4459 seq_puts(m, "PSR/Panel-Replay Unsupported\n"); 4460 return -ENODEV; 4461 } 4462 4463 if (connector->base.status != connector_status_connected) 4464 return -ENODEV; 4465 4466 ret = psr_get_status_and_error_status(intel_dp, &status, &error_status); 4467 if (ret) 4468 return ret; 4469 4470 status &= DP_PSR_SINK_STATE_MASK; 4471 if (status < ARRAY_SIZE(sink_status)) 4472 str = sink_status[status]; 4473 else 4474 str = "unknown"; 4475 4476 seq_printf(m, "Sink %s status: 0x%x [%s]\n", psr_mode_str(intel_dp), status, str); 4477 4478 seq_printf(m, "Sink %s error status: 0x%x", psr_mode_str(intel_dp), error_status); 4479 4480 if (error_status & (DP_PSR_RFB_STORAGE_ERROR | 4481 DP_PSR_VSC_SDP_UNCORRECTABLE_ERROR | 4482 DP_PSR_LINK_CRC_ERROR)) 4483 seq_puts(m, ":\n"); 4484 else 4485 seq_puts(m, "\n"); 4486 if (error_status & DP_PSR_RFB_STORAGE_ERROR) 4487 seq_printf(m, "\t%s RFB storage error\n", psr_mode_str(intel_dp)); 4488 if (error_status & DP_PSR_VSC_SDP_UNCORRECTABLE_ERROR) 4489 seq_printf(m, "\t%s VSC SDP uncorrectable error\n", psr_mode_str(intel_dp)); 4490 if (error_status & DP_PSR_LINK_CRC_ERROR) 4491 seq_printf(m, "\t%s Link CRC error\n", psr_mode_str(intel_dp)); 4492 4493 return ret; 4494 } 4495 DEFINE_SHOW_ATTRIBUTE(i915_psr_sink_status); 4496 4497 static int i915_psr_status_show(struct seq_file *m, void *data) 4498 { 4499 struct intel_connector *connector = m->private; 4500 struct intel_dp *intel_dp = intel_attached_dp(connector); 4501 4502 return intel_psr_status(m, intel_dp, connector); 4503 } 4504 DEFINE_SHOW_ATTRIBUTE(i915_psr_status); 4505 4506 void intel_psr_connector_debugfs_add(struct intel_connector *connector) 4507 { 4508 struct intel_display *display = to_intel_display(connector); 4509 struct dentry *root = connector->base.debugfs_entry; 4510 4511 if (connector->base.connector_type != DRM_MODE_CONNECTOR_eDP && 4512 connector->base.connector_type != DRM_MODE_CONNECTOR_DisplayPort) 4513 return; 4514 4515 debugfs_create_file("i915_psr_sink_status", 0444, root, 4516 connector, &i915_psr_sink_status_fops); 4517 4518 if (HAS_PSR(display) || HAS_DP20(display)) 4519 debugfs_create_file("i915_psr_status", 0444, root, 4520 connector, &i915_psr_status_fops); 4521 } 4522 4523 bool intel_psr_needs_alpm(struct intel_dp *intel_dp, const struct intel_crtc_state *crtc_state) 4524 { 4525 /* 4526 * eDP Panel Replay uses always ALPM 4527 * PSR2 uses ALPM but PSR1 doesn't 4528 */ 4529 return intel_dp_is_edp(intel_dp) && (crtc_state->has_sel_update || 4530 crtc_state->has_panel_replay); 4531 } 4532 4533 bool intel_psr_needs_alpm_aux_less(struct intel_dp *intel_dp, 4534 const struct intel_crtc_state *crtc_state) 4535 { 4536 return intel_dp_is_edp(intel_dp) && crtc_state->has_panel_replay; 4537 } 4538 4539 void intel_psr_compute_config_late(struct intel_dp *intel_dp, 4540 struct intel_crtc_state *crtc_state) 4541 { 4542 struct intel_display *display = to_intel_display(intel_dp); 4543 int vblank = intel_crtc_vblank_length(crtc_state); 4544 int wake_lines; 4545 4546 if (intel_psr_needs_alpm_aux_less(intel_dp, crtc_state)) 4547 wake_lines = crtc_state->alpm_state.aux_less_wake_lines; 4548 else if (intel_psr_needs_alpm(intel_dp, crtc_state)) 4549 wake_lines = DISPLAY_VER(display) < 20 ? 4550 psr2_block_count_lines(crtc_state->alpm_state.io_wake_lines, 4551 crtc_state->alpm_state.fast_wake_lines) : 4552 crtc_state->alpm_state.io_wake_lines; 4553 else 4554 wake_lines = 0; 4555 4556 /* 4557 * Disable the PSR features if wake lines exceed the available vblank. 4558 * Though SCL is computed based on these PSR features, it is not reset 4559 * even if the PSR features are disabled to avoid changing vblank start 4560 * at this stage. 4561 */ 4562 if (wake_lines && !_wake_lines_fit_into_vblank(crtc_state, vblank, wake_lines)) { 4563 drm_dbg_kms(display->drm, 4564 "Adjusting PSR/PR mode: vblank too short for wake lines = %d\n", 4565 wake_lines); 4566 4567 if (crtc_state->has_panel_replay) { 4568 crtc_state->has_panel_replay = false; 4569 /* 4570 * #TODO : Add fall back to PSR/PSR2 4571 * Since panel replay cannot be supported, we can fall back to PSR/PSR2. 4572 * This will require calling compute_config for psr and psr2 with check for 4573 * actual guardband instead of vblank_length. 4574 */ 4575 crtc_state->has_psr = false; 4576 } 4577 4578 crtc_state->has_sel_update = false; 4579 crtc_state->enable_psr2_su_region_et = false; 4580 crtc_state->enable_psr2_sel_fetch = false; 4581 } 4582 4583 /* Wa_18037818876 */ 4584 if (intel_psr_needs_wa_18037818876(intel_dp, crtc_state)) { 4585 crtc_state->has_psr = false; 4586 drm_dbg_kms(display->drm, 4587 "PSR disabled to workaround PSR FSM hang issue\n"); 4588 } 4589 4590 intel_psr_set_non_psr_pipes(intel_dp, crtc_state); 4591 } 4592 4593 int intel_psr_min_guardband(struct intel_crtc_state *crtc_state) 4594 { 4595 struct intel_display *display = to_intel_display(crtc_state); 4596 int psr_min_guardband; 4597 int wake_lines; 4598 4599 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) 4600 return 0; 4601 4602 if (crtc_state->has_panel_replay) 4603 wake_lines = crtc_state->alpm_state.aux_less_wake_lines; 4604 else if (crtc_state->has_sel_update) 4605 wake_lines = DISPLAY_VER(display) < 20 ? 4606 psr2_block_count_lines(crtc_state->alpm_state.io_wake_lines, 4607 crtc_state->alpm_state.fast_wake_lines) : 4608 crtc_state->alpm_state.io_wake_lines; 4609 else 4610 return 0; 4611 4612 psr_min_guardband = wake_lines + crtc_state->set_context_latency; 4613 4614 if (crtc_state->req_psr2_sdp_prior_scanline) 4615 psr_min_guardband++; 4616 4617 return psr_min_guardband; 4618 } 4619 4620 bool intel_psr_use_trans_push(const struct intel_crtc_state *crtc_state) 4621 { 4622 struct intel_display *display = to_intel_display(crtc_state); 4623 4624 return HAS_PSR_TRANS_PUSH_FRAME_CHANGE(display) && crtc_state->has_psr; 4625 } 4626