1 /* 2 * Copyright © 2014 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 */ 23 24 #include <linux/debugfs.h> 25 26 #include <drm/drm_atomic_helper.h> 27 #include <drm/drm_damage_helper.h> 28 #include <drm/drm_debugfs.h> 29 #include <drm/drm_print.h> 30 #include <drm/drm_vblank.h> 31 #include <drm/intel/step.h> 32 33 #include "intel_alpm.h" 34 #include "intel_atomic.h" 35 #include "intel_crtc.h" 36 #include "intel_cursor_regs.h" 37 #include "intel_ddi.h" 38 #include "intel_de.h" 39 #include "intel_display_irq.h" 40 #include "intel_display_regs.h" 41 #include "intel_display_rpm.h" 42 #include "intel_display_types.h" 43 #include "intel_display_utils.h" 44 #include "intel_display_wa.h" 45 #include "intel_dmc.h" 46 #include "intel_dp.h" 47 #include "intel_dpcd.h" 48 #include "intel_dp_aux.h" 49 #include "intel_dp_tunnel.h" 50 #include "intel_dsb.h" 51 #include "intel_frontbuffer.h" 52 #include "intel_hdmi.h" 53 #include "intel_psr.h" 54 #include "intel_psr_regs.h" 55 #include "intel_quirks.h" 56 #include "intel_snps_phy.h" 57 #include "intel_vblank.h" 58 #include "intel_vdsc.h" 59 #include "intel_vrr.h" 60 #include "skl_universal_plane.h" 61 62 /** 63 * DOC: Panel Self Refresh (PSR/SRD) 64 * 65 * Since Haswell Display controller supports Panel Self-Refresh on display 66 * panels witch have a remote frame buffer (RFB) implemented according to PSR 67 * spec in eDP1.3. PSR feature allows the display to go to lower standby states 68 * when system is idle but display is on as it eliminates display refresh 69 * request to DDR memory completely as long as the frame buffer for that 70 * display is unchanged. 71 * 72 * Panel Self Refresh must be supported by both Hardware (source) and 73 * Panel (sink). 74 * 75 * PSR saves power by caching the framebuffer in the panel RFB, which allows us 76 * to power down the link and memory controller. For DSI panels the same idea 77 * is called "manual mode". 78 * 79 * The implementation uses the hardware-based PSR support which automatically 80 * enters/exits self-refresh mode. The hardware takes care of sending the 81 * required DP aux message and could even retrain the link (that part isn't 82 * enabled yet though). The hardware also keeps track of any frontbuffer 83 * changes to know when to exit self-refresh mode again. Unfortunately that 84 * part doesn't work too well, hence why the i915 PSR support uses the 85 * software frontbuffer tracking to make sure it doesn't miss a screen 86 * update. For this integration intel_psr_invalidate() and intel_psr_flush() 87 * get called by the frontbuffer tracking code. Note that because of locking 88 * issues the self-refresh re-enable code is done from a work queue, which 89 * must be correctly synchronized/cancelled when shutting down the pipe." 90 * 91 */ 92 93 /* 94 * Description of PSR mask bits: 95 * 96 * EDP_PSR_DEBUG[16]/EDP_PSR_DEBUG_MASK_DISP_REG_WRITE (hsw-skl): 97 * 98 * When unmasked (nearly) all display register writes (eg. even 99 * SWF) trigger a PSR exit. Some registers are excluded from this 100 * and they have a more specific mask (described below). On icl+ 101 * this bit no longer exists and is effectively always set. 102 * 103 * PIPE_MISC[21]/PIPE_MISC_PSR_MASK_PIPE_REG_WRITE (skl+): 104 * 105 * When unmasked (nearly) all pipe/plane register writes 106 * trigger a PSR exit. Some plane registers are excluded from this 107 * and they have a more specific mask (described below). 108 * 109 * CHICKEN_PIPESL_1[11]/SKL_PSR_MASK_PLANE_FLIP (skl+): 110 * PIPE_MISC[23]/PIPE_MISC_PSR_MASK_PRIMARY_FLIP (bdw): 111 * EDP_PSR_DEBUG[23]/EDP_PSR_DEBUG_MASK_PRIMARY_FLIP (hsw): 112 * 113 * When unmasked PRI_SURF/PLANE_SURF writes trigger a PSR exit. 114 * SPR_SURF/CURBASE are not included in this and instead are 115 * controlled by PIPE_MISC_PSR_MASK_PIPE_REG_WRITE (skl+) or 116 * EDP_PSR_DEBUG_MASK_DISP_REG_WRITE (hsw/bdw). 117 * 118 * PIPE_MISC[22]/PIPE_MISC_PSR_MASK_SPRITE_ENABLE (bdw): 119 * EDP_PSR_DEBUG[21]/EDP_PSR_DEBUG_MASK_SPRITE_ENABLE (hsw): 120 * 121 * When unmasked PSR is blocked as long as the sprite 122 * plane is enabled. skl+ with their universal planes no 123 * longer have a mask bit like this, and no plane being 124 * enabledb blocks PSR. 125 * 126 * PIPE_MISC[21]/PIPE_MISC_PSR_MASK_CURSOR_MOVE (bdw): 127 * EDP_PSR_DEBUG[20]/EDP_PSR_DEBUG_MASK_CURSOR_MOVE (hsw): 128 * 129 * When umasked CURPOS writes trigger a PSR exit. On skl+ 130 * this doesn't exit but CURPOS is included in the 131 * PIPE_MISC_PSR_MASK_PIPE_REG_WRITE mask. 132 * 133 * PIPE_MISC[20]/PIPE_MISC_PSR_MASK_VBLANK_VSYNC_INT (bdw+): 134 * EDP_PSR_DEBUG[19]/EDP_PSR_DEBUG_MASK_VBLANK_VSYNC_INT (hsw): 135 * 136 * When unmasked PSR is blocked as long as vblank and/or vsync 137 * interrupt is unmasked in IMR *and* enabled in IER. 138 * 139 * CHICKEN_TRANS[30]/SKL_UNMASK_VBL_TO_PIPE_IN_SRD (skl+): 140 * CHICKEN_PAR1_1[15]/HSW_MASK_VBL_TO_PIPE_IN_SRD (hsw/bdw): 141 * 142 * Selectcs whether PSR exit generates an extra vblank before 143 * the first frame is transmitted. Also note the opposite polarity 144 * if the bit on hsw/bdw vs. skl+ (masked==generate the extra vblank, 145 * unmasked==do not generate the extra vblank). 146 * 147 * With DC states enabled the extra vblank happens after link training, 148 * with DC states disabled it happens immediately upuon PSR exit trigger. 149 * No idea as of now why there is a difference. HSW/BDW (which don't 150 * even have DMC) always generate it after link training. Go figure. 151 * 152 * Unfortunately CHICKEN_TRANS itself seems to be double buffered 153 * and thus won't latch until the first vblank. So with DC states 154 * enabled the register effectively uses the reset value during DC5 155 * exit+PSR exit sequence, and thus the bit does nothing until 156 * latched by the vblank that it was trying to prevent from being 157 * generated in the first place. So we should probably call this 158 * one a chicken/egg bit instead on skl+. 159 * 160 * In standby mode (as opposed to link-off) this makes no difference 161 * as the timing generator keeps running the whole time generating 162 * normal periodic vblanks. 163 * 164 * WaPsrDPAMaskVBlankInSRD asks us to set the bit on hsw/bdw, 165 * and doing so makes the behaviour match the skl+ reset value. 166 * 167 * CHICKEN_PIPESL_1[0]/BDW_UNMASK_VBL_TO_REGS_IN_SRD (bdw): 168 * CHICKEN_PIPESL_1[15]/HSW_UNMASK_VBL_TO_REGS_IN_SRD (hsw): 169 * 170 * On BDW without this bit is no vblanks whatsoever are 171 * generated after PSR exit. On HSW this has no apparent effect. 172 * WaPsrDPRSUnmaskVBlankInSRD says to set this. 173 * 174 * The rest of the bits are more self-explanatory and/or 175 * irrelevant for normal operation. 176 * 177 * Description of intel_crtc_state variables. has_psr, has_panel_replay and 178 * has_sel_update: 179 * 180 * has_psr (alone): PSR1 181 * has_psr + has_sel_update: PSR2 182 * has_psr + has_panel_replay: Panel Replay 183 * has_psr + has_panel_replay + has_sel_update: Panel Replay Selective Update 184 * 185 * Description of some intel_psr variables. enabled, panel_replay_enabled, 186 * sel_update_enabled 187 * 188 * enabled (alone): PSR1 189 * enabled + sel_update_enabled: PSR2 190 * enabled + panel_replay_enabled: Panel Replay 191 * enabled + panel_replay_enabled + sel_update_enabled: Panel Replay SU 192 */ 193 194 #define CAN_PSR(intel_dp) ((intel_dp)->psr.sink_support && \ 195 (intel_dp)->psr.source_support) 196 197 bool intel_encoder_can_psr(struct intel_encoder *encoder) 198 { 199 if (intel_encoder_is_dp(encoder) || encoder->type == INTEL_OUTPUT_DP_MST) 200 return CAN_PSR(enc_to_intel_dp(encoder)) || 201 CAN_PANEL_REPLAY(enc_to_intel_dp(encoder)); 202 else 203 return false; 204 } 205 206 bool intel_psr_needs_aux_io_power(struct intel_encoder *encoder, 207 const struct intel_crtc_state *crtc_state) 208 { 209 /* 210 * For PSR/PR modes only eDP requires the AUX IO power to be enabled whenever 211 * the output is enabled. For non-eDP outputs the main link is always 212 * on, hence it doesn't require the HW initiated AUX wake-up signaling used 213 * for eDP. 214 * 215 * TODO: 216 * - Consider leaving AUX IO disabled for eDP / PR as well, in case 217 * the ALPM with main-link off mode is not enabled. 218 * - Leave AUX IO enabled for DP / PR, once support for ALPM with 219 * main-link off mode is added for it and this mode gets enabled. 220 */ 221 return intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP) && 222 intel_encoder_can_psr(encoder); 223 } 224 225 static bool psr_global_enabled(struct intel_dp *intel_dp) 226 { 227 struct intel_connector *connector = intel_dp->attached_connector; 228 229 switch (intel_dp->psr.debug & I915_PSR_DEBUG_MODE_MASK) { 230 case I915_PSR_DEBUG_DEFAULT: 231 return intel_dp_is_edp(intel_dp) ? 232 connector->panel.vbt.psr.enable : true; 233 case I915_PSR_DEBUG_DISABLE: 234 return false; 235 default: 236 return true; 237 } 238 } 239 240 static bool sel_update_global_enabled(struct intel_dp *intel_dp) 241 { 242 switch (intel_dp->psr.debug & I915_PSR_DEBUG_MODE_MASK) { 243 case I915_PSR_DEBUG_DISABLE: 244 case I915_PSR_DEBUG_FORCE_PSR1: 245 return false; 246 default: 247 return true; 248 } 249 } 250 251 static bool panel_replay_global_enabled(struct intel_dp *intel_dp) 252 { 253 struct intel_display *display = to_intel_display(intel_dp); 254 255 return !(intel_dp->psr.debug & I915_PSR_DEBUG_PANEL_REPLAY_DISABLE) && 256 display->params.enable_panel_replay; 257 } 258 259 static u32 psr_irq_psr_error_bit_get(struct intel_dp *intel_dp) 260 { 261 struct intel_display *display = to_intel_display(intel_dp); 262 263 return DISPLAY_VER(display) >= 12 ? TGL_PSR_ERROR : 264 EDP_PSR_ERROR(intel_dp->psr.transcoder); 265 } 266 267 static u32 psr_irq_post_exit_bit_get(struct intel_dp *intel_dp) 268 { 269 struct intel_display *display = to_intel_display(intel_dp); 270 271 return DISPLAY_VER(display) >= 12 ? TGL_PSR_POST_EXIT : 272 EDP_PSR_POST_EXIT(intel_dp->psr.transcoder); 273 } 274 275 static u32 psr_irq_pre_entry_bit_get(struct intel_dp *intel_dp) 276 { 277 struct intel_display *display = to_intel_display(intel_dp); 278 279 return DISPLAY_VER(display) >= 12 ? TGL_PSR_PRE_ENTRY : 280 EDP_PSR_PRE_ENTRY(intel_dp->psr.transcoder); 281 } 282 283 static u32 psr_irq_mask_get(struct intel_dp *intel_dp) 284 { 285 struct intel_display *display = to_intel_display(intel_dp); 286 287 return DISPLAY_VER(display) >= 12 ? TGL_PSR_MASK : 288 EDP_PSR_MASK(intel_dp->psr.transcoder); 289 } 290 291 static intel_reg_t psr_ctl_reg(struct intel_display *display, 292 enum transcoder cpu_transcoder) 293 { 294 if (DISPLAY_VER(display) >= 8) 295 return EDP_PSR_CTL(display, cpu_transcoder); 296 else 297 return HSW_SRD_CTL; 298 } 299 300 static intel_reg_t psr_debug_reg(struct intel_display *display, 301 enum transcoder cpu_transcoder) 302 { 303 if (DISPLAY_VER(display) >= 8) 304 return EDP_PSR_DEBUG(display, cpu_transcoder); 305 else 306 return HSW_SRD_DEBUG; 307 } 308 309 static intel_reg_t psr_perf_cnt_reg(struct intel_display *display, 310 enum transcoder cpu_transcoder) 311 { 312 if (DISPLAY_VER(display) >= 8) 313 return EDP_PSR_PERF_CNT(display, cpu_transcoder); 314 else 315 return HSW_SRD_PERF_CNT; 316 } 317 318 static intel_reg_t psr_status_reg(struct intel_display *display, 319 enum transcoder cpu_transcoder) 320 { 321 if (DISPLAY_VER(display) >= 8) 322 return EDP_PSR_STATUS(display, cpu_transcoder); 323 else 324 return HSW_SRD_STATUS; 325 } 326 327 static intel_reg_t psr_imr_reg(struct intel_display *display, 328 enum transcoder cpu_transcoder) 329 { 330 if (DISPLAY_VER(display) >= 12) 331 return TRANS_PSR_IMR(display, cpu_transcoder); 332 else 333 return EDP_PSR_IMR; 334 } 335 336 static intel_reg_t psr_iir_reg(struct intel_display *display, 337 enum transcoder cpu_transcoder) 338 { 339 if (DISPLAY_VER(display) >= 12) 340 return TRANS_PSR_IIR(display, cpu_transcoder); 341 else 342 return EDP_PSR_IIR; 343 } 344 345 static intel_reg_t psr_aux_ctl_reg(struct intel_display *display, 346 enum transcoder cpu_transcoder) 347 { 348 if (DISPLAY_VER(display) >= 8) 349 return EDP_PSR_AUX_CTL(display, cpu_transcoder); 350 else 351 return HSW_SRD_AUX_CTL; 352 } 353 354 static intel_reg_t psr_aux_data_reg(struct intel_display *display, 355 enum transcoder cpu_transcoder, int i) 356 { 357 if (DISPLAY_VER(display) >= 8) 358 return EDP_PSR_AUX_DATA(display, cpu_transcoder, i); 359 else 360 return HSW_SRD_AUX_DATA(i); 361 } 362 363 static void psr_irq_control(struct intel_dp *intel_dp) 364 { 365 struct intel_display *display = to_intel_display(intel_dp); 366 enum transcoder cpu_transcoder = intel_dp->psr.transcoder; 367 u32 mask; 368 369 if (intel_dp->psr.panel_replay_enabled) 370 return; 371 372 mask = psr_irq_psr_error_bit_get(intel_dp); 373 if (intel_dp->psr.debug & I915_PSR_DEBUG_IRQ) 374 mask |= psr_irq_post_exit_bit_get(intel_dp) | 375 psr_irq_pre_entry_bit_get(intel_dp); 376 377 intel_de_rmw(display, psr_imr_reg(display, cpu_transcoder), 378 psr_irq_mask_get(intel_dp), ~mask); 379 } 380 381 static void psr_event_print(struct intel_display *display, 382 u32 val, bool sel_update_enabled) 383 { 384 drm_dbg_kms(display->drm, "PSR exit events: 0x%x\n", val); 385 if (val & PSR_EVENT_PSR2_WD_TIMER_EXPIRE) 386 drm_dbg_kms(display->drm, "\tPSR2 watchdog timer expired\n"); 387 if ((val & PSR_EVENT_PSR2_DISABLED) && sel_update_enabled) 388 drm_dbg_kms(display->drm, "\tPSR2 disabled\n"); 389 if (val & PSR_EVENT_SU_DIRTY_FIFO_UNDERRUN) 390 drm_dbg_kms(display->drm, "\tSU dirty FIFO underrun\n"); 391 if (val & PSR_EVENT_SU_CRC_FIFO_UNDERRUN) 392 drm_dbg_kms(display->drm, "\tSU CRC FIFO underrun\n"); 393 if (val & PSR_EVENT_GRAPHICS_RESET) 394 drm_dbg_kms(display->drm, "\tGraphics reset\n"); 395 if (val & PSR_EVENT_PCH_INTERRUPT) 396 drm_dbg_kms(display->drm, "\tPCH interrupt\n"); 397 if (val & PSR_EVENT_MEMORY_UP) 398 drm_dbg_kms(display->drm, "\tMemory up\n"); 399 if (val & PSR_EVENT_FRONT_BUFFER_MODIFY) 400 drm_dbg_kms(display->drm, "\tFront buffer modification\n"); 401 if (val & PSR_EVENT_WD_TIMER_EXPIRE) 402 drm_dbg_kms(display->drm, "\tPSR watchdog timer expired\n"); 403 if (val & PSR_EVENT_PIPE_REGISTERS_UPDATE) 404 drm_dbg_kms(display->drm, "\tPIPE registers updated\n"); 405 if (val & PSR_EVENT_REGISTER_UPDATE) 406 drm_dbg_kms(display->drm, "\tRegister updated\n"); 407 if (val & PSR_EVENT_HDCP_ENABLE) 408 drm_dbg_kms(display->drm, "\tHDCP enabled\n"); 409 if (val & PSR_EVENT_KVMR_SESSION_ENABLE) 410 drm_dbg_kms(display->drm, "\tKVMR session enabled\n"); 411 if (val & PSR_EVENT_VBI_ENABLE) 412 drm_dbg_kms(display->drm, "\tVBI enabled\n"); 413 if (val & PSR_EVENT_LPSP_MODE_EXIT) 414 drm_dbg_kms(display->drm, "\tLPSP mode exited\n"); 415 if ((val & PSR_EVENT_PSR_DISABLE) && !sel_update_enabled) 416 drm_dbg_kms(display->drm, "\tPSR disabled\n"); 417 } 418 419 void intel_psr_irq_handler(struct intel_dp *intel_dp, u32 psr_iir) 420 { 421 struct intel_display *display = to_intel_display(intel_dp); 422 enum transcoder cpu_transcoder = intel_dp->psr.transcoder; 423 ktime_t time_ns = ktime_get(); 424 425 if (psr_iir & psr_irq_pre_entry_bit_get(intel_dp)) { 426 intel_dp->psr.last_entry_attempt = time_ns; 427 drm_dbg_kms(display->drm, 428 "[transcoder %s] PSR entry attempt in 2 vblanks\n", 429 transcoder_name(cpu_transcoder)); 430 } 431 432 if (psr_iir & psr_irq_post_exit_bit_get(intel_dp)) { 433 intel_dp->psr.last_exit = time_ns; 434 drm_dbg_kms(display->drm, 435 "[transcoder %s] PSR exit completed\n", 436 transcoder_name(cpu_transcoder)); 437 438 if (DISPLAY_VER(display) >= 9) { 439 u32 val; 440 441 val = intel_de_rmw(display, 442 PSR_EVENT(display, cpu_transcoder), 443 0, 0); 444 445 psr_event_print(display, val, intel_dp->psr.sel_update_enabled); 446 } 447 } 448 449 if (psr_iir & psr_irq_psr_error_bit_get(intel_dp)) { 450 drm_warn(display->drm, "[transcoder %s] PSR aux error\n", 451 transcoder_name(cpu_transcoder)); 452 453 intel_dp->psr.irq_aux_error = true; 454 455 /* 456 * If this interruption is not masked it will keep 457 * interrupting so fast that it prevents the scheduled 458 * work to run. 459 * Also after a PSR error, we don't want to arm PSR 460 * again so we don't care about unmask the interruption 461 * or unset irq_aux_error. 462 */ 463 intel_de_rmw(display, psr_imr_reg(display, cpu_transcoder), 464 0, psr_irq_psr_error_bit_get(intel_dp)); 465 466 queue_work(display->wq.unordered, &intel_dp->psr.work); 467 } 468 } 469 470 static u8 intel_dp_get_sink_sync_latency(struct intel_dp *intel_dp) 471 { 472 struct intel_display *display = to_intel_display(intel_dp); 473 u8 val = 8; /* assume the worst if we can't read the value */ 474 475 if (drm_dp_dpcd_readb(&intel_dp->aux, 476 DP_SYNCHRONIZATION_LATENCY_IN_SINK, &val) == 1) 477 val &= DP_MAX_RESYNC_FRAME_COUNT_MASK; 478 else 479 drm_dbg_kms(display->drm, 480 "Unable to get sink synchronization latency, assuming 8 frames\n"); 481 return val; 482 } 483 484 static void _psr_compute_su_granularity(struct intel_dp *intel_dp, 485 struct intel_connector *connector) 486 { 487 struct intel_display *display = to_intel_display(intel_dp); 488 ssize_t r; 489 __le16 w; 490 u8 y; 491 492 /* 493 * If sink don't have specific granularity requirements set legacy 494 * ones. 495 */ 496 if (!(connector->dp.psr_caps.dpcd[1] & DP_PSR2_SU_GRANULARITY_REQUIRED)) { 497 /* As PSR2 HW sends full lines, we do not care about x granularity */ 498 w = cpu_to_le16(4); 499 y = 4; 500 goto exit; 501 } 502 503 r = drm_dp_dpcd_read(&intel_dp->aux, DP_PSR2_SU_X_GRANULARITY, &w, sizeof(w)); 504 if (r != sizeof(w)) 505 drm_dbg_kms(display->drm, 506 "Unable to read selective update x granularity\n"); 507 /* 508 * Spec says that if the value read is 0 the default granularity should 509 * be used instead. 510 */ 511 if (r != sizeof(w) || w == 0) 512 w = cpu_to_le16(4); 513 514 r = drm_dp_dpcd_read(&intel_dp->aux, DP_PSR2_SU_Y_GRANULARITY, &y, 1); 515 if (r != 1) { 516 drm_dbg_kms(display->drm, 517 "Unable to read selective update y granularity\n"); 518 y = 4; 519 } 520 if (y == 0) 521 y = 1; 522 523 exit: 524 connector->dp.psr_caps.su_w_granularity = le16_to_cpu(w); 525 connector->dp.psr_caps.su_y_granularity = y; 526 } 527 528 static enum intel_panel_replay_dsc_support 529 compute_pr_dsc_support(struct intel_connector *connector) 530 { 531 u8 pr_dsc_mode; 532 u8 val; 533 534 val = connector->dp.panel_replay_caps.dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_CAPABILITY)]; 535 pr_dsc_mode = REG_FIELD_GET8(DP_PANEL_REPLAY_DSC_DECODE_CAPABILITY_IN_PR_MASK, val); 536 537 switch (pr_dsc_mode) { 538 case DP_DSC_DECODE_CAPABILITY_IN_PR_FULL_FRAME_ONLY: 539 return INTEL_DP_PANEL_REPLAY_DSC_FULL_FRAME_ONLY; 540 case DP_DSC_DECODE_CAPABILITY_IN_PR_SUPPORTED: 541 return INTEL_DP_PANEL_REPLAY_DSC_SELECTIVE_UPDATE; 542 default: 543 MISSING_CASE(pr_dsc_mode); 544 fallthrough; 545 case DP_DSC_DECODE_CAPABILITY_IN_PR_NOT_SUPPORTED: 546 case DP_DSC_DECODE_CAPABILITY_IN_PR_RESERVED: 547 return INTEL_DP_PANEL_REPLAY_DSC_NOT_SUPPORTED; 548 } 549 } 550 551 static const char *panel_replay_dsc_support_str(enum intel_panel_replay_dsc_support dsc_support) 552 { 553 switch (dsc_support) { 554 case INTEL_DP_PANEL_REPLAY_DSC_NOT_SUPPORTED: 555 return "not supported"; 556 case INTEL_DP_PANEL_REPLAY_DSC_FULL_FRAME_ONLY: 557 return "full frame only"; 558 case INTEL_DP_PANEL_REPLAY_DSC_SELECTIVE_UPDATE: 559 return "selective update"; 560 default: 561 MISSING_CASE(dsc_support); 562 return "n/a"; 563 }; 564 } 565 566 static void _panel_replay_compute_su_granularity(struct intel_connector *connector) 567 { 568 u16 w; 569 u8 y; 570 571 if (!(connector->dp.panel_replay_caps.dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_CAPABILITY)] & 572 DP_PANEL_REPLAY_SU_GRANULARITY_REQUIRED)) { 573 w = 4; 574 y = 4; 575 goto exit; 576 } 577 578 /* 579 * Spec says that if the value read is 0 the default granularity should 580 * be used instead. 581 */ 582 w = le16_to_cpu(*(__le16 *)&connector->dp.panel_replay_caps.dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_X_GRANULARITY)]) ? : 4; 583 y = connector->dp.panel_replay_caps.dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_Y_GRANULARITY)] ? : 1; 584 585 exit: 586 connector->dp.panel_replay_caps.su_w_granularity = w; 587 connector->dp.panel_replay_caps.su_y_granularity = y; 588 } 589 590 static void _panel_replay_init_dpcd(struct intel_dp *intel_dp, struct intel_connector *connector) 591 { 592 struct intel_display *display = to_intel_display(intel_dp); 593 int ret; 594 595 /* TODO: Enable Panel Replay on MST once it's properly implemented. */ 596 if (intel_dp->mst_detect == DRM_DP_MST) 597 return; 598 599 if (intel_dp_is_edp(intel_dp) && 600 intel_has_dpcd_quirk(intel_dp, QUIRK_DISABLE_EDP_PANEL_REPLAY)) { 601 drm_dbg_kms(display->drm, 602 "Panel Replay support not currently available for this setup\n"); 603 return; 604 } 605 606 ret = drm_dp_dpcd_read_data(&intel_dp->aux, DP_PANEL_REPLAY_CAP_SUPPORT, 607 &connector->dp.panel_replay_caps.dpcd, 608 sizeof(connector->dp.panel_replay_caps.dpcd)); 609 if (ret < 0) 610 return; 611 612 if (!(connector->dp.panel_replay_caps.dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_SUPPORT)] & 613 DP_PANEL_REPLAY_SUPPORT)) 614 return; 615 616 if (intel_dp_is_edp(intel_dp)) { 617 if (!intel_alpm_aux_less_wake_supported(intel_dp)) { 618 drm_dbg_kms(display->drm, 619 "Panel doesn't support AUX-less ALPM, eDP Panel Replay not possible\n"); 620 return; 621 } 622 623 if (!(connector->dp.panel_replay_caps.dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_SUPPORT)] & 624 DP_PANEL_REPLAY_EARLY_TRANSPORT_SUPPORT)) { 625 drm_dbg_kms(display->drm, 626 "Panel doesn't support early transport, eDP Panel Replay not possible\n"); 627 return; 628 } 629 } 630 631 connector->dp.panel_replay_caps.support = true; 632 intel_dp->psr.sink_panel_replay_support = true; 633 634 if (connector->dp.panel_replay_caps.dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_SUPPORT)] & 635 DP_PANEL_REPLAY_SU_SUPPORT) { 636 connector->dp.panel_replay_caps.su_support = true; 637 638 _panel_replay_compute_su_granularity(connector); 639 } 640 641 connector->dp.panel_replay_caps.dsc_support = compute_pr_dsc_support(connector); 642 643 drm_dbg_kms(display->drm, 644 "Panel replay %sis supported by panel (in DSC mode: %s)\n", 645 connector->dp.panel_replay_caps.su_support ? 646 "selective_update " : "", 647 panel_replay_dsc_support_str(connector->dp.panel_replay_caps.dsc_support)); 648 } 649 650 static void _psr_init_dpcd(struct intel_dp *intel_dp, struct intel_connector *connector) 651 { 652 struct intel_display *display = to_intel_display(intel_dp); 653 int ret; 654 655 ret = drm_dp_dpcd_read_data(&intel_dp->aux, DP_PSR_SUPPORT, connector->dp.psr_caps.dpcd, 656 sizeof(connector->dp.psr_caps.dpcd)); 657 if (ret < 0) 658 return; 659 660 if (!connector->dp.psr_caps.dpcd[0]) 661 return; 662 663 drm_dbg_kms(display->drm, "eDP panel supports PSR version %x\n", 664 connector->dp.psr_caps.dpcd[0]); 665 666 if (drm_dp_has_quirk(&intel_dp->desc, DP_DPCD_QUIRK_NO_PSR)) { 667 drm_dbg_kms(display->drm, 668 "PSR support not currently available for this panel\n"); 669 return; 670 } 671 672 if (!(intel_dp->edp_dpcd[1] & DP_EDP_SET_POWER_CAP)) { 673 drm_dbg_kms(display->drm, 674 "Panel lacks power state control, PSR cannot be enabled\n"); 675 return; 676 } 677 678 connector->dp.psr_caps.support = true; 679 intel_dp->psr.sink_support = true; 680 681 connector->dp.psr_caps.sync_latency = intel_dp_get_sink_sync_latency(intel_dp); 682 683 if (intel_has_quirk(display, QUIRK_DISABLE_PSR2)) 684 return; 685 686 if (DISPLAY_VER(display) >= 9 && 687 connector->dp.psr_caps.dpcd[0] >= DP_PSR2_WITH_Y_COORD_IS_SUPPORTED) { 688 bool y_req = connector->dp.psr_caps.dpcd[1] & 689 DP_PSR2_SU_Y_COORDINATE_REQUIRED; 690 691 /* 692 * All panels that supports PSR version 03h (PSR2 + 693 * Y-coordinate) can handle Y-coordinates in VSC but we are 694 * only sure that it is going to be used when required by the 695 * panel. This way panel is capable to do selective update 696 * without a aux frame sync. 697 * 698 * To support PSR version 02h and PSR version 03h without 699 * Y-coordinate requirement panels we would need to enable 700 * GTC first. 701 */ 702 connector->dp.psr_caps.su_support = y_req && 703 intel_alpm_aux_wake_supported(intel_dp); 704 drm_dbg_kms(display->drm, "PSR2 %ssupported\n", 705 connector->dp.psr_caps.su_support ? "" : "not "); 706 } 707 708 if (connector->dp.psr_caps.su_support) { 709 ret = drm_dp_dpcd_read_byte(&intel_dp->aux, 710 INTEL_DPCD_INTEL_WA_REGISTER_CAPS, 711 &connector->dp.psr_caps.intel_wa_dpcd); 712 if (ret < 0) 713 return; 714 _psr_compute_su_granularity(intel_dp, connector); 715 } 716 } 717 718 void intel_psr_init_dpcd(struct intel_dp *intel_dp, struct intel_connector *connector) 719 { 720 _psr_init_dpcd(intel_dp, connector); 721 722 _panel_replay_init_dpcd(intel_dp, connector); 723 } 724 725 static void hsw_psr_setup_aux(struct intel_dp *intel_dp) 726 { 727 struct intel_display *display = to_intel_display(intel_dp); 728 enum transcoder cpu_transcoder = intel_dp->psr.transcoder; 729 u32 aux_clock_divider, aux_ctl; 730 /* write DP_SET_POWER=D0 */ 731 static const u8 aux_msg[] = { 732 [0] = (DP_AUX_NATIVE_WRITE << 4) | ((DP_SET_POWER >> 16) & 0xf), 733 [1] = (DP_SET_POWER >> 8) & 0xff, 734 [2] = DP_SET_POWER & 0xff, 735 [3] = 1 - 1, 736 [4] = DP_SET_POWER_D0, 737 }; 738 int i; 739 740 BUILD_BUG_ON(sizeof(aux_msg) > 20); 741 for (i = 0; i < sizeof(aux_msg); i += 4) 742 intel_de_write(display, 743 psr_aux_data_reg(display, cpu_transcoder, i >> 2), 744 intel_dp_aux_pack(&aux_msg[i], sizeof(aux_msg) - i)); 745 746 aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, 0); 747 748 /* Start with bits set for DDI_AUX_CTL register */ 749 aux_ctl = intel_dp->get_aux_send_ctl(intel_dp, sizeof(aux_msg), 750 aux_clock_divider); 751 752 /* Select only valid bits for SRD_AUX_CTL */ 753 aux_ctl &= EDP_PSR_AUX_CTL_TIME_OUT_MASK | 754 EDP_PSR_AUX_CTL_MESSAGE_SIZE_MASK | 755 EDP_PSR_AUX_CTL_PRECHARGE_2US_MASK | 756 EDP_PSR_AUX_CTL_BIT_CLOCK_2X_MASK; 757 758 intel_de_write(display, psr_aux_ctl_reg(display, cpu_transcoder), 759 aux_ctl); 760 } 761 762 static bool psr2_su_region_et_valid(struct intel_connector *connector, bool panel_replay) 763 { 764 struct intel_dp *intel_dp = intel_attached_dp(connector); 765 struct intel_display *display = to_intel_display(intel_dp); 766 767 if (DISPLAY_VER(display) < 20 || !intel_dp_is_edp(intel_dp) || 768 intel_dp->psr.debug & I915_PSR_DEBUG_SU_REGION_ET_DISABLE) 769 return false; 770 771 return panel_replay ? 772 connector->dp.panel_replay_caps.dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_SUPPORT)] & 773 DP_PANEL_REPLAY_EARLY_TRANSPORT_SUPPORT : 774 connector->dp.psr_caps.dpcd[0] == DP_PSR2_WITH_Y_COORD_ET_SUPPORTED; 775 } 776 777 static void _panel_replay_enable_sink(struct intel_dp *intel_dp, 778 const struct intel_crtc_state *crtc_state) 779 { 780 u8 panel_replay_config[2]; 781 u8 panel_replay_config_3; 782 783 panel_replay_config[0] = DP_PANEL_REPLAY_ENABLE | 784 DP_PANEL_REPLAY_VSC_SDP_CRC_EN | 785 DP_PANEL_REPLAY_UNRECOVERABLE_ERROR_EN | 786 DP_PANEL_REPLAY_RFB_STORAGE_ERROR_EN | 787 DP_PANEL_REPLAY_ACTIVE_FRAME_CRC_ERROR_EN; 788 panel_replay_config[1] = DP_PANEL_REPLAY_CRC_VERIFICATION; 789 if (crtc_state->has_sel_update) 790 panel_replay_config[0] |= DP_PANEL_REPLAY_SU_ENABLE; 791 792 if (crtc_state->enable_psr2_su_region_et) 793 panel_replay_config[0] |= DP_PANEL_REPLAY_ENABLE_SU_REGION_ET; 794 795 if (crtc_state->req_psr2_sdp_prior_scanline) 796 panel_replay_config[1] |= 797 DP_PANEL_REPLAY_SU_REGION_SCANLINE_CAPTURE; 798 799 drm_dp_dpcd_write(&intel_dp->aux, PANEL_REPLAY_CONFIG, 800 panel_replay_config, sizeof(panel_replay_config)); 801 802 panel_replay_config_3 = intel_dp_as_sdp_transmission_time(); 803 drm_dp_dpcd_writeb(&intel_dp->aux, PANEL_REPLAY_CONFIG3, panel_replay_config_3); 804 } 805 806 static void _psr_enable_sink(struct intel_dp *intel_dp, 807 const struct intel_crtc_state *crtc_state) 808 { 809 struct intel_display *display = to_intel_display(intel_dp); 810 u8 val = 0; 811 812 if (crtc_state->has_sel_update) { 813 val |= DP_PSR_ENABLE_PSR2 | DP_PSR_IRQ_HPD_WITH_CRC_ERRORS; 814 } else { 815 if (intel_dp->psr.link_standby) 816 val |= DP_PSR_MAIN_LINK_ACTIVE; 817 818 if (DISPLAY_VER(display) >= 8) 819 val |= DP_PSR_CRC_VERIFICATION; 820 } 821 822 if (crtc_state->req_psr2_sdp_prior_scanline) 823 val |= DP_PSR_SU_REGION_SCANLINE_CAPTURE; 824 825 if (crtc_state->enable_psr2_su_region_et) 826 val |= DP_PANEL_REPLAY_ENABLE_SU_REGION_ET; 827 828 if (intel_dp->psr.entry_setup_frames > 0) 829 val |= DP_PSR_FRAME_CAPTURE; 830 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, val); 831 832 val |= DP_PSR_ENABLE; 833 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, val); 834 } 835 836 static void intel_psr_enable_sink(struct intel_dp *intel_dp, 837 const struct intel_crtc_state *crtc_state) 838 { 839 intel_alpm_enable_sink(intel_dp, crtc_state); 840 841 crtc_state->has_panel_replay ? 842 _panel_replay_enable_sink(intel_dp, crtc_state) : 843 _psr_enable_sink(intel_dp, crtc_state); 844 845 if (intel_dp_is_edp(intel_dp)) 846 drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, DP_SET_POWER_D0); 847 } 848 849 void intel_psr_panel_replay_enable_sink(struct intel_dp *intel_dp) 850 { 851 /* 852 * NOTE: We might want to trigger mode set when 853 * disabling/enabling Panel Replay via debugfs interface to 854 * ensure this bit is cleared/set accordingly. 855 */ 856 if (CAN_PANEL_REPLAY(intel_dp) && panel_replay_global_enabled(intel_dp)) 857 drm_dp_dpcd_writeb(&intel_dp->aux, PANEL_REPLAY_CONFIG, 858 DP_PANEL_REPLAY_ENABLE); 859 } 860 861 static u32 intel_psr1_get_tp_time(struct intel_dp *intel_dp) 862 { 863 struct intel_display *display = to_intel_display(intel_dp); 864 struct intel_connector *connector = intel_dp->attached_connector; 865 u32 val = 0; 866 867 if (DISPLAY_VER(display) >= 11) 868 val |= EDP_PSR_TP4_TIME_0us; 869 870 if (display->params.psr_safest_params) { 871 val |= EDP_PSR_TP1_TIME_2500us; 872 val |= EDP_PSR_TP2_TP3_TIME_2500us; 873 goto check_tp3_sel; 874 } 875 876 if (connector->panel.vbt.psr.tp1_wakeup_time_us == 0) 877 val |= EDP_PSR_TP1_TIME_0us; 878 else if (connector->panel.vbt.psr.tp1_wakeup_time_us <= 100) 879 val |= EDP_PSR_TP1_TIME_100us; 880 else if (connector->panel.vbt.psr.tp1_wakeup_time_us <= 500) 881 val |= EDP_PSR_TP1_TIME_500us; 882 else 883 val |= EDP_PSR_TP1_TIME_2500us; 884 885 if (connector->panel.vbt.psr.tp2_tp3_wakeup_time_us == 0) 886 val |= EDP_PSR_TP2_TP3_TIME_0us; 887 else if (connector->panel.vbt.psr.tp2_tp3_wakeup_time_us <= 100) 888 val |= EDP_PSR_TP2_TP3_TIME_100us; 889 else if (connector->panel.vbt.psr.tp2_tp3_wakeup_time_us <= 500) 890 val |= EDP_PSR_TP2_TP3_TIME_500us; 891 else 892 val |= EDP_PSR_TP2_TP3_TIME_2500us; 893 894 /* 895 * WA 0479: hsw,bdw 896 * "Do not skip both TP1 and TP2/TP3" 897 */ 898 if (DISPLAY_VER(display) < 9 && 899 connector->panel.vbt.psr.tp1_wakeup_time_us == 0 && 900 connector->panel.vbt.psr.tp2_tp3_wakeup_time_us == 0) 901 val |= EDP_PSR_TP2_TP3_TIME_100us; 902 903 check_tp3_sel: 904 if (intel_dp_source_supports_tps3(display) && 905 drm_dp_tps3_supported(intel_dp->dpcd)) 906 val |= EDP_PSR_TP_TP1_TP3; 907 else 908 val |= EDP_PSR_TP_TP1_TP2; 909 910 return val; 911 } 912 913 static u8 psr_compute_idle_frames(struct intel_dp *intel_dp) 914 { 915 struct intel_display *display = to_intel_display(intel_dp); 916 struct intel_connector *connector = intel_dp->attached_connector; 917 int idle_frames; 918 919 /* Let's use 6 as the minimum to cover all known cases including the 920 * off-by-one issue that HW has in some cases. 921 */ 922 idle_frames = max(6, connector->panel.vbt.psr.idle_frames); 923 idle_frames = max(idle_frames, connector->dp.psr_caps.sync_latency + 1); 924 925 if (drm_WARN_ON(display->drm, idle_frames > 0xf)) 926 idle_frames = 0xf; 927 928 return idle_frames; 929 } 930 931 static bool is_dc5_dc6_blocked(struct intel_dp *intel_dp) 932 { 933 struct intel_display *display = to_intel_display(intel_dp); 934 u32 current_dc_state = intel_display_power_get_current_dc_state(display); 935 struct intel_crtc *crtc = intel_crtc_for_pipe(display, intel_dp->psr.pipe); 936 struct drm_vblank_crtc *vblank = drm_crtc_vblank_crtc(&crtc->base); 937 938 return (current_dc_state != DC_STATE_EN_UPTO_DC5 && 939 current_dc_state != DC_STATE_EN_UPTO_DC6) || 940 intel_dp->psr.active_non_psr_pipes || 941 READ_ONCE(vblank->enabled); 942 } 943 944 static void hsw_activate_psr1(struct intel_dp *intel_dp) 945 { 946 struct intel_display *display = to_intel_display(intel_dp); 947 enum transcoder cpu_transcoder = intel_dp->psr.transcoder; 948 u32 max_sleep_time = 0x1f; 949 u32 val = EDP_PSR_ENABLE; 950 951 val |= EDP_PSR_IDLE_FRAMES(psr_compute_idle_frames(intel_dp)); 952 953 if (DISPLAY_VER(display) < 20) 954 val |= EDP_PSR_MAX_SLEEP_TIME(max_sleep_time); 955 956 if (display->platform.haswell) 957 val |= EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES; 958 959 if (intel_dp->psr.link_standby) 960 val |= EDP_PSR_LINK_STANDBY; 961 962 val |= intel_psr1_get_tp_time(intel_dp); 963 964 if (DISPLAY_VER(display) >= 8) 965 val |= EDP_PSR_CRC_ENABLE; 966 967 if (DISPLAY_VER(display) >= 20) 968 val |= LNL_EDP_PSR_ENTRY_SETUP_FRAMES(intel_dp->psr.entry_setup_frames); 969 970 intel_de_rmw(display, psr_ctl_reg(display, cpu_transcoder), 971 ~EDP_PSR_RESTORE_PSR_ACTIVE_CTX_MASK, val); 972 973 /* Wa_16025596647 */ 974 if ((DISPLAY_VER(display) == 20 || 975 IS_DISPLAY_VERx100_STEP(display, 3000, STEP_A0, STEP_B0)) && 976 is_dc5_dc6_blocked(intel_dp) && intel_dp->psr.pkg_c_latency_used) 977 intel_dmc_start_pkgc_exit_at_start_of_undelayed_vblank(display, 978 intel_dp->psr.pipe, 979 true); 980 } 981 982 static u32 intel_psr2_get_tp_time(struct intel_dp *intel_dp) 983 { 984 struct intel_display *display = to_intel_display(intel_dp); 985 struct intel_connector *connector = intel_dp->attached_connector; 986 u32 val = 0; 987 988 if (display->params.psr_safest_params) 989 return EDP_PSR2_TP2_TIME_2500us; 990 991 if (connector->panel.vbt.psr.psr2_tp2_tp3_wakeup_time_us >= 0 && 992 connector->panel.vbt.psr.psr2_tp2_tp3_wakeup_time_us <= 50) 993 val |= EDP_PSR2_TP2_TIME_50us; 994 else if (connector->panel.vbt.psr.psr2_tp2_tp3_wakeup_time_us <= 100) 995 val |= EDP_PSR2_TP2_TIME_100us; 996 else if (connector->panel.vbt.psr.psr2_tp2_tp3_wakeup_time_us <= 500) 997 val |= EDP_PSR2_TP2_TIME_500us; 998 else 999 val |= EDP_PSR2_TP2_TIME_2500us; 1000 1001 return val; 1002 } 1003 1004 static int 1005 psr2_block_count_lines(u8 io_wake_lines, u8 fast_wake_lines) 1006 { 1007 return io_wake_lines < 9 && fast_wake_lines < 9 ? 8 : 12; 1008 } 1009 1010 static int psr2_block_count(struct intel_dp *intel_dp) 1011 { 1012 return psr2_block_count_lines(intel_dp->psr.io_wake_lines, 1013 intel_dp->psr.fast_wake_lines) / 4; 1014 } 1015 1016 static u8 frames_before_su_entry(struct intel_dp *intel_dp) 1017 { 1018 struct intel_connector *connector = intel_dp->attached_connector; 1019 u8 frames_before_su_entry; 1020 1021 frames_before_su_entry = max_t(u8, 1022 connector->dp.psr_caps.sync_latency + 1, 1023 2); 1024 1025 /* Entry setup frames must be at least 1 less than frames before SU entry */ 1026 if (intel_dp->psr.entry_setup_frames >= frames_before_su_entry) 1027 frames_before_su_entry = intel_dp->psr.entry_setup_frames + 1; 1028 1029 return frames_before_su_entry; 1030 } 1031 1032 static bool intel_psr_allow_pr_bw_optimization(struct intel_dp *intel_dp) 1033 { 1034 if (intel_dp_is_edp(intel_dp)) 1035 return false; 1036 1037 if (!intel_dp_tunnel_bw_alloc_is_enabled(intel_dp)) 1038 return false; 1039 1040 if (!intel_dp_tunnel_pr_optimization_supported(intel_dp)) 1041 return false; 1042 1043 return true; 1044 } 1045 1046 static void dg2_activate_panel_replay(struct intel_dp *intel_dp) 1047 { 1048 struct intel_display *display = to_intel_display(intel_dp); 1049 struct intel_psr *psr = &intel_dp->psr; 1050 enum transcoder cpu_transcoder = intel_dp->psr.transcoder; 1051 u32 dp2_ctl_set = TRANS_DP2_PANEL_REPLAY_ENABLE; 1052 u32 dp2_ctl_clear = 0; 1053 1054 if (intel_dp_is_edp(intel_dp) && psr->sel_update_enabled) { 1055 u32 val = psr->su_region_et_enabled ? 1056 LNL_EDP_PSR2_SU_REGION_ET_ENABLE : 0; 1057 1058 if (intel_dp->psr.req_psr2_sdp_prior_scanline) 1059 val |= EDP_PSR2_SU_SDP_SCANLINE; 1060 1061 intel_de_write(display, EDP_PSR2_CTL(display, cpu_transcoder), 1062 val); 1063 } 1064 1065 if (intel_psr_allow_pr_bw_optimization(intel_dp)) 1066 dp2_ctl_set |= TRANS_DP2_PR_TUNNELING_ENABLE; 1067 else 1068 dp2_ctl_clear = TRANS_DP2_PR_TUNNELING_ENABLE; 1069 1070 intel_de_rmw(display, 1071 PSR2_MAN_TRK_CTL(display, intel_dp->psr.transcoder), 1072 0, ADLP_PSR2_MAN_TRK_CTL_SF_CONTINUOS_FULL_FRAME); 1073 1074 intel_de_rmw(display, TRANS_DP2_CTL(intel_dp->psr.transcoder), dp2_ctl_clear, dp2_ctl_set); 1075 } 1076 1077 static void hsw_activate_psr2(struct intel_dp *intel_dp) 1078 { 1079 struct intel_display *display = to_intel_display(intel_dp); 1080 enum transcoder cpu_transcoder = intel_dp->psr.transcoder; 1081 u32 val = EDP_PSR2_ENABLE; 1082 u32 psr_val = 0; 1083 u8 idle_frames; 1084 1085 /* DC3CO / Wa_16025596647 */ 1086 if (intel_dp->psr.dc3co_allowed || 1087 ((DISPLAY_VER(display) == 20 || 1088 IS_DISPLAY_VERx100_STEP(display, 3000, STEP_A0, STEP_B0)) && 1089 is_dc5_dc6_blocked(intel_dp) && intel_dp->psr.pkg_c_latency_used)) 1090 idle_frames = 0; 1091 else 1092 idle_frames = psr_compute_idle_frames(intel_dp); 1093 val |= EDP_PSR2_IDLE_FRAMES(idle_frames); 1094 1095 if (DISPLAY_VER(display) < 14 && !display->platform.alderlake_p) 1096 val |= EDP_SU_TRACK_ENABLE; 1097 1098 if (DISPLAY_VER(display) >= 10 && DISPLAY_VER(display) < 13) 1099 val |= EDP_Y_COORDINATE_ENABLE; 1100 1101 val |= EDP_PSR2_FRAME_BEFORE_SU(frames_before_su_entry(intel_dp)); 1102 1103 val |= intel_psr2_get_tp_time(intel_dp); 1104 1105 if (DISPLAY_VER(display) >= 12 && DISPLAY_VER(display) < 20) { 1106 if (psr2_block_count(intel_dp) > 2) 1107 val |= TGL_EDP_PSR2_BLOCK_COUNT_NUM_3; 1108 else 1109 val |= TGL_EDP_PSR2_BLOCK_COUNT_NUM_2; 1110 } 1111 1112 /* Wa_22012278275:adl-p */ 1113 if (intel_display_wa(display, INTEL_DISPLAY_WA_22012278275)) { 1114 static const u8 map[] = { 1115 2, /* 5 lines */ 1116 1, /* 6 lines */ 1117 0, /* 7 lines */ 1118 3, /* 8 lines */ 1119 6, /* 9 lines */ 1120 5, /* 10 lines */ 1121 4, /* 11 lines */ 1122 7, /* 12 lines */ 1123 }; 1124 /* 1125 * Still using the default IO_BUFFER_WAKE and FAST_WAKE, see 1126 * comments below for more information 1127 */ 1128 int tmp; 1129 1130 tmp = map[intel_dp->psr.io_wake_lines - 1131 TGL_EDP_PSR2_IO_BUFFER_WAKE_MIN_LINES]; 1132 val |= TGL_EDP_PSR2_IO_BUFFER_WAKE(tmp + TGL_EDP_PSR2_IO_BUFFER_WAKE_MIN_LINES); 1133 1134 tmp = map[intel_dp->psr.fast_wake_lines - TGL_EDP_PSR2_FAST_WAKE_MIN_LINES]; 1135 val |= TGL_EDP_PSR2_FAST_WAKE(tmp + TGL_EDP_PSR2_FAST_WAKE_MIN_LINES); 1136 } else if (DISPLAY_VER(display) >= 20) { 1137 val |= LNL_EDP_PSR2_IO_BUFFER_WAKE(intel_dp->psr.io_wake_lines); 1138 } else if (DISPLAY_VER(display) >= 12) { 1139 val |= TGL_EDP_PSR2_IO_BUFFER_WAKE(intel_dp->psr.io_wake_lines); 1140 val |= TGL_EDP_PSR2_FAST_WAKE(intel_dp->psr.fast_wake_lines); 1141 } else if (DISPLAY_VER(display) >= 9) { 1142 val |= EDP_PSR2_IO_BUFFER_WAKE(intel_dp->psr.io_wake_lines); 1143 val |= EDP_PSR2_FAST_WAKE(intel_dp->psr.fast_wake_lines); 1144 } 1145 1146 if (intel_dp->psr.req_psr2_sdp_prior_scanline) 1147 val |= EDP_PSR2_SU_SDP_SCANLINE; 1148 1149 if (DISPLAY_VER(display) >= 20) 1150 psr_val |= LNL_EDP_PSR_ENTRY_SETUP_FRAMES(intel_dp->psr.entry_setup_frames); 1151 1152 if (intel_dp->psr.psr2_sel_fetch_enabled) { 1153 u32 tmp; 1154 1155 tmp = intel_de_read(display, 1156 PSR2_MAN_TRK_CTL(display, cpu_transcoder)); 1157 drm_WARN_ON(display->drm, !(tmp & PSR2_MAN_TRK_CTL_ENABLE)); 1158 } else if (HAS_PSR2_SEL_FETCH(display)) { 1159 intel_de_write(display, 1160 PSR2_MAN_TRK_CTL(display, cpu_transcoder), 0); 1161 } 1162 1163 if (intel_dp->psr.su_region_et_enabled) 1164 val |= LNL_EDP_PSR2_SU_REGION_ET_ENABLE; 1165 1166 /* 1167 * PSR2 HW is incorrectly using EDP_PSR_TP1_TP3_SEL and BSpec is 1168 * recommending keep this bit unset while PSR2 is enabled. 1169 */ 1170 intel_de_write(display, psr_ctl_reg(display, cpu_transcoder), psr_val); 1171 1172 intel_de_write(display, EDP_PSR2_CTL(display, cpu_transcoder), val); 1173 } 1174 1175 static bool 1176 transcoder_has_psr2(struct intel_display *display, enum transcoder cpu_transcoder) 1177 { 1178 if (display->platform.alderlake_p || DISPLAY_VER(display) >= 14) 1179 return cpu_transcoder == TRANSCODER_A || cpu_transcoder == TRANSCODER_B; 1180 else if (DISPLAY_VER(display) >= 12) 1181 return cpu_transcoder == TRANSCODER_A; 1182 else if (DISPLAY_VER(display) >= 9) 1183 return cpu_transcoder == TRANSCODER_EDP; 1184 else 1185 return false; 1186 } 1187 1188 static u32 intel_get_frame_time_us(const struct intel_crtc_state *crtc_state) 1189 { 1190 if (!crtc_state->hw.active) 1191 return 0; 1192 1193 return DIV_ROUND_UP(1000 * 1000, 1194 drm_mode_vrefresh(&crtc_state->hw.adjusted_mode)); 1195 } 1196 1197 static void psr2_program_idle_frames(struct intel_dp *intel_dp, 1198 u32 idle_frames) 1199 { 1200 struct intel_display *display = to_intel_display(intel_dp); 1201 enum transcoder cpu_transcoder = intel_dp->psr.transcoder; 1202 1203 intel_de_rmw(display, EDP_PSR2_CTL(display, cpu_transcoder), 1204 EDP_PSR2_IDLE_FRAMES_MASK, 1205 EDP_PSR2_IDLE_FRAMES(idle_frames)); 1206 } 1207 1208 static bool intel_psr2_sel_fetch_config_valid(struct intel_dp *intel_dp, 1209 struct intel_crtc_state *crtc_state) 1210 { 1211 struct intel_display *display = to_intel_display(intel_dp); 1212 1213 if (!display->params.enable_psr2_sel_fetch && 1214 intel_dp->psr.debug != I915_PSR_DEBUG_ENABLE_SEL_FETCH) { 1215 drm_dbg_kms(display->drm, 1216 "PSR2 sel fetch not enabled, disabled by parameter\n"); 1217 return false; 1218 } 1219 1220 return crtc_state->enable_psr2_sel_fetch = true; 1221 } 1222 1223 static bool psr2_granularity_check(struct intel_crtc_state *crtc_state, 1224 struct intel_connector *connector) 1225 { 1226 struct intel_dp *intel_dp = intel_attached_dp(connector); 1227 struct intel_display *display = to_intel_display(intel_dp); 1228 const struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config; 1229 const int crtc_hdisplay = crtc_state->hw.adjusted_mode.crtc_hdisplay; 1230 const int crtc_vdisplay = crtc_state->hw.adjusted_mode.crtc_vdisplay; 1231 u16 y_granularity = 0; 1232 u16 sink_y_granularity = crtc_state->has_panel_replay ? 1233 connector->dp.panel_replay_caps.su_y_granularity : 1234 connector->dp.psr_caps.su_y_granularity; 1235 u16 sink_w_granularity; 1236 1237 if (crtc_state->has_panel_replay) 1238 sink_w_granularity = connector->dp.panel_replay_caps.su_w_granularity == 1239 DP_PANEL_REPLAY_FULL_LINE_GRANULARITY ? 1240 crtc_hdisplay : connector->dp.panel_replay_caps.su_w_granularity; 1241 else 1242 sink_w_granularity = connector->dp.psr_caps.su_w_granularity; 1243 1244 /* PSR2 HW only send full lines so we only need to validate the width */ 1245 if (crtc_hdisplay % sink_w_granularity) 1246 return false; 1247 1248 if (crtc_vdisplay % sink_y_granularity) 1249 return false; 1250 1251 /* HW tracking is only aligned to 4 lines */ 1252 if (!crtc_state->enable_psr2_sel_fetch) 1253 return sink_y_granularity == 4; 1254 1255 /* 1256 * adl_p and mtl platforms have 1 line granularity. 1257 * For other platforms with SW tracking we can adjust the y coordinates 1258 * to match sink requirement if multiple of 4. 1259 */ 1260 if (display->platform.alderlake_p || DISPLAY_VER(display) >= 14) 1261 y_granularity = sink_y_granularity; 1262 else if (sink_y_granularity <= 2) 1263 y_granularity = 4; 1264 else if ((sink_y_granularity % 4) == 0) 1265 y_granularity = sink_y_granularity; 1266 1267 if (y_granularity == 0 || crtc_vdisplay % y_granularity) 1268 return false; 1269 1270 if (crtc_state->dsc.compression_enable && 1271 vdsc_cfg->slice_height % y_granularity) 1272 return false; 1273 1274 crtc_state->su_y_granularity = y_granularity; 1275 return true; 1276 } 1277 1278 static bool apply_scanline_indication_wa(struct intel_crtc_state *crtc_state, 1279 struct intel_connector *connector) 1280 { 1281 struct intel_dp *intel_dp = intel_attached_dp(connector); 1282 u8 early_scanline_support = connector->dp.psr_caps.intel_wa_dpcd & 1283 INTEL_DPCD_INTEL_WA_REGISTER_CAPS_PSR2_EARLYSCANLINE_SDP_SUPPORT_MASK; 1284 1285 if (intel_dp->edp_dpcd[0] >= DP_EDP_15) 1286 return true; 1287 1288 switch (early_scanline_support) { 1289 case INTEL_DPCD_INTEL_WA_REGISTER_CAPS_FALL_BACK_TO_PSR1: 1290 crtc_state->req_psr2_sdp_prior_scanline = false; 1291 return false; 1292 case INTEL_DPCD_INTEL_WA_REGISTER_CAPS_PSR2_WITH_EARLY_SCANLINE: 1293 return true; 1294 case INTEL_DPCD_INTEL_WA_REGISTER_CAPS_PSR2_WITHOUT_EARLY_SCANLINE: 1295 crtc_state->req_psr2_sdp_prior_scanline = false; 1296 return true; 1297 default: 1298 MISSING_CASE(early_scanline_support); 1299 return false; 1300 } 1301 } 1302 1303 static bool _compute_psr2_sdp_prior_scanline_indication(struct intel_crtc_state *crtc_state, 1304 struct intel_connector *connector) 1305 { 1306 struct intel_dp *intel_dp = intel_attached_dp(connector); 1307 struct intel_display *display = to_intel_display(intel_dp); 1308 const struct drm_display_mode *adjusted_mode = &crtc_state->uapi.adjusted_mode; 1309 u32 hblank_total, hblank_ns, req_ns; 1310 1311 hblank_total = adjusted_mode->crtc_hblank_end - adjusted_mode->crtc_hblank_start; 1312 hblank_ns = div_u64(1000000ULL * hblank_total, adjusted_mode->crtc_clock); 1313 1314 /* From spec: ((60 / number of lanes) + 11) * 1000 / symbol clock frequency MHz */ 1315 req_ns = ((60 / crtc_state->lane_count) + 11) * 1000 / (crtc_state->port_clock / 1000); 1316 1317 if ((hblank_ns - req_ns) > 100) 1318 return true; 1319 1320 /* Not supported <13 / Wa_22012279113:adl-p */ 1321 if (DISPLAY_VER(display) < 14 || intel_dp->edp_dpcd[0] < DP_EDP_14b) 1322 return false; 1323 1324 crtc_state->req_psr2_sdp_prior_scanline = true; 1325 1326 return apply_scanline_indication_wa(crtc_state, connector); 1327 } 1328 1329 static int intel_psr_entry_setup_frames(struct intel_dp *intel_dp, 1330 struct drm_connector_state *conn_state, 1331 const struct drm_display_mode *adjusted_mode) 1332 { 1333 struct intel_display *display = to_intel_display(intel_dp); 1334 struct intel_connector *connector = to_intel_connector(conn_state->connector); 1335 int psr_setup_time = drm_dp_psr_setup_time(connector->dp.psr_caps.dpcd); 1336 int entry_setup_frames = 0; 1337 1338 if (psr_setup_time < 0) { 1339 drm_dbg_kms(display->drm, 1340 "PSR condition failed: Invalid PSR setup time (0x%02x)\n", 1341 connector->dp.psr_caps.dpcd[1]); 1342 return -ETIME; 1343 } 1344 1345 if (intel_usecs_to_scanlines(adjusted_mode, psr_setup_time) > 1346 adjusted_mode->crtc_vtotal - adjusted_mode->crtc_vdisplay - 1) { 1347 if (DISPLAY_VER(display) >= 20) { 1348 /* setup entry frames can be up to 3 frames */ 1349 entry_setup_frames = 1; 1350 drm_dbg_kms(display->drm, 1351 "PSR setup entry frames %d\n", 1352 entry_setup_frames); 1353 } else { 1354 drm_dbg_kms(display->drm, 1355 "PSR condition failed: PSR setup time (%d us) too long\n", 1356 psr_setup_time); 1357 return -ETIME; 1358 } 1359 } 1360 1361 return entry_setup_frames; 1362 } 1363 1364 static 1365 int _intel_psr_min_set_context_latency(const struct intel_crtc_state *crtc_state, 1366 bool needs_panel_replay, 1367 bool needs_sel_update) 1368 { 1369 struct intel_display *display = to_intel_display(crtc_state); 1370 1371 if (!crtc_state->has_psr) 1372 return 0; 1373 1374 /* Wa_14015401596 */ 1375 if (intel_vrr_possible(crtc_state) && IS_DISPLAY_VER(display, 13, 14)) 1376 return 1; 1377 1378 /* Rest is for SRD_STATUS needed on LunarLake and onwards */ 1379 if (DISPLAY_VER(display) < 20) 1380 return 0; 1381 1382 /* 1383 * Comment on SRD_STATUS register in Bspec for LunarLake and onwards: 1384 * 1385 * To deterministically capture the transition of the state machine 1386 * going from SRDOFFACK to IDLE, the delayed V. Blank should be at least 1387 * one line after the non-delayed V. Blank. 1388 * 1389 * Legacy TG: TRANS_SET_CONTEXT_LATENCY > 0 1390 * VRR TG: TRANS_VRR_CTL[ VRR Guardband ] < (TRANS_VRR_VMAX[ VRR Vmax ] 1391 * - TRANS_VTOTAL[ Vertical Active ]) 1392 * 1393 * SRD_STATUS is used only by PSR1 on PantherLake. 1394 * SRD_STATUS is used by PSR1 and Panel Replay DP on LunarLake. 1395 */ 1396 1397 if (needs_sel_update) 1398 return 0; 1399 1400 if (DISPLAY_VER(display) < 30 && 1401 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) 1402 return 0; 1403 1404 if (DISPLAY_VER(display) >= 30 && 1405 needs_panel_replay) 1406 return 0; 1407 1408 return 1; 1409 } 1410 1411 static bool _wake_lines_fit_into_vblank(const struct intel_crtc_state *crtc_state, 1412 int vblank, 1413 int wake_lines) 1414 { 1415 if (crtc_state->req_psr2_sdp_prior_scanline) 1416 vblank -= 1; 1417 1418 /* Vblank >= PSR2_CTL Block Count Number maximum line count */ 1419 if (vblank < wake_lines) 1420 return false; 1421 1422 return true; 1423 } 1424 1425 static bool wake_lines_fit_into_vblank(struct intel_dp *intel_dp, 1426 const struct intel_crtc_state *crtc_state, 1427 bool aux_less, 1428 bool needs_panel_replay, 1429 bool needs_sel_update) 1430 { 1431 struct intel_display *display = to_intel_display(intel_dp); 1432 int vblank = crtc_state->hw.adjusted_mode.crtc_vblank_end - 1433 crtc_state->hw.adjusted_mode.crtc_vblank_start; 1434 int wake_lines; 1435 int scl = _intel_psr_min_set_context_latency(crtc_state, 1436 needs_panel_replay, 1437 needs_sel_update); 1438 vblank -= scl; 1439 1440 if (aux_less) 1441 wake_lines = crtc_state->alpm_state.aux_less_wake_lines; 1442 else 1443 wake_lines = DISPLAY_VER(display) < 20 ? 1444 psr2_block_count_lines(crtc_state->alpm_state.io_wake_lines, 1445 crtc_state->alpm_state.fast_wake_lines) : 1446 crtc_state->alpm_state.io_wake_lines; 1447 1448 /* 1449 * Guardband has not been computed yet, so we conservatively check if the 1450 * full vblank duration is sufficient to accommodate wake line requirements 1451 * for PSR features like Panel Replay and Selective Update. 1452 * 1453 * Once the actual guardband is available, a more accurate validation is 1454 * performed in intel_psr_compute_config_late(), and PSR features are 1455 * disabled if wake lines exceed the available guardband. 1456 */ 1457 return _wake_lines_fit_into_vblank(crtc_state, vblank, wake_lines); 1458 } 1459 1460 static bool alpm_config_valid(struct intel_dp *intel_dp, 1461 struct intel_crtc_state *crtc_state, 1462 bool aux_less, 1463 bool needs_panel_replay, 1464 bool needs_sel_update) 1465 { 1466 struct intel_display *display = to_intel_display(intel_dp); 1467 1468 if (!intel_alpm_compute_params(intel_dp, crtc_state)) { 1469 drm_dbg_kms(display->drm, 1470 "PSR2/Panel Replay not enabled, Unable to use long enough wake times\n"); 1471 return false; 1472 } 1473 1474 if (!wake_lines_fit_into_vblank(intel_dp, crtc_state, aux_less, 1475 needs_panel_replay, needs_sel_update)) { 1476 drm_dbg_kms(display->drm, 1477 "PSR2/Panel Replay not enabled, too short vblank time\n"); 1478 return false; 1479 } 1480 1481 return true; 1482 } 1483 1484 static bool intel_psr2_config_valid(struct intel_dp *intel_dp, 1485 struct intel_crtc_state *crtc_state, 1486 struct drm_connector_state *conn_state) 1487 { 1488 struct intel_display *display = to_intel_display(intel_dp); 1489 struct intel_connector *connector = to_intel_connector(conn_state->connector); 1490 int crtc_hdisplay = crtc_state->hw.adjusted_mode.crtc_hdisplay; 1491 int crtc_vdisplay = crtc_state->hw.adjusted_mode.crtc_vdisplay; 1492 int psr_max_h = 0, psr_max_v = 0, max_bpp = 0; 1493 1494 if (!connector->dp.psr_caps.su_support || display->params.enable_psr == 1) 1495 return false; 1496 1497 /* JSL and EHL only supports eDP 1.3 */ 1498 if (display->platform.jasperlake || display->platform.elkhartlake) { 1499 drm_dbg_kms(display->drm, "PSR2 not supported by phy\n"); 1500 return false; 1501 } 1502 1503 /* Wa_16011181250 */ 1504 if (intel_display_wa(display, INTEL_DISPLAY_WA_16011181250)) { 1505 drm_dbg_kms(display->drm, 1506 "PSR2 is defeatured for this platform\n"); 1507 return false; 1508 } 1509 1510 if (display->platform.alderlake_p && IS_DISPLAY_STEP(display, STEP_A0, STEP_B0)) { 1511 drm_dbg_kms(display->drm, 1512 "PSR2 not completely functional in this stepping\n"); 1513 return false; 1514 } 1515 1516 if (!transcoder_has_psr2(display, crtc_state->cpu_transcoder)) { 1517 drm_dbg_kms(display->drm, 1518 "PSR2 not supported in transcoder %s\n", 1519 transcoder_name(crtc_state->cpu_transcoder)); 1520 return false; 1521 } 1522 1523 /* 1524 * DSC and PSR2 cannot be enabled simultaneously. If a requested 1525 * resolution requires DSC to be enabled, priority is given to DSC 1526 * over PSR2. 1527 */ 1528 if (crtc_state->dsc.compression_enable && 1529 (DISPLAY_VER(display) < 14 && !display->platform.alderlake_p)) { 1530 drm_dbg_kms(display->drm, 1531 "PSR2 cannot be enabled since DSC is enabled\n"); 1532 return false; 1533 } 1534 1535 if (DISPLAY_VER(display) >= 20) { 1536 psr_max_h = crtc_hdisplay; 1537 psr_max_v = crtc_vdisplay; 1538 max_bpp = crtc_state->pipe_bpp; 1539 } else if (IS_DISPLAY_VER(display, 12, 14)) { 1540 psr_max_h = 5120; 1541 psr_max_v = 3200; 1542 max_bpp = 30; 1543 } else if (IS_DISPLAY_VER(display, 10, 11)) { 1544 psr_max_h = 4096; 1545 psr_max_v = 2304; 1546 max_bpp = 24; 1547 } else if (DISPLAY_VER(display) == 9) { 1548 psr_max_h = 3640; 1549 psr_max_v = 2304; 1550 max_bpp = 24; 1551 } 1552 1553 if (crtc_state->pipe_bpp > max_bpp) { 1554 drm_dbg_kms(display->drm, 1555 "PSR2 not enabled, pipe bpp %d > max supported %d\n", 1556 crtc_state->pipe_bpp, max_bpp); 1557 return false; 1558 } 1559 1560 /* Wa_16011303918:adl-p */ 1561 if (crtc_state->vrr.enable && 1562 display->platform.alderlake_p && IS_DISPLAY_STEP(display, STEP_A0, STEP_B0)) { 1563 drm_dbg_kms(display->drm, 1564 "PSR2 not enabled, not compatible with HW stepping + VRR\n"); 1565 return false; 1566 } 1567 1568 if (!alpm_config_valid(intel_dp, crtc_state, false, false, true)) 1569 return false; 1570 1571 if (!crtc_state->enable_psr2_sel_fetch && 1572 (crtc_hdisplay > psr_max_h || crtc_vdisplay > psr_max_v)) { 1573 drm_dbg_kms(display->drm, 1574 "PSR2 not enabled, resolution %dx%d > max supported %dx%d\n", 1575 crtc_hdisplay, crtc_vdisplay, 1576 psr_max_h, psr_max_v); 1577 return false; 1578 } 1579 1580 return true; 1581 } 1582 1583 static bool intel_sel_update_config_valid(struct intel_crtc_state *crtc_state, 1584 struct drm_connector_state *conn_state) 1585 { 1586 struct intel_connector *connector = to_intel_connector(conn_state->connector); 1587 struct intel_dp *intel_dp = intel_attached_dp(connector); 1588 struct intel_display *display = to_intel_display(intel_dp); 1589 1590 if (HAS_PSR2_SEL_FETCH(display) && 1591 !intel_psr2_sel_fetch_config_valid(intel_dp, crtc_state) && 1592 !HAS_PSR_HW_TRACKING(display)) { 1593 drm_dbg_kms(display->drm, 1594 "Selective update not enabled, selective fetch not valid and no HW tracking available\n"); 1595 goto unsupported; 1596 } 1597 1598 if (!sel_update_global_enabled(intel_dp)) { 1599 drm_dbg_kms(display->drm, 1600 "Selective update disabled by flag\n"); 1601 goto unsupported; 1602 } 1603 1604 if (!crtc_state->has_panel_replay && !intel_psr2_config_valid(intel_dp, crtc_state, 1605 conn_state)) 1606 goto unsupported; 1607 1608 if (!_compute_psr2_sdp_prior_scanline_indication(crtc_state, connector)) { 1609 drm_dbg_kms(display->drm, 1610 "Selective update not enabled, SDP indication do not fit in hblank\n"); 1611 goto unsupported; 1612 } 1613 1614 if (crtc_state->has_panel_replay) { 1615 if (DISPLAY_VER(display) < 14) 1616 goto unsupported; 1617 1618 if (!connector->dp.panel_replay_caps.su_support) 1619 goto unsupported; 1620 1621 if (intel_dsc_enabled_on_link(crtc_state) && 1622 connector->dp.panel_replay_caps.dsc_support != 1623 INTEL_DP_PANEL_REPLAY_DSC_SELECTIVE_UPDATE) { 1624 drm_dbg_kms(display->drm, 1625 "Selective update with Panel Replay not enabled because it's not supported with DSC\n"); 1626 goto unsupported; 1627 } 1628 } 1629 1630 if (crtc_state->crc_enabled) { 1631 drm_dbg_kms(display->drm, 1632 "Selective update not enabled because it would inhibit pipe CRC calculation\n"); 1633 goto unsupported; 1634 } 1635 1636 if (!psr2_granularity_check(crtc_state, connector)) { 1637 drm_dbg_kms(display->drm, 1638 "Selective update not enabled, SU granularity not compatible\n"); 1639 goto unsupported; 1640 } 1641 1642 crtc_state->enable_psr2_su_region_et = psr2_su_region_et_valid(connector, 1643 crtc_state->has_panel_replay); 1644 1645 return true; 1646 1647 unsupported: 1648 crtc_state->enable_psr2_sel_fetch = false; 1649 return false; 1650 } 1651 1652 static bool _psr_compute_config(struct intel_dp *intel_dp, 1653 struct intel_crtc_state *crtc_state, 1654 struct drm_connector_state *conn_state) 1655 { 1656 struct intel_display *display = to_intel_display(intel_dp); 1657 const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; 1658 int entry_setup_frames; 1659 1660 if (!CAN_PSR(intel_dp) || !display->params.enable_psr) 1661 return false; 1662 1663 /* 1664 * Currently PSR doesn't work reliably with VRR enabled. 1665 */ 1666 if (crtc_state->vrr.enable) 1667 return false; 1668 1669 entry_setup_frames = intel_psr_entry_setup_frames(intel_dp, conn_state, adjusted_mode); 1670 1671 if (entry_setup_frames >= 0) { 1672 crtc_state->entry_setup_frames = entry_setup_frames; 1673 } else { 1674 crtc_state->no_psr_reason = "PSR setup timing not met"; 1675 drm_dbg_kms(display->drm, 1676 "PSR condition failed: PSR setup timing not met\n"); 1677 return false; 1678 } 1679 1680 return true; 1681 } 1682 1683 static inline bool compute_link_off_after_as_sdp_when_pr_active(struct intel_connector *connector) 1684 { 1685 return (connector->dp.panel_replay_caps.dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_CAPABILITY)] & 1686 DP_PANEL_REPLAY_LINK_OFF_SUPPORTED_IN_PR_AFTER_ADAPTIVE_SYNC_SDP); 1687 } 1688 1689 static inline bool compute_disable_as_sdp_when_pr_active(struct intel_connector *connector) 1690 { 1691 return !(connector->dp.panel_replay_caps.dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_CAPABILITY)] & 1692 DP_PANEL_REPLAY_ASYNC_VIDEO_TIMING_NOT_SUPPORTED_IN_PR); 1693 } 1694 1695 static bool _panel_replay_compute_config(struct intel_crtc_state *crtc_state, 1696 const struct drm_connector_state *conn_state) 1697 { 1698 struct intel_connector *connector = 1699 to_intel_connector(conn_state->connector); 1700 struct intel_dp *intel_dp = intel_attached_dp(connector); 1701 struct intel_display *display = to_intel_display(intel_dp); 1702 struct intel_hdcp *hdcp = &connector->hdcp; 1703 1704 if (!CAN_PANEL_REPLAY(intel_dp)) 1705 return false; 1706 1707 if (!connector->dp.panel_replay_caps.support) 1708 return false; 1709 1710 if (!panel_replay_global_enabled(intel_dp)) { 1711 drm_dbg_kms(display->drm, "Panel Replay disabled by flag\n"); 1712 return false; 1713 } 1714 1715 if (crtc_state->crc_enabled) { 1716 drm_dbg_kms(display->drm, 1717 "Panel Replay not enabled because it would inhibit pipe CRC calculation\n"); 1718 return false; 1719 } 1720 1721 if (intel_dsc_enabled_on_link(crtc_state) && 1722 connector->dp.panel_replay_caps.dsc_support == 1723 INTEL_DP_PANEL_REPLAY_DSC_NOT_SUPPORTED) { 1724 drm_dbg_kms(display->drm, 1725 "Panel Replay not enabled because it's not supported with DSC\n"); 1726 return false; 1727 } 1728 1729 crtc_state->link_off_after_as_sdp_when_pr_active = compute_link_off_after_as_sdp_when_pr_active(connector); 1730 crtc_state->disable_as_sdp_when_pr_active = compute_disable_as_sdp_when_pr_active(connector); 1731 1732 if (!intel_dp_is_edp(intel_dp)) 1733 return true; 1734 1735 /* Remaining checks are for eDP only */ 1736 1737 if (to_intel_crtc(crtc_state->uapi.crtc)->pipe != PIPE_A && 1738 to_intel_crtc(crtc_state->uapi.crtc)->pipe != PIPE_B) 1739 return false; 1740 1741 /* 128b/132b Panel Replay is not supported on eDP */ 1742 if (intel_dp_is_uhbr(crtc_state)) { 1743 drm_dbg_kms(display->drm, 1744 "Panel Replay is not supported with 128b/132b\n"); 1745 return false; 1746 } 1747 1748 /* HW will not allow Panel Replay on eDP when HDCP enabled */ 1749 if (conn_state->content_protection == 1750 DRM_MODE_CONTENT_PROTECTION_DESIRED || 1751 (conn_state->content_protection == 1752 DRM_MODE_CONTENT_PROTECTION_ENABLED && hdcp->value == 1753 DRM_MODE_CONTENT_PROTECTION_UNDESIRED)) { 1754 drm_dbg_kms(display->drm, 1755 "Panel Replay is not supported with HDCP\n"); 1756 return false; 1757 } 1758 1759 if (!alpm_config_valid(intel_dp, crtc_state, true, true, false)) 1760 return false; 1761 1762 return true; 1763 } 1764 1765 static bool intel_psr_needs_wa_18037818876(struct intel_dp *intel_dp, 1766 struct intel_crtc_state *crtc_state) 1767 { 1768 struct intel_display *display = to_intel_display(intel_dp); 1769 1770 return (DISPLAY_VER(display) == 20 && crtc_state->entry_setup_frames > 0 && 1771 !crtc_state->has_sel_update); 1772 } 1773 1774 static void psr2_dc3co_disable_locked(struct intel_dp *intel_dp) 1775 { 1776 struct intel_display *display = to_intel_display(intel_dp); 1777 1778 if (intel_dp->psr.dc3co_allowed) { 1779 intel_dp->psr.dc3co_allowed = false; 1780 intel_display_power_set_target_dc_state(display, DC_STATE_EN_UPTO_DC6); 1781 psr2_program_idle_frames(intel_dp, psr_compute_idle_frames(intel_dp)); 1782 } 1783 } 1784 1785 static void psr2_dc3co_disable_work(struct work_struct *work) 1786 { 1787 struct intel_dp *intel_dp = 1788 container_of(work, typeof(*intel_dp), psr.dc3co_work.work); 1789 1790 mutex_lock(&intel_dp->psr.lock); 1791 psr2_dc3co_disable_locked(intel_dp); 1792 mutex_unlock(&intel_dp->psr.lock); 1793 } 1794 1795 static void 1796 psr2_dc3co_flush_locked(struct intel_dp *intel_dp, unsigned int frontbuffer_bits) 1797 { 1798 struct intel_display *display = to_intel_display(intel_dp); 1799 1800 if (!intel_dp->psr.dc3co_allowed) 1801 return; 1802 1803 if (!intel_dp->psr.sel_update_enabled || 1804 !intel_dp->psr.active) 1805 return; 1806 /* 1807 * At every frontbuffer flush flip event modified delay of delayed work, 1808 * when delayed work schedules that means display has been idle. 1809 */ 1810 if (!(frontbuffer_bits & 1811 INTEL_FRONTBUFFER_ALL_MASK(intel_dp->psr.pipe))) 1812 return; 1813 1814 mod_delayed_work(display->wq.unordered, &intel_dp->psr.dc3co_work, 1815 intel_dp->psr.dc3co_exit_delay); 1816 } 1817 1818 static 1819 void intel_psr_set_non_psr_pipes(struct intel_dp *intel_dp, 1820 struct intel_crtc_state *crtc_state) 1821 { 1822 struct intel_display *display = to_intel_display(intel_dp); 1823 struct intel_atomic_state *state = to_intel_atomic_state(crtc_state->uapi.state); 1824 struct intel_crtc *crtc; 1825 u8 active_pipes = 0; 1826 1827 /* Wa_16025596647 */ 1828 if (!intel_display_wa(display, INTEL_DISPLAY_WA_16025596647)) 1829 return; 1830 1831 /* Not needed by Panel Replay */ 1832 if (crtc_state->has_panel_replay) 1833 return; 1834 1835 /* We ignore possible secondary PSR/Panel Replay capable eDP */ 1836 for_each_intel_crtc(display, crtc) 1837 active_pipes |= crtc->active ? BIT(crtc->pipe) : 0; 1838 1839 active_pipes = intel_calc_active_pipes(state, active_pipes); 1840 1841 crtc_state->active_non_psr_pipes = active_pipes & 1842 ~BIT(to_intel_crtc(crtc_state->uapi.crtc)->pipe); 1843 } 1844 1845 void intel_psr_compute_config(struct intel_dp *intel_dp, 1846 struct intel_crtc_state *crtc_state, 1847 struct drm_connector_state *conn_state) 1848 { 1849 struct intel_display *display = to_intel_display(intel_dp); 1850 struct intel_connector *connector = to_intel_connector(conn_state->connector); 1851 const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; 1852 1853 if (!psr_global_enabled(intel_dp)) { 1854 drm_dbg_kms(display->drm, "PSR disabled by flag\n"); 1855 return; 1856 } 1857 1858 if (intel_dp->psr.sink_not_reliable) { 1859 drm_dbg_kms(display->drm, 1860 "PSR sink implementation is not reliable\n"); 1861 return; 1862 } 1863 1864 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { 1865 drm_dbg_kms(display->drm, 1866 "PSR condition failed: Interlaced mode enabled\n"); 1867 return; 1868 } 1869 1870 /* 1871 * FIXME figure out what is wrong with PSR+joiner and 1872 * fix it. Presumably something related to the fact that 1873 * PSR is a transcoder level feature. 1874 */ 1875 if (crtc_state->joiner_pipes) { 1876 drm_dbg_kms(display->drm, 1877 "PSR disabled due to joiner\n"); 1878 return; 1879 } 1880 1881 /* Only used for state verification. */ 1882 crtc_state->panel_replay_dsc_support = connector->dp.panel_replay_caps.dsc_support; 1883 crtc_state->has_panel_replay = _panel_replay_compute_config(crtc_state, conn_state); 1884 1885 crtc_state->has_psr = crtc_state->has_panel_replay ? true : 1886 _psr_compute_config(intel_dp, crtc_state, conn_state); 1887 1888 if (!crtc_state->has_psr) 1889 return; 1890 1891 crtc_state->has_sel_update = intel_sel_update_config_valid(crtc_state, conn_state); 1892 } 1893 1894 void intel_psr_get_config(struct intel_encoder *encoder, 1895 struct intel_crtc_state *pipe_config) 1896 { 1897 struct intel_display *display = to_intel_display(encoder); 1898 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 1899 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; 1900 struct intel_dp *intel_dp; 1901 u32 val; 1902 1903 if (!dig_port) 1904 return; 1905 1906 intel_dp = &dig_port->dp; 1907 if (!(CAN_PSR(intel_dp) || CAN_PANEL_REPLAY(intel_dp))) 1908 return; 1909 1910 mutex_lock(&intel_dp->psr.lock); 1911 if (!intel_dp->psr.enabled) 1912 goto unlock; 1913 1914 if (intel_dp->psr.panel_replay_enabled) { 1915 pipe_config->has_psr = pipe_config->has_panel_replay = true; 1916 } else { 1917 /* 1918 * Not possible to read EDP_PSR/PSR2_CTL registers as it is 1919 * enabled/disabled because of frontbuffer tracking and others. 1920 */ 1921 pipe_config->has_psr = true; 1922 } 1923 1924 pipe_config->has_sel_update = intel_dp->psr.sel_update_enabled; 1925 pipe_config->infoframes.enable |= intel_hdmi_infoframe_enable(DP_SDP_VSC); 1926 1927 if (!intel_dp->psr.sel_update_enabled) 1928 goto unlock; 1929 1930 if (HAS_PSR2_SEL_FETCH(display)) { 1931 val = intel_de_read(display, 1932 PSR2_MAN_TRK_CTL(display, cpu_transcoder)); 1933 if (val & PSR2_MAN_TRK_CTL_ENABLE) 1934 pipe_config->enable_psr2_sel_fetch = true; 1935 } 1936 1937 pipe_config->enable_psr2_su_region_et = intel_dp->psr.su_region_et_enabled; 1938 unlock: 1939 mutex_unlock(&intel_dp->psr.lock); 1940 } 1941 1942 static void intel_psr_activate(struct intel_dp *intel_dp) 1943 { 1944 struct intel_display *display = to_intel_display(intel_dp); 1945 enum transcoder cpu_transcoder = intel_dp->psr.transcoder; 1946 1947 drm_WARN_ON(display->drm, 1948 transcoder_has_psr2(display, cpu_transcoder) && 1949 intel_de_read(display, EDP_PSR2_CTL(display, cpu_transcoder)) & EDP_PSR2_ENABLE); 1950 1951 drm_WARN_ON(display->drm, 1952 intel_de_read(display, psr_ctl_reg(display, cpu_transcoder)) & EDP_PSR_ENABLE); 1953 1954 drm_WARN_ON(display->drm, intel_dp->psr.active); 1955 1956 drm_WARN_ON(display->drm, !intel_dp->psr.enabled); 1957 1958 lockdep_assert_held(&intel_dp->psr.lock); 1959 1960 /* psr1, psr2 and panel-replay are mutually exclusive.*/ 1961 if (intel_dp->psr.panel_replay_enabled) 1962 dg2_activate_panel_replay(intel_dp); 1963 else if (intel_dp->psr.sel_update_enabled) 1964 hsw_activate_psr2(intel_dp); 1965 else 1966 hsw_activate_psr1(intel_dp); 1967 1968 intel_dp->psr.active = true; 1969 intel_dp->psr.no_psr_reason = NULL; 1970 } 1971 1972 /* 1973 * Wa_16013835468 1974 * Wa_14015648006 1975 */ 1976 static void wm_optimization_wa(struct intel_dp *intel_dp, 1977 const struct intel_crtc_state *crtc_state) 1978 { 1979 struct intel_display *display = to_intel_display(intel_dp); 1980 enum pipe pipe = intel_dp->psr.pipe; 1981 bool activate = false; 1982 1983 /* Wa_14015648006 */ 1984 if (IS_DISPLAY_VER(display, 11, 14) && crtc_state->wm_level_disabled) 1985 activate = true; 1986 1987 /* Wa_16013835468 */ 1988 if (DISPLAY_VER(display) == 12 && 1989 crtc_state->hw.adjusted_mode.crtc_vblank_start != 1990 crtc_state->hw.adjusted_mode.crtc_vdisplay) 1991 activate = true; 1992 1993 if (activate) 1994 intel_de_rmw(display, GEN8_CHICKEN_DCPR_1, 1995 0, LATENCY_REPORTING_REMOVED(pipe)); 1996 else 1997 intel_de_rmw(display, GEN8_CHICKEN_DCPR_1, 1998 LATENCY_REPORTING_REMOVED(pipe), 0); 1999 } 2000 2001 static void intel_psr_enable_source(struct intel_dp *intel_dp, 2002 const struct intel_crtc_state *crtc_state) 2003 { 2004 struct intel_display *display = to_intel_display(intel_dp); 2005 enum transcoder cpu_transcoder = intel_dp->psr.transcoder; 2006 u32 mask = 0; 2007 2008 /* 2009 * Only HSW and BDW have PSR AUX registers that need to be setup. 2010 * SKL+ use hardcoded values PSR AUX transactions 2011 */ 2012 if (DISPLAY_VER(display) < 9) 2013 hsw_psr_setup_aux(intel_dp); 2014 2015 /* 2016 * Per Spec: Avoid continuous PSR exit by masking MEMUP and HPD also 2017 * mask LPSP to avoid dependency on other drivers that might block 2018 * runtime_pm besides preventing other hw tracking issues now we 2019 * can rely on frontbuffer tracking. 2020 * 2021 * From bspec prior LunarLake: 2022 * Only PSR_MASK[Mask FBC modify] and PSR_MASK[Mask Hotplug] are used in 2023 * panel replay mode. 2024 * 2025 * From bspec beyod LunarLake: 2026 * Panel Replay on DP: No bits are applicable 2027 * Panel Replay on eDP: All bits are applicable 2028 */ 2029 if (DISPLAY_VER(display) < 20 || intel_dp_is_edp(intel_dp)) 2030 mask = EDP_PSR_DEBUG_MASK_HPD; 2031 2032 if (intel_dp_is_edp(intel_dp)) { 2033 mask |= EDP_PSR_DEBUG_MASK_MEMUP; 2034 2035 /* 2036 * For some unknown reason on HSW non-ULT (or at least on 2037 * Dell Latitude E6540) external displays start to flicker 2038 * when PSR is enabled on the eDP. SR/PC6 residency is much 2039 * higher than should be possible with an external display. 2040 * As a workaround leave LPSP unmasked to prevent PSR entry 2041 * when external displays are active. 2042 */ 2043 if (DISPLAY_VER(display) >= 8 || display->platform.haswell_ult) 2044 mask |= EDP_PSR_DEBUG_MASK_LPSP; 2045 2046 if (DISPLAY_VER(display) < 20) 2047 mask |= EDP_PSR_DEBUG_MASK_MAX_SLEEP; 2048 2049 /* 2050 * No separate pipe reg write mask on hsw/bdw, so have to unmask all 2051 * registers in order to keep the CURSURFLIVE tricks working :( 2052 */ 2053 if (IS_DISPLAY_VER(display, 9, 10)) 2054 mask |= EDP_PSR_DEBUG_MASK_DISP_REG_WRITE; 2055 2056 /* allow PSR with sprite enabled */ 2057 if (display->platform.haswell) 2058 mask |= EDP_PSR_DEBUG_MASK_SPRITE_ENABLE; 2059 } 2060 2061 intel_de_write(display, psr_debug_reg(display, cpu_transcoder), mask); 2062 2063 psr_irq_control(intel_dp); 2064 2065 if (HAS_PSR_HW_TRACKING(display) && HAS_PSR2_SEL_FETCH(display)) 2066 intel_de_rmw(display, CHICKEN_PAR1_1, IGNORE_PSR2_HW_TRACKING, 2067 intel_dp->psr.psr2_sel_fetch_enabled ? 2068 IGNORE_PSR2_HW_TRACKING : 0); 2069 2070 /* 2071 * Wa_16013835468 2072 * Wa_14015648006 2073 */ 2074 wm_optimization_wa(intel_dp, crtc_state); 2075 2076 if (intel_dp->psr.sel_update_enabled) { 2077 if (DISPLAY_VER(display) == 9) 2078 intel_de_rmw(display, CHICKEN_TRANS(display, cpu_transcoder), 0, 2079 PSR2_VSC_ENABLE_PROG_HEADER | 2080 PSR2_ADD_VERTICAL_LINE_COUNT); 2081 2082 /* 2083 * Wa_16014451276:adlp,mtl[a0,b0] 2084 * All supported adlp panels have 1-based X granularity, this may 2085 * cause issues if non-supported panels are used. 2086 */ 2087 if (!intel_dp->psr.panel_replay_enabled && 2088 (IS_DISPLAY_VERx100_STEP(display, 1400, STEP_A0, STEP_B0) || 2089 display->platform.alderlake_p)) 2090 intel_de_rmw(display, CHICKEN_TRANS(display, cpu_transcoder), 2091 0, ADLP_1_BASED_X_GRANULARITY); 2092 2093 /* Wa_16012604467:adlp,mtl[a0,b0] */ 2094 if (!intel_dp->psr.panel_replay_enabled && 2095 IS_DISPLAY_VERx100_STEP(display, 1400, STEP_A0, STEP_B0)) 2096 intel_de_rmw(display, 2097 MTL_CLKGATE_DIS_TRANS(display, cpu_transcoder), 2098 0, 2099 MTL_CLKGATE_DIS_TRANS_DMASC_GATING_DIS); 2100 else if (display->platform.alderlake_p) 2101 intel_de_rmw(display, CLKGATE_DIS_MISC, 0, 2102 CLKGATE_DIS_MISC_DMASC_GATING_DIS); 2103 } 2104 2105 /* Wa_16025596647 */ 2106 if ((DISPLAY_VER(display) == 20 || 2107 IS_DISPLAY_VERx100_STEP(display, 3000, STEP_A0, STEP_B0)) && 2108 !intel_dp->psr.panel_replay_enabled) 2109 intel_dmc_block_pkgc(display, intel_dp->psr.pipe, true); 2110 2111 intel_alpm_configure(intel_dp, crtc_state); 2112 2113 if (HAS_PSR_TRANS_PUSH_FRAME_CHANGE(display)) 2114 intel_vrr_psr_frame_change_enable(crtc_state); 2115 } 2116 2117 static bool psr_interrupt_error_check(struct intel_dp *intel_dp) 2118 { 2119 struct intel_display *display = to_intel_display(intel_dp); 2120 enum transcoder cpu_transcoder = intel_dp->psr.transcoder; 2121 u32 val; 2122 2123 if (intel_dp->psr.panel_replay_enabled) 2124 goto no_err; 2125 2126 /* 2127 * If a PSR error happened and the driver is reloaded, the EDP_PSR_IIR 2128 * will still keep the error set even after the reset done in the 2129 * irq_preinstall and irq_uninstall hooks. 2130 * And enabling in this situation cause the screen to freeze in the 2131 * first time that PSR HW tries to activate so lets keep PSR disabled 2132 * to avoid any rendering problems. 2133 */ 2134 val = intel_de_read(display, psr_iir_reg(display, cpu_transcoder)); 2135 val &= psr_irq_psr_error_bit_get(intel_dp); 2136 if (val) { 2137 intel_dp->psr.sink_not_reliable = true; 2138 drm_dbg_kms(display->drm, 2139 "PSR interruption error set, not enabling PSR\n"); 2140 return false; 2141 } 2142 2143 no_err: 2144 return true; 2145 } 2146 2147 static void intel_psr_enable_locked(struct intel_dp *intel_dp, 2148 const struct intel_crtc_state *crtc_state) 2149 { 2150 struct intel_display *display = to_intel_display(intel_dp); 2151 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 2152 u32 val; 2153 2154 drm_WARN_ON(display->drm, intel_dp->psr.enabled); 2155 2156 intel_dp->psr.sel_update_enabled = crtc_state->has_sel_update; 2157 intel_dp->psr.panel_replay_enabled = crtc_state->has_panel_replay; 2158 intel_dp->psr.busy_frontbuffer_bits = 0; 2159 intel_dp->psr.pipe = to_intel_crtc(crtc_state->uapi.crtc)->pipe; 2160 intel_dp->psr.transcoder = crtc_state->cpu_transcoder; 2161 /* DC5/DC6 requires at least 6 idle frames */ 2162 val = usecs_to_jiffies(intel_get_frame_time_us(crtc_state) * 6); 2163 intel_dp->psr.dc3co_exit_delay = val; 2164 intel_dp->psr.psr2_sel_fetch_enabled = crtc_state->enable_psr2_sel_fetch; 2165 intel_dp->psr.su_region_et_enabled = crtc_state->enable_psr2_su_region_et; 2166 intel_dp->psr.psr2_sel_fetch_cff_enabled = false; 2167 intel_dp->psr.req_psr2_sdp_prior_scanline = 2168 crtc_state->req_psr2_sdp_prior_scanline; 2169 intel_dp->psr.active_non_psr_pipes = crtc_state->active_non_psr_pipes; 2170 intel_dp->psr.pkg_c_latency_used = crtc_state->pkg_c_latency_used; 2171 intel_dp->psr.io_wake_lines = crtc_state->alpm_state.io_wake_lines; 2172 intel_dp->psr.fast_wake_lines = crtc_state->alpm_state.fast_wake_lines; 2173 intel_dp->psr.entry_setup_frames = crtc_state->entry_setup_frames; 2174 2175 if (!psr_interrupt_error_check(intel_dp)) 2176 return; 2177 2178 if (intel_dp->psr.panel_replay_enabled) 2179 drm_dbg_kms(display->drm, "Enabling Panel Replay\n"); 2180 else 2181 drm_dbg_kms(display->drm, "Enabling PSR%s\n", 2182 intel_dp->psr.sel_update_enabled ? "2" : "1"); 2183 2184 /* 2185 * Enabling sink PSR/Panel Replay here only for PSR. Panel Replay enable 2186 * bit is already written at this point. Sink ALPM is enabled here for 2187 * PSR and Panel Replay. See 2188 * intel_psr_panel_replay_enable_sink. Modifiers/options: 2189 * - Selective Update 2190 * - Region Early Transport 2191 * - Selective Update Region Scanline Capture 2192 * - VSC_SDP_CRC 2193 * - HPD on different Errors 2194 * - CRC verification 2195 * are written for PSR and Panel Replay here. 2196 */ 2197 intel_psr_enable_sink(intel_dp, crtc_state); 2198 2199 if (intel_dp_is_edp(intel_dp)) 2200 intel_snps_phy_update_psr_power_state(&dig_port->base, true); 2201 2202 intel_psr_enable_source(intel_dp, crtc_state); 2203 intel_dp->psr.enabled = true; 2204 intel_dp->psr.pause_counter = 0; 2205 2206 /* 2207 * Link_ok is sticky and set here on PSR enable. We can assume link 2208 * training is complete as we never continue to PSR enable with 2209 * untrained link. Link_ok is kept as set until first short pulse 2210 * interrupt. This is targeted to workaround panels stating bad link 2211 * after PSR is enabled. 2212 */ 2213 intel_dp->psr.link_ok = true; 2214 2215 intel_psr_activate(intel_dp); 2216 } 2217 2218 static void intel_psr_exit(struct intel_dp *intel_dp) 2219 { 2220 struct intel_display *display = to_intel_display(intel_dp); 2221 enum transcoder cpu_transcoder = intel_dp->psr.transcoder; 2222 u32 val; 2223 2224 if (!intel_dp->psr.active) { 2225 if (transcoder_has_psr2(display, cpu_transcoder)) { 2226 val = intel_de_read(display, 2227 EDP_PSR2_CTL(display, cpu_transcoder)); 2228 drm_WARN_ON(display->drm, val & EDP_PSR2_ENABLE); 2229 } 2230 2231 val = intel_de_read(display, 2232 psr_ctl_reg(display, cpu_transcoder)); 2233 drm_WARN_ON(display->drm, val & EDP_PSR_ENABLE); 2234 2235 return; 2236 } 2237 2238 if (intel_dp->psr.panel_replay_enabled) { 2239 intel_de_rmw(display, TRANS_DP2_CTL(intel_dp->psr.transcoder), 2240 TRANS_DP2_PANEL_REPLAY_ENABLE, 0); 2241 } else if (intel_dp->psr.sel_update_enabled) { 2242 val = intel_de_rmw(display, 2243 EDP_PSR2_CTL(display, cpu_transcoder), 2244 EDP_PSR2_ENABLE, 0); 2245 2246 drm_WARN_ON(display->drm, !(val & EDP_PSR2_ENABLE)); 2247 } else { 2248 if ((DISPLAY_VER(display) == 20 || 2249 IS_DISPLAY_VERx100_STEP(display, 3000, STEP_A0, STEP_B0)) && 2250 intel_dp->psr.pkg_c_latency_used) 2251 intel_dmc_start_pkgc_exit_at_start_of_undelayed_vblank(display, 2252 intel_dp->psr.pipe, 2253 false); 2254 2255 val = intel_de_rmw(display, 2256 psr_ctl_reg(display, cpu_transcoder), 2257 EDP_PSR_ENABLE, 0); 2258 2259 drm_WARN_ON(display->drm, !(val & EDP_PSR_ENABLE)); 2260 } 2261 intel_dp->psr.active = false; 2262 } 2263 2264 bool intel_psr2_in_deep_sleep(struct intel_dp *intel_dp) 2265 { 2266 struct intel_display *display = to_intel_display(intel_dp); 2267 enum transcoder cpu_transcoder; 2268 bool in_deep_sleep = false; 2269 u32 val; 2270 2271 mutex_lock(&intel_dp->psr.lock); 2272 2273 if (!intel_dp->psr.enabled || !intel_dp->psr.sel_update_enabled) 2274 goto out; 2275 2276 cpu_transcoder = intel_dp->psr.transcoder; 2277 val = intel_de_read(display, EDP_PSR2_STATUS(display, cpu_transcoder)); 2278 in_deep_sleep = (val & EDP_PSR2_STATUS_STATE_MASK) == 2279 EDP_PSR2_STATUS_STATE_DEEP_SLEEP; 2280 out: 2281 mutex_unlock(&intel_dp->psr.lock); 2282 return in_deep_sleep; 2283 } 2284 2285 static void intel_psr_wait_exit_locked(struct intel_dp *intel_dp) 2286 { 2287 struct intel_display *display = to_intel_display(intel_dp); 2288 enum transcoder cpu_transcoder = intel_dp->psr.transcoder; 2289 intel_reg_t psr_status; 2290 u32 psr_status_mask; 2291 2292 if (intel_dp_is_edp(intel_dp) && (intel_dp->psr.sel_update_enabled || 2293 intel_dp->psr.panel_replay_enabled)) { 2294 psr_status = EDP_PSR2_STATUS(display, cpu_transcoder); 2295 psr_status_mask = EDP_PSR2_STATUS_STATE_MASK; 2296 } else { 2297 psr_status = psr_status_reg(display, cpu_transcoder); 2298 psr_status_mask = EDP_PSR_STATUS_STATE_MASK; 2299 } 2300 2301 /* Wait till PSR is idle */ 2302 if (intel_de_wait_for_clear_ms(display, psr_status, 2303 psr_status_mask, 2000)) 2304 drm_err(display->drm, "Timed out waiting PSR idle state\n"); 2305 } 2306 2307 static void intel_psr_disable_locked(struct intel_dp *intel_dp) 2308 { 2309 struct intel_display *display = to_intel_display(intel_dp); 2310 enum transcoder cpu_transcoder = intel_dp->psr.transcoder; 2311 2312 lockdep_assert_held(&intel_dp->psr.lock); 2313 2314 if (!intel_dp->psr.enabled) 2315 return; 2316 2317 if (intel_dp->psr.panel_replay_enabled) 2318 drm_dbg_kms(display->drm, "Disabling Panel Replay\n"); 2319 else 2320 drm_dbg_kms(display->drm, "Disabling PSR%s\n", 2321 intel_dp->psr.sel_update_enabled ? "2" : "1"); 2322 2323 intel_psr_exit(intel_dp); 2324 intel_psr_wait_exit_locked(intel_dp); 2325 2326 /* 2327 * Wa_16013835468 2328 * Wa_14015648006 2329 */ 2330 if (DISPLAY_VER(display) >= 11) 2331 intel_de_rmw(display, GEN8_CHICKEN_DCPR_1, 2332 LATENCY_REPORTING_REMOVED(intel_dp->psr.pipe), 0); 2333 2334 if (intel_dp->psr.sel_update_enabled) { 2335 /* Wa_16012604467:adlp,mtl[a0,b0] */ 2336 if (!intel_dp->psr.panel_replay_enabled && 2337 IS_DISPLAY_VERx100_STEP(display, 1400, STEP_A0, STEP_B0)) 2338 intel_de_rmw(display, 2339 MTL_CLKGATE_DIS_TRANS(display, cpu_transcoder), 2340 MTL_CLKGATE_DIS_TRANS_DMASC_GATING_DIS, 0); 2341 else if (display->platform.alderlake_p) 2342 intel_de_rmw(display, CLKGATE_DIS_MISC, 2343 CLKGATE_DIS_MISC_DMASC_GATING_DIS, 0); 2344 } 2345 2346 if (intel_dp_is_edp(intel_dp)) 2347 intel_snps_phy_update_psr_power_state(&dp_to_dig_port(intel_dp)->base, false); 2348 2349 if (intel_dp->psr.panel_replay_enabled && intel_dp_is_edp(intel_dp)) 2350 intel_alpm_disable(intel_dp); 2351 2352 /* Disable PSR on Sink */ 2353 if (!intel_dp->psr.panel_replay_enabled) { 2354 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, 0); 2355 2356 if (intel_dp->psr.sel_update_enabled) 2357 drm_dp_dpcd_writeb(&intel_dp->aux, 2358 DP_RECEIVER_ALPM_CONFIG, 0); 2359 } 2360 2361 /* Wa_16025596647 */ 2362 if ((DISPLAY_VER(display) == 20 || 2363 IS_DISPLAY_VERx100_STEP(display, 3000, STEP_A0, STEP_B0)) && 2364 !intel_dp->psr.panel_replay_enabled) 2365 intel_dmc_block_pkgc(display, intel_dp->psr.pipe, false); 2366 2367 intel_dp->psr.enabled = false; 2368 intel_dp->psr.panel_replay_enabled = false; 2369 intel_dp->psr.sel_update_enabled = false; 2370 intel_dp->psr.psr2_sel_fetch_enabled = false; 2371 intel_dp->psr.su_region_et_enabled = false; 2372 intel_dp->psr.psr2_sel_fetch_cff_enabled = false; 2373 intel_dp->psr.active_non_psr_pipes = 0; 2374 intel_dp->psr.pkg_c_latency_used = 0; 2375 cancel_delayed_work(&intel_dp->psr.dc3co_work); 2376 intel_dp->psr.dc3co_allowed = false; 2377 } 2378 2379 /** 2380 * intel_psr_disable - Disable PSR 2381 * @intel_dp: Intel DP 2382 * @old_crtc_state: old CRTC state 2383 * 2384 * This function needs to be called before disabling pipe. 2385 */ 2386 void intel_psr_disable(struct intel_dp *intel_dp, 2387 const struct intel_crtc_state *old_crtc_state) 2388 { 2389 struct intel_display *display = to_intel_display(intel_dp); 2390 2391 if (!old_crtc_state->has_psr) 2392 return; 2393 2394 if (drm_WARN_ON(display->drm, !CAN_PSR(intel_dp) && 2395 !CAN_PANEL_REPLAY(intel_dp))) 2396 return; 2397 2398 mutex_lock(&intel_dp->psr.lock); 2399 2400 intel_psr_disable_locked(intel_dp); 2401 2402 intel_dp->psr.link_ok = false; 2403 2404 mutex_unlock(&intel_dp->psr.lock); 2405 cancel_work_sync(&intel_dp->psr.work); 2406 cancel_delayed_work_sync(&intel_dp->psr.dc3co_work); 2407 } 2408 2409 /** 2410 * intel_psr_pause - Pause PSR 2411 * @intel_dp: Intel DP 2412 * 2413 * This function need to be called after enabling psr. 2414 */ 2415 void intel_psr_pause(struct intel_dp *intel_dp) 2416 { 2417 struct intel_psr *psr = &intel_dp->psr; 2418 2419 if (!CAN_PSR(intel_dp) && !CAN_PANEL_REPLAY(intel_dp)) 2420 return; 2421 2422 mutex_lock(&psr->lock); 2423 2424 if (!psr->enabled) { 2425 mutex_unlock(&psr->lock); 2426 return; 2427 } 2428 2429 if (intel_dp->psr.pause_counter++ == 0) { 2430 intel_psr_exit(intel_dp); 2431 intel_psr_wait_exit_locked(intel_dp); 2432 } 2433 2434 mutex_unlock(&psr->lock); 2435 2436 cancel_work_sync(&psr->work); 2437 cancel_delayed_work_sync(&psr->dc3co_work); 2438 } 2439 2440 /** 2441 * intel_psr_resume - Resume PSR 2442 * @intel_dp: Intel DP 2443 * 2444 * This function need to be called after pausing psr. 2445 */ 2446 void intel_psr_resume(struct intel_dp *intel_dp) 2447 { 2448 struct intel_display *display = to_intel_display(intel_dp); 2449 struct intel_psr *psr = &intel_dp->psr; 2450 2451 if (!CAN_PSR(intel_dp) && !CAN_PANEL_REPLAY(intel_dp)) 2452 return; 2453 2454 mutex_lock(&psr->lock); 2455 2456 if (!psr->enabled) 2457 goto out; 2458 2459 if (!psr->pause_counter) { 2460 drm_warn(display->drm, "Unbalanced PSR pause/resume!\n"); 2461 goto out; 2462 } 2463 2464 if (--intel_dp->psr.pause_counter == 0) { 2465 intel_psr_activate(intel_dp); 2466 /* re-arm cancelled dc3co work from pause */ 2467 if (intel_dp->psr.dc3co_allowed) 2468 mod_delayed_work(display->wq.unordered, &intel_dp->psr.dc3co_work, 2469 intel_dp->psr.dc3co_exit_delay); 2470 } 2471 2472 out: 2473 mutex_unlock(&psr->lock); 2474 } 2475 2476 /** 2477 * intel_psr_needs_vblank_notification - Check if PSR need vblank enable/disable 2478 * notification. 2479 * @crtc_state: CRTC status 2480 * 2481 * We need to block DC6 entry in case of Panel Replay as enabling VBI doesn't 2482 * prevent it in case of Panel Replay. Panel Replay switches main link off on 2483 * DC entry. This means vblank interrupts are not fired and is a problem if 2484 * user-space is polling for vblank events. Also Wa_16025596647 needs 2485 * information when vblank is enabled/disabled. 2486 */ 2487 bool intel_psr_needs_vblank_notification(const struct intel_crtc_state *crtc_state) 2488 { 2489 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2490 struct intel_display *display = to_intel_display(crtc_state); 2491 struct intel_encoder *encoder; 2492 2493 for_each_encoder_on_crtc(crtc->base.dev, &crtc->base, encoder) { 2494 struct intel_dp *intel_dp; 2495 2496 if (!intel_encoder_is_dp(encoder)) 2497 continue; 2498 2499 intel_dp = enc_to_intel_dp(encoder); 2500 2501 if (!intel_dp_is_edp(intel_dp)) 2502 continue; 2503 2504 if (CAN_PANEL_REPLAY(intel_dp)) 2505 return true; 2506 2507 if ((DISPLAY_VER(display) == 20 || 2508 IS_DISPLAY_VERx100_STEP(display, 3000, STEP_A0, STEP_B0)) && 2509 CAN_PSR(intel_dp)) 2510 return true; 2511 } 2512 2513 return false; 2514 } 2515 2516 /** 2517 * intel_psr_trigger_frame_change_event - Trigger "Frame Change" event 2518 * @dsb: DSB context 2519 * @state: the atomic state 2520 * @crtc: the CRTC 2521 * 2522 * Generate PSR "Frame Change" event. 2523 */ 2524 void intel_psr_trigger_frame_change_event(struct intel_dsb *dsb, 2525 struct intel_atomic_state *state, 2526 struct intel_crtc *crtc) 2527 { 2528 const struct intel_crtc_state *crtc_state = 2529 intel_pre_commit_crtc_state(state, crtc); 2530 struct intel_display *display = to_intel_display(crtc); 2531 2532 if (!crtc_state->has_psr || intel_psr_use_trans_push(crtc_state)) 2533 return; 2534 2535 intel_de_write_dsb(display, dsb, 2536 CURSURFLIVE(display, crtc->pipe), 0); 2537 } 2538 2539 /** 2540 * intel_psr_min_set_context_latency - Minimum 'set context latency' lines needed by PSR 2541 * @crtc_state: the crtc state 2542 * 2543 * Return minimum SCL lines/delay needed by PSR. 2544 */ 2545 int intel_psr_min_set_context_latency(const struct intel_crtc_state *crtc_state) 2546 { 2547 2548 return _intel_psr_min_set_context_latency(crtc_state, 2549 crtc_state->has_panel_replay, 2550 crtc_state->has_sel_update); 2551 } 2552 2553 static u32 man_trk_ctl_enable_bit_get(struct intel_display *display) 2554 { 2555 return display->platform.alderlake_p || DISPLAY_VER(display) >= 14 ? 0 : 2556 PSR2_MAN_TRK_CTL_ENABLE; 2557 } 2558 2559 static u32 man_trk_ctl_single_full_frame_bit_get(struct intel_display *display) 2560 { 2561 return display->platform.alderlake_p || DISPLAY_VER(display) >= 14 ? 2562 ADLP_PSR2_MAN_TRK_CTL_SF_SINGLE_FULL_FRAME : 2563 PSR2_MAN_TRK_CTL_SF_SINGLE_FULL_FRAME; 2564 } 2565 2566 static u32 man_trk_ctl_partial_frame_bit_get(struct intel_display *display) 2567 { 2568 return display->platform.alderlake_p || DISPLAY_VER(display) >= 14 ? 2569 ADLP_PSR2_MAN_TRK_CTL_SF_PARTIAL_FRAME_UPDATE : 2570 PSR2_MAN_TRK_CTL_SF_PARTIAL_FRAME_UPDATE; 2571 } 2572 2573 static u32 man_trk_ctl_continuos_full_frame(struct intel_display *display) 2574 { 2575 return display->platform.alderlake_p || DISPLAY_VER(display) >= 14 ? 2576 ADLP_PSR2_MAN_TRK_CTL_SF_CONTINUOS_FULL_FRAME : 2577 PSR2_MAN_TRK_CTL_SF_CONTINUOS_FULL_FRAME; 2578 } 2579 2580 static void intel_psr_force_update(struct intel_dp *intel_dp) 2581 { 2582 struct intel_display *display = to_intel_display(intel_dp); 2583 2584 /* 2585 * Display WA #0884: skl+ 2586 * This documented WA for bxt can be safely applied 2587 * broadly so we can force HW tracking to exit PSR 2588 * instead of disabling and re-enabling. 2589 * Workaround tells us to write 0 to CUR_SURFLIVE_A, 2590 * but it makes more sense write to the current active 2591 * pipe. 2592 * 2593 * This workaround do not exist for platforms with display 10 or newer 2594 * but testing proved that it works for up display 13, for newer 2595 * than that testing will be needed. 2596 */ 2597 intel_de_write(display, CURSURFLIVE(display, intel_dp->psr.pipe), 0); 2598 } 2599 2600 void intel_psr2_program_trans_man_trk_ctl(struct intel_dsb *dsb, 2601 const struct intel_crtc_state *crtc_state) 2602 { 2603 struct intel_display *display = to_intel_display(crtc_state); 2604 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2605 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 2606 struct intel_encoder *encoder; 2607 2608 if (!crtc_state->enable_psr2_sel_fetch) 2609 return; 2610 2611 for_each_intel_encoder_mask_with_psr(display->drm, encoder, 2612 crtc_state->uapi.encoder_mask) { 2613 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2614 2615 if (!dsb) 2616 lockdep_assert_held(&intel_dp->psr.lock); 2617 2618 if (DISPLAY_VER(display) < 20 && intel_dp->psr.psr2_sel_fetch_cff_enabled) 2619 return; 2620 break; 2621 } 2622 2623 intel_de_write_dsb(display, dsb, 2624 PSR2_MAN_TRK_CTL(display, cpu_transcoder), 2625 crtc_state->psr2_man_track_ctl); 2626 2627 if (!crtc_state->enable_psr2_su_region_et) 2628 return; 2629 2630 intel_de_write_dsb(display, dsb, PIPE_SRCSZ_ERLY_TPT(crtc->pipe), 2631 crtc_state->pipe_srcsz_early_tpt); 2632 2633 if (!crtc_state->dsc.compression_enable) 2634 return; 2635 2636 intel_dsc_su_et_parameters_configure(dsb, encoder, crtc_state, 2637 drm_rect_height(&crtc_state->psr2_su_area)); 2638 } 2639 2640 static void psr2_man_trk_ctl_calc(struct intel_crtc_state *crtc_state, 2641 bool full_update) 2642 { 2643 struct intel_display *display = to_intel_display(crtc_state); 2644 u32 val = man_trk_ctl_enable_bit_get(display); 2645 2646 /* SF partial frame enable has to be set even on full update */ 2647 val |= man_trk_ctl_partial_frame_bit_get(display); 2648 2649 if (full_update) { 2650 val |= man_trk_ctl_continuos_full_frame(display); 2651 goto exit; 2652 } 2653 2654 if (crtc_state->psr2_su_area.y1 == -1) 2655 goto exit; 2656 2657 if (display->platform.alderlake_p || DISPLAY_VER(display) >= 14) { 2658 val |= ADLP_PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR(crtc_state->psr2_su_area.y1); 2659 val |= ADLP_PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR(crtc_state->psr2_su_area.y2 - 1); 2660 } else { 2661 drm_WARN_ON(crtc_state->uapi.crtc->dev, 2662 crtc_state->psr2_su_area.y1 % 4 || 2663 crtc_state->psr2_su_area.y2 % 4); 2664 2665 val |= PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR( 2666 crtc_state->psr2_su_area.y1 / 4 + 1); 2667 val |= PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR( 2668 crtc_state->psr2_su_area.y2 / 4 + 1); 2669 } 2670 exit: 2671 crtc_state->psr2_man_track_ctl = val; 2672 } 2673 2674 static u32 psr2_pipe_srcsz_early_tpt_calc(struct intel_crtc_state *crtc_state, 2675 bool full_update) 2676 { 2677 int width, height; 2678 2679 if (!crtc_state->enable_psr2_su_region_et || full_update) 2680 return 0; 2681 2682 width = drm_rect_width(&crtc_state->psr2_su_area); 2683 height = drm_rect_height(&crtc_state->psr2_su_area); 2684 2685 return PIPESRC_WIDTH(width - 1) | PIPESRC_HEIGHT(height - 1); 2686 } 2687 2688 static void clip_area_update(struct drm_rect *overlap_damage_area, 2689 struct drm_rect *damage_area, 2690 struct drm_rect *display_area) 2691 { 2692 if (!drm_rect_intersect(damage_area, display_area)) 2693 return; 2694 2695 if (overlap_damage_area->y1 == -1) { 2696 overlap_damage_area->y1 = damage_area->y1; 2697 overlap_damage_area->y2 = damage_area->y2; 2698 return; 2699 } 2700 2701 if (damage_area->y1 < overlap_damage_area->y1) 2702 overlap_damage_area->y1 = damage_area->y1; 2703 2704 if (damage_area->y2 > overlap_damage_area->y2) 2705 overlap_damage_area->y2 = damage_area->y2; 2706 } 2707 2708 static bool intel_psr2_sel_fetch_pipe_alignment(struct intel_crtc_state *crtc_state) 2709 { 2710 struct intel_display *display = to_intel_display(crtc_state); 2711 const struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config; 2712 u16 y_alignment; 2713 bool su_area_changed = false; 2714 2715 /* ADLP aligns the SU region to vdsc slice height in case dsc is enabled */ 2716 if (crtc_state->dsc.compression_enable && 2717 (display->platform.alderlake_p || DISPLAY_VER(display) >= 14)) 2718 y_alignment = vdsc_cfg->slice_height; 2719 else 2720 y_alignment = crtc_state->su_y_granularity; 2721 2722 if (crtc_state->psr2_su_area.y1 % y_alignment) { 2723 crtc_state->psr2_su_area.y1 -= crtc_state->psr2_su_area.y1 % y_alignment; 2724 su_area_changed = true; 2725 } 2726 2727 if (crtc_state->psr2_su_area.y2 % y_alignment) { 2728 crtc_state->psr2_su_area.y2 = ((crtc_state->psr2_su_area.y2 / 2729 y_alignment) + 1) * y_alignment; 2730 su_area_changed = true; 2731 } 2732 2733 return su_area_changed; 2734 } 2735 2736 /* 2737 * When early transport is in use we need to extend SU area to cover 2738 * cursor fully when cursor is in SU area. 2739 */ 2740 static void 2741 intel_psr2_sel_fetch_et_alignment(struct intel_atomic_state *state, 2742 struct intel_crtc *crtc, 2743 struct drm_rect *display_area, 2744 bool *cursor_in_su_area) 2745 { 2746 struct intel_crtc_state *crtc_state = intel_atomic_get_new_crtc_state(state, crtc); 2747 struct intel_plane_state *new_plane_state; 2748 struct intel_plane *plane; 2749 int i; 2750 2751 if (!crtc_state->enable_psr2_su_region_et) 2752 return; 2753 2754 for_each_new_intel_plane_in_state(state, plane, new_plane_state, i) { 2755 struct drm_rect inter; 2756 2757 if (new_plane_state->hw.crtc != crtc_state->uapi.crtc) 2758 continue; 2759 2760 if (plane->id != PLANE_CURSOR) 2761 continue; 2762 2763 if (!new_plane_state->uapi.visible) 2764 continue; 2765 2766 inter = crtc_state->psr2_su_area; 2767 if (!drm_rect_intersect(&inter, &new_plane_state->uapi.dst)) 2768 continue; 2769 2770 clip_area_update(&crtc_state->psr2_su_area, &new_plane_state->uapi.dst, 2771 display_area); 2772 *cursor_in_su_area = true; 2773 } 2774 } 2775 2776 /* 2777 * TODO: Not clear how to handle planes with negative position, 2778 * also planes are not updated if they have a negative X 2779 * position so for now doing a full update in this cases 2780 * 2781 * Plane scaling and rotation is not supported by selective fetch and both 2782 * properties can change without a modeset, so need to be check at every 2783 * atomic commit. 2784 */ 2785 static bool psr2_sel_fetch_plane_state_supported(const struct intel_plane_state *plane_state) 2786 { 2787 if (plane_state->uapi.dst.y1 < 0 || 2788 plane_state->uapi.dst.x1 < 0 || 2789 plane_state->scaler_id >= 0 || 2790 plane_state->hw.rotation != DRM_MODE_ROTATE_0) 2791 return false; 2792 2793 return true; 2794 } 2795 2796 /* 2797 * Check for pipe properties that is not supported by selective fetch. 2798 * 2799 * TODO: pipe scaling causes a modeset but skl_update_scaler_crtc() is executed 2800 * after intel_psr_compute_config(), so for now keeping PSR2 selective fetch 2801 * enabled and going to the full update path. 2802 */ 2803 static bool psr2_sel_fetch_pipe_state_supported(const struct intel_crtc_state *crtc_state) 2804 { 2805 if (crtc_state->scaler_state.scaler_id >= 0 || 2806 crtc_state->async_flip_planes) 2807 return false; 2808 2809 return true; 2810 } 2811 2812 /* Wa 14019834836 */ 2813 static void intel_psr_apply_pr_link_on_su_wa(struct intel_crtc_state *crtc_state) 2814 { 2815 struct intel_display *display = to_intel_display(crtc_state); 2816 struct intel_encoder *encoder; 2817 int hactive_limit; 2818 2819 if (crtc_state->psr2_su_area.y1 != 0 || 2820 crtc_state->psr2_su_area.y2 != 0) 2821 return; 2822 2823 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) 2824 hactive_limit = intel_dp_is_uhbr(crtc_state) ? 1230 : 546; 2825 else 2826 hactive_limit = intel_dp_is_uhbr(crtc_state) ? 615 : 273; 2827 2828 if (crtc_state->hw.adjusted_mode.hdisplay < hactive_limit) 2829 return; 2830 2831 for_each_intel_encoder_mask_with_psr(display->drm, encoder, 2832 crtc_state->uapi.encoder_mask) { 2833 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2834 2835 if (!intel_dp_is_edp(intel_dp) && 2836 intel_dp->psr.panel_replay_enabled && 2837 intel_dp->psr.sel_update_enabled) { 2838 crtc_state->psr2_su_area.y2++; 2839 return; 2840 } 2841 } 2842 } 2843 2844 static void 2845 intel_psr_apply_su_area_workarounds(struct intel_crtc_state *crtc_state) 2846 { 2847 struct intel_display *display = to_intel_display(crtc_state); 2848 2849 /* Wa_14014971492 */ 2850 if (!crtc_state->has_panel_replay && 2851 ((IS_DISPLAY_VERx100_STEP(display, 1400, STEP_A0, STEP_B0) || 2852 display->platform.alderlake_p || display->platform.tigerlake)) && 2853 crtc_state->splitter.enable) 2854 crtc_state->psr2_su_area.y1 = 0; 2855 2856 if (intel_display_wa(display, INTEL_DISPLAY_WA_16029024088) && 2857 crtc_state->req_psr2_sdp_prior_scanline && 2858 !crtc_state->enable_psr2_su_region_et) 2859 crtc_state->psr2_su_area.y1 = 0; 2860 2861 /* Wa 14019834836 */ 2862 if (DISPLAY_VER(display) == 30) 2863 intel_psr_apply_pr_link_on_su_wa(crtc_state); 2864 } 2865 2866 int intel_psr2_sel_fetch_update(struct intel_atomic_state *state, 2867 struct intel_crtc *crtc) 2868 { 2869 struct intel_display *display = to_intel_display(state); 2870 struct intel_crtc_state *crtc_state = intel_atomic_get_new_crtc_state(state, crtc); 2871 struct intel_plane_state *new_plane_state, *old_plane_state; 2872 struct intel_plane *plane; 2873 struct drm_rect display_area = { 2874 .x1 = 0, 2875 .y1 = 0, 2876 .x2 = crtc_state->hw.adjusted_mode.crtc_hdisplay, 2877 .y2 = crtc_state->hw.adjusted_mode.crtc_vdisplay, 2878 }; 2879 bool full_update = false, su_area_changed; 2880 int i, ret; 2881 2882 if (!crtc_state->enable_psr2_sel_fetch) 2883 return 0; 2884 2885 if (!psr2_sel_fetch_pipe_state_supported(crtc_state)) { 2886 full_update = true; 2887 goto skip_sel_fetch_set_loop; 2888 } 2889 2890 crtc_state->psr2_su_area.x1 = 0; 2891 crtc_state->psr2_su_area.y1 = -1; 2892 crtc_state->psr2_su_area.x2 = drm_rect_width(&display_area); 2893 crtc_state->psr2_su_area.y2 = -1; 2894 2895 /* 2896 * Calculate minimal selective fetch area of each plane and calculate 2897 * the pipe damaged area. 2898 * In the next loop the plane selective fetch area will actually be set 2899 * using whole pipe damaged area. 2900 */ 2901 for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state, 2902 new_plane_state, i) { 2903 struct drm_rect src, damaged_area = { .x1 = 0, .y1 = -1, 2904 .x2 = INT_MAX }; 2905 2906 if (new_plane_state->hw.crtc != crtc_state->uapi.crtc) 2907 continue; 2908 2909 if (!new_plane_state->uapi.visible && 2910 !old_plane_state->uapi.visible) 2911 continue; 2912 2913 if (!psr2_sel_fetch_plane_state_supported(new_plane_state)) { 2914 full_update = true; 2915 break; 2916 } 2917 2918 /* 2919 * If visibility or plane moved, mark the whole plane area as 2920 * damaged as it needs to be complete redraw in the new and old 2921 * position. 2922 */ 2923 if (new_plane_state->uapi.visible != old_plane_state->uapi.visible || 2924 !drm_rect_equals(&new_plane_state->uapi.dst, 2925 &old_plane_state->uapi.dst)) { 2926 if (old_plane_state->uapi.visible) { 2927 damaged_area.y1 = old_plane_state->uapi.dst.y1; 2928 damaged_area.y2 = old_plane_state->uapi.dst.y2; 2929 clip_area_update(&crtc_state->psr2_su_area, &damaged_area, 2930 &display_area); 2931 } 2932 2933 if (new_plane_state->uapi.visible) { 2934 damaged_area.y1 = new_plane_state->uapi.dst.y1; 2935 damaged_area.y2 = new_plane_state->uapi.dst.y2; 2936 clip_area_update(&crtc_state->psr2_su_area, &damaged_area, 2937 &display_area); 2938 } 2939 continue; 2940 } else if (new_plane_state->uapi.alpha != old_plane_state->uapi.alpha) { 2941 /* If alpha changed mark the whole plane area as damaged */ 2942 damaged_area.y1 = new_plane_state->uapi.dst.y1; 2943 damaged_area.y2 = new_plane_state->uapi.dst.y2; 2944 clip_area_update(&crtc_state->psr2_su_area, &damaged_area, 2945 &display_area); 2946 continue; 2947 } 2948 2949 src = drm_plane_state_src(&new_plane_state->uapi); 2950 drm_rect_fp_to_int(&src, &src); 2951 2952 if (!drm_atomic_helper_damage_merged(&old_plane_state->uapi, 2953 &new_plane_state->uapi, &damaged_area)) 2954 continue; 2955 2956 damaged_area.y1 += new_plane_state->uapi.dst.y1 - src.y1; 2957 damaged_area.y2 += new_plane_state->uapi.dst.y1 - src.y1; 2958 damaged_area.x1 += new_plane_state->uapi.dst.x1 - src.x1; 2959 damaged_area.x2 += new_plane_state->uapi.dst.x1 - src.x1; 2960 2961 clip_area_update(&crtc_state->psr2_su_area, &damaged_area, &display_area); 2962 } 2963 2964 /* 2965 * TODO: For now we are just using full update in case 2966 * selective fetch area calculation fails. To optimize this we 2967 * should identify cases where this happens and fix the area 2968 * calculation for those. 2969 */ 2970 if (crtc_state->psr2_su_area.y1 == -1) { 2971 drm_info_once(display->drm, 2972 "Selective fetch area calculation failed in pipe %c\n", 2973 pipe_name(crtc->pipe)); 2974 full_update = true; 2975 } 2976 2977 if (full_update) 2978 goto skip_sel_fetch_set_loop; 2979 2980 intel_psr_apply_su_area_workarounds(crtc_state); 2981 2982 ret = drm_atomic_add_affected_planes(&state->base, &crtc->base); 2983 if (ret) 2984 return ret; 2985 2986 do { 2987 bool cursor_in_su_area = false; 2988 2989 /* 2990 * Adjust su area to cover cursor fully as necessary 2991 * (early transport). This needs to be done after 2992 * drm_atomic_add_affected_planes to ensure visible 2993 * cursor is added into affected planes even when 2994 * cursor is not updated by itself. 2995 */ 2996 intel_psr2_sel_fetch_et_alignment(state, crtc, &display_area, 2997 &cursor_in_su_area); 2998 2999 su_area_changed = intel_psr2_sel_fetch_pipe_alignment(crtc_state); 3000 3001 /* 3002 * If the cursor was outside the SU area before 3003 * alignment, the alignment step (which only expands 3004 * SU) may pull the cursor partially inside, so we 3005 * must run ET alignment again to fully cover it. But 3006 * if the cursor was already fully inside before 3007 * alignment, expanding the SU area won't change that, 3008 * so no further work is needed. 3009 */ 3010 if (cursor_in_su_area) 3011 break; 3012 } while (su_area_changed); 3013 3014 /* 3015 * Now that we have the pipe damaged area check if it intersect with 3016 * every plane, if it does set the plane selective fetch area. 3017 */ 3018 for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state, 3019 new_plane_state, i) { 3020 struct drm_rect *sel_fetch_area, inter; 3021 struct intel_plane *linked = new_plane_state->planar_linked_plane; 3022 3023 if (new_plane_state->hw.crtc != crtc_state->uapi.crtc || 3024 !new_plane_state->uapi.visible) 3025 continue; 3026 3027 inter = crtc_state->psr2_su_area; 3028 sel_fetch_area = &new_plane_state->psr2_sel_fetch_area; 3029 if (!drm_rect_intersect(&inter, &new_plane_state->uapi.dst)) { 3030 sel_fetch_area->y1 = -1; 3031 sel_fetch_area->y2 = -1; 3032 /* 3033 * if plane sel fetch was previously enabled -> 3034 * disable it 3035 */ 3036 if (drm_rect_height(&old_plane_state->psr2_sel_fetch_area) > 0) 3037 crtc_state->update_planes |= BIT(plane->id); 3038 3039 continue; 3040 } 3041 3042 if (!psr2_sel_fetch_plane_state_supported(new_plane_state)) { 3043 full_update = true; 3044 break; 3045 } 3046 3047 sel_fetch_area = &new_plane_state->psr2_sel_fetch_area; 3048 sel_fetch_area->y1 = inter.y1 - new_plane_state->uapi.dst.y1; 3049 sel_fetch_area->y2 = inter.y2 - new_plane_state->uapi.dst.y1; 3050 crtc_state->update_planes |= BIT(plane->id); 3051 3052 /* 3053 * Sel_fetch_area is calculated for UV plane. Use 3054 * same area for Y plane as well. 3055 */ 3056 if (linked) { 3057 struct intel_plane_state *linked_new_plane_state; 3058 struct drm_rect *linked_sel_fetch_area; 3059 3060 linked_new_plane_state = intel_atomic_get_plane_state(state, linked); 3061 if (IS_ERR(linked_new_plane_state)) 3062 return PTR_ERR(linked_new_plane_state); 3063 3064 linked_sel_fetch_area = &linked_new_plane_state->psr2_sel_fetch_area; 3065 linked_sel_fetch_area->y1 = sel_fetch_area->y1; 3066 linked_sel_fetch_area->y2 = sel_fetch_area->y2; 3067 crtc_state->update_planes |= BIT(linked->id); 3068 } 3069 } 3070 3071 skip_sel_fetch_set_loop: 3072 if (full_update) 3073 clip_area_update(&crtc_state->psr2_su_area, &display_area, 3074 &display_area); 3075 3076 psr2_man_trk_ctl_calc(crtc_state, full_update); 3077 crtc_state->pipe_srcsz_early_tpt = 3078 psr2_pipe_srcsz_early_tpt_calc(crtc_state, full_update); 3079 return 0; 3080 } 3081 3082 void intel_psr2_panic_force_full_update(const struct intel_crtc_state *crtc_state) 3083 { 3084 struct intel_display *display = to_intel_display(crtc_state); 3085 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 3086 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 3087 u32 val = man_trk_ctl_enable_bit_get(display); 3088 3089 /* SF partial frame enable has to be set even on full update */ 3090 val |= man_trk_ctl_partial_frame_bit_get(display); 3091 val |= man_trk_ctl_continuos_full_frame(display); 3092 3093 /* Directly write the register */ 3094 intel_de_write_fw(display, PSR2_MAN_TRK_CTL(display, cpu_transcoder), val); 3095 3096 if (!crtc_state->enable_psr2_su_region_et) 3097 return; 3098 3099 intel_de_write_fw(display, PIPE_SRCSZ_ERLY_TPT(crtc->pipe), 0); 3100 } 3101 3102 void intel_psr_pre_plane_update(struct intel_atomic_state *state, 3103 struct intel_crtc *crtc) 3104 { 3105 struct intel_display *display = to_intel_display(state); 3106 const struct intel_crtc_state *old_crtc_state = 3107 intel_atomic_get_old_crtc_state(state, crtc); 3108 const struct intel_crtc_state *new_crtc_state = 3109 intel_atomic_get_new_crtc_state(state, crtc); 3110 struct intel_encoder *encoder; 3111 3112 if (!HAS_PSR(display)) 3113 return; 3114 3115 for_each_intel_encoder_mask_with_psr(state->base.dev, encoder, 3116 old_crtc_state->uapi.encoder_mask) { 3117 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 3118 struct intel_psr *psr = &intel_dp->psr; 3119 3120 mutex_lock(&psr->lock); 3121 3122 if (!new_crtc_state->has_psr) 3123 psr->no_psr_reason = new_crtc_state->no_psr_reason; 3124 3125 if (psr->enabled) { 3126 /* 3127 * Reasons to disable: 3128 * - PSR disabled in new state 3129 * - All planes will go inactive 3130 * - Changing between PSR versions 3131 * - Region Early Transport changing 3132 * - Display WA #1136: skl, bxt 3133 */ 3134 if (intel_crtc_needs_modeset(new_crtc_state) || 3135 new_crtc_state->update_m_n || 3136 new_crtc_state->update_lrr || 3137 !new_crtc_state->has_psr || 3138 !new_crtc_state->active_planes || 3139 new_crtc_state->has_sel_update != psr->sel_update_enabled || 3140 new_crtc_state->enable_psr2_su_region_et != psr->su_region_et_enabled || 3141 new_crtc_state->has_panel_replay != psr->panel_replay_enabled || 3142 (DISPLAY_VER(display) < 11 && new_crtc_state->wm_level_disabled)) 3143 intel_psr_disable_locked(intel_dp); 3144 else if (new_crtc_state->wm_level_disabled) 3145 /* Wa_14015648006 */ 3146 wm_optimization_wa(intel_dp, new_crtc_state); 3147 } 3148 3149 mutex_unlock(&psr->lock); 3150 } 3151 } 3152 3153 static void 3154 verify_panel_replay_dsc_state(const struct intel_crtc_state *crtc_state) 3155 { 3156 struct intel_display *display = to_intel_display(crtc_state); 3157 3158 if (!crtc_state->has_panel_replay) 3159 return; 3160 3161 drm_WARN_ON(display->drm, 3162 intel_dsc_enabled_on_link(crtc_state) && 3163 crtc_state->panel_replay_dsc_support == 3164 INTEL_DP_PANEL_REPLAY_DSC_NOT_SUPPORTED); 3165 } 3166 3167 void intel_psr_post_plane_update(struct intel_atomic_state *state, 3168 struct intel_crtc *crtc) 3169 { 3170 struct intel_display *display = to_intel_display(state); 3171 const struct intel_crtc_state *crtc_state = 3172 intel_atomic_get_new_crtc_state(state, crtc); 3173 struct intel_encoder *encoder; 3174 bool dc3co_allowed; 3175 3176 if (!crtc_state->has_psr) 3177 return; 3178 3179 dc3co_allowed = intel_display_power_dc3co_allowed(display); 3180 3181 verify_panel_replay_dsc_state(crtc_state); 3182 3183 for_each_intel_encoder_mask_with_psr(state->base.dev, encoder, 3184 crtc_state->uapi.encoder_mask) { 3185 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 3186 struct intel_psr *psr = &intel_dp->psr; 3187 bool keep_disabled = false; 3188 3189 mutex_lock(&psr->lock); 3190 3191 drm_WARN_ON(display->drm, 3192 psr->enabled && !crtc_state->active_planes); 3193 3194 if (psr->sink_not_reliable) 3195 keep_disabled = true; 3196 3197 if (!crtc_state->active_planes) { 3198 psr->no_psr_reason = "All planes inactive"; 3199 keep_disabled = true; 3200 } 3201 3202 /* Display WA #1136: skl, bxt */ 3203 if (DISPLAY_VER(display) < 11 && crtc_state->wm_level_disabled) { 3204 psr->no_psr_reason = "Workaround #1136 for skl, bxt"; 3205 keep_disabled = true; 3206 } 3207 3208 intel_dp->psr.dc3co_allowed = dc3co_allowed; 3209 3210 if (!psr->enabled && !keep_disabled) 3211 intel_psr_enable_locked(intel_dp, crtc_state); 3212 else if (psr->enabled && !crtc_state->wm_level_disabled) 3213 /* Wa_14015648006 */ 3214 wm_optimization_wa(intel_dp, crtc_state); 3215 3216 /* Force a PSR exit when enabling CRC to avoid CRC timeouts */ 3217 if (crtc_state->crc_enabled && psr->enabled) 3218 intel_psr_force_update(intel_dp); 3219 3220 /* 3221 * Clear possible busy bits in case we have 3222 * invalidate -> flip -> flush sequence. 3223 */ 3224 intel_dp->psr.busy_frontbuffer_bits = 0; 3225 3226 if (intel_dp->psr.dc3co_allowed) { 3227 mod_delayed_work(display->wq.unordered, &intel_dp->psr.dc3co_work, 3228 intel_dp->psr.dc3co_exit_delay); 3229 } 3230 3231 mutex_unlock(&psr->lock); 3232 } 3233 } 3234 3235 /* 3236 * From bspec: Panel Self Refresh (BDW+) 3237 * Max. time for PSR to idle = Inverse of the refresh rate + 6 ms of 3238 * exit training time + 1.5 ms of aux channel handshake. 50 ms is 3239 * defensive enough to cover everything. 3240 */ 3241 #define PSR_IDLE_TIMEOUT_MS 50 3242 3243 static int 3244 _psr2_ready_for_pipe_update_locked(const struct intel_crtc_state *new_crtc_state, 3245 struct intel_dsb *dsb) 3246 { 3247 struct intel_display *display = to_intel_display(new_crtc_state); 3248 enum transcoder cpu_transcoder = new_crtc_state->cpu_transcoder; 3249 3250 /* 3251 * Any state lower than EDP_PSR2_STATUS_STATE_DEEP_SLEEP is enough. 3252 * As all higher states has bit 4 of PSR2 state set we can just wait for 3253 * EDP_PSR2_STATUS_STATE_DEEP_SLEEP to be cleared. 3254 */ 3255 if (dsb) { 3256 intel_dsb_poll(dsb, EDP_PSR2_STATUS(display, cpu_transcoder), 3257 EDP_PSR2_STATUS_STATE_DEEP_SLEEP, 0, 200, 3258 PSR_IDLE_TIMEOUT_MS * 1000 / 200); 3259 return true; 3260 } 3261 3262 return intel_de_wait_for_clear_ms(display, 3263 EDP_PSR2_STATUS(display, cpu_transcoder), 3264 EDP_PSR2_STATUS_STATE_DEEP_SLEEP, 3265 PSR_IDLE_TIMEOUT_MS); 3266 } 3267 3268 static int 3269 _psr1_ready_for_pipe_update_locked(const struct intel_crtc_state *new_crtc_state, 3270 struct intel_dsb *dsb) 3271 { 3272 struct intel_display *display = to_intel_display(new_crtc_state); 3273 enum transcoder cpu_transcoder = new_crtc_state->cpu_transcoder; 3274 3275 if (dsb) { 3276 intel_dsb_poll(dsb, psr_status_reg(display, cpu_transcoder), 3277 EDP_PSR_STATUS_STATE_MASK, 0, 200, 3278 PSR_IDLE_TIMEOUT_MS * 1000 / 200); 3279 return true; 3280 } 3281 3282 return intel_de_wait_for_clear_ms(display, 3283 psr_status_reg(display, cpu_transcoder), 3284 EDP_PSR_STATUS_STATE_MASK, 3285 PSR_IDLE_TIMEOUT_MS); 3286 } 3287 3288 /** 3289 * intel_psr_wait_for_idle_locked - wait for PSR be ready for a pipe update 3290 * @new_crtc_state: new CRTC state 3291 * 3292 * This function is expected to be called from pipe_update_start() where it is 3293 * not expected to race with PSR enable or disable. 3294 */ 3295 void intel_psr_wait_for_idle_locked(const struct intel_crtc_state *new_crtc_state) 3296 { 3297 struct intel_display *display = to_intel_display(new_crtc_state); 3298 struct intel_encoder *encoder; 3299 3300 if (!new_crtc_state->has_psr) 3301 return; 3302 3303 for_each_intel_encoder_mask_with_psr(display->drm, encoder, 3304 new_crtc_state->uapi.encoder_mask) { 3305 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 3306 int ret; 3307 3308 lockdep_assert_held(&intel_dp->psr.lock); 3309 3310 if (!intel_dp->psr.enabled || intel_dp->psr.panel_replay_enabled) 3311 continue; 3312 3313 if (intel_dp->psr.sel_update_enabled) 3314 ret = _psr2_ready_for_pipe_update_locked(new_crtc_state, 3315 NULL); 3316 else 3317 ret = _psr1_ready_for_pipe_update_locked(new_crtc_state, 3318 NULL); 3319 3320 if (ret) 3321 drm_err(display->drm, 3322 "PSR wait timed out, atomic update may fail\n"); 3323 } 3324 } 3325 3326 void intel_psr_wait_for_idle_dsb(struct intel_dsb *dsb, 3327 const struct intel_crtc_state *new_crtc_state) 3328 { 3329 if (!new_crtc_state->has_psr || new_crtc_state->has_panel_replay) 3330 return; 3331 3332 if (new_crtc_state->has_sel_update) 3333 _psr2_ready_for_pipe_update_locked(new_crtc_state, dsb); 3334 else 3335 _psr1_ready_for_pipe_update_locked(new_crtc_state, dsb); 3336 } 3337 3338 static bool __psr_wait_for_idle_locked(struct intel_dp *intel_dp) 3339 { 3340 struct intel_display *display = to_intel_display(intel_dp); 3341 enum transcoder cpu_transcoder = intel_dp->psr.transcoder; 3342 intel_reg_t reg; 3343 u32 mask; 3344 int err; 3345 3346 if (!intel_dp->psr.enabled) 3347 return false; 3348 3349 if (intel_dp_is_edp(intel_dp) && (intel_dp->psr.sel_update_enabled || 3350 intel_dp->psr.panel_replay_enabled)) { 3351 reg = EDP_PSR2_STATUS(display, cpu_transcoder); 3352 mask = EDP_PSR2_STATUS_STATE_MASK; 3353 } else { 3354 reg = psr_status_reg(display, cpu_transcoder); 3355 mask = EDP_PSR_STATUS_STATE_MASK; 3356 } 3357 3358 mutex_unlock(&intel_dp->psr.lock); 3359 3360 err = intel_de_wait_for_clear_ms(display, reg, mask, 50); 3361 if (err) 3362 drm_err(display->drm, 3363 "Timed out waiting for PSR Idle for re-enable\n"); 3364 3365 /* After the unlocked wait, verify that PSR is still wanted! */ 3366 mutex_lock(&intel_dp->psr.lock); 3367 return err == 0 && intel_dp->psr.enabled && !intel_dp->psr.pause_counter; 3368 } 3369 3370 static int intel_psr_fastset_force(struct intel_display *display) 3371 { 3372 struct drm_connector_list_iter conn_iter; 3373 struct drm_modeset_acquire_ctx ctx; 3374 struct drm_atomic_commit *state; 3375 struct drm_connector *conn; 3376 int err = 0; 3377 3378 state = drm_atomic_commit_alloc(display->drm); 3379 if (!state) 3380 return -ENOMEM; 3381 3382 drm_modeset_acquire_init(&ctx, DRM_MODESET_ACQUIRE_INTERRUPTIBLE); 3383 3384 state->acquire_ctx = &ctx; 3385 to_intel_atomic_state(state)->internal = true; 3386 3387 retry: 3388 drm_connector_list_iter_begin(display->drm, &conn_iter); 3389 drm_for_each_connector_iter(conn, &conn_iter) { 3390 struct drm_connector_state *conn_state; 3391 struct drm_crtc_state *crtc_state; 3392 3393 if (conn->connector_type != DRM_MODE_CONNECTOR_eDP) 3394 continue; 3395 3396 conn_state = drm_atomic_get_connector_state(state, conn); 3397 if (IS_ERR(conn_state)) { 3398 err = PTR_ERR(conn_state); 3399 break; 3400 } 3401 3402 if (!conn_state->crtc) 3403 continue; 3404 3405 crtc_state = drm_atomic_get_crtc_state(state, conn_state->crtc); 3406 if (IS_ERR(crtc_state)) { 3407 err = PTR_ERR(crtc_state); 3408 break; 3409 } 3410 3411 /* Mark mode as changed to trigger a pipe->update() */ 3412 crtc_state->mode_changed = true; 3413 } 3414 drm_connector_list_iter_end(&conn_iter); 3415 3416 if (err == 0) 3417 err = drm_atomic_commit(state); 3418 3419 if (err == -EDEADLK) { 3420 drm_atomic_commit_clear(state); 3421 err = drm_modeset_backoff(&ctx); 3422 if (!err) 3423 goto retry; 3424 } 3425 3426 drm_modeset_drop_locks(&ctx); 3427 drm_modeset_acquire_fini(&ctx); 3428 drm_atomic_commit_put(state); 3429 3430 return err; 3431 } 3432 3433 int intel_psr_debug_set(struct intel_dp *intel_dp, u64 val) 3434 { 3435 struct intel_display *display = to_intel_display(intel_dp); 3436 const u32 mode = val & I915_PSR_DEBUG_MODE_MASK; 3437 const u32 disable_bits = val & (I915_PSR_DEBUG_SU_REGION_ET_DISABLE | 3438 I915_PSR_DEBUG_PANEL_REPLAY_DISABLE); 3439 u32 old_mode, old_disable_bits; 3440 int ret; 3441 3442 if (val & ~(I915_PSR_DEBUG_IRQ | I915_PSR_DEBUG_SU_REGION_ET_DISABLE | 3443 I915_PSR_DEBUG_PANEL_REPLAY_DISABLE | 3444 I915_PSR_DEBUG_MODE_MASK) || 3445 mode > I915_PSR_DEBUG_ENABLE_SEL_FETCH) { 3446 drm_dbg_kms(display->drm, "Invalid debug mask %llx\n", val); 3447 return -EINVAL; 3448 } 3449 3450 ret = mutex_lock_interruptible(&intel_dp->psr.lock); 3451 if (ret) 3452 return ret; 3453 3454 old_mode = intel_dp->psr.debug & I915_PSR_DEBUG_MODE_MASK; 3455 old_disable_bits = intel_dp->psr.debug & 3456 (I915_PSR_DEBUG_SU_REGION_ET_DISABLE | 3457 I915_PSR_DEBUG_PANEL_REPLAY_DISABLE); 3458 3459 intel_dp->psr.debug = val; 3460 3461 /* 3462 * Do it right away if it's already enabled, otherwise it will be done 3463 * when enabling the source. 3464 */ 3465 if (intel_dp->psr.enabled) 3466 psr_irq_control(intel_dp); 3467 3468 mutex_unlock(&intel_dp->psr.lock); 3469 3470 if (old_mode != mode || old_disable_bits != disable_bits) 3471 ret = intel_psr_fastset_force(display); 3472 3473 return ret; 3474 } 3475 3476 static void intel_psr_handle_irq(struct intel_dp *intel_dp) 3477 { 3478 struct intel_psr *psr = &intel_dp->psr; 3479 3480 intel_psr_disable_locked(intel_dp); 3481 psr->sink_not_reliable = true; 3482 /* let's make sure that sink is awaken */ 3483 drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, DP_SET_POWER_D0); 3484 } 3485 3486 static void intel_psr_work(struct work_struct *work) 3487 { 3488 struct intel_dp *intel_dp = 3489 container_of(work, typeof(*intel_dp), psr.work); 3490 3491 mutex_lock(&intel_dp->psr.lock); 3492 3493 if (!intel_dp->psr.enabled) 3494 goto unlock; 3495 3496 if (READ_ONCE(intel_dp->psr.irq_aux_error)) { 3497 intel_psr_handle_irq(intel_dp); 3498 goto unlock; 3499 } 3500 3501 if (intel_dp->psr.pause_counter) 3502 goto unlock; 3503 3504 /* 3505 * We have to make sure PSR is ready for re-enable 3506 * otherwise it keeps disabled until next full enable/disable cycle. 3507 * PSR might take some time to get fully disabled 3508 * and be ready for re-enable. 3509 */ 3510 if (!__psr_wait_for_idle_locked(intel_dp)) 3511 goto unlock; 3512 3513 /* 3514 * The delayed work can race with an invalidate hence we need to 3515 * recheck. Since psr_flush first clears this and then reschedules we 3516 * won't ever miss a flush when bailing out here. 3517 */ 3518 if (intel_dp->psr.busy_frontbuffer_bits || intel_dp->psr.active) 3519 goto unlock; 3520 3521 intel_psr_activate(intel_dp); 3522 unlock: 3523 mutex_unlock(&intel_dp->psr.lock); 3524 } 3525 3526 static void intel_psr_configure_full_frame_update(struct intel_dp *intel_dp) 3527 { 3528 struct intel_display *display = to_intel_display(intel_dp); 3529 enum transcoder cpu_transcoder = intel_dp->psr.transcoder; 3530 3531 if (!intel_dp->psr.psr2_sel_fetch_enabled) 3532 return; 3533 3534 if (DISPLAY_VER(display) >= 20) 3535 intel_de_write(display, LNL_SFF_CTL(cpu_transcoder), 3536 LNL_SFF_CTL_SF_SINGLE_FULL_FRAME); 3537 else 3538 intel_de_write(display, 3539 PSR2_MAN_TRK_CTL(display, cpu_transcoder), 3540 man_trk_ctl_enable_bit_get(display) | 3541 man_trk_ctl_partial_frame_bit_get(display) | 3542 man_trk_ctl_single_full_frame_bit_get(display) | 3543 man_trk_ctl_continuos_full_frame(display)); 3544 } 3545 3546 static void _psr_invalidate_handle(struct intel_dp *intel_dp) 3547 { 3548 struct intel_display *display = to_intel_display(intel_dp); 3549 3550 if (DISPLAY_VER(display) < 20 && intel_dp->psr.psr2_sel_fetch_enabled) { 3551 if (!intel_dp->psr.psr2_sel_fetch_cff_enabled) { 3552 intel_dp->psr.psr2_sel_fetch_cff_enabled = true; 3553 intel_psr_configure_full_frame_update(intel_dp); 3554 } 3555 3556 intel_psr_force_update(intel_dp); 3557 } else { 3558 intel_psr_exit(intel_dp); 3559 } 3560 } 3561 3562 /** 3563 * intel_psr_invalidate - Invalidate PSR 3564 * @display: display device 3565 * @frontbuffer_bits: frontbuffer plane tracking bits 3566 * @origin: which operation caused the invalidate 3567 * 3568 * Since the hardware frontbuffer tracking has gaps we need to integrate 3569 * with the software frontbuffer tracking. This function gets called every 3570 * time frontbuffer rendering starts and a buffer gets dirtied. PSR must be 3571 * disabled if the frontbuffer mask contains a buffer relevant to PSR. 3572 * 3573 * Dirty frontbuffers relevant to PSR are tracked in busy_frontbuffer_bits." 3574 */ 3575 void intel_psr_invalidate(struct intel_display *display, 3576 unsigned frontbuffer_bits, enum fb_op_origin origin) 3577 { 3578 struct intel_encoder *encoder; 3579 3580 if (origin == ORIGIN_FLIP) 3581 return; 3582 3583 for_each_intel_encoder_with_psr(display->drm, encoder) { 3584 unsigned int pipe_frontbuffer_bits = frontbuffer_bits; 3585 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 3586 3587 mutex_lock(&intel_dp->psr.lock); 3588 if (!intel_dp->psr.enabled) { 3589 mutex_unlock(&intel_dp->psr.lock); 3590 continue; 3591 } 3592 3593 pipe_frontbuffer_bits &= 3594 INTEL_FRONTBUFFER_ALL_MASK(intel_dp->psr.pipe); 3595 intel_dp->psr.busy_frontbuffer_bits |= pipe_frontbuffer_bits; 3596 3597 if (pipe_frontbuffer_bits) 3598 _psr_invalidate_handle(intel_dp); 3599 3600 mutex_unlock(&intel_dp->psr.lock); 3601 } 3602 } 3603 3604 static void _psr_flush_handle(struct intel_dp *intel_dp) 3605 { 3606 struct intel_display *display = to_intel_display(intel_dp); 3607 3608 if (DISPLAY_VER(display) >= 20) { 3609 /* 3610 * We can use PSR exit on LunarLake onwards. Also 3611 * using trans push mechanism to trigger Frame Change 3612 * event requires using PSR exit. 3613 */ 3614 intel_psr_exit(intel_dp); 3615 } else if (intel_dp->psr.psr2_sel_fetch_enabled) { 3616 /* Selective fetch prior LNL */ 3617 if (intel_dp->psr.psr2_sel_fetch_cff_enabled) { 3618 /* can we turn CFF off? */ 3619 if (intel_dp->psr.busy_frontbuffer_bits == 0) 3620 intel_dp->psr.psr2_sel_fetch_cff_enabled = false; 3621 } 3622 3623 /* 3624 * Still keep cff bit enabled as we don't have proper SU 3625 * configuration in case update is sent for any reason after 3626 * sff bit gets cleared by the HW on next vblank. 3627 * 3628 * NOTE: Setting cff bit is not needed for LunarLake onwards as 3629 * we have own register for SFF bit and we are not overwriting 3630 * existing SU configuration 3631 */ 3632 intel_psr_configure_full_frame_update(intel_dp); 3633 3634 intel_psr_force_update(intel_dp); 3635 } else { 3636 /* 3637 * On older platforms using PSR exit was seen causing problems 3638 */ 3639 intel_psr_force_update(intel_dp); 3640 } 3641 3642 if (!intel_dp->psr.active && !intel_dp->psr.busy_frontbuffer_bits) 3643 queue_work(display->wq.unordered, &intel_dp->psr.work); 3644 } 3645 3646 /** 3647 * intel_psr_flush - Flush PSR 3648 * @display: display device 3649 * @frontbuffer_bits: frontbuffer plane tracking bits 3650 * @origin: which operation caused the flush 3651 * 3652 * Since the hardware frontbuffer tracking has gaps we need to integrate 3653 * with the software frontbuffer tracking. This function gets called every 3654 * time frontbuffer rendering has completed and flushed out to memory. PSR 3655 * can be enabled again if no other frontbuffer relevant to PSR is dirty. 3656 * 3657 * Dirty frontbuffers relevant to PSR are tracked in busy_frontbuffer_bits. 3658 */ 3659 void intel_psr_flush(struct intel_display *display, 3660 unsigned frontbuffer_bits, enum fb_op_origin origin) 3661 { 3662 struct intel_encoder *encoder; 3663 3664 for_each_intel_encoder_with_psr(display->drm, encoder) { 3665 unsigned int pipe_frontbuffer_bits = frontbuffer_bits; 3666 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 3667 3668 mutex_lock(&intel_dp->psr.lock); 3669 if (!intel_dp->psr.enabled) { 3670 mutex_unlock(&intel_dp->psr.lock); 3671 continue; 3672 } 3673 3674 pipe_frontbuffer_bits &= 3675 INTEL_FRONTBUFFER_ALL_MASK(intel_dp->psr.pipe); 3676 intel_dp->psr.busy_frontbuffer_bits &= ~pipe_frontbuffer_bits; 3677 3678 /* 3679 * If the PSR is paused by an explicit intel_psr_paused() call, 3680 * we have to ensure that the PSR is not activated until 3681 * intel_psr_resume() is called. 3682 */ 3683 if (intel_dp->psr.pause_counter) 3684 goto unlock; 3685 3686 if (origin == ORIGIN_FLIP || 3687 (origin == ORIGIN_CURSOR_UPDATE && 3688 !intel_dp->psr.psr2_sel_fetch_enabled)) { 3689 psr2_dc3co_flush_locked(intel_dp, frontbuffer_bits); 3690 goto unlock; 3691 } 3692 3693 if (pipe_frontbuffer_bits == 0) 3694 goto unlock; 3695 3696 /* By definition flush = invalidate + flush */ 3697 _psr_flush_handle(intel_dp); 3698 unlock: 3699 mutex_unlock(&intel_dp->psr.lock); 3700 } 3701 } 3702 3703 /** 3704 * intel_psr_init - Init basic PSR work and mutex. 3705 * @intel_dp: Intel DP 3706 * 3707 * This function is called after the initializing connector. 3708 * (the initializing of connector treats the handling of connector capabilities) 3709 * And it initializes basic PSR stuff for each DP Encoder. 3710 */ 3711 void intel_psr_init(struct intel_dp *intel_dp) 3712 { 3713 struct intel_display *display = to_intel_display(intel_dp); 3714 struct intel_connector *connector = intel_dp->attached_connector; 3715 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 3716 3717 if (!(HAS_PSR(display) || HAS_DP20(display))) 3718 return; 3719 3720 /* 3721 * HSW spec explicitly says PSR is tied to port A. 3722 * BDW+ platforms have a instance of PSR registers per transcoder but 3723 * BDW, GEN9 and GEN11 are not validated by HW team in other transcoder 3724 * than eDP one. 3725 * For now it only supports one instance of PSR for BDW, GEN9 and GEN11. 3726 * So lets keep it hardcoded to PORT_A for BDW, GEN9 and GEN11. 3727 * But GEN12 supports a instance of PSR registers per transcoder. 3728 */ 3729 if (DISPLAY_VER(display) < 12 && dig_port->base.port != PORT_A) { 3730 drm_dbg_kms(display->drm, 3731 "PSR condition failed: Port not supported\n"); 3732 return; 3733 } 3734 3735 if ((HAS_DP20(display) && !intel_dp_is_edp(intel_dp)) || 3736 DISPLAY_VER(display) >= 20) 3737 intel_dp->psr.source_panel_replay_support = true; 3738 3739 if (HAS_PSR(display) && intel_dp_is_edp(intel_dp)) 3740 intel_dp->psr.source_support = true; 3741 3742 /* Set link_standby x link_off defaults */ 3743 if (DISPLAY_VER(display) < 12) 3744 /* For new platforms up to TGL let's respect VBT back again */ 3745 intel_dp->psr.link_standby = connector->panel.vbt.psr.full_link; 3746 3747 INIT_WORK(&intel_dp->psr.work, intel_psr_work); 3748 INIT_DELAYED_WORK(&intel_dp->psr.dc3co_work, psr2_dc3co_disable_work); 3749 mutex_init(&intel_dp->psr.lock); 3750 } 3751 3752 static int psr_get_status_and_error_status(struct intel_dp *intel_dp, 3753 u8 *status, u8 *error_status) 3754 { 3755 struct drm_dp_aux *aux = &intel_dp->aux; 3756 int ret; 3757 unsigned int offset; 3758 3759 offset = intel_dp->psr.panel_replay_enabled ? 3760 DP_SINK_DEVICE_PR_AND_FRAME_LOCK_STATUS : DP_PSR_STATUS; 3761 3762 ret = drm_dp_dpcd_readb(aux, offset, status); 3763 if (ret != 1) 3764 return ret; 3765 3766 offset = intel_dp->psr.panel_replay_enabled ? 3767 DP_PANEL_REPLAY_ERROR_STATUS : DP_PSR_ERROR_STATUS; 3768 3769 ret = drm_dp_dpcd_readb(aux, offset, error_status); 3770 if (ret != 1) 3771 return ret; 3772 3773 *status = *status & DP_PSR_SINK_STATE_MASK; 3774 3775 return 0; 3776 } 3777 3778 static void psr_alpm_check(struct intel_dp *intel_dp) 3779 { 3780 struct intel_psr *psr = &intel_dp->psr; 3781 3782 if (!psr->sel_update_enabled) 3783 return; 3784 3785 if (intel_alpm_get_error(intel_dp)) { 3786 intel_psr_disable_locked(intel_dp); 3787 psr->sink_not_reliable = true; 3788 } 3789 } 3790 3791 static void psr_capability_changed_check(struct intel_dp *intel_dp) 3792 { 3793 struct intel_display *display = to_intel_display(intel_dp); 3794 struct intel_psr *psr = &intel_dp->psr; 3795 u8 val; 3796 int r; 3797 3798 r = drm_dp_dpcd_readb(&intel_dp->aux, DP_PSR_ESI, &val); 3799 if (r != 1) { 3800 drm_err(display->drm, "Error reading DP_PSR_ESI\n"); 3801 return; 3802 } 3803 3804 if (val & DP_PSR_CAPS_CHANGE) { 3805 intel_psr_disable_locked(intel_dp); 3806 psr->sink_not_reliable = true; 3807 drm_dbg_kms(display->drm, 3808 "Sink PSR capability changed, disabling PSR\n"); 3809 3810 /* Clearing it */ 3811 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_ESI, val); 3812 } 3813 } 3814 3815 /* 3816 * On common bits: 3817 * DP_PSR_RFB_STORAGE_ERROR == DP_PANEL_REPLAY_RFB_STORAGE_ERROR 3818 * DP_PSR_VSC_SDP_UNCORRECTABLE_ERROR == DP_PANEL_REPLAY_VSC_SDP_UNCORRECTABLE_ERROR 3819 * DP_PSR_LINK_CRC_ERROR == DP_PANEL_REPLAY_LINK_CRC_ERROR 3820 * this function is relying on PSR definitions 3821 */ 3822 void intel_psr_short_pulse(struct intel_dp *intel_dp) 3823 { 3824 struct intel_display *display = to_intel_display(intel_dp); 3825 struct intel_psr *psr = &intel_dp->psr; 3826 u8 status, error_status; 3827 const u8 errors = DP_PSR_RFB_STORAGE_ERROR | 3828 DP_PSR_VSC_SDP_UNCORRECTABLE_ERROR | 3829 DP_PSR_LINK_CRC_ERROR; 3830 3831 if (!CAN_PSR(intel_dp) && !CAN_PANEL_REPLAY(intel_dp)) 3832 return; 3833 3834 mutex_lock(&psr->lock); 3835 3836 psr->link_ok = false; 3837 3838 if (!psr->enabled) 3839 goto exit; 3840 3841 if (psr_get_status_and_error_status(intel_dp, &status, &error_status)) { 3842 drm_err(display->drm, 3843 "Error reading PSR status or error status\n"); 3844 goto exit; 3845 } 3846 3847 if ((!psr->panel_replay_enabled && status == DP_PSR_SINK_INTERNAL_ERROR) || 3848 (error_status & errors)) { 3849 intel_psr_disable_locked(intel_dp); 3850 psr->sink_not_reliable = true; 3851 } 3852 3853 if (!psr->panel_replay_enabled && status == DP_PSR_SINK_INTERNAL_ERROR && 3854 !error_status) 3855 drm_dbg_kms(display->drm, 3856 "PSR sink internal error, disabling PSR\n"); 3857 if (error_status & DP_PSR_RFB_STORAGE_ERROR) 3858 drm_dbg_kms(display->drm, 3859 "PSR RFB storage error, disabling PSR\n"); 3860 if (error_status & DP_PSR_VSC_SDP_UNCORRECTABLE_ERROR) 3861 drm_dbg_kms(display->drm, 3862 "PSR VSC SDP uncorrectable error, disabling PSR\n"); 3863 if (error_status & DP_PSR_LINK_CRC_ERROR) 3864 drm_dbg_kms(display->drm, 3865 "PSR Link CRC error, disabling PSR\n"); 3866 3867 if (error_status & ~errors) 3868 drm_err(display->drm, 3869 "PSR_ERROR_STATUS unhandled errors %x\n", 3870 error_status & ~errors); 3871 /* clear status register */ 3872 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_ERROR_STATUS, error_status); 3873 3874 if (!psr->panel_replay_enabled) { 3875 psr_alpm_check(intel_dp); 3876 psr_capability_changed_check(intel_dp); 3877 } 3878 3879 exit: 3880 mutex_unlock(&psr->lock); 3881 } 3882 3883 bool intel_psr_enabled(struct intel_dp *intel_dp) 3884 { 3885 bool ret; 3886 3887 if (!CAN_PSR(intel_dp)) 3888 return false; 3889 3890 mutex_lock(&intel_dp->psr.lock); 3891 ret = intel_dp->psr.enabled; 3892 mutex_unlock(&intel_dp->psr.lock); 3893 3894 return ret; 3895 } 3896 3897 /** 3898 * intel_psr_link_ok - return psr->link_ok 3899 * @intel_dp: struct intel_dp 3900 * 3901 * We are seeing unexpected link re-trainings with some panels. This is caused 3902 * by panel stating bad link status after PSR is enabled. Code checking link 3903 * status can call this to ensure it can ignore bad link status stated by the 3904 * panel I.e. if panel is stating bad link and intel_psr_link_ok is stating link 3905 * is ok caller should rely on latter. 3906 * 3907 * Return value of link_ok 3908 */ 3909 bool intel_psr_link_ok(struct intel_dp *intel_dp) 3910 { 3911 bool ret; 3912 3913 if ((!CAN_PSR(intel_dp) && !CAN_PANEL_REPLAY(intel_dp)) || 3914 !intel_dp_is_edp(intel_dp)) 3915 return false; 3916 3917 mutex_lock(&intel_dp->psr.lock); 3918 ret = intel_dp->psr.link_ok; 3919 mutex_unlock(&intel_dp->psr.lock); 3920 3921 return ret; 3922 } 3923 3924 /** 3925 * intel_psr_lock - grab PSR lock 3926 * @crtc_state: the crtc state 3927 * 3928 * This is initially meant to be used by around CRTC update, when 3929 * vblank sensitive registers are updated and we need grab the lock 3930 * before it to avoid vblank evasion. 3931 */ 3932 void intel_psr_lock(const struct intel_crtc_state *crtc_state) 3933 { 3934 struct intel_display *display = to_intel_display(crtc_state); 3935 struct intel_encoder *encoder; 3936 3937 if (!crtc_state->has_psr) 3938 return; 3939 3940 for_each_intel_encoder_mask_with_psr(display->drm, encoder, 3941 crtc_state->uapi.encoder_mask) { 3942 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 3943 3944 mutex_lock(&intel_dp->psr.lock); 3945 break; 3946 } 3947 } 3948 3949 /** 3950 * intel_psr_unlock - release PSR lock 3951 * @crtc_state: the crtc state 3952 * 3953 * Release the PSR lock that was held during pipe update. 3954 */ 3955 void intel_psr_unlock(const struct intel_crtc_state *crtc_state) 3956 { 3957 struct intel_display *display = to_intel_display(crtc_state); 3958 struct intel_encoder *encoder; 3959 3960 if (!crtc_state->has_psr) 3961 return; 3962 3963 for_each_intel_encoder_mask_with_psr(display->drm, encoder, 3964 crtc_state->uapi.encoder_mask) { 3965 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 3966 3967 mutex_unlock(&intel_dp->psr.lock); 3968 break; 3969 } 3970 } 3971 3972 /* Wa_16025596647 */ 3973 static void intel_psr_apply_underrun_on_idle_wa_locked(struct intel_dp *intel_dp) 3974 { 3975 struct intel_display *display = to_intel_display(intel_dp); 3976 bool dc5_dc6_blocked; 3977 3978 if (!intel_dp->psr.active || !intel_dp->psr.pkg_c_latency_used) 3979 return; 3980 3981 dc5_dc6_blocked = is_dc5_dc6_blocked(intel_dp); 3982 3983 if (intel_dp->psr.sel_update_enabled) 3984 psr2_program_idle_frames(intel_dp, dc5_dc6_blocked ? 0 : 3985 psr_compute_idle_frames(intel_dp)); 3986 else 3987 intel_dmc_start_pkgc_exit_at_start_of_undelayed_vblank(display, 3988 intel_dp->psr.pipe, 3989 dc5_dc6_blocked); 3990 } 3991 3992 static void psr_dc5_dc6_wa_work(struct work_struct *work) 3993 { 3994 struct intel_display *display = container_of(work, typeof(*display), 3995 psr_dc5_dc6_wa_work); 3996 struct intel_encoder *encoder; 3997 3998 for_each_intel_encoder_with_psr(display->drm, encoder) { 3999 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 4000 4001 mutex_lock(&intel_dp->psr.lock); 4002 4003 if (intel_dp->psr.enabled && !intel_dp->psr.panel_replay_enabled && 4004 !intel_dp->psr.pkg_c_latency_used) 4005 intel_psr_apply_underrun_on_idle_wa_locked(intel_dp); 4006 4007 mutex_unlock(&intel_dp->psr.lock); 4008 } 4009 } 4010 4011 /** 4012 * intel_psr_notify_dc5_dc6 - Notify PSR about enable/disable dc5/dc6 4013 * @display: intel atomic state 4014 * 4015 * This is targeted for underrun on idle PSR HW bug (Wa_16025596647) to schedule 4016 * psr_dc5_dc6_wa_work used for applying/removing the workaround. 4017 */ 4018 void intel_psr_notify_dc5_dc6(struct intel_display *display) 4019 { 4020 if (!intel_display_wa(display, INTEL_DISPLAY_WA_16025596647)) 4021 return; 4022 4023 schedule_work(&display->psr_dc5_dc6_wa_work); 4024 } 4025 4026 /** 4027 * intel_psr_dc5_dc6_wa_init - Init work for underrun on idle PSR HW bug wa 4028 * @display: intel atomic state 4029 * 4030 * This is targeted for underrun on idle PSR HW bug (Wa_16025596647) to init 4031 * psr_dc5_dc6_wa_work used for applying the workaround. 4032 */ 4033 void intel_psr_dc5_dc6_wa_init(struct intel_display *display) 4034 { 4035 if (!intel_display_wa(display, INTEL_DISPLAY_WA_16025596647)) 4036 return; 4037 4038 INIT_WORK(&display->psr_dc5_dc6_wa_work, psr_dc5_dc6_wa_work); 4039 } 4040 4041 /** 4042 * intel_psr_notify_pipe_change - Notify PSR about enable/disable of a pipe 4043 * @state: intel atomic state 4044 * @crtc: intel crtc 4045 * @enable: enable/disable 4046 * 4047 * This is targeted for underrun on idle PSR HW bug (Wa_16025596647) to apply 4048 * remove the workaround when pipe is getting enabled/disabled 4049 */ 4050 void intel_psr_notify_pipe_change(struct intel_atomic_state *state, 4051 struct intel_crtc *crtc, bool enable) 4052 { 4053 struct intel_display *display = to_intel_display(state); 4054 struct intel_encoder *encoder; 4055 4056 if (!intel_display_wa(display, INTEL_DISPLAY_WA_16025596647)) 4057 return; 4058 4059 for_each_intel_encoder_with_psr(display->drm, encoder) { 4060 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 4061 u8 active_non_psr_pipes; 4062 4063 mutex_lock(&intel_dp->psr.lock); 4064 4065 if (!intel_dp->psr.enabled || intel_dp->psr.panel_replay_enabled) 4066 goto unlock; 4067 4068 active_non_psr_pipes = intel_dp->psr.active_non_psr_pipes; 4069 4070 if (enable) 4071 active_non_psr_pipes |= BIT(crtc->pipe); 4072 else 4073 active_non_psr_pipes &= ~BIT(crtc->pipe); 4074 4075 if (active_non_psr_pipes == intel_dp->psr.active_non_psr_pipes) 4076 goto unlock; 4077 4078 if ((enable && intel_dp->psr.active_non_psr_pipes) || 4079 (!enable && !intel_dp->psr.active_non_psr_pipes) || 4080 !intel_dp->psr.pkg_c_latency_used) { 4081 intel_dp->psr.active_non_psr_pipes = active_non_psr_pipes; 4082 goto unlock; 4083 } 4084 4085 intel_dp->psr.active_non_psr_pipes = active_non_psr_pipes; 4086 4087 intel_psr_apply_underrun_on_idle_wa_locked(intel_dp); 4088 unlock: 4089 mutex_unlock(&intel_dp->psr.lock); 4090 } 4091 } 4092 4093 /** 4094 * intel_psr_notify_vblank_enable_disable - Notify PSR about enable/disable of vblank 4095 * @display: intel display struct 4096 * @enable: enable/disable 4097 * 4098 * This is targeted for underrun on idle PSR HW bug (Wa_16025596647) to apply 4099 * remove the workaround when vblank is getting enabled/disabled 4100 */ 4101 void intel_psr_notify_vblank_enable_disable(struct intel_display *display, 4102 bool enable) 4103 { 4104 struct intel_encoder *encoder; 4105 4106 for_each_intel_encoder_with_psr(display->drm, encoder) { 4107 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 4108 4109 mutex_lock(&intel_dp->psr.lock); 4110 if (CAN_PANEL_REPLAY(intel_dp)) { 4111 if (enable) 4112 intel_dp->psr.vblank_wakeref = 4113 intel_display_power_get(display, 4114 POWER_DOMAIN_DC_OFF); 4115 else 4116 intel_display_power_put(display, POWER_DOMAIN_DC_OFF, 4117 intel_dp->psr.vblank_wakeref); 4118 } 4119 4120 if (intel_dp->psr.enabled && !intel_dp->psr.panel_replay_enabled && 4121 intel_dp->psr.pkg_c_latency_used) 4122 intel_psr_apply_underrun_on_idle_wa_locked(intel_dp); 4123 4124 mutex_unlock(&intel_dp->psr.lock); 4125 } 4126 } 4127 4128 static void 4129 psr_source_status(struct intel_dp *intel_dp, struct seq_file *m) 4130 { 4131 struct intel_display *display = to_intel_display(intel_dp); 4132 enum transcoder cpu_transcoder = intel_dp->psr.transcoder; 4133 const char *status = "unknown"; 4134 u32 val, status_val; 4135 4136 if ((intel_dp_is_edp(intel_dp) || DISPLAY_VER(display) >= 30) && 4137 (intel_dp->psr.sel_update_enabled || intel_dp->psr.panel_replay_enabled)) { 4138 static const char * const live_status[] = { 4139 "IDLE", 4140 "CAPTURE", 4141 "CAPTURE_FS", 4142 "SLEEP", 4143 "BUFON_FW", 4144 "ML_UP", 4145 "SU_STANDBY", 4146 "FAST_SLEEP", 4147 "DEEP_SLEEP", 4148 "BUF_ON", 4149 "TG_ON" 4150 }; 4151 val = intel_de_read(display, 4152 EDP_PSR2_STATUS(display, cpu_transcoder)); 4153 status_val = REG_FIELD_GET(EDP_PSR2_STATUS_STATE_MASK, val); 4154 if (status_val < ARRAY_SIZE(live_status)) 4155 status = live_status[status_val]; 4156 } else { 4157 static const char * const live_status[] = { 4158 "IDLE", 4159 "SRDONACK", 4160 "SRDENT", 4161 "BUFOFF", 4162 "BUFON", 4163 "AUXACK", 4164 "SRDOFFACK", 4165 "SRDENT_ON", 4166 }; 4167 val = intel_de_read(display, 4168 psr_status_reg(display, cpu_transcoder)); 4169 status_val = REG_FIELD_GET(EDP_PSR_STATUS_STATE_MASK, val); 4170 if (status_val < ARRAY_SIZE(live_status)) 4171 status = live_status[status_val]; 4172 } 4173 4174 seq_printf(m, "Source PSR/PanelReplay status: %s [0x%08x]\n", status, val); 4175 } 4176 4177 static void intel_psr_sink_capability(struct intel_connector *connector, 4178 struct seq_file *m) 4179 { 4180 seq_printf(m, "Sink support: PSR = %s", 4181 str_yes_no(connector->dp.psr_caps.support)); 4182 4183 if (connector->dp.psr_caps.support) 4184 seq_printf(m, " [0x%02x]", connector->dp.psr_caps.dpcd[0]); 4185 if (connector->dp.psr_caps.dpcd[0] == DP_PSR2_WITH_Y_COORD_ET_SUPPORTED) 4186 seq_printf(m, " (Early Transport)"); 4187 seq_printf(m, ", Panel Replay = %s", str_yes_no(connector->dp.panel_replay_caps.support)); 4188 seq_printf(m, ", Panel Replay Selective Update = %s", 4189 str_yes_no(connector->dp.panel_replay_caps.su_support)); 4190 seq_printf(m, ", Panel Replay DSC support = %s", 4191 panel_replay_dsc_support_str(connector->dp.panel_replay_caps.dsc_support)); 4192 if (connector->dp.panel_replay_caps.dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_SUPPORT)] & 4193 DP_PANEL_REPLAY_EARLY_TRANSPORT_SUPPORT) 4194 seq_printf(m, " (Early Transport)"); 4195 seq_printf(m, "\n"); 4196 } 4197 4198 static void intel_psr_print_mode(struct intel_dp *intel_dp, 4199 struct seq_file *m) 4200 { 4201 struct intel_psr *psr = &intel_dp->psr; 4202 const char *status, *mode, *region_et; 4203 4204 if (psr->enabled) 4205 status = " enabled"; 4206 else 4207 status = "disabled"; 4208 4209 if (psr->panel_replay_enabled && psr->sel_update_enabled) 4210 mode = "Panel Replay Selective Update"; 4211 else if (psr->panel_replay_enabled) 4212 mode = "Panel Replay"; 4213 else if (psr->sel_update_enabled) 4214 mode = "PSR2"; 4215 else if (psr->enabled) 4216 mode = "PSR1"; 4217 else 4218 mode = ""; 4219 4220 if (psr->su_region_et_enabled) 4221 region_et = " (Early Transport)"; 4222 else 4223 region_et = ""; 4224 4225 seq_printf(m, "PSR mode: %s%s%s\n", mode, status, region_et); 4226 if (psr->no_psr_reason) 4227 seq_printf(m, " %s\n", psr->no_psr_reason); 4228 } 4229 4230 static int intel_psr_status(struct seq_file *m, struct intel_dp *intel_dp, 4231 struct intel_connector *connector) 4232 { 4233 struct intel_display *display = to_intel_display(intel_dp); 4234 enum transcoder cpu_transcoder = intel_dp->psr.transcoder; 4235 struct intel_psr *psr = &intel_dp->psr; 4236 struct ref_tracker *wakeref; 4237 bool enabled; 4238 u32 val, psr2_ctl; 4239 4240 intel_psr_sink_capability(connector, m); 4241 4242 if (!(connector->dp.psr_caps.support || connector->dp.panel_replay_caps.support)) 4243 return 0; 4244 4245 wakeref = intel_display_rpm_get(display); 4246 mutex_lock(&psr->lock); 4247 4248 intel_psr_print_mode(intel_dp, m); 4249 4250 if (!psr->enabled) { 4251 seq_printf(m, "PSR sink not reliable: %s\n", 4252 str_yes_no(psr->sink_not_reliable)); 4253 4254 goto unlock; 4255 } 4256 4257 if (psr->panel_replay_enabled) { 4258 val = intel_de_read(display, TRANS_DP2_CTL(cpu_transcoder)); 4259 4260 if (intel_dp_is_edp(intel_dp)) 4261 psr2_ctl = intel_de_read(display, 4262 EDP_PSR2_CTL(display, 4263 cpu_transcoder)); 4264 4265 enabled = val & TRANS_DP2_PANEL_REPLAY_ENABLE; 4266 } else if (psr->sel_update_enabled) { 4267 val = intel_de_read(display, 4268 EDP_PSR2_CTL(display, cpu_transcoder)); 4269 enabled = val & EDP_PSR2_ENABLE; 4270 } else { 4271 val = intel_de_read(display, psr_ctl_reg(display, cpu_transcoder)); 4272 enabled = val & EDP_PSR_ENABLE; 4273 } 4274 seq_printf(m, "Source PSR/PanelReplay ctl: %s [0x%08x]\n", 4275 str_enabled_disabled(enabled), val); 4276 if (psr->panel_replay_enabled && intel_dp_is_edp(intel_dp)) 4277 seq_printf(m, "PSR2_CTL: 0x%08x\n", 4278 psr2_ctl); 4279 psr_source_status(intel_dp, m); 4280 seq_printf(m, "Busy frontbuffer bits: 0x%08x\n", 4281 psr->busy_frontbuffer_bits); 4282 4283 /* 4284 * SKL+ Perf counter is reset to 0 everytime DC state is entered 4285 */ 4286 val = intel_de_read(display, psr_perf_cnt_reg(display, cpu_transcoder)); 4287 seq_printf(m, "Performance counter: %u\n", 4288 REG_FIELD_GET(EDP_PSR_PERF_CNT_MASK, val)); 4289 4290 if (psr->debug & I915_PSR_DEBUG_IRQ) { 4291 seq_printf(m, "Last attempted entry at: %lld\n", 4292 psr->last_entry_attempt); 4293 seq_printf(m, "Last exit at: %lld\n", psr->last_exit); 4294 } 4295 4296 if (psr->sel_update_enabled) { 4297 u32 su_frames_val[3]; 4298 int frame; 4299 4300 /* 4301 * PSR2_SU_STATUS register has been tied-off since DG2/ADL-P 4302 * (it returns zeros only) and it has been removed on Xe2_LPD. 4303 */ 4304 if (DISPLAY_VER(display) < 13) { 4305 /* 4306 * Reading all 3 registers before hand to minimize crossing a 4307 * frame boundary between register reads 4308 */ 4309 for (frame = 0; frame < PSR2_SU_STATUS_FRAMES; frame += 3) { 4310 val = intel_de_read(display, 4311 PSR2_SU_STATUS(display, cpu_transcoder, frame)); 4312 su_frames_val[frame / 3] = val; 4313 } 4314 4315 seq_puts(m, "Frame:\tPSR2 SU blocks:\n"); 4316 4317 for (frame = 0; frame < PSR2_SU_STATUS_FRAMES; frame++) { 4318 u32 su_blocks; 4319 4320 su_blocks = su_frames_val[frame / 3] & 4321 PSR2_SU_STATUS_MASK(frame); 4322 su_blocks = su_blocks >> PSR2_SU_STATUS_SHIFT(frame); 4323 seq_printf(m, "%d\t%d\n", frame, su_blocks); 4324 } 4325 } 4326 4327 seq_printf(m, "PSR2 selective fetch: %s\n", 4328 str_enabled_disabled(psr->psr2_sel_fetch_enabled)); 4329 } 4330 4331 unlock: 4332 mutex_unlock(&psr->lock); 4333 intel_display_rpm_put(display, wakeref); 4334 4335 return 0; 4336 } 4337 4338 static int i915_edp_psr_status_show(struct seq_file *m, void *data) 4339 { 4340 struct intel_display *display = m->private; 4341 struct intel_dp *intel_dp = NULL; 4342 struct intel_encoder *encoder; 4343 4344 if (!HAS_PSR(display)) 4345 return -ENODEV; 4346 4347 /* Find the first EDP which supports PSR */ 4348 for_each_intel_encoder_with_psr(display->drm, encoder) { 4349 intel_dp = enc_to_intel_dp(encoder); 4350 break; 4351 } 4352 4353 if (!intel_dp) 4354 return -ENODEV; 4355 4356 return intel_psr_status(m, intel_dp, intel_dp->attached_connector); 4357 } 4358 DEFINE_SHOW_ATTRIBUTE(i915_edp_psr_status); 4359 4360 static int 4361 i915_edp_psr_debug_set(void *data, u64 val) 4362 { 4363 struct intel_display *display = data; 4364 struct intel_encoder *encoder; 4365 int ret = -ENODEV; 4366 4367 if (!HAS_PSR(display)) 4368 return ret; 4369 4370 for_each_intel_encoder_with_psr(display->drm, encoder) { 4371 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 4372 4373 drm_dbg_kms(display->drm, "Setting PSR debug to %llx\n", val); 4374 4375 // TODO: split to each transcoder's PSR debug state 4376 with_intel_display_rpm(display) 4377 ret = intel_psr_debug_set(intel_dp, val); 4378 } 4379 4380 return ret; 4381 } 4382 4383 static int 4384 i915_edp_psr_debug_get(void *data, u64 *val) 4385 { 4386 struct intel_display *display = data; 4387 struct intel_encoder *encoder; 4388 4389 if (!HAS_PSR(display)) 4390 return -ENODEV; 4391 4392 for_each_intel_encoder_with_psr(display->drm, encoder) { 4393 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 4394 4395 // TODO: split to each transcoder's PSR debug state 4396 *val = READ_ONCE(intel_dp->psr.debug); 4397 return 0; 4398 } 4399 4400 return -ENODEV; 4401 } 4402 4403 DEFINE_SIMPLE_ATTRIBUTE(i915_edp_psr_debug_fops, 4404 i915_edp_psr_debug_get, i915_edp_psr_debug_set, 4405 "%llu\n"); 4406 4407 void intel_psr_debugfs_register(struct intel_display *display) 4408 { 4409 struct dentry *debugfs_root = display->drm->debugfs_root; 4410 4411 debugfs_create_file("i915_edp_psr_debug", 0644, debugfs_root, 4412 display, &i915_edp_psr_debug_fops); 4413 4414 debugfs_create_file("i915_edp_psr_status", 0444, debugfs_root, 4415 display, &i915_edp_psr_status_fops); 4416 } 4417 4418 static const char *psr_mode_str(struct intel_dp *intel_dp) 4419 { 4420 if (intel_dp->psr.panel_replay_enabled) 4421 return "PANEL-REPLAY"; 4422 else if (intel_dp->psr.enabled) 4423 return "PSR"; 4424 4425 return "unknown"; 4426 } 4427 4428 static int i915_psr_sink_status_show(struct seq_file *m, void *data) 4429 { 4430 struct intel_connector *connector = m->private; 4431 struct intel_dp *intel_dp = intel_attached_dp(connector); 4432 static const char * const sink_status[] = { 4433 "inactive", 4434 "transition to active, capture and display", 4435 "active, display from RFB", 4436 "active, capture and display on sink device timings", 4437 "transition to inactive, capture and display, timing re-sync", 4438 "reserved", 4439 "reserved", 4440 "sink internal error", 4441 }; 4442 const char *str; 4443 int ret; 4444 u8 status, error_status; 4445 4446 if (!(CAN_PSR(intel_dp) || CAN_PANEL_REPLAY(intel_dp))) { 4447 seq_puts(m, "PSR/Panel-Replay Unsupported\n"); 4448 return -ENODEV; 4449 } 4450 4451 if (connector->base.status != connector_status_connected) 4452 return -ENODEV; 4453 4454 ret = psr_get_status_and_error_status(intel_dp, &status, &error_status); 4455 if (ret) 4456 return ret; 4457 4458 status &= DP_PSR_SINK_STATE_MASK; 4459 if (status < ARRAY_SIZE(sink_status)) 4460 str = sink_status[status]; 4461 else 4462 str = "unknown"; 4463 4464 seq_printf(m, "Sink %s status: 0x%x [%s]\n", psr_mode_str(intel_dp), status, str); 4465 4466 seq_printf(m, "Sink %s error status: 0x%x", psr_mode_str(intel_dp), error_status); 4467 4468 if (error_status & (DP_PSR_RFB_STORAGE_ERROR | 4469 DP_PSR_VSC_SDP_UNCORRECTABLE_ERROR | 4470 DP_PSR_LINK_CRC_ERROR)) 4471 seq_puts(m, ":\n"); 4472 else 4473 seq_puts(m, "\n"); 4474 if (error_status & DP_PSR_RFB_STORAGE_ERROR) 4475 seq_printf(m, "\t%s RFB storage error\n", psr_mode_str(intel_dp)); 4476 if (error_status & DP_PSR_VSC_SDP_UNCORRECTABLE_ERROR) 4477 seq_printf(m, "\t%s VSC SDP uncorrectable error\n", psr_mode_str(intel_dp)); 4478 if (error_status & DP_PSR_LINK_CRC_ERROR) 4479 seq_printf(m, "\t%s Link CRC error\n", psr_mode_str(intel_dp)); 4480 4481 return ret; 4482 } 4483 DEFINE_SHOW_ATTRIBUTE(i915_psr_sink_status); 4484 4485 static int i915_psr_status_show(struct seq_file *m, void *data) 4486 { 4487 struct intel_connector *connector = m->private; 4488 struct intel_dp *intel_dp = intel_attached_dp(connector); 4489 4490 return intel_psr_status(m, intel_dp, connector); 4491 } 4492 DEFINE_SHOW_ATTRIBUTE(i915_psr_status); 4493 4494 void intel_psr_connector_debugfs_add(struct intel_connector *connector) 4495 { 4496 struct intel_display *display = to_intel_display(connector); 4497 struct dentry *root = connector->base.debugfs_entry; 4498 4499 if (connector->base.connector_type != DRM_MODE_CONNECTOR_eDP && 4500 connector->base.connector_type != DRM_MODE_CONNECTOR_DisplayPort) 4501 return; 4502 4503 debugfs_create_file("i915_psr_sink_status", 0444, root, 4504 connector, &i915_psr_sink_status_fops); 4505 4506 if (HAS_PSR(display) || HAS_DP20(display)) 4507 debugfs_create_file("i915_psr_status", 0444, root, 4508 connector, &i915_psr_status_fops); 4509 } 4510 4511 bool intel_psr_needs_alpm(struct intel_dp *intel_dp, const struct intel_crtc_state *crtc_state) 4512 { 4513 /* 4514 * eDP Panel Replay uses always ALPM 4515 * PSR2 uses ALPM but PSR1 doesn't 4516 */ 4517 return intel_dp_is_edp(intel_dp) && (crtc_state->has_sel_update || 4518 crtc_state->has_panel_replay); 4519 } 4520 4521 bool intel_psr_needs_alpm_aux_less(struct intel_dp *intel_dp, 4522 const struct intel_crtc_state *crtc_state) 4523 { 4524 return intel_dp_is_edp(intel_dp) && crtc_state->has_panel_replay; 4525 } 4526 4527 void intel_psr_compute_config_late(struct intel_dp *intel_dp, 4528 struct intel_crtc_state *crtc_state) 4529 { 4530 struct intel_display *display = to_intel_display(intel_dp); 4531 int vblank = intel_crtc_vblank_length(crtc_state); 4532 int wake_lines; 4533 4534 if (intel_psr_needs_alpm_aux_less(intel_dp, crtc_state)) 4535 wake_lines = crtc_state->alpm_state.aux_less_wake_lines; 4536 else if (intel_psr_needs_alpm(intel_dp, crtc_state)) 4537 wake_lines = DISPLAY_VER(display) < 20 ? 4538 psr2_block_count_lines(crtc_state->alpm_state.io_wake_lines, 4539 crtc_state->alpm_state.fast_wake_lines) : 4540 crtc_state->alpm_state.io_wake_lines; 4541 else 4542 wake_lines = 0; 4543 4544 /* 4545 * Disable the PSR features if wake lines exceed the available vblank. 4546 * Though SCL is computed based on these PSR features, it is not reset 4547 * even if the PSR features are disabled to avoid changing vblank start 4548 * at this stage. 4549 */ 4550 if (wake_lines && !_wake_lines_fit_into_vblank(crtc_state, vblank, wake_lines)) { 4551 drm_dbg_kms(display->drm, 4552 "Adjusting PSR/PR mode: vblank too short for wake lines = %d\n", 4553 wake_lines); 4554 4555 if (crtc_state->has_panel_replay) { 4556 crtc_state->has_panel_replay = false; 4557 /* 4558 * #TODO : Add fall back to PSR/PSR2 4559 * Since panel replay cannot be supported, we can fall back to PSR/PSR2. 4560 * This will require calling compute_config for psr and psr2 with check for 4561 * actual guardband instead of vblank_length. 4562 */ 4563 crtc_state->has_psr = false; 4564 } 4565 4566 crtc_state->has_sel_update = false; 4567 crtc_state->enable_psr2_su_region_et = false; 4568 crtc_state->enable_psr2_sel_fetch = false; 4569 } 4570 4571 /* Wa_18037818876 */ 4572 if (intel_psr_needs_wa_18037818876(intel_dp, crtc_state)) { 4573 crtc_state->has_psr = false; 4574 drm_dbg_kms(display->drm, 4575 "PSR disabled to workaround PSR FSM hang issue\n"); 4576 } 4577 4578 intel_psr_set_non_psr_pipes(intel_dp, crtc_state); 4579 } 4580 4581 int intel_psr_min_guardband(struct intel_crtc_state *crtc_state) 4582 { 4583 struct intel_display *display = to_intel_display(crtc_state); 4584 int psr_min_guardband; 4585 int wake_lines; 4586 4587 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) 4588 return 0; 4589 4590 if (crtc_state->has_panel_replay) 4591 wake_lines = crtc_state->alpm_state.aux_less_wake_lines; 4592 else if (crtc_state->has_sel_update) 4593 wake_lines = DISPLAY_VER(display) < 20 ? 4594 psr2_block_count_lines(crtc_state->alpm_state.io_wake_lines, 4595 crtc_state->alpm_state.fast_wake_lines) : 4596 crtc_state->alpm_state.io_wake_lines; 4597 else 4598 return 0; 4599 4600 psr_min_guardband = wake_lines + crtc_state->set_context_latency; 4601 4602 if (crtc_state->req_psr2_sdp_prior_scanline) 4603 psr_min_guardband++; 4604 4605 return psr_min_guardband; 4606 } 4607 4608 bool intel_psr_use_trans_push(const struct intel_crtc_state *crtc_state) 4609 { 4610 struct intel_display *display = to_intel_display(crtc_state); 4611 4612 return HAS_PSR_TRANS_PUSH_FRAME_CHANGE(display) && crtc_state->has_psr; 4613 } 4614 4615 bool intel_psr_pr_async_video_timing_supported(struct intel_dp *intel_dp) 4616 { 4617 struct intel_connector *connector = intel_dp->attached_connector; 4618 u8 *dpcd = connector->dp.panel_replay_caps.dpcd; 4619 u8 pr_support = dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_SUPPORT)]; 4620 u8 pr_cap = dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_CAPABILITY)]; 4621 4622 return (pr_support & DP_PANEL_REPLAY_SUPPORT) && 4623 !(pr_cap & DP_PANEL_REPLAY_ASYNC_VIDEO_TIMING_NOT_SUPPORTED_IN_PR); 4624 } 4625