1 /* 2 * Copyright © 2014 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 */ 23 24 #include <drm/drm_atomic_helper.h> 25 26 #include "display/intel_dp.h" 27 28 #include "i915_drv.h" 29 #include "intel_atomic.h" 30 #include "intel_de.h" 31 #include "intel_display_types.h" 32 #include "intel_dp_aux.h" 33 #include "intel_hdmi.h" 34 #include "intel_psr.h" 35 #include "intel_sprite.h" 36 #include "skl_universal_plane.h" 37 38 /** 39 * DOC: Panel Self Refresh (PSR/SRD) 40 * 41 * Since Haswell Display controller supports Panel Self-Refresh on display 42 * panels witch have a remote frame buffer (RFB) implemented according to PSR 43 * spec in eDP1.3. PSR feature allows the display to go to lower standby states 44 * when system is idle but display is on as it eliminates display refresh 45 * request to DDR memory completely as long as the frame buffer for that 46 * display is unchanged. 47 * 48 * Panel Self Refresh must be supported by both Hardware (source) and 49 * Panel (sink). 50 * 51 * PSR saves power by caching the framebuffer in the panel RFB, which allows us 52 * to power down the link and memory controller. For DSI panels the same idea 53 * is called "manual mode". 54 * 55 * The implementation uses the hardware-based PSR support which automatically 56 * enters/exits self-refresh mode. The hardware takes care of sending the 57 * required DP aux message and could even retrain the link (that part isn't 58 * enabled yet though). The hardware also keeps track of any frontbuffer 59 * changes to know when to exit self-refresh mode again. Unfortunately that 60 * part doesn't work too well, hence why the i915 PSR support uses the 61 * software frontbuffer tracking to make sure it doesn't miss a screen 62 * update. For this integration intel_psr_invalidate() and intel_psr_flush() 63 * get called by the frontbuffer tracking code. Note that because of locking 64 * issues the self-refresh re-enable code is done from a work queue, which 65 * must be correctly synchronized/cancelled when shutting down the pipe." 66 * 67 * DC3CO (DC3 clock off) 68 * 69 * On top of PSR2, GEN12 adds a intermediate power savings state that turns 70 * clock off automatically during PSR2 idle state. 71 * The smaller overhead of DC3co entry/exit vs. the overhead of PSR2 deep sleep 72 * entry/exit allows the HW to enter a low-power state even when page flipping 73 * periodically (for instance a 30fps video playback scenario). 74 * 75 * Every time a flips occurs PSR2 will get out of deep sleep state(if it was), 76 * so DC3CO is enabled and tgl_dc3co_disable_work is schedule to run after 6 77 * frames, if no other flip occurs and the function above is executed, DC3CO is 78 * disabled and PSR2 is configured to enter deep sleep, resetting again in case 79 * of another flip. 80 * Front buffer modifications do not trigger DC3CO activation on purpose as it 81 * would bring a lot of complexity and most of the moderns systems will only 82 * use page flips. 83 */ 84 85 static bool psr_global_enabled(struct intel_dp *intel_dp) 86 { 87 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 88 89 switch (intel_dp->psr.debug & I915_PSR_DEBUG_MODE_MASK) { 90 case I915_PSR_DEBUG_DEFAULT: 91 return i915->params.enable_psr; 92 case I915_PSR_DEBUG_DISABLE: 93 return false; 94 default: 95 return true; 96 } 97 } 98 99 static bool psr2_global_enabled(struct intel_dp *intel_dp) 100 { 101 switch (intel_dp->psr.debug & I915_PSR_DEBUG_MODE_MASK) { 102 case I915_PSR_DEBUG_DISABLE: 103 case I915_PSR_DEBUG_FORCE_PSR1: 104 return false; 105 default: 106 return true; 107 } 108 } 109 110 static void psr_irq_control(struct intel_dp *intel_dp) 111 { 112 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 113 enum transcoder trans_shift; 114 i915_reg_t imr_reg; 115 u32 mask, val; 116 117 /* 118 * gen12+ has registers relative to transcoder and one per transcoder 119 * using the same bit definition: handle it as TRANSCODER_EDP to force 120 * 0 shift in bit definition 121 */ 122 if (DISPLAY_VER(dev_priv) >= 12) { 123 trans_shift = 0; 124 imr_reg = TRANS_PSR_IMR(intel_dp->psr.transcoder); 125 } else { 126 trans_shift = intel_dp->psr.transcoder; 127 imr_reg = EDP_PSR_IMR; 128 } 129 130 mask = EDP_PSR_ERROR(trans_shift); 131 if (intel_dp->psr.debug & I915_PSR_DEBUG_IRQ) 132 mask |= EDP_PSR_POST_EXIT(trans_shift) | 133 EDP_PSR_PRE_ENTRY(trans_shift); 134 135 /* Warning: it is masking/setting reserved bits too */ 136 val = intel_de_read(dev_priv, imr_reg); 137 val &= ~EDP_PSR_TRANS_MASK(trans_shift); 138 val |= ~mask; 139 intel_de_write(dev_priv, imr_reg, val); 140 } 141 142 static void psr_event_print(struct drm_i915_private *i915, 143 u32 val, bool psr2_enabled) 144 { 145 drm_dbg_kms(&i915->drm, "PSR exit events: 0x%x\n", val); 146 if (val & PSR_EVENT_PSR2_WD_TIMER_EXPIRE) 147 drm_dbg_kms(&i915->drm, "\tPSR2 watchdog timer expired\n"); 148 if ((val & PSR_EVENT_PSR2_DISABLED) && psr2_enabled) 149 drm_dbg_kms(&i915->drm, "\tPSR2 disabled\n"); 150 if (val & PSR_EVENT_SU_DIRTY_FIFO_UNDERRUN) 151 drm_dbg_kms(&i915->drm, "\tSU dirty FIFO underrun\n"); 152 if (val & PSR_EVENT_SU_CRC_FIFO_UNDERRUN) 153 drm_dbg_kms(&i915->drm, "\tSU CRC FIFO underrun\n"); 154 if (val & PSR_EVENT_GRAPHICS_RESET) 155 drm_dbg_kms(&i915->drm, "\tGraphics reset\n"); 156 if (val & PSR_EVENT_PCH_INTERRUPT) 157 drm_dbg_kms(&i915->drm, "\tPCH interrupt\n"); 158 if (val & PSR_EVENT_MEMORY_UP) 159 drm_dbg_kms(&i915->drm, "\tMemory up\n"); 160 if (val & PSR_EVENT_FRONT_BUFFER_MODIFY) 161 drm_dbg_kms(&i915->drm, "\tFront buffer modification\n"); 162 if (val & PSR_EVENT_WD_TIMER_EXPIRE) 163 drm_dbg_kms(&i915->drm, "\tPSR watchdog timer expired\n"); 164 if (val & PSR_EVENT_PIPE_REGISTERS_UPDATE) 165 drm_dbg_kms(&i915->drm, "\tPIPE registers updated\n"); 166 if (val & PSR_EVENT_REGISTER_UPDATE) 167 drm_dbg_kms(&i915->drm, "\tRegister updated\n"); 168 if (val & PSR_EVENT_HDCP_ENABLE) 169 drm_dbg_kms(&i915->drm, "\tHDCP enabled\n"); 170 if (val & PSR_EVENT_KVMR_SESSION_ENABLE) 171 drm_dbg_kms(&i915->drm, "\tKVMR session enabled\n"); 172 if (val & PSR_EVENT_VBI_ENABLE) 173 drm_dbg_kms(&i915->drm, "\tVBI enabled\n"); 174 if (val & PSR_EVENT_LPSP_MODE_EXIT) 175 drm_dbg_kms(&i915->drm, "\tLPSP mode exited\n"); 176 if ((val & PSR_EVENT_PSR_DISABLE) && !psr2_enabled) 177 drm_dbg_kms(&i915->drm, "\tPSR disabled\n"); 178 } 179 180 void intel_psr_irq_handler(struct intel_dp *intel_dp, u32 psr_iir) 181 { 182 enum transcoder cpu_transcoder = intel_dp->psr.transcoder; 183 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 184 ktime_t time_ns = ktime_get(); 185 enum transcoder trans_shift; 186 i915_reg_t imr_reg; 187 188 if (DISPLAY_VER(dev_priv) >= 12) { 189 trans_shift = 0; 190 imr_reg = TRANS_PSR_IMR(intel_dp->psr.transcoder); 191 } else { 192 trans_shift = intel_dp->psr.transcoder; 193 imr_reg = EDP_PSR_IMR; 194 } 195 196 if (psr_iir & EDP_PSR_PRE_ENTRY(trans_shift)) { 197 intel_dp->psr.last_entry_attempt = time_ns; 198 drm_dbg_kms(&dev_priv->drm, 199 "[transcoder %s] PSR entry attempt in 2 vblanks\n", 200 transcoder_name(cpu_transcoder)); 201 } 202 203 if (psr_iir & EDP_PSR_POST_EXIT(trans_shift)) { 204 intel_dp->psr.last_exit = time_ns; 205 drm_dbg_kms(&dev_priv->drm, 206 "[transcoder %s] PSR exit completed\n", 207 transcoder_name(cpu_transcoder)); 208 209 if (DISPLAY_VER(dev_priv) >= 9) { 210 u32 val = intel_de_read(dev_priv, 211 PSR_EVENT(cpu_transcoder)); 212 bool psr2_enabled = intel_dp->psr.psr2_enabled; 213 214 intel_de_write(dev_priv, PSR_EVENT(cpu_transcoder), 215 val); 216 psr_event_print(dev_priv, val, psr2_enabled); 217 } 218 } 219 220 if (psr_iir & EDP_PSR_ERROR(trans_shift)) { 221 u32 val; 222 223 drm_warn(&dev_priv->drm, "[transcoder %s] PSR aux error\n", 224 transcoder_name(cpu_transcoder)); 225 226 intel_dp->psr.irq_aux_error = true; 227 228 /* 229 * If this interruption is not masked it will keep 230 * interrupting so fast that it prevents the scheduled 231 * work to run. 232 * Also after a PSR error, we don't want to arm PSR 233 * again so we don't care about unmask the interruption 234 * or unset irq_aux_error. 235 */ 236 val = intel_de_read(dev_priv, imr_reg); 237 val |= EDP_PSR_ERROR(trans_shift); 238 intel_de_write(dev_priv, imr_reg, val); 239 240 schedule_work(&intel_dp->psr.work); 241 } 242 } 243 244 static bool intel_dp_get_alpm_status(struct intel_dp *intel_dp) 245 { 246 u8 alpm_caps = 0; 247 248 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_RECEIVER_ALPM_CAP, 249 &alpm_caps) != 1) 250 return false; 251 return alpm_caps & DP_ALPM_CAP; 252 } 253 254 static u8 intel_dp_get_sink_sync_latency(struct intel_dp *intel_dp) 255 { 256 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 257 u8 val = 8; /* assume the worst if we can't read the value */ 258 259 if (drm_dp_dpcd_readb(&intel_dp->aux, 260 DP_SYNCHRONIZATION_LATENCY_IN_SINK, &val) == 1) 261 val &= DP_MAX_RESYNC_FRAME_COUNT_MASK; 262 else 263 drm_dbg_kms(&i915->drm, 264 "Unable to get sink synchronization latency, assuming 8 frames\n"); 265 return val; 266 } 267 268 static void intel_dp_get_su_granularity(struct intel_dp *intel_dp) 269 { 270 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 271 ssize_t r; 272 u16 w; 273 u8 y; 274 275 /* If sink don't have specific granularity requirements set legacy ones */ 276 if (!(intel_dp->psr_dpcd[1] & DP_PSR2_SU_GRANULARITY_REQUIRED)) { 277 /* As PSR2 HW sends full lines, we do not care about x granularity */ 278 w = 4; 279 y = 4; 280 goto exit; 281 } 282 283 r = drm_dp_dpcd_read(&intel_dp->aux, DP_PSR2_SU_X_GRANULARITY, &w, 2); 284 if (r != 2) 285 drm_dbg_kms(&i915->drm, 286 "Unable to read DP_PSR2_SU_X_GRANULARITY\n"); 287 /* 288 * Spec says that if the value read is 0 the default granularity should 289 * be used instead. 290 */ 291 if (r != 2 || w == 0) 292 w = 4; 293 294 r = drm_dp_dpcd_read(&intel_dp->aux, DP_PSR2_SU_Y_GRANULARITY, &y, 1); 295 if (r != 1) { 296 drm_dbg_kms(&i915->drm, 297 "Unable to read DP_PSR2_SU_Y_GRANULARITY\n"); 298 y = 4; 299 } 300 if (y == 0) 301 y = 1; 302 303 exit: 304 intel_dp->psr.su_w_granularity = w; 305 intel_dp->psr.su_y_granularity = y; 306 } 307 308 void intel_psr_init_dpcd(struct intel_dp *intel_dp) 309 { 310 struct drm_i915_private *dev_priv = 311 to_i915(dp_to_dig_port(intel_dp)->base.base.dev); 312 313 drm_dp_dpcd_read(&intel_dp->aux, DP_PSR_SUPPORT, intel_dp->psr_dpcd, 314 sizeof(intel_dp->psr_dpcd)); 315 316 if (!intel_dp->psr_dpcd[0]) 317 return; 318 drm_dbg_kms(&dev_priv->drm, "eDP panel supports PSR version %x\n", 319 intel_dp->psr_dpcd[0]); 320 321 if (drm_dp_has_quirk(&intel_dp->desc, DP_DPCD_QUIRK_NO_PSR)) { 322 drm_dbg_kms(&dev_priv->drm, 323 "PSR support not currently available for this panel\n"); 324 return; 325 } 326 327 if (!(intel_dp->edp_dpcd[1] & DP_EDP_SET_POWER_CAP)) { 328 drm_dbg_kms(&dev_priv->drm, 329 "Panel lacks power state control, PSR cannot be enabled\n"); 330 return; 331 } 332 333 intel_dp->psr.sink_support = true; 334 intel_dp->psr.sink_sync_latency = 335 intel_dp_get_sink_sync_latency(intel_dp); 336 337 if (DISPLAY_VER(dev_priv) >= 9 && 338 (intel_dp->psr_dpcd[0] == DP_PSR2_WITH_Y_COORD_IS_SUPPORTED)) { 339 bool y_req = intel_dp->psr_dpcd[1] & 340 DP_PSR2_SU_Y_COORDINATE_REQUIRED; 341 bool alpm = intel_dp_get_alpm_status(intel_dp); 342 343 /* 344 * All panels that supports PSR version 03h (PSR2 + 345 * Y-coordinate) can handle Y-coordinates in VSC but we are 346 * only sure that it is going to be used when required by the 347 * panel. This way panel is capable to do selective update 348 * without a aux frame sync. 349 * 350 * To support PSR version 02h and PSR version 03h without 351 * Y-coordinate requirement panels we would need to enable 352 * GTC first. 353 */ 354 intel_dp->psr.sink_psr2_support = y_req && alpm; 355 drm_dbg_kms(&dev_priv->drm, "PSR2 %ssupported\n", 356 intel_dp->psr.sink_psr2_support ? "" : "not "); 357 358 if (intel_dp->psr.sink_psr2_support) { 359 intel_dp->psr.colorimetry_support = 360 intel_dp_get_colorimetry_status(intel_dp); 361 intel_dp_get_su_granularity(intel_dp); 362 } 363 } 364 } 365 366 static void hsw_psr_setup_aux(struct intel_dp *intel_dp) 367 { 368 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 369 u32 aux_clock_divider, aux_ctl; 370 int i; 371 static const u8 aux_msg[] = { 372 [0] = DP_AUX_NATIVE_WRITE << 4, 373 [1] = DP_SET_POWER >> 8, 374 [2] = DP_SET_POWER & 0xff, 375 [3] = 1 - 1, 376 [4] = DP_SET_POWER_D0, 377 }; 378 u32 psr_aux_mask = EDP_PSR_AUX_CTL_TIME_OUT_MASK | 379 EDP_PSR_AUX_CTL_MESSAGE_SIZE_MASK | 380 EDP_PSR_AUX_CTL_PRECHARGE_2US_MASK | 381 EDP_PSR_AUX_CTL_BIT_CLOCK_2X_MASK; 382 383 BUILD_BUG_ON(sizeof(aux_msg) > 20); 384 for (i = 0; i < sizeof(aux_msg); i += 4) 385 intel_de_write(dev_priv, 386 EDP_PSR_AUX_DATA(intel_dp->psr.transcoder, i >> 2), 387 intel_dp_pack_aux(&aux_msg[i], sizeof(aux_msg) - i)); 388 389 aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, 0); 390 391 /* Start with bits set for DDI_AUX_CTL register */ 392 aux_ctl = intel_dp->get_aux_send_ctl(intel_dp, sizeof(aux_msg), 393 aux_clock_divider); 394 395 /* Select only valid bits for SRD_AUX_CTL */ 396 aux_ctl &= psr_aux_mask; 397 intel_de_write(dev_priv, EDP_PSR_AUX_CTL(intel_dp->psr.transcoder), 398 aux_ctl); 399 } 400 401 static void intel_psr_enable_sink(struct intel_dp *intel_dp) 402 { 403 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 404 u8 dpcd_val = DP_PSR_ENABLE; 405 406 /* Enable ALPM at sink for psr2 */ 407 if (intel_dp->psr.psr2_enabled) { 408 drm_dp_dpcd_writeb(&intel_dp->aux, DP_RECEIVER_ALPM_CONFIG, 409 DP_ALPM_ENABLE | 410 DP_ALPM_LOCK_ERROR_IRQ_HPD_ENABLE); 411 412 dpcd_val |= DP_PSR_ENABLE_PSR2 | DP_PSR_IRQ_HPD_WITH_CRC_ERRORS; 413 } else { 414 if (intel_dp->psr.link_standby) 415 dpcd_val |= DP_PSR_MAIN_LINK_ACTIVE; 416 417 if (DISPLAY_VER(dev_priv) >= 8) 418 dpcd_val |= DP_PSR_CRC_VERIFICATION; 419 } 420 421 if (intel_dp->psr.req_psr2_sdp_prior_scanline) 422 dpcd_val |= DP_PSR_SU_REGION_SCANLINE_CAPTURE; 423 424 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, dpcd_val); 425 426 drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, DP_SET_POWER_D0); 427 } 428 429 static u32 intel_psr1_get_tp_time(struct intel_dp *intel_dp) 430 { 431 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 432 u32 val = 0; 433 434 if (DISPLAY_VER(dev_priv) >= 11) 435 val |= EDP_PSR_TP4_TIME_0US; 436 437 if (dev_priv->params.psr_safest_params) { 438 val |= EDP_PSR_TP1_TIME_2500us; 439 val |= EDP_PSR_TP2_TP3_TIME_2500us; 440 goto check_tp3_sel; 441 } 442 443 if (dev_priv->vbt.psr.tp1_wakeup_time_us == 0) 444 val |= EDP_PSR_TP1_TIME_0us; 445 else if (dev_priv->vbt.psr.tp1_wakeup_time_us <= 100) 446 val |= EDP_PSR_TP1_TIME_100us; 447 else if (dev_priv->vbt.psr.tp1_wakeup_time_us <= 500) 448 val |= EDP_PSR_TP1_TIME_500us; 449 else 450 val |= EDP_PSR_TP1_TIME_2500us; 451 452 if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us == 0) 453 val |= EDP_PSR_TP2_TP3_TIME_0us; 454 else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 100) 455 val |= EDP_PSR_TP2_TP3_TIME_100us; 456 else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 500) 457 val |= EDP_PSR_TP2_TP3_TIME_500us; 458 else 459 val |= EDP_PSR_TP2_TP3_TIME_2500us; 460 461 check_tp3_sel: 462 if (intel_dp_source_supports_hbr2(intel_dp) && 463 drm_dp_tps3_supported(intel_dp->dpcd)) 464 val |= EDP_PSR_TP1_TP3_SEL; 465 else 466 val |= EDP_PSR_TP1_TP2_SEL; 467 468 return val; 469 } 470 471 static u8 psr_compute_idle_frames(struct intel_dp *intel_dp) 472 { 473 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 474 int idle_frames; 475 476 /* Let's use 6 as the minimum to cover all known cases including the 477 * off-by-one issue that HW has in some cases. 478 */ 479 idle_frames = max(6, dev_priv->vbt.psr.idle_frames); 480 idle_frames = max(idle_frames, intel_dp->psr.sink_sync_latency + 1); 481 482 if (drm_WARN_ON(&dev_priv->drm, idle_frames > 0xf)) 483 idle_frames = 0xf; 484 485 return idle_frames; 486 } 487 488 static void hsw_activate_psr1(struct intel_dp *intel_dp) 489 { 490 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 491 u32 max_sleep_time = 0x1f; 492 u32 val = EDP_PSR_ENABLE; 493 494 val |= psr_compute_idle_frames(intel_dp) << EDP_PSR_IDLE_FRAME_SHIFT; 495 496 val |= max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT; 497 if (IS_HASWELL(dev_priv)) 498 val |= EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES; 499 500 if (intel_dp->psr.link_standby) 501 val |= EDP_PSR_LINK_STANDBY; 502 503 val |= intel_psr1_get_tp_time(intel_dp); 504 505 if (DISPLAY_VER(dev_priv) >= 8) 506 val |= EDP_PSR_CRC_ENABLE; 507 508 val |= (intel_de_read(dev_priv, EDP_PSR_CTL(intel_dp->psr.transcoder)) & 509 EDP_PSR_RESTORE_PSR_ACTIVE_CTX_MASK); 510 intel_de_write(dev_priv, EDP_PSR_CTL(intel_dp->psr.transcoder), val); 511 } 512 513 static u32 intel_psr2_get_tp_time(struct intel_dp *intel_dp) 514 { 515 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 516 u32 val = 0; 517 518 if (dev_priv->params.psr_safest_params) 519 return EDP_PSR2_TP2_TIME_2500us; 520 521 if (dev_priv->vbt.psr.psr2_tp2_tp3_wakeup_time_us >= 0 && 522 dev_priv->vbt.psr.psr2_tp2_tp3_wakeup_time_us <= 50) 523 val |= EDP_PSR2_TP2_TIME_50us; 524 else if (dev_priv->vbt.psr.psr2_tp2_tp3_wakeup_time_us <= 100) 525 val |= EDP_PSR2_TP2_TIME_100us; 526 else if (dev_priv->vbt.psr.psr2_tp2_tp3_wakeup_time_us <= 500) 527 val |= EDP_PSR2_TP2_TIME_500us; 528 else 529 val |= EDP_PSR2_TP2_TIME_2500us; 530 531 return val; 532 } 533 534 static void hsw_activate_psr2(struct intel_dp *intel_dp) 535 { 536 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 537 u32 val; 538 539 val = psr_compute_idle_frames(intel_dp) << EDP_PSR2_IDLE_FRAME_SHIFT; 540 541 val |= EDP_PSR2_ENABLE | EDP_SU_TRACK_ENABLE; 542 if (DISPLAY_VER(dev_priv) >= 10 && DISPLAY_VER(dev_priv) <= 12) 543 val |= EDP_Y_COORDINATE_ENABLE; 544 545 val |= EDP_PSR2_FRAME_BEFORE_SU(intel_dp->psr.sink_sync_latency + 1); 546 val |= intel_psr2_get_tp_time(intel_dp); 547 548 /* Wa_22012278275:adlp */ 549 if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_D1)) { 550 static const u8 map[] = { 551 2, /* 5 lines */ 552 1, /* 6 lines */ 553 0, /* 7 lines */ 554 3, /* 8 lines */ 555 6, /* 9 lines */ 556 5, /* 10 lines */ 557 4, /* 11 lines */ 558 7, /* 12 lines */ 559 }; 560 /* 561 * Still using the default IO_BUFFER_WAKE and FAST_WAKE, see 562 * comments bellow for more information 563 */ 564 u32 tmp, lines = 7; 565 566 val |= TGL_EDP_PSR2_BLOCK_COUNT_NUM_2; 567 568 tmp = map[lines - TGL_EDP_PSR2_IO_BUFFER_WAKE_MIN_LINES]; 569 tmp = tmp << TGL_EDP_PSR2_IO_BUFFER_WAKE_SHIFT; 570 val |= tmp; 571 572 tmp = map[lines - TGL_EDP_PSR2_FAST_WAKE_MIN_LINES]; 573 tmp = tmp << TGL_EDP_PSR2_FAST_WAKE_MIN_SHIFT; 574 val |= tmp; 575 } else if (DISPLAY_VER(dev_priv) >= 12) { 576 /* 577 * TODO: 7 lines of IO_BUFFER_WAKE and FAST_WAKE are default 578 * values from BSpec. In order to setting an optimal power 579 * consumption, lower than 4k resoluition mode needs to decrese 580 * IO_BUFFER_WAKE and FAST_WAKE. And higher than 4K resolution 581 * mode needs to increase IO_BUFFER_WAKE and FAST_WAKE. 582 */ 583 val |= TGL_EDP_PSR2_BLOCK_COUNT_NUM_2; 584 val |= TGL_EDP_PSR2_IO_BUFFER_WAKE(7); 585 val |= TGL_EDP_PSR2_FAST_WAKE(7); 586 } else if (DISPLAY_VER(dev_priv) >= 9) { 587 val |= EDP_PSR2_IO_BUFFER_WAKE(7); 588 val |= EDP_PSR2_FAST_WAKE(7); 589 } 590 591 if (intel_dp->psr.req_psr2_sdp_prior_scanline) 592 val |= EDP_PSR2_SU_SDP_SCANLINE; 593 594 if (intel_dp->psr.psr2_sel_fetch_enabled) { 595 /* WA 1408330847 */ 596 if (IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_A0) || 597 IS_RKL_REVID(dev_priv, RKL_REVID_A0, RKL_REVID_A0)) 598 intel_de_rmw(dev_priv, CHICKEN_PAR1_1, 599 DIS_RAM_BYPASS_PSR2_MAN_TRACK, 600 DIS_RAM_BYPASS_PSR2_MAN_TRACK); 601 602 intel_de_write(dev_priv, 603 PSR2_MAN_TRK_CTL(intel_dp->psr.transcoder), 604 PSR2_MAN_TRK_CTL_ENABLE); 605 } else if (HAS_PSR2_SEL_FETCH(dev_priv)) { 606 intel_de_write(dev_priv, 607 PSR2_MAN_TRK_CTL(intel_dp->psr.transcoder), 0); 608 } 609 610 /* 611 * PSR2 HW is incorrectly using EDP_PSR_TP1_TP3_SEL and BSpec is 612 * recommending keep this bit unset while PSR2 is enabled. 613 */ 614 intel_de_write(dev_priv, EDP_PSR_CTL(intel_dp->psr.transcoder), 0); 615 616 intel_de_write(dev_priv, EDP_PSR2_CTL(intel_dp->psr.transcoder), val); 617 } 618 619 static bool 620 transcoder_has_psr2(struct drm_i915_private *dev_priv, enum transcoder trans) 621 { 622 if (DISPLAY_VER(dev_priv) < 9) 623 return false; 624 else if (DISPLAY_VER(dev_priv) >= 12) 625 return trans == TRANSCODER_A; 626 else 627 return trans == TRANSCODER_EDP; 628 } 629 630 static u32 intel_get_frame_time_us(const struct intel_crtc_state *cstate) 631 { 632 if (!cstate || !cstate->hw.active) 633 return 0; 634 635 return DIV_ROUND_UP(1000 * 1000, 636 drm_mode_vrefresh(&cstate->hw.adjusted_mode)); 637 } 638 639 static void psr2_program_idle_frames(struct intel_dp *intel_dp, 640 u32 idle_frames) 641 { 642 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 643 u32 val; 644 645 idle_frames <<= EDP_PSR2_IDLE_FRAME_SHIFT; 646 val = intel_de_read(dev_priv, EDP_PSR2_CTL(intel_dp->psr.transcoder)); 647 val &= ~EDP_PSR2_IDLE_FRAME_MASK; 648 val |= idle_frames; 649 intel_de_write(dev_priv, EDP_PSR2_CTL(intel_dp->psr.transcoder), val); 650 } 651 652 static void tgl_psr2_enable_dc3co(struct intel_dp *intel_dp) 653 { 654 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 655 656 psr2_program_idle_frames(intel_dp, 0); 657 intel_display_power_set_target_dc_state(dev_priv, DC_STATE_EN_DC3CO); 658 } 659 660 static void tgl_psr2_disable_dc3co(struct intel_dp *intel_dp) 661 { 662 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 663 664 intel_display_power_set_target_dc_state(dev_priv, DC_STATE_EN_UPTO_DC6); 665 psr2_program_idle_frames(intel_dp, psr_compute_idle_frames(intel_dp)); 666 } 667 668 static void tgl_dc3co_disable_work(struct work_struct *work) 669 { 670 struct intel_dp *intel_dp = 671 container_of(work, typeof(*intel_dp), psr.dc3co_work.work); 672 673 mutex_lock(&intel_dp->psr.lock); 674 /* If delayed work is pending, it is not idle */ 675 if (delayed_work_pending(&intel_dp->psr.dc3co_work)) 676 goto unlock; 677 678 tgl_psr2_disable_dc3co(intel_dp); 679 unlock: 680 mutex_unlock(&intel_dp->psr.lock); 681 } 682 683 static void tgl_disallow_dc3co_on_psr2_exit(struct intel_dp *intel_dp) 684 { 685 if (!intel_dp->psr.dc3co_exitline) 686 return; 687 688 cancel_delayed_work(&intel_dp->psr.dc3co_work); 689 /* Before PSR2 exit disallow dc3co*/ 690 tgl_psr2_disable_dc3co(intel_dp); 691 } 692 693 static bool 694 dc3co_is_pipe_port_compatible(struct intel_dp *intel_dp, 695 struct intel_crtc_state *crtc_state) 696 { 697 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 698 enum pipe pipe = to_intel_crtc(crtc_state->uapi.crtc)->pipe; 699 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 700 enum port port = dig_port->base.port; 701 702 if (IS_ALDERLAKE_P(dev_priv)) 703 return pipe <= PIPE_B && port <= PORT_B; 704 else 705 return pipe == PIPE_A && port == PORT_A; 706 } 707 708 static void 709 tgl_dc3co_exitline_compute_config(struct intel_dp *intel_dp, 710 struct intel_crtc_state *crtc_state) 711 { 712 const u32 crtc_vdisplay = crtc_state->uapi.adjusted_mode.crtc_vdisplay; 713 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 714 u32 exit_scanlines; 715 716 /* 717 * FIXME: Due to the changed sequence of activating/deactivating DC3CO, 718 * disable DC3CO until the changed dc3co activating/deactivating sequence 719 * is applied. B.Specs:49196 720 */ 721 return; 722 723 /* 724 * DMC's DC3CO exit mechanism has an issue with Selective Fecth 725 * TODO: when the issue is addressed, this restriction should be removed. 726 */ 727 if (crtc_state->enable_psr2_sel_fetch) 728 return; 729 730 if (!(dev_priv->dmc.allowed_dc_mask & DC_STATE_EN_DC3CO)) 731 return; 732 733 if (!dc3co_is_pipe_port_compatible(intel_dp, crtc_state)) 734 return; 735 736 /* Wa_16011303918:adlp */ 737 if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_A0)) 738 return; 739 740 /* 741 * DC3CO Exit time 200us B.Spec 49196 742 * PSR2 transcoder Early Exit scanlines = ROUNDUP(200 / line time) + 1 743 */ 744 exit_scanlines = 745 intel_usecs_to_scanlines(&crtc_state->uapi.adjusted_mode, 200) + 1; 746 747 if (drm_WARN_ON(&dev_priv->drm, exit_scanlines > crtc_vdisplay)) 748 return; 749 750 crtc_state->dc3co_exitline = crtc_vdisplay - exit_scanlines; 751 } 752 753 static bool intel_psr2_sel_fetch_config_valid(struct intel_dp *intel_dp, 754 struct intel_crtc_state *crtc_state) 755 { 756 struct intel_atomic_state *state = to_intel_atomic_state(crtc_state->uapi.state); 757 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 758 struct intel_plane_state *plane_state; 759 struct intel_plane *plane; 760 int i; 761 762 if (!dev_priv->params.enable_psr2_sel_fetch && 763 intel_dp->psr.debug != I915_PSR_DEBUG_ENABLE_SEL_FETCH) { 764 drm_dbg_kms(&dev_priv->drm, 765 "PSR2 sel fetch not enabled, disabled by parameter\n"); 766 return false; 767 } 768 769 if (crtc_state->uapi.async_flip) { 770 drm_dbg_kms(&dev_priv->drm, 771 "PSR2 sel fetch not enabled, async flip enabled\n"); 772 return false; 773 } 774 775 for_each_new_intel_plane_in_state(state, plane, plane_state, i) { 776 if (plane_state->uapi.rotation != DRM_MODE_ROTATE_0) { 777 drm_dbg_kms(&dev_priv->drm, 778 "PSR2 sel fetch not enabled, plane rotated\n"); 779 return false; 780 } 781 } 782 783 /* Wa_14010254185 Wa_14010103792 */ 784 if (IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B1)) { 785 drm_dbg_kms(&dev_priv->drm, 786 "PSR2 sel fetch not enabled, missing the implementation of WAs\n"); 787 return false; 788 } 789 790 return crtc_state->enable_psr2_sel_fetch = true; 791 } 792 793 static bool psr2_granularity_check(struct intel_dp *intel_dp, 794 struct intel_crtc_state *crtc_state) 795 { 796 const int crtc_hdisplay = crtc_state->hw.adjusted_mode.crtc_hdisplay; 797 const int crtc_vdisplay = crtc_state->hw.adjusted_mode.crtc_vdisplay; 798 u16 y_granularity = 0; 799 800 /* PSR2 HW only send full lines so we only need to validate the width */ 801 if (crtc_hdisplay % intel_dp->psr.su_w_granularity) 802 return false; 803 804 if (crtc_vdisplay % intel_dp->psr.su_y_granularity) 805 return false; 806 807 /* HW tracking is only aligned to 4 lines */ 808 if (!crtc_state->enable_psr2_sel_fetch) 809 return intel_dp->psr.su_y_granularity == 4; 810 811 /* 812 * For SW tracking we can adjust the y to match sink requirement if 813 * multiple of 4 814 */ 815 if (intel_dp->psr.su_y_granularity <= 2) 816 y_granularity = 4; 817 else if ((intel_dp->psr.su_y_granularity % 4) == 0) 818 y_granularity = intel_dp->psr.su_y_granularity; 819 820 if (y_granularity == 0 || crtc_vdisplay % y_granularity) 821 return false; 822 823 crtc_state->su_y_granularity = y_granularity; 824 return true; 825 } 826 827 static bool _compute_psr2_sdp_prior_scanline_indication(struct intel_dp *intel_dp, 828 struct intel_crtc_state *crtc_state) 829 { 830 const struct drm_display_mode *adjusted_mode = &crtc_state->uapi.adjusted_mode; 831 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 832 u32 hblank_total, hblank_ns, req_ns; 833 834 hblank_total = adjusted_mode->crtc_hblank_end - adjusted_mode->crtc_hblank_start; 835 hblank_ns = div_u64(1000000ULL * hblank_total, adjusted_mode->crtc_clock); 836 837 /* From spec: (72 / number of lanes) * 1000 / symbol clock frequency MHz */ 838 req_ns = (72 / crtc_state->lane_count) * 1000 / (crtc_state->port_clock / 1000); 839 840 if ((hblank_ns - req_ns) > 100) 841 return true; 842 843 if (DISPLAY_VER(dev_priv) < 13 || intel_dp->edp_dpcd[0] < DP_EDP_14b) 844 return false; 845 846 crtc_state->req_psr2_sdp_prior_scanline = true; 847 return true; 848 } 849 850 static bool intel_psr2_config_valid(struct intel_dp *intel_dp, 851 struct intel_crtc_state *crtc_state) 852 { 853 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 854 int crtc_hdisplay = crtc_state->hw.adjusted_mode.crtc_hdisplay; 855 int crtc_vdisplay = crtc_state->hw.adjusted_mode.crtc_vdisplay; 856 int psr_max_h = 0, psr_max_v = 0, max_bpp = 0; 857 858 if (!intel_dp->psr.sink_psr2_support) 859 return false; 860 861 /* JSL and EHL only supports eDP 1.3 */ 862 if (IS_JSL_EHL(dev_priv)) { 863 drm_dbg_kms(&dev_priv->drm, "PSR2 not supported by phy\n"); 864 return false; 865 } 866 867 /* Wa_16011181250 */ 868 if (IS_ROCKETLAKE(dev_priv) || IS_ALDERLAKE_S(dev_priv)) { 869 drm_dbg_kms(&dev_priv->drm, "PSR2 is defeatured for this platform\n"); 870 return false; 871 } 872 873 /* 874 * We are missing the implementation of some workarounds to enabled PSR2 875 * in Alderlake_P, until ready PSR2 should be kept disabled. 876 */ 877 if (IS_ALDERLAKE_P(dev_priv)) { 878 drm_dbg_kms(&dev_priv->drm, "PSR2 is missing the implementation of workarounds\n"); 879 return false; 880 } 881 882 if (!transcoder_has_psr2(dev_priv, crtc_state->cpu_transcoder)) { 883 drm_dbg_kms(&dev_priv->drm, 884 "PSR2 not supported in transcoder %s\n", 885 transcoder_name(crtc_state->cpu_transcoder)); 886 return false; 887 } 888 889 if (!psr2_global_enabled(intel_dp)) { 890 drm_dbg_kms(&dev_priv->drm, "PSR2 disabled by flag\n"); 891 return false; 892 } 893 894 /* 895 * DSC and PSR2 cannot be enabled simultaneously. If a requested 896 * resolution requires DSC to be enabled, priority is given to DSC 897 * over PSR2. 898 */ 899 if (crtc_state->dsc.compression_enable) { 900 drm_dbg_kms(&dev_priv->drm, 901 "PSR2 cannot be enabled since DSC is enabled\n"); 902 return false; 903 } 904 905 if (crtc_state->crc_enabled) { 906 drm_dbg_kms(&dev_priv->drm, 907 "PSR2 not enabled because it would inhibit pipe CRC calculation\n"); 908 return false; 909 } 910 911 if (DISPLAY_VER(dev_priv) >= 12) { 912 psr_max_h = 5120; 913 psr_max_v = 3200; 914 max_bpp = 30; 915 } else if (DISPLAY_VER(dev_priv) >= 10) { 916 psr_max_h = 4096; 917 psr_max_v = 2304; 918 max_bpp = 24; 919 } else if (DISPLAY_VER(dev_priv) == 9) { 920 psr_max_h = 3640; 921 psr_max_v = 2304; 922 max_bpp = 24; 923 } 924 925 if (crtc_state->pipe_bpp > max_bpp) { 926 drm_dbg_kms(&dev_priv->drm, 927 "PSR2 not enabled, pipe bpp %d > max supported %d\n", 928 crtc_state->pipe_bpp, max_bpp); 929 return false; 930 } 931 932 if (HAS_PSR2_SEL_FETCH(dev_priv)) { 933 if (!intel_psr2_sel_fetch_config_valid(intel_dp, crtc_state) && 934 !HAS_PSR_HW_TRACKING(dev_priv)) { 935 drm_dbg_kms(&dev_priv->drm, 936 "PSR2 not enabled, selective fetch not valid and no HW tracking available\n"); 937 return false; 938 } 939 } 940 941 /* Wa_2209313811 */ 942 if (!crtc_state->enable_psr2_sel_fetch && 943 IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B1)) { 944 drm_dbg_kms(&dev_priv->drm, "PSR2 HW tracking is not supported this Display stepping\n"); 945 return false; 946 } 947 948 if (!psr2_granularity_check(intel_dp, crtc_state)) { 949 drm_dbg_kms(&dev_priv->drm, "PSR2 not enabled, SU granularity not compatible\n"); 950 return false; 951 } 952 953 if (!crtc_state->enable_psr2_sel_fetch && 954 (crtc_hdisplay > psr_max_h || crtc_vdisplay > psr_max_v)) { 955 drm_dbg_kms(&dev_priv->drm, 956 "PSR2 not enabled, resolution %dx%d > max supported %dx%d\n", 957 crtc_hdisplay, crtc_vdisplay, 958 psr_max_h, psr_max_v); 959 return false; 960 } 961 962 if (!_compute_psr2_sdp_prior_scanline_indication(intel_dp, crtc_state)) { 963 drm_dbg_kms(&dev_priv->drm, 964 "PSR2 not enabled, PSR2 SDP indication do not fit in hblank\n"); 965 return false; 966 } 967 968 /* Wa_16011303918:adlp */ 969 if (crtc_state->vrr.enable && 970 IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_A0)) { 971 drm_dbg_kms(&dev_priv->drm, 972 "PSR2 not enabled, not compatible with HW stepping + VRR\n"); 973 return false; 974 } 975 976 tgl_dc3co_exitline_compute_config(intel_dp, crtc_state); 977 return true; 978 } 979 980 void intel_psr_compute_config(struct intel_dp *intel_dp, 981 struct intel_crtc_state *crtc_state) 982 { 983 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 984 const struct drm_display_mode *adjusted_mode = 985 &crtc_state->hw.adjusted_mode; 986 int psr_setup_time; 987 988 /* 989 * Current PSR panels dont work reliably with VRR enabled 990 * So if VRR is enabled, do not enable PSR. 991 */ 992 if (crtc_state->vrr.enable) 993 return; 994 995 if (!CAN_PSR(intel_dp)) 996 return; 997 998 if (!psr_global_enabled(intel_dp)) { 999 drm_dbg_kms(&dev_priv->drm, "PSR disabled by flag\n"); 1000 return; 1001 } 1002 1003 if (intel_dp->psr.sink_not_reliable) { 1004 drm_dbg_kms(&dev_priv->drm, 1005 "PSR sink implementation is not reliable\n"); 1006 return; 1007 } 1008 1009 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { 1010 drm_dbg_kms(&dev_priv->drm, 1011 "PSR condition failed: Interlaced mode enabled\n"); 1012 return; 1013 } 1014 1015 psr_setup_time = drm_dp_psr_setup_time(intel_dp->psr_dpcd); 1016 if (psr_setup_time < 0) { 1017 drm_dbg_kms(&dev_priv->drm, 1018 "PSR condition failed: Invalid PSR setup time (0x%02x)\n", 1019 intel_dp->psr_dpcd[1]); 1020 return; 1021 } 1022 1023 if (intel_usecs_to_scanlines(adjusted_mode, psr_setup_time) > 1024 adjusted_mode->crtc_vtotal - adjusted_mode->crtc_vdisplay - 1) { 1025 drm_dbg_kms(&dev_priv->drm, 1026 "PSR condition failed: PSR setup time (%d us) too long\n", 1027 psr_setup_time); 1028 return; 1029 } 1030 1031 crtc_state->has_psr = true; 1032 crtc_state->has_psr2 = intel_psr2_config_valid(intel_dp, crtc_state); 1033 crtc_state->infoframes.enable |= intel_hdmi_infoframe_enable(DP_SDP_VSC); 1034 } 1035 1036 void intel_psr_get_config(struct intel_encoder *encoder, 1037 struct intel_crtc_state *pipe_config) 1038 { 1039 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1040 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 1041 struct intel_dp *intel_dp; 1042 u32 val; 1043 1044 if (!dig_port) 1045 return; 1046 1047 intel_dp = &dig_port->dp; 1048 if (!CAN_PSR(intel_dp)) 1049 return; 1050 1051 mutex_lock(&intel_dp->psr.lock); 1052 if (!intel_dp->psr.enabled) 1053 goto unlock; 1054 1055 /* 1056 * Not possible to read EDP_PSR/PSR2_CTL registers as it is 1057 * enabled/disabled because of frontbuffer tracking and others. 1058 */ 1059 pipe_config->has_psr = true; 1060 pipe_config->has_psr2 = intel_dp->psr.psr2_enabled; 1061 pipe_config->infoframes.enable |= intel_hdmi_infoframe_enable(DP_SDP_VSC); 1062 1063 if (!intel_dp->psr.psr2_enabled) 1064 goto unlock; 1065 1066 if (HAS_PSR2_SEL_FETCH(dev_priv)) { 1067 val = intel_de_read(dev_priv, PSR2_MAN_TRK_CTL(intel_dp->psr.transcoder)); 1068 if (val & PSR2_MAN_TRK_CTL_ENABLE) 1069 pipe_config->enable_psr2_sel_fetch = true; 1070 } 1071 1072 if (DISPLAY_VER(dev_priv) >= 12) { 1073 val = intel_de_read(dev_priv, EXITLINE(intel_dp->psr.transcoder)); 1074 val &= EXITLINE_MASK; 1075 pipe_config->dc3co_exitline = val; 1076 } 1077 unlock: 1078 mutex_unlock(&intel_dp->psr.lock); 1079 } 1080 1081 static void intel_psr_activate(struct intel_dp *intel_dp) 1082 { 1083 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 1084 enum transcoder transcoder = intel_dp->psr.transcoder; 1085 1086 if (transcoder_has_psr2(dev_priv, transcoder)) 1087 drm_WARN_ON(&dev_priv->drm, 1088 intel_de_read(dev_priv, EDP_PSR2_CTL(transcoder)) & EDP_PSR2_ENABLE); 1089 1090 drm_WARN_ON(&dev_priv->drm, 1091 intel_de_read(dev_priv, EDP_PSR_CTL(transcoder)) & EDP_PSR_ENABLE); 1092 drm_WARN_ON(&dev_priv->drm, intel_dp->psr.active); 1093 lockdep_assert_held(&intel_dp->psr.lock); 1094 1095 /* psr1 and psr2 are mutually exclusive.*/ 1096 if (intel_dp->psr.psr2_enabled) 1097 hsw_activate_psr2(intel_dp); 1098 else 1099 hsw_activate_psr1(intel_dp); 1100 1101 intel_dp->psr.active = true; 1102 } 1103 1104 static void intel_psr_enable_source(struct intel_dp *intel_dp) 1105 { 1106 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 1107 enum transcoder cpu_transcoder = intel_dp->psr.transcoder; 1108 u32 mask; 1109 1110 /* Only HSW and BDW have PSR AUX registers that need to be setup. SKL+ 1111 * use hardcoded values PSR AUX transactions 1112 */ 1113 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) 1114 hsw_psr_setup_aux(intel_dp); 1115 1116 if (intel_dp->psr.psr2_enabled && DISPLAY_VER(dev_priv) == 9) { 1117 i915_reg_t reg = CHICKEN_TRANS(cpu_transcoder); 1118 u32 chicken = intel_de_read(dev_priv, reg); 1119 1120 chicken |= PSR2_VSC_ENABLE_PROG_HEADER | 1121 PSR2_ADD_VERTICAL_LINE_COUNT; 1122 intel_de_write(dev_priv, reg, chicken); 1123 } 1124 1125 /* 1126 * Per Spec: Avoid continuous PSR exit by masking MEMUP and HPD also 1127 * mask LPSP to avoid dependency on other drivers that might block 1128 * runtime_pm besides preventing other hw tracking issues now we 1129 * can rely on frontbuffer tracking. 1130 */ 1131 mask = EDP_PSR_DEBUG_MASK_MEMUP | 1132 EDP_PSR_DEBUG_MASK_HPD | 1133 EDP_PSR_DEBUG_MASK_LPSP | 1134 EDP_PSR_DEBUG_MASK_MAX_SLEEP; 1135 1136 if (DISPLAY_VER(dev_priv) < 11) 1137 mask |= EDP_PSR_DEBUG_MASK_DISP_REG_WRITE; 1138 1139 intel_de_write(dev_priv, EDP_PSR_DEBUG(intel_dp->psr.transcoder), 1140 mask); 1141 1142 psr_irq_control(intel_dp); 1143 1144 if (intel_dp->psr.dc3co_exitline) { 1145 u32 val; 1146 1147 /* 1148 * TODO: if future platforms supports DC3CO in more than one 1149 * transcoder, EXITLINE will need to be unset when disabling PSR 1150 */ 1151 val = intel_de_read(dev_priv, EXITLINE(cpu_transcoder)); 1152 val &= ~EXITLINE_MASK; 1153 val |= intel_dp->psr.dc3co_exitline << EXITLINE_SHIFT; 1154 val |= EXITLINE_ENABLE; 1155 intel_de_write(dev_priv, EXITLINE(cpu_transcoder), val); 1156 } 1157 1158 if (HAS_PSR_HW_TRACKING(dev_priv) && HAS_PSR2_SEL_FETCH(dev_priv)) 1159 intel_de_rmw(dev_priv, CHICKEN_PAR1_1, IGNORE_PSR2_HW_TRACKING, 1160 intel_dp->psr.psr2_sel_fetch_enabled ? 1161 IGNORE_PSR2_HW_TRACKING : 0); 1162 1163 /* Wa_16011168373:adlp */ 1164 if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_A0) && 1165 intel_dp->psr.psr2_enabled) 1166 intel_de_rmw(dev_priv, 1167 TRANS_SET_CONTEXT_LATENCY(intel_dp->psr.transcoder), 1168 TRANS_SET_CONTEXT_LATENCY_MASK, 1169 TRANS_SET_CONTEXT_LATENCY_VALUE(1)); 1170 } 1171 1172 static bool psr_interrupt_error_check(struct intel_dp *intel_dp) 1173 { 1174 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 1175 u32 val; 1176 1177 /* 1178 * If a PSR error happened and the driver is reloaded, the EDP_PSR_IIR 1179 * will still keep the error set even after the reset done in the 1180 * irq_preinstall and irq_uninstall hooks. 1181 * And enabling in this situation cause the screen to freeze in the 1182 * first time that PSR HW tries to activate so lets keep PSR disabled 1183 * to avoid any rendering problems. 1184 */ 1185 if (DISPLAY_VER(dev_priv) >= 12) { 1186 val = intel_de_read(dev_priv, 1187 TRANS_PSR_IIR(intel_dp->psr.transcoder)); 1188 val &= EDP_PSR_ERROR(0); 1189 } else { 1190 val = intel_de_read(dev_priv, EDP_PSR_IIR); 1191 val &= EDP_PSR_ERROR(intel_dp->psr.transcoder); 1192 } 1193 if (val) { 1194 intel_dp->psr.sink_not_reliable = true; 1195 drm_dbg_kms(&dev_priv->drm, 1196 "PSR interruption error set, not enabling PSR\n"); 1197 return false; 1198 } 1199 1200 return true; 1201 } 1202 1203 static void intel_psr_enable_locked(struct intel_dp *intel_dp, 1204 const struct intel_crtc_state *crtc_state, 1205 const struct drm_connector_state *conn_state) 1206 { 1207 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 1208 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 1209 struct intel_encoder *encoder = &dig_port->base; 1210 u32 val; 1211 1212 drm_WARN_ON(&dev_priv->drm, intel_dp->psr.enabled); 1213 1214 intel_dp->psr.psr2_enabled = crtc_state->has_psr2; 1215 intel_dp->psr.busy_frontbuffer_bits = 0; 1216 intel_dp->psr.pipe = to_intel_crtc(crtc_state->uapi.crtc)->pipe; 1217 intel_dp->psr.transcoder = crtc_state->cpu_transcoder; 1218 /* DC5/DC6 requires at least 6 idle frames */ 1219 val = usecs_to_jiffies(intel_get_frame_time_us(crtc_state) * 6); 1220 intel_dp->psr.dc3co_exit_delay = val; 1221 intel_dp->psr.dc3co_exitline = crtc_state->dc3co_exitline; 1222 intel_dp->psr.psr2_sel_fetch_enabled = crtc_state->enable_psr2_sel_fetch; 1223 intel_dp->psr.req_psr2_sdp_prior_scanline = 1224 crtc_state->req_psr2_sdp_prior_scanline; 1225 1226 if (!psr_interrupt_error_check(intel_dp)) 1227 return; 1228 1229 drm_dbg_kms(&dev_priv->drm, "Enabling PSR%s\n", 1230 intel_dp->psr.psr2_enabled ? "2" : "1"); 1231 intel_dp_compute_psr_vsc_sdp(intel_dp, crtc_state, conn_state, 1232 &intel_dp->psr.vsc); 1233 intel_write_dp_vsc_sdp(encoder, crtc_state, &intel_dp->psr.vsc); 1234 intel_psr_enable_sink(intel_dp); 1235 intel_psr_enable_source(intel_dp); 1236 intel_dp->psr.enabled = true; 1237 intel_dp->psr.paused = false; 1238 1239 intel_psr_activate(intel_dp); 1240 } 1241 1242 /** 1243 * intel_psr_enable - Enable PSR 1244 * @intel_dp: Intel DP 1245 * @crtc_state: new CRTC state 1246 * @conn_state: new CONNECTOR state 1247 * 1248 * This function can only be called after the pipe is fully trained and enabled. 1249 */ 1250 void intel_psr_enable(struct intel_dp *intel_dp, 1251 const struct intel_crtc_state *crtc_state, 1252 const struct drm_connector_state *conn_state) 1253 { 1254 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 1255 1256 if (!CAN_PSR(intel_dp)) 1257 return; 1258 1259 if (!crtc_state->has_psr) 1260 return; 1261 1262 drm_WARN_ON(&dev_priv->drm, dev_priv->drrs.dp); 1263 1264 mutex_lock(&intel_dp->psr.lock); 1265 intel_psr_enable_locked(intel_dp, crtc_state, conn_state); 1266 mutex_unlock(&intel_dp->psr.lock); 1267 } 1268 1269 static void intel_psr_exit(struct intel_dp *intel_dp) 1270 { 1271 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 1272 u32 val; 1273 1274 if (!intel_dp->psr.active) { 1275 if (transcoder_has_psr2(dev_priv, intel_dp->psr.transcoder)) { 1276 val = intel_de_read(dev_priv, 1277 EDP_PSR2_CTL(intel_dp->psr.transcoder)); 1278 drm_WARN_ON(&dev_priv->drm, val & EDP_PSR2_ENABLE); 1279 } 1280 1281 val = intel_de_read(dev_priv, 1282 EDP_PSR_CTL(intel_dp->psr.transcoder)); 1283 drm_WARN_ON(&dev_priv->drm, val & EDP_PSR_ENABLE); 1284 1285 return; 1286 } 1287 1288 if (intel_dp->psr.psr2_enabled) { 1289 tgl_disallow_dc3co_on_psr2_exit(intel_dp); 1290 val = intel_de_read(dev_priv, 1291 EDP_PSR2_CTL(intel_dp->psr.transcoder)); 1292 drm_WARN_ON(&dev_priv->drm, !(val & EDP_PSR2_ENABLE)); 1293 val &= ~EDP_PSR2_ENABLE; 1294 intel_de_write(dev_priv, 1295 EDP_PSR2_CTL(intel_dp->psr.transcoder), val); 1296 } else { 1297 val = intel_de_read(dev_priv, 1298 EDP_PSR_CTL(intel_dp->psr.transcoder)); 1299 drm_WARN_ON(&dev_priv->drm, !(val & EDP_PSR_ENABLE)); 1300 val &= ~EDP_PSR_ENABLE; 1301 intel_de_write(dev_priv, 1302 EDP_PSR_CTL(intel_dp->psr.transcoder), val); 1303 } 1304 intel_dp->psr.active = false; 1305 } 1306 1307 static void intel_psr_wait_exit_locked(struct intel_dp *intel_dp) 1308 { 1309 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 1310 i915_reg_t psr_status; 1311 u32 psr_status_mask; 1312 1313 if (intel_dp->psr.psr2_enabled) { 1314 psr_status = EDP_PSR2_STATUS(intel_dp->psr.transcoder); 1315 psr_status_mask = EDP_PSR2_STATUS_STATE_MASK; 1316 } else { 1317 psr_status = EDP_PSR_STATUS(intel_dp->psr.transcoder); 1318 psr_status_mask = EDP_PSR_STATUS_STATE_MASK; 1319 } 1320 1321 /* Wait till PSR is idle */ 1322 if (intel_de_wait_for_clear(dev_priv, psr_status, 1323 psr_status_mask, 2000)) 1324 drm_err(&dev_priv->drm, "Timed out waiting PSR idle state\n"); 1325 } 1326 1327 static void intel_psr_disable_locked(struct intel_dp *intel_dp) 1328 { 1329 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 1330 1331 lockdep_assert_held(&intel_dp->psr.lock); 1332 1333 if (!intel_dp->psr.enabled) 1334 return; 1335 1336 drm_dbg_kms(&dev_priv->drm, "Disabling PSR%s\n", 1337 intel_dp->psr.psr2_enabled ? "2" : "1"); 1338 1339 intel_psr_exit(intel_dp); 1340 intel_psr_wait_exit_locked(intel_dp); 1341 1342 /* WA 1408330847 */ 1343 if (intel_dp->psr.psr2_sel_fetch_enabled && 1344 (IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_A0) || 1345 IS_RKL_REVID(dev_priv, RKL_REVID_A0, RKL_REVID_A0))) 1346 intel_de_rmw(dev_priv, CHICKEN_PAR1_1, 1347 DIS_RAM_BYPASS_PSR2_MAN_TRACK, 0); 1348 1349 /* Wa_16011168373:adlp */ 1350 if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_A0) && 1351 intel_dp->psr.psr2_enabled) 1352 intel_de_rmw(dev_priv, 1353 TRANS_SET_CONTEXT_LATENCY(intel_dp->psr.transcoder), 1354 TRANS_SET_CONTEXT_LATENCY_MASK, 0); 1355 1356 /* Disable PSR on Sink */ 1357 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, 0); 1358 1359 if (intel_dp->psr.psr2_enabled) 1360 drm_dp_dpcd_writeb(&intel_dp->aux, DP_RECEIVER_ALPM_CONFIG, 0); 1361 1362 intel_dp->psr.enabled = false; 1363 } 1364 1365 /** 1366 * intel_psr_disable - Disable PSR 1367 * @intel_dp: Intel DP 1368 * @old_crtc_state: old CRTC state 1369 * 1370 * This function needs to be called before disabling pipe. 1371 */ 1372 void intel_psr_disable(struct intel_dp *intel_dp, 1373 const struct intel_crtc_state *old_crtc_state) 1374 { 1375 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 1376 1377 if (!old_crtc_state->has_psr) 1378 return; 1379 1380 if (drm_WARN_ON(&dev_priv->drm, !CAN_PSR(intel_dp))) 1381 return; 1382 1383 mutex_lock(&intel_dp->psr.lock); 1384 1385 intel_psr_disable_locked(intel_dp); 1386 1387 mutex_unlock(&intel_dp->psr.lock); 1388 cancel_work_sync(&intel_dp->psr.work); 1389 cancel_delayed_work_sync(&intel_dp->psr.dc3co_work); 1390 } 1391 1392 /** 1393 * intel_psr_pause - Pause PSR 1394 * @intel_dp: Intel DP 1395 * 1396 * This function need to be called after enabling psr. 1397 */ 1398 void intel_psr_pause(struct intel_dp *intel_dp) 1399 { 1400 struct intel_psr *psr = &intel_dp->psr; 1401 1402 if (!CAN_PSR(intel_dp)) 1403 return; 1404 1405 mutex_lock(&psr->lock); 1406 1407 if (!psr->enabled) { 1408 mutex_unlock(&psr->lock); 1409 return; 1410 } 1411 1412 intel_psr_exit(intel_dp); 1413 intel_psr_wait_exit_locked(intel_dp); 1414 psr->paused = true; 1415 1416 mutex_unlock(&psr->lock); 1417 1418 cancel_work_sync(&psr->work); 1419 cancel_delayed_work_sync(&psr->dc3co_work); 1420 } 1421 1422 /** 1423 * intel_psr_resume - Resume PSR 1424 * @intel_dp: Intel DP 1425 * 1426 * This function need to be called after pausing psr. 1427 */ 1428 void intel_psr_resume(struct intel_dp *intel_dp) 1429 { 1430 struct intel_psr *psr = &intel_dp->psr; 1431 1432 if (!CAN_PSR(intel_dp)) 1433 return; 1434 1435 mutex_lock(&psr->lock); 1436 1437 if (!psr->paused) 1438 goto unlock; 1439 1440 psr->paused = false; 1441 intel_psr_activate(intel_dp); 1442 1443 unlock: 1444 mutex_unlock(&psr->lock); 1445 } 1446 1447 static void psr_force_hw_tracking_exit(struct intel_dp *intel_dp) 1448 { 1449 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 1450 1451 if (DISPLAY_VER(dev_priv) >= 9) 1452 /* 1453 * Display WA #0884: skl+ 1454 * This documented WA for bxt can be safely applied 1455 * broadly so we can force HW tracking to exit PSR 1456 * instead of disabling and re-enabling. 1457 * Workaround tells us to write 0 to CUR_SURFLIVE_A, 1458 * but it makes more sense write to the current active 1459 * pipe. 1460 */ 1461 intel_de_write(dev_priv, CURSURFLIVE(intel_dp->psr.pipe), 0); 1462 else 1463 /* 1464 * A write to CURSURFLIVE do not cause HW tracking to exit PSR 1465 * on older gens so doing the manual exit instead. 1466 */ 1467 intel_psr_exit(intel_dp); 1468 } 1469 1470 void intel_psr2_program_plane_sel_fetch(struct intel_plane *plane, 1471 const struct intel_crtc_state *crtc_state, 1472 const struct intel_plane_state *plane_state, 1473 int color_plane) 1474 { 1475 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 1476 enum pipe pipe = plane->pipe; 1477 const struct drm_rect *clip; 1478 u32 val, offset; 1479 int ret, x, y; 1480 1481 if (!crtc_state->enable_psr2_sel_fetch) 1482 return; 1483 1484 val = plane_state ? plane_state->ctl : 0; 1485 val &= plane->id == PLANE_CURSOR ? val : PLANE_SEL_FETCH_CTL_ENABLE; 1486 intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_CTL(pipe, plane->id), val); 1487 if (!val || plane->id == PLANE_CURSOR) 1488 return; 1489 1490 clip = &plane_state->psr2_sel_fetch_area; 1491 1492 val = (clip->y1 + plane_state->uapi.dst.y1) << 16; 1493 val |= plane_state->uapi.dst.x1; 1494 intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_POS(pipe, plane->id), val); 1495 1496 /* TODO: consider auxiliary surfaces */ 1497 x = plane_state->uapi.src.x1 >> 16; 1498 y = (plane_state->uapi.src.y1 >> 16) + clip->y1; 1499 ret = skl_calc_main_surface_offset(plane_state, &x, &y, &offset); 1500 if (ret) 1501 drm_warn_once(&dev_priv->drm, "skl_calc_main_surface_offset() returned %i\n", 1502 ret); 1503 val = y << 16 | x; 1504 intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_OFFSET(pipe, plane->id), 1505 val); 1506 1507 /* Sizes are 0 based */ 1508 val = (drm_rect_height(clip) - 1) << 16; 1509 val |= (drm_rect_width(&plane_state->uapi.src) >> 16) - 1; 1510 intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_SIZE(pipe, plane->id), val); 1511 } 1512 1513 void intel_psr2_program_trans_man_trk_ctl(const struct intel_crtc_state *crtc_state) 1514 { 1515 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 1516 1517 if (!HAS_PSR2_SEL_FETCH(dev_priv) || 1518 !crtc_state->enable_psr2_sel_fetch) 1519 return; 1520 1521 intel_de_write(dev_priv, PSR2_MAN_TRK_CTL(crtc_state->cpu_transcoder), 1522 crtc_state->psr2_man_track_ctl); 1523 } 1524 1525 static void psr2_man_trk_ctl_calc(struct intel_crtc_state *crtc_state, 1526 struct drm_rect *clip, bool full_update) 1527 { 1528 u32 val = PSR2_MAN_TRK_CTL_ENABLE; 1529 1530 if (full_update) { 1531 val |= PSR2_MAN_TRK_CTL_SF_SINGLE_FULL_FRAME; 1532 goto exit; 1533 } 1534 1535 if (clip->y1 == -1) 1536 goto exit; 1537 1538 drm_WARN_ON(crtc_state->uapi.crtc->dev, clip->y1 % 4 || clip->y2 % 4); 1539 1540 val |= PSR2_MAN_TRK_CTL_SF_PARTIAL_FRAME_UPDATE; 1541 val |= PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR(clip->y1 / 4 + 1); 1542 val |= PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR(clip->y2 / 4 + 1); 1543 exit: 1544 crtc_state->psr2_man_track_ctl = val; 1545 } 1546 1547 static void clip_area_update(struct drm_rect *overlap_damage_area, 1548 struct drm_rect *damage_area) 1549 { 1550 if (overlap_damage_area->y1 == -1) { 1551 overlap_damage_area->y1 = damage_area->y1; 1552 overlap_damage_area->y2 = damage_area->y2; 1553 return; 1554 } 1555 1556 if (damage_area->y1 < overlap_damage_area->y1) 1557 overlap_damage_area->y1 = damage_area->y1; 1558 1559 if (damage_area->y2 > overlap_damage_area->y2) 1560 overlap_damage_area->y2 = damage_area->y2; 1561 } 1562 1563 static void intel_psr2_sel_fetch_pipe_alignment(const struct intel_crtc_state *crtc_state, 1564 struct drm_rect *pipe_clip) 1565 { 1566 const u16 y_alignment = crtc_state->su_y_granularity; 1567 1568 pipe_clip->y1 -= pipe_clip->y1 % y_alignment; 1569 if (pipe_clip->y2 % y_alignment) 1570 pipe_clip->y2 = ((pipe_clip->y2 / y_alignment) + 1) * y_alignment; 1571 } 1572 1573 int intel_psr2_sel_fetch_update(struct intel_atomic_state *state, 1574 struct intel_crtc *crtc) 1575 { 1576 struct intel_crtc_state *crtc_state = intel_atomic_get_new_crtc_state(state, crtc); 1577 struct drm_rect pipe_clip = { .x1 = 0, .y1 = -1, .x2 = INT_MAX, .y2 = -1 }; 1578 struct intel_plane_state *new_plane_state, *old_plane_state; 1579 struct intel_plane *plane; 1580 bool full_update = false; 1581 int i, ret; 1582 1583 if (!crtc_state->enable_psr2_sel_fetch) 1584 return 0; 1585 1586 ret = drm_atomic_add_affected_planes(&state->base, &crtc->base); 1587 if (ret) 1588 return ret; 1589 1590 /* 1591 * Calculate minimal selective fetch area of each plane and calculate 1592 * the pipe damaged area. 1593 * In the next loop the plane selective fetch area will actually be set 1594 * using whole pipe damaged area. 1595 */ 1596 for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state, 1597 new_plane_state, i) { 1598 struct drm_rect src, damaged_area = { .y1 = -1 }; 1599 struct drm_mode_rect *damaged_clips; 1600 u32 num_clips, j; 1601 1602 if (new_plane_state->uapi.crtc != crtc_state->uapi.crtc) 1603 continue; 1604 1605 if (!new_plane_state->uapi.visible && 1606 !old_plane_state->uapi.visible) 1607 continue; 1608 1609 /* 1610 * TODO: Not clear how to handle planes with negative position, 1611 * also planes are not updated if they have a negative X 1612 * position so for now doing a full update in this cases 1613 */ 1614 if (new_plane_state->uapi.dst.y1 < 0 || 1615 new_plane_state->uapi.dst.x1 < 0) { 1616 full_update = true; 1617 break; 1618 } 1619 1620 num_clips = drm_plane_get_damage_clips_count(&new_plane_state->uapi); 1621 1622 /* 1623 * If visibility or plane moved, mark the whole plane area as 1624 * damaged as it needs to be complete redraw in the new and old 1625 * position. 1626 */ 1627 if (new_plane_state->uapi.visible != old_plane_state->uapi.visible || 1628 !drm_rect_equals(&new_plane_state->uapi.dst, 1629 &old_plane_state->uapi.dst)) { 1630 if (old_plane_state->uapi.visible) { 1631 damaged_area.y1 = old_plane_state->uapi.dst.y1; 1632 damaged_area.y2 = old_plane_state->uapi.dst.y2; 1633 clip_area_update(&pipe_clip, &damaged_area); 1634 } 1635 1636 if (new_plane_state->uapi.visible) { 1637 damaged_area.y1 = new_plane_state->uapi.dst.y1; 1638 damaged_area.y2 = new_plane_state->uapi.dst.y2; 1639 clip_area_update(&pipe_clip, &damaged_area); 1640 } 1641 continue; 1642 } else if (new_plane_state->uapi.alpha != old_plane_state->uapi.alpha || 1643 (!num_clips && 1644 new_plane_state->uapi.fb != old_plane_state->uapi.fb)) { 1645 /* 1646 * If the plane don't have damaged areas but the 1647 * framebuffer changed or alpha changed, mark the whole 1648 * plane area as damaged. 1649 */ 1650 damaged_area.y1 = new_plane_state->uapi.dst.y1; 1651 damaged_area.y2 = new_plane_state->uapi.dst.y2; 1652 clip_area_update(&pipe_clip, &damaged_area); 1653 continue; 1654 } 1655 1656 drm_rect_fp_to_int(&src, &new_plane_state->uapi.src); 1657 damaged_clips = drm_plane_get_damage_clips(&new_plane_state->uapi); 1658 1659 for (j = 0; j < num_clips; j++) { 1660 struct drm_rect clip; 1661 1662 clip.x1 = damaged_clips[j].x1; 1663 clip.y1 = damaged_clips[j].y1; 1664 clip.x2 = damaged_clips[j].x2; 1665 clip.y2 = damaged_clips[j].y2; 1666 if (drm_rect_intersect(&clip, &src)) 1667 clip_area_update(&damaged_area, &clip); 1668 } 1669 1670 if (damaged_area.y1 == -1) 1671 continue; 1672 1673 damaged_area.y1 += new_plane_state->uapi.dst.y1 - src.y1; 1674 damaged_area.y2 += new_plane_state->uapi.dst.y1 - src.y1; 1675 clip_area_update(&pipe_clip, &damaged_area); 1676 } 1677 1678 if (full_update) 1679 goto skip_sel_fetch_set_loop; 1680 1681 intel_psr2_sel_fetch_pipe_alignment(crtc_state, &pipe_clip); 1682 1683 /* 1684 * Now that we have the pipe damaged area check if it intersect with 1685 * every plane, if it does set the plane selective fetch area. 1686 */ 1687 for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state, 1688 new_plane_state, i) { 1689 struct drm_rect *sel_fetch_area, inter; 1690 1691 if (new_plane_state->uapi.crtc != crtc_state->uapi.crtc || 1692 !new_plane_state->uapi.visible) 1693 continue; 1694 1695 inter = pipe_clip; 1696 if (!drm_rect_intersect(&inter, &new_plane_state->uapi.dst)) 1697 continue; 1698 1699 sel_fetch_area = &new_plane_state->psr2_sel_fetch_area; 1700 sel_fetch_area->y1 = inter.y1 - new_plane_state->uapi.dst.y1; 1701 sel_fetch_area->y2 = inter.y2 - new_plane_state->uapi.dst.y1; 1702 } 1703 1704 skip_sel_fetch_set_loop: 1705 psr2_man_trk_ctl_calc(crtc_state, &pipe_clip, full_update); 1706 return 0; 1707 } 1708 1709 /** 1710 * intel_psr_update - Update PSR state 1711 * @intel_dp: Intel DP 1712 * @crtc_state: new CRTC state 1713 * @conn_state: new CONNECTOR state 1714 * 1715 * This functions will update PSR states, disabling, enabling or switching PSR 1716 * version when executing fastsets. For full modeset, intel_psr_disable() and 1717 * intel_psr_enable() should be called instead. 1718 */ 1719 void intel_psr_update(struct intel_dp *intel_dp, 1720 const struct intel_crtc_state *crtc_state, 1721 const struct drm_connector_state *conn_state) 1722 { 1723 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 1724 struct intel_psr *psr = &intel_dp->psr; 1725 bool enable, psr2_enable; 1726 1727 if (!CAN_PSR(intel_dp)) 1728 return; 1729 1730 mutex_lock(&intel_dp->psr.lock); 1731 1732 enable = crtc_state->has_psr; 1733 psr2_enable = crtc_state->has_psr2; 1734 1735 if (enable == psr->enabled && psr2_enable == psr->psr2_enabled && 1736 crtc_state->enable_psr2_sel_fetch == psr->psr2_sel_fetch_enabled) { 1737 /* Force a PSR exit when enabling CRC to avoid CRC timeouts */ 1738 if (crtc_state->crc_enabled && psr->enabled) 1739 psr_force_hw_tracking_exit(intel_dp); 1740 else if (DISPLAY_VER(dev_priv) < 9 && psr->enabled) { 1741 /* 1742 * Activate PSR again after a force exit when enabling 1743 * CRC in older gens 1744 */ 1745 if (!intel_dp->psr.active && 1746 !intel_dp->psr.busy_frontbuffer_bits) 1747 schedule_work(&intel_dp->psr.work); 1748 } 1749 1750 goto unlock; 1751 } 1752 1753 if (psr->enabled) 1754 intel_psr_disable_locked(intel_dp); 1755 1756 if (enable) 1757 intel_psr_enable_locked(intel_dp, crtc_state, conn_state); 1758 1759 unlock: 1760 mutex_unlock(&intel_dp->psr.lock); 1761 } 1762 1763 /** 1764 * psr_wait_for_idle - wait for PSR1 to idle 1765 * @intel_dp: Intel DP 1766 * @out_value: PSR status in case of failure 1767 * 1768 * Returns: 0 on success or -ETIMEOUT if PSR status does not idle. 1769 * 1770 */ 1771 static int psr_wait_for_idle(struct intel_dp *intel_dp, u32 *out_value) 1772 { 1773 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 1774 1775 /* 1776 * From bspec: Panel Self Refresh (BDW+) 1777 * Max. time for PSR to idle = Inverse of the refresh rate + 6 ms of 1778 * exit training time + 1.5 ms of aux channel handshake. 50 ms is 1779 * defensive enough to cover everything. 1780 */ 1781 return __intel_wait_for_register(&dev_priv->uncore, 1782 EDP_PSR_STATUS(intel_dp->psr.transcoder), 1783 EDP_PSR_STATUS_STATE_MASK, 1784 EDP_PSR_STATUS_STATE_IDLE, 2, 50, 1785 out_value); 1786 } 1787 1788 /** 1789 * intel_psr_wait_for_idle - wait for PSR1 to idle 1790 * @new_crtc_state: new CRTC state 1791 * 1792 * This function is expected to be called from pipe_update_start() where it is 1793 * not expected to race with PSR enable or disable. 1794 */ 1795 void intel_psr_wait_for_idle(const struct intel_crtc_state *new_crtc_state) 1796 { 1797 struct drm_i915_private *dev_priv = to_i915(new_crtc_state->uapi.crtc->dev); 1798 struct intel_encoder *encoder; 1799 1800 if (!new_crtc_state->has_psr) 1801 return; 1802 1803 for_each_intel_encoder_mask_with_psr(&dev_priv->drm, encoder, 1804 new_crtc_state->uapi.encoder_mask) { 1805 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 1806 u32 psr_status; 1807 1808 mutex_lock(&intel_dp->psr.lock); 1809 if (!intel_dp->psr.enabled || intel_dp->psr.psr2_enabled) { 1810 mutex_unlock(&intel_dp->psr.lock); 1811 continue; 1812 } 1813 1814 /* when the PSR1 is enabled */ 1815 if (psr_wait_for_idle(intel_dp, &psr_status)) 1816 drm_err(&dev_priv->drm, 1817 "PSR idle timed out 0x%x, atomic update may fail\n", 1818 psr_status); 1819 mutex_unlock(&intel_dp->psr.lock); 1820 } 1821 } 1822 1823 static bool __psr_wait_for_idle_locked(struct intel_dp *intel_dp) 1824 { 1825 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 1826 i915_reg_t reg; 1827 u32 mask; 1828 int err; 1829 1830 if (!intel_dp->psr.enabled) 1831 return false; 1832 1833 if (intel_dp->psr.psr2_enabled) { 1834 reg = EDP_PSR2_STATUS(intel_dp->psr.transcoder); 1835 mask = EDP_PSR2_STATUS_STATE_MASK; 1836 } else { 1837 reg = EDP_PSR_STATUS(intel_dp->psr.transcoder); 1838 mask = EDP_PSR_STATUS_STATE_MASK; 1839 } 1840 1841 mutex_unlock(&intel_dp->psr.lock); 1842 1843 err = intel_de_wait_for_clear(dev_priv, reg, mask, 50); 1844 if (err) 1845 drm_err(&dev_priv->drm, 1846 "Timed out waiting for PSR Idle for re-enable\n"); 1847 1848 /* After the unlocked wait, verify that PSR is still wanted! */ 1849 mutex_lock(&intel_dp->psr.lock); 1850 return err == 0 && intel_dp->psr.enabled; 1851 } 1852 1853 static int intel_psr_fastset_force(struct drm_i915_private *dev_priv) 1854 { 1855 struct drm_connector_list_iter conn_iter; 1856 struct drm_device *dev = &dev_priv->drm; 1857 struct drm_modeset_acquire_ctx ctx; 1858 struct drm_atomic_state *state; 1859 struct drm_connector *conn; 1860 int err = 0; 1861 1862 state = drm_atomic_state_alloc(dev); 1863 if (!state) 1864 return -ENOMEM; 1865 1866 drm_modeset_acquire_init(&ctx, DRM_MODESET_ACQUIRE_INTERRUPTIBLE); 1867 state->acquire_ctx = &ctx; 1868 1869 retry: 1870 1871 drm_connector_list_iter_begin(dev, &conn_iter); 1872 drm_for_each_connector_iter(conn, &conn_iter) { 1873 struct drm_connector_state *conn_state; 1874 struct drm_crtc_state *crtc_state; 1875 1876 if (conn->connector_type != DRM_MODE_CONNECTOR_eDP) 1877 continue; 1878 1879 conn_state = drm_atomic_get_connector_state(state, conn); 1880 if (IS_ERR(conn_state)) { 1881 err = PTR_ERR(conn_state); 1882 break; 1883 } 1884 1885 if (!conn_state->crtc) 1886 continue; 1887 1888 crtc_state = drm_atomic_get_crtc_state(state, conn_state->crtc); 1889 if (IS_ERR(crtc_state)) { 1890 err = PTR_ERR(crtc_state); 1891 break; 1892 } 1893 1894 /* Mark mode as changed to trigger a pipe->update() */ 1895 crtc_state->mode_changed = true; 1896 } 1897 drm_connector_list_iter_end(&conn_iter); 1898 1899 if (err == 0) 1900 err = drm_atomic_commit(state); 1901 1902 if (err == -EDEADLK) { 1903 drm_atomic_state_clear(state); 1904 err = drm_modeset_backoff(&ctx); 1905 if (!err) 1906 goto retry; 1907 } 1908 1909 drm_modeset_drop_locks(&ctx); 1910 drm_modeset_acquire_fini(&ctx); 1911 drm_atomic_state_put(state); 1912 1913 return err; 1914 } 1915 1916 int intel_psr_debug_set(struct intel_dp *intel_dp, u64 val) 1917 { 1918 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 1919 const u32 mode = val & I915_PSR_DEBUG_MODE_MASK; 1920 u32 old_mode; 1921 int ret; 1922 1923 if (val & ~(I915_PSR_DEBUG_IRQ | I915_PSR_DEBUG_MODE_MASK) || 1924 mode > I915_PSR_DEBUG_ENABLE_SEL_FETCH) { 1925 drm_dbg_kms(&dev_priv->drm, "Invalid debug mask %llx\n", val); 1926 return -EINVAL; 1927 } 1928 1929 ret = mutex_lock_interruptible(&intel_dp->psr.lock); 1930 if (ret) 1931 return ret; 1932 1933 old_mode = intel_dp->psr.debug & I915_PSR_DEBUG_MODE_MASK; 1934 intel_dp->psr.debug = val; 1935 1936 /* 1937 * Do it right away if it's already enabled, otherwise it will be done 1938 * when enabling the source. 1939 */ 1940 if (intel_dp->psr.enabled) 1941 psr_irq_control(intel_dp); 1942 1943 mutex_unlock(&intel_dp->psr.lock); 1944 1945 if (old_mode != mode) 1946 ret = intel_psr_fastset_force(dev_priv); 1947 1948 return ret; 1949 } 1950 1951 static void intel_psr_handle_irq(struct intel_dp *intel_dp) 1952 { 1953 struct intel_psr *psr = &intel_dp->psr; 1954 1955 intel_psr_disable_locked(intel_dp); 1956 psr->sink_not_reliable = true; 1957 /* let's make sure that sink is awaken */ 1958 drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, DP_SET_POWER_D0); 1959 } 1960 1961 static void intel_psr_work(struct work_struct *work) 1962 { 1963 struct intel_dp *intel_dp = 1964 container_of(work, typeof(*intel_dp), psr.work); 1965 1966 mutex_lock(&intel_dp->psr.lock); 1967 1968 if (!intel_dp->psr.enabled) 1969 goto unlock; 1970 1971 if (READ_ONCE(intel_dp->psr.irq_aux_error)) 1972 intel_psr_handle_irq(intel_dp); 1973 1974 /* 1975 * We have to make sure PSR is ready for re-enable 1976 * otherwise it keeps disabled until next full enable/disable cycle. 1977 * PSR might take some time to get fully disabled 1978 * and be ready for re-enable. 1979 */ 1980 if (!__psr_wait_for_idle_locked(intel_dp)) 1981 goto unlock; 1982 1983 /* 1984 * The delayed work can race with an invalidate hence we need to 1985 * recheck. Since psr_flush first clears this and then reschedules we 1986 * won't ever miss a flush when bailing out here. 1987 */ 1988 if (intel_dp->psr.busy_frontbuffer_bits || intel_dp->psr.active) 1989 goto unlock; 1990 1991 intel_psr_activate(intel_dp); 1992 unlock: 1993 mutex_unlock(&intel_dp->psr.lock); 1994 } 1995 1996 /** 1997 * intel_psr_invalidate - Invalidade PSR 1998 * @dev_priv: i915 device 1999 * @frontbuffer_bits: frontbuffer plane tracking bits 2000 * @origin: which operation caused the invalidate 2001 * 2002 * Since the hardware frontbuffer tracking has gaps we need to integrate 2003 * with the software frontbuffer tracking. This function gets called every 2004 * time frontbuffer rendering starts and a buffer gets dirtied. PSR must be 2005 * disabled if the frontbuffer mask contains a buffer relevant to PSR. 2006 * 2007 * Dirty frontbuffers relevant to PSR are tracked in busy_frontbuffer_bits." 2008 */ 2009 void intel_psr_invalidate(struct drm_i915_private *dev_priv, 2010 unsigned frontbuffer_bits, enum fb_op_origin origin) 2011 { 2012 struct intel_encoder *encoder; 2013 2014 if (origin == ORIGIN_FLIP) 2015 return; 2016 2017 for_each_intel_encoder_with_psr(&dev_priv->drm, encoder) { 2018 unsigned int pipe_frontbuffer_bits = frontbuffer_bits; 2019 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2020 2021 mutex_lock(&intel_dp->psr.lock); 2022 if (!intel_dp->psr.enabled) { 2023 mutex_unlock(&intel_dp->psr.lock); 2024 continue; 2025 } 2026 2027 pipe_frontbuffer_bits &= 2028 INTEL_FRONTBUFFER_ALL_MASK(intel_dp->psr.pipe); 2029 intel_dp->psr.busy_frontbuffer_bits |= pipe_frontbuffer_bits; 2030 2031 if (pipe_frontbuffer_bits) 2032 intel_psr_exit(intel_dp); 2033 2034 mutex_unlock(&intel_dp->psr.lock); 2035 } 2036 } 2037 /* 2038 * When we will be completely rely on PSR2 S/W tracking in future, 2039 * intel_psr_flush() will invalidate and flush the PSR for ORIGIN_FLIP 2040 * event also therefore tgl_dc3co_flush() require to be changed 2041 * accordingly in future. 2042 */ 2043 static void 2044 tgl_dc3co_flush(struct intel_dp *intel_dp, unsigned int frontbuffer_bits, 2045 enum fb_op_origin origin) 2046 { 2047 mutex_lock(&intel_dp->psr.lock); 2048 2049 if (!intel_dp->psr.dc3co_exitline) 2050 goto unlock; 2051 2052 if (!intel_dp->psr.psr2_enabled || !intel_dp->psr.active) 2053 goto unlock; 2054 2055 /* 2056 * At every frontbuffer flush flip event modified delay of delayed work, 2057 * when delayed work schedules that means display has been idle. 2058 */ 2059 if (!(frontbuffer_bits & 2060 INTEL_FRONTBUFFER_ALL_MASK(intel_dp->psr.pipe))) 2061 goto unlock; 2062 2063 tgl_psr2_enable_dc3co(intel_dp); 2064 mod_delayed_work(system_wq, &intel_dp->psr.dc3co_work, 2065 intel_dp->psr.dc3co_exit_delay); 2066 2067 unlock: 2068 mutex_unlock(&intel_dp->psr.lock); 2069 } 2070 2071 /** 2072 * intel_psr_flush - Flush PSR 2073 * @dev_priv: i915 device 2074 * @frontbuffer_bits: frontbuffer plane tracking bits 2075 * @origin: which operation caused the flush 2076 * 2077 * Since the hardware frontbuffer tracking has gaps we need to integrate 2078 * with the software frontbuffer tracking. This function gets called every 2079 * time frontbuffer rendering has completed and flushed out to memory. PSR 2080 * can be enabled again if no other frontbuffer relevant to PSR is dirty. 2081 * 2082 * Dirty frontbuffers relevant to PSR are tracked in busy_frontbuffer_bits. 2083 */ 2084 void intel_psr_flush(struct drm_i915_private *dev_priv, 2085 unsigned frontbuffer_bits, enum fb_op_origin origin) 2086 { 2087 struct intel_encoder *encoder; 2088 2089 for_each_intel_encoder_with_psr(&dev_priv->drm, encoder) { 2090 unsigned int pipe_frontbuffer_bits = frontbuffer_bits; 2091 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2092 2093 if (origin == ORIGIN_FLIP) { 2094 tgl_dc3co_flush(intel_dp, frontbuffer_bits, origin); 2095 continue; 2096 } 2097 2098 mutex_lock(&intel_dp->psr.lock); 2099 if (!intel_dp->psr.enabled) { 2100 mutex_unlock(&intel_dp->psr.lock); 2101 continue; 2102 } 2103 2104 pipe_frontbuffer_bits &= 2105 INTEL_FRONTBUFFER_ALL_MASK(intel_dp->psr.pipe); 2106 intel_dp->psr.busy_frontbuffer_bits &= ~pipe_frontbuffer_bits; 2107 2108 /* 2109 * If the PSR is paused by an explicit intel_psr_paused() call, 2110 * we have to ensure that the PSR is not activated until 2111 * intel_psr_resume() is called. 2112 */ 2113 if (intel_dp->psr.paused) { 2114 mutex_unlock(&intel_dp->psr.lock); 2115 continue; 2116 } 2117 2118 /* By definition flush = invalidate + flush */ 2119 if (pipe_frontbuffer_bits) 2120 psr_force_hw_tracking_exit(intel_dp); 2121 2122 if (!intel_dp->psr.active && !intel_dp->psr.busy_frontbuffer_bits) 2123 schedule_work(&intel_dp->psr.work); 2124 mutex_unlock(&intel_dp->psr.lock); 2125 } 2126 } 2127 2128 /** 2129 * intel_psr_init - Init basic PSR work and mutex. 2130 * @intel_dp: Intel DP 2131 * 2132 * This function is called after the initializing connector. 2133 * (the initializing of connector treats the handling of connector capabilities) 2134 * And it initializes basic PSR stuff for each DP Encoder. 2135 */ 2136 void intel_psr_init(struct intel_dp *intel_dp) 2137 { 2138 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 2139 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 2140 2141 if (!HAS_PSR(dev_priv)) 2142 return; 2143 2144 /* 2145 * HSW spec explicitly says PSR is tied to port A. 2146 * BDW+ platforms have a instance of PSR registers per transcoder but 2147 * BDW, GEN9 and GEN11 are not validated by HW team in other transcoder 2148 * than eDP one. 2149 * For now it only supports one instance of PSR for BDW, GEN9 and GEN11. 2150 * So lets keep it hardcoded to PORT_A for BDW, GEN9 and GEN11. 2151 * But GEN12 supports a instance of PSR registers per transcoder. 2152 */ 2153 if (DISPLAY_VER(dev_priv) < 12 && dig_port->base.port != PORT_A) { 2154 drm_dbg_kms(&dev_priv->drm, 2155 "PSR condition failed: Port not supported\n"); 2156 return; 2157 } 2158 2159 intel_dp->psr.source_support = true; 2160 2161 if (IS_HASWELL(dev_priv)) 2162 /* 2163 * HSW don't have PSR registers on the same space as transcoder 2164 * so set this to a value that when subtract to the register 2165 * in transcoder space results in the right offset for HSW 2166 */ 2167 dev_priv->hsw_psr_mmio_adjust = _SRD_CTL_EDP - _HSW_EDP_PSR_BASE; 2168 2169 if (dev_priv->params.enable_psr == -1) 2170 if (DISPLAY_VER(dev_priv) < 9 || !dev_priv->vbt.psr.enable) 2171 dev_priv->params.enable_psr = 0; 2172 2173 /* Set link_standby x link_off defaults */ 2174 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) 2175 /* HSW and BDW require workarounds that we don't implement. */ 2176 intel_dp->psr.link_standby = false; 2177 else if (DISPLAY_VER(dev_priv) < 12) 2178 /* For new platforms up to TGL let's respect VBT back again */ 2179 intel_dp->psr.link_standby = dev_priv->vbt.psr.full_link; 2180 2181 INIT_WORK(&intel_dp->psr.work, intel_psr_work); 2182 INIT_DELAYED_WORK(&intel_dp->psr.dc3co_work, tgl_dc3co_disable_work); 2183 mutex_init(&intel_dp->psr.lock); 2184 } 2185 2186 static int psr_get_status_and_error_status(struct intel_dp *intel_dp, 2187 u8 *status, u8 *error_status) 2188 { 2189 struct drm_dp_aux *aux = &intel_dp->aux; 2190 int ret; 2191 2192 ret = drm_dp_dpcd_readb(aux, DP_PSR_STATUS, status); 2193 if (ret != 1) 2194 return ret; 2195 2196 ret = drm_dp_dpcd_readb(aux, DP_PSR_ERROR_STATUS, error_status); 2197 if (ret != 1) 2198 return ret; 2199 2200 *status = *status & DP_PSR_SINK_STATE_MASK; 2201 2202 return 0; 2203 } 2204 2205 static void psr_alpm_check(struct intel_dp *intel_dp) 2206 { 2207 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 2208 struct drm_dp_aux *aux = &intel_dp->aux; 2209 struct intel_psr *psr = &intel_dp->psr; 2210 u8 val; 2211 int r; 2212 2213 if (!psr->psr2_enabled) 2214 return; 2215 2216 r = drm_dp_dpcd_readb(aux, DP_RECEIVER_ALPM_STATUS, &val); 2217 if (r != 1) { 2218 drm_err(&dev_priv->drm, "Error reading ALPM status\n"); 2219 return; 2220 } 2221 2222 if (val & DP_ALPM_LOCK_TIMEOUT_ERROR) { 2223 intel_psr_disable_locked(intel_dp); 2224 psr->sink_not_reliable = true; 2225 drm_dbg_kms(&dev_priv->drm, 2226 "ALPM lock timeout error, disabling PSR\n"); 2227 2228 /* Clearing error */ 2229 drm_dp_dpcd_writeb(aux, DP_RECEIVER_ALPM_STATUS, val); 2230 } 2231 } 2232 2233 static void psr_capability_changed_check(struct intel_dp *intel_dp) 2234 { 2235 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 2236 struct intel_psr *psr = &intel_dp->psr; 2237 u8 val; 2238 int r; 2239 2240 r = drm_dp_dpcd_readb(&intel_dp->aux, DP_PSR_ESI, &val); 2241 if (r != 1) { 2242 drm_err(&dev_priv->drm, "Error reading DP_PSR_ESI\n"); 2243 return; 2244 } 2245 2246 if (val & DP_PSR_CAPS_CHANGE) { 2247 intel_psr_disable_locked(intel_dp); 2248 psr->sink_not_reliable = true; 2249 drm_dbg_kms(&dev_priv->drm, 2250 "Sink PSR capability changed, disabling PSR\n"); 2251 2252 /* Clearing it */ 2253 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_ESI, val); 2254 } 2255 } 2256 2257 void intel_psr_short_pulse(struct intel_dp *intel_dp) 2258 { 2259 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 2260 struct intel_psr *psr = &intel_dp->psr; 2261 u8 status, error_status; 2262 const u8 errors = DP_PSR_RFB_STORAGE_ERROR | 2263 DP_PSR_VSC_SDP_UNCORRECTABLE_ERROR | 2264 DP_PSR_LINK_CRC_ERROR; 2265 2266 if (!CAN_PSR(intel_dp)) 2267 return; 2268 2269 mutex_lock(&psr->lock); 2270 2271 if (!psr->enabled) 2272 goto exit; 2273 2274 if (psr_get_status_and_error_status(intel_dp, &status, &error_status)) { 2275 drm_err(&dev_priv->drm, 2276 "Error reading PSR status or error status\n"); 2277 goto exit; 2278 } 2279 2280 if (status == DP_PSR_SINK_INTERNAL_ERROR || (error_status & errors)) { 2281 intel_psr_disable_locked(intel_dp); 2282 psr->sink_not_reliable = true; 2283 } 2284 2285 if (status == DP_PSR_SINK_INTERNAL_ERROR && !error_status) 2286 drm_dbg_kms(&dev_priv->drm, 2287 "PSR sink internal error, disabling PSR\n"); 2288 if (error_status & DP_PSR_RFB_STORAGE_ERROR) 2289 drm_dbg_kms(&dev_priv->drm, 2290 "PSR RFB storage error, disabling PSR\n"); 2291 if (error_status & DP_PSR_VSC_SDP_UNCORRECTABLE_ERROR) 2292 drm_dbg_kms(&dev_priv->drm, 2293 "PSR VSC SDP uncorrectable error, disabling PSR\n"); 2294 if (error_status & DP_PSR_LINK_CRC_ERROR) 2295 drm_dbg_kms(&dev_priv->drm, 2296 "PSR Link CRC error, disabling PSR\n"); 2297 2298 if (error_status & ~errors) 2299 drm_err(&dev_priv->drm, 2300 "PSR_ERROR_STATUS unhandled errors %x\n", 2301 error_status & ~errors); 2302 /* clear status register */ 2303 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_ERROR_STATUS, error_status); 2304 2305 psr_alpm_check(intel_dp); 2306 psr_capability_changed_check(intel_dp); 2307 2308 exit: 2309 mutex_unlock(&psr->lock); 2310 } 2311 2312 bool intel_psr_enabled(struct intel_dp *intel_dp) 2313 { 2314 bool ret; 2315 2316 if (!CAN_PSR(intel_dp)) 2317 return false; 2318 2319 mutex_lock(&intel_dp->psr.lock); 2320 ret = intel_dp->psr.enabled; 2321 mutex_unlock(&intel_dp->psr.lock); 2322 2323 return ret; 2324 } 2325