1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2021 Intel Corporation 4 */ 5 6 #include "gem/i915_gem_lmem.h" 7 #include "gem/i915_gem_region.h" 8 #include "i915_drv.h" 9 #include "intel_atomic_plane.h" 10 #include "intel_crtc.h" 11 #include "intel_display.h" 12 #include "intel_display_types.h" 13 #include "intel_fb.h" 14 #include "intel_frontbuffer.h" 15 #include "intel_plane_initial.h" 16 17 void intel_plane_initial_vblank_wait(struct intel_crtc *crtc) 18 { 19 intel_crtc_wait_for_next_vblank(crtc); 20 } 21 22 static bool 23 intel_reuse_initial_plane_obj(struct intel_crtc *this, 24 const struct intel_initial_plane_config plane_configs[], 25 struct drm_framebuffer **fb, 26 struct i915_vma **vma) 27 { 28 struct intel_display *display = to_intel_display(this); 29 struct intel_crtc *crtc; 30 31 for_each_intel_crtc(display->drm, crtc) { 32 struct intel_plane *plane = 33 to_intel_plane(crtc->base.primary); 34 const struct intel_plane_state *plane_state = 35 to_intel_plane_state(plane->base.state); 36 const struct intel_crtc_state *crtc_state = 37 to_intel_crtc_state(crtc->base.state); 38 39 if (!crtc_state->uapi.active) 40 continue; 41 42 if (!plane_state->ggtt_vma) 43 continue; 44 45 if (plane_configs[this->pipe].base == plane_configs[crtc->pipe].base) { 46 *fb = plane_state->hw.fb; 47 *vma = plane_state->ggtt_vma; 48 return true; 49 } 50 } 51 52 return false; 53 } 54 55 static enum intel_memory_type 56 initial_plane_memory_type(struct drm_i915_private *i915) 57 { 58 if (IS_DGFX(i915)) 59 return INTEL_MEMORY_LOCAL; 60 else if (HAS_LMEMBAR_SMEM_STOLEN(i915)) 61 return INTEL_MEMORY_STOLEN_LOCAL; 62 else 63 return INTEL_MEMORY_STOLEN_SYSTEM; 64 } 65 66 static bool 67 initial_plane_phys(struct intel_display *display, 68 struct intel_initial_plane_config *plane_config) 69 { 70 struct drm_i915_private *i915 = to_i915(display->drm); 71 struct i915_ggtt *ggtt = to_gt(i915)->ggtt; 72 struct intel_memory_region *mem; 73 enum intel_memory_type mem_type; 74 bool is_present, is_local; 75 dma_addr_t dma_addr; 76 u32 base; 77 78 mem_type = initial_plane_memory_type(i915); 79 mem = intel_memory_region_by_type(i915, mem_type); 80 if (!mem) { 81 drm_dbg_kms(display->drm, 82 "Initial plane memory region (type %s) not initialized\n", 83 intel_memory_type_str(mem_type)); 84 return false; 85 } 86 87 base = round_down(plane_config->base, I915_GTT_MIN_ALIGNMENT); 88 89 dma_addr = intel_ggtt_read_entry(&ggtt->vm, base, &is_present, &is_local); 90 91 if (!is_present) { 92 drm_err(display->drm, 93 "Initial plane FB PTE not present\n"); 94 return false; 95 } 96 97 if (intel_memory_type_is_local(mem->type) != is_local) { 98 drm_err(display->drm, 99 "Initial plane FB PTE unsuitable for %s\n", 100 mem->region.name); 101 return false; 102 } 103 104 if (dma_addr < mem->region.start || dma_addr > mem->region.end) { 105 drm_err(display->drm, 106 "Initial plane programming using invalid range, dma_addr=%pa (%s [%pa-%pa])\n", 107 &dma_addr, mem->region.name, &mem->region.start, &mem->region.end); 108 return false; 109 } 110 111 drm_dbg(display->drm, 112 "Using dma_addr=%pa, based on initial plane programming\n", 113 &dma_addr); 114 115 plane_config->phys_base = dma_addr - mem->region.start; 116 plane_config->mem = mem; 117 118 return true; 119 } 120 121 static struct i915_vma * 122 initial_plane_vma(struct intel_display *display, 123 struct intel_initial_plane_config *plane_config) 124 { 125 struct drm_i915_private *i915 = to_i915(display->drm); 126 struct intel_memory_region *mem; 127 struct drm_i915_gem_object *obj; 128 struct drm_mm_node orig_mm = {}; 129 struct i915_vma *vma; 130 resource_size_t phys_base; 131 u32 base, size; 132 u64 pinctl; 133 134 if (plane_config->size == 0) 135 return NULL; 136 137 if (!initial_plane_phys(display, plane_config)) 138 return NULL; 139 140 phys_base = plane_config->phys_base; 141 mem = plane_config->mem; 142 143 base = round_down(plane_config->base, I915_GTT_MIN_ALIGNMENT); 144 size = round_up(plane_config->base + plane_config->size, 145 mem->min_page_size); 146 size -= base; 147 148 /* 149 * If the FB is too big, just don't use it since fbdev is not very 150 * important and we should probably use that space with FBC or other 151 * features. 152 */ 153 if (IS_ENABLED(CONFIG_FRAMEBUFFER_CONSOLE) && 154 mem == i915->mm.stolen_region && 155 size * 2 > i915->dsm.usable_size) { 156 drm_dbg_kms(display->drm, "Initial FB size exceeds half of stolen, discarding\n"); 157 return NULL; 158 } 159 160 obj = i915_gem_object_create_region_at(mem, phys_base, size, 161 I915_BO_ALLOC_USER | 162 I915_BO_PREALLOC); 163 if (IS_ERR(obj)) { 164 drm_dbg_kms(display->drm, "Failed to preallocate initial FB in %s\n", 165 mem->region.name); 166 return NULL; 167 } 168 169 /* 170 * Mark it WT ahead of time to avoid changing the 171 * cache_level during fbdev initialization. The 172 * unbind there would get stuck waiting for rcu. 173 */ 174 i915_gem_object_set_cache_coherency(obj, HAS_WT(i915) ? 175 I915_CACHE_WT : I915_CACHE_NONE); 176 177 switch (plane_config->tiling) { 178 case I915_TILING_NONE: 179 break; 180 case I915_TILING_X: 181 case I915_TILING_Y: 182 obj->tiling_and_stride = 183 plane_config->fb->base.pitches[0] | 184 plane_config->tiling; 185 break; 186 default: 187 MISSING_CASE(plane_config->tiling); 188 goto err_obj; 189 } 190 191 /* 192 * MTL GOP likes to place the framebuffer high up in ggtt, 193 * which can cause problems for ggtt_reserve_guc_top(). 194 * Try to pin it to a low ggtt address instead to avoid that. 195 */ 196 base = 0; 197 198 if (base != plane_config->base) { 199 struct i915_ggtt *ggtt = to_gt(i915)->ggtt; 200 int ret; 201 202 /* 203 * Make sure the original and new locations 204 * can't overlap. That would corrupt the original 205 * PTEs which are still being used for scanout. 206 */ 207 ret = i915_gem_gtt_reserve(&ggtt->vm, NULL, &orig_mm, 208 size, plane_config->base, 209 I915_COLOR_UNEVICTABLE, PIN_NOEVICT); 210 if (ret) 211 goto err_obj; 212 } 213 214 vma = i915_vma_instance(obj, &to_gt(i915)->ggtt->vm, NULL); 215 if (IS_ERR(vma)) 216 goto err_obj; 217 218 retry: 219 pinctl = PIN_GLOBAL | PIN_OFFSET_FIXED | base; 220 if (!i915_gem_object_is_lmem(obj)) 221 pinctl |= PIN_MAPPABLE; 222 if (i915_vma_pin(vma, 0, 0, pinctl)) { 223 if (drm_mm_node_allocated(&orig_mm)) { 224 drm_mm_remove_node(&orig_mm); 225 /* 226 * Try again, but this time pin 227 * it to its original location. 228 */ 229 base = plane_config->base; 230 goto retry; 231 } 232 goto err_obj; 233 } 234 235 if (i915_gem_object_is_tiled(obj) && 236 !i915_vma_is_map_and_fenceable(vma)) 237 goto err_obj; 238 239 if (drm_mm_node_allocated(&orig_mm)) 240 drm_mm_remove_node(&orig_mm); 241 242 drm_dbg_kms(display->drm, 243 "Initial plane fb bound to 0x%x in the ggtt (original 0x%x)\n", 244 i915_ggtt_offset(vma), plane_config->base); 245 246 return vma; 247 248 err_obj: 249 if (drm_mm_node_allocated(&orig_mm)) 250 drm_mm_remove_node(&orig_mm); 251 i915_gem_object_put(obj); 252 return NULL; 253 } 254 255 static bool 256 intel_alloc_initial_plane_obj(struct intel_crtc *crtc, 257 struct intel_initial_plane_config *plane_config) 258 { 259 struct intel_display *display = to_intel_display(crtc); 260 struct drm_mode_fb_cmd2 mode_cmd = {}; 261 struct drm_framebuffer *fb = &plane_config->fb->base; 262 struct i915_vma *vma; 263 264 switch (fb->modifier) { 265 case DRM_FORMAT_MOD_LINEAR: 266 case I915_FORMAT_MOD_X_TILED: 267 case I915_FORMAT_MOD_Y_TILED: 268 case I915_FORMAT_MOD_4_TILED: 269 break; 270 default: 271 drm_dbg(display->drm, 272 "Unsupported modifier for initial FB: 0x%llx\n", 273 fb->modifier); 274 return false; 275 } 276 277 vma = initial_plane_vma(display, plane_config); 278 if (!vma) 279 return false; 280 281 mode_cmd.pixel_format = fb->format->format; 282 mode_cmd.width = fb->width; 283 mode_cmd.height = fb->height; 284 mode_cmd.pitches[0] = fb->pitches[0]; 285 mode_cmd.modifier[0] = fb->modifier; 286 mode_cmd.flags = DRM_MODE_FB_MODIFIERS; 287 288 if (intel_framebuffer_init(to_intel_framebuffer(fb), 289 intel_bo_to_drm_bo(vma->obj), &mode_cmd)) { 290 drm_dbg_kms(display->drm, "intel fb init failed\n"); 291 goto err_vma; 292 } 293 294 plane_config->vma = vma; 295 return true; 296 297 err_vma: 298 i915_vma_put(vma); 299 return false; 300 } 301 302 static void 303 intel_find_initial_plane_obj(struct intel_crtc *crtc, 304 struct intel_initial_plane_config plane_configs[]) 305 { 306 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 307 struct intel_initial_plane_config *plane_config = 308 &plane_configs[crtc->pipe]; 309 struct intel_plane *plane = 310 to_intel_plane(crtc->base.primary); 311 struct intel_plane_state *plane_state = 312 to_intel_plane_state(plane->base.state); 313 struct drm_framebuffer *fb; 314 struct i915_vma *vma; 315 316 /* 317 * TODO: 318 * Disable planes if get_initial_plane_config() failed. 319 * Make sure things work if the surface base is not page aligned. 320 */ 321 if (!plane_config->fb) 322 return; 323 324 if (intel_alloc_initial_plane_obj(crtc, plane_config)) { 325 fb = &plane_config->fb->base; 326 vma = plane_config->vma; 327 goto valid_fb; 328 } 329 330 /* 331 * Failed to alloc the obj, check to see if we should share 332 * an fb with another CRTC instead 333 */ 334 if (intel_reuse_initial_plane_obj(crtc, plane_configs, &fb, &vma)) 335 goto valid_fb; 336 337 /* 338 * We've failed to reconstruct the BIOS FB. Current display state 339 * indicates that the primary plane is visible, but has a NULL FB, 340 * which will lead to problems later if we don't fix it up. The 341 * simplest solution is to just disable the primary plane now and 342 * pretend the BIOS never had it enabled. 343 */ 344 intel_plane_disable_noatomic(crtc, plane); 345 346 return; 347 348 valid_fb: 349 plane_state->uapi.rotation = plane_config->rotation; 350 intel_fb_fill_view(to_intel_framebuffer(fb), 351 plane_state->uapi.rotation, &plane_state->view); 352 353 __i915_vma_pin(vma); 354 plane_state->ggtt_vma = i915_vma_get(vma); 355 if (intel_plane_uses_fence(plane_state) && 356 i915_vma_pin_fence(vma) == 0 && vma->fence) 357 plane_state->flags |= PLANE_HAS_FENCE; 358 359 plane_state->uapi.src_x = 0; 360 plane_state->uapi.src_y = 0; 361 plane_state->uapi.src_w = fb->width << 16; 362 plane_state->uapi.src_h = fb->height << 16; 363 364 plane_state->uapi.crtc_x = 0; 365 plane_state->uapi.crtc_y = 0; 366 plane_state->uapi.crtc_w = fb->width; 367 plane_state->uapi.crtc_h = fb->height; 368 369 if (plane_config->tiling) 370 dev_priv->preserve_bios_swizzle = true; 371 372 plane_state->uapi.fb = fb; 373 drm_framebuffer_get(fb); 374 375 plane_state->uapi.crtc = &crtc->base; 376 intel_plane_copy_uapi_to_hw_state(plane_state, plane_state, crtc); 377 378 atomic_or(plane->frontbuffer_bit, &to_intel_frontbuffer(fb)->bits); 379 } 380 381 static void plane_config_fini(struct intel_initial_plane_config *plane_config) 382 { 383 if (plane_config->fb) { 384 struct drm_framebuffer *fb = &plane_config->fb->base; 385 386 /* We may only have the stub and not a full framebuffer */ 387 if (drm_framebuffer_read_refcount(fb)) 388 drm_framebuffer_put(fb); 389 else 390 kfree(fb); 391 } 392 393 if (plane_config->vma) 394 i915_vma_put(plane_config->vma); 395 } 396 397 void intel_initial_plane_config(struct intel_display *display) 398 { 399 struct intel_initial_plane_config plane_configs[I915_MAX_PIPES] = {}; 400 struct intel_crtc *crtc; 401 402 for_each_intel_crtc(display->drm, crtc) { 403 struct intel_initial_plane_config *plane_config = 404 &plane_configs[crtc->pipe]; 405 406 if (!to_intel_crtc_state(crtc->base.state)->uapi.active) 407 continue; 408 409 /* 410 * Note that reserving the BIOS fb up front prevents us 411 * from stuffing other stolen allocations like the ring 412 * on top. This prevents some ugliness at boot time, and 413 * can even allow for smooth boot transitions if the BIOS 414 * fb is large enough for the active pipe configuration. 415 */ 416 display->funcs.display->get_initial_plane_config(crtc, plane_config); 417 418 /* 419 * If the fb is shared between multiple heads, we'll 420 * just get the first one. 421 */ 422 intel_find_initial_plane_obj(crtc, plane_configs); 423 424 if (display->funcs.display->fixup_initial_plane_config(crtc, plane_config)) 425 intel_plane_initial_vblank_wait(crtc); 426 427 plane_config_fini(plane_config); 428 } 429 } 430