1 /* 2 * Copyright © 2013 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 * Author: Damien Lespiau <damien.lespiau@intel.com> 24 * 25 */ 26 27 #include <linux/ctype.h> 28 #include <linux/debugfs.h> 29 #include <linux/seq_file.h> 30 31 #include <drm/drm_print.h> 32 33 #include "intel_atomic.h" 34 #include "intel_de.h" 35 #include "intel_display_irq.h" 36 #include "intel_display_regs.h" 37 #include "intel_display_types.h" 38 #include "intel_parent.h" 39 #include "intel_pipe_crc.h" 40 #include "intel_pipe_crc_regs.h" 41 42 static const char * const pipe_crc_sources[] = { 43 [INTEL_PIPE_CRC_SOURCE_NONE] = "none", 44 [INTEL_PIPE_CRC_SOURCE_PLANE1] = "plane1", 45 [INTEL_PIPE_CRC_SOURCE_PLANE2] = "plane2", 46 [INTEL_PIPE_CRC_SOURCE_PLANE3] = "plane3", 47 [INTEL_PIPE_CRC_SOURCE_PLANE4] = "plane4", 48 [INTEL_PIPE_CRC_SOURCE_PLANE5] = "plane5", 49 [INTEL_PIPE_CRC_SOURCE_PLANE6] = "plane6", 50 [INTEL_PIPE_CRC_SOURCE_PLANE7] = "plane7", 51 [INTEL_PIPE_CRC_SOURCE_PIPE] = "pipe", 52 [INTEL_PIPE_CRC_SOURCE_TV] = "TV", 53 [INTEL_PIPE_CRC_SOURCE_DP_B] = "DP-B", 54 [INTEL_PIPE_CRC_SOURCE_DP_C] = "DP-C", 55 [INTEL_PIPE_CRC_SOURCE_DP_D] = "DP-D", 56 [INTEL_PIPE_CRC_SOURCE_AUTO] = "auto", 57 }; 58 59 static int i8xx_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source, 60 u32 *val) 61 { 62 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) 63 *source = INTEL_PIPE_CRC_SOURCE_PIPE; 64 65 switch (*source) { 66 case INTEL_PIPE_CRC_SOURCE_PIPE: 67 *val = PIPE_CRC_ENABLE | PIPE_CRC_INCLUDE_BORDER_I8XX; 68 break; 69 case INTEL_PIPE_CRC_SOURCE_NONE: 70 *val = 0; 71 break; 72 default: 73 return -EINVAL; 74 } 75 76 return 0; 77 } 78 79 static void i9xx_pipe_crc_auto_source(struct intel_display *display, 80 enum pipe pipe, 81 enum intel_pipe_crc_source *source) 82 { 83 struct intel_encoder *encoder; 84 struct intel_crtc *crtc; 85 struct intel_digital_port *dig_port; 86 87 *source = INTEL_PIPE_CRC_SOURCE_PIPE; 88 89 drm_modeset_lock_all(display->drm); 90 for_each_intel_encoder(display->drm, encoder) { 91 if (!encoder->base.crtc) 92 continue; 93 94 crtc = to_intel_crtc(encoder->base.crtc); 95 96 if (crtc->pipe != pipe) 97 continue; 98 99 switch (encoder->type) { 100 case INTEL_OUTPUT_TVOUT: 101 *source = INTEL_PIPE_CRC_SOURCE_TV; 102 break; 103 case INTEL_OUTPUT_DP: 104 case INTEL_OUTPUT_EDP: 105 dig_port = enc_to_dig_port(encoder); 106 switch (dig_port->base.port) { 107 case PORT_B: 108 *source = INTEL_PIPE_CRC_SOURCE_DP_B; 109 break; 110 case PORT_C: 111 *source = INTEL_PIPE_CRC_SOURCE_DP_C; 112 break; 113 case PORT_D: 114 *source = INTEL_PIPE_CRC_SOURCE_DP_D; 115 break; 116 default: 117 drm_WARN(display->drm, 1, "nonexisting DP port %c\n", 118 port_name(dig_port->base.port)); 119 break; 120 } 121 break; 122 default: 123 break; 124 } 125 } 126 drm_modeset_unlock_all(display->drm); 127 } 128 129 static int vlv_pipe_crc_ctl_reg(struct intel_display *display, 130 enum pipe pipe, 131 enum intel_pipe_crc_source *source, 132 u32 *val) 133 { 134 bool need_stable_symbols = false; 135 136 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) 137 i9xx_pipe_crc_auto_source(display, pipe, source); 138 139 switch (*source) { 140 case INTEL_PIPE_CRC_SOURCE_PIPE: 141 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_VLV; 142 break; 143 case INTEL_PIPE_CRC_SOURCE_DP_B: 144 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_VLV; 145 need_stable_symbols = true; 146 break; 147 case INTEL_PIPE_CRC_SOURCE_DP_C: 148 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_VLV; 149 need_stable_symbols = true; 150 break; 151 case INTEL_PIPE_CRC_SOURCE_DP_D: 152 if (!display->platform.cherryview) 153 return -EINVAL; 154 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_VLV; 155 need_stable_symbols = true; 156 break; 157 case INTEL_PIPE_CRC_SOURCE_NONE: 158 *val = 0; 159 break; 160 default: 161 return -EINVAL; 162 } 163 164 /* 165 * When the pipe CRC tap point is after the transcoders we need 166 * to tweak symbol-level features to produce a deterministic series of 167 * symbols for a given frame. We need to reset those features only once 168 * a frame (instead of every nth symbol): 169 * - DC-balance: used to ensure a better clock recovery from the data 170 * link (SDVO) 171 * - DisplayPort scrambling: used for EMI reduction 172 */ 173 if (need_stable_symbols) { 174 u32 tmp = intel_de_read(display, PORT_DFT2_G4X(display)); 175 176 tmp |= DC_BALANCE_RESET_VLV; 177 switch (pipe) { 178 case PIPE_A: 179 tmp |= PIPE_A_SCRAMBLE_RESET; 180 break; 181 case PIPE_B: 182 tmp |= PIPE_B_SCRAMBLE_RESET; 183 break; 184 case PIPE_C: 185 tmp |= PIPE_C_SCRAMBLE_RESET; 186 break; 187 default: 188 return -EINVAL; 189 } 190 intel_de_write(display, PORT_DFT2_G4X(display), tmp); 191 } 192 193 return 0; 194 } 195 196 static int i9xx_pipe_crc_ctl_reg(struct intel_display *display, 197 enum pipe pipe, 198 enum intel_pipe_crc_source *source, 199 u32 *val) 200 { 201 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) 202 i9xx_pipe_crc_auto_source(display, pipe, source); 203 204 switch (*source) { 205 case INTEL_PIPE_CRC_SOURCE_PIPE: 206 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_I9XX; 207 break; 208 case INTEL_PIPE_CRC_SOURCE_TV: 209 if (!SUPPORTS_TV(display)) 210 return -EINVAL; 211 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_TV_PRE; 212 break; 213 case INTEL_PIPE_CRC_SOURCE_NONE: 214 *val = 0; 215 break; 216 default: 217 /* 218 * The DP CRC source doesn't work on g4x. 219 * It can be made to work to some degree by selecting 220 * the correct CRC source before the port is enabled, 221 * and not touching the CRC source bits again until 222 * the port is disabled. But even then the bits 223 * eventually get stuck and a reboot is needed to get 224 * working CRCs on the pipe again. Let's simply 225 * refuse to use DP CRCs on g4x. 226 */ 227 return -EINVAL; 228 } 229 230 return 0; 231 } 232 233 static void vlv_undo_pipe_scramble_reset(struct intel_display *display, 234 enum pipe pipe) 235 { 236 u32 tmp = intel_de_read(display, PORT_DFT2_G4X(display)); 237 238 switch (pipe) { 239 case PIPE_A: 240 tmp &= ~PIPE_A_SCRAMBLE_RESET; 241 break; 242 case PIPE_B: 243 tmp &= ~PIPE_B_SCRAMBLE_RESET; 244 break; 245 case PIPE_C: 246 tmp &= ~PIPE_C_SCRAMBLE_RESET; 247 break; 248 default: 249 return; 250 } 251 if (!(tmp & PIPE_SCRAMBLE_RESET_MASK)) 252 tmp &= ~DC_BALANCE_RESET_VLV; 253 intel_de_write(display, PORT_DFT2_G4X(display), tmp); 254 } 255 256 static int ilk_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source, 257 u32 *val) 258 { 259 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) 260 *source = INTEL_PIPE_CRC_SOURCE_PIPE; 261 262 switch (*source) { 263 case INTEL_PIPE_CRC_SOURCE_PLANE1: 264 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_ILK; 265 break; 266 case INTEL_PIPE_CRC_SOURCE_PLANE2: 267 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_ILK; 268 break; 269 case INTEL_PIPE_CRC_SOURCE_PIPE: 270 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_ILK; 271 break; 272 case INTEL_PIPE_CRC_SOURCE_NONE: 273 *val = 0; 274 break; 275 default: 276 return -EINVAL; 277 } 278 279 return 0; 280 } 281 282 static void 283 intel_crtc_crc_setup_workarounds(struct intel_crtc *crtc, bool enable) 284 { 285 struct intel_display *display = to_intel_display(crtc); 286 struct intel_crtc_state *pipe_config; 287 struct drm_atomic_state *state; 288 struct drm_modeset_acquire_ctx ctx; 289 int ret; 290 291 if (display->platform.i945gm || display->platform.i915gm) 292 i915gm_irq_cstate_wa(display, enable); 293 294 drm_modeset_acquire_init(&ctx, 0); 295 296 state = drm_atomic_state_alloc(display->drm); 297 if (!state) { 298 ret = -ENOMEM; 299 goto unlock; 300 } 301 302 state->acquire_ctx = &ctx; 303 to_intel_atomic_state(state)->internal = true; 304 305 retry: 306 pipe_config = intel_atomic_get_crtc_state(state, crtc); 307 if (IS_ERR(pipe_config)) { 308 ret = PTR_ERR(pipe_config); 309 goto put_state; 310 } 311 312 pipe_config->uapi.mode_changed = pipe_config->has_psr; 313 pipe_config->crc_enabled = enable; 314 315 if (display->platform.haswell && 316 pipe_config->hw.active && crtc->pipe == PIPE_A && 317 pipe_config->cpu_transcoder == TRANSCODER_EDP) 318 pipe_config->uapi.mode_changed = true; 319 320 ret = drm_atomic_commit(state); 321 322 put_state: 323 if (ret == -EDEADLK) { 324 drm_atomic_state_clear(state); 325 drm_modeset_backoff(&ctx); 326 goto retry; 327 } 328 329 drm_atomic_state_put(state); 330 unlock: 331 drm_WARN(display->drm, ret, 332 "Toggling workaround to %i returns %i\n", enable, ret); 333 drm_modeset_drop_locks(&ctx); 334 drm_modeset_acquire_fini(&ctx); 335 } 336 337 static int ivb_pipe_crc_ctl_reg(struct intel_display *display, 338 enum pipe pipe, 339 enum intel_pipe_crc_source *source, 340 u32 *val) 341 { 342 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) 343 *source = INTEL_PIPE_CRC_SOURCE_PIPE; 344 345 switch (*source) { 346 case INTEL_PIPE_CRC_SOURCE_PLANE1: 347 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_IVB; 348 break; 349 case INTEL_PIPE_CRC_SOURCE_PLANE2: 350 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_IVB; 351 break; 352 case INTEL_PIPE_CRC_SOURCE_PIPE: 353 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PF_IVB; 354 break; 355 case INTEL_PIPE_CRC_SOURCE_NONE: 356 *val = 0; 357 break; 358 default: 359 return -EINVAL; 360 } 361 362 return 0; 363 } 364 365 static int skl_pipe_crc_ctl_reg(struct intel_display *display, 366 enum pipe pipe, 367 enum intel_pipe_crc_source *source, 368 u32 *val) 369 { 370 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) 371 *source = INTEL_PIPE_CRC_SOURCE_PIPE; 372 373 switch (*source) { 374 case INTEL_PIPE_CRC_SOURCE_PLANE1: 375 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PLANE_1_SKL; 376 break; 377 case INTEL_PIPE_CRC_SOURCE_PLANE2: 378 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PLANE_2_SKL; 379 break; 380 case INTEL_PIPE_CRC_SOURCE_PLANE3: 381 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PLANE_3_SKL; 382 break; 383 case INTEL_PIPE_CRC_SOURCE_PLANE4: 384 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PLANE_4_SKL; 385 break; 386 case INTEL_PIPE_CRC_SOURCE_PLANE5: 387 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PLANE_5_SKL; 388 break; 389 case INTEL_PIPE_CRC_SOURCE_PLANE6: 390 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PLANE_6_SKL; 391 break; 392 case INTEL_PIPE_CRC_SOURCE_PLANE7: 393 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PLANE_7_SKL; 394 break; 395 case INTEL_PIPE_CRC_SOURCE_PIPE: 396 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DMUX_SKL; 397 break; 398 case INTEL_PIPE_CRC_SOURCE_NONE: 399 *val = 0; 400 break; 401 default: 402 return -EINVAL; 403 } 404 405 return 0; 406 } 407 408 static int get_new_crc_ctl_reg(struct intel_display *display, 409 enum pipe pipe, 410 enum intel_pipe_crc_source *source, u32 *val) 411 { 412 if (DISPLAY_VER(display) == 2) 413 return i8xx_pipe_crc_ctl_reg(source, val); 414 else if (DISPLAY_VER(display) < 5) 415 return i9xx_pipe_crc_ctl_reg(display, pipe, source, val); 416 else if (display->platform.valleyview || display->platform.cherryview) 417 return vlv_pipe_crc_ctl_reg(display, pipe, source, val); 418 else if (display->platform.ironlake || display->platform.sandybridge) 419 return ilk_pipe_crc_ctl_reg(source, val); 420 else if (DISPLAY_VER(display) < 9) 421 return ivb_pipe_crc_ctl_reg(display, pipe, source, val); 422 else 423 return skl_pipe_crc_ctl_reg(display, pipe, source, val); 424 } 425 426 static int 427 display_crc_ctl_parse_source(const char *buf, enum intel_pipe_crc_source *s) 428 { 429 int i; 430 431 if (!buf) { 432 *s = INTEL_PIPE_CRC_SOURCE_NONE; 433 return 0; 434 } 435 436 i = match_string(pipe_crc_sources, ARRAY_SIZE(pipe_crc_sources), buf); 437 if (i < 0) 438 return i; 439 440 *s = i; 441 return 0; 442 } 443 444 void intel_crtc_crc_init(struct intel_crtc *crtc) 445 { 446 struct intel_pipe_crc *pipe_crc = &crtc->pipe_crc; 447 448 spin_lock_init(&pipe_crc->lock); 449 } 450 451 static int i8xx_crc_source_valid(struct intel_display *display, 452 const enum intel_pipe_crc_source source) 453 { 454 switch (source) { 455 case INTEL_PIPE_CRC_SOURCE_PIPE: 456 case INTEL_PIPE_CRC_SOURCE_NONE: 457 return 0; 458 default: 459 return -EINVAL; 460 } 461 } 462 463 static int i9xx_crc_source_valid(struct intel_display *display, 464 const enum intel_pipe_crc_source source) 465 { 466 switch (source) { 467 case INTEL_PIPE_CRC_SOURCE_PIPE: 468 case INTEL_PIPE_CRC_SOURCE_TV: 469 case INTEL_PIPE_CRC_SOURCE_NONE: 470 return 0; 471 default: 472 return -EINVAL; 473 } 474 } 475 476 static int vlv_crc_source_valid(struct intel_display *display, 477 const enum intel_pipe_crc_source source) 478 { 479 switch (source) { 480 case INTEL_PIPE_CRC_SOURCE_PIPE: 481 case INTEL_PIPE_CRC_SOURCE_DP_B: 482 case INTEL_PIPE_CRC_SOURCE_DP_C: 483 case INTEL_PIPE_CRC_SOURCE_DP_D: 484 case INTEL_PIPE_CRC_SOURCE_NONE: 485 return 0; 486 default: 487 return -EINVAL; 488 } 489 } 490 491 static int ilk_crc_source_valid(struct intel_display *display, 492 const enum intel_pipe_crc_source source) 493 { 494 switch (source) { 495 case INTEL_PIPE_CRC_SOURCE_PIPE: 496 case INTEL_PIPE_CRC_SOURCE_PLANE1: 497 case INTEL_PIPE_CRC_SOURCE_PLANE2: 498 case INTEL_PIPE_CRC_SOURCE_NONE: 499 return 0; 500 default: 501 return -EINVAL; 502 } 503 } 504 505 static int ivb_crc_source_valid(struct intel_display *display, 506 const enum intel_pipe_crc_source source) 507 { 508 switch (source) { 509 case INTEL_PIPE_CRC_SOURCE_PIPE: 510 case INTEL_PIPE_CRC_SOURCE_PLANE1: 511 case INTEL_PIPE_CRC_SOURCE_PLANE2: 512 case INTEL_PIPE_CRC_SOURCE_NONE: 513 return 0; 514 default: 515 return -EINVAL; 516 } 517 } 518 519 static int skl_crc_source_valid(struct intel_display *display, 520 const enum intel_pipe_crc_source source) 521 { 522 switch (source) { 523 case INTEL_PIPE_CRC_SOURCE_PIPE: 524 case INTEL_PIPE_CRC_SOURCE_PLANE1: 525 case INTEL_PIPE_CRC_SOURCE_PLANE2: 526 case INTEL_PIPE_CRC_SOURCE_PLANE3: 527 case INTEL_PIPE_CRC_SOURCE_PLANE4: 528 case INTEL_PIPE_CRC_SOURCE_PLANE5: 529 case INTEL_PIPE_CRC_SOURCE_PLANE6: 530 case INTEL_PIPE_CRC_SOURCE_PLANE7: 531 case INTEL_PIPE_CRC_SOURCE_NONE: 532 return 0; 533 default: 534 return -EINVAL; 535 } 536 } 537 538 static int 539 intel_is_valid_crc_source(struct intel_display *display, 540 const enum intel_pipe_crc_source source) 541 { 542 if (DISPLAY_VER(display) == 2) 543 return i8xx_crc_source_valid(display, source); 544 else if (DISPLAY_VER(display) < 5) 545 return i9xx_crc_source_valid(display, source); 546 else if (display->platform.valleyview || display->platform.cherryview) 547 return vlv_crc_source_valid(display, source); 548 else if (display->platform.ironlake || display->platform.sandybridge) 549 return ilk_crc_source_valid(display, source); 550 else if (DISPLAY_VER(display) < 9) 551 return ivb_crc_source_valid(display, source); 552 else 553 return skl_crc_source_valid(display, source); 554 } 555 556 const char *const *intel_crtc_get_crc_sources(struct drm_crtc *crtc, 557 size_t *count) 558 { 559 *count = ARRAY_SIZE(pipe_crc_sources); 560 return pipe_crc_sources; 561 } 562 563 int intel_crtc_verify_crc_source(struct drm_crtc *crtc, const char *source_name, 564 size_t *values_cnt) 565 { 566 struct intel_display *display = to_intel_display(crtc->dev); 567 enum intel_pipe_crc_source source; 568 569 if (display_crc_ctl_parse_source(source_name, &source) < 0) { 570 drm_dbg_kms(display->drm, "unknown source %s\n", source_name); 571 return -EINVAL; 572 } 573 574 if (source == INTEL_PIPE_CRC_SOURCE_AUTO || 575 intel_is_valid_crc_source(display, source) == 0) { 576 *values_cnt = 5; 577 return 0; 578 } 579 580 return -EINVAL; 581 } 582 583 int intel_crtc_set_crc_source(struct drm_crtc *_crtc, const char *source_name) 584 { 585 struct intel_crtc *crtc = to_intel_crtc(_crtc); 586 struct intel_display *display = to_intel_display(crtc); 587 struct intel_pipe_crc *pipe_crc = &crtc->pipe_crc; 588 enum intel_display_power_domain power_domain; 589 enum intel_pipe_crc_source source; 590 enum pipe pipe = crtc->pipe; 591 struct ref_tracker *wakeref; 592 u32 val = 0; /* shut up gcc */ 593 int ret = 0; 594 bool enable; 595 596 if (display_crc_ctl_parse_source(source_name, &source) < 0) { 597 drm_dbg_kms(display->drm, "unknown source %s\n", source_name); 598 return -EINVAL; 599 } 600 601 power_domain = POWER_DOMAIN_PIPE(pipe); 602 wakeref = intel_display_power_get_if_enabled(display, power_domain); 603 if (!wakeref) { 604 drm_dbg_kms(display->drm, 605 "Trying to capture CRC while pipe is off\n"); 606 return -EIO; 607 } 608 609 enable = source != INTEL_PIPE_CRC_SOURCE_NONE; 610 if (enable) 611 intel_crtc_crc_setup_workarounds(crtc, true); 612 613 ret = get_new_crc_ctl_reg(display, pipe, &source, &val); 614 if (ret != 0) 615 goto out; 616 617 pipe_crc->source = source; 618 intel_de_write(display, PIPE_CRC_CTL(display, pipe), val); 619 intel_de_posting_read(display, PIPE_CRC_CTL(display, pipe)); 620 621 if (!source) { 622 if (display->platform.valleyview || display->platform.cherryview) 623 vlv_undo_pipe_scramble_reset(display, pipe); 624 } 625 626 pipe_crc->skipped = 0; 627 628 out: 629 if (!enable) 630 intel_crtc_crc_setup_workarounds(crtc, false); 631 632 intel_display_power_put(display, power_domain, wakeref); 633 634 return ret; 635 } 636 637 void intel_crtc_enable_pipe_crc(struct intel_crtc *crtc) 638 { 639 struct intel_display *display = to_intel_display(crtc); 640 struct intel_pipe_crc *pipe_crc = &crtc->pipe_crc; 641 enum pipe pipe = crtc->pipe; 642 u32 val = 0; 643 644 if (!crtc->base.crc.opened) 645 return; 646 647 if (get_new_crc_ctl_reg(display, pipe, &pipe_crc->source, &val) < 0) 648 return; 649 650 /* Don't need pipe_crc->lock here, IRQs are not generated. */ 651 pipe_crc->skipped = 0; 652 653 intel_de_write(display, PIPE_CRC_CTL(display, pipe), val); 654 intel_de_posting_read(display, PIPE_CRC_CTL(display, pipe)); 655 } 656 657 void intel_crtc_disable_pipe_crc(struct intel_crtc *crtc) 658 { 659 struct intel_display *display = to_intel_display(crtc); 660 struct intel_pipe_crc *pipe_crc = &crtc->pipe_crc; 661 enum pipe pipe = crtc->pipe; 662 663 /* Swallow crc's until we stop generating them. */ 664 spin_lock_irq(&pipe_crc->lock); 665 pipe_crc->skipped = INT_MIN; 666 spin_unlock_irq(&pipe_crc->lock); 667 668 intel_de_write(display, PIPE_CRC_CTL(display, pipe), 0); 669 intel_de_posting_read(display, PIPE_CRC_CTL(display, pipe)); 670 intel_parent_irq_synchronize(display); 671 } 672