xref: /linux/drivers/gpu/drm/i915/display/intel_pipe_crc.c (revision c532de5a67a70f8533d495f8f2aaa9a0491c3ad0) 
1 /*
2  * Copyright © 2013 Intel Corporation
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice (including the next
12  * paragraph) shall be included in all copies or substantial portions of the
13  * Software.
14  *
15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21  * IN THE SOFTWARE.
22  *
23  * Author: Damien Lespiau <damien.lespiau@intel.com>
24  *
25  */
26 
27 #include <linux/ctype.h>
28 #include <linux/debugfs.h>
29 #include <linux/seq_file.h>
30 
31 #include "i915_irq.h"
32 #include "i915_reg.h"
33 #include "intel_atomic.h"
34 #include "intel_de.h"
35 #include "intel_display_types.h"
36 #include "intel_pipe_crc.h"
37 #include "intel_pipe_crc_regs.h"
38 
39 static const char * const pipe_crc_sources[] = {
40 	[INTEL_PIPE_CRC_SOURCE_NONE] = "none",
41 	[INTEL_PIPE_CRC_SOURCE_PLANE1] = "plane1",
42 	[INTEL_PIPE_CRC_SOURCE_PLANE2] = "plane2",
43 	[INTEL_PIPE_CRC_SOURCE_PLANE3] = "plane3",
44 	[INTEL_PIPE_CRC_SOURCE_PLANE4] = "plane4",
45 	[INTEL_PIPE_CRC_SOURCE_PLANE5] = "plane5",
46 	[INTEL_PIPE_CRC_SOURCE_PLANE6] = "plane6",
47 	[INTEL_PIPE_CRC_SOURCE_PLANE7] = "plane7",
48 	[INTEL_PIPE_CRC_SOURCE_PIPE] = "pipe",
49 	[INTEL_PIPE_CRC_SOURCE_TV] = "TV",
50 	[INTEL_PIPE_CRC_SOURCE_DP_B] = "DP-B",
51 	[INTEL_PIPE_CRC_SOURCE_DP_C] = "DP-C",
52 	[INTEL_PIPE_CRC_SOURCE_DP_D] = "DP-D",
53 	[INTEL_PIPE_CRC_SOURCE_AUTO] = "auto",
54 };
55 
56 static int i8xx_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
57 				 u32 *val)
58 {
59 	if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
60 		*source = INTEL_PIPE_CRC_SOURCE_PIPE;
61 
62 	switch (*source) {
63 	case INTEL_PIPE_CRC_SOURCE_PIPE:
64 		*val = PIPE_CRC_ENABLE | PIPE_CRC_INCLUDE_BORDER_I8XX;
65 		break;
66 	case INTEL_PIPE_CRC_SOURCE_NONE:
67 		*val = 0;
68 		break;
69 	default:
70 		return -EINVAL;
71 	}
72 
73 	return 0;
74 }
75 
76 static void i9xx_pipe_crc_auto_source(struct drm_i915_private *dev_priv,
77 				      enum pipe pipe,
78 				      enum intel_pipe_crc_source *source)
79 {
80 	struct intel_encoder *encoder;
81 	struct intel_crtc *crtc;
82 	struct intel_digital_port *dig_port;
83 
84 	*source = INTEL_PIPE_CRC_SOURCE_PIPE;
85 
86 	drm_modeset_lock_all(&dev_priv->drm);
87 	for_each_intel_encoder(&dev_priv->drm, encoder) {
88 		if (!encoder->base.crtc)
89 			continue;
90 
91 		crtc = to_intel_crtc(encoder->base.crtc);
92 
93 		if (crtc->pipe != pipe)
94 			continue;
95 
96 		switch (encoder->type) {
97 		case INTEL_OUTPUT_TVOUT:
98 			*source = INTEL_PIPE_CRC_SOURCE_TV;
99 			break;
100 		case INTEL_OUTPUT_DP:
101 		case INTEL_OUTPUT_EDP:
102 			dig_port = enc_to_dig_port(encoder);
103 			switch (dig_port->base.port) {
104 			case PORT_B:
105 				*source = INTEL_PIPE_CRC_SOURCE_DP_B;
106 				break;
107 			case PORT_C:
108 				*source = INTEL_PIPE_CRC_SOURCE_DP_C;
109 				break;
110 			case PORT_D:
111 				*source = INTEL_PIPE_CRC_SOURCE_DP_D;
112 				break;
113 			default:
114 				drm_WARN(&dev_priv->drm, 1, "nonexisting DP port %c\n",
115 					 port_name(dig_port->base.port));
116 				break;
117 			}
118 			break;
119 		default:
120 			break;
121 		}
122 	}
123 	drm_modeset_unlock_all(&dev_priv->drm);
124 }
125 
126 static int vlv_pipe_crc_ctl_reg(struct drm_i915_private *dev_priv,
127 				enum pipe pipe,
128 				enum intel_pipe_crc_source *source,
129 				u32 *val)
130 {
131 	bool need_stable_symbols = false;
132 
133 	if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
134 		i9xx_pipe_crc_auto_source(dev_priv, pipe, source);
135 
136 	switch (*source) {
137 	case INTEL_PIPE_CRC_SOURCE_PIPE:
138 		*val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_VLV;
139 		break;
140 	case INTEL_PIPE_CRC_SOURCE_DP_B:
141 		*val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_VLV;
142 		need_stable_symbols = true;
143 		break;
144 	case INTEL_PIPE_CRC_SOURCE_DP_C:
145 		*val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_VLV;
146 		need_stable_symbols = true;
147 		break;
148 	case INTEL_PIPE_CRC_SOURCE_DP_D:
149 		if (!IS_CHERRYVIEW(dev_priv))
150 			return -EINVAL;
151 		*val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_VLV;
152 		need_stable_symbols = true;
153 		break;
154 	case INTEL_PIPE_CRC_SOURCE_NONE:
155 		*val = 0;
156 		break;
157 	default:
158 		return -EINVAL;
159 	}
160 
161 	/*
162 	 * When the pipe CRC tap point is after the transcoders we need
163 	 * to tweak symbol-level features to produce a deterministic series of
164 	 * symbols for a given frame. We need to reset those features only once
165 	 * a frame (instead of every nth symbol):
166 	 *   - DC-balance: used to ensure a better clock recovery from the data
167 	 *     link (SDVO)
168 	 *   - DisplayPort scrambling: used for EMI reduction
169 	 */
170 	if (need_stable_symbols) {
171 		u32 tmp = intel_de_read(dev_priv, PORT_DFT2_G4X(dev_priv));
172 
173 		tmp |= DC_BALANCE_RESET_VLV;
174 		switch (pipe) {
175 		case PIPE_A:
176 			tmp |= PIPE_A_SCRAMBLE_RESET;
177 			break;
178 		case PIPE_B:
179 			tmp |= PIPE_B_SCRAMBLE_RESET;
180 			break;
181 		case PIPE_C:
182 			tmp |= PIPE_C_SCRAMBLE_RESET;
183 			break;
184 		default:
185 			return -EINVAL;
186 		}
187 		intel_de_write(dev_priv, PORT_DFT2_G4X(dev_priv), tmp);
188 	}
189 
190 	return 0;
191 }
192 
193 static int i9xx_pipe_crc_ctl_reg(struct drm_i915_private *dev_priv,
194 				 enum pipe pipe,
195 				 enum intel_pipe_crc_source *source,
196 				 u32 *val)
197 {
198 	if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
199 		i9xx_pipe_crc_auto_source(dev_priv, pipe, source);
200 
201 	switch (*source) {
202 	case INTEL_PIPE_CRC_SOURCE_PIPE:
203 		*val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_I9XX;
204 		break;
205 	case INTEL_PIPE_CRC_SOURCE_TV:
206 		if (!SUPPORTS_TV(dev_priv))
207 			return -EINVAL;
208 		*val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_TV_PRE;
209 		break;
210 	case INTEL_PIPE_CRC_SOURCE_NONE:
211 		*val = 0;
212 		break;
213 	default:
214 		/*
215 		 * The DP CRC source doesn't work on g4x.
216 		 * It can be made to work to some degree by selecting
217 		 * the correct CRC source before the port is enabled,
218 		 * and not touching the CRC source bits again until
219 		 * the port is disabled. But even then the bits
220 		 * eventually get stuck and a reboot is needed to get
221 		 * working CRCs on the pipe again. Let's simply
222 		 * refuse to use DP CRCs on g4x.
223 		 */
224 		return -EINVAL;
225 	}
226 
227 	return 0;
228 }
229 
230 static void vlv_undo_pipe_scramble_reset(struct drm_i915_private *dev_priv,
231 					 enum pipe pipe)
232 {
233 	u32 tmp = intel_de_read(dev_priv, PORT_DFT2_G4X(dev_priv));
234 
235 	switch (pipe) {
236 	case PIPE_A:
237 		tmp &= ~PIPE_A_SCRAMBLE_RESET;
238 		break;
239 	case PIPE_B:
240 		tmp &= ~PIPE_B_SCRAMBLE_RESET;
241 		break;
242 	case PIPE_C:
243 		tmp &= ~PIPE_C_SCRAMBLE_RESET;
244 		break;
245 	default:
246 		return;
247 	}
248 	if (!(tmp & PIPE_SCRAMBLE_RESET_MASK))
249 		tmp &= ~DC_BALANCE_RESET_VLV;
250 	intel_de_write(dev_priv, PORT_DFT2_G4X(dev_priv), tmp);
251 }
252 
253 static int ilk_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
254 				u32 *val)
255 {
256 	if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
257 		*source = INTEL_PIPE_CRC_SOURCE_PIPE;
258 
259 	switch (*source) {
260 	case INTEL_PIPE_CRC_SOURCE_PLANE1:
261 		*val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_ILK;
262 		break;
263 	case INTEL_PIPE_CRC_SOURCE_PLANE2:
264 		*val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_ILK;
265 		break;
266 	case INTEL_PIPE_CRC_SOURCE_PIPE:
267 		*val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_ILK;
268 		break;
269 	case INTEL_PIPE_CRC_SOURCE_NONE:
270 		*val = 0;
271 		break;
272 	default:
273 		return -EINVAL;
274 	}
275 
276 	return 0;
277 }
278 
279 static void
280 intel_crtc_crc_setup_workarounds(struct intel_crtc *crtc, bool enable)
281 {
282 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
283 	struct intel_crtc_state *pipe_config;
284 	struct drm_atomic_state *state;
285 	struct drm_modeset_acquire_ctx ctx;
286 	int ret;
287 
288 	drm_modeset_acquire_init(&ctx, 0);
289 
290 	state = drm_atomic_state_alloc(&dev_priv->drm);
291 	if (!state) {
292 		ret = -ENOMEM;
293 		goto unlock;
294 	}
295 
296 	state->acquire_ctx = &ctx;
297 	to_intel_atomic_state(state)->internal = true;
298 
299 retry:
300 	pipe_config = intel_atomic_get_crtc_state(state, crtc);
301 	if (IS_ERR(pipe_config)) {
302 		ret = PTR_ERR(pipe_config);
303 		goto put_state;
304 	}
305 
306 	pipe_config->uapi.mode_changed = pipe_config->has_psr;
307 	pipe_config->crc_enabled = enable;
308 
309 	if (IS_HASWELL(dev_priv) &&
310 	    pipe_config->hw.active && crtc->pipe == PIPE_A &&
311 	    pipe_config->cpu_transcoder == TRANSCODER_EDP)
312 		pipe_config->uapi.mode_changed = true;
313 
314 	ret = drm_atomic_commit(state);
315 
316 put_state:
317 	if (ret == -EDEADLK) {
318 		drm_atomic_state_clear(state);
319 		drm_modeset_backoff(&ctx);
320 		goto retry;
321 	}
322 
323 	drm_atomic_state_put(state);
324 unlock:
325 	drm_WARN(&dev_priv->drm, ret,
326 		 "Toggling workaround to %i returns %i\n", enable, ret);
327 	drm_modeset_drop_locks(&ctx);
328 	drm_modeset_acquire_fini(&ctx);
329 }
330 
331 static int ivb_pipe_crc_ctl_reg(struct drm_i915_private *dev_priv,
332 				enum pipe pipe,
333 				enum intel_pipe_crc_source *source,
334 				u32 *val)
335 {
336 	if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
337 		*source = INTEL_PIPE_CRC_SOURCE_PIPE;
338 
339 	switch (*source) {
340 	case INTEL_PIPE_CRC_SOURCE_PLANE1:
341 		*val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_IVB;
342 		break;
343 	case INTEL_PIPE_CRC_SOURCE_PLANE2:
344 		*val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_IVB;
345 		break;
346 	case INTEL_PIPE_CRC_SOURCE_PIPE:
347 		*val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PF_IVB;
348 		break;
349 	case INTEL_PIPE_CRC_SOURCE_NONE:
350 		*val = 0;
351 		break;
352 	default:
353 		return -EINVAL;
354 	}
355 
356 	return 0;
357 }
358 
359 static int skl_pipe_crc_ctl_reg(struct drm_i915_private *dev_priv,
360 				enum pipe pipe,
361 				enum intel_pipe_crc_source *source,
362 				u32 *val)
363 {
364 	if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
365 		*source = INTEL_PIPE_CRC_SOURCE_PIPE;
366 
367 	switch (*source) {
368 	case INTEL_PIPE_CRC_SOURCE_PLANE1:
369 		*val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PLANE_1_SKL;
370 		break;
371 	case INTEL_PIPE_CRC_SOURCE_PLANE2:
372 		*val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PLANE_2_SKL;
373 		break;
374 	case INTEL_PIPE_CRC_SOURCE_PLANE3:
375 		*val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PLANE_3_SKL;
376 		break;
377 	case INTEL_PIPE_CRC_SOURCE_PLANE4:
378 		*val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PLANE_4_SKL;
379 		break;
380 	case INTEL_PIPE_CRC_SOURCE_PLANE5:
381 		*val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PLANE_5_SKL;
382 		break;
383 	case INTEL_PIPE_CRC_SOURCE_PLANE6:
384 		*val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PLANE_6_SKL;
385 		break;
386 	case INTEL_PIPE_CRC_SOURCE_PLANE7:
387 		*val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PLANE_7_SKL;
388 		break;
389 	case INTEL_PIPE_CRC_SOURCE_PIPE:
390 		*val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DMUX_SKL;
391 		break;
392 	case INTEL_PIPE_CRC_SOURCE_NONE:
393 		*val = 0;
394 		break;
395 	default:
396 		return -EINVAL;
397 	}
398 
399 	return 0;
400 }
401 
402 static int get_new_crc_ctl_reg(struct drm_i915_private *dev_priv,
403 			       enum pipe pipe,
404 			       enum intel_pipe_crc_source *source, u32 *val)
405 {
406 	if (DISPLAY_VER(dev_priv) == 2)
407 		return i8xx_pipe_crc_ctl_reg(source, val);
408 	else if (DISPLAY_VER(dev_priv) < 5)
409 		return i9xx_pipe_crc_ctl_reg(dev_priv, pipe, source, val);
410 	else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
411 		return vlv_pipe_crc_ctl_reg(dev_priv, pipe, source, val);
412 	else if (IS_IRONLAKE(dev_priv) || IS_SANDYBRIDGE(dev_priv))
413 		return ilk_pipe_crc_ctl_reg(source, val);
414 	else if (DISPLAY_VER(dev_priv) < 9)
415 		return ivb_pipe_crc_ctl_reg(dev_priv, pipe, source, val);
416 	else
417 		return skl_pipe_crc_ctl_reg(dev_priv, pipe, source, val);
418 }
419 
420 static int
421 display_crc_ctl_parse_source(const char *buf, enum intel_pipe_crc_source *s)
422 {
423 	int i;
424 
425 	if (!buf) {
426 		*s = INTEL_PIPE_CRC_SOURCE_NONE;
427 		return 0;
428 	}
429 
430 	i = match_string(pipe_crc_sources, ARRAY_SIZE(pipe_crc_sources), buf);
431 	if (i < 0)
432 		return i;
433 
434 	*s = i;
435 	return 0;
436 }
437 
438 void intel_crtc_crc_init(struct intel_crtc *crtc)
439 {
440 	struct intel_pipe_crc *pipe_crc = &crtc->pipe_crc;
441 
442 	spin_lock_init(&pipe_crc->lock);
443 }
444 
445 static int i8xx_crc_source_valid(struct drm_i915_private *dev_priv,
446 				 const enum intel_pipe_crc_source source)
447 {
448 	switch (source) {
449 	case INTEL_PIPE_CRC_SOURCE_PIPE:
450 	case INTEL_PIPE_CRC_SOURCE_NONE:
451 		return 0;
452 	default:
453 		return -EINVAL;
454 	}
455 }
456 
457 static int i9xx_crc_source_valid(struct drm_i915_private *dev_priv,
458 				 const enum intel_pipe_crc_source source)
459 {
460 	switch (source) {
461 	case INTEL_PIPE_CRC_SOURCE_PIPE:
462 	case INTEL_PIPE_CRC_SOURCE_TV:
463 	case INTEL_PIPE_CRC_SOURCE_NONE:
464 		return 0;
465 	default:
466 		return -EINVAL;
467 	}
468 }
469 
470 static int vlv_crc_source_valid(struct drm_i915_private *dev_priv,
471 				const enum intel_pipe_crc_source source)
472 {
473 	switch (source) {
474 	case INTEL_PIPE_CRC_SOURCE_PIPE:
475 	case INTEL_PIPE_CRC_SOURCE_DP_B:
476 	case INTEL_PIPE_CRC_SOURCE_DP_C:
477 	case INTEL_PIPE_CRC_SOURCE_DP_D:
478 	case INTEL_PIPE_CRC_SOURCE_NONE:
479 		return 0;
480 	default:
481 		return -EINVAL;
482 	}
483 }
484 
485 static int ilk_crc_source_valid(struct drm_i915_private *dev_priv,
486 				const enum intel_pipe_crc_source source)
487 {
488 	switch (source) {
489 	case INTEL_PIPE_CRC_SOURCE_PIPE:
490 	case INTEL_PIPE_CRC_SOURCE_PLANE1:
491 	case INTEL_PIPE_CRC_SOURCE_PLANE2:
492 	case INTEL_PIPE_CRC_SOURCE_NONE:
493 		return 0;
494 	default:
495 		return -EINVAL;
496 	}
497 }
498 
499 static int ivb_crc_source_valid(struct drm_i915_private *dev_priv,
500 				const enum intel_pipe_crc_source source)
501 {
502 	switch (source) {
503 	case INTEL_PIPE_CRC_SOURCE_PIPE:
504 	case INTEL_PIPE_CRC_SOURCE_PLANE1:
505 	case INTEL_PIPE_CRC_SOURCE_PLANE2:
506 	case INTEL_PIPE_CRC_SOURCE_NONE:
507 		return 0;
508 	default:
509 		return -EINVAL;
510 	}
511 }
512 
513 static int skl_crc_source_valid(struct drm_i915_private *dev_priv,
514 				const enum intel_pipe_crc_source source)
515 {
516 	switch (source) {
517 	case INTEL_PIPE_CRC_SOURCE_PIPE:
518 	case INTEL_PIPE_CRC_SOURCE_PLANE1:
519 	case INTEL_PIPE_CRC_SOURCE_PLANE2:
520 	case INTEL_PIPE_CRC_SOURCE_PLANE3:
521 	case INTEL_PIPE_CRC_SOURCE_PLANE4:
522 	case INTEL_PIPE_CRC_SOURCE_PLANE5:
523 	case INTEL_PIPE_CRC_SOURCE_PLANE6:
524 	case INTEL_PIPE_CRC_SOURCE_PLANE7:
525 	case INTEL_PIPE_CRC_SOURCE_NONE:
526 		return 0;
527 	default:
528 		return -EINVAL;
529 	}
530 }
531 
532 static int
533 intel_is_valid_crc_source(struct drm_i915_private *dev_priv,
534 			  const enum intel_pipe_crc_source source)
535 {
536 	if (DISPLAY_VER(dev_priv) == 2)
537 		return i8xx_crc_source_valid(dev_priv, source);
538 	else if (DISPLAY_VER(dev_priv) < 5)
539 		return i9xx_crc_source_valid(dev_priv, source);
540 	else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
541 		return vlv_crc_source_valid(dev_priv, source);
542 	else if (IS_IRONLAKE(dev_priv) || IS_SANDYBRIDGE(dev_priv))
543 		return ilk_crc_source_valid(dev_priv, source);
544 	else if (DISPLAY_VER(dev_priv) < 9)
545 		return ivb_crc_source_valid(dev_priv, source);
546 	else
547 		return skl_crc_source_valid(dev_priv, source);
548 }
549 
550 const char *const *intel_crtc_get_crc_sources(struct drm_crtc *crtc,
551 					      size_t *count)
552 {
553 	*count = ARRAY_SIZE(pipe_crc_sources);
554 	return pipe_crc_sources;
555 }
556 
557 int intel_crtc_verify_crc_source(struct drm_crtc *crtc, const char *source_name,
558 				 size_t *values_cnt)
559 {
560 	struct drm_i915_private *dev_priv = to_i915(crtc->dev);
561 	enum intel_pipe_crc_source source;
562 
563 	if (display_crc_ctl_parse_source(source_name, &source) < 0) {
564 		drm_dbg(&dev_priv->drm, "unknown source %s\n", source_name);
565 		return -EINVAL;
566 	}
567 
568 	if (source == INTEL_PIPE_CRC_SOURCE_AUTO ||
569 	    intel_is_valid_crc_source(dev_priv, source) == 0) {
570 		*values_cnt = 5;
571 		return 0;
572 	}
573 
574 	return -EINVAL;
575 }
576 
577 int intel_crtc_set_crc_source(struct drm_crtc *_crtc, const char *source_name)
578 {
579 	struct intel_crtc *crtc = to_intel_crtc(_crtc);
580 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
581 	struct intel_pipe_crc *pipe_crc = &crtc->pipe_crc;
582 	enum intel_display_power_domain power_domain;
583 	enum intel_pipe_crc_source source;
584 	enum pipe pipe = crtc->pipe;
585 	intel_wakeref_t wakeref;
586 	u32 val = 0; /* shut up gcc */
587 	int ret = 0;
588 	bool enable;
589 
590 	if (display_crc_ctl_parse_source(source_name, &source) < 0) {
591 		drm_dbg(&dev_priv->drm, "unknown source %s\n", source_name);
592 		return -EINVAL;
593 	}
594 
595 	power_domain = POWER_DOMAIN_PIPE(pipe);
596 	wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
597 	if (!wakeref) {
598 		drm_dbg_kms(&dev_priv->drm,
599 			    "Trying to capture CRC while pipe is off\n");
600 		return -EIO;
601 	}
602 
603 	enable = source != INTEL_PIPE_CRC_SOURCE_NONE;
604 	if (enable)
605 		intel_crtc_crc_setup_workarounds(crtc, true);
606 
607 	ret = get_new_crc_ctl_reg(dev_priv, pipe, &source, &val);
608 	if (ret != 0)
609 		goto out;
610 
611 	pipe_crc->source = source;
612 	intel_de_write(dev_priv, PIPE_CRC_CTL(dev_priv, pipe), val);
613 	intel_de_posting_read(dev_priv, PIPE_CRC_CTL(dev_priv, pipe));
614 
615 	if (!source) {
616 		if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
617 			vlv_undo_pipe_scramble_reset(dev_priv, pipe);
618 	}
619 
620 	pipe_crc->skipped = 0;
621 
622 out:
623 	if (!enable)
624 		intel_crtc_crc_setup_workarounds(crtc, false);
625 
626 	intel_display_power_put(dev_priv, power_domain, wakeref);
627 
628 	return ret;
629 }
630 
631 void intel_crtc_enable_pipe_crc(struct intel_crtc *crtc)
632 {
633 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
634 	struct intel_pipe_crc *pipe_crc = &crtc->pipe_crc;
635 	enum pipe pipe = crtc->pipe;
636 	u32 val = 0;
637 
638 	if (!crtc->base.crc.opened)
639 		return;
640 
641 	if (get_new_crc_ctl_reg(dev_priv, pipe, &pipe_crc->source, &val) < 0)
642 		return;
643 
644 	/* Don't need pipe_crc->lock here, IRQs are not generated. */
645 	pipe_crc->skipped = 0;
646 
647 	intel_de_write(dev_priv, PIPE_CRC_CTL(dev_priv, pipe), val);
648 	intel_de_posting_read(dev_priv, PIPE_CRC_CTL(dev_priv, pipe));
649 }
650 
651 void intel_crtc_disable_pipe_crc(struct intel_crtc *crtc)
652 {
653 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
654 	struct intel_pipe_crc *pipe_crc = &crtc->pipe_crc;
655 	enum pipe pipe = crtc->pipe;
656 
657 	/* Swallow crc's until we stop generating them. */
658 	spin_lock_irq(&pipe_crc->lock);
659 	pipe_crc->skipped = INT_MIN;
660 	spin_unlock_irq(&pipe_crc->lock);
661 
662 	intel_de_write(dev_priv, PIPE_CRC_CTL(dev_priv, pipe), 0);
663 	intel_de_posting_read(dev_priv, PIPE_CRC_CTL(dev_priv, pipe));
664 	intel_synchronize_irq(dev_priv);
665 }
666