1 /* 2 * Copyright © 2013 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 * Author: Damien Lespiau <damien.lespiau@intel.com> 24 * 25 */ 26 27 #include <linux/ctype.h> 28 #include <linux/debugfs.h> 29 #include <linux/seq_file.h> 30 31 #include "i915_irq.h" 32 #include "i915_reg.h" 33 #include "intel_atomic.h" 34 #include "intel_de.h" 35 #include "intel_display_irq.h" 36 #include "intel_display_types.h" 37 #include "intel_pipe_crc.h" 38 #include "intel_pipe_crc_regs.h" 39 40 static const char * const pipe_crc_sources[] = { 41 [INTEL_PIPE_CRC_SOURCE_NONE] = "none", 42 [INTEL_PIPE_CRC_SOURCE_PLANE1] = "plane1", 43 [INTEL_PIPE_CRC_SOURCE_PLANE2] = "plane2", 44 [INTEL_PIPE_CRC_SOURCE_PLANE3] = "plane3", 45 [INTEL_PIPE_CRC_SOURCE_PLANE4] = "plane4", 46 [INTEL_PIPE_CRC_SOURCE_PLANE5] = "plane5", 47 [INTEL_PIPE_CRC_SOURCE_PLANE6] = "plane6", 48 [INTEL_PIPE_CRC_SOURCE_PLANE7] = "plane7", 49 [INTEL_PIPE_CRC_SOURCE_PIPE] = "pipe", 50 [INTEL_PIPE_CRC_SOURCE_TV] = "TV", 51 [INTEL_PIPE_CRC_SOURCE_DP_B] = "DP-B", 52 [INTEL_PIPE_CRC_SOURCE_DP_C] = "DP-C", 53 [INTEL_PIPE_CRC_SOURCE_DP_D] = "DP-D", 54 [INTEL_PIPE_CRC_SOURCE_AUTO] = "auto", 55 }; 56 57 static int i8xx_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source, 58 u32 *val) 59 { 60 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) 61 *source = INTEL_PIPE_CRC_SOURCE_PIPE; 62 63 switch (*source) { 64 case INTEL_PIPE_CRC_SOURCE_PIPE: 65 *val = PIPE_CRC_ENABLE | PIPE_CRC_INCLUDE_BORDER_I8XX; 66 break; 67 case INTEL_PIPE_CRC_SOURCE_NONE: 68 *val = 0; 69 break; 70 default: 71 return -EINVAL; 72 } 73 74 return 0; 75 } 76 77 static void i9xx_pipe_crc_auto_source(struct drm_i915_private *dev_priv, 78 enum pipe pipe, 79 enum intel_pipe_crc_source *source) 80 { 81 struct intel_encoder *encoder; 82 struct intel_crtc *crtc; 83 struct intel_digital_port *dig_port; 84 85 *source = INTEL_PIPE_CRC_SOURCE_PIPE; 86 87 drm_modeset_lock_all(&dev_priv->drm); 88 for_each_intel_encoder(&dev_priv->drm, encoder) { 89 if (!encoder->base.crtc) 90 continue; 91 92 crtc = to_intel_crtc(encoder->base.crtc); 93 94 if (crtc->pipe != pipe) 95 continue; 96 97 switch (encoder->type) { 98 case INTEL_OUTPUT_TVOUT: 99 *source = INTEL_PIPE_CRC_SOURCE_TV; 100 break; 101 case INTEL_OUTPUT_DP: 102 case INTEL_OUTPUT_EDP: 103 dig_port = enc_to_dig_port(encoder); 104 switch (dig_port->base.port) { 105 case PORT_B: 106 *source = INTEL_PIPE_CRC_SOURCE_DP_B; 107 break; 108 case PORT_C: 109 *source = INTEL_PIPE_CRC_SOURCE_DP_C; 110 break; 111 case PORT_D: 112 *source = INTEL_PIPE_CRC_SOURCE_DP_D; 113 break; 114 default: 115 drm_WARN(&dev_priv->drm, 1, "nonexisting DP port %c\n", 116 port_name(dig_port->base.port)); 117 break; 118 } 119 break; 120 default: 121 break; 122 } 123 } 124 drm_modeset_unlock_all(&dev_priv->drm); 125 } 126 127 static int vlv_pipe_crc_ctl_reg(struct drm_i915_private *dev_priv, 128 enum pipe pipe, 129 enum intel_pipe_crc_source *source, 130 u32 *val) 131 { 132 bool need_stable_symbols = false; 133 134 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) 135 i9xx_pipe_crc_auto_source(dev_priv, pipe, source); 136 137 switch (*source) { 138 case INTEL_PIPE_CRC_SOURCE_PIPE: 139 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_VLV; 140 break; 141 case INTEL_PIPE_CRC_SOURCE_DP_B: 142 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_VLV; 143 need_stable_symbols = true; 144 break; 145 case INTEL_PIPE_CRC_SOURCE_DP_C: 146 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_VLV; 147 need_stable_symbols = true; 148 break; 149 case INTEL_PIPE_CRC_SOURCE_DP_D: 150 if (!IS_CHERRYVIEW(dev_priv)) 151 return -EINVAL; 152 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_VLV; 153 need_stable_symbols = true; 154 break; 155 case INTEL_PIPE_CRC_SOURCE_NONE: 156 *val = 0; 157 break; 158 default: 159 return -EINVAL; 160 } 161 162 /* 163 * When the pipe CRC tap point is after the transcoders we need 164 * to tweak symbol-level features to produce a deterministic series of 165 * symbols for a given frame. We need to reset those features only once 166 * a frame (instead of every nth symbol): 167 * - DC-balance: used to ensure a better clock recovery from the data 168 * link (SDVO) 169 * - DisplayPort scrambling: used for EMI reduction 170 */ 171 if (need_stable_symbols) { 172 u32 tmp = intel_de_read(dev_priv, PORT_DFT2_G4X(dev_priv)); 173 174 tmp |= DC_BALANCE_RESET_VLV; 175 switch (pipe) { 176 case PIPE_A: 177 tmp |= PIPE_A_SCRAMBLE_RESET; 178 break; 179 case PIPE_B: 180 tmp |= PIPE_B_SCRAMBLE_RESET; 181 break; 182 case PIPE_C: 183 tmp |= PIPE_C_SCRAMBLE_RESET; 184 break; 185 default: 186 return -EINVAL; 187 } 188 intel_de_write(dev_priv, PORT_DFT2_G4X(dev_priv), tmp); 189 } 190 191 return 0; 192 } 193 194 static int i9xx_pipe_crc_ctl_reg(struct drm_i915_private *dev_priv, 195 enum pipe pipe, 196 enum intel_pipe_crc_source *source, 197 u32 *val) 198 { 199 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) 200 i9xx_pipe_crc_auto_source(dev_priv, pipe, source); 201 202 switch (*source) { 203 case INTEL_PIPE_CRC_SOURCE_PIPE: 204 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_I9XX; 205 break; 206 case INTEL_PIPE_CRC_SOURCE_TV: 207 if (!SUPPORTS_TV(dev_priv)) 208 return -EINVAL; 209 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_TV_PRE; 210 break; 211 case INTEL_PIPE_CRC_SOURCE_NONE: 212 *val = 0; 213 break; 214 default: 215 /* 216 * The DP CRC source doesn't work on g4x. 217 * It can be made to work to some degree by selecting 218 * the correct CRC source before the port is enabled, 219 * and not touching the CRC source bits again until 220 * the port is disabled. But even then the bits 221 * eventually get stuck and a reboot is needed to get 222 * working CRCs on the pipe again. Let's simply 223 * refuse to use DP CRCs on g4x. 224 */ 225 return -EINVAL; 226 } 227 228 return 0; 229 } 230 231 static void vlv_undo_pipe_scramble_reset(struct drm_i915_private *dev_priv, 232 enum pipe pipe) 233 { 234 u32 tmp = intel_de_read(dev_priv, PORT_DFT2_G4X(dev_priv)); 235 236 switch (pipe) { 237 case PIPE_A: 238 tmp &= ~PIPE_A_SCRAMBLE_RESET; 239 break; 240 case PIPE_B: 241 tmp &= ~PIPE_B_SCRAMBLE_RESET; 242 break; 243 case PIPE_C: 244 tmp &= ~PIPE_C_SCRAMBLE_RESET; 245 break; 246 default: 247 return; 248 } 249 if (!(tmp & PIPE_SCRAMBLE_RESET_MASK)) 250 tmp &= ~DC_BALANCE_RESET_VLV; 251 intel_de_write(dev_priv, PORT_DFT2_G4X(dev_priv), tmp); 252 } 253 254 static int ilk_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source, 255 u32 *val) 256 { 257 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) 258 *source = INTEL_PIPE_CRC_SOURCE_PIPE; 259 260 switch (*source) { 261 case INTEL_PIPE_CRC_SOURCE_PLANE1: 262 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_ILK; 263 break; 264 case INTEL_PIPE_CRC_SOURCE_PLANE2: 265 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_ILK; 266 break; 267 case INTEL_PIPE_CRC_SOURCE_PIPE: 268 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_ILK; 269 break; 270 case INTEL_PIPE_CRC_SOURCE_NONE: 271 *val = 0; 272 break; 273 default: 274 return -EINVAL; 275 } 276 277 return 0; 278 } 279 280 static void 281 intel_crtc_crc_setup_workarounds(struct intel_crtc *crtc, bool enable) 282 { 283 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 284 struct intel_crtc_state *pipe_config; 285 struct drm_atomic_state *state; 286 struct drm_modeset_acquire_ctx ctx; 287 int ret; 288 289 if (IS_I945GM(dev_priv) || IS_I915GM(dev_priv)) 290 i915gm_irq_cstate_wa(dev_priv, enable); 291 292 drm_modeset_acquire_init(&ctx, 0); 293 294 state = drm_atomic_state_alloc(&dev_priv->drm); 295 if (!state) { 296 ret = -ENOMEM; 297 goto unlock; 298 } 299 300 state->acquire_ctx = &ctx; 301 to_intel_atomic_state(state)->internal = true; 302 303 retry: 304 pipe_config = intel_atomic_get_crtc_state(state, crtc); 305 if (IS_ERR(pipe_config)) { 306 ret = PTR_ERR(pipe_config); 307 goto put_state; 308 } 309 310 pipe_config->uapi.mode_changed = pipe_config->has_psr; 311 pipe_config->crc_enabled = enable; 312 313 if (IS_HASWELL(dev_priv) && 314 pipe_config->hw.active && crtc->pipe == PIPE_A && 315 pipe_config->cpu_transcoder == TRANSCODER_EDP) 316 pipe_config->uapi.mode_changed = true; 317 318 ret = drm_atomic_commit(state); 319 320 put_state: 321 if (ret == -EDEADLK) { 322 drm_atomic_state_clear(state); 323 drm_modeset_backoff(&ctx); 324 goto retry; 325 } 326 327 drm_atomic_state_put(state); 328 unlock: 329 drm_WARN(&dev_priv->drm, ret, 330 "Toggling workaround to %i returns %i\n", enable, ret); 331 drm_modeset_drop_locks(&ctx); 332 drm_modeset_acquire_fini(&ctx); 333 } 334 335 static int ivb_pipe_crc_ctl_reg(struct drm_i915_private *dev_priv, 336 enum pipe pipe, 337 enum intel_pipe_crc_source *source, 338 u32 *val) 339 { 340 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) 341 *source = INTEL_PIPE_CRC_SOURCE_PIPE; 342 343 switch (*source) { 344 case INTEL_PIPE_CRC_SOURCE_PLANE1: 345 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_IVB; 346 break; 347 case INTEL_PIPE_CRC_SOURCE_PLANE2: 348 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_IVB; 349 break; 350 case INTEL_PIPE_CRC_SOURCE_PIPE: 351 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PF_IVB; 352 break; 353 case INTEL_PIPE_CRC_SOURCE_NONE: 354 *val = 0; 355 break; 356 default: 357 return -EINVAL; 358 } 359 360 return 0; 361 } 362 363 static int skl_pipe_crc_ctl_reg(struct drm_i915_private *dev_priv, 364 enum pipe pipe, 365 enum intel_pipe_crc_source *source, 366 u32 *val) 367 { 368 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) 369 *source = INTEL_PIPE_CRC_SOURCE_PIPE; 370 371 switch (*source) { 372 case INTEL_PIPE_CRC_SOURCE_PLANE1: 373 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PLANE_1_SKL; 374 break; 375 case INTEL_PIPE_CRC_SOURCE_PLANE2: 376 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PLANE_2_SKL; 377 break; 378 case INTEL_PIPE_CRC_SOURCE_PLANE3: 379 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PLANE_3_SKL; 380 break; 381 case INTEL_PIPE_CRC_SOURCE_PLANE4: 382 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PLANE_4_SKL; 383 break; 384 case INTEL_PIPE_CRC_SOURCE_PLANE5: 385 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PLANE_5_SKL; 386 break; 387 case INTEL_PIPE_CRC_SOURCE_PLANE6: 388 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PLANE_6_SKL; 389 break; 390 case INTEL_PIPE_CRC_SOURCE_PLANE7: 391 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PLANE_7_SKL; 392 break; 393 case INTEL_PIPE_CRC_SOURCE_PIPE: 394 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DMUX_SKL; 395 break; 396 case INTEL_PIPE_CRC_SOURCE_NONE: 397 *val = 0; 398 break; 399 default: 400 return -EINVAL; 401 } 402 403 return 0; 404 } 405 406 static int get_new_crc_ctl_reg(struct drm_i915_private *dev_priv, 407 enum pipe pipe, 408 enum intel_pipe_crc_source *source, u32 *val) 409 { 410 if (DISPLAY_VER(dev_priv) == 2) 411 return i8xx_pipe_crc_ctl_reg(source, val); 412 else if (DISPLAY_VER(dev_priv) < 5) 413 return i9xx_pipe_crc_ctl_reg(dev_priv, pipe, source, val); 414 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) 415 return vlv_pipe_crc_ctl_reg(dev_priv, pipe, source, val); 416 else if (IS_IRONLAKE(dev_priv) || IS_SANDYBRIDGE(dev_priv)) 417 return ilk_pipe_crc_ctl_reg(source, val); 418 else if (DISPLAY_VER(dev_priv) < 9) 419 return ivb_pipe_crc_ctl_reg(dev_priv, pipe, source, val); 420 else 421 return skl_pipe_crc_ctl_reg(dev_priv, pipe, source, val); 422 } 423 424 static int 425 display_crc_ctl_parse_source(const char *buf, enum intel_pipe_crc_source *s) 426 { 427 int i; 428 429 if (!buf) { 430 *s = INTEL_PIPE_CRC_SOURCE_NONE; 431 return 0; 432 } 433 434 i = match_string(pipe_crc_sources, ARRAY_SIZE(pipe_crc_sources), buf); 435 if (i < 0) 436 return i; 437 438 *s = i; 439 return 0; 440 } 441 442 void intel_crtc_crc_init(struct intel_crtc *crtc) 443 { 444 struct intel_pipe_crc *pipe_crc = &crtc->pipe_crc; 445 446 spin_lock_init(&pipe_crc->lock); 447 } 448 449 static int i8xx_crc_source_valid(struct drm_i915_private *dev_priv, 450 const enum intel_pipe_crc_source source) 451 { 452 switch (source) { 453 case INTEL_PIPE_CRC_SOURCE_PIPE: 454 case INTEL_PIPE_CRC_SOURCE_NONE: 455 return 0; 456 default: 457 return -EINVAL; 458 } 459 } 460 461 static int i9xx_crc_source_valid(struct drm_i915_private *dev_priv, 462 const enum intel_pipe_crc_source source) 463 { 464 switch (source) { 465 case INTEL_PIPE_CRC_SOURCE_PIPE: 466 case INTEL_PIPE_CRC_SOURCE_TV: 467 case INTEL_PIPE_CRC_SOURCE_NONE: 468 return 0; 469 default: 470 return -EINVAL; 471 } 472 } 473 474 static int vlv_crc_source_valid(struct drm_i915_private *dev_priv, 475 const enum intel_pipe_crc_source source) 476 { 477 switch (source) { 478 case INTEL_PIPE_CRC_SOURCE_PIPE: 479 case INTEL_PIPE_CRC_SOURCE_DP_B: 480 case INTEL_PIPE_CRC_SOURCE_DP_C: 481 case INTEL_PIPE_CRC_SOURCE_DP_D: 482 case INTEL_PIPE_CRC_SOURCE_NONE: 483 return 0; 484 default: 485 return -EINVAL; 486 } 487 } 488 489 static int ilk_crc_source_valid(struct drm_i915_private *dev_priv, 490 const enum intel_pipe_crc_source source) 491 { 492 switch (source) { 493 case INTEL_PIPE_CRC_SOURCE_PIPE: 494 case INTEL_PIPE_CRC_SOURCE_PLANE1: 495 case INTEL_PIPE_CRC_SOURCE_PLANE2: 496 case INTEL_PIPE_CRC_SOURCE_NONE: 497 return 0; 498 default: 499 return -EINVAL; 500 } 501 } 502 503 static int ivb_crc_source_valid(struct drm_i915_private *dev_priv, 504 const enum intel_pipe_crc_source source) 505 { 506 switch (source) { 507 case INTEL_PIPE_CRC_SOURCE_PIPE: 508 case INTEL_PIPE_CRC_SOURCE_PLANE1: 509 case INTEL_PIPE_CRC_SOURCE_PLANE2: 510 case INTEL_PIPE_CRC_SOURCE_NONE: 511 return 0; 512 default: 513 return -EINVAL; 514 } 515 } 516 517 static int skl_crc_source_valid(struct drm_i915_private *dev_priv, 518 const enum intel_pipe_crc_source source) 519 { 520 switch (source) { 521 case INTEL_PIPE_CRC_SOURCE_PIPE: 522 case INTEL_PIPE_CRC_SOURCE_PLANE1: 523 case INTEL_PIPE_CRC_SOURCE_PLANE2: 524 case INTEL_PIPE_CRC_SOURCE_PLANE3: 525 case INTEL_PIPE_CRC_SOURCE_PLANE4: 526 case INTEL_PIPE_CRC_SOURCE_PLANE5: 527 case INTEL_PIPE_CRC_SOURCE_PLANE6: 528 case INTEL_PIPE_CRC_SOURCE_PLANE7: 529 case INTEL_PIPE_CRC_SOURCE_NONE: 530 return 0; 531 default: 532 return -EINVAL; 533 } 534 } 535 536 static int 537 intel_is_valid_crc_source(struct drm_i915_private *dev_priv, 538 const enum intel_pipe_crc_source source) 539 { 540 if (DISPLAY_VER(dev_priv) == 2) 541 return i8xx_crc_source_valid(dev_priv, source); 542 else if (DISPLAY_VER(dev_priv) < 5) 543 return i9xx_crc_source_valid(dev_priv, source); 544 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) 545 return vlv_crc_source_valid(dev_priv, source); 546 else if (IS_IRONLAKE(dev_priv) || IS_SANDYBRIDGE(dev_priv)) 547 return ilk_crc_source_valid(dev_priv, source); 548 else if (DISPLAY_VER(dev_priv) < 9) 549 return ivb_crc_source_valid(dev_priv, source); 550 else 551 return skl_crc_source_valid(dev_priv, source); 552 } 553 554 const char *const *intel_crtc_get_crc_sources(struct drm_crtc *crtc, 555 size_t *count) 556 { 557 *count = ARRAY_SIZE(pipe_crc_sources); 558 return pipe_crc_sources; 559 } 560 561 int intel_crtc_verify_crc_source(struct drm_crtc *crtc, const char *source_name, 562 size_t *values_cnt) 563 { 564 struct drm_i915_private *dev_priv = to_i915(crtc->dev); 565 enum intel_pipe_crc_source source; 566 567 if (display_crc_ctl_parse_source(source_name, &source) < 0) { 568 drm_dbg(&dev_priv->drm, "unknown source %s\n", source_name); 569 return -EINVAL; 570 } 571 572 if (source == INTEL_PIPE_CRC_SOURCE_AUTO || 573 intel_is_valid_crc_source(dev_priv, source) == 0) { 574 *values_cnt = 5; 575 return 0; 576 } 577 578 return -EINVAL; 579 } 580 581 int intel_crtc_set_crc_source(struct drm_crtc *_crtc, const char *source_name) 582 { 583 struct intel_crtc *crtc = to_intel_crtc(_crtc); 584 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 585 struct intel_pipe_crc *pipe_crc = &crtc->pipe_crc; 586 enum intel_display_power_domain power_domain; 587 enum intel_pipe_crc_source source; 588 enum pipe pipe = crtc->pipe; 589 intel_wakeref_t wakeref; 590 u32 val = 0; /* shut up gcc */ 591 int ret = 0; 592 bool enable; 593 594 if (display_crc_ctl_parse_source(source_name, &source) < 0) { 595 drm_dbg(&dev_priv->drm, "unknown source %s\n", source_name); 596 return -EINVAL; 597 } 598 599 power_domain = POWER_DOMAIN_PIPE(pipe); 600 wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain); 601 if (!wakeref) { 602 drm_dbg_kms(&dev_priv->drm, 603 "Trying to capture CRC while pipe is off\n"); 604 return -EIO; 605 } 606 607 enable = source != INTEL_PIPE_CRC_SOURCE_NONE; 608 if (enable) 609 intel_crtc_crc_setup_workarounds(crtc, true); 610 611 ret = get_new_crc_ctl_reg(dev_priv, pipe, &source, &val); 612 if (ret != 0) 613 goto out; 614 615 pipe_crc->source = source; 616 intel_de_write(dev_priv, PIPE_CRC_CTL(dev_priv, pipe), val); 617 intel_de_posting_read(dev_priv, PIPE_CRC_CTL(dev_priv, pipe)); 618 619 if (!source) { 620 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) 621 vlv_undo_pipe_scramble_reset(dev_priv, pipe); 622 } 623 624 pipe_crc->skipped = 0; 625 626 out: 627 if (!enable) 628 intel_crtc_crc_setup_workarounds(crtc, false); 629 630 intel_display_power_put(dev_priv, power_domain, wakeref); 631 632 return ret; 633 } 634 635 void intel_crtc_enable_pipe_crc(struct intel_crtc *crtc) 636 { 637 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 638 struct intel_pipe_crc *pipe_crc = &crtc->pipe_crc; 639 enum pipe pipe = crtc->pipe; 640 u32 val = 0; 641 642 if (!crtc->base.crc.opened) 643 return; 644 645 if (get_new_crc_ctl_reg(dev_priv, pipe, &pipe_crc->source, &val) < 0) 646 return; 647 648 /* Don't need pipe_crc->lock here, IRQs are not generated. */ 649 pipe_crc->skipped = 0; 650 651 intel_de_write(dev_priv, PIPE_CRC_CTL(dev_priv, pipe), val); 652 intel_de_posting_read(dev_priv, PIPE_CRC_CTL(dev_priv, pipe)); 653 } 654 655 void intel_crtc_disable_pipe_crc(struct intel_crtc *crtc) 656 { 657 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 658 struct intel_pipe_crc *pipe_crc = &crtc->pipe_crc; 659 enum pipe pipe = crtc->pipe; 660 661 /* Swallow crc's until we stop generating them. */ 662 spin_lock_irq(&pipe_crc->lock); 663 pipe_crc->skipped = INT_MIN; 664 spin_unlock_irq(&pipe_crc->lock); 665 666 intel_de_write(dev_priv, PIPE_CRC_CTL(dev_priv, pipe), 0); 667 intel_de_posting_read(dev_priv, PIPE_CRC_CTL(dev_priv, pipe)); 668 intel_synchronize_irq(dev_priv); 669 } 670