1*24abc472SJani Nikula /* SPDX-License-Identifier: MIT */ 2*24abc472SJani Nikula /* Copyright © 2025 Intel Corporation */ 3*24abc472SJani Nikula 4*24abc472SJani Nikula #ifndef __INTEL_PFIT_REGS_H__ 5*24abc472SJani Nikula #define __INTEL_PFIT_REGS_H__ 6*24abc472SJani Nikula 7*24abc472SJani Nikula #include "intel_display_reg_defs.h" 8*24abc472SJani Nikula 9*24abc472SJani Nikula /* Panel fitting */ 10*24abc472SJani Nikula #define PFIT_CONTROL(dev_priv) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61230) 11*24abc472SJani Nikula #define PFIT_ENABLE REG_BIT(31) 12*24abc472SJani Nikula #define PFIT_PIPE_MASK REG_GENMASK(30, 29) /* 965+ */ 13*24abc472SJani Nikula #define PFIT_PIPE(pipe) REG_FIELD_PREP(PFIT_PIPE_MASK, (pipe)) 14*24abc472SJani Nikula #define PFIT_SCALING_MASK REG_GENMASK(28, 26) /* 965+ */ 15*24abc472SJani Nikula #define PFIT_SCALING_AUTO REG_FIELD_PREP(PFIT_SCALING_MASK, 0) 16*24abc472SJani Nikula #define PFIT_SCALING_PROGRAMMED REG_FIELD_PREP(PFIT_SCALING_MASK, 1) 17*24abc472SJani Nikula #define PFIT_SCALING_PILLAR REG_FIELD_PREP(PFIT_SCALING_MASK, 2) 18*24abc472SJani Nikula #define PFIT_SCALING_LETTER REG_FIELD_PREP(PFIT_SCALING_MASK, 3) 19*24abc472SJani Nikula #define PFIT_FILTER_MASK REG_GENMASK(25, 24) /* 965+ */ 20*24abc472SJani Nikula #define PFIT_FILTER_FUZZY REG_FIELD_PREP(PFIT_FILTER_MASK, 0) 21*24abc472SJani Nikula #define PFIT_FILTER_CRISP REG_FIELD_PREP(PFIT_FILTER_MASK, 1) 22*24abc472SJani Nikula #define PFIT_FILTER_MEDIAN REG_FIELD_PREP(PFIT_FILTER_MASK, 2) 23*24abc472SJani Nikula #define PFIT_VERT_INTERP_MASK REG_GENMASK(11, 10) /* pre-965 */ 24*24abc472SJani Nikula #define PFIT_VERT_INTERP_BILINEAR REG_FIELD_PREP(PFIT_VERT_INTERP_MASK, 1) 25*24abc472SJani Nikula #define PFIT_VERT_AUTO_SCALE REG_BIT(9) /* pre-965 */ 26*24abc472SJani Nikula #define PFIT_HORIZ_INTERP_MASK REG_GENMASK(7, 6) /* pre-965 */ 27*24abc472SJani Nikula #define PFIT_HORIZ_INTERP_BILINEAR REG_FIELD_PREP(PFIT_HORIZ_INTERP_MASK, 1) 28*24abc472SJani Nikula #define PFIT_HORIZ_AUTO_SCALE REG_BIT(5) /* pre-965 */ 29*24abc472SJani Nikula #define PFIT_PANEL_8TO6_DITHER_ENABLE REG_BIT(3) /* pre-965 */ 30*24abc472SJani Nikula 31*24abc472SJani Nikula #define PFIT_PGM_RATIOS(dev_priv) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61234) 32*24abc472SJani Nikula #define PFIT_VERT_SCALE_MASK REG_GENMASK(31, 20) /* pre-965 */ 33*24abc472SJani Nikula #define PFIT_VERT_SCALE(x) REG_FIELD_PREP(PFIT_VERT_SCALE_MASK, (x)) 34*24abc472SJani Nikula #define PFIT_HORIZ_SCALE_MASK REG_GENMASK(15, 4) /* pre-965 */ 35*24abc472SJani Nikula #define PFIT_HORIZ_SCALE(x) REG_FIELD_PREP(PFIT_HORIZ_SCALE_MASK, (x)) 36*24abc472SJani Nikula #define PFIT_VERT_SCALE_MASK_965 REG_GENMASK(28, 16) /* 965+ */ 37*24abc472SJani Nikula #define PFIT_HORIZ_SCALE_MASK_965 REG_GENMASK(12, 0) /* 965+ */ 38*24abc472SJani Nikula 39*24abc472SJani Nikula #define PFIT_AUTO_RATIOS(dev_priv) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61238) 40*24abc472SJani Nikula 41*24abc472SJani Nikula /* CPU panel fitter */ 42*24abc472SJani Nikula /* IVB+ has 3 fitters, 0 is 7x5 capable, the other two only 3x3 */ 43*24abc472SJani Nikula #define _PFA_CTL_1 0x68080 44*24abc472SJani Nikula #define _PFB_CTL_1 0x68880 45*24abc472SJani Nikula #define PF_CTL(pipe) _MMIO_PIPE(pipe, _PFA_CTL_1, _PFB_CTL_1) 46*24abc472SJani Nikula #define PF_ENABLE REG_BIT(31) 47*24abc472SJani Nikula #define PF_PIPE_SEL_MASK_IVB REG_GENMASK(30, 29) /* ivb/hsw */ 48*24abc472SJani Nikula #define PF_PIPE_SEL_IVB(pipe) REG_FIELD_PREP(PF_PIPE_SEL_MASK_IVB, (pipe)) 49*24abc472SJani Nikula #define PF_FILTER_MASK REG_GENMASK(24, 23) 50*24abc472SJani Nikula #define PF_FILTER_PROGRAMMED REG_FIELD_PREP(PF_FILTER_MASK, 0) 51*24abc472SJani Nikula #define PF_FILTER_MED_3x3 REG_FIELD_PREP(PF_FILTER_MASK, 1) 52*24abc472SJani Nikula #define PF_FILTER_EDGE_ENHANCE REG_FIELD_PREP(PF_FILTER_EDGE_MASK, 2) 53*24abc472SJani Nikula #define PF_FILTER_EDGE_SOFTEN REG_FIELD_PREP(PF_FILTER_EDGE_MASK, 3) 54*24abc472SJani Nikula 55*24abc472SJani Nikula #define _PFA_WIN_SZ 0x68074 56*24abc472SJani Nikula #define _PFB_WIN_SZ 0x68874 57*24abc472SJani Nikula #define PF_WIN_SZ(pipe) _MMIO_PIPE(pipe, _PFA_WIN_SZ, _PFB_WIN_SZ) 58*24abc472SJani Nikula #define PF_WIN_XSIZE_MASK REG_GENMASK(31, 16) 59*24abc472SJani Nikula #define PF_WIN_XSIZE(w) REG_FIELD_PREP(PF_WIN_XSIZE_MASK, (w)) 60*24abc472SJani Nikula #define PF_WIN_YSIZE_MASK REG_GENMASK(15, 0) 61*24abc472SJani Nikula #define PF_WIN_YSIZE(h) REG_FIELD_PREP(PF_WIN_YSIZE_MASK, (h)) 62*24abc472SJani Nikula 63*24abc472SJani Nikula #define _PFA_WIN_POS 0x68070 64*24abc472SJani Nikula #define _PFB_WIN_POS 0x68870 65*24abc472SJani Nikula #define PF_WIN_POS(pipe) _MMIO_PIPE(pipe, _PFA_WIN_POS, _PFB_WIN_POS) 66*24abc472SJani Nikula #define PF_WIN_XPOS_MASK REG_GENMASK(31, 16) 67*24abc472SJani Nikula #define PF_WIN_XPOS(x) REG_FIELD_PREP(PF_WIN_XPOS_MASK, (x)) 68*24abc472SJani Nikula #define PF_WIN_YPOS_MASK REG_GENMASK(15, 0) 69*24abc472SJani Nikula #define PF_WIN_YPOS(y) REG_FIELD_PREP(PF_WIN_YPOS_MASK, (y)) 70*24abc472SJani Nikula 71*24abc472SJani Nikula #define _PFA_VSCALE 0x68084 72*24abc472SJani Nikula #define _PFB_VSCALE 0x68884 73*24abc472SJani Nikula #define PF_VSCALE(pipe) _MMIO_PIPE(pipe, _PFA_VSCALE, _PFB_VSCALE) 74*24abc472SJani Nikula 75*24abc472SJani Nikula #define _PFA_HSCALE 0x68090 76*24abc472SJani Nikula #define _PFB_HSCALE 0x68890 77*24abc472SJani Nikula #define PF_HSCALE(pipe) _MMIO_PIPE(pipe, _PFA_HSCALE, _PFB_HSCALE) 78*24abc472SJani Nikula 79*24abc472SJani Nikula #endif /* __INTEL_PFIT_REGS_H__ */ 80