1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2021 Intel Corporation 4 */ 5 6 #include "g4x_dp.h" 7 #include "i915_drv.h" 8 #include "i915_reg.h" 9 #include "intel_crt.h" 10 #include "intel_crt_regs.h" 11 #include "intel_de.h" 12 #include "intel_display_types.h" 13 #include "intel_dpll.h" 14 #include "intel_fdi.h" 15 #include "intel_fdi_regs.h" 16 #include "intel_lvds.h" 17 #include "intel_lvds_regs.h" 18 #include "intel_pch_display.h" 19 #include "intel_pch_refclk.h" 20 #include "intel_pps.h" 21 #include "intel_sdvo.h" 22 23 bool intel_has_pch_trancoder(struct drm_i915_private *i915, 24 enum pipe pch_transcoder) 25 { 26 return HAS_PCH_IBX(i915) || HAS_PCH_CPT(i915) || 27 (HAS_PCH_LPT_H(i915) && pch_transcoder == PIPE_A); 28 } 29 30 enum pipe intel_crtc_pch_transcoder(struct intel_crtc *crtc) 31 { 32 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 33 34 if (HAS_PCH_LPT(i915)) 35 return PIPE_A; 36 else 37 return crtc->pipe; 38 } 39 40 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv, 41 enum pipe pipe, enum port port, 42 i915_reg_t dp_reg) 43 { 44 struct intel_display *display = &dev_priv->display; 45 enum pipe port_pipe; 46 bool state; 47 48 state = g4x_dp_port_enabled(display, dp_reg, port, &port_pipe); 49 50 INTEL_DISPLAY_STATE_WARN(display, state && port_pipe == pipe, 51 "PCH DP %c enabled on transcoder %c, should be disabled\n", 52 port_name(port), pipe_name(pipe)); 53 54 INTEL_DISPLAY_STATE_WARN(display, 55 HAS_PCH_IBX(dev_priv) && !state && port_pipe == PIPE_B, 56 "IBX PCH DP %c still using transcoder B\n", 57 port_name(port)); 58 } 59 60 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv, 61 enum pipe pipe, enum port port, 62 i915_reg_t hdmi_reg) 63 { 64 struct intel_display *display = &dev_priv->display; 65 enum pipe port_pipe; 66 bool state; 67 68 state = intel_sdvo_port_enabled(display, hdmi_reg, &port_pipe); 69 70 INTEL_DISPLAY_STATE_WARN(display, state && port_pipe == pipe, 71 "PCH HDMI %c enabled on transcoder %c, should be disabled\n", 72 port_name(port), pipe_name(pipe)); 73 74 INTEL_DISPLAY_STATE_WARN(display, 75 HAS_PCH_IBX(dev_priv) && !state && port_pipe == PIPE_B, 76 "IBX PCH HDMI %c still using transcoder B\n", 77 port_name(port)); 78 } 79 80 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv, 81 enum pipe pipe) 82 { 83 struct intel_display *display = &dev_priv->display; 84 enum pipe port_pipe; 85 86 assert_pch_dp_disabled(dev_priv, pipe, PORT_B, PCH_DP_B); 87 assert_pch_dp_disabled(dev_priv, pipe, PORT_C, PCH_DP_C); 88 assert_pch_dp_disabled(dev_priv, pipe, PORT_D, PCH_DP_D); 89 90 INTEL_DISPLAY_STATE_WARN(display, 91 intel_crt_port_enabled(display, PCH_ADPA, &port_pipe) && port_pipe == pipe, 92 "PCH VGA enabled on transcoder %c, should be disabled\n", 93 pipe_name(pipe)); 94 95 INTEL_DISPLAY_STATE_WARN(display, 96 intel_lvds_port_enabled(dev_priv, PCH_LVDS, &port_pipe) && port_pipe == pipe, 97 "PCH LVDS enabled on transcoder %c, should be disabled\n", 98 pipe_name(pipe)); 99 100 /* PCH SDVOB multiplex with HDMIB */ 101 assert_pch_hdmi_disabled(dev_priv, pipe, PORT_B, PCH_HDMIB); 102 assert_pch_hdmi_disabled(dev_priv, pipe, PORT_C, PCH_HDMIC); 103 assert_pch_hdmi_disabled(dev_priv, pipe, PORT_D, PCH_HDMID); 104 } 105 106 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv, 107 enum pipe pipe) 108 { 109 struct intel_display *display = &dev_priv->display; 110 u32 val; 111 bool enabled; 112 113 val = intel_de_read(display, PCH_TRANSCONF(pipe)); 114 enabled = !!(val & TRANS_ENABLE); 115 INTEL_DISPLAY_STATE_WARN(display, enabled, 116 "transcoder assertion failed, should be off on pipe %c but is still active\n", 117 pipe_name(pipe)); 118 } 119 120 static void ibx_sanitize_pch_hdmi_port(struct drm_i915_private *dev_priv, 121 enum port port, i915_reg_t hdmi_reg) 122 { 123 u32 val = intel_de_read(dev_priv, hdmi_reg); 124 125 if (val & SDVO_ENABLE || 126 (val & SDVO_PIPE_SEL_MASK) == SDVO_PIPE_SEL(PIPE_A)) 127 return; 128 129 drm_dbg_kms(&dev_priv->drm, 130 "Sanitizing transcoder select for HDMI %c\n", 131 port_name(port)); 132 133 val &= ~SDVO_PIPE_SEL_MASK; 134 val |= SDVO_PIPE_SEL(PIPE_A); 135 136 intel_de_write(dev_priv, hdmi_reg, val); 137 } 138 139 static void ibx_sanitize_pch_dp_port(struct drm_i915_private *dev_priv, 140 enum port port, i915_reg_t dp_reg) 141 { 142 u32 val = intel_de_read(dev_priv, dp_reg); 143 144 if (val & DP_PORT_EN || 145 (val & DP_PIPE_SEL_MASK) == DP_PIPE_SEL(PIPE_A)) 146 return; 147 148 drm_dbg_kms(&dev_priv->drm, 149 "Sanitizing transcoder select for DP %c\n", 150 port_name(port)); 151 152 val &= ~DP_PIPE_SEL_MASK; 153 val |= DP_PIPE_SEL(PIPE_A); 154 155 intel_de_write(dev_priv, dp_reg, val); 156 } 157 158 static void ibx_sanitize_pch_ports(struct drm_i915_private *dev_priv) 159 { 160 /* 161 * The BIOS may select transcoder B on some of the PCH 162 * ports even it doesn't enable the port. This would trip 163 * assert_pch_dp_disabled() and assert_pch_hdmi_disabled(). 164 * Sanitize the transcoder select bits to prevent that. We 165 * assume that the BIOS never actually enabled the port, 166 * because if it did we'd actually have to toggle the port 167 * on and back off to make the transcoder A select stick 168 * (see. intel_dp_link_down(), intel_disable_hdmi(), 169 * intel_disable_sdvo()). 170 */ 171 ibx_sanitize_pch_dp_port(dev_priv, PORT_B, PCH_DP_B); 172 ibx_sanitize_pch_dp_port(dev_priv, PORT_C, PCH_DP_C); 173 ibx_sanitize_pch_dp_port(dev_priv, PORT_D, PCH_DP_D); 174 175 /* PCH SDVOB multiplex with HDMIB */ 176 ibx_sanitize_pch_hdmi_port(dev_priv, PORT_B, PCH_HDMIB); 177 ibx_sanitize_pch_hdmi_port(dev_priv, PORT_C, PCH_HDMIC); 178 ibx_sanitize_pch_hdmi_port(dev_priv, PORT_D, PCH_HDMID); 179 } 180 181 static void intel_pch_transcoder_set_m1_n1(struct intel_crtc *crtc, 182 const struct intel_link_m_n *m_n) 183 { 184 struct intel_display *display = to_intel_display(crtc); 185 enum pipe pipe = crtc->pipe; 186 187 intel_set_m_n(display, m_n, 188 PCH_TRANS_DATA_M1(pipe), PCH_TRANS_DATA_N1(pipe), 189 PCH_TRANS_LINK_M1(pipe), PCH_TRANS_LINK_N1(pipe)); 190 } 191 192 static void intel_pch_transcoder_set_m2_n2(struct intel_crtc *crtc, 193 const struct intel_link_m_n *m_n) 194 { 195 struct intel_display *display = to_intel_display(crtc); 196 enum pipe pipe = crtc->pipe; 197 198 intel_set_m_n(display, m_n, 199 PCH_TRANS_DATA_M2(pipe), PCH_TRANS_DATA_N2(pipe), 200 PCH_TRANS_LINK_M2(pipe), PCH_TRANS_LINK_N2(pipe)); 201 } 202 203 void intel_pch_transcoder_get_m1_n1(struct intel_crtc *crtc, 204 struct intel_link_m_n *m_n) 205 { 206 struct intel_display *display = to_intel_display(crtc); 207 enum pipe pipe = crtc->pipe; 208 209 intel_get_m_n(display, m_n, 210 PCH_TRANS_DATA_M1(pipe), PCH_TRANS_DATA_N1(pipe), 211 PCH_TRANS_LINK_M1(pipe), PCH_TRANS_LINK_N1(pipe)); 212 } 213 214 void intel_pch_transcoder_get_m2_n2(struct intel_crtc *crtc, 215 struct intel_link_m_n *m_n) 216 { 217 struct intel_display *display = to_intel_display(crtc); 218 enum pipe pipe = crtc->pipe; 219 220 intel_get_m_n(display, m_n, 221 PCH_TRANS_DATA_M2(pipe), PCH_TRANS_DATA_N2(pipe), 222 PCH_TRANS_LINK_M2(pipe), PCH_TRANS_LINK_N2(pipe)); 223 } 224 225 static void ilk_pch_transcoder_set_timings(const struct intel_crtc_state *crtc_state, 226 enum pipe pch_transcoder) 227 { 228 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 229 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 230 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 231 232 intel_de_write(dev_priv, PCH_TRANS_HTOTAL(pch_transcoder), 233 intel_de_read(dev_priv, TRANS_HTOTAL(dev_priv, cpu_transcoder))); 234 intel_de_write(dev_priv, PCH_TRANS_HBLANK(pch_transcoder), 235 intel_de_read(dev_priv, TRANS_HBLANK(dev_priv, cpu_transcoder))); 236 intel_de_write(dev_priv, PCH_TRANS_HSYNC(pch_transcoder), 237 intel_de_read(dev_priv, TRANS_HSYNC(dev_priv, cpu_transcoder))); 238 239 intel_de_write(dev_priv, PCH_TRANS_VTOTAL(pch_transcoder), 240 intel_de_read(dev_priv, TRANS_VTOTAL(dev_priv, cpu_transcoder))); 241 intel_de_write(dev_priv, PCH_TRANS_VBLANK(pch_transcoder), 242 intel_de_read(dev_priv, TRANS_VBLANK(dev_priv, cpu_transcoder))); 243 intel_de_write(dev_priv, PCH_TRANS_VSYNC(pch_transcoder), 244 intel_de_read(dev_priv, TRANS_VSYNC(dev_priv, cpu_transcoder))); 245 intel_de_write(dev_priv, PCH_TRANS_VSYNCSHIFT(pch_transcoder), 246 intel_de_read(dev_priv, TRANS_VSYNCSHIFT(dev_priv, cpu_transcoder))); 247 } 248 249 static void ilk_enable_pch_transcoder(const struct intel_crtc_state *crtc_state) 250 { 251 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 252 struct intel_display *display = to_intel_display(crtc); 253 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 254 enum pipe pipe = crtc->pipe; 255 i915_reg_t reg; 256 u32 val, pipeconf_val; 257 258 /* Make sure PCH DPLL is enabled */ 259 assert_shared_dpll_enabled(display, crtc_state->shared_dpll); 260 261 /* FDI must be feeding us bits for PCH ports */ 262 assert_fdi_tx_enabled(display, pipe); 263 assert_fdi_rx_enabled(display, pipe); 264 265 if (HAS_PCH_CPT(dev_priv)) { 266 reg = TRANS_CHICKEN2(pipe); 267 val = intel_de_read(display, reg); 268 /* 269 * Workaround: Set the timing override bit 270 * before enabling the pch transcoder. 271 */ 272 val |= TRANS_CHICKEN2_TIMING_OVERRIDE; 273 /* Configure frame start delay to match the CPU */ 274 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK; 275 val |= TRANS_CHICKEN2_FRAME_START_DELAY(crtc_state->framestart_delay - 1); 276 intel_de_write(display, reg, val); 277 } 278 279 reg = PCH_TRANSCONF(pipe); 280 val = intel_de_read(display, reg); 281 pipeconf_val = intel_de_read(display, TRANSCONF(display, pipe)); 282 283 if (HAS_PCH_IBX(dev_priv)) { 284 /* Configure frame start delay to match the CPU */ 285 val &= ~TRANS_FRAME_START_DELAY_MASK; 286 val |= TRANS_FRAME_START_DELAY(crtc_state->framestart_delay - 1); 287 288 /* 289 * Make the BPC in transcoder be consistent with 290 * that in pipeconf reg. For HDMI we must use 8bpc 291 * here for both 8bpc and 12bpc. 292 */ 293 val &= ~TRANSCONF_BPC_MASK; 294 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 295 val |= TRANSCONF_BPC_8; 296 else 297 val |= pipeconf_val & TRANSCONF_BPC_MASK; 298 } 299 300 val &= ~TRANS_INTERLACE_MASK; 301 if ((pipeconf_val & TRANSCONF_INTERLACE_MASK_ILK) == TRANSCONF_INTERLACE_IF_ID_ILK) { 302 if (HAS_PCH_IBX(dev_priv) && 303 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO)) 304 val |= TRANS_INTERLACE_LEGACY_VSYNC_IBX; 305 else 306 val |= TRANS_INTERLACE_INTERLACED; 307 } else { 308 val |= TRANS_INTERLACE_PROGRESSIVE; 309 } 310 311 intel_de_write(display, reg, val | TRANS_ENABLE); 312 if (intel_de_wait_for_set(display, reg, TRANS_STATE_ENABLE, 100)) 313 drm_err(display->drm, "failed to enable transcoder %c\n", 314 pipe_name(pipe)); 315 } 316 317 static void ilk_disable_pch_transcoder(struct intel_crtc *crtc) 318 { 319 struct intel_display *display = to_intel_display(crtc); 320 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 321 enum pipe pipe = crtc->pipe; 322 i915_reg_t reg; 323 324 /* FDI relies on the transcoder */ 325 assert_fdi_tx_disabled(display, pipe); 326 assert_fdi_rx_disabled(display, pipe); 327 328 /* Ports must be off as well */ 329 assert_pch_ports_disabled(dev_priv, pipe); 330 331 reg = PCH_TRANSCONF(pipe); 332 intel_de_rmw(dev_priv, reg, TRANS_ENABLE, 0); 333 /* wait for PCH transcoder off, transcoder state */ 334 if (intel_de_wait_for_clear(dev_priv, reg, TRANS_STATE_ENABLE, 50)) 335 drm_err(&dev_priv->drm, "failed to disable transcoder %c\n", 336 pipe_name(pipe)); 337 338 if (HAS_PCH_CPT(dev_priv)) 339 /* Workaround: Clear the timing override chicken bit again. */ 340 intel_de_rmw(dev_priv, TRANS_CHICKEN2(pipe), 341 TRANS_CHICKEN2_TIMING_OVERRIDE, 0); 342 } 343 344 void ilk_pch_pre_enable(struct intel_atomic_state *state, 345 struct intel_crtc *crtc) 346 { 347 const struct intel_crtc_state *crtc_state = 348 intel_atomic_get_new_crtc_state(state, crtc); 349 350 /* 351 * Note: FDI PLL enabling _must_ be done before we enable the 352 * cpu pipes, hence this is separate from all the other fdi/pch 353 * enabling. 354 */ 355 ilk_fdi_pll_enable(crtc_state); 356 } 357 358 /* 359 * Enable PCH resources required for PCH ports: 360 * - PCH PLLs 361 * - FDI training & RX/TX 362 * - update transcoder timings 363 * - DP transcoding bits 364 * - transcoder 365 */ 366 void ilk_pch_enable(struct intel_atomic_state *state, 367 struct intel_crtc *crtc) 368 { 369 struct intel_display *display = to_intel_display(state); 370 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 371 const struct intel_crtc_state *crtc_state = 372 intel_atomic_get_new_crtc_state(state, crtc); 373 enum pipe pipe = crtc->pipe; 374 u32 temp; 375 376 assert_pch_transcoder_disabled(dev_priv, pipe); 377 378 /* For PCH output, training FDI link */ 379 intel_fdi_link_train(crtc, crtc_state); 380 381 /* 382 * We need to program the right clock selection 383 * before writing the pixel multiplier into the DPLL. 384 */ 385 if (HAS_PCH_CPT(dev_priv)) { 386 u32 sel; 387 388 temp = intel_de_read(display, PCH_DPLL_SEL); 389 temp |= TRANS_DPLL_ENABLE(pipe); 390 sel = TRANS_DPLLB_SEL(pipe); 391 if (crtc_state->shared_dpll == 392 intel_get_shared_dpll_by_id(display, DPLL_ID_PCH_PLL_B)) 393 temp |= sel; 394 else 395 temp &= ~sel; 396 intel_de_write(display, PCH_DPLL_SEL, temp); 397 } 398 399 /* 400 * XXX: pch pll's can be enabled any time before we enable the PCH 401 * transcoder, and we actually should do this to not upset any PCH 402 * transcoder that already use the clock when we share it. 403 * 404 * Note that enable_shared_dpll tries to do the right thing, but 405 * get_shared_dpll unconditionally resets the pll - we need that 406 * to have the right LVDS enable sequence. 407 */ 408 intel_enable_shared_dpll(crtc_state); 409 410 /* set transcoder timing, panel must allow it */ 411 assert_pps_unlocked(display, pipe); 412 if (intel_crtc_has_dp_encoder(crtc_state)) { 413 intel_pch_transcoder_set_m1_n1(crtc, &crtc_state->dp_m_n); 414 intel_pch_transcoder_set_m2_n2(crtc, &crtc_state->dp_m2_n2); 415 } 416 ilk_pch_transcoder_set_timings(crtc_state, pipe); 417 418 intel_fdi_normal_train(crtc); 419 420 /* For PCH DP, enable TRANS_DP_CTL */ 421 if (HAS_PCH_CPT(dev_priv) && 422 intel_crtc_has_dp_encoder(crtc_state)) { 423 const struct drm_display_mode *adjusted_mode = 424 &crtc_state->hw.adjusted_mode; 425 u32 bpc = (intel_de_read(display, TRANSCONF(display, pipe)) 426 & TRANSCONF_BPC_MASK) >> 5; 427 i915_reg_t reg = TRANS_DP_CTL(pipe); 428 enum port port; 429 430 temp = intel_de_read(display, reg); 431 temp &= ~(TRANS_DP_PORT_SEL_MASK | 432 TRANS_DP_VSYNC_ACTIVE_HIGH | 433 TRANS_DP_HSYNC_ACTIVE_HIGH | 434 TRANS_DP_BPC_MASK); 435 temp |= TRANS_DP_OUTPUT_ENABLE; 436 temp |= bpc << 9; /* same format but at 11:9 */ 437 438 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) 439 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH; 440 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) 441 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH; 442 443 port = intel_get_crtc_new_encoder(state, crtc_state)->port; 444 drm_WARN_ON(display->drm, port < PORT_B || port > PORT_D); 445 temp |= TRANS_DP_PORT_SEL(port); 446 447 intel_de_write(display, reg, temp); 448 } 449 450 ilk_enable_pch_transcoder(crtc_state); 451 } 452 453 void ilk_pch_disable(struct intel_atomic_state *state, 454 struct intel_crtc *crtc) 455 { 456 ilk_fdi_disable(crtc); 457 } 458 459 void ilk_pch_post_disable(struct intel_atomic_state *state, 460 struct intel_crtc *crtc) 461 { 462 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 463 enum pipe pipe = crtc->pipe; 464 465 ilk_disable_pch_transcoder(crtc); 466 467 if (HAS_PCH_CPT(dev_priv)) { 468 /* disable TRANS_DP_CTL */ 469 intel_de_rmw(dev_priv, TRANS_DP_CTL(pipe), 470 TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK, 471 TRANS_DP_PORT_SEL_NONE); 472 473 /* disable DPLL_SEL */ 474 intel_de_rmw(dev_priv, PCH_DPLL_SEL, 475 TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe), 0); 476 } 477 478 ilk_fdi_pll_disable(crtc); 479 } 480 481 static void ilk_pch_clock_get(struct intel_crtc_state *crtc_state) 482 { 483 struct intel_display *display = to_intel_display(crtc_state); 484 485 /* read out port_clock from the DPLL */ 486 i9xx_crtc_clock_get(crtc_state); 487 488 /* 489 * In case there is an active pipe without active ports, 490 * we may need some idea for the dotclock anyway. 491 * Calculate one based on the FDI configuration. 492 */ 493 crtc_state->hw.adjusted_mode.crtc_clock = 494 intel_dotclock_calculate(intel_fdi_link_freq(display, crtc_state), 495 &crtc_state->fdi_m_n); 496 } 497 498 void ilk_pch_get_config(struct intel_crtc_state *crtc_state) 499 { 500 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 501 struct intel_display *display = to_intel_display(crtc); 502 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 503 struct intel_shared_dpll *pll; 504 enum pipe pipe = crtc->pipe; 505 enum intel_dpll_id pll_id; 506 bool pll_active; 507 u32 tmp; 508 509 if ((intel_de_read(display, PCH_TRANSCONF(pipe)) & TRANS_ENABLE) == 0) 510 return; 511 512 crtc_state->has_pch_encoder = true; 513 514 tmp = intel_de_read(display, FDI_RX_CTL(pipe)); 515 crtc_state->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >> 516 FDI_DP_PORT_WIDTH_SHIFT) + 1; 517 518 intel_cpu_transcoder_get_m1_n1(crtc, crtc_state->cpu_transcoder, 519 &crtc_state->fdi_m_n); 520 521 if (HAS_PCH_IBX(dev_priv)) { 522 /* 523 * The pipe->pch transcoder and pch transcoder->pll 524 * mapping is fixed. 525 */ 526 pll_id = (enum intel_dpll_id) pipe; 527 } else { 528 tmp = intel_de_read(display, PCH_DPLL_SEL); 529 if (tmp & TRANS_DPLLB_SEL(pipe)) 530 pll_id = DPLL_ID_PCH_PLL_B; 531 else 532 pll_id = DPLL_ID_PCH_PLL_A; 533 } 534 535 crtc_state->shared_dpll = intel_get_shared_dpll_by_id(display, pll_id); 536 pll = crtc_state->shared_dpll; 537 538 pll_active = intel_dpll_get_hw_state(display, pll, 539 &crtc_state->dpll_hw_state); 540 drm_WARN_ON(display->drm, !pll_active); 541 542 tmp = crtc_state->dpll_hw_state.i9xx.dpll; 543 crtc_state->pixel_multiplier = 544 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK) 545 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1; 546 547 ilk_pch_clock_get(crtc_state); 548 } 549 550 static void lpt_enable_pch_transcoder(const struct intel_crtc_state *crtc_state) 551 { 552 struct intel_display *display = to_intel_display(crtc_state); 553 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 554 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 555 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 556 u32 val, pipeconf_val; 557 558 /* FDI must be feeding us bits for PCH ports */ 559 assert_fdi_tx_enabled(display, (enum pipe)cpu_transcoder); 560 assert_fdi_rx_enabled(display, PIPE_A); 561 562 val = intel_de_read(dev_priv, TRANS_CHICKEN2(PIPE_A)); 563 /* Workaround: set timing override bit. */ 564 val |= TRANS_CHICKEN2_TIMING_OVERRIDE; 565 /* Configure frame start delay to match the CPU */ 566 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK; 567 val |= TRANS_CHICKEN2_FRAME_START_DELAY(crtc_state->framestart_delay - 1); 568 intel_de_write(dev_priv, TRANS_CHICKEN2(PIPE_A), val); 569 570 val = TRANS_ENABLE; 571 pipeconf_val = intel_de_read(dev_priv, 572 TRANSCONF(dev_priv, cpu_transcoder)); 573 574 if ((pipeconf_val & TRANSCONF_INTERLACE_MASK_HSW) == TRANSCONF_INTERLACE_IF_ID_ILK) 575 val |= TRANS_INTERLACE_INTERLACED; 576 else 577 val |= TRANS_INTERLACE_PROGRESSIVE; 578 579 intel_de_write(dev_priv, LPT_TRANSCONF, val); 580 if (intel_de_wait_for_set(dev_priv, LPT_TRANSCONF, 581 TRANS_STATE_ENABLE, 100)) 582 drm_err(&dev_priv->drm, "Failed to enable PCH transcoder\n"); 583 } 584 585 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv) 586 { 587 intel_de_rmw(dev_priv, LPT_TRANSCONF, TRANS_ENABLE, 0); 588 /* wait for PCH transcoder off, transcoder state */ 589 if (intel_de_wait_for_clear(dev_priv, LPT_TRANSCONF, 590 TRANS_STATE_ENABLE, 50)) 591 drm_err(&dev_priv->drm, "Failed to disable PCH transcoder\n"); 592 593 /* Workaround: clear timing override bit. */ 594 intel_de_rmw(dev_priv, TRANS_CHICKEN2(PIPE_A), TRANS_CHICKEN2_TIMING_OVERRIDE, 0); 595 } 596 597 void lpt_pch_enable(struct intel_atomic_state *state, 598 struct intel_crtc *crtc) 599 { 600 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 601 const struct intel_crtc_state *crtc_state = 602 intel_atomic_get_new_crtc_state(state, crtc); 603 604 assert_pch_transcoder_disabled(dev_priv, PIPE_A); 605 606 lpt_program_iclkip(crtc_state); 607 608 /* Set transcoder timing. */ 609 ilk_pch_transcoder_set_timings(crtc_state, PIPE_A); 610 611 lpt_enable_pch_transcoder(crtc_state); 612 } 613 614 void lpt_pch_disable(struct intel_atomic_state *state, 615 struct intel_crtc *crtc) 616 { 617 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 618 619 lpt_disable_pch_transcoder(dev_priv); 620 621 lpt_disable_iclkip(dev_priv); 622 } 623 624 void lpt_pch_get_config(struct intel_crtc_state *crtc_state) 625 { 626 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 627 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 628 u32 tmp; 629 630 if ((intel_de_read(dev_priv, LPT_TRANSCONF) & TRANS_ENABLE) == 0) 631 return; 632 633 crtc_state->has_pch_encoder = true; 634 635 tmp = intel_de_read(dev_priv, FDI_RX_CTL(PIPE_A)); 636 crtc_state->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >> 637 FDI_DP_PORT_WIDTH_SHIFT) + 1; 638 639 intel_cpu_transcoder_get_m1_n1(crtc, crtc_state->cpu_transcoder, 640 &crtc_state->fdi_m_n); 641 642 crtc_state->hw.adjusted_mode.crtc_clock = lpt_get_iclkip(dev_priv); 643 } 644 645 void intel_pch_sanitize(struct drm_i915_private *i915) 646 { 647 if (HAS_PCH_IBX(i915)) 648 ibx_sanitize_pch_ports(i915); 649 } 650