1 /* 2 * Copyright © 2009 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 * SOFTWARE. 22 * 23 * Authors: 24 * Daniel Vetter <daniel@ffwll.ch> 25 * 26 * Derived from Xorg ddx, xf86-video-intel, src/i830_video.c 27 */ 28 29 #include <drm/drm_fourcc.h> 30 31 #include "gem/i915_gem_internal.h" 32 #include "gem/i915_gem_object_frontbuffer.h" 33 #include "gem/i915_gem_pm.h" 34 #include "gt/intel_gpu_commands.h" 35 #include "gt/intel_ring.h" 36 37 #include "i915_drv.h" 38 #include "i915_reg.h" 39 #include "intel_color_regs.h" 40 #include "intel_de.h" 41 #include "intel_display_types.h" 42 #include "intel_frontbuffer.h" 43 #include "intel_overlay.h" 44 #include "intel_pci_config.h" 45 46 /* Limits for overlay size. According to intel doc, the real limits are: 47 * Y width: 4095, UV width (planar): 2047, Y height: 2047, 48 * UV width (planar): * 1023. But the xorg thinks 2048 for height and width. Use 49 * the mininum of both. */ 50 #define IMAGE_MAX_WIDTH 2048 51 #define IMAGE_MAX_HEIGHT 2046 /* 2 * 1023 */ 52 /* on 830 and 845 these large limits result in the card hanging */ 53 #define IMAGE_MAX_WIDTH_LEGACY 1024 54 #define IMAGE_MAX_HEIGHT_LEGACY 1088 55 56 /* overlay register definitions */ 57 /* OCMD register */ 58 #define OCMD_TILED_SURFACE (0x1<<19) 59 #define OCMD_MIRROR_MASK (0x3<<17) 60 #define OCMD_MIRROR_MODE (0x3<<17) 61 #define OCMD_MIRROR_HORIZONTAL (0x1<<17) 62 #define OCMD_MIRROR_VERTICAL (0x2<<17) 63 #define OCMD_MIRROR_BOTH (0x3<<17) 64 #define OCMD_BYTEORDER_MASK (0x3<<14) /* zero for YUYV or FOURCC YUY2 */ 65 #define OCMD_UV_SWAP (0x1<<14) /* YVYU */ 66 #define OCMD_Y_SWAP (0x2<<14) /* UYVY or FOURCC UYVY */ 67 #define OCMD_Y_AND_UV_SWAP (0x3<<14) /* VYUY */ 68 #define OCMD_SOURCE_FORMAT_MASK (0xf<<10) 69 #define OCMD_RGB_888 (0x1<<10) /* not in i965 Intel docs */ 70 #define OCMD_RGB_555 (0x2<<10) /* not in i965 Intel docs */ 71 #define OCMD_RGB_565 (0x3<<10) /* not in i965 Intel docs */ 72 #define OCMD_YUV_422_PACKED (0x8<<10) 73 #define OCMD_YUV_411_PACKED (0x9<<10) /* not in i965 Intel docs */ 74 #define OCMD_YUV_420_PLANAR (0xc<<10) 75 #define OCMD_YUV_422_PLANAR (0xd<<10) 76 #define OCMD_YUV_410_PLANAR (0xe<<10) /* also 411 */ 77 #define OCMD_TVSYNCFLIP_PARITY (0x1<<9) 78 #define OCMD_TVSYNCFLIP_ENABLE (0x1<<7) 79 #define OCMD_BUF_TYPE_MASK (0x1<<5) 80 #define OCMD_BUF_TYPE_FRAME (0x0<<5) 81 #define OCMD_BUF_TYPE_FIELD (0x1<<5) 82 #define OCMD_TEST_MODE (0x1<<4) 83 #define OCMD_BUFFER_SELECT (0x3<<2) 84 #define OCMD_BUFFER0 (0x0<<2) 85 #define OCMD_BUFFER1 (0x1<<2) 86 #define OCMD_FIELD_SELECT (0x1<<2) 87 #define OCMD_FIELD0 (0x0<<1) 88 #define OCMD_FIELD1 (0x1<<1) 89 #define OCMD_ENABLE (0x1<<0) 90 91 /* OCONFIG register */ 92 #define OCONF_PIPE_MASK (0x1<<18) 93 #define OCONF_PIPE_A (0x0<<18) 94 #define OCONF_PIPE_B (0x1<<18) 95 #define OCONF_GAMMA2_ENABLE (0x1<<16) 96 #define OCONF_CSC_MODE_BT601 (0x0<<5) 97 #define OCONF_CSC_MODE_BT709 (0x1<<5) 98 #define OCONF_CSC_BYPASS (0x1<<4) 99 #define OCONF_CC_OUT_8BIT (0x1<<3) 100 #define OCONF_TEST_MODE (0x1<<2) 101 #define OCONF_THREE_LINE_BUFFER (0x1<<0) 102 #define OCONF_TWO_LINE_BUFFER (0x0<<0) 103 104 /* DCLRKM (dst-key) register */ 105 #define DST_KEY_ENABLE (0x1<<31) 106 #define CLK_RGB24_MASK 0x0 107 #define CLK_RGB16_MASK 0x070307 108 #define CLK_RGB15_MASK 0x070707 109 110 #define RGB30_TO_COLORKEY(c) \ 111 ((((c) & 0x3fc00000) >> 6) | (((c) & 0x000ff000) >> 4) | (((c) & 0x000003fc) >> 2)) 112 #define RGB16_TO_COLORKEY(c) \ 113 ((((c) & 0xf800) << 8) | (((c) & 0x07e0) << 5) | (((c) & 0x001f) << 3)) 114 #define RGB15_TO_COLORKEY(c) \ 115 ((((c) & 0x7c00) << 9) | (((c) & 0x03e0) << 6) | (((c) & 0x001f) << 3)) 116 #define RGB8I_TO_COLORKEY(c) \ 117 ((((c) & 0xff) << 16) | (((c) & 0xff) << 8) | (((c) & 0xff) << 0)) 118 119 /* overlay flip addr flag */ 120 #define OFC_UPDATE 0x1 121 122 /* polyphase filter coefficients */ 123 #define N_HORIZ_Y_TAPS 5 124 #define N_VERT_Y_TAPS 3 125 #define N_HORIZ_UV_TAPS 3 126 #define N_VERT_UV_TAPS 3 127 #define N_PHASES 17 128 #define MAX_TAPS 5 129 130 /* memory bufferd overlay registers */ 131 struct overlay_registers { 132 u32 OBUF_0Y; 133 u32 OBUF_1Y; 134 u32 OBUF_0U; 135 u32 OBUF_0V; 136 u32 OBUF_1U; 137 u32 OBUF_1V; 138 u32 OSTRIDE; 139 u32 YRGB_VPH; 140 u32 UV_VPH; 141 u32 HORZ_PH; 142 u32 INIT_PHS; 143 u32 DWINPOS; 144 u32 DWINSZ; 145 u32 SWIDTH; 146 u32 SWIDTHSW; 147 u32 SHEIGHT; 148 u32 YRGBSCALE; 149 u32 UVSCALE; 150 u32 OCLRC0; 151 u32 OCLRC1; 152 u32 DCLRKV; 153 u32 DCLRKM; 154 u32 SCLRKVH; 155 u32 SCLRKVL; 156 u32 SCLRKEN; 157 u32 OCONFIG; 158 u32 OCMD; 159 u32 RESERVED1; /* 0x6C */ 160 u32 OSTART_0Y; 161 u32 OSTART_1Y; 162 u32 OSTART_0U; 163 u32 OSTART_0V; 164 u32 OSTART_1U; 165 u32 OSTART_1V; 166 u32 OTILEOFF_0Y; 167 u32 OTILEOFF_1Y; 168 u32 OTILEOFF_0U; 169 u32 OTILEOFF_0V; 170 u32 OTILEOFF_1U; 171 u32 OTILEOFF_1V; 172 u32 FASTHSCALE; /* 0xA0 */ 173 u32 UVSCALEV; /* 0xA4 */ 174 u32 RESERVEDC[(0x200 - 0xA8) / 4]; /* 0xA8 - 0x1FC */ 175 u16 Y_VCOEFS[N_VERT_Y_TAPS * N_PHASES]; /* 0x200 */ 176 u16 RESERVEDD[0x100 / 2 - N_VERT_Y_TAPS * N_PHASES]; 177 u16 Y_HCOEFS[N_HORIZ_Y_TAPS * N_PHASES]; /* 0x300 */ 178 u16 RESERVEDE[0x200 / 2 - N_HORIZ_Y_TAPS * N_PHASES]; 179 u16 UV_VCOEFS[N_VERT_UV_TAPS * N_PHASES]; /* 0x500 */ 180 u16 RESERVEDF[0x100 / 2 - N_VERT_UV_TAPS * N_PHASES]; 181 u16 UV_HCOEFS[N_HORIZ_UV_TAPS * N_PHASES]; /* 0x600 */ 182 u16 RESERVEDG[0x100 / 2 - N_HORIZ_UV_TAPS * N_PHASES]; 183 }; 184 185 struct intel_overlay { 186 struct intel_display *display; 187 struct intel_context *context; 188 struct intel_crtc *crtc; 189 struct i915_vma *vma; 190 struct i915_vma *old_vma; 191 struct intel_frontbuffer *frontbuffer; 192 bool active; 193 bool pfit_active; 194 u32 pfit_vscale_ratio; /* shifted-point number, (1<<12) == 1.0 */ 195 u32 color_key:24; 196 u32 color_key_enabled:1; 197 u32 brightness, contrast, saturation; 198 u32 old_xscale, old_yscale; 199 /* register access */ 200 struct drm_i915_gem_object *reg_bo; 201 struct overlay_registers __iomem *regs; 202 u32 flip_addr; 203 /* flip handling */ 204 struct i915_active last_flip; 205 void (*flip_complete)(struct intel_overlay *ovl); 206 }; 207 208 static void i830_overlay_clock_gating(struct intel_display *display, 209 bool enable) 210 { 211 struct pci_dev *pdev = to_pci_dev(display->drm->dev); 212 u8 val; 213 214 /* WA_OVERLAY_CLKGATE:alm */ 215 if (enable) 216 intel_de_write(display, DSPCLK_GATE_D(display), 0); 217 else 218 intel_de_write(display, DSPCLK_GATE_D(display), 219 OVRUNIT_CLOCK_GATE_DISABLE); 220 221 /* WA_DISABLE_L2CACHE_CLOCK_GATING:alm */ 222 pci_bus_read_config_byte(pdev->bus, 223 PCI_DEVFN(0, 0), I830_CLOCK_GATE, &val); 224 if (enable) 225 val &= ~I830_L2_CACHE_CLOCK_GATE_DISABLE; 226 else 227 val |= I830_L2_CACHE_CLOCK_GATE_DISABLE; 228 pci_bus_write_config_byte(pdev->bus, 229 PCI_DEVFN(0, 0), I830_CLOCK_GATE, val); 230 } 231 232 static struct i915_request * 233 alloc_request(struct intel_overlay *overlay, void (*fn)(struct intel_overlay *)) 234 { 235 struct i915_request *rq; 236 int err; 237 238 overlay->flip_complete = fn; 239 240 rq = i915_request_create(overlay->context); 241 if (IS_ERR(rq)) 242 return rq; 243 244 err = i915_active_add_request(&overlay->last_flip, rq); 245 if (err) { 246 i915_request_add(rq); 247 return ERR_PTR(err); 248 } 249 250 return rq; 251 } 252 253 /* overlay needs to be disable in OCMD reg */ 254 static int intel_overlay_on(struct intel_overlay *overlay) 255 { 256 struct intel_display *display = overlay->display; 257 struct i915_request *rq; 258 u32 *cs; 259 260 drm_WARN_ON(display->drm, overlay->active); 261 262 rq = alloc_request(overlay, NULL); 263 if (IS_ERR(rq)) 264 return PTR_ERR(rq); 265 266 cs = intel_ring_begin(rq, 4); 267 if (IS_ERR(cs)) { 268 i915_request_add(rq); 269 return PTR_ERR(cs); 270 } 271 272 overlay->active = true; 273 274 if (display->platform.i830) 275 i830_overlay_clock_gating(display, false); 276 277 *cs++ = MI_OVERLAY_FLIP | MI_OVERLAY_ON; 278 *cs++ = overlay->flip_addr | OFC_UPDATE; 279 *cs++ = MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP; 280 *cs++ = MI_NOOP; 281 intel_ring_advance(rq, cs); 282 283 i915_request_add(rq); 284 285 return i915_active_wait(&overlay->last_flip); 286 } 287 288 static void intel_overlay_flip_prepare(struct intel_overlay *overlay, 289 struct i915_vma *vma) 290 { 291 struct intel_display *display = overlay->display; 292 struct drm_i915_private *i915 = to_i915(display->drm); 293 enum pipe pipe = overlay->crtc->pipe; 294 struct intel_frontbuffer *frontbuffer = NULL; 295 296 drm_WARN_ON(display->drm, overlay->old_vma); 297 298 if (vma) 299 frontbuffer = intel_frontbuffer_get(intel_bo_to_drm_bo(vma->obj)); 300 301 intel_frontbuffer_track(overlay->frontbuffer, frontbuffer, 302 INTEL_FRONTBUFFER_OVERLAY(pipe)); 303 304 if (overlay->frontbuffer) 305 intel_frontbuffer_put(overlay->frontbuffer); 306 overlay->frontbuffer = frontbuffer; 307 308 intel_frontbuffer_flip_prepare(i915, INTEL_FRONTBUFFER_OVERLAY(pipe)); 309 310 overlay->old_vma = overlay->vma; 311 if (vma) 312 overlay->vma = i915_vma_get(vma); 313 else 314 overlay->vma = NULL; 315 } 316 317 /* overlay needs to be enabled in OCMD reg */ 318 static int intel_overlay_continue(struct intel_overlay *overlay, 319 struct i915_vma *vma, 320 bool load_polyphase_filter) 321 { 322 struct intel_display *display = overlay->display; 323 struct i915_request *rq; 324 u32 flip_addr = overlay->flip_addr; 325 u32 tmp, *cs; 326 327 drm_WARN_ON(display->drm, !overlay->active); 328 329 if (load_polyphase_filter) 330 flip_addr |= OFC_UPDATE; 331 332 /* check for underruns */ 333 tmp = intel_de_read(display, DOVSTA); 334 if (tmp & (1 << 17)) 335 drm_dbg(display->drm, "overlay underrun, DOVSTA: %x\n", tmp); 336 337 rq = alloc_request(overlay, NULL); 338 if (IS_ERR(rq)) 339 return PTR_ERR(rq); 340 341 cs = intel_ring_begin(rq, 2); 342 if (IS_ERR(cs)) { 343 i915_request_add(rq); 344 return PTR_ERR(cs); 345 } 346 347 *cs++ = MI_OVERLAY_FLIP | MI_OVERLAY_CONTINUE; 348 *cs++ = flip_addr; 349 intel_ring_advance(rq, cs); 350 351 intel_overlay_flip_prepare(overlay, vma); 352 i915_request_add(rq); 353 354 return 0; 355 } 356 357 static void intel_overlay_release_old_vma(struct intel_overlay *overlay) 358 { 359 struct intel_display *display = overlay->display; 360 struct drm_i915_private *i915 = to_i915(display->drm); 361 struct i915_vma *vma; 362 363 vma = fetch_and_zero(&overlay->old_vma); 364 if (drm_WARN_ON(display->drm, !vma)) 365 return; 366 367 intel_frontbuffer_flip_complete(i915, INTEL_FRONTBUFFER_OVERLAY(overlay->crtc->pipe)); 368 369 i915_vma_unpin(vma); 370 i915_vma_put(vma); 371 } 372 373 static void 374 intel_overlay_release_old_vid_tail(struct intel_overlay *overlay) 375 { 376 intel_overlay_release_old_vma(overlay); 377 } 378 379 static void intel_overlay_off_tail(struct intel_overlay *overlay) 380 { 381 struct intel_display *display = overlay->display; 382 383 intel_overlay_release_old_vma(overlay); 384 385 overlay->crtc->overlay = NULL; 386 overlay->crtc = NULL; 387 overlay->active = false; 388 389 if (display->platform.i830) 390 i830_overlay_clock_gating(display, true); 391 } 392 393 static void intel_overlay_last_flip_retire(struct i915_active *active) 394 { 395 struct intel_overlay *overlay = 396 container_of(active, typeof(*overlay), last_flip); 397 398 if (overlay->flip_complete) 399 overlay->flip_complete(overlay); 400 } 401 402 /* overlay needs to be disabled in OCMD reg */ 403 static int intel_overlay_off(struct intel_overlay *overlay) 404 { 405 struct intel_display *display = overlay->display; 406 struct i915_request *rq; 407 u32 *cs, flip_addr = overlay->flip_addr; 408 409 drm_WARN_ON(display->drm, !overlay->active); 410 411 /* According to intel docs the overlay hw may hang (when switching 412 * off) without loading the filter coeffs. It is however unclear whether 413 * this applies to the disabling of the overlay or to the switching off 414 * of the hw. Do it in both cases */ 415 flip_addr |= OFC_UPDATE; 416 417 rq = alloc_request(overlay, intel_overlay_off_tail); 418 if (IS_ERR(rq)) 419 return PTR_ERR(rq); 420 421 cs = intel_ring_begin(rq, 6); 422 if (IS_ERR(cs)) { 423 i915_request_add(rq); 424 return PTR_ERR(cs); 425 } 426 427 /* wait for overlay to go idle */ 428 *cs++ = MI_OVERLAY_FLIP | MI_OVERLAY_CONTINUE; 429 *cs++ = flip_addr; 430 *cs++ = MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP; 431 432 /* turn overlay off */ 433 *cs++ = MI_OVERLAY_FLIP | MI_OVERLAY_OFF; 434 *cs++ = flip_addr; 435 *cs++ = MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP; 436 437 intel_ring_advance(rq, cs); 438 439 intel_overlay_flip_prepare(overlay, NULL); 440 i915_request_add(rq); 441 442 return i915_active_wait(&overlay->last_flip); 443 } 444 445 /* recover from an interruption due to a signal 446 * We have to be careful not to repeat work forever an make forward progess. */ 447 static int intel_overlay_recover_from_interrupt(struct intel_overlay *overlay) 448 { 449 return i915_active_wait(&overlay->last_flip); 450 } 451 452 /* Wait for pending overlay flip and release old frame. 453 * Needs to be called before the overlay register are changed 454 * via intel_overlay_(un)map_regs 455 */ 456 static int intel_overlay_release_old_vid(struct intel_overlay *overlay) 457 { 458 struct intel_display *display = overlay->display; 459 struct i915_request *rq; 460 u32 *cs; 461 462 /* 463 * Only wait if there is actually an old frame to release to 464 * guarantee forward progress. 465 */ 466 if (!overlay->old_vma) 467 return 0; 468 469 if (!(intel_de_read(display, GEN2_ISR) & I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT)) { 470 intel_overlay_release_old_vid_tail(overlay); 471 return 0; 472 } 473 474 rq = alloc_request(overlay, intel_overlay_release_old_vid_tail); 475 if (IS_ERR(rq)) 476 return PTR_ERR(rq); 477 478 cs = intel_ring_begin(rq, 2); 479 if (IS_ERR(cs)) { 480 i915_request_add(rq); 481 return PTR_ERR(cs); 482 } 483 484 *cs++ = MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP; 485 *cs++ = MI_NOOP; 486 intel_ring_advance(rq, cs); 487 488 i915_request_add(rq); 489 490 return i915_active_wait(&overlay->last_flip); 491 } 492 493 void intel_overlay_reset(struct intel_display *display) 494 { 495 struct intel_overlay *overlay = display->overlay; 496 497 if (!overlay) 498 return; 499 500 overlay->old_xscale = 0; 501 overlay->old_yscale = 0; 502 overlay->crtc = NULL; 503 overlay->active = false; 504 } 505 506 static int packed_depth_bytes(u32 format) 507 { 508 switch (format & I915_OVERLAY_DEPTH_MASK) { 509 case I915_OVERLAY_YUV422: 510 return 4; 511 case I915_OVERLAY_YUV411: 512 /* return 6; not implemented */ 513 default: 514 return -EINVAL; 515 } 516 } 517 518 static int packed_width_bytes(u32 format, short width) 519 { 520 switch (format & I915_OVERLAY_DEPTH_MASK) { 521 case I915_OVERLAY_YUV422: 522 return width << 1; 523 default: 524 return -EINVAL; 525 } 526 } 527 528 static int uv_hsubsampling(u32 format) 529 { 530 switch (format & I915_OVERLAY_DEPTH_MASK) { 531 case I915_OVERLAY_YUV422: 532 case I915_OVERLAY_YUV420: 533 return 2; 534 case I915_OVERLAY_YUV411: 535 case I915_OVERLAY_YUV410: 536 return 4; 537 default: 538 return -EINVAL; 539 } 540 } 541 542 static int uv_vsubsampling(u32 format) 543 { 544 switch (format & I915_OVERLAY_DEPTH_MASK) { 545 case I915_OVERLAY_YUV420: 546 case I915_OVERLAY_YUV410: 547 return 2; 548 case I915_OVERLAY_YUV422: 549 case I915_OVERLAY_YUV411: 550 return 1; 551 default: 552 return -EINVAL; 553 } 554 } 555 556 static u32 calc_swidthsw(struct intel_display *display, u32 offset, u32 width) 557 { 558 u32 sw; 559 560 if (DISPLAY_VER(display) == 2) 561 sw = ALIGN((offset & 31) + width, 32); 562 else 563 sw = ALIGN((offset & 63) + width, 64); 564 565 if (sw == 0) 566 return 0; 567 568 return (sw - 32) >> 3; 569 } 570 571 static const u16 y_static_hcoeffs[N_PHASES][N_HORIZ_Y_TAPS] = { 572 [ 0] = { 0x3000, 0xb4a0, 0x1930, 0x1920, 0xb4a0, }, 573 [ 1] = { 0x3000, 0xb500, 0x19d0, 0x1880, 0xb440, }, 574 [ 2] = { 0x3000, 0xb540, 0x1a88, 0x2f80, 0xb3e0, }, 575 [ 3] = { 0x3000, 0xb580, 0x1b30, 0x2e20, 0xb380, }, 576 [ 4] = { 0x3000, 0xb5c0, 0x1bd8, 0x2cc0, 0xb320, }, 577 [ 5] = { 0x3020, 0xb5e0, 0x1c60, 0x2b80, 0xb2c0, }, 578 [ 6] = { 0x3020, 0xb5e0, 0x1cf8, 0x2a20, 0xb260, }, 579 [ 7] = { 0x3020, 0xb5e0, 0x1d80, 0x28e0, 0xb200, }, 580 [ 8] = { 0x3020, 0xb5c0, 0x1e08, 0x3f40, 0xb1c0, }, 581 [ 9] = { 0x3020, 0xb580, 0x1e78, 0x3ce0, 0xb160, }, 582 [10] = { 0x3040, 0xb520, 0x1ed8, 0x3aa0, 0xb120, }, 583 [11] = { 0x3040, 0xb4a0, 0x1f30, 0x3880, 0xb0e0, }, 584 [12] = { 0x3040, 0xb400, 0x1f78, 0x3680, 0xb0a0, }, 585 [13] = { 0x3020, 0xb340, 0x1fb8, 0x34a0, 0xb060, }, 586 [14] = { 0x3020, 0xb240, 0x1fe0, 0x32e0, 0xb040, }, 587 [15] = { 0x3020, 0xb140, 0x1ff8, 0x3160, 0xb020, }, 588 [16] = { 0xb000, 0x3000, 0x0800, 0x3000, 0xb000, }, 589 }; 590 591 static const u16 uv_static_hcoeffs[N_PHASES][N_HORIZ_UV_TAPS] = { 592 [ 0] = { 0x3000, 0x1800, 0x1800, }, 593 [ 1] = { 0xb000, 0x18d0, 0x2e60, }, 594 [ 2] = { 0xb000, 0x1990, 0x2ce0, }, 595 [ 3] = { 0xb020, 0x1a68, 0x2b40, }, 596 [ 4] = { 0xb040, 0x1b20, 0x29e0, }, 597 [ 5] = { 0xb060, 0x1bd8, 0x2880, }, 598 [ 6] = { 0xb080, 0x1c88, 0x3e60, }, 599 [ 7] = { 0xb0a0, 0x1d28, 0x3c00, }, 600 [ 8] = { 0xb0c0, 0x1db8, 0x39e0, }, 601 [ 9] = { 0xb0e0, 0x1e40, 0x37e0, }, 602 [10] = { 0xb100, 0x1eb8, 0x3620, }, 603 [11] = { 0xb100, 0x1f18, 0x34a0, }, 604 [12] = { 0xb100, 0x1f68, 0x3360, }, 605 [13] = { 0xb0e0, 0x1fa8, 0x3240, }, 606 [14] = { 0xb0c0, 0x1fe0, 0x3140, }, 607 [15] = { 0xb060, 0x1ff0, 0x30a0, }, 608 [16] = { 0x3000, 0x0800, 0x3000, }, 609 }; 610 611 static void update_polyphase_filter(struct overlay_registers __iomem *regs) 612 { 613 memcpy_toio(regs->Y_HCOEFS, y_static_hcoeffs, sizeof(y_static_hcoeffs)); 614 memcpy_toio(regs->UV_HCOEFS, uv_static_hcoeffs, 615 sizeof(uv_static_hcoeffs)); 616 } 617 618 static bool update_scaling_factors(struct intel_overlay *overlay, 619 struct overlay_registers __iomem *regs, 620 struct drm_intel_overlay_put_image *params) 621 { 622 /* fixed point with a 12 bit shift */ 623 u32 xscale, yscale, xscale_UV, yscale_UV; 624 #define FP_SHIFT 12 625 #define FRACT_MASK 0xfff 626 bool scale_changed = false; 627 int uv_hscale = uv_hsubsampling(params->flags); 628 int uv_vscale = uv_vsubsampling(params->flags); 629 630 if (params->dst_width > 1) 631 xscale = ((params->src_scan_width - 1) << FP_SHIFT) / 632 params->dst_width; 633 else 634 xscale = 1 << FP_SHIFT; 635 636 if (params->dst_height > 1) 637 yscale = ((params->src_scan_height - 1) << FP_SHIFT) / 638 params->dst_height; 639 else 640 yscale = 1 << FP_SHIFT; 641 642 /*if (params->format & I915_OVERLAY_YUV_PLANAR) {*/ 643 xscale_UV = xscale/uv_hscale; 644 yscale_UV = yscale/uv_vscale; 645 /* make the Y scale to UV scale ratio an exact multiply */ 646 xscale = xscale_UV * uv_hscale; 647 yscale = yscale_UV * uv_vscale; 648 /*} else { 649 xscale_UV = 0; 650 yscale_UV = 0; 651 }*/ 652 653 if (xscale != overlay->old_xscale || yscale != overlay->old_yscale) 654 scale_changed = true; 655 overlay->old_xscale = xscale; 656 overlay->old_yscale = yscale; 657 658 iowrite32(((yscale & FRACT_MASK) << 20) | 659 ((xscale >> FP_SHIFT) << 16) | 660 ((xscale & FRACT_MASK) << 3), 661 ®s->YRGBSCALE); 662 663 iowrite32(((yscale_UV & FRACT_MASK) << 20) | 664 ((xscale_UV >> FP_SHIFT) << 16) | 665 ((xscale_UV & FRACT_MASK) << 3), 666 ®s->UVSCALE); 667 668 iowrite32((((yscale >> FP_SHIFT) << 16) | 669 ((yscale_UV >> FP_SHIFT) << 0)), 670 ®s->UVSCALEV); 671 672 if (scale_changed) 673 update_polyphase_filter(regs); 674 675 return scale_changed; 676 } 677 678 static void update_colorkey(struct intel_overlay *overlay, 679 struct overlay_registers __iomem *regs) 680 { 681 const struct intel_plane_state *state = 682 to_intel_plane_state(overlay->crtc->base.primary->state); 683 u32 key = overlay->color_key; 684 u32 format = 0; 685 u32 flags = 0; 686 687 if (overlay->color_key_enabled) 688 flags |= DST_KEY_ENABLE; 689 690 if (state->uapi.visible) 691 format = state->hw.fb->format->format; 692 693 switch (format) { 694 case DRM_FORMAT_C8: 695 key = RGB8I_TO_COLORKEY(key); 696 flags |= CLK_RGB24_MASK; 697 break; 698 case DRM_FORMAT_XRGB1555: 699 key = RGB15_TO_COLORKEY(key); 700 flags |= CLK_RGB15_MASK; 701 break; 702 case DRM_FORMAT_RGB565: 703 key = RGB16_TO_COLORKEY(key); 704 flags |= CLK_RGB16_MASK; 705 break; 706 case DRM_FORMAT_XRGB2101010: 707 case DRM_FORMAT_XBGR2101010: 708 key = RGB30_TO_COLORKEY(key); 709 flags |= CLK_RGB24_MASK; 710 break; 711 default: 712 flags |= CLK_RGB24_MASK; 713 break; 714 } 715 716 iowrite32(key, ®s->DCLRKV); 717 iowrite32(flags, ®s->DCLRKM); 718 } 719 720 static u32 overlay_cmd_reg(struct drm_intel_overlay_put_image *params) 721 { 722 u32 cmd = OCMD_ENABLE | OCMD_BUF_TYPE_FRAME | OCMD_BUFFER0; 723 724 if (params->flags & I915_OVERLAY_YUV_PLANAR) { 725 switch (params->flags & I915_OVERLAY_DEPTH_MASK) { 726 case I915_OVERLAY_YUV422: 727 cmd |= OCMD_YUV_422_PLANAR; 728 break; 729 case I915_OVERLAY_YUV420: 730 cmd |= OCMD_YUV_420_PLANAR; 731 break; 732 case I915_OVERLAY_YUV411: 733 case I915_OVERLAY_YUV410: 734 cmd |= OCMD_YUV_410_PLANAR; 735 break; 736 } 737 } else { /* YUV packed */ 738 switch (params->flags & I915_OVERLAY_DEPTH_MASK) { 739 case I915_OVERLAY_YUV422: 740 cmd |= OCMD_YUV_422_PACKED; 741 break; 742 case I915_OVERLAY_YUV411: 743 cmd |= OCMD_YUV_411_PACKED; 744 break; 745 } 746 747 switch (params->flags & I915_OVERLAY_SWAP_MASK) { 748 case I915_OVERLAY_NO_SWAP: 749 break; 750 case I915_OVERLAY_UV_SWAP: 751 cmd |= OCMD_UV_SWAP; 752 break; 753 case I915_OVERLAY_Y_SWAP: 754 cmd |= OCMD_Y_SWAP; 755 break; 756 case I915_OVERLAY_Y_AND_UV_SWAP: 757 cmd |= OCMD_Y_AND_UV_SWAP; 758 break; 759 } 760 } 761 762 return cmd; 763 } 764 765 static struct i915_vma *intel_overlay_pin_fb(struct drm_i915_gem_object *new_bo) 766 { 767 struct i915_gem_ww_ctx ww; 768 struct i915_vma *vma; 769 int ret; 770 771 i915_gem_ww_ctx_init(&ww, true); 772 retry: 773 ret = i915_gem_object_lock(new_bo, &ww); 774 if (!ret) { 775 vma = i915_gem_object_pin_to_display_plane(new_bo, &ww, 0, 776 NULL, PIN_MAPPABLE); 777 ret = PTR_ERR_OR_ZERO(vma); 778 } 779 if (ret == -EDEADLK) { 780 ret = i915_gem_ww_ctx_backoff(&ww); 781 if (!ret) 782 goto retry; 783 } 784 i915_gem_ww_ctx_fini(&ww); 785 if (ret) 786 return ERR_PTR(ret); 787 788 return vma; 789 } 790 791 static int intel_overlay_do_put_image(struct intel_overlay *overlay, 792 struct drm_i915_gem_object *new_bo, 793 struct drm_intel_overlay_put_image *params) 794 { 795 struct intel_display *display = overlay->display; 796 struct drm_i915_private *dev_priv = to_i915(display->drm); 797 struct overlay_registers __iomem *regs = overlay->regs; 798 u32 swidth, swidthsw, sheight, ostride; 799 enum pipe pipe = overlay->crtc->pipe; 800 bool scale_changed = false; 801 struct i915_vma *vma; 802 int ret, tmp_width; 803 804 drm_WARN_ON(display->drm, 805 !drm_modeset_is_locked(&display->drm->mode_config.connection_mutex)); 806 807 ret = intel_overlay_release_old_vid(overlay); 808 if (ret != 0) 809 return ret; 810 811 atomic_inc(&dev_priv->gpu_error.pending_fb_pin); 812 813 vma = intel_overlay_pin_fb(new_bo); 814 if (IS_ERR(vma)) { 815 ret = PTR_ERR(vma); 816 goto out_pin_section; 817 } 818 819 i915_gem_object_flush_frontbuffer(new_bo, ORIGIN_DIRTYFB); 820 821 if (!overlay->active) { 822 const struct intel_crtc_state *crtc_state = 823 overlay->crtc->config; 824 u32 oconfig = 0; 825 826 if (crtc_state->gamma_enable && 827 crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT) 828 oconfig |= OCONF_CC_OUT_8BIT; 829 if (crtc_state->gamma_enable) 830 oconfig |= OCONF_GAMMA2_ENABLE; 831 if (DISPLAY_VER(display) == 4) 832 oconfig |= OCONF_CSC_MODE_BT709; 833 oconfig |= pipe == 0 ? 834 OCONF_PIPE_A : OCONF_PIPE_B; 835 iowrite32(oconfig, ®s->OCONFIG); 836 837 ret = intel_overlay_on(overlay); 838 if (ret != 0) 839 goto out_unpin; 840 } 841 842 iowrite32(params->dst_y << 16 | params->dst_x, ®s->DWINPOS); 843 iowrite32(params->dst_height << 16 | params->dst_width, ®s->DWINSZ); 844 845 if (params->flags & I915_OVERLAY_YUV_PACKED) 846 tmp_width = packed_width_bytes(params->flags, 847 params->src_width); 848 else 849 tmp_width = params->src_width; 850 851 swidth = params->src_width; 852 swidthsw = calc_swidthsw(display, params->offset_Y, tmp_width); 853 sheight = params->src_height; 854 iowrite32(i915_ggtt_offset(vma) + params->offset_Y, ®s->OBUF_0Y); 855 ostride = params->stride_Y; 856 857 if (params->flags & I915_OVERLAY_YUV_PLANAR) { 858 int uv_hscale = uv_hsubsampling(params->flags); 859 int uv_vscale = uv_vsubsampling(params->flags); 860 u32 tmp_U, tmp_V; 861 862 swidth |= (params->src_width / uv_hscale) << 16; 863 sheight |= (params->src_height / uv_vscale) << 16; 864 865 tmp_U = calc_swidthsw(display, params->offset_U, 866 params->src_width / uv_hscale); 867 tmp_V = calc_swidthsw(display, params->offset_V, 868 params->src_width / uv_hscale); 869 swidthsw |= max(tmp_U, tmp_V) << 16; 870 871 iowrite32(i915_ggtt_offset(vma) + params->offset_U, 872 ®s->OBUF_0U); 873 iowrite32(i915_ggtt_offset(vma) + params->offset_V, 874 ®s->OBUF_0V); 875 876 ostride |= params->stride_UV << 16; 877 } 878 879 iowrite32(swidth, ®s->SWIDTH); 880 iowrite32(swidthsw, ®s->SWIDTHSW); 881 iowrite32(sheight, ®s->SHEIGHT); 882 iowrite32(ostride, ®s->OSTRIDE); 883 884 scale_changed = update_scaling_factors(overlay, regs, params); 885 886 update_colorkey(overlay, regs); 887 888 iowrite32(overlay_cmd_reg(params), ®s->OCMD); 889 890 ret = intel_overlay_continue(overlay, vma, scale_changed); 891 if (ret) 892 goto out_unpin; 893 894 return 0; 895 896 out_unpin: 897 i915_vma_unpin(vma); 898 out_pin_section: 899 atomic_dec(&dev_priv->gpu_error.pending_fb_pin); 900 901 return ret; 902 } 903 904 int intel_overlay_switch_off(struct intel_overlay *overlay) 905 { 906 struct intel_display *display = overlay->display; 907 int ret; 908 909 drm_WARN_ON(display->drm, 910 !drm_modeset_is_locked(&display->drm->mode_config.connection_mutex)); 911 912 ret = intel_overlay_recover_from_interrupt(overlay); 913 if (ret != 0) 914 return ret; 915 916 if (!overlay->active) 917 return 0; 918 919 ret = intel_overlay_release_old_vid(overlay); 920 if (ret != 0) 921 return ret; 922 923 iowrite32(0, &overlay->regs->OCMD); 924 925 return intel_overlay_off(overlay); 926 } 927 928 static int check_overlay_possible_on_crtc(struct intel_overlay *overlay, 929 struct intel_crtc *crtc) 930 { 931 if (!crtc->active) 932 return -EINVAL; 933 934 /* can't use the overlay with double wide pipe */ 935 if (crtc->config->double_wide) 936 return -EINVAL; 937 938 return 0; 939 } 940 941 static void update_pfit_vscale_ratio(struct intel_overlay *overlay) 942 { 943 struct intel_display *display = overlay->display; 944 u32 ratio; 945 946 /* XXX: This is not the same logic as in the xorg driver, but more in 947 * line with the intel documentation for the i965 948 */ 949 if (DISPLAY_VER(display) >= 4) { 950 u32 tmp = intel_de_read(display, PFIT_PGM_RATIOS(display)); 951 952 /* on i965 use the PGM reg to read out the autoscaler values */ 953 ratio = REG_FIELD_GET(PFIT_VERT_SCALE_MASK_965, tmp); 954 } else { 955 u32 tmp; 956 957 if (intel_de_read(display, PFIT_CONTROL(display)) & PFIT_VERT_AUTO_SCALE) 958 tmp = intel_de_read(display, PFIT_AUTO_RATIOS(display)); 959 else 960 tmp = intel_de_read(display, PFIT_PGM_RATIOS(display)); 961 962 ratio = REG_FIELD_GET(PFIT_VERT_SCALE_MASK, tmp); 963 } 964 965 overlay->pfit_vscale_ratio = ratio; 966 } 967 968 static int check_overlay_dst(struct intel_overlay *overlay, 969 struct drm_intel_overlay_put_image *rec) 970 { 971 const struct intel_crtc_state *crtc_state = 972 overlay->crtc->config; 973 struct drm_rect req, clipped; 974 975 drm_rect_init(&req, rec->dst_x, rec->dst_y, 976 rec->dst_width, rec->dst_height); 977 978 clipped = req; 979 980 if (!drm_rect_intersect(&clipped, &crtc_state->pipe_src)) 981 return -EINVAL; 982 983 if (!drm_rect_equals(&clipped, &req)) 984 return -EINVAL; 985 986 return 0; 987 } 988 989 static int check_overlay_scaling(struct drm_intel_overlay_put_image *rec) 990 { 991 u32 tmp; 992 993 /* downscaling limit is 8.0 */ 994 tmp = ((rec->src_scan_height << 16) / rec->dst_height) >> 16; 995 if (tmp > 7) 996 return -EINVAL; 997 998 tmp = ((rec->src_scan_width << 16) / rec->dst_width) >> 16; 999 if (tmp > 7) 1000 return -EINVAL; 1001 1002 return 0; 1003 } 1004 1005 static int check_overlay_src(struct intel_display *display, 1006 struct drm_intel_overlay_put_image *rec, 1007 struct drm_i915_gem_object *new_bo) 1008 { 1009 int uv_hscale = uv_hsubsampling(rec->flags); 1010 int uv_vscale = uv_vsubsampling(rec->flags); 1011 u32 stride_mask; 1012 int depth; 1013 u32 tmp; 1014 1015 /* check src dimensions */ 1016 if (display->platform.i845g || display->platform.i830) { 1017 if (rec->src_height > IMAGE_MAX_HEIGHT_LEGACY || 1018 rec->src_width > IMAGE_MAX_WIDTH_LEGACY) 1019 return -EINVAL; 1020 } else { 1021 if (rec->src_height > IMAGE_MAX_HEIGHT || 1022 rec->src_width > IMAGE_MAX_WIDTH) 1023 return -EINVAL; 1024 } 1025 1026 /* better safe than sorry, use 4 as the maximal subsampling ratio */ 1027 if (rec->src_height < N_VERT_Y_TAPS*4 || 1028 rec->src_width < N_HORIZ_Y_TAPS*4) 1029 return -EINVAL; 1030 1031 /* check alignment constraints */ 1032 switch (rec->flags & I915_OVERLAY_TYPE_MASK) { 1033 case I915_OVERLAY_RGB: 1034 /* not implemented */ 1035 return -EINVAL; 1036 1037 case I915_OVERLAY_YUV_PACKED: 1038 if (uv_vscale != 1) 1039 return -EINVAL; 1040 1041 depth = packed_depth_bytes(rec->flags); 1042 if (depth < 0) 1043 return depth; 1044 1045 /* ignore UV planes */ 1046 rec->stride_UV = 0; 1047 rec->offset_U = 0; 1048 rec->offset_V = 0; 1049 /* check pixel alignment */ 1050 if (rec->offset_Y % depth) 1051 return -EINVAL; 1052 break; 1053 1054 case I915_OVERLAY_YUV_PLANAR: 1055 if (uv_vscale < 0 || uv_hscale < 0) 1056 return -EINVAL; 1057 /* no offset restrictions for planar formats */ 1058 break; 1059 1060 default: 1061 return -EINVAL; 1062 } 1063 1064 if (rec->src_width % uv_hscale) 1065 return -EINVAL; 1066 1067 /* stride checking */ 1068 if (display->platform.i830 || display->platform.i845g) 1069 stride_mask = 255; 1070 else 1071 stride_mask = 63; 1072 1073 if (rec->stride_Y & stride_mask || rec->stride_UV & stride_mask) 1074 return -EINVAL; 1075 if (DISPLAY_VER(display) == 4 && rec->stride_Y < 512) 1076 return -EINVAL; 1077 1078 tmp = (rec->flags & I915_OVERLAY_TYPE_MASK) == I915_OVERLAY_YUV_PLANAR ? 1079 4096 : 8192; 1080 if (rec->stride_Y > tmp || rec->stride_UV > 2*1024) 1081 return -EINVAL; 1082 1083 /* check buffer dimensions */ 1084 switch (rec->flags & I915_OVERLAY_TYPE_MASK) { 1085 case I915_OVERLAY_RGB: 1086 case I915_OVERLAY_YUV_PACKED: 1087 /* always 4 Y values per depth pixels */ 1088 if (packed_width_bytes(rec->flags, rec->src_width) > rec->stride_Y) 1089 return -EINVAL; 1090 1091 tmp = rec->stride_Y*rec->src_height; 1092 if (rec->offset_Y + tmp > new_bo->base.size) 1093 return -EINVAL; 1094 break; 1095 1096 case I915_OVERLAY_YUV_PLANAR: 1097 if (rec->src_width > rec->stride_Y) 1098 return -EINVAL; 1099 if (rec->src_width/uv_hscale > rec->stride_UV) 1100 return -EINVAL; 1101 1102 tmp = rec->stride_Y * rec->src_height; 1103 if (rec->offset_Y + tmp > new_bo->base.size) 1104 return -EINVAL; 1105 1106 tmp = rec->stride_UV * (rec->src_height / uv_vscale); 1107 if (rec->offset_U + tmp > new_bo->base.size || 1108 rec->offset_V + tmp > new_bo->base.size) 1109 return -EINVAL; 1110 break; 1111 } 1112 1113 return 0; 1114 } 1115 1116 int intel_overlay_put_image_ioctl(struct drm_device *dev, void *data, 1117 struct drm_file *file_priv) 1118 { 1119 struct intel_display *display = to_intel_display(dev); 1120 struct drm_intel_overlay_put_image *params = data; 1121 struct intel_overlay *overlay; 1122 struct drm_crtc *drmmode_crtc; 1123 struct intel_crtc *crtc; 1124 struct drm_i915_gem_object *new_bo; 1125 int ret; 1126 1127 overlay = display->overlay; 1128 if (!overlay) { 1129 drm_dbg(display->drm, "userspace bug: no overlay\n"); 1130 return -ENODEV; 1131 } 1132 1133 if (!(params->flags & I915_OVERLAY_ENABLE)) { 1134 drm_modeset_lock_all(dev); 1135 ret = intel_overlay_switch_off(overlay); 1136 drm_modeset_unlock_all(dev); 1137 1138 return ret; 1139 } 1140 1141 drmmode_crtc = drm_crtc_find(dev, file_priv, params->crtc_id); 1142 if (!drmmode_crtc) 1143 return -ENOENT; 1144 crtc = to_intel_crtc(drmmode_crtc); 1145 1146 new_bo = i915_gem_object_lookup(file_priv, params->bo_handle); 1147 if (!new_bo) 1148 return -ENOENT; 1149 1150 drm_modeset_lock_all(dev); 1151 1152 if (i915_gem_object_is_tiled(new_bo)) { 1153 drm_dbg_kms(display->drm, 1154 "buffer used for overlay image can not be tiled\n"); 1155 ret = -EINVAL; 1156 goto out_unlock; 1157 } 1158 1159 ret = intel_overlay_recover_from_interrupt(overlay); 1160 if (ret != 0) 1161 goto out_unlock; 1162 1163 if (overlay->crtc != crtc) { 1164 ret = intel_overlay_switch_off(overlay); 1165 if (ret != 0) 1166 goto out_unlock; 1167 1168 ret = check_overlay_possible_on_crtc(overlay, crtc); 1169 if (ret != 0) 1170 goto out_unlock; 1171 1172 overlay->crtc = crtc; 1173 crtc->overlay = overlay; 1174 1175 /* line too wide, i.e. one-line-mode */ 1176 if (drm_rect_width(&crtc->config->pipe_src) > 1024 && 1177 crtc->config->gmch_pfit.control & PFIT_ENABLE) { 1178 overlay->pfit_active = true; 1179 update_pfit_vscale_ratio(overlay); 1180 } else 1181 overlay->pfit_active = false; 1182 } 1183 1184 ret = check_overlay_dst(overlay, params); 1185 if (ret != 0) 1186 goto out_unlock; 1187 1188 if (overlay->pfit_active) { 1189 params->dst_y = (((u32)params->dst_y << 12) / 1190 overlay->pfit_vscale_ratio); 1191 /* shifting right rounds downwards, so add 1 */ 1192 params->dst_height = (((u32)params->dst_height << 12) / 1193 overlay->pfit_vscale_ratio) + 1; 1194 } 1195 1196 if (params->src_scan_height > params->src_height || 1197 params->src_scan_width > params->src_width) { 1198 ret = -EINVAL; 1199 goto out_unlock; 1200 } 1201 1202 ret = check_overlay_src(display, params, new_bo); 1203 if (ret != 0) 1204 goto out_unlock; 1205 1206 /* Check scaling after src size to prevent a divide-by-zero. */ 1207 ret = check_overlay_scaling(params); 1208 if (ret != 0) 1209 goto out_unlock; 1210 1211 ret = intel_overlay_do_put_image(overlay, new_bo, params); 1212 if (ret != 0) 1213 goto out_unlock; 1214 1215 drm_modeset_unlock_all(dev); 1216 i915_gem_object_put(new_bo); 1217 1218 return 0; 1219 1220 out_unlock: 1221 drm_modeset_unlock_all(dev); 1222 i915_gem_object_put(new_bo); 1223 1224 return ret; 1225 } 1226 1227 static void update_reg_attrs(struct intel_overlay *overlay, 1228 struct overlay_registers __iomem *regs) 1229 { 1230 iowrite32((overlay->contrast << 18) | (overlay->brightness & 0xff), 1231 ®s->OCLRC0); 1232 iowrite32(overlay->saturation, ®s->OCLRC1); 1233 } 1234 1235 static bool check_gamma_bounds(u32 gamma1, u32 gamma2) 1236 { 1237 int i; 1238 1239 if (gamma1 & 0xff000000 || gamma2 & 0xff000000) 1240 return false; 1241 1242 for (i = 0; i < 3; i++) { 1243 if (((gamma1 >> i*8) & 0xff) >= ((gamma2 >> i*8) & 0xff)) 1244 return false; 1245 } 1246 1247 return true; 1248 } 1249 1250 static bool check_gamma5_errata(u32 gamma5) 1251 { 1252 int i; 1253 1254 for (i = 0; i < 3; i++) { 1255 if (((gamma5 >> i*8) & 0xff) == 0x80) 1256 return false; 1257 } 1258 1259 return true; 1260 } 1261 1262 static int check_gamma(struct drm_intel_overlay_attrs *attrs) 1263 { 1264 if (!check_gamma_bounds(0, attrs->gamma0) || 1265 !check_gamma_bounds(attrs->gamma0, attrs->gamma1) || 1266 !check_gamma_bounds(attrs->gamma1, attrs->gamma2) || 1267 !check_gamma_bounds(attrs->gamma2, attrs->gamma3) || 1268 !check_gamma_bounds(attrs->gamma3, attrs->gamma4) || 1269 !check_gamma_bounds(attrs->gamma4, attrs->gamma5) || 1270 !check_gamma_bounds(attrs->gamma5, 0x00ffffff)) 1271 return -EINVAL; 1272 1273 if (!check_gamma5_errata(attrs->gamma5)) 1274 return -EINVAL; 1275 1276 return 0; 1277 } 1278 1279 int intel_overlay_attrs_ioctl(struct drm_device *dev, void *data, 1280 struct drm_file *file_priv) 1281 { 1282 struct intel_display *display = to_intel_display(dev); 1283 struct drm_intel_overlay_attrs *attrs = data; 1284 struct intel_overlay *overlay; 1285 int ret; 1286 1287 overlay = display->overlay; 1288 if (!overlay) { 1289 drm_dbg(display->drm, "userspace bug: no overlay\n"); 1290 return -ENODEV; 1291 } 1292 1293 drm_modeset_lock_all(dev); 1294 1295 ret = -EINVAL; 1296 if (!(attrs->flags & I915_OVERLAY_UPDATE_ATTRS)) { 1297 attrs->color_key = overlay->color_key; 1298 attrs->brightness = overlay->brightness; 1299 attrs->contrast = overlay->contrast; 1300 attrs->saturation = overlay->saturation; 1301 1302 if (DISPLAY_VER(display) != 2) { 1303 attrs->gamma0 = intel_de_read(display, OGAMC0); 1304 attrs->gamma1 = intel_de_read(display, OGAMC1); 1305 attrs->gamma2 = intel_de_read(display, OGAMC2); 1306 attrs->gamma3 = intel_de_read(display, OGAMC3); 1307 attrs->gamma4 = intel_de_read(display, OGAMC4); 1308 attrs->gamma5 = intel_de_read(display, OGAMC5); 1309 } 1310 } else { 1311 if (attrs->brightness < -128 || attrs->brightness > 127) 1312 goto out_unlock; 1313 if (attrs->contrast > 255) 1314 goto out_unlock; 1315 if (attrs->saturation > 1023) 1316 goto out_unlock; 1317 1318 overlay->color_key = attrs->color_key; 1319 overlay->brightness = attrs->brightness; 1320 overlay->contrast = attrs->contrast; 1321 overlay->saturation = attrs->saturation; 1322 1323 update_reg_attrs(overlay, overlay->regs); 1324 1325 if (attrs->flags & I915_OVERLAY_UPDATE_GAMMA) { 1326 if (DISPLAY_VER(display) == 2) 1327 goto out_unlock; 1328 1329 if (overlay->active) { 1330 ret = -EBUSY; 1331 goto out_unlock; 1332 } 1333 1334 ret = check_gamma(attrs); 1335 if (ret) 1336 goto out_unlock; 1337 1338 intel_de_write(display, OGAMC0, attrs->gamma0); 1339 intel_de_write(display, OGAMC1, attrs->gamma1); 1340 intel_de_write(display, OGAMC2, attrs->gamma2); 1341 intel_de_write(display, OGAMC3, attrs->gamma3); 1342 intel_de_write(display, OGAMC4, attrs->gamma4); 1343 intel_de_write(display, OGAMC5, attrs->gamma5); 1344 } 1345 } 1346 overlay->color_key_enabled = (attrs->flags & I915_OVERLAY_DISABLE_DEST_COLORKEY) == 0; 1347 1348 ret = 0; 1349 out_unlock: 1350 drm_modeset_unlock_all(dev); 1351 1352 return ret; 1353 } 1354 1355 static int get_registers(struct intel_overlay *overlay, bool use_phys) 1356 { 1357 struct intel_display *display = overlay->display; 1358 struct drm_i915_private *i915 = to_i915(display->drm); 1359 struct drm_i915_gem_object *obj = ERR_PTR(-ENODEV); 1360 struct i915_vma *vma; 1361 int err; 1362 1363 if (!display->platform.meteorlake) /* Wa_22018444074 */ 1364 obj = i915_gem_object_create_stolen(i915, PAGE_SIZE); 1365 if (IS_ERR(obj)) 1366 obj = i915_gem_object_create_internal(i915, PAGE_SIZE); 1367 if (IS_ERR(obj)) 1368 return PTR_ERR(obj); 1369 1370 vma = i915_gem_object_ggtt_pin(obj, NULL, 0, 0, PIN_MAPPABLE); 1371 if (IS_ERR(vma)) { 1372 err = PTR_ERR(vma); 1373 goto err_put_bo; 1374 } 1375 1376 if (use_phys) 1377 overlay->flip_addr = sg_dma_address(obj->mm.pages->sgl); 1378 else 1379 overlay->flip_addr = i915_ggtt_offset(vma); 1380 overlay->regs = i915_vma_pin_iomap(vma); 1381 i915_vma_unpin(vma); 1382 1383 if (IS_ERR(overlay->regs)) { 1384 err = PTR_ERR(overlay->regs); 1385 goto err_put_bo; 1386 } 1387 1388 overlay->reg_bo = obj; 1389 return 0; 1390 1391 err_put_bo: 1392 i915_gem_object_put(obj); 1393 return err; 1394 } 1395 1396 void intel_overlay_setup(struct intel_display *display) 1397 { 1398 struct drm_i915_private *dev_priv = to_i915(display->drm); 1399 struct intel_overlay *overlay; 1400 struct intel_engine_cs *engine; 1401 int ret; 1402 1403 if (!HAS_OVERLAY(display)) 1404 return; 1405 1406 engine = to_gt(dev_priv)->engine[RCS0]; 1407 if (!engine || !engine->kernel_context) 1408 return; 1409 1410 overlay = kzalloc(sizeof(*overlay), GFP_KERNEL); 1411 if (!overlay) 1412 return; 1413 1414 overlay->display = display; 1415 overlay->context = engine->kernel_context; 1416 overlay->color_key = 0x0101fe; 1417 overlay->color_key_enabled = true; 1418 overlay->brightness = -19; 1419 overlay->contrast = 75; 1420 overlay->saturation = 146; 1421 1422 i915_active_init(&overlay->last_flip, 1423 NULL, intel_overlay_last_flip_retire, 0); 1424 1425 ret = get_registers(overlay, OVERLAY_NEEDS_PHYSICAL(display)); 1426 if (ret) 1427 goto out_free; 1428 1429 memset_io(overlay->regs, 0, sizeof(struct overlay_registers)); 1430 update_polyphase_filter(overlay->regs); 1431 update_reg_attrs(overlay, overlay->regs); 1432 1433 display->overlay = overlay; 1434 drm_info(display->drm, "Initialized overlay support.\n"); 1435 return; 1436 1437 out_free: 1438 kfree(overlay); 1439 } 1440 1441 bool intel_overlay_available(struct intel_display *display) 1442 { 1443 return display->overlay; 1444 } 1445 1446 void intel_overlay_cleanup(struct intel_display *display) 1447 { 1448 struct intel_overlay *overlay; 1449 1450 overlay = fetch_and_zero(&display->overlay); 1451 if (!overlay) 1452 return; 1453 1454 /* 1455 * The bo's should be free'd by the generic code already. 1456 * Furthermore modesetting teardown happens beforehand so the 1457 * hardware should be off already. 1458 */ 1459 drm_WARN_ON(display->drm, overlay->active); 1460 1461 i915_gem_object_put(overlay->reg_bo); 1462 i915_active_fini(&overlay->last_flip); 1463 1464 kfree(overlay); 1465 } 1466 1467 #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR) 1468 1469 struct intel_overlay_snapshot { 1470 struct overlay_registers regs; 1471 unsigned long base; 1472 u32 dovsta; 1473 u32 isr; 1474 }; 1475 1476 struct intel_overlay_snapshot * 1477 intel_overlay_snapshot_capture(struct intel_display *display) 1478 { 1479 struct intel_overlay *overlay = display->overlay; 1480 struct intel_overlay_snapshot *error; 1481 1482 if (!overlay || !overlay->active) 1483 return NULL; 1484 1485 error = kmalloc(sizeof(*error), GFP_ATOMIC); 1486 if (error == NULL) 1487 return NULL; 1488 1489 error->dovsta = intel_de_read(display, DOVSTA); 1490 error->isr = intel_de_read(display, GEN2_ISR); 1491 error->base = overlay->flip_addr; 1492 1493 memcpy_fromio(&error->regs, overlay->regs, sizeof(error->regs)); 1494 1495 return error; 1496 } 1497 1498 void 1499 intel_overlay_snapshot_print(const struct intel_overlay_snapshot *error, 1500 struct drm_printer *p) 1501 { 1502 if (!error) 1503 return; 1504 1505 drm_printf(p, "Overlay, status: 0x%08x, interrupt: 0x%08x\n", 1506 error->dovsta, error->isr); 1507 drm_printf(p, " Register file at 0x%08lx:\n", error->base); 1508 1509 #define P(x) drm_printf(p, " " #x ": 0x%08x\n", error->regs.x) 1510 P(OBUF_0Y); 1511 P(OBUF_1Y); 1512 P(OBUF_0U); 1513 P(OBUF_0V); 1514 P(OBUF_1U); 1515 P(OBUF_1V); 1516 P(OSTRIDE); 1517 P(YRGB_VPH); 1518 P(UV_VPH); 1519 P(HORZ_PH); 1520 P(INIT_PHS); 1521 P(DWINPOS); 1522 P(DWINSZ); 1523 P(SWIDTH); 1524 P(SWIDTHSW); 1525 P(SHEIGHT); 1526 P(YRGBSCALE); 1527 P(UVSCALE); 1528 P(OCLRC0); 1529 P(OCLRC1); 1530 P(DCLRKV); 1531 P(DCLRKM); 1532 P(SCLRKVH); 1533 P(SCLRKVL); 1534 P(SCLRKEN); 1535 P(OCONFIG); 1536 P(OCMD); 1537 P(OSTART_0Y); 1538 P(OSTART_1Y); 1539 P(OSTART_0U); 1540 P(OSTART_0V); 1541 P(OSTART_1U); 1542 P(OSTART_1V); 1543 P(OTILEOFF_0Y); 1544 P(OTILEOFF_1Y); 1545 P(OTILEOFF_0U); 1546 P(OTILEOFF_0V); 1547 P(OTILEOFF_1U); 1548 P(OTILEOFF_1V); 1549 P(FASTHSCALE); 1550 P(UVSCALEV); 1551 #undef P 1552 } 1553 1554 #endif 1555