1 /* 2 * Copyright © 2009 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 * SOFTWARE. 22 * 23 * Authors: 24 * Daniel Vetter <daniel@ffwll.ch> 25 * 26 * Derived from Xorg ddx, xf86-video-intel, src/i830_video.c 27 */ 28 29 #include <drm/drm_fourcc.h> 30 #include <drm/drm_gem.h> 31 #include <drm/drm_print.h> 32 33 #include "intel_color_regs.h" 34 #include "intel_de.h" 35 #include "intel_display_regs.h" 36 #include "intel_display_types.h" 37 #include "intel_frontbuffer.h" 38 #include "intel_overlay.h" 39 #include "intel_parent.h" 40 #include "intel_pfit_regs.h" 41 42 /* Limits for overlay size. According to intel doc, the real limits are: 43 * Y width: 4095, UV width (planar): 2047, Y height: 2047, 44 * UV width (planar): * 1023. But the xorg thinks 2048 for height and width. Use 45 * the minimum of both. 46 */ 47 #define IMAGE_MAX_WIDTH 2048 48 #define IMAGE_MAX_HEIGHT 2046 /* 2 * 1023 */ 49 /* on 830 and 845 these large limits result in the card hanging */ 50 #define IMAGE_MAX_WIDTH_LEGACY 1024 51 #define IMAGE_MAX_HEIGHT_LEGACY 1088 52 53 /* overlay register definitions */ 54 /* OCMD register */ 55 #define OCMD_TILED_SURFACE (0x1<<19) 56 #define OCMD_MIRROR_MASK (0x3<<17) 57 #define OCMD_MIRROR_MODE (0x3<<17) 58 #define OCMD_MIRROR_HORIZONTAL (0x1<<17) 59 #define OCMD_MIRROR_VERTICAL (0x2<<17) 60 #define OCMD_MIRROR_BOTH (0x3<<17) 61 #define OCMD_BYTEORDER_MASK (0x3<<14) /* zero for YUYV or FOURCC YUY2 */ 62 #define OCMD_UV_SWAP (0x1<<14) /* YVYU */ 63 #define OCMD_Y_SWAP (0x2<<14) /* UYVY or FOURCC UYVY */ 64 #define OCMD_Y_AND_UV_SWAP (0x3<<14) /* VYUY */ 65 #define OCMD_SOURCE_FORMAT_MASK (0xf<<10) 66 #define OCMD_RGB_888 (0x1<<10) /* not in i965 Intel docs */ 67 #define OCMD_RGB_555 (0x2<<10) /* not in i965 Intel docs */ 68 #define OCMD_RGB_565 (0x3<<10) /* not in i965 Intel docs */ 69 #define OCMD_YUV_422_PACKED (0x8<<10) 70 #define OCMD_YUV_411_PACKED (0x9<<10) /* not in i965 Intel docs */ 71 #define OCMD_YUV_420_PLANAR (0xc<<10) 72 #define OCMD_YUV_422_PLANAR (0xd<<10) 73 #define OCMD_YUV_410_PLANAR (0xe<<10) /* also 411 */ 74 #define OCMD_TVSYNCFLIP_PARITY (0x1<<9) 75 #define OCMD_TVSYNCFLIP_ENABLE (0x1<<7) 76 #define OCMD_BUF_TYPE_MASK (0x1<<5) 77 #define OCMD_BUF_TYPE_FRAME (0x0<<5) 78 #define OCMD_BUF_TYPE_FIELD (0x1<<5) 79 #define OCMD_TEST_MODE (0x1<<4) 80 #define OCMD_BUFFER_SELECT (0x3<<2) 81 #define OCMD_BUFFER0 (0x0<<2) 82 #define OCMD_BUFFER1 (0x1<<2) 83 #define OCMD_FIELD_SELECT (0x1<<2) 84 #define OCMD_FIELD0 (0x0<<1) 85 #define OCMD_FIELD1 (0x1<<1) 86 #define OCMD_ENABLE (0x1<<0) 87 88 /* OCONFIG register */ 89 #define OCONF_PIPE_MASK (0x1<<18) 90 #define OCONF_PIPE_A (0x0<<18) 91 #define OCONF_PIPE_B (0x1<<18) 92 #define OCONF_GAMMA2_ENABLE (0x1<<16) 93 #define OCONF_CSC_MODE_BT601 (0x0<<5) 94 #define OCONF_CSC_MODE_BT709 (0x1<<5) 95 #define OCONF_CSC_BYPASS (0x1<<4) 96 #define OCONF_CC_OUT_8BIT (0x1<<3) 97 #define OCONF_TEST_MODE (0x1<<2) 98 #define OCONF_THREE_LINE_BUFFER (0x1<<0) 99 #define OCONF_TWO_LINE_BUFFER (0x0<<0) 100 101 /* DCLRKM (dst-key) register */ 102 #define DST_KEY_ENABLE (0x1<<31) 103 #define CLK_RGB24_MASK 0x0 104 #define CLK_RGB16_MASK 0x070307 105 #define CLK_RGB15_MASK 0x070707 106 107 #define RGB30_TO_COLORKEY(c) \ 108 ((((c) & 0x3fc00000) >> 6) | (((c) & 0x000ff000) >> 4) | (((c) & 0x000003fc) >> 2)) 109 #define RGB16_TO_COLORKEY(c) \ 110 ((((c) & 0xf800) << 8) | (((c) & 0x07e0) << 5) | (((c) & 0x001f) << 3)) 111 #define RGB15_TO_COLORKEY(c) \ 112 ((((c) & 0x7c00) << 9) | (((c) & 0x03e0) << 6) | (((c) & 0x001f) << 3)) 113 #define RGB8I_TO_COLORKEY(c) \ 114 ((((c) & 0xff) << 16) | (((c) & 0xff) << 8) | (((c) & 0xff) << 0)) 115 116 /* polyphase filter coefficients */ 117 #define N_HORIZ_Y_TAPS 5 118 #define N_VERT_Y_TAPS 3 119 #define N_HORIZ_UV_TAPS 3 120 #define N_VERT_UV_TAPS 3 121 #define N_PHASES 17 122 #define MAX_TAPS 5 123 124 /* memory bufferd overlay registers */ 125 struct overlay_registers { 126 u32 OBUF_0Y; 127 u32 OBUF_1Y; 128 u32 OBUF_0U; 129 u32 OBUF_0V; 130 u32 OBUF_1U; 131 u32 OBUF_1V; 132 u32 OSTRIDE; 133 u32 YRGB_VPH; 134 u32 UV_VPH; 135 u32 HORZ_PH; 136 u32 INIT_PHS; 137 u32 DWINPOS; 138 u32 DWINSZ; 139 u32 SWIDTH; 140 u32 SWIDTHSW; 141 u32 SHEIGHT; 142 u32 YRGBSCALE; 143 u32 UVSCALE; 144 u32 OCLRC0; 145 u32 OCLRC1; 146 u32 DCLRKV; 147 u32 DCLRKM; 148 u32 SCLRKVH; 149 u32 SCLRKVL; 150 u32 SCLRKEN; 151 u32 OCONFIG; 152 u32 OCMD; 153 u32 RESERVED1; /* 0x6C */ 154 u32 OSTART_0Y; 155 u32 OSTART_1Y; 156 u32 OSTART_0U; 157 u32 OSTART_0V; 158 u32 OSTART_1U; 159 u32 OSTART_1V; 160 u32 OTILEOFF_0Y; 161 u32 OTILEOFF_1Y; 162 u32 OTILEOFF_0U; 163 u32 OTILEOFF_0V; 164 u32 OTILEOFF_1U; 165 u32 OTILEOFF_1V; 166 u32 FASTHSCALE; /* 0xA0 */ 167 u32 UVSCALEV; /* 0xA4 */ 168 u32 RESERVEDC[(0x200 - 0xA8) / 4]; /* 0xA8 - 0x1FC */ 169 u16 Y_VCOEFS[N_VERT_Y_TAPS * N_PHASES]; /* 0x200 */ 170 u16 RESERVEDD[0x100 / 2 - N_VERT_Y_TAPS * N_PHASES]; 171 u16 Y_HCOEFS[N_HORIZ_Y_TAPS * N_PHASES]; /* 0x300 */ 172 u16 RESERVEDE[0x200 / 2 - N_HORIZ_Y_TAPS * N_PHASES]; 173 u16 UV_VCOEFS[N_VERT_UV_TAPS * N_PHASES]; /* 0x500 */ 174 u16 RESERVEDF[0x100 / 2 - N_VERT_UV_TAPS * N_PHASES]; 175 u16 UV_HCOEFS[N_HORIZ_UV_TAPS * N_PHASES]; /* 0x600 */ 176 u16 RESERVEDG[0x100 / 2 - N_HORIZ_UV_TAPS * N_PHASES]; 177 }; 178 179 struct intel_overlay { 180 struct intel_display *display; 181 struct intel_crtc *crtc; 182 bool pfit_active; 183 u32 pfit_vscale_ratio; /* shifted-point number, (1<<12) == 1.0 */ 184 u32 color_key:24; 185 u32 color_key_enabled:1; 186 u32 brightness, contrast, saturation; 187 u32 old_xscale, old_yscale; 188 struct overlay_registers __iomem *regs; 189 }; 190 191 void intel_overlay_reset(struct intel_display *display) 192 { 193 struct intel_overlay *overlay = display->overlay; 194 195 if (!overlay) 196 return; 197 198 overlay->old_xscale = 0; 199 overlay->old_yscale = 0; 200 overlay->crtc = NULL; 201 202 intel_parent_overlay_reset(display); 203 } 204 205 static int packed_depth_bytes(u32 format) 206 { 207 switch (format & I915_OVERLAY_DEPTH_MASK) { 208 case I915_OVERLAY_YUV422: 209 return 4; 210 case I915_OVERLAY_YUV411: 211 /* return 6; not implemented */ 212 default: 213 return -EINVAL; 214 } 215 } 216 217 static int packed_width_bytes(u32 format, short width) 218 { 219 switch (format & I915_OVERLAY_DEPTH_MASK) { 220 case I915_OVERLAY_YUV422: 221 return width << 1; 222 default: 223 return -EINVAL; 224 } 225 } 226 227 static int uv_hsubsampling(u32 format) 228 { 229 switch (format & I915_OVERLAY_DEPTH_MASK) { 230 case I915_OVERLAY_YUV422: 231 case I915_OVERLAY_YUV420: 232 return 2; 233 case I915_OVERLAY_YUV411: 234 case I915_OVERLAY_YUV410: 235 return 4; 236 default: 237 return -EINVAL; 238 } 239 } 240 241 static int uv_vsubsampling(u32 format) 242 { 243 switch (format & I915_OVERLAY_DEPTH_MASK) { 244 case I915_OVERLAY_YUV420: 245 case I915_OVERLAY_YUV410: 246 return 2; 247 case I915_OVERLAY_YUV422: 248 case I915_OVERLAY_YUV411: 249 return 1; 250 default: 251 return -EINVAL; 252 } 253 } 254 255 static u32 calc_swidthsw(struct intel_display *display, u32 offset, u32 width) 256 { 257 u32 sw; 258 259 if (DISPLAY_VER(display) == 2) 260 sw = ALIGN((offset & 31) + width, 32); 261 else 262 sw = ALIGN((offset & 63) + width, 64); 263 264 if (sw == 0) 265 return 0; 266 267 return (sw - 32) >> 3; 268 } 269 270 static const u16 y_static_hcoeffs[N_PHASES][N_HORIZ_Y_TAPS] = { 271 [ 0] = { 0x3000, 0xb4a0, 0x1930, 0x1920, 0xb4a0, }, 272 [ 1] = { 0x3000, 0xb500, 0x19d0, 0x1880, 0xb440, }, 273 [ 2] = { 0x3000, 0xb540, 0x1a88, 0x2f80, 0xb3e0, }, 274 [ 3] = { 0x3000, 0xb580, 0x1b30, 0x2e20, 0xb380, }, 275 [ 4] = { 0x3000, 0xb5c0, 0x1bd8, 0x2cc0, 0xb320, }, 276 [ 5] = { 0x3020, 0xb5e0, 0x1c60, 0x2b80, 0xb2c0, }, 277 [ 6] = { 0x3020, 0xb5e0, 0x1cf8, 0x2a20, 0xb260, }, 278 [ 7] = { 0x3020, 0xb5e0, 0x1d80, 0x28e0, 0xb200, }, 279 [ 8] = { 0x3020, 0xb5c0, 0x1e08, 0x3f40, 0xb1c0, }, 280 [ 9] = { 0x3020, 0xb580, 0x1e78, 0x3ce0, 0xb160, }, 281 [10] = { 0x3040, 0xb520, 0x1ed8, 0x3aa0, 0xb120, }, 282 [11] = { 0x3040, 0xb4a0, 0x1f30, 0x3880, 0xb0e0, }, 283 [12] = { 0x3040, 0xb400, 0x1f78, 0x3680, 0xb0a0, }, 284 [13] = { 0x3020, 0xb340, 0x1fb8, 0x34a0, 0xb060, }, 285 [14] = { 0x3020, 0xb240, 0x1fe0, 0x32e0, 0xb040, }, 286 [15] = { 0x3020, 0xb140, 0x1ff8, 0x3160, 0xb020, }, 287 [16] = { 0xb000, 0x3000, 0x0800, 0x3000, 0xb000, }, 288 }; 289 290 static const u16 uv_static_hcoeffs[N_PHASES][N_HORIZ_UV_TAPS] = { 291 [ 0] = { 0x3000, 0x1800, 0x1800, }, 292 [ 1] = { 0xb000, 0x18d0, 0x2e60, }, 293 [ 2] = { 0xb000, 0x1990, 0x2ce0, }, 294 [ 3] = { 0xb020, 0x1a68, 0x2b40, }, 295 [ 4] = { 0xb040, 0x1b20, 0x29e0, }, 296 [ 5] = { 0xb060, 0x1bd8, 0x2880, }, 297 [ 6] = { 0xb080, 0x1c88, 0x3e60, }, 298 [ 7] = { 0xb0a0, 0x1d28, 0x3c00, }, 299 [ 8] = { 0xb0c0, 0x1db8, 0x39e0, }, 300 [ 9] = { 0xb0e0, 0x1e40, 0x37e0, }, 301 [10] = { 0xb100, 0x1eb8, 0x3620, }, 302 [11] = { 0xb100, 0x1f18, 0x34a0, }, 303 [12] = { 0xb100, 0x1f68, 0x3360, }, 304 [13] = { 0xb0e0, 0x1fa8, 0x3240, }, 305 [14] = { 0xb0c0, 0x1fe0, 0x3140, }, 306 [15] = { 0xb060, 0x1ff0, 0x30a0, }, 307 [16] = { 0x3000, 0x0800, 0x3000, }, 308 }; 309 310 static void update_polyphase_filter(struct overlay_registers __iomem *regs) 311 { 312 memcpy_toio(regs->Y_HCOEFS, y_static_hcoeffs, sizeof(y_static_hcoeffs)); 313 memcpy_toio(regs->UV_HCOEFS, uv_static_hcoeffs, 314 sizeof(uv_static_hcoeffs)); 315 } 316 317 static bool update_scaling_factors(struct intel_overlay *overlay, 318 struct overlay_registers __iomem *regs, 319 struct drm_intel_overlay_put_image *params) 320 { 321 /* fixed point with a 12 bit shift */ 322 u32 xscale, yscale, xscale_UV, yscale_UV; 323 #define FP_SHIFT 12 324 #define FRACT_MASK 0xfff 325 bool scale_changed = false; 326 int uv_hscale = uv_hsubsampling(params->flags); 327 int uv_vscale = uv_vsubsampling(params->flags); 328 329 if (params->dst_width > 1) 330 xscale = ((params->src_scan_width - 1) << FP_SHIFT) / 331 params->dst_width; 332 else 333 xscale = 1 << FP_SHIFT; 334 335 if (params->dst_height > 1) 336 yscale = ((params->src_scan_height - 1) << FP_SHIFT) / 337 params->dst_height; 338 else 339 yscale = 1 << FP_SHIFT; 340 341 /*if (params->format & I915_OVERLAY_YUV_PLANAR) {*/ 342 xscale_UV = xscale/uv_hscale; 343 yscale_UV = yscale/uv_vscale; 344 /* make the Y scale to UV scale ratio an exact multiply */ 345 xscale = xscale_UV * uv_hscale; 346 yscale = yscale_UV * uv_vscale; 347 /*} else { 348 xscale_UV = 0; 349 yscale_UV = 0; 350 }*/ 351 352 if (xscale != overlay->old_xscale || yscale != overlay->old_yscale) 353 scale_changed = true; 354 overlay->old_xscale = xscale; 355 overlay->old_yscale = yscale; 356 357 iowrite32(((yscale & FRACT_MASK) << 20) | 358 ((xscale >> FP_SHIFT) << 16) | 359 ((xscale & FRACT_MASK) << 3), 360 ®s->YRGBSCALE); 361 362 iowrite32(((yscale_UV & FRACT_MASK) << 20) | 363 ((xscale_UV >> FP_SHIFT) << 16) | 364 ((xscale_UV & FRACT_MASK) << 3), 365 ®s->UVSCALE); 366 367 iowrite32((((yscale >> FP_SHIFT) << 16) | 368 ((yscale_UV >> FP_SHIFT) << 0)), 369 ®s->UVSCALEV); 370 371 if (scale_changed) 372 update_polyphase_filter(regs); 373 374 return scale_changed; 375 } 376 377 static void update_colorkey(struct intel_overlay *overlay, 378 struct overlay_registers __iomem *regs) 379 { 380 const struct intel_plane_state *state = 381 to_intel_plane_state(overlay->crtc->base.primary->state); 382 u32 key = overlay->color_key; 383 u32 format = 0; 384 u32 flags = 0; 385 386 if (overlay->color_key_enabled) 387 flags |= DST_KEY_ENABLE; 388 389 if (state->uapi.visible) 390 format = state->hw.fb->format->format; 391 392 switch (format) { 393 case DRM_FORMAT_C8: 394 key = RGB8I_TO_COLORKEY(key); 395 flags |= CLK_RGB24_MASK; 396 break; 397 case DRM_FORMAT_XRGB1555: 398 key = RGB15_TO_COLORKEY(key); 399 flags |= CLK_RGB15_MASK; 400 break; 401 case DRM_FORMAT_RGB565: 402 key = RGB16_TO_COLORKEY(key); 403 flags |= CLK_RGB16_MASK; 404 break; 405 case DRM_FORMAT_XRGB2101010: 406 case DRM_FORMAT_XBGR2101010: 407 key = RGB30_TO_COLORKEY(key); 408 flags |= CLK_RGB24_MASK; 409 break; 410 default: 411 flags |= CLK_RGB24_MASK; 412 break; 413 } 414 415 iowrite32(key, ®s->DCLRKV); 416 iowrite32(flags, ®s->DCLRKM); 417 } 418 419 static u32 overlay_cmd_reg(struct drm_intel_overlay_put_image *params) 420 { 421 u32 cmd = OCMD_ENABLE | OCMD_BUF_TYPE_FRAME | OCMD_BUFFER0; 422 423 if (params->flags & I915_OVERLAY_YUV_PLANAR) { 424 switch (params->flags & I915_OVERLAY_DEPTH_MASK) { 425 case I915_OVERLAY_YUV422: 426 cmd |= OCMD_YUV_422_PLANAR; 427 break; 428 case I915_OVERLAY_YUV420: 429 cmd |= OCMD_YUV_420_PLANAR; 430 break; 431 case I915_OVERLAY_YUV411: 432 case I915_OVERLAY_YUV410: 433 cmd |= OCMD_YUV_410_PLANAR; 434 break; 435 } 436 } else { /* YUV packed */ 437 switch (params->flags & I915_OVERLAY_DEPTH_MASK) { 438 case I915_OVERLAY_YUV422: 439 cmd |= OCMD_YUV_422_PACKED; 440 break; 441 case I915_OVERLAY_YUV411: 442 cmd |= OCMD_YUV_411_PACKED; 443 break; 444 } 445 446 switch (params->flags & I915_OVERLAY_SWAP_MASK) { 447 case I915_OVERLAY_NO_SWAP: 448 break; 449 case I915_OVERLAY_UV_SWAP: 450 cmd |= OCMD_UV_SWAP; 451 break; 452 case I915_OVERLAY_Y_SWAP: 453 cmd |= OCMD_Y_SWAP; 454 break; 455 case I915_OVERLAY_Y_AND_UV_SWAP: 456 cmd |= OCMD_Y_AND_UV_SWAP; 457 break; 458 } 459 } 460 461 return cmd; 462 } 463 464 static int intel_overlay_do_put_image(struct intel_overlay *overlay, 465 struct drm_gem_object *obj, 466 struct drm_intel_overlay_put_image *params) 467 { 468 struct intel_display *display = overlay->display; 469 struct overlay_registers __iomem *regs = overlay->regs; 470 u32 swidth, swidthsw, sheight, ostride; 471 enum pipe pipe = overlay->crtc->pipe; 472 bool scale_changed = false; 473 struct i915_vma *vma; 474 int ret, tmp_width; 475 u32 tmp, offset; 476 477 drm_WARN_ON(display->drm, 478 !drm_modeset_is_locked(&display->drm->mode_config.connection_mutex)); 479 480 ret = intel_parent_overlay_release_old_vid(display); 481 if (ret != 0) 482 return ret; 483 484 vma = intel_parent_overlay_pin_fb(display, obj, &offset); 485 if (IS_ERR(vma)) 486 return PTR_ERR(vma); 487 488 if (!intel_parent_overlay_is_active(display)) { 489 const struct intel_crtc_state *crtc_state = 490 overlay->crtc->config; 491 u32 oconfig = 0; 492 493 if (crtc_state->gamma_enable && 494 crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT) 495 oconfig |= OCONF_CC_OUT_8BIT; 496 if (crtc_state->gamma_enable) 497 oconfig |= OCONF_GAMMA2_ENABLE; 498 if (DISPLAY_VER(display) == 4) 499 oconfig |= OCONF_CSC_MODE_BT709; 500 oconfig |= pipe == 0 ? 501 OCONF_PIPE_A : OCONF_PIPE_B; 502 iowrite32(oconfig, ®s->OCONFIG); 503 504 ret = intel_parent_overlay_on(display, INTEL_FRONTBUFFER_OVERLAY(pipe)); 505 if (ret != 0) 506 goto out_unpin; 507 } 508 509 iowrite32(params->dst_y << 16 | params->dst_x, ®s->DWINPOS); 510 iowrite32(params->dst_height << 16 | params->dst_width, ®s->DWINSZ); 511 512 if (params->flags & I915_OVERLAY_YUV_PACKED) 513 tmp_width = packed_width_bytes(params->flags, 514 params->src_width); 515 else 516 tmp_width = params->src_width; 517 518 swidth = params->src_width; 519 swidthsw = calc_swidthsw(display, params->offset_Y, tmp_width); 520 sheight = params->src_height; 521 iowrite32(offset + params->offset_Y, ®s->OBUF_0Y); 522 ostride = params->stride_Y; 523 524 if (params->flags & I915_OVERLAY_YUV_PLANAR) { 525 int uv_hscale = uv_hsubsampling(params->flags); 526 int uv_vscale = uv_vsubsampling(params->flags); 527 u32 tmp_U, tmp_V; 528 529 swidth |= (params->src_width / uv_hscale) << 16; 530 sheight |= (params->src_height / uv_vscale) << 16; 531 532 tmp_U = calc_swidthsw(display, params->offset_U, 533 params->src_width / uv_hscale); 534 tmp_V = calc_swidthsw(display, params->offset_V, 535 params->src_width / uv_hscale); 536 swidthsw |= max(tmp_U, tmp_V) << 16; 537 538 iowrite32(offset + params->offset_U, 539 ®s->OBUF_0U); 540 iowrite32(offset + params->offset_V, 541 ®s->OBUF_0V); 542 543 ostride |= params->stride_UV << 16; 544 } 545 546 iowrite32(swidth, ®s->SWIDTH); 547 iowrite32(swidthsw, ®s->SWIDTHSW); 548 iowrite32(sheight, ®s->SHEIGHT); 549 iowrite32(ostride, ®s->OSTRIDE); 550 551 scale_changed = update_scaling_factors(overlay, regs, params); 552 553 update_colorkey(overlay, regs); 554 555 iowrite32(overlay_cmd_reg(params), ®s->OCMD); 556 557 /* check for underruns */ 558 tmp = intel_de_read(display, DOVSTA); 559 if (tmp & (1 << 17)) 560 drm_dbg(display->drm, "overlay underrun, DOVSTA: %x\n", tmp); 561 562 ret = intel_parent_overlay_continue(display, vma, scale_changed); 563 if (ret) 564 goto out_unpin; 565 566 return 0; 567 568 out_unpin: 569 intel_parent_overlay_unpin_fb(display, vma); 570 571 return ret; 572 } 573 574 int intel_overlay_switch_off(struct intel_overlay *overlay) 575 { 576 struct intel_display *display = overlay->display; 577 int ret; 578 579 drm_WARN_ON(display->drm, 580 !drm_modeset_is_locked(&display->drm->mode_config.connection_mutex)); 581 582 ret = intel_parent_overlay_recover_from_interrupt(display); 583 if (ret != 0) 584 return ret; 585 586 if (!intel_parent_overlay_is_active(display)) 587 return 0; 588 589 ret = intel_parent_overlay_release_old_vid(display); 590 if (ret != 0) 591 return ret; 592 593 iowrite32(0, &overlay->regs->OCMD); 594 595 overlay->crtc->overlay = NULL; 596 overlay->crtc = NULL; 597 598 return intel_parent_overlay_off(display); 599 } 600 601 static int check_overlay_possible_on_crtc(struct intel_overlay *overlay, 602 struct intel_crtc *crtc) 603 { 604 if (!crtc->active) 605 return -EINVAL; 606 607 /* can't use the overlay with double wide pipe */ 608 if (crtc->config->double_wide) 609 return -EINVAL; 610 611 return 0; 612 } 613 614 static void update_pfit_vscale_ratio(struct intel_overlay *overlay) 615 { 616 struct intel_display *display = overlay->display; 617 u32 ratio; 618 619 /* XXX: This is not the same logic as in the xorg driver, but more in 620 * line with the intel documentation for the i965 621 */ 622 if (DISPLAY_VER(display) >= 4) { 623 u32 tmp = intel_de_read(display, PFIT_PGM_RATIOS(display)); 624 625 /* on i965 use the PGM reg to read out the autoscaler values */ 626 ratio = REG_FIELD_GET(PFIT_VERT_SCALE_MASK_965, tmp); 627 } else { 628 u32 tmp; 629 630 if (intel_de_read(display, PFIT_CONTROL(display)) & PFIT_VERT_AUTO_SCALE) 631 tmp = intel_de_read(display, PFIT_AUTO_RATIOS(display)); 632 else 633 tmp = intel_de_read(display, PFIT_PGM_RATIOS(display)); 634 635 ratio = REG_FIELD_GET(PFIT_VERT_SCALE_MASK, tmp); 636 } 637 638 overlay->pfit_vscale_ratio = ratio; 639 } 640 641 static int check_overlay_dst(struct intel_overlay *overlay, 642 struct drm_intel_overlay_put_image *rec) 643 { 644 const struct intel_crtc_state *crtc_state = 645 overlay->crtc->config; 646 struct drm_rect req, clipped; 647 648 drm_rect_init(&req, rec->dst_x, rec->dst_y, 649 rec->dst_width, rec->dst_height); 650 651 clipped = req; 652 653 if (!drm_rect_intersect(&clipped, &crtc_state->pipe_src)) 654 return -EINVAL; 655 656 if (!drm_rect_equals(&clipped, &req)) 657 return -EINVAL; 658 659 return 0; 660 } 661 662 static int check_overlay_scaling(struct drm_intel_overlay_put_image *rec) 663 { 664 u32 tmp; 665 666 /* downscaling limit is 8.0 */ 667 tmp = ((rec->src_scan_height << 16) / rec->dst_height) >> 16; 668 if (tmp > 7) 669 return -EINVAL; 670 671 tmp = ((rec->src_scan_width << 16) / rec->dst_width) >> 16; 672 if (tmp > 7) 673 return -EINVAL; 674 675 return 0; 676 } 677 678 static int check_overlay_src(struct intel_display *display, 679 struct drm_intel_overlay_put_image *rec, 680 struct drm_gem_object *obj) 681 { 682 int uv_hscale = uv_hsubsampling(rec->flags); 683 int uv_vscale = uv_vsubsampling(rec->flags); 684 u32 stride_mask; 685 int depth; 686 u32 tmp; 687 688 /* check src dimensions */ 689 if (display->platform.i845g || display->platform.i830) { 690 if (rec->src_height > IMAGE_MAX_HEIGHT_LEGACY || 691 rec->src_width > IMAGE_MAX_WIDTH_LEGACY) 692 return -EINVAL; 693 } else { 694 if (rec->src_height > IMAGE_MAX_HEIGHT || 695 rec->src_width > IMAGE_MAX_WIDTH) 696 return -EINVAL; 697 } 698 699 /* better safe than sorry, use 4 as the maximal subsampling ratio */ 700 if (rec->src_height < N_VERT_Y_TAPS*4 || 701 rec->src_width < N_HORIZ_Y_TAPS*4) 702 return -EINVAL; 703 704 /* check alignment constraints */ 705 switch (rec->flags & I915_OVERLAY_TYPE_MASK) { 706 case I915_OVERLAY_RGB: 707 /* not implemented */ 708 return -EINVAL; 709 710 case I915_OVERLAY_YUV_PACKED: 711 if (uv_vscale != 1) 712 return -EINVAL; 713 714 depth = packed_depth_bytes(rec->flags); 715 if (depth < 0) 716 return depth; 717 718 /* ignore UV planes */ 719 rec->stride_UV = 0; 720 rec->offset_U = 0; 721 rec->offset_V = 0; 722 /* check pixel alignment */ 723 if (rec->offset_Y % depth) 724 return -EINVAL; 725 break; 726 727 case I915_OVERLAY_YUV_PLANAR: 728 if (uv_vscale < 0 || uv_hscale < 0) 729 return -EINVAL; 730 /* no offset restrictions for planar formats */ 731 break; 732 733 default: 734 return -EINVAL; 735 } 736 737 if (rec->src_width % uv_hscale) 738 return -EINVAL; 739 740 /* stride checking */ 741 if (display->platform.i830 || display->platform.i845g) 742 stride_mask = 255; 743 else 744 stride_mask = 63; 745 746 if (rec->stride_Y & stride_mask || rec->stride_UV & stride_mask) 747 return -EINVAL; 748 if (DISPLAY_VER(display) == 4 && rec->stride_Y < 512) 749 return -EINVAL; 750 751 tmp = (rec->flags & I915_OVERLAY_TYPE_MASK) == I915_OVERLAY_YUV_PLANAR ? 752 4096 : 8192; 753 if (rec->stride_Y > tmp || rec->stride_UV > 2*1024) 754 return -EINVAL; 755 756 /* check buffer dimensions */ 757 switch (rec->flags & I915_OVERLAY_TYPE_MASK) { 758 case I915_OVERLAY_RGB: 759 case I915_OVERLAY_YUV_PACKED: 760 /* always 4 Y values per depth pixels */ 761 if (packed_width_bytes(rec->flags, rec->src_width) > rec->stride_Y) 762 return -EINVAL; 763 764 tmp = rec->stride_Y*rec->src_height; 765 if (rec->offset_Y + tmp > obj->size) 766 return -EINVAL; 767 break; 768 769 case I915_OVERLAY_YUV_PLANAR: 770 if (rec->src_width > rec->stride_Y) 771 return -EINVAL; 772 if (rec->src_width/uv_hscale > rec->stride_UV) 773 return -EINVAL; 774 775 tmp = rec->stride_Y * rec->src_height; 776 if (rec->offset_Y + tmp > obj->size) 777 return -EINVAL; 778 779 tmp = rec->stride_UV * (rec->src_height / uv_vscale); 780 if (rec->offset_U + tmp > obj->size || 781 rec->offset_V + tmp > obj->size) 782 return -EINVAL; 783 break; 784 } 785 786 return 0; 787 } 788 789 int intel_overlay_put_image_ioctl(struct drm_device *dev, void *data, 790 struct drm_file *file_priv) 791 { 792 struct intel_display *display = to_intel_display(dev); 793 struct drm_intel_overlay_put_image *params = data; 794 struct intel_overlay *overlay; 795 struct drm_crtc *drmmode_crtc; 796 struct drm_gem_object *obj; 797 struct intel_crtc *crtc; 798 int ret; 799 800 overlay = display->overlay; 801 if (!overlay) { 802 drm_dbg(display->drm, "userspace bug: no overlay\n"); 803 return -ENODEV; 804 } 805 806 if (!(params->flags & I915_OVERLAY_ENABLE)) { 807 drm_modeset_lock_all(dev); 808 ret = intel_overlay_switch_off(overlay); 809 drm_modeset_unlock_all(dev); 810 811 return ret; 812 } 813 814 drmmode_crtc = drm_crtc_find(dev, file_priv, params->crtc_id); 815 if (!drmmode_crtc) 816 return -ENOENT; 817 crtc = to_intel_crtc(drmmode_crtc); 818 819 obj = intel_parent_overlay_obj_lookup(display, file_priv, params->bo_handle); 820 if (IS_ERR(obj)) 821 return PTR_ERR(obj); 822 823 drm_modeset_lock_all(dev); 824 825 ret = intel_parent_overlay_recover_from_interrupt(display); 826 if (ret != 0) 827 goto out_unlock; 828 829 if (overlay->crtc != crtc) { 830 ret = intel_overlay_switch_off(overlay); 831 if (ret != 0) 832 goto out_unlock; 833 834 ret = check_overlay_possible_on_crtc(overlay, crtc); 835 if (ret != 0) 836 goto out_unlock; 837 838 overlay->crtc = crtc; 839 crtc->overlay = overlay; 840 841 /* line too wide, i.e. one-line-mode */ 842 if (drm_rect_width(&crtc->config->pipe_src) > 1024 && 843 crtc->config->gmch_pfit.control & PFIT_ENABLE) { 844 overlay->pfit_active = true; 845 update_pfit_vscale_ratio(overlay); 846 } else 847 overlay->pfit_active = false; 848 } 849 850 ret = check_overlay_dst(overlay, params); 851 if (ret != 0) 852 goto out_unlock; 853 854 if (overlay->pfit_active) { 855 params->dst_y = (((u32)params->dst_y << 12) / 856 overlay->pfit_vscale_ratio); 857 /* shifting right rounds downwards, so add 1 */ 858 params->dst_height = (((u32)params->dst_height << 12) / 859 overlay->pfit_vscale_ratio) + 1; 860 } 861 862 if (params->src_scan_height > params->src_height || 863 params->src_scan_width > params->src_width) { 864 ret = -EINVAL; 865 goto out_unlock; 866 } 867 868 ret = check_overlay_src(display, params, obj); 869 if (ret != 0) 870 goto out_unlock; 871 872 /* Check scaling after src size to prevent a divide-by-zero. */ 873 ret = check_overlay_scaling(params); 874 if (ret != 0) 875 goto out_unlock; 876 877 ret = intel_overlay_do_put_image(overlay, obj, params); 878 if (ret != 0) 879 goto out_unlock; 880 881 drm_modeset_unlock_all(dev); 882 drm_gem_object_put(obj); 883 884 return 0; 885 886 out_unlock: 887 drm_modeset_unlock_all(dev); 888 drm_gem_object_put(obj); 889 890 return ret; 891 } 892 893 static void update_reg_attrs(struct intel_overlay *overlay, 894 struct overlay_registers __iomem *regs) 895 { 896 iowrite32((overlay->contrast << 18) | (overlay->brightness & 0xff), 897 ®s->OCLRC0); 898 iowrite32(overlay->saturation, ®s->OCLRC1); 899 } 900 901 static bool check_gamma_bounds(u32 gamma1, u32 gamma2) 902 { 903 int i; 904 905 if (gamma1 & 0xff000000 || gamma2 & 0xff000000) 906 return false; 907 908 for (i = 0; i < 3; i++) { 909 if (((gamma1 >> i*8) & 0xff) >= ((gamma2 >> i*8) & 0xff)) 910 return false; 911 } 912 913 return true; 914 } 915 916 static bool check_gamma5_errata(u32 gamma5) 917 { 918 int i; 919 920 for (i = 0; i < 3; i++) { 921 if (((gamma5 >> i*8) & 0xff) == 0x80) 922 return false; 923 } 924 925 return true; 926 } 927 928 static int check_gamma(struct drm_intel_overlay_attrs *attrs) 929 { 930 if (!check_gamma_bounds(0, attrs->gamma0) || 931 !check_gamma_bounds(attrs->gamma0, attrs->gamma1) || 932 !check_gamma_bounds(attrs->gamma1, attrs->gamma2) || 933 !check_gamma_bounds(attrs->gamma2, attrs->gamma3) || 934 !check_gamma_bounds(attrs->gamma3, attrs->gamma4) || 935 !check_gamma_bounds(attrs->gamma4, attrs->gamma5) || 936 !check_gamma_bounds(attrs->gamma5, 0x00ffffff)) 937 return -EINVAL; 938 939 if (!check_gamma5_errata(attrs->gamma5)) 940 return -EINVAL; 941 942 return 0; 943 } 944 945 int intel_overlay_attrs_ioctl(struct drm_device *dev, void *data, 946 struct drm_file *file_priv) 947 { 948 struct intel_display *display = to_intel_display(dev); 949 struct drm_intel_overlay_attrs *attrs = data; 950 struct intel_overlay *overlay; 951 int ret; 952 953 overlay = display->overlay; 954 if (!overlay) { 955 drm_dbg(display->drm, "userspace bug: no overlay\n"); 956 return -ENODEV; 957 } 958 959 drm_modeset_lock_all(dev); 960 961 ret = -EINVAL; 962 if (!(attrs->flags & I915_OVERLAY_UPDATE_ATTRS)) { 963 attrs->color_key = overlay->color_key; 964 attrs->brightness = overlay->brightness; 965 attrs->contrast = overlay->contrast; 966 attrs->saturation = overlay->saturation; 967 968 if (DISPLAY_VER(display) != 2) { 969 attrs->gamma0 = intel_de_read(display, OGAMC0); 970 attrs->gamma1 = intel_de_read(display, OGAMC1); 971 attrs->gamma2 = intel_de_read(display, OGAMC2); 972 attrs->gamma3 = intel_de_read(display, OGAMC3); 973 attrs->gamma4 = intel_de_read(display, OGAMC4); 974 attrs->gamma5 = intel_de_read(display, OGAMC5); 975 } 976 } else { 977 if (attrs->brightness < -128 || attrs->brightness > 127) 978 goto out_unlock; 979 if (attrs->contrast > 255) 980 goto out_unlock; 981 if (attrs->saturation > 1023) 982 goto out_unlock; 983 984 overlay->color_key = attrs->color_key; 985 overlay->brightness = attrs->brightness; 986 overlay->contrast = attrs->contrast; 987 overlay->saturation = attrs->saturation; 988 989 update_reg_attrs(overlay, overlay->regs); 990 991 if (attrs->flags & I915_OVERLAY_UPDATE_GAMMA) { 992 if (DISPLAY_VER(display) == 2) 993 goto out_unlock; 994 995 if (intel_parent_overlay_is_active(display)) { 996 ret = -EBUSY; 997 goto out_unlock; 998 } 999 1000 ret = check_gamma(attrs); 1001 if (ret) 1002 goto out_unlock; 1003 1004 intel_de_write(display, OGAMC0, attrs->gamma0); 1005 intel_de_write(display, OGAMC1, attrs->gamma1); 1006 intel_de_write(display, OGAMC2, attrs->gamma2); 1007 intel_de_write(display, OGAMC3, attrs->gamma3); 1008 intel_de_write(display, OGAMC4, attrs->gamma4); 1009 intel_de_write(display, OGAMC5, attrs->gamma5); 1010 } 1011 } 1012 overlay->color_key_enabled = (attrs->flags & I915_OVERLAY_DISABLE_DEST_COLORKEY) == 0; 1013 1014 ret = 0; 1015 out_unlock: 1016 drm_modeset_unlock_all(dev); 1017 1018 return ret; 1019 } 1020 1021 void intel_overlay_setup(struct intel_display *display) 1022 { 1023 struct intel_overlay *overlay; 1024 void __iomem *regs; 1025 1026 if (!HAS_OVERLAY(display)) 1027 return; 1028 1029 overlay = kzalloc_obj(*overlay); 1030 if (!overlay) 1031 return; 1032 1033 regs = intel_parent_overlay_setup(display, 1034 OVERLAY_NEEDS_PHYSICAL(display)); 1035 if (IS_ERR(regs)) 1036 goto out_free; 1037 1038 overlay->display = display; 1039 overlay->regs = regs; 1040 overlay->color_key = 0x0101fe; 1041 overlay->color_key_enabled = true; 1042 overlay->brightness = -19; 1043 overlay->contrast = 75; 1044 overlay->saturation = 146; 1045 1046 memset_io(overlay->regs, 0, sizeof(struct overlay_registers)); 1047 update_polyphase_filter(overlay->regs); 1048 update_reg_attrs(overlay, overlay->regs); 1049 1050 display->overlay = overlay; 1051 drm_info(display->drm, "Initialized overlay support.\n"); 1052 return; 1053 1054 out_free: 1055 kfree(overlay); 1056 } 1057 1058 bool intel_overlay_available(struct intel_display *display) 1059 { 1060 return display->overlay; 1061 } 1062 1063 void intel_overlay_cleanup(struct intel_display *display) 1064 { 1065 if (!display->overlay) 1066 return; 1067 1068 intel_parent_overlay_cleanup(display); 1069 1070 kfree(display->overlay); 1071 display->overlay = NULL; 1072 } 1073