1 /* 2 * Copyright © 2009 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 * SOFTWARE. 22 * 23 * Authors: 24 * Daniel Vetter <daniel@ffwll.ch> 25 * 26 * Derived from Xorg ddx, xf86-video-intel, src/i830_video.c 27 */ 28 29 #include <drm/drm_fourcc.h> 30 #include <drm/i915_drm.h> 31 32 #include "gem/i915_gem_pm.h" 33 #include "gt/intel_ring.h" 34 35 #include "i915_drv.h" 36 #include "i915_reg.h" 37 #include "intel_display_types.h" 38 #include "intel_frontbuffer.h" 39 #include "intel_overlay.h" 40 41 /* Limits for overlay size. According to intel doc, the real limits are: 42 * Y width: 4095, UV width (planar): 2047, Y height: 2047, 43 * UV width (planar): * 1023. But the xorg thinks 2048 for height and width. Use 44 * the mininum of both. */ 45 #define IMAGE_MAX_WIDTH 2048 46 #define IMAGE_MAX_HEIGHT 2046 /* 2 * 1023 */ 47 /* on 830 and 845 these large limits result in the card hanging */ 48 #define IMAGE_MAX_WIDTH_LEGACY 1024 49 #define IMAGE_MAX_HEIGHT_LEGACY 1088 50 51 /* overlay register definitions */ 52 /* OCMD register */ 53 #define OCMD_TILED_SURFACE (0x1<<19) 54 #define OCMD_MIRROR_MASK (0x3<<17) 55 #define OCMD_MIRROR_MODE (0x3<<17) 56 #define OCMD_MIRROR_HORIZONTAL (0x1<<17) 57 #define OCMD_MIRROR_VERTICAL (0x2<<17) 58 #define OCMD_MIRROR_BOTH (0x3<<17) 59 #define OCMD_BYTEORDER_MASK (0x3<<14) /* zero for YUYV or FOURCC YUY2 */ 60 #define OCMD_UV_SWAP (0x1<<14) /* YVYU */ 61 #define OCMD_Y_SWAP (0x2<<14) /* UYVY or FOURCC UYVY */ 62 #define OCMD_Y_AND_UV_SWAP (0x3<<14) /* VYUY */ 63 #define OCMD_SOURCE_FORMAT_MASK (0xf<<10) 64 #define OCMD_RGB_888 (0x1<<10) /* not in i965 Intel docs */ 65 #define OCMD_RGB_555 (0x2<<10) /* not in i965 Intel docs */ 66 #define OCMD_RGB_565 (0x3<<10) /* not in i965 Intel docs */ 67 #define OCMD_YUV_422_PACKED (0x8<<10) 68 #define OCMD_YUV_411_PACKED (0x9<<10) /* not in i965 Intel docs */ 69 #define OCMD_YUV_420_PLANAR (0xc<<10) 70 #define OCMD_YUV_422_PLANAR (0xd<<10) 71 #define OCMD_YUV_410_PLANAR (0xe<<10) /* also 411 */ 72 #define OCMD_TVSYNCFLIP_PARITY (0x1<<9) 73 #define OCMD_TVSYNCFLIP_ENABLE (0x1<<7) 74 #define OCMD_BUF_TYPE_MASK (0x1<<5) 75 #define OCMD_BUF_TYPE_FRAME (0x0<<5) 76 #define OCMD_BUF_TYPE_FIELD (0x1<<5) 77 #define OCMD_TEST_MODE (0x1<<4) 78 #define OCMD_BUFFER_SELECT (0x3<<2) 79 #define OCMD_BUFFER0 (0x0<<2) 80 #define OCMD_BUFFER1 (0x1<<2) 81 #define OCMD_FIELD_SELECT (0x1<<2) 82 #define OCMD_FIELD0 (0x0<<1) 83 #define OCMD_FIELD1 (0x1<<1) 84 #define OCMD_ENABLE (0x1<<0) 85 86 /* OCONFIG register */ 87 #define OCONF_PIPE_MASK (0x1<<18) 88 #define OCONF_PIPE_A (0x0<<18) 89 #define OCONF_PIPE_B (0x1<<18) 90 #define OCONF_GAMMA2_ENABLE (0x1<<16) 91 #define OCONF_CSC_MODE_BT601 (0x0<<5) 92 #define OCONF_CSC_MODE_BT709 (0x1<<5) 93 #define OCONF_CSC_BYPASS (0x1<<4) 94 #define OCONF_CC_OUT_8BIT (0x1<<3) 95 #define OCONF_TEST_MODE (0x1<<2) 96 #define OCONF_THREE_LINE_BUFFER (0x1<<0) 97 #define OCONF_TWO_LINE_BUFFER (0x0<<0) 98 99 /* DCLRKM (dst-key) register */ 100 #define DST_KEY_ENABLE (0x1<<31) 101 #define CLK_RGB24_MASK 0x0 102 #define CLK_RGB16_MASK 0x070307 103 #define CLK_RGB15_MASK 0x070707 104 #define CLK_RGB8I_MASK 0xffffff 105 106 #define RGB16_TO_COLORKEY(c) \ 107 (((c & 0xF800) << 8) | ((c & 0x07E0) << 5) | ((c & 0x001F) << 3)) 108 #define RGB15_TO_COLORKEY(c) \ 109 (((c & 0x7c00) << 9) | ((c & 0x03E0) << 6) | ((c & 0x001F) << 3)) 110 111 /* overlay flip addr flag */ 112 #define OFC_UPDATE 0x1 113 114 /* polyphase filter coefficients */ 115 #define N_HORIZ_Y_TAPS 5 116 #define N_VERT_Y_TAPS 3 117 #define N_HORIZ_UV_TAPS 3 118 #define N_VERT_UV_TAPS 3 119 #define N_PHASES 17 120 #define MAX_TAPS 5 121 122 /* memory bufferd overlay registers */ 123 struct overlay_registers { 124 u32 OBUF_0Y; 125 u32 OBUF_1Y; 126 u32 OBUF_0U; 127 u32 OBUF_0V; 128 u32 OBUF_1U; 129 u32 OBUF_1V; 130 u32 OSTRIDE; 131 u32 YRGB_VPH; 132 u32 UV_VPH; 133 u32 HORZ_PH; 134 u32 INIT_PHS; 135 u32 DWINPOS; 136 u32 DWINSZ; 137 u32 SWIDTH; 138 u32 SWIDTHSW; 139 u32 SHEIGHT; 140 u32 YRGBSCALE; 141 u32 UVSCALE; 142 u32 OCLRC0; 143 u32 OCLRC1; 144 u32 DCLRKV; 145 u32 DCLRKM; 146 u32 SCLRKVH; 147 u32 SCLRKVL; 148 u32 SCLRKEN; 149 u32 OCONFIG; 150 u32 OCMD; 151 u32 RESERVED1; /* 0x6C */ 152 u32 OSTART_0Y; 153 u32 OSTART_1Y; 154 u32 OSTART_0U; 155 u32 OSTART_0V; 156 u32 OSTART_1U; 157 u32 OSTART_1V; 158 u32 OTILEOFF_0Y; 159 u32 OTILEOFF_1Y; 160 u32 OTILEOFF_0U; 161 u32 OTILEOFF_0V; 162 u32 OTILEOFF_1U; 163 u32 OTILEOFF_1V; 164 u32 FASTHSCALE; /* 0xA0 */ 165 u32 UVSCALEV; /* 0xA4 */ 166 u32 RESERVEDC[(0x200 - 0xA8) / 4]; /* 0xA8 - 0x1FC */ 167 u16 Y_VCOEFS[N_VERT_Y_TAPS * N_PHASES]; /* 0x200 */ 168 u16 RESERVEDD[0x100 / 2 - N_VERT_Y_TAPS * N_PHASES]; 169 u16 Y_HCOEFS[N_HORIZ_Y_TAPS * N_PHASES]; /* 0x300 */ 170 u16 RESERVEDE[0x200 / 2 - N_HORIZ_Y_TAPS * N_PHASES]; 171 u16 UV_VCOEFS[N_VERT_UV_TAPS * N_PHASES]; /* 0x500 */ 172 u16 RESERVEDF[0x100 / 2 - N_VERT_UV_TAPS * N_PHASES]; 173 u16 UV_HCOEFS[N_HORIZ_UV_TAPS * N_PHASES]; /* 0x600 */ 174 u16 RESERVEDG[0x100 / 2 - N_HORIZ_UV_TAPS * N_PHASES]; 175 }; 176 177 struct intel_overlay { 178 struct drm_i915_private *i915; 179 struct intel_context *context; 180 struct intel_crtc *crtc; 181 struct i915_vma *vma; 182 struct i915_vma *old_vma; 183 bool active; 184 bool pfit_active; 185 u32 pfit_vscale_ratio; /* shifted-point number, (1<<12) == 1.0 */ 186 u32 color_key:24; 187 u32 color_key_enabled:1; 188 u32 brightness, contrast, saturation; 189 u32 old_xscale, old_yscale; 190 /* register access */ 191 struct drm_i915_gem_object *reg_bo; 192 struct overlay_registers __iomem *regs; 193 u32 flip_addr; 194 /* flip handling */ 195 struct i915_active last_flip; 196 void (*flip_complete)(struct intel_overlay *ovl); 197 }; 198 199 static void i830_overlay_clock_gating(struct drm_i915_private *dev_priv, 200 bool enable) 201 { 202 struct pci_dev *pdev = dev_priv->drm.pdev; 203 u8 val; 204 205 /* WA_OVERLAY_CLKGATE:alm */ 206 if (enable) 207 I915_WRITE(DSPCLK_GATE_D, 0); 208 else 209 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE); 210 211 /* WA_DISABLE_L2CACHE_CLOCK_GATING:alm */ 212 pci_bus_read_config_byte(pdev->bus, 213 PCI_DEVFN(0, 0), I830_CLOCK_GATE, &val); 214 if (enable) 215 val &= ~I830_L2_CACHE_CLOCK_GATE_DISABLE; 216 else 217 val |= I830_L2_CACHE_CLOCK_GATE_DISABLE; 218 pci_bus_write_config_byte(pdev->bus, 219 PCI_DEVFN(0, 0), I830_CLOCK_GATE, val); 220 } 221 222 static struct i915_request * 223 alloc_request(struct intel_overlay *overlay, void (*fn)(struct intel_overlay *)) 224 { 225 struct i915_request *rq; 226 int err; 227 228 overlay->flip_complete = fn; 229 230 rq = i915_request_create(overlay->context); 231 if (IS_ERR(rq)) 232 return rq; 233 234 err = i915_active_add_request(&overlay->last_flip, rq); 235 if (err) { 236 i915_request_add(rq); 237 return ERR_PTR(err); 238 } 239 240 return rq; 241 } 242 243 /* overlay needs to be disable in OCMD reg */ 244 static int intel_overlay_on(struct intel_overlay *overlay) 245 { 246 struct drm_i915_private *dev_priv = overlay->i915; 247 struct i915_request *rq; 248 u32 *cs; 249 250 WARN_ON(overlay->active); 251 252 rq = alloc_request(overlay, NULL); 253 if (IS_ERR(rq)) 254 return PTR_ERR(rq); 255 256 cs = intel_ring_begin(rq, 4); 257 if (IS_ERR(cs)) { 258 i915_request_add(rq); 259 return PTR_ERR(cs); 260 } 261 262 overlay->active = true; 263 264 if (IS_I830(dev_priv)) 265 i830_overlay_clock_gating(dev_priv, false); 266 267 *cs++ = MI_OVERLAY_FLIP | MI_OVERLAY_ON; 268 *cs++ = overlay->flip_addr | OFC_UPDATE; 269 *cs++ = MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP; 270 *cs++ = MI_NOOP; 271 intel_ring_advance(rq, cs); 272 273 i915_request_add(rq); 274 275 return i915_active_wait(&overlay->last_flip); 276 } 277 278 static void intel_overlay_flip_prepare(struct intel_overlay *overlay, 279 struct i915_vma *vma) 280 { 281 enum pipe pipe = overlay->crtc->pipe; 282 283 WARN_ON(overlay->old_vma); 284 285 intel_frontbuffer_track(overlay->vma ? overlay->vma->obj->frontbuffer : NULL, 286 vma ? vma->obj->frontbuffer : NULL, 287 INTEL_FRONTBUFFER_OVERLAY(pipe)); 288 289 intel_frontbuffer_flip_prepare(overlay->i915, 290 INTEL_FRONTBUFFER_OVERLAY(pipe)); 291 292 overlay->old_vma = overlay->vma; 293 if (vma) 294 overlay->vma = i915_vma_get(vma); 295 else 296 overlay->vma = NULL; 297 } 298 299 /* overlay needs to be enabled in OCMD reg */ 300 static int intel_overlay_continue(struct intel_overlay *overlay, 301 struct i915_vma *vma, 302 bool load_polyphase_filter) 303 { 304 struct drm_i915_private *dev_priv = overlay->i915; 305 struct i915_request *rq; 306 u32 flip_addr = overlay->flip_addr; 307 u32 tmp, *cs; 308 309 WARN_ON(!overlay->active); 310 311 if (load_polyphase_filter) 312 flip_addr |= OFC_UPDATE; 313 314 /* check for underruns */ 315 tmp = I915_READ(DOVSTA); 316 if (tmp & (1 << 17)) 317 DRM_DEBUG("overlay underrun, DOVSTA: %x\n", tmp); 318 319 rq = alloc_request(overlay, NULL); 320 if (IS_ERR(rq)) 321 return PTR_ERR(rq); 322 323 cs = intel_ring_begin(rq, 2); 324 if (IS_ERR(cs)) { 325 i915_request_add(rq); 326 return PTR_ERR(cs); 327 } 328 329 *cs++ = MI_OVERLAY_FLIP | MI_OVERLAY_CONTINUE; 330 *cs++ = flip_addr; 331 intel_ring_advance(rq, cs); 332 333 intel_overlay_flip_prepare(overlay, vma); 334 i915_request_add(rq); 335 336 return 0; 337 } 338 339 static void intel_overlay_release_old_vma(struct intel_overlay *overlay) 340 { 341 struct i915_vma *vma; 342 343 vma = fetch_and_zero(&overlay->old_vma); 344 if (WARN_ON(!vma)) 345 return; 346 347 intel_frontbuffer_flip_complete(overlay->i915, 348 INTEL_FRONTBUFFER_OVERLAY(overlay->crtc->pipe)); 349 350 i915_gem_object_unpin_from_display_plane(vma); 351 i915_vma_put(vma); 352 } 353 354 static void 355 intel_overlay_release_old_vid_tail(struct intel_overlay *overlay) 356 { 357 intel_overlay_release_old_vma(overlay); 358 } 359 360 static void intel_overlay_off_tail(struct intel_overlay *overlay) 361 { 362 struct drm_i915_private *dev_priv = overlay->i915; 363 364 intel_overlay_release_old_vma(overlay); 365 366 overlay->crtc->overlay = NULL; 367 overlay->crtc = NULL; 368 overlay->active = false; 369 370 if (IS_I830(dev_priv)) 371 i830_overlay_clock_gating(dev_priv, true); 372 } 373 374 static void 375 intel_overlay_last_flip_retire(struct i915_active *active) 376 { 377 struct intel_overlay *overlay = 378 container_of(active, typeof(*overlay), last_flip); 379 380 if (overlay->flip_complete) 381 overlay->flip_complete(overlay); 382 } 383 384 /* overlay needs to be disabled in OCMD reg */ 385 static int intel_overlay_off(struct intel_overlay *overlay) 386 { 387 struct i915_request *rq; 388 u32 *cs, flip_addr = overlay->flip_addr; 389 390 WARN_ON(!overlay->active); 391 392 /* According to intel docs the overlay hw may hang (when switching 393 * off) without loading the filter coeffs. It is however unclear whether 394 * this applies to the disabling of the overlay or to the switching off 395 * of the hw. Do it in both cases */ 396 flip_addr |= OFC_UPDATE; 397 398 rq = alloc_request(overlay, intel_overlay_off_tail); 399 if (IS_ERR(rq)) 400 return PTR_ERR(rq); 401 402 cs = intel_ring_begin(rq, 6); 403 if (IS_ERR(cs)) { 404 i915_request_add(rq); 405 return PTR_ERR(cs); 406 } 407 408 /* wait for overlay to go idle */ 409 *cs++ = MI_OVERLAY_FLIP | MI_OVERLAY_CONTINUE; 410 *cs++ = flip_addr; 411 *cs++ = MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP; 412 413 /* turn overlay off */ 414 *cs++ = MI_OVERLAY_FLIP | MI_OVERLAY_OFF; 415 *cs++ = flip_addr; 416 *cs++ = MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP; 417 418 intel_ring_advance(rq, cs); 419 420 intel_overlay_flip_prepare(overlay, NULL); 421 i915_request_add(rq); 422 423 return i915_active_wait(&overlay->last_flip); 424 } 425 426 /* recover from an interruption due to a signal 427 * We have to be careful not to repeat work forever an make forward progess. */ 428 static int intel_overlay_recover_from_interrupt(struct intel_overlay *overlay) 429 { 430 return i915_active_wait(&overlay->last_flip); 431 } 432 433 /* Wait for pending overlay flip and release old frame. 434 * Needs to be called before the overlay register are changed 435 * via intel_overlay_(un)map_regs 436 */ 437 static int intel_overlay_release_old_vid(struct intel_overlay *overlay) 438 { 439 struct drm_i915_private *dev_priv = overlay->i915; 440 struct i915_request *rq; 441 u32 *cs; 442 443 /* 444 * Only wait if there is actually an old frame to release to 445 * guarantee forward progress. 446 */ 447 if (!overlay->old_vma) 448 return 0; 449 450 if (!(I915_READ(GEN2_ISR) & I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT)) { 451 intel_overlay_release_old_vid_tail(overlay); 452 return 0; 453 } 454 455 rq = alloc_request(overlay, intel_overlay_release_old_vid_tail); 456 if (IS_ERR(rq)) 457 return PTR_ERR(rq); 458 459 cs = intel_ring_begin(rq, 2); 460 if (IS_ERR(cs)) { 461 i915_request_add(rq); 462 return PTR_ERR(cs); 463 } 464 465 *cs++ = MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP; 466 *cs++ = MI_NOOP; 467 intel_ring_advance(rq, cs); 468 469 i915_request_add(rq); 470 471 return i915_active_wait(&overlay->last_flip); 472 } 473 474 void intel_overlay_reset(struct drm_i915_private *dev_priv) 475 { 476 struct intel_overlay *overlay = dev_priv->overlay; 477 478 if (!overlay) 479 return; 480 481 overlay->old_xscale = 0; 482 overlay->old_yscale = 0; 483 overlay->crtc = NULL; 484 overlay->active = false; 485 } 486 487 static int packed_depth_bytes(u32 format) 488 { 489 switch (format & I915_OVERLAY_DEPTH_MASK) { 490 case I915_OVERLAY_YUV422: 491 return 4; 492 case I915_OVERLAY_YUV411: 493 /* return 6; not implemented */ 494 default: 495 return -EINVAL; 496 } 497 } 498 499 static int packed_width_bytes(u32 format, short width) 500 { 501 switch (format & I915_OVERLAY_DEPTH_MASK) { 502 case I915_OVERLAY_YUV422: 503 return width << 1; 504 default: 505 return -EINVAL; 506 } 507 } 508 509 static int uv_hsubsampling(u32 format) 510 { 511 switch (format & I915_OVERLAY_DEPTH_MASK) { 512 case I915_OVERLAY_YUV422: 513 case I915_OVERLAY_YUV420: 514 return 2; 515 case I915_OVERLAY_YUV411: 516 case I915_OVERLAY_YUV410: 517 return 4; 518 default: 519 return -EINVAL; 520 } 521 } 522 523 static int uv_vsubsampling(u32 format) 524 { 525 switch (format & I915_OVERLAY_DEPTH_MASK) { 526 case I915_OVERLAY_YUV420: 527 case I915_OVERLAY_YUV410: 528 return 2; 529 case I915_OVERLAY_YUV422: 530 case I915_OVERLAY_YUV411: 531 return 1; 532 default: 533 return -EINVAL; 534 } 535 } 536 537 static u32 calc_swidthsw(struct drm_i915_private *dev_priv, u32 offset, u32 width) 538 { 539 u32 sw; 540 541 if (IS_GEN(dev_priv, 2)) 542 sw = ALIGN((offset & 31) + width, 32); 543 else 544 sw = ALIGN((offset & 63) + width, 64); 545 546 if (sw == 0) 547 return 0; 548 549 return (sw - 32) >> 3; 550 } 551 552 static const u16 y_static_hcoeffs[N_PHASES][N_HORIZ_Y_TAPS] = { 553 [ 0] = { 0x3000, 0xb4a0, 0x1930, 0x1920, 0xb4a0, }, 554 [ 1] = { 0x3000, 0xb500, 0x19d0, 0x1880, 0xb440, }, 555 [ 2] = { 0x3000, 0xb540, 0x1a88, 0x2f80, 0xb3e0, }, 556 [ 3] = { 0x3000, 0xb580, 0x1b30, 0x2e20, 0xb380, }, 557 [ 4] = { 0x3000, 0xb5c0, 0x1bd8, 0x2cc0, 0xb320, }, 558 [ 5] = { 0x3020, 0xb5e0, 0x1c60, 0x2b80, 0xb2c0, }, 559 [ 6] = { 0x3020, 0xb5e0, 0x1cf8, 0x2a20, 0xb260, }, 560 [ 7] = { 0x3020, 0xb5e0, 0x1d80, 0x28e0, 0xb200, }, 561 [ 8] = { 0x3020, 0xb5c0, 0x1e08, 0x3f40, 0xb1c0, }, 562 [ 9] = { 0x3020, 0xb580, 0x1e78, 0x3ce0, 0xb160, }, 563 [10] = { 0x3040, 0xb520, 0x1ed8, 0x3aa0, 0xb120, }, 564 [11] = { 0x3040, 0xb4a0, 0x1f30, 0x3880, 0xb0e0, }, 565 [12] = { 0x3040, 0xb400, 0x1f78, 0x3680, 0xb0a0, }, 566 [13] = { 0x3020, 0xb340, 0x1fb8, 0x34a0, 0xb060, }, 567 [14] = { 0x3020, 0xb240, 0x1fe0, 0x32e0, 0xb040, }, 568 [15] = { 0x3020, 0xb140, 0x1ff8, 0x3160, 0xb020, }, 569 [16] = { 0xb000, 0x3000, 0x0800, 0x3000, 0xb000, }, 570 }; 571 572 static const u16 uv_static_hcoeffs[N_PHASES][N_HORIZ_UV_TAPS] = { 573 [ 0] = { 0x3000, 0x1800, 0x1800, }, 574 [ 1] = { 0xb000, 0x18d0, 0x2e60, }, 575 [ 2] = { 0xb000, 0x1990, 0x2ce0, }, 576 [ 3] = { 0xb020, 0x1a68, 0x2b40, }, 577 [ 4] = { 0xb040, 0x1b20, 0x29e0, }, 578 [ 5] = { 0xb060, 0x1bd8, 0x2880, }, 579 [ 6] = { 0xb080, 0x1c88, 0x3e60, }, 580 [ 7] = { 0xb0a0, 0x1d28, 0x3c00, }, 581 [ 8] = { 0xb0c0, 0x1db8, 0x39e0, }, 582 [ 9] = { 0xb0e0, 0x1e40, 0x37e0, }, 583 [10] = { 0xb100, 0x1eb8, 0x3620, }, 584 [11] = { 0xb100, 0x1f18, 0x34a0, }, 585 [12] = { 0xb100, 0x1f68, 0x3360, }, 586 [13] = { 0xb0e0, 0x1fa8, 0x3240, }, 587 [14] = { 0xb0c0, 0x1fe0, 0x3140, }, 588 [15] = { 0xb060, 0x1ff0, 0x30a0, }, 589 [16] = { 0x3000, 0x0800, 0x3000, }, 590 }; 591 592 static void update_polyphase_filter(struct overlay_registers __iomem *regs) 593 { 594 memcpy_toio(regs->Y_HCOEFS, y_static_hcoeffs, sizeof(y_static_hcoeffs)); 595 memcpy_toio(regs->UV_HCOEFS, uv_static_hcoeffs, 596 sizeof(uv_static_hcoeffs)); 597 } 598 599 static bool update_scaling_factors(struct intel_overlay *overlay, 600 struct overlay_registers __iomem *regs, 601 struct drm_intel_overlay_put_image *params) 602 { 603 /* fixed point with a 12 bit shift */ 604 u32 xscale, yscale, xscale_UV, yscale_UV; 605 #define FP_SHIFT 12 606 #define FRACT_MASK 0xfff 607 bool scale_changed = false; 608 int uv_hscale = uv_hsubsampling(params->flags); 609 int uv_vscale = uv_vsubsampling(params->flags); 610 611 if (params->dst_width > 1) 612 xscale = ((params->src_scan_width - 1) << FP_SHIFT) / 613 params->dst_width; 614 else 615 xscale = 1 << FP_SHIFT; 616 617 if (params->dst_height > 1) 618 yscale = ((params->src_scan_height - 1) << FP_SHIFT) / 619 params->dst_height; 620 else 621 yscale = 1 << FP_SHIFT; 622 623 /*if (params->format & I915_OVERLAY_YUV_PLANAR) {*/ 624 xscale_UV = xscale/uv_hscale; 625 yscale_UV = yscale/uv_vscale; 626 /* make the Y scale to UV scale ratio an exact multiply */ 627 xscale = xscale_UV * uv_hscale; 628 yscale = yscale_UV * uv_vscale; 629 /*} else { 630 xscale_UV = 0; 631 yscale_UV = 0; 632 }*/ 633 634 if (xscale != overlay->old_xscale || yscale != overlay->old_yscale) 635 scale_changed = true; 636 overlay->old_xscale = xscale; 637 overlay->old_yscale = yscale; 638 639 iowrite32(((yscale & FRACT_MASK) << 20) | 640 ((xscale >> FP_SHIFT) << 16) | 641 ((xscale & FRACT_MASK) << 3), 642 ®s->YRGBSCALE); 643 644 iowrite32(((yscale_UV & FRACT_MASK) << 20) | 645 ((xscale_UV >> FP_SHIFT) << 16) | 646 ((xscale_UV & FRACT_MASK) << 3), 647 ®s->UVSCALE); 648 649 iowrite32((((yscale >> FP_SHIFT) << 16) | 650 ((yscale_UV >> FP_SHIFT) << 0)), 651 ®s->UVSCALEV); 652 653 if (scale_changed) 654 update_polyphase_filter(regs); 655 656 return scale_changed; 657 } 658 659 static void update_colorkey(struct intel_overlay *overlay, 660 struct overlay_registers __iomem *regs) 661 { 662 const struct intel_plane_state *state = 663 to_intel_plane_state(overlay->crtc->base.primary->state); 664 u32 key = overlay->color_key; 665 u32 format = 0; 666 u32 flags = 0; 667 668 if (overlay->color_key_enabled) 669 flags |= DST_KEY_ENABLE; 670 671 if (state->base.visible) 672 format = state->base.fb->format->format; 673 674 switch (format) { 675 case DRM_FORMAT_C8: 676 key = 0; 677 flags |= CLK_RGB8I_MASK; 678 break; 679 case DRM_FORMAT_XRGB1555: 680 key = RGB15_TO_COLORKEY(key); 681 flags |= CLK_RGB15_MASK; 682 break; 683 case DRM_FORMAT_RGB565: 684 key = RGB16_TO_COLORKEY(key); 685 flags |= CLK_RGB16_MASK; 686 break; 687 default: 688 flags |= CLK_RGB24_MASK; 689 break; 690 } 691 692 iowrite32(key, ®s->DCLRKV); 693 iowrite32(flags, ®s->DCLRKM); 694 } 695 696 static u32 overlay_cmd_reg(struct drm_intel_overlay_put_image *params) 697 { 698 u32 cmd = OCMD_ENABLE | OCMD_BUF_TYPE_FRAME | OCMD_BUFFER0; 699 700 if (params->flags & I915_OVERLAY_YUV_PLANAR) { 701 switch (params->flags & I915_OVERLAY_DEPTH_MASK) { 702 case I915_OVERLAY_YUV422: 703 cmd |= OCMD_YUV_422_PLANAR; 704 break; 705 case I915_OVERLAY_YUV420: 706 cmd |= OCMD_YUV_420_PLANAR; 707 break; 708 case I915_OVERLAY_YUV411: 709 case I915_OVERLAY_YUV410: 710 cmd |= OCMD_YUV_410_PLANAR; 711 break; 712 } 713 } else { /* YUV packed */ 714 switch (params->flags & I915_OVERLAY_DEPTH_MASK) { 715 case I915_OVERLAY_YUV422: 716 cmd |= OCMD_YUV_422_PACKED; 717 break; 718 case I915_OVERLAY_YUV411: 719 cmd |= OCMD_YUV_411_PACKED; 720 break; 721 } 722 723 switch (params->flags & I915_OVERLAY_SWAP_MASK) { 724 case I915_OVERLAY_NO_SWAP: 725 break; 726 case I915_OVERLAY_UV_SWAP: 727 cmd |= OCMD_UV_SWAP; 728 break; 729 case I915_OVERLAY_Y_SWAP: 730 cmd |= OCMD_Y_SWAP; 731 break; 732 case I915_OVERLAY_Y_AND_UV_SWAP: 733 cmd |= OCMD_Y_AND_UV_SWAP; 734 break; 735 } 736 } 737 738 return cmd; 739 } 740 741 static int intel_overlay_do_put_image(struct intel_overlay *overlay, 742 struct drm_i915_gem_object *new_bo, 743 struct drm_intel_overlay_put_image *params) 744 { 745 struct overlay_registers __iomem *regs = overlay->regs; 746 struct drm_i915_private *dev_priv = overlay->i915; 747 u32 swidth, swidthsw, sheight, ostride; 748 enum pipe pipe = overlay->crtc->pipe; 749 bool scale_changed = false; 750 struct i915_vma *vma; 751 int ret, tmp_width; 752 753 WARN_ON(!drm_modeset_is_locked(&dev_priv->drm.mode_config.connection_mutex)); 754 755 ret = intel_overlay_release_old_vid(overlay); 756 if (ret != 0) 757 return ret; 758 759 atomic_inc(&dev_priv->gpu_error.pending_fb_pin); 760 761 i915_gem_object_lock(new_bo); 762 vma = i915_gem_object_pin_to_display_plane(new_bo, 763 0, NULL, PIN_MAPPABLE); 764 i915_gem_object_unlock(new_bo); 765 if (IS_ERR(vma)) { 766 ret = PTR_ERR(vma); 767 goto out_pin_section; 768 } 769 intel_frontbuffer_flush(new_bo->frontbuffer, ORIGIN_DIRTYFB); 770 771 if (!overlay->active) { 772 u32 oconfig; 773 774 oconfig = OCONF_CC_OUT_8BIT; 775 if (IS_GEN(dev_priv, 4)) 776 oconfig |= OCONF_CSC_MODE_BT709; 777 oconfig |= pipe == 0 ? 778 OCONF_PIPE_A : OCONF_PIPE_B; 779 iowrite32(oconfig, ®s->OCONFIG); 780 781 ret = intel_overlay_on(overlay); 782 if (ret != 0) 783 goto out_unpin; 784 } 785 786 iowrite32(params->dst_y << 16 | params->dst_x, ®s->DWINPOS); 787 iowrite32(params->dst_height << 16 | params->dst_width, ®s->DWINSZ); 788 789 if (params->flags & I915_OVERLAY_YUV_PACKED) 790 tmp_width = packed_width_bytes(params->flags, 791 params->src_width); 792 else 793 tmp_width = params->src_width; 794 795 swidth = params->src_width; 796 swidthsw = calc_swidthsw(dev_priv, params->offset_Y, tmp_width); 797 sheight = params->src_height; 798 iowrite32(i915_ggtt_offset(vma) + params->offset_Y, ®s->OBUF_0Y); 799 ostride = params->stride_Y; 800 801 if (params->flags & I915_OVERLAY_YUV_PLANAR) { 802 int uv_hscale = uv_hsubsampling(params->flags); 803 int uv_vscale = uv_vsubsampling(params->flags); 804 u32 tmp_U, tmp_V; 805 806 swidth |= (params->src_width / uv_hscale) << 16; 807 sheight |= (params->src_height / uv_vscale) << 16; 808 809 tmp_U = calc_swidthsw(dev_priv, params->offset_U, 810 params->src_width / uv_hscale); 811 tmp_V = calc_swidthsw(dev_priv, params->offset_V, 812 params->src_width / uv_hscale); 813 swidthsw |= max(tmp_U, tmp_V) << 16; 814 815 iowrite32(i915_ggtt_offset(vma) + params->offset_U, 816 ®s->OBUF_0U); 817 iowrite32(i915_ggtt_offset(vma) + params->offset_V, 818 ®s->OBUF_0V); 819 820 ostride |= params->stride_UV << 16; 821 } 822 823 iowrite32(swidth, ®s->SWIDTH); 824 iowrite32(swidthsw, ®s->SWIDTHSW); 825 iowrite32(sheight, ®s->SHEIGHT); 826 iowrite32(ostride, ®s->OSTRIDE); 827 828 scale_changed = update_scaling_factors(overlay, regs, params); 829 830 update_colorkey(overlay, regs); 831 832 iowrite32(overlay_cmd_reg(params), ®s->OCMD); 833 834 ret = intel_overlay_continue(overlay, vma, scale_changed); 835 if (ret) 836 goto out_unpin; 837 838 return 0; 839 840 out_unpin: 841 i915_gem_object_unpin_from_display_plane(vma); 842 out_pin_section: 843 atomic_dec(&dev_priv->gpu_error.pending_fb_pin); 844 845 return ret; 846 } 847 848 int intel_overlay_switch_off(struct intel_overlay *overlay) 849 { 850 struct drm_i915_private *dev_priv = overlay->i915; 851 int ret; 852 853 WARN_ON(!drm_modeset_is_locked(&dev_priv->drm.mode_config.connection_mutex)); 854 855 ret = intel_overlay_recover_from_interrupt(overlay); 856 if (ret != 0) 857 return ret; 858 859 if (!overlay->active) 860 return 0; 861 862 ret = intel_overlay_release_old_vid(overlay); 863 if (ret != 0) 864 return ret; 865 866 iowrite32(0, &overlay->regs->OCMD); 867 868 return intel_overlay_off(overlay); 869 } 870 871 static int check_overlay_possible_on_crtc(struct intel_overlay *overlay, 872 struct intel_crtc *crtc) 873 { 874 if (!crtc->active) 875 return -EINVAL; 876 877 /* can't use the overlay with double wide pipe */ 878 if (crtc->config->double_wide) 879 return -EINVAL; 880 881 return 0; 882 } 883 884 static void update_pfit_vscale_ratio(struct intel_overlay *overlay) 885 { 886 struct drm_i915_private *dev_priv = overlay->i915; 887 u32 pfit_control = I915_READ(PFIT_CONTROL); 888 u32 ratio; 889 890 /* XXX: This is not the same logic as in the xorg driver, but more in 891 * line with the intel documentation for the i965 892 */ 893 if (INTEL_GEN(dev_priv) >= 4) { 894 /* on i965 use the PGM reg to read out the autoscaler values */ 895 ratio = I915_READ(PFIT_PGM_RATIOS) >> PFIT_VERT_SCALE_SHIFT_965; 896 } else { 897 if (pfit_control & VERT_AUTO_SCALE) 898 ratio = I915_READ(PFIT_AUTO_RATIOS); 899 else 900 ratio = I915_READ(PFIT_PGM_RATIOS); 901 ratio >>= PFIT_VERT_SCALE_SHIFT; 902 } 903 904 overlay->pfit_vscale_ratio = ratio; 905 } 906 907 static int check_overlay_dst(struct intel_overlay *overlay, 908 struct drm_intel_overlay_put_image *rec) 909 { 910 const struct intel_crtc_state *pipe_config = 911 overlay->crtc->config; 912 913 if (rec->dst_x < pipe_config->pipe_src_w && 914 rec->dst_x + rec->dst_width <= pipe_config->pipe_src_w && 915 rec->dst_y < pipe_config->pipe_src_h && 916 rec->dst_y + rec->dst_height <= pipe_config->pipe_src_h) 917 return 0; 918 else 919 return -EINVAL; 920 } 921 922 static int check_overlay_scaling(struct drm_intel_overlay_put_image *rec) 923 { 924 u32 tmp; 925 926 /* downscaling limit is 8.0 */ 927 tmp = ((rec->src_scan_height << 16) / rec->dst_height) >> 16; 928 if (tmp > 7) 929 return -EINVAL; 930 931 tmp = ((rec->src_scan_width << 16) / rec->dst_width) >> 16; 932 if (tmp > 7) 933 return -EINVAL; 934 935 return 0; 936 } 937 938 static int check_overlay_src(struct drm_i915_private *dev_priv, 939 struct drm_intel_overlay_put_image *rec, 940 struct drm_i915_gem_object *new_bo) 941 { 942 int uv_hscale = uv_hsubsampling(rec->flags); 943 int uv_vscale = uv_vsubsampling(rec->flags); 944 u32 stride_mask; 945 int depth; 946 u32 tmp; 947 948 /* check src dimensions */ 949 if (IS_I845G(dev_priv) || IS_I830(dev_priv)) { 950 if (rec->src_height > IMAGE_MAX_HEIGHT_LEGACY || 951 rec->src_width > IMAGE_MAX_WIDTH_LEGACY) 952 return -EINVAL; 953 } else { 954 if (rec->src_height > IMAGE_MAX_HEIGHT || 955 rec->src_width > IMAGE_MAX_WIDTH) 956 return -EINVAL; 957 } 958 959 /* better safe than sorry, use 4 as the maximal subsampling ratio */ 960 if (rec->src_height < N_VERT_Y_TAPS*4 || 961 rec->src_width < N_HORIZ_Y_TAPS*4) 962 return -EINVAL; 963 964 /* check alignment constraints */ 965 switch (rec->flags & I915_OVERLAY_TYPE_MASK) { 966 case I915_OVERLAY_RGB: 967 /* not implemented */ 968 return -EINVAL; 969 970 case I915_OVERLAY_YUV_PACKED: 971 if (uv_vscale != 1) 972 return -EINVAL; 973 974 depth = packed_depth_bytes(rec->flags); 975 if (depth < 0) 976 return depth; 977 978 /* ignore UV planes */ 979 rec->stride_UV = 0; 980 rec->offset_U = 0; 981 rec->offset_V = 0; 982 /* check pixel alignment */ 983 if (rec->offset_Y % depth) 984 return -EINVAL; 985 break; 986 987 case I915_OVERLAY_YUV_PLANAR: 988 if (uv_vscale < 0 || uv_hscale < 0) 989 return -EINVAL; 990 /* no offset restrictions for planar formats */ 991 break; 992 993 default: 994 return -EINVAL; 995 } 996 997 if (rec->src_width % uv_hscale) 998 return -EINVAL; 999 1000 /* stride checking */ 1001 if (IS_I830(dev_priv) || IS_I845G(dev_priv)) 1002 stride_mask = 255; 1003 else 1004 stride_mask = 63; 1005 1006 if (rec->stride_Y & stride_mask || rec->stride_UV & stride_mask) 1007 return -EINVAL; 1008 if (IS_GEN(dev_priv, 4) && rec->stride_Y < 512) 1009 return -EINVAL; 1010 1011 tmp = (rec->flags & I915_OVERLAY_TYPE_MASK) == I915_OVERLAY_YUV_PLANAR ? 1012 4096 : 8192; 1013 if (rec->stride_Y > tmp || rec->stride_UV > 2*1024) 1014 return -EINVAL; 1015 1016 /* check buffer dimensions */ 1017 switch (rec->flags & I915_OVERLAY_TYPE_MASK) { 1018 case I915_OVERLAY_RGB: 1019 case I915_OVERLAY_YUV_PACKED: 1020 /* always 4 Y values per depth pixels */ 1021 if (packed_width_bytes(rec->flags, rec->src_width) > rec->stride_Y) 1022 return -EINVAL; 1023 1024 tmp = rec->stride_Y*rec->src_height; 1025 if (rec->offset_Y + tmp > new_bo->base.size) 1026 return -EINVAL; 1027 break; 1028 1029 case I915_OVERLAY_YUV_PLANAR: 1030 if (rec->src_width > rec->stride_Y) 1031 return -EINVAL; 1032 if (rec->src_width/uv_hscale > rec->stride_UV) 1033 return -EINVAL; 1034 1035 tmp = rec->stride_Y * rec->src_height; 1036 if (rec->offset_Y + tmp > new_bo->base.size) 1037 return -EINVAL; 1038 1039 tmp = rec->stride_UV * (rec->src_height / uv_vscale); 1040 if (rec->offset_U + tmp > new_bo->base.size || 1041 rec->offset_V + tmp > new_bo->base.size) 1042 return -EINVAL; 1043 break; 1044 } 1045 1046 return 0; 1047 } 1048 1049 int intel_overlay_put_image_ioctl(struct drm_device *dev, void *data, 1050 struct drm_file *file_priv) 1051 { 1052 struct drm_intel_overlay_put_image *params = data; 1053 struct drm_i915_private *dev_priv = to_i915(dev); 1054 struct intel_overlay *overlay; 1055 struct drm_crtc *drmmode_crtc; 1056 struct intel_crtc *crtc; 1057 struct drm_i915_gem_object *new_bo; 1058 int ret; 1059 1060 overlay = dev_priv->overlay; 1061 if (!overlay) { 1062 DRM_DEBUG("userspace bug: no overlay\n"); 1063 return -ENODEV; 1064 } 1065 1066 if (!(params->flags & I915_OVERLAY_ENABLE)) { 1067 drm_modeset_lock_all(dev); 1068 ret = intel_overlay_switch_off(overlay); 1069 drm_modeset_unlock_all(dev); 1070 1071 return ret; 1072 } 1073 1074 drmmode_crtc = drm_crtc_find(dev, file_priv, params->crtc_id); 1075 if (!drmmode_crtc) 1076 return -ENOENT; 1077 crtc = to_intel_crtc(drmmode_crtc); 1078 1079 new_bo = i915_gem_object_lookup(file_priv, params->bo_handle); 1080 if (!new_bo) 1081 return -ENOENT; 1082 1083 drm_modeset_lock_all(dev); 1084 1085 if (i915_gem_object_is_tiled(new_bo)) { 1086 DRM_DEBUG_KMS("buffer used for overlay image can not be tiled\n"); 1087 ret = -EINVAL; 1088 goto out_unlock; 1089 } 1090 1091 ret = intel_overlay_recover_from_interrupt(overlay); 1092 if (ret != 0) 1093 goto out_unlock; 1094 1095 if (overlay->crtc != crtc) { 1096 ret = intel_overlay_switch_off(overlay); 1097 if (ret != 0) 1098 goto out_unlock; 1099 1100 ret = check_overlay_possible_on_crtc(overlay, crtc); 1101 if (ret != 0) 1102 goto out_unlock; 1103 1104 overlay->crtc = crtc; 1105 crtc->overlay = overlay; 1106 1107 /* line too wide, i.e. one-line-mode */ 1108 if (crtc->config->pipe_src_w > 1024 && 1109 crtc->config->gmch_pfit.control & PFIT_ENABLE) { 1110 overlay->pfit_active = true; 1111 update_pfit_vscale_ratio(overlay); 1112 } else 1113 overlay->pfit_active = false; 1114 } 1115 1116 ret = check_overlay_dst(overlay, params); 1117 if (ret != 0) 1118 goto out_unlock; 1119 1120 if (overlay->pfit_active) { 1121 params->dst_y = (((u32)params->dst_y << 12) / 1122 overlay->pfit_vscale_ratio); 1123 /* shifting right rounds downwards, so add 1 */ 1124 params->dst_height = (((u32)params->dst_height << 12) / 1125 overlay->pfit_vscale_ratio) + 1; 1126 } 1127 1128 if (params->src_scan_height > params->src_height || 1129 params->src_scan_width > params->src_width) { 1130 ret = -EINVAL; 1131 goto out_unlock; 1132 } 1133 1134 ret = check_overlay_src(dev_priv, params, new_bo); 1135 if (ret != 0) 1136 goto out_unlock; 1137 1138 /* Check scaling after src size to prevent a divide-by-zero. */ 1139 ret = check_overlay_scaling(params); 1140 if (ret != 0) 1141 goto out_unlock; 1142 1143 ret = intel_overlay_do_put_image(overlay, new_bo, params); 1144 if (ret != 0) 1145 goto out_unlock; 1146 1147 drm_modeset_unlock_all(dev); 1148 i915_gem_object_put(new_bo); 1149 1150 return 0; 1151 1152 out_unlock: 1153 drm_modeset_unlock_all(dev); 1154 i915_gem_object_put(new_bo); 1155 1156 return ret; 1157 } 1158 1159 static void update_reg_attrs(struct intel_overlay *overlay, 1160 struct overlay_registers __iomem *regs) 1161 { 1162 iowrite32((overlay->contrast << 18) | (overlay->brightness & 0xff), 1163 ®s->OCLRC0); 1164 iowrite32(overlay->saturation, ®s->OCLRC1); 1165 } 1166 1167 static bool check_gamma_bounds(u32 gamma1, u32 gamma2) 1168 { 1169 int i; 1170 1171 if (gamma1 & 0xff000000 || gamma2 & 0xff000000) 1172 return false; 1173 1174 for (i = 0; i < 3; i++) { 1175 if (((gamma1 >> i*8) & 0xff) >= ((gamma2 >> i*8) & 0xff)) 1176 return false; 1177 } 1178 1179 return true; 1180 } 1181 1182 static bool check_gamma5_errata(u32 gamma5) 1183 { 1184 int i; 1185 1186 for (i = 0; i < 3; i++) { 1187 if (((gamma5 >> i*8) & 0xff) == 0x80) 1188 return false; 1189 } 1190 1191 return true; 1192 } 1193 1194 static int check_gamma(struct drm_intel_overlay_attrs *attrs) 1195 { 1196 if (!check_gamma_bounds(0, attrs->gamma0) || 1197 !check_gamma_bounds(attrs->gamma0, attrs->gamma1) || 1198 !check_gamma_bounds(attrs->gamma1, attrs->gamma2) || 1199 !check_gamma_bounds(attrs->gamma2, attrs->gamma3) || 1200 !check_gamma_bounds(attrs->gamma3, attrs->gamma4) || 1201 !check_gamma_bounds(attrs->gamma4, attrs->gamma5) || 1202 !check_gamma_bounds(attrs->gamma5, 0x00ffffff)) 1203 return -EINVAL; 1204 1205 if (!check_gamma5_errata(attrs->gamma5)) 1206 return -EINVAL; 1207 1208 return 0; 1209 } 1210 1211 int intel_overlay_attrs_ioctl(struct drm_device *dev, void *data, 1212 struct drm_file *file_priv) 1213 { 1214 struct drm_intel_overlay_attrs *attrs = data; 1215 struct drm_i915_private *dev_priv = to_i915(dev); 1216 struct intel_overlay *overlay; 1217 int ret; 1218 1219 overlay = dev_priv->overlay; 1220 if (!overlay) { 1221 DRM_DEBUG("userspace bug: no overlay\n"); 1222 return -ENODEV; 1223 } 1224 1225 drm_modeset_lock_all(dev); 1226 1227 ret = -EINVAL; 1228 if (!(attrs->flags & I915_OVERLAY_UPDATE_ATTRS)) { 1229 attrs->color_key = overlay->color_key; 1230 attrs->brightness = overlay->brightness; 1231 attrs->contrast = overlay->contrast; 1232 attrs->saturation = overlay->saturation; 1233 1234 if (!IS_GEN(dev_priv, 2)) { 1235 attrs->gamma0 = I915_READ(OGAMC0); 1236 attrs->gamma1 = I915_READ(OGAMC1); 1237 attrs->gamma2 = I915_READ(OGAMC2); 1238 attrs->gamma3 = I915_READ(OGAMC3); 1239 attrs->gamma4 = I915_READ(OGAMC4); 1240 attrs->gamma5 = I915_READ(OGAMC5); 1241 } 1242 } else { 1243 if (attrs->brightness < -128 || attrs->brightness > 127) 1244 goto out_unlock; 1245 if (attrs->contrast > 255) 1246 goto out_unlock; 1247 if (attrs->saturation > 1023) 1248 goto out_unlock; 1249 1250 overlay->color_key = attrs->color_key; 1251 overlay->brightness = attrs->brightness; 1252 overlay->contrast = attrs->contrast; 1253 overlay->saturation = attrs->saturation; 1254 1255 update_reg_attrs(overlay, overlay->regs); 1256 1257 if (attrs->flags & I915_OVERLAY_UPDATE_GAMMA) { 1258 if (IS_GEN(dev_priv, 2)) 1259 goto out_unlock; 1260 1261 if (overlay->active) { 1262 ret = -EBUSY; 1263 goto out_unlock; 1264 } 1265 1266 ret = check_gamma(attrs); 1267 if (ret) 1268 goto out_unlock; 1269 1270 I915_WRITE(OGAMC0, attrs->gamma0); 1271 I915_WRITE(OGAMC1, attrs->gamma1); 1272 I915_WRITE(OGAMC2, attrs->gamma2); 1273 I915_WRITE(OGAMC3, attrs->gamma3); 1274 I915_WRITE(OGAMC4, attrs->gamma4); 1275 I915_WRITE(OGAMC5, attrs->gamma5); 1276 } 1277 } 1278 overlay->color_key_enabled = (attrs->flags & I915_OVERLAY_DISABLE_DEST_COLORKEY) == 0; 1279 1280 ret = 0; 1281 out_unlock: 1282 drm_modeset_unlock_all(dev); 1283 1284 return ret; 1285 } 1286 1287 static int get_registers(struct intel_overlay *overlay, bool use_phys) 1288 { 1289 struct drm_i915_private *i915 = overlay->i915; 1290 struct drm_i915_gem_object *obj; 1291 struct i915_vma *vma; 1292 int err; 1293 1294 obj = i915_gem_object_create_stolen(i915, PAGE_SIZE); 1295 if (IS_ERR(obj)) 1296 obj = i915_gem_object_create_internal(i915, PAGE_SIZE); 1297 if (IS_ERR(obj)) 1298 return PTR_ERR(obj); 1299 1300 vma = i915_gem_object_ggtt_pin(obj, NULL, 0, 0, PIN_MAPPABLE); 1301 if (IS_ERR(vma)) { 1302 err = PTR_ERR(vma); 1303 goto err_put_bo; 1304 } 1305 1306 if (use_phys) 1307 overlay->flip_addr = sg_dma_address(obj->mm.pages->sgl); 1308 else 1309 overlay->flip_addr = i915_ggtt_offset(vma); 1310 overlay->regs = i915_vma_pin_iomap(vma); 1311 i915_vma_unpin(vma); 1312 1313 if (IS_ERR(overlay->regs)) { 1314 err = PTR_ERR(overlay->regs); 1315 goto err_put_bo; 1316 } 1317 1318 overlay->reg_bo = obj; 1319 return 0; 1320 1321 err_put_bo: 1322 i915_gem_object_put(obj); 1323 return err; 1324 } 1325 1326 void intel_overlay_setup(struct drm_i915_private *dev_priv) 1327 { 1328 struct intel_overlay *overlay; 1329 int ret; 1330 1331 if (!HAS_OVERLAY(dev_priv)) 1332 return; 1333 1334 if (!HAS_ENGINE(dev_priv, RCS0)) 1335 return; 1336 1337 overlay = kzalloc(sizeof(*overlay), GFP_KERNEL); 1338 if (!overlay) 1339 return; 1340 1341 overlay->i915 = dev_priv; 1342 overlay->context = dev_priv->engine[RCS0]->kernel_context; 1343 GEM_BUG_ON(!overlay->context); 1344 1345 overlay->color_key = 0x0101fe; 1346 overlay->color_key_enabled = true; 1347 overlay->brightness = -19; 1348 overlay->contrast = 75; 1349 overlay->saturation = 146; 1350 1351 i915_active_init(&overlay->last_flip, 1352 NULL, intel_overlay_last_flip_retire); 1353 1354 ret = get_registers(overlay, OVERLAY_NEEDS_PHYSICAL(dev_priv)); 1355 if (ret) 1356 goto out_free; 1357 1358 memset_io(overlay->regs, 0, sizeof(struct overlay_registers)); 1359 update_polyphase_filter(overlay->regs); 1360 update_reg_attrs(overlay, overlay->regs); 1361 1362 dev_priv->overlay = overlay; 1363 DRM_INFO("Initialized overlay support.\n"); 1364 return; 1365 1366 out_free: 1367 kfree(overlay); 1368 } 1369 1370 void intel_overlay_cleanup(struct drm_i915_private *dev_priv) 1371 { 1372 struct intel_overlay *overlay; 1373 1374 overlay = fetch_and_zero(&dev_priv->overlay); 1375 if (!overlay) 1376 return; 1377 1378 /* 1379 * The bo's should be free'd by the generic code already. 1380 * Furthermore modesetting teardown happens beforehand so the 1381 * hardware should be off already. 1382 */ 1383 WARN_ON(overlay->active); 1384 1385 i915_gem_object_put(overlay->reg_bo); 1386 i915_active_fini(&overlay->last_flip); 1387 1388 kfree(overlay); 1389 } 1390 1391 #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR) 1392 1393 struct intel_overlay_error_state { 1394 struct overlay_registers regs; 1395 unsigned long base; 1396 u32 dovsta; 1397 u32 isr; 1398 }; 1399 1400 struct intel_overlay_error_state * 1401 intel_overlay_capture_error_state(struct drm_i915_private *dev_priv) 1402 { 1403 struct intel_overlay *overlay = dev_priv->overlay; 1404 struct intel_overlay_error_state *error; 1405 1406 if (!overlay || !overlay->active) 1407 return NULL; 1408 1409 error = kmalloc(sizeof(*error), GFP_ATOMIC); 1410 if (error == NULL) 1411 return NULL; 1412 1413 error->dovsta = I915_READ(DOVSTA); 1414 error->isr = I915_READ(GEN2_ISR); 1415 error->base = overlay->flip_addr; 1416 1417 memcpy_fromio(&error->regs, overlay->regs, sizeof(error->regs)); 1418 1419 return error; 1420 } 1421 1422 void 1423 intel_overlay_print_error_state(struct drm_i915_error_state_buf *m, 1424 struct intel_overlay_error_state *error) 1425 { 1426 i915_error_printf(m, "Overlay, status: 0x%08x, interrupt: 0x%08x\n", 1427 error->dovsta, error->isr); 1428 i915_error_printf(m, " Register file at 0x%08lx:\n", 1429 error->base); 1430 1431 #define P(x) i915_error_printf(m, " " #x ": 0x%08x\n", error->regs.x) 1432 P(OBUF_0Y); 1433 P(OBUF_1Y); 1434 P(OBUF_0U); 1435 P(OBUF_0V); 1436 P(OBUF_1U); 1437 P(OBUF_1V); 1438 P(OSTRIDE); 1439 P(YRGB_VPH); 1440 P(UV_VPH); 1441 P(HORZ_PH); 1442 P(INIT_PHS); 1443 P(DWINPOS); 1444 P(DWINSZ); 1445 P(SWIDTH); 1446 P(SWIDTHSW); 1447 P(SHEIGHT); 1448 P(YRGBSCALE); 1449 P(UVSCALE); 1450 P(OCLRC0); 1451 P(OCLRC1); 1452 P(DCLRKV); 1453 P(DCLRKM); 1454 P(SCLRKVH); 1455 P(SCLRKVL); 1456 P(SCLRKEN); 1457 P(OCONFIG); 1458 P(OCMD); 1459 P(OSTART_0Y); 1460 P(OSTART_1Y); 1461 P(OSTART_0U); 1462 P(OSTART_0V); 1463 P(OSTART_1U); 1464 P(OSTART_1V); 1465 P(OTILEOFF_0Y); 1466 P(OTILEOFF_1Y); 1467 P(OTILEOFF_0U); 1468 P(OTILEOFF_0V); 1469 P(OTILEOFF_1U); 1470 P(OTILEOFF_1V); 1471 P(FASTHSCALE); 1472 P(UVSCALEV); 1473 #undef P 1474 } 1475 1476 #endif 1477