1 /* 2 * Copyright © 2009 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 * SOFTWARE. 22 * 23 * Authors: 24 * Daniel Vetter <daniel@ffwll.ch> 25 * 26 * Derived from Xorg ddx, xf86-video-intel, src/i830_video.c 27 */ 28 29 #include <drm/drm_fourcc.h> 30 31 #include "gem/i915_gem_internal.h" 32 #include "gem/i915_gem_object_frontbuffer.h" 33 #include "gem/i915_gem_pm.h" 34 35 #include "gt/intel_gpu_commands.h" 36 #include "gt/intel_ring.h" 37 38 #include "i915_drv.h" 39 #include "i915_reg.h" 40 #include "intel_color_regs.h" 41 #include "intel_de.h" 42 #include "intel_display_regs.h" 43 #include "intel_display_types.h" 44 #include "intel_frontbuffer.h" 45 #include "intel_overlay.h" 46 #include "intel_pci_config.h" 47 #include "intel_pfit_regs.h" 48 49 /* Limits for overlay size. According to intel doc, the real limits are: 50 * Y width: 4095, UV width (planar): 2047, Y height: 2047, 51 * UV width (planar): * 1023. But the xorg thinks 2048 for height and width. Use 52 * the minimum of both. 53 */ 54 #define IMAGE_MAX_WIDTH 2048 55 #define IMAGE_MAX_HEIGHT 2046 /* 2 * 1023 */ 56 /* on 830 and 845 these large limits result in the card hanging */ 57 #define IMAGE_MAX_WIDTH_LEGACY 1024 58 #define IMAGE_MAX_HEIGHT_LEGACY 1088 59 60 /* overlay register definitions */ 61 /* OCMD register */ 62 #define OCMD_TILED_SURFACE (0x1<<19) 63 #define OCMD_MIRROR_MASK (0x3<<17) 64 #define OCMD_MIRROR_MODE (0x3<<17) 65 #define OCMD_MIRROR_HORIZONTAL (0x1<<17) 66 #define OCMD_MIRROR_VERTICAL (0x2<<17) 67 #define OCMD_MIRROR_BOTH (0x3<<17) 68 #define OCMD_BYTEORDER_MASK (0x3<<14) /* zero for YUYV or FOURCC YUY2 */ 69 #define OCMD_UV_SWAP (0x1<<14) /* YVYU */ 70 #define OCMD_Y_SWAP (0x2<<14) /* UYVY or FOURCC UYVY */ 71 #define OCMD_Y_AND_UV_SWAP (0x3<<14) /* VYUY */ 72 #define OCMD_SOURCE_FORMAT_MASK (0xf<<10) 73 #define OCMD_RGB_888 (0x1<<10) /* not in i965 Intel docs */ 74 #define OCMD_RGB_555 (0x2<<10) /* not in i965 Intel docs */ 75 #define OCMD_RGB_565 (0x3<<10) /* not in i965 Intel docs */ 76 #define OCMD_YUV_422_PACKED (0x8<<10) 77 #define OCMD_YUV_411_PACKED (0x9<<10) /* not in i965 Intel docs */ 78 #define OCMD_YUV_420_PLANAR (0xc<<10) 79 #define OCMD_YUV_422_PLANAR (0xd<<10) 80 #define OCMD_YUV_410_PLANAR (0xe<<10) /* also 411 */ 81 #define OCMD_TVSYNCFLIP_PARITY (0x1<<9) 82 #define OCMD_TVSYNCFLIP_ENABLE (0x1<<7) 83 #define OCMD_BUF_TYPE_MASK (0x1<<5) 84 #define OCMD_BUF_TYPE_FRAME (0x0<<5) 85 #define OCMD_BUF_TYPE_FIELD (0x1<<5) 86 #define OCMD_TEST_MODE (0x1<<4) 87 #define OCMD_BUFFER_SELECT (0x3<<2) 88 #define OCMD_BUFFER0 (0x0<<2) 89 #define OCMD_BUFFER1 (0x1<<2) 90 #define OCMD_FIELD_SELECT (0x1<<2) 91 #define OCMD_FIELD0 (0x0<<1) 92 #define OCMD_FIELD1 (0x1<<1) 93 #define OCMD_ENABLE (0x1<<0) 94 95 /* OCONFIG register */ 96 #define OCONF_PIPE_MASK (0x1<<18) 97 #define OCONF_PIPE_A (0x0<<18) 98 #define OCONF_PIPE_B (0x1<<18) 99 #define OCONF_GAMMA2_ENABLE (0x1<<16) 100 #define OCONF_CSC_MODE_BT601 (0x0<<5) 101 #define OCONF_CSC_MODE_BT709 (0x1<<5) 102 #define OCONF_CSC_BYPASS (0x1<<4) 103 #define OCONF_CC_OUT_8BIT (0x1<<3) 104 #define OCONF_TEST_MODE (0x1<<2) 105 #define OCONF_THREE_LINE_BUFFER (0x1<<0) 106 #define OCONF_TWO_LINE_BUFFER (0x0<<0) 107 108 /* DCLRKM (dst-key) register */ 109 #define DST_KEY_ENABLE (0x1<<31) 110 #define CLK_RGB24_MASK 0x0 111 #define CLK_RGB16_MASK 0x070307 112 #define CLK_RGB15_MASK 0x070707 113 114 #define RGB30_TO_COLORKEY(c) \ 115 ((((c) & 0x3fc00000) >> 6) | (((c) & 0x000ff000) >> 4) | (((c) & 0x000003fc) >> 2)) 116 #define RGB16_TO_COLORKEY(c) \ 117 ((((c) & 0xf800) << 8) | (((c) & 0x07e0) << 5) | (((c) & 0x001f) << 3)) 118 #define RGB15_TO_COLORKEY(c) \ 119 ((((c) & 0x7c00) << 9) | (((c) & 0x03e0) << 6) | (((c) & 0x001f) << 3)) 120 #define RGB8I_TO_COLORKEY(c) \ 121 ((((c) & 0xff) << 16) | (((c) & 0xff) << 8) | (((c) & 0xff) << 0)) 122 123 /* overlay flip addr flag */ 124 #define OFC_UPDATE 0x1 125 126 /* polyphase filter coefficients */ 127 #define N_HORIZ_Y_TAPS 5 128 #define N_VERT_Y_TAPS 3 129 #define N_HORIZ_UV_TAPS 3 130 #define N_VERT_UV_TAPS 3 131 #define N_PHASES 17 132 #define MAX_TAPS 5 133 134 /* memory bufferd overlay registers */ 135 struct overlay_registers { 136 u32 OBUF_0Y; 137 u32 OBUF_1Y; 138 u32 OBUF_0U; 139 u32 OBUF_0V; 140 u32 OBUF_1U; 141 u32 OBUF_1V; 142 u32 OSTRIDE; 143 u32 YRGB_VPH; 144 u32 UV_VPH; 145 u32 HORZ_PH; 146 u32 INIT_PHS; 147 u32 DWINPOS; 148 u32 DWINSZ; 149 u32 SWIDTH; 150 u32 SWIDTHSW; 151 u32 SHEIGHT; 152 u32 YRGBSCALE; 153 u32 UVSCALE; 154 u32 OCLRC0; 155 u32 OCLRC1; 156 u32 DCLRKV; 157 u32 DCLRKM; 158 u32 SCLRKVH; 159 u32 SCLRKVL; 160 u32 SCLRKEN; 161 u32 OCONFIG; 162 u32 OCMD; 163 u32 RESERVED1; /* 0x6C */ 164 u32 OSTART_0Y; 165 u32 OSTART_1Y; 166 u32 OSTART_0U; 167 u32 OSTART_0V; 168 u32 OSTART_1U; 169 u32 OSTART_1V; 170 u32 OTILEOFF_0Y; 171 u32 OTILEOFF_1Y; 172 u32 OTILEOFF_0U; 173 u32 OTILEOFF_0V; 174 u32 OTILEOFF_1U; 175 u32 OTILEOFF_1V; 176 u32 FASTHSCALE; /* 0xA0 */ 177 u32 UVSCALEV; /* 0xA4 */ 178 u32 RESERVEDC[(0x200 - 0xA8) / 4]; /* 0xA8 - 0x1FC */ 179 u16 Y_VCOEFS[N_VERT_Y_TAPS * N_PHASES]; /* 0x200 */ 180 u16 RESERVEDD[0x100 / 2 - N_VERT_Y_TAPS * N_PHASES]; 181 u16 Y_HCOEFS[N_HORIZ_Y_TAPS * N_PHASES]; /* 0x300 */ 182 u16 RESERVEDE[0x200 / 2 - N_HORIZ_Y_TAPS * N_PHASES]; 183 u16 UV_VCOEFS[N_VERT_UV_TAPS * N_PHASES]; /* 0x500 */ 184 u16 RESERVEDF[0x100 / 2 - N_VERT_UV_TAPS * N_PHASES]; 185 u16 UV_HCOEFS[N_HORIZ_UV_TAPS * N_PHASES]; /* 0x600 */ 186 u16 RESERVEDG[0x100 / 2 - N_HORIZ_UV_TAPS * N_PHASES]; 187 }; 188 189 struct intel_overlay { 190 struct intel_display *display; 191 struct intel_context *context; 192 struct intel_crtc *crtc; 193 struct i915_vma *vma; 194 struct i915_vma *old_vma; 195 struct intel_frontbuffer *frontbuffer; 196 bool active; 197 bool pfit_active; 198 u32 pfit_vscale_ratio; /* shifted-point number, (1<<12) == 1.0 */ 199 u32 color_key:24; 200 u32 color_key_enabled:1; 201 u32 brightness, contrast, saturation; 202 u32 old_xscale, old_yscale; 203 /* register access */ 204 struct drm_i915_gem_object *reg_bo; 205 struct overlay_registers __iomem *regs; 206 u32 flip_addr; 207 /* flip handling */ 208 struct i915_active last_flip; 209 void (*flip_complete)(struct intel_overlay *ovl); 210 }; 211 212 static void i830_overlay_clock_gating(struct intel_display *display, 213 bool enable) 214 { 215 struct pci_dev *pdev = to_pci_dev(display->drm->dev); 216 u8 val; 217 218 /* WA_OVERLAY_CLKGATE:alm */ 219 if (enable) 220 intel_de_write(display, DSPCLK_GATE_D(display), 0); 221 else 222 intel_de_write(display, DSPCLK_GATE_D(display), 223 OVRUNIT_CLOCK_GATE_DISABLE); 224 225 /* WA_DISABLE_L2CACHE_CLOCK_GATING:alm */ 226 pci_bus_read_config_byte(pdev->bus, 227 PCI_DEVFN(0, 0), I830_CLOCK_GATE, &val); 228 if (enable) 229 val &= ~I830_L2_CACHE_CLOCK_GATE_DISABLE; 230 else 231 val |= I830_L2_CACHE_CLOCK_GATE_DISABLE; 232 pci_bus_write_config_byte(pdev->bus, 233 PCI_DEVFN(0, 0), I830_CLOCK_GATE, val); 234 } 235 236 static struct i915_request * 237 alloc_request(struct intel_overlay *overlay, void (*fn)(struct intel_overlay *)) 238 { 239 struct i915_request *rq; 240 int err; 241 242 overlay->flip_complete = fn; 243 244 rq = i915_request_create(overlay->context); 245 if (IS_ERR(rq)) 246 return rq; 247 248 err = i915_active_add_request(&overlay->last_flip, rq); 249 if (err) { 250 i915_request_add(rq); 251 return ERR_PTR(err); 252 } 253 254 return rq; 255 } 256 257 /* overlay needs to be disable in OCMD reg */ 258 static int intel_overlay_on(struct intel_overlay *overlay) 259 { 260 struct intel_display *display = overlay->display; 261 struct i915_request *rq; 262 u32 *cs; 263 264 drm_WARN_ON(display->drm, overlay->active); 265 266 rq = alloc_request(overlay, NULL); 267 if (IS_ERR(rq)) 268 return PTR_ERR(rq); 269 270 cs = intel_ring_begin(rq, 4); 271 if (IS_ERR(cs)) { 272 i915_request_add(rq); 273 return PTR_ERR(cs); 274 } 275 276 overlay->active = true; 277 278 if (display->platform.i830) 279 i830_overlay_clock_gating(display, false); 280 281 *cs++ = MI_OVERLAY_FLIP | MI_OVERLAY_ON; 282 *cs++ = overlay->flip_addr | OFC_UPDATE; 283 *cs++ = MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP; 284 *cs++ = MI_NOOP; 285 intel_ring_advance(rq, cs); 286 287 i915_request_add(rq); 288 289 return i915_active_wait(&overlay->last_flip); 290 } 291 292 static void intel_overlay_flip_prepare(struct intel_overlay *overlay, 293 struct i915_vma *vma) 294 { 295 struct intel_display *display = overlay->display; 296 enum pipe pipe = overlay->crtc->pipe; 297 struct intel_frontbuffer *frontbuffer = NULL; 298 299 drm_WARN_ON(display->drm, overlay->old_vma); 300 301 if (vma) 302 frontbuffer = intel_frontbuffer_get(intel_bo_to_drm_bo(vma->obj)); 303 304 intel_frontbuffer_track(overlay->frontbuffer, frontbuffer, 305 INTEL_FRONTBUFFER_OVERLAY(pipe)); 306 307 if (overlay->frontbuffer) 308 intel_frontbuffer_put(overlay->frontbuffer); 309 overlay->frontbuffer = frontbuffer; 310 311 intel_frontbuffer_flip_prepare(display, INTEL_FRONTBUFFER_OVERLAY(pipe)); 312 313 overlay->old_vma = overlay->vma; 314 if (vma) 315 overlay->vma = i915_vma_get(vma); 316 else 317 overlay->vma = NULL; 318 } 319 320 /* overlay needs to be enabled in OCMD reg */ 321 static int intel_overlay_continue(struct intel_overlay *overlay, 322 struct i915_vma *vma, 323 bool load_polyphase_filter) 324 { 325 struct intel_display *display = overlay->display; 326 struct i915_request *rq; 327 u32 flip_addr = overlay->flip_addr; 328 u32 tmp, *cs; 329 330 drm_WARN_ON(display->drm, !overlay->active); 331 332 if (load_polyphase_filter) 333 flip_addr |= OFC_UPDATE; 334 335 /* check for underruns */ 336 tmp = intel_de_read(display, DOVSTA); 337 if (tmp & (1 << 17)) 338 drm_dbg(display->drm, "overlay underrun, DOVSTA: %x\n", tmp); 339 340 rq = alloc_request(overlay, NULL); 341 if (IS_ERR(rq)) 342 return PTR_ERR(rq); 343 344 cs = intel_ring_begin(rq, 2); 345 if (IS_ERR(cs)) { 346 i915_request_add(rq); 347 return PTR_ERR(cs); 348 } 349 350 *cs++ = MI_OVERLAY_FLIP | MI_OVERLAY_CONTINUE; 351 *cs++ = flip_addr; 352 intel_ring_advance(rq, cs); 353 354 intel_overlay_flip_prepare(overlay, vma); 355 i915_request_add(rq); 356 357 return 0; 358 } 359 360 static void intel_overlay_release_old_vma(struct intel_overlay *overlay) 361 { 362 struct intel_display *display = overlay->display; 363 struct i915_vma *vma; 364 365 vma = fetch_and_zero(&overlay->old_vma); 366 if (drm_WARN_ON(display->drm, !vma)) 367 return; 368 369 intel_frontbuffer_flip_complete(display, INTEL_FRONTBUFFER_OVERLAY(overlay->crtc->pipe)); 370 371 i915_vma_unpin(vma); 372 i915_vma_put(vma); 373 } 374 375 static void 376 intel_overlay_release_old_vid_tail(struct intel_overlay *overlay) 377 { 378 intel_overlay_release_old_vma(overlay); 379 } 380 381 static void intel_overlay_off_tail(struct intel_overlay *overlay) 382 { 383 struct intel_display *display = overlay->display; 384 385 intel_overlay_release_old_vma(overlay); 386 387 overlay->crtc->overlay = NULL; 388 overlay->crtc = NULL; 389 overlay->active = false; 390 391 if (display->platform.i830) 392 i830_overlay_clock_gating(display, true); 393 } 394 395 static void intel_overlay_last_flip_retire(struct i915_active *active) 396 { 397 struct intel_overlay *overlay = 398 container_of(active, typeof(*overlay), last_flip); 399 400 if (overlay->flip_complete) 401 overlay->flip_complete(overlay); 402 } 403 404 /* overlay needs to be disabled in OCMD reg */ 405 static int intel_overlay_off(struct intel_overlay *overlay) 406 { 407 struct intel_display *display = overlay->display; 408 struct i915_request *rq; 409 u32 *cs, flip_addr = overlay->flip_addr; 410 411 drm_WARN_ON(display->drm, !overlay->active); 412 413 /* 414 * According to intel docs the overlay hw may hang (when switching 415 * off) without loading the filter coeffs. It is however unclear whether 416 * this applies to the disabling of the overlay or to the switching off 417 * of the hw. Do it in both cases. 418 */ 419 flip_addr |= OFC_UPDATE; 420 421 rq = alloc_request(overlay, intel_overlay_off_tail); 422 if (IS_ERR(rq)) 423 return PTR_ERR(rq); 424 425 cs = intel_ring_begin(rq, 6); 426 if (IS_ERR(cs)) { 427 i915_request_add(rq); 428 return PTR_ERR(cs); 429 } 430 431 /* wait for overlay to go idle */ 432 *cs++ = MI_OVERLAY_FLIP | MI_OVERLAY_CONTINUE; 433 *cs++ = flip_addr; 434 *cs++ = MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP; 435 436 /* turn overlay off */ 437 *cs++ = MI_OVERLAY_FLIP | MI_OVERLAY_OFF; 438 *cs++ = flip_addr; 439 *cs++ = MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP; 440 441 intel_ring_advance(rq, cs); 442 443 intel_overlay_flip_prepare(overlay, NULL); 444 i915_request_add(rq); 445 446 return i915_active_wait(&overlay->last_flip); 447 } 448 449 /* 450 * Recover from an interruption due to a signal. 451 * We have to be careful not to repeat work forever an make forward progress. 452 */ 453 static int intel_overlay_recover_from_interrupt(struct intel_overlay *overlay) 454 { 455 return i915_active_wait(&overlay->last_flip); 456 } 457 458 /* 459 * Wait for pending overlay flip and release old frame. 460 * Needs to be called before the overlay register are changed 461 * via intel_overlay_(un)map_regs. 462 */ 463 static int intel_overlay_release_old_vid(struct intel_overlay *overlay) 464 { 465 struct intel_display *display = overlay->display; 466 struct i915_request *rq; 467 u32 *cs; 468 469 /* 470 * Only wait if there is actually an old frame to release to 471 * guarantee forward progress. 472 */ 473 if (!overlay->old_vma) 474 return 0; 475 476 if (!(intel_de_read(display, GEN2_ISR) & I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT)) { 477 intel_overlay_release_old_vid_tail(overlay); 478 return 0; 479 } 480 481 rq = alloc_request(overlay, intel_overlay_release_old_vid_tail); 482 if (IS_ERR(rq)) 483 return PTR_ERR(rq); 484 485 cs = intel_ring_begin(rq, 2); 486 if (IS_ERR(cs)) { 487 i915_request_add(rq); 488 return PTR_ERR(cs); 489 } 490 491 *cs++ = MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP; 492 *cs++ = MI_NOOP; 493 intel_ring_advance(rq, cs); 494 495 i915_request_add(rq); 496 497 return i915_active_wait(&overlay->last_flip); 498 } 499 500 void intel_overlay_reset(struct intel_display *display) 501 { 502 struct intel_overlay *overlay = display->overlay; 503 504 if (!overlay) 505 return; 506 507 overlay->old_xscale = 0; 508 overlay->old_yscale = 0; 509 overlay->crtc = NULL; 510 overlay->active = false; 511 } 512 513 static int packed_depth_bytes(u32 format) 514 { 515 switch (format & I915_OVERLAY_DEPTH_MASK) { 516 case I915_OVERLAY_YUV422: 517 return 4; 518 case I915_OVERLAY_YUV411: 519 /* return 6; not implemented */ 520 default: 521 return -EINVAL; 522 } 523 } 524 525 static int packed_width_bytes(u32 format, short width) 526 { 527 switch (format & I915_OVERLAY_DEPTH_MASK) { 528 case I915_OVERLAY_YUV422: 529 return width << 1; 530 default: 531 return -EINVAL; 532 } 533 } 534 535 static int uv_hsubsampling(u32 format) 536 { 537 switch (format & I915_OVERLAY_DEPTH_MASK) { 538 case I915_OVERLAY_YUV422: 539 case I915_OVERLAY_YUV420: 540 return 2; 541 case I915_OVERLAY_YUV411: 542 case I915_OVERLAY_YUV410: 543 return 4; 544 default: 545 return -EINVAL; 546 } 547 } 548 549 static int uv_vsubsampling(u32 format) 550 { 551 switch (format & I915_OVERLAY_DEPTH_MASK) { 552 case I915_OVERLAY_YUV420: 553 case I915_OVERLAY_YUV410: 554 return 2; 555 case I915_OVERLAY_YUV422: 556 case I915_OVERLAY_YUV411: 557 return 1; 558 default: 559 return -EINVAL; 560 } 561 } 562 563 static u32 calc_swidthsw(struct intel_display *display, u32 offset, u32 width) 564 { 565 u32 sw; 566 567 if (DISPLAY_VER(display) == 2) 568 sw = ALIGN((offset & 31) + width, 32); 569 else 570 sw = ALIGN((offset & 63) + width, 64); 571 572 if (sw == 0) 573 return 0; 574 575 return (sw - 32) >> 3; 576 } 577 578 static const u16 y_static_hcoeffs[N_PHASES][N_HORIZ_Y_TAPS] = { 579 [ 0] = { 0x3000, 0xb4a0, 0x1930, 0x1920, 0xb4a0, }, 580 [ 1] = { 0x3000, 0xb500, 0x19d0, 0x1880, 0xb440, }, 581 [ 2] = { 0x3000, 0xb540, 0x1a88, 0x2f80, 0xb3e0, }, 582 [ 3] = { 0x3000, 0xb580, 0x1b30, 0x2e20, 0xb380, }, 583 [ 4] = { 0x3000, 0xb5c0, 0x1bd8, 0x2cc0, 0xb320, }, 584 [ 5] = { 0x3020, 0xb5e0, 0x1c60, 0x2b80, 0xb2c0, }, 585 [ 6] = { 0x3020, 0xb5e0, 0x1cf8, 0x2a20, 0xb260, }, 586 [ 7] = { 0x3020, 0xb5e0, 0x1d80, 0x28e0, 0xb200, }, 587 [ 8] = { 0x3020, 0xb5c0, 0x1e08, 0x3f40, 0xb1c0, }, 588 [ 9] = { 0x3020, 0xb580, 0x1e78, 0x3ce0, 0xb160, }, 589 [10] = { 0x3040, 0xb520, 0x1ed8, 0x3aa0, 0xb120, }, 590 [11] = { 0x3040, 0xb4a0, 0x1f30, 0x3880, 0xb0e0, }, 591 [12] = { 0x3040, 0xb400, 0x1f78, 0x3680, 0xb0a0, }, 592 [13] = { 0x3020, 0xb340, 0x1fb8, 0x34a0, 0xb060, }, 593 [14] = { 0x3020, 0xb240, 0x1fe0, 0x32e0, 0xb040, }, 594 [15] = { 0x3020, 0xb140, 0x1ff8, 0x3160, 0xb020, }, 595 [16] = { 0xb000, 0x3000, 0x0800, 0x3000, 0xb000, }, 596 }; 597 598 static const u16 uv_static_hcoeffs[N_PHASES][N_HORIZ_UV_TAPS] = { 599 [ 0] = { 0x3000, 0x1800, 0x1800, }, 600 [ 1] = { 0xb000, 0x18d0, 0x2e60, }, 601 [ 2] = { 0xb000, 0x1990, 0x2ce0, }, 602 [ 3] = { 0xb020, 0x1a68, 0x2b40, }, 603 [ 4] = { 0xb040, 0x1b20, 0x29e0, }, 604 [ 5] = { 0xb060, 0x1bd8, 0x2880, }, 605 [ 6] = { 0xb080, 0x1c88, 0x3e60, }, 606 [ 7] = { 0xb0a0, 0x1d28, 0x3c00, }, 607 [ 8] = { 0xb0c0, 0x1db8, 0x39e0, }, 608 [ 9] = { 0xb0e0, 0x1e40, 0x37e0, }, 609 [10] = { 0xb100, 0x1eb8, 0x3620, }, 610 [11] = { 0xb100, 0x1f18, 0x34a0, }, 611 [12] = { 0xb100, 0x1f68, 0x3360, }, 612 [13] = { 0xb0e0, 0x1fa8, 0x3240, }, 613 [14] = { 0xb0c0, 0x1fe0, 0x3140, }, 614 [15] = { 0xb060, 0x1ff0, 0x30a0, }, 615 [16] = { 0x3000, 0x0800, 0x3000, }, 616 }; 617 618 static void update_polyphase_filter(struct overlay_registers __iomem *regs) 619 { 620 memcpy_toio(regs->Y_HCOEFS, y_static_hcoeffs, sizeof(y_static_hcoeffs)); 621 memcpy_toio(regs->UV_HCOEFS, uv_static_hcoeffs, 622 sizeof(uv_static_hcoeffs)); 623 } 624 625 static bool update_scaling_factors(struct intel_overlay *overlay, 626 struct overlay_registers __iomem *regs, 627 struct drm_intel_overlay_put_image *params) 628 { 629 /* fixed point with a 12 bit shift */ 630 u32 xscale, yscale, xscale_UV, yscale_UV; 631 #define FP_SHIFT 12 632 #define FRACT_MASK 0xfff 633 bool scale_changed = false; 634 int uv_hscale = uv_hsubsampling(params->flags); 635 int uv_vscale = uv_vsubsampling(params->flags); 636 637 if (params->dst_width > 1) 638 xscale = ((params->src_scan_width - 1) << FP_SHIFT) / 639 params->dst_width; 640 else 641 xscale = 1 << FP_SHIFT; 642 643 if (params->dst_height > 1) 644 yscale = ((params->src_scan_height - 1) << FP_SHIFT) / 645 params->dst_height; 646 else 647 yscale = 1 << FP_SHIFT; 648 649 /*if (params->format & I915_OVERLAY_YUV_PLANAR) {*/ 650 xscale_UV = xscale/uv_hscale; 651 yscale_UV = yscale/uv_vscale; 652 /* make the Y scale to UV scale ratio an exact multiply */ 653 xscale = xscale_UV * uv_hscale; 654 yscale = yscale_UV * uv_vscale; 655 /*} else { 656 xscale_UV = 0; 657 yscale_UV = 0; 658 }*/ 659 660 if (xscale != overlay->old_xscale || yscale != overlay->old_yscale) 661 scale_changed = true; 662 overlay->old_xscale = xscale; 663 overlay->old_yscale = yscale; 664 665 iowrite32(((yscale & FRACT_MASK) << 20) | 666 ((xscale >> FP_SHIFT) << 16) | 667 ((xscale & FRACT_MASK) << 3), 668 ®s->YRGBSCALE); 669 670 iowrite32(((yscale_UV & FRACT_MASK) << 20) | 671 ((xscale_UV >> FP_SHIFT) << 16) | 672 ((xscale_UV & FRACT_MASK) << 3), 673 ®s->UVSCALE); 674 675 iowrite32((((yscale >> FP_SHIFT) << 16) | 676 ((yscale_UV >> FP_SHIFT) << 0)), 677 ®s->UVSCALEV); 678 679 if (scale_changed) 680 update_polyphase_filter(regs); 681 682 return scale_changed; 683 } 684 685 static void update_colorkey(struct intel_overlay *overlay, 686 struct overlay_registers __iomem *regs) 687 { 688 const struct intel_plane_state *state = 689 to_intel_plane_state(overlay->crtc->base.primary->state); 690 u32 key = overlay->color_key; 691 u32 format = 0; 692 u32 flags = 0; 693 694 if (overlay->color_key_enabled) 695 flags |= DST_KEY_ENABLE; 696 697 if (state->uapi.visible) 698 format = state->hw.fb->format->format; 699 700 switch (format) { 701 case DRM_FORMAT_C8: 702 key = RGB8I_TO_COLORKEY(key); 703 flags |= CLK_RGB24_MASK; 704 break; 705 case DRM_FORMAT_XRGB1555: 706 key = RGB15_TO_COLORKEY(key); 707 flags |= CLK_RGB15_MASK; 708 break; 709 case DRM_FORMAT_RGB565: 710 key = RGB16_TO_COLORKEY(key); 711 flags |= CLK_RGB16_MASK; 712 break; 713 case DRM_FORMAT_XRGB2101010: 714 case DRM_FORMAT_XBGR2101010: 715 key = RGB30_TO_COLORKEY(key); 716 flags |= CLK_RGB24_MASK; 717 break; 718 default: 719 flags |= CLK_RGB24_MASK; 720 break; 721 } 722 723 iowrite32(key, ®s->DCLRKV); 724 iowrite32(flags, ®s->DCLRKM); 725 } 726 727 static u32 overlay_cmd_reg(struct drm_intel_overlay_put_image *params) 728 { 729 u32 cmd = OCMD_ENABLE | OCMD_BUF_TYPE_FRAME | OCMD_BUFFER0; 730 731 if (params->flags & I915_OVERLAY_YUV_PLANAR) { 732 switch (params->flags & I915_OVERLAY_DEPTH_MASK) { 733 case I915_OVERLAY_YUV422: 734 cmd |= OCMD_YUV_422_PLANAR; 735 break; 736 case I915_OVERLAY_YUV420: 737 cmd |= OCMD_YUV_420_PLANAR; 738 break; 739 case I915_OVERLAY_YUV411: 740 case I915_OVERLAY_YUV410: 741 cmd |= OCMD_YUV_410_PLANAR; 742 break; 743 } 744 } else { /* YUV packed */ 745 switch (params->flags & I915_OVERLAY_DEPTH_MASK) { 746 case I915_OVERLAY_YUV422: 747 cmd |= OCMD_YUV_422_PACKED; 748 break; 749 case I915_OVERLAY_YUV411: 750 cmd |= OCMD_YUV_411_PACKED; 751 break; 752 } 753 754 switch (params->flags & I915_OVERLAY_SWAP_MASK) { 755 case I915_OVERLAY_NO_SWAP: 756 break; 757 case I915_OVERLAY_UV_SWAP: 758 cmd |= OCMD_UV_SWAP; 759 break; 760 case I915_OVERLAY_Y_SWAP: 761 cmd |= OCMD_Y_SWAP; 762 break; 763 case I915_OVERLAY_Y_AND_UV_SWAP: 764 cmd |= OCMD_Y_AND_UV_SWAP; 765 break; 766 } 767 } 768 769 return cmd; 770 } 771 772 static struct i915_vma *intel_overlay_pin_fb(struct drm_i915_gem_object *new_bo) 773 { 774 struct i915_gem_ww_ctx ww; 775 struct i915_vma *vma; 776 int ret; 777 778 i915_gem_ww_ctx_init(&ww, true); 779 retry: 780 ret = i915_gem_object_lock(new_bo, &ww); 781 if (!ret) { 782 vma = i915_gem_object_pin_to_display_plane(new_bo, &ww, 0, 0, 783 NULL, PIN_MAPPABLE); 784 ret = PTR_ERR_OR_ZERO(vma); 785 } 786 if (ret == -EDEADLK) { 787 ret = i915_gem_ww_ctx_backoff(&ww); 788 if (!ret) 789 goto retry; 790 } 791 i915_gem_ww_ctx_fini(&ww); 792 if (ret) 793 return ERR_PTR(ret); 794 795 return vma; 796 } 797 798 static int intel_overlay_do_put_image(struct intel_overlay *overlay, 799 struct drm_i915_gem_object *new_bo, 800 struct drm_intel_overlay_put_image *params) 801 { 802 struct intel_display *display = overlay->display; 803 struct overlay_registers __iomem *regs = overlay->regs; 804 u32 swidth, swidthsw, sheight, ostride; 805 enum pipe pipe = overlay->crtc->pipe; 806 bool scale_changed = false; 807 struct i915_vma *vma; 808 int ret, tmp_width; 809 810 drm_WARN_ON(display->drm, 811 !drm_modeset_is_locked(&display->drm->mode_config.connection_mutex)); 812 813 ret = intel_overlay_release_old_vid(overlay); 814 if (ret != 0) 815 return ret; 816 817 atomic_inc(&display->restore.pending_fb_pin); 818 819 vma = intel_overlay_pin_fb(new_bo); 820 if (IS_ERR(vma)) { 821 ret = PTR_ERR(vma); 822 goto out_pin_section; 823 } 824 825 i915_gem_object_flush_frontbuffer(new_bo, ORIGIN_DIRTYFB); 826 827 if (!overlay->active) { 828 const struct intel_crtc_state *crtc_state = 829 overlay->crtc->config; 830 u32 oconfig = 0; 831 832 if (crtc_state->gamma_enable && 833 crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT) 834 oconfig |= OCONF_CC_OUT_8BIT; 835 if (crtc_state->gamma_enable) 836 oconfig |= OCONF_GAMMA2_ENABLE; 837 if (DISPLAY_VER(display) == 4) 838 oconfig |= OCONF_CSC_MODE_BT709; 839 oconfig |= pipe == 0 ? 840 OCONF_PIPE_A : OCONF_PIPE_B; 841 iowrite32(oconfig, ®s->OCONFIG); 842 843 ret = intel_overlay_on(overlay); 844 if (ret != 0) 845 goto out_unpin; 846 } 847 848 iowrite32(params->dst_y << 16 | params->dst_x, ®s->DWINPOS); 849 iowrite32(params->dst_height << 16 | params->dst_width, ®s->DWINSZ); 850 851 if (params->flags & I915_OVERLAY_YUV_PACKED) 852 tmp_width = packed_width_bytes(params->flags, 853 params->src_width); 854 else 855 tmp_width = params->src_width; 856 857 swidth = params->src_width; 858 swidthsw = calc_swidthsw(display, params->offset_Y, tmp_width); 859 sheight = params->src_height; 860 iowrite32(i915_ggtt_offset(vma) + params->offset_Y, ®s->OBUF_0Y); 861 ostride = params->stride_Y; 862 863 if (params->flags & I915_OVERLAY_YUV_PLANAR) { 864 int uv_hscale = uv_hsubsampling(params->flags); 865 int uv_vscale = uv_vsubsampling(params->flags); 866 u32 tmp_U, tmp_V; 867 868 swidth |= (params->src_width / uv_hscale) << 16; 869 sheight |= (params->src_height / uv_vscale) << 16; 870 871 tmp_U = calc_swidthsw(display, params->offset_U, 872 params->src_width / uv_hscale); 873 tmp_V = calc_swidthsw(display, params->offset_V, 874 params->src_width / uv_hscale); 875 swidthsw |= max(tmp_U, tmp_V) << 16; 876 877 iowrite32(i915_ggtt_offset(vma) + params->offset_U, 878 ®s->OBUF_0U); 879 iowrite32(i915_ggtt_offset(vma) + params->offset_V, 880 ®s->OBUF_0V); 881 882 ostride |= params->stride_UV << 16; 883 } 884 885 iowrite32(swidth, ®s->SWIDTH); 886 iowrite32(swidthsw, ®s->SWIDTHSW); 887 iowrite32(sheight, ®s->SHEIGHT); 888 iowrite32(ostride, ®s->OSTRIDE); 889 890 scale_changed = update_scaling_factors(overlay, regs, params); 891 892 update_colorkey(overlay, regs); 893 894 iowrite32(overlay_cmd_reg(params), ®s->OCMD); 895 896 ret = intel_overlay_continue(overlay, vma, scale_changed); 897 if (ret) 898 goto out_unpin; 899 900 return 0; 901 902 out_unpin: 903 i915_vma_unpin(vma); 904 out_pin_section: 905 atomic_dec(&display->restore.pending_fb_pin); 906 907 return ret; 908 } 909 910 int intel_overlay_switch_off(struct intel_overlay *overlay) 911 { 912 struct intel_display *display = overlay->display; 913 int ret; 914 915 drm_WARN_ON(display->drm, 916 !drm_modeset_is_locked(&display->drm->mode_config.connection_mutex)); 917 918 ret = intel_overlay_recover_from_interrupt(overlay); 919 if (ret != 0) 920 return ret; 921 922 if (!overlay->active) 923 return 0; 924 925 ret = intel_overlay_release_old_vid(overlay); 926 if (ret != 0) 927 return ret; 928 929 iowrite32(0, &overlay->regs->OCMD); 930 931 return intel_overlay_off(overlay); 932 } 933 934 static int check_overlay_possible_on_crtc(struct intel_overlay *overlay, 935 struct intel_crtc *crtc) 936 { 937 if (!crtc->active) 938 return -EINVAL; 939 940 /* can't use the overlay with double wide pipe */ 941 if (crtc->config->double_wide) 942 return -EINVAL; 943 944 return 0; 945 } 946 947 static void update_pfit_vscale_ratio(struct intel_overlay *overlay) 948 { 949 struct intel_display *display = overlay->display; 950 u32 ratio; 951 952 /* XXX: This is not the same logic as in the xorg driver, but more in 953 * line with the intel documentation for the i965 954 */ 955 if (DISPLAY_VER(display) >= 4) { 956 u32 tmp = intel_de_read(display, PFIT_PGM_RATIOS(display)); 957 958 /* on i965 use the PGM reg to read out the autoscaler values */ 959 ratio = REG_FIELD_GET(PFIT_VERT_SCALE_MASK_965, tmp); 960 } else { 961 u32 tmp; 962 963 if (intel_de_read(display, PFIT_CONTROL(display)) & PFIT_VERT_AUTO_SCALE) 964 tmp = intel_de_read(display, PFIT_AUTO_RATIOS(display)); 965 else 966 tmp = intel_de_read(display, PFIT_PGM_RATIOS(display)); 967 968 ratio = REG_FIELD_GET(PFIT_VERT_SCALE_MASK, tmp); 969 } 970 971 overlay->pfit_vscale_ratio = ratio; 972 } 973 974 static int check_overlay_dst(struct intel_overlay *overlay, 975 struct drm_intel_overlay_put_image *rec) 976 { 977 const struct intel_crtc_state *crtc_state = 978 overlay->crtc->config; 979 struct drm_rect req, clipped; 980 981 drm_rect_init(&req, rec->dst_x, rec->dst_y, 982 rec->dst_width, rec->dst_height); 983 984 clipped = req; 985 986 if (!drm_rect_intersect(&clipped, &crtc_state->pipe_src)) 987 return -EINVAL; 988 989 if (!drm_rect_equals(&clipped, &req)) 990 return -EINVAL; 991 992 return 0; 993 } 994 995 static int check_overlay_scaling(struct drm_intel_overlay_put_image *rec) 996 { 997 u32 tmp; 998 999 /* downscaling limit is 8.0 */ 1000 tmp = ((rec->src_scan_height << 16) / rec->dst_height) >> 16; 1001 if (tmp > 7) 1002 return -EINVAL; 1003 1004 tmp = ((rec->src_scan_width << 16) / rec->dst_width) >> 16; 1005 if (tmp > 7) 1006 return -EINVAL; 1007 1008 return 0; 1009 } 1010 1011 static int check_overlay_src(struct intel_display *display, 1012 struct drm_intel_overlay_put_image *rec, 1013 struct drm_i915_gem_object *new_bo) 1014 { 1015 int uv_hscale = uv_hsubsampling(rec->flags); 1016 int uv_vscale = uv_vsubsampling(rec->flags); 1017 u32 stride_mask; 1018 int depth; 1019 u32 tmp; 1020 1021 /* check src dimensions */ 1022 if (display->platform.i845g || display->platform.i830) { 1023 if (rec->src_height > IMAGE_MAX_HEIGHT_LEGACY || 1024 rec->src_width > IMAGE_MAX_WIDTH_LEGACY) 1025 return -EINVAL; 1026 } else { 1027 if (rec->src_height > IMAGE_MAX_HEIGHT || 1028 rec->src_width > IMAGE_MAX_WIDTH) 1029 return -EINVAL; 1030 } 1031 1032 /* better safe than sorry, use 4 as the maximal subsampling ratio */ 1033 if (rec->src_height < N_VERT_Y_TAPS*4 || 1034 rec->src_width < N_HORIZ_Y_TAPS*4) 1035 return -EINVAL; 1036 1037 /* check alignment constraints */ 1038 switch (rec->flags & I915_OVERLAY_TYPE_MASK) { 1039 case I915_OVERLAY_RGB: 1040 /* not implemented */ 1041 return -EINVAL; 1042 1043 case I915_OVERLAY_YUV_PACKED: 1044 if (uv_vscale != 1) 1045 return -EINVAL; 1046 1047 depth = packed_depth_bytes(rec->flags); 1048 if (depth < 0) 1049 return depth; 1050 1051 /* ignore UV planes */ 1052 rec->stride_UV = 0; 1053 rec->offset_U = 0; 1054 rec->offset_V = 0; 1055 /* check pixel alignment */ 1056 if (rec->offset_Y % depth) 1057 return -EINVAL; 1058 break; 1059 1060 case I915_OVERLAY_YUV_PLANAR: 1061 if (uv_vscale < 0 || uv_hscale < 0) 1062 return -EINVAL; 1063 /* no offset restrictions for planar formats */ 1064 break; 1065 1066 default: 1067 return -EINVAL; 1068 } 1069 1070 if (rec->src_width % uv_hscale) 1071 return -EINVAL; 1072 1073 /* stride checking */ 1074 if (display->platform.i830 || display->platform.i845g) 1075 stride_mask = 255; 1076 else 1077 stride_mask = 63; 1078 1079 if (rec->stride_Y & stride_mask || rec->stride_UV & stride_mask) 1080 return -EINVAL; 1081 if (DISPLAY_VER(display) == 4 && rec->stride_Y < 512) 1082 return -EINVAL; 1083 1084 tmp = (rec->flags & I915_OVERLAY_TYPE_MASK) == I915_OVERLAY_YUV_PLANAR ? 1085 4096 : 8192; 1086 if (rec->stride_Y > tmp || rec->stride_UV > 2*1024) 1087 return -EINVAL; 1088 1089 /* check buffer dimensions */ 1090 switch (rec->flags & I915_OVERLAY_TYPE_MASK) { 1091 case I915_OVERLAY_RGB: 1092 case I915_OVERLAY_YUV_PACKED: 1093 /* always 4 Y values per depth pixels */ 1094 if (packed_width_bytes(rec->flags, rec->src_width) > rec->stride_Y) 1095 return -EINVAL; 1096 1097 tmp = rec->stride_Y*rec->src_height; 1098 if (rec->offset_Y + tmp > new_bo->base.size) 1099 return -EINVAL; 1100 break; 1101 1102 case I915_OVERLAY_YUV_PLANAR: 1103 if (rec->src_width > rec->stride_Y) 1104 return -EINVAL; 1105 if (rec->src_width/uv_hscale > rec->stride_UV) 1106 return -EINVAL; 1107 1108 tmp = rec->stride_Y * rec->src_height; 1109 if (rec->offset_Y + tmp > new_bo->base.size) 1110 return -EINVAL; 1111 1112 tmp = rec->stride_UV * (rec->src_height / uv_vscale); 1113 if (rec->offset_U + tmp > new_bo->base.size || 1114 rec->offset_V + tmp > new_bo->base.size) 1115 return -EINVAL; 1116 break; 1117 } 1118 1119 return 0; 1120 } 1121 1122 int intel_overlay_put_image_ioctl(struct drm_device *dev, void *data, 1123 struct drm_file *file_priv) 1124 { 1125 struct intel_display *display = to_intel_display(dev); 1126 struct drm_intel_overlay_put_image *params = data; 1127 struct intel_overlay *overlay; 1128 struct drm_crtc *drmmode_crtc; 1129 struct intel_crtc *crtc; 1130 struct drm_i915_gem_object *new_bo; 1131 int ret; 1132 1133 overlay = display->overlay; 1134 if (!overlay) { 1135 drm_dbg(display->drm, "userspace bug: no overlay\n"); 1136 return -ENODEV; 1137 } 1138 1139 if (!(params->flags & I915_OVERLAY_ENABLE)) { 1140 drm_modeset_lock_all(dev); 1141 ret = intel_overlay_switch_off(overlay); 1142 drm_modeset_unlock_all(dev); 1143 1144 return ret; 1145 } 1146 1147 drmmode_crtc = drm_crtc_find(dev, file_priv, params->crtc_id); 1148 if (!drmmode_crtc) 1149 return -ENOENT; 1150 crtc = to_intel_crtc(drmmode_crtc); 1151 1152 new_bo = i915_gem_object_lookup(file_priv, params->bo_handle); 1153 if (!new_bo) 1154 return -ENOENT; 1155 1156 drm_modeset_lock_all(dev); 1157 1158 if (i915_gem_object_is_tiled(new_bo)) { 1159 drm_dbg_kms(display->drm, 1160 "buffer used for overlay image can not be tiled\n"); 1161 ret = -EINVAL; 1162 goto out_unlock; 1163 } 1164 1165 ret = intel_overlay_recover_from_interrupt(overlay); 1166 if (ret != 0) 1167 goto out_unlock; 1168 1169 if (overlay->crtc != crtc) { 1170 ret = intel_overlay_switch_off(overlay); 1171 if (ret != 0) 1172 goto out_unlock; 1173 1174 ret = check_overlay_possible_on_crtc(overlay, crtc); 1175 if (ret != 0) 1176 goto out_unlock; 1177 1178 overlay->crtc = crtc; 1179 crtc->overlay = overlay; 1180 1181 /* line too wide, i.e. one-line-mode */ 1182 if (drm_rect_width(&crtc->config->pipe_src) > 1024 && 1183 crtc->config->gmch_pfit.control & PFIT_ENABLE) { 1184 overlay->pfit_active = true; 1185 update_pfit_vscale_ratio(overlay); 1186 } else 1187 overlay->pfit_active = false; 1188 } 1189 1190 ret = check_overlay_dst(overlay, params); 1191 if (ret != 0) 1192 goto out_unlock; 1193 1194 if (overlay->pfit_active) { 1195 params->dst_y = (((u32)params->dst_y << 12) / 1196 overlay->pfit_vscale_ratio); 1197 /* shifting right rounds downwards, so add 1 */ 1198 params->dst_height = (((u32)params->dst_height << 12) / 1199 overlay->pfit_vscale_ratio) + 1; 1200 } 1201 1202 if (params->src_scan_height > params->src_height || 1203 params->src_scan_width > params->src_width) { 1204 ret = -EINVAL; 1205 goto out_unlock; 1206 } 1207 1208 ret = check_overlay_src(display, params, new_bo); 1209 if (ret != 0) 1210 goto out_unlock; 1211 1212 /* Check scaling after src size to prevent a divide-by-zero. */ 1213 ret = check_overlay_scaling(params); 1214 if (ret != 0) 1215 goto out_unlock; 1216 1217 ret = intel_overlay_do_put_image(overlay, new_bo, params); 1218 if (ret != 0) 1219 goto out_unlock; 1220 1221 drm_modeset_unlock_all(dev); 1222 i915_gem_object_put(new_bo); 1223 1224 return 0; 1225 1226 out_unlock: 1227 drm_modeset_unlock_all(dev); 1228 i915_gem_object_put(new_bo); 1229 1230 return ret; 1231 } 1232 1233 static void update_reg_attrs(struct intel_overlay *overlay, 1234 struct overlay_registers __iomem *regs) 1235 { 1236 iowrite32((overlay->contrast << 18) | (overlay->brightness & 0xff), 1237 ®s->OCLRC0); 1238 iowrite32(overlay->saturation, ®s->OCLRC1); 1239 } 1240 1241 static bool check_gamma_bounds(u32 gamma1, u32 gamma2) 1242 { 1243 int i; 1244 1245 if (gamma1 & 0xff000000 || gamma2 & 0xff000000) 1246 return false; 1247 1248 for (i = 0; i < 3; i++) { 1249 if (((gamma1 >> i*8) & 0xff) >= ((gamma2 >> i*8) & 0xff)) 1250 return false; 1251 } 1252 1253 return true; 1254 } 1255 1256 static bool check_gamma5_errata(u32 gamma5) 1257 { 1258 int i; 1259 1260 for (i = 0; i < 3; i++) { 1261 if (((gamma5 >> i*8) & 0xff) == 0x80) 1262 return false; 1263 } 1264 1265 return true; 1266 } 1267 1268 static int check_gamma(struct drm_intel_overlay_attrs *attrs) 1269 { 1270 if (!check_gamma_bounds(0, attrs->gamma0) || 1271 !check_gamma_bounds(attrs->gamma0, attrs->gamma1) || 1272 !check_gamma_bounds(attrs->gamma1, attrs->gamma2) || 1273 !check_gamma_bounds(attrs->gamma2, attrs->gamma3) || 1274 !check_gamma_bounds(attrs->gamma3, attrs->gamma4) || 1275 !check_gamma_bounds(attrs->gamma4, attrs->gamma5) || 1276 !check_gamma_bounds(attrs->gamma5, 0x00ffffff)) 1277 return -EINVAL; 1278 1279 if (!check_gamma5_errata(attrs->gamma5)) 1280 return -EINVAL; 1281 1282 return 0; 1283 } 1284 1285 int intel_overlay_attrs_ioctl(struct drm_device *dev, void *data, 1286 struct drm_file *file_priv) 1287 { 1288 struct intel_display *display = to_intel_display(dev); 1289 struct drm_intel_overlay_attrs *attrs = data; 1290 struct intel_overlay *overlay; 1291 int ret; 1292 1293 overlay = display->overlay; 1294 if (!overlay) { 1295 drm_dbg(display->drm, "userspace bug: no overlay\n"); 1296 return -ENODEV; 1297 } 1298 1299 drm_modeset_lock_all(dev); 1300 1301 ret = -EINVAL; 1302 if (!(attrs->flags & I915_OVERLAY_UPDATE_ATTRS)) { 1303 attrs->color_key = overlay->color_key; 1304 attrs->brightness = overlay->brightness; 1305 attrs->contrast = overlay->contrast; 1306 attrs->saturation = overlay->saturation; 1307 1308 if (DISPLAY_VER(display) != 2) { 1309 attrs->gamma0 = intel_de_read(display, OGAMC0); 1310 attrs->gamma1 = intel_de_read(display, OGAMC1); 1311 attrs->gamma2 = intel_de_read(display, OGAMC2); 1312 attrs->gamma3 = intel_de_read(display, OGAMC3); 1313 attrs->gamma4 = intel_de_read(display, OGAMC4); 1314 attrs->gamma5 = intel_de_read(display, OGAMC5); 1315 } 1316 } else { 1317 if (attrs->brightness < -128 || attrs->brightness > 127) 1318 goto out_unlock; 1319 if (attrs->contrast > 255) 1320 goto out_unlock; 1321 if (attrs->saturation > 1023) 1322 goto out_unlock; 1323 1324 overlay->color_key = attrs->color_key; 1325 overlay->brightness = attrs->brightness; 1326 overlay->contrast = attrs->contrast; 1327 overlay->saturation = attrs->saturation; 1328 1329 update_reg_attrs(overlay, overlay->regs); 1330 1331 if (attrs->flags & I915_OVERLAY_UPDATE_GAMMA) { 1332 if (DISPLAY_VER(display) == 2) 1333 goto out_unlock; 1334 1335 if (overlay->active) { 1336 ret = -EBUSY; 1337 goto out_unlock; 1338 } 1339 1340 ret = check_gamma(attrs); 1341 if (ret) 1342 goto out_unlock; 1343 1344 intel_de_write(display, OGAMC0, attrs->gamma0); 1345 intel_de_write(display, OGAMC1, attrs->gamma1); 1346 intel_de_write(display, OGAMC2, attrs->gamma2); 1347 intel_de_write(display, OGAMC3, attrs->gamma3); 1348 intel_de_write(display, OGAMC4, attrs->gamma4); 1349 intel_de_write(display, OGAMC5, attrs->gamma5); 1350 } 1351 } 1352 overlay->color_key_enabled = (attrs->flags & I915_OVERLAY_DISABLE_DEST_COLORKEY) == 0; 1353 1354 ret = 0; 1355 out_unlock: 1356 drm_modeset_unlock_all(dev); 1357 1358 return ret; 1359 } 1360 1361 static int get_registers(struct intel_overlay *overlay, bool use_phys) 1362 { 1363 struct intel_display *display = overlay->display; 1364 struct drm_i915_private *i915 = to_i915(display->drm); 1365 struct drm_i915_gem_object *obj = ERR_PTR(-ENODEV); 1366 struct i915_vma *vma; 1367 int err; 1368 1369 if (!display->platform.meteorlake) /* Wa_22018444074 */ 1370 obj = i915_gem_object_create_stolen(i915, PAGE_SIZE); 1371 if (IS_ERR(obj)) 1372 obj = i915_gem_object_create_internal(i915, PAGE_SIZE); 1373 if (IS_ERR(obj)) 1374 return PTR_ERR(obj); 1375 1376 vma = i915_gem_object_ggtt_pin(obj, NULL, 0, 0, PIN_MAPPABLE); 1377 if (IS_ERR(vma)) { 1378 err = PTR_ERR(vma); 1379 goto err_put_bo; 1380 } 1381 1382 if (use_phys) 1383 overlay->flip_addr = sg_dma_address(obj->mm.pages->sgl); 1384 else 1385 overlay->flip_addr = i915_ggtt_offset(vma); 1386 overlay->regs = i915_vma_pin_iomap(vma); 1387 i915_vma_unpin(vma); 1388 1389 if (IS_ERR(overlay->regs)) { 1390 err = PTR_ERR(overlay->regs); 1391 goto err_put_bo; 1392 } 1393 1394 overlay->reg_bo = obj; 1395 return 0; 1396 1397 err_put_bo: 1398 i915_gem_object_put(obj); 1399 return err; 1400 } 1401 1402 void intel_overlay_setup(struct intel_display *display) 1403 { 1404 struct drm_i915_private *dev_priv = to_i915(display->drm); 1405 struct intel_overlay *overlay; 1406 struct intel_engine_cs *engine; 1407 int ret; 1408 1409 if (!HAS_OVERLAY(display)) 1410 return; 1411 1412 engine = to_gt(dev_priv)->engine[RCS0]; 1413 if (!engine || !engine->kernel_context) 1414 return; 1415 1416 overlay = kzalloc(sizeof(*overlay), GFP_KERNEL); 1417 if (!overlay) 1418 return; 1419 1420 overlay->display = display; 1421 overlay->context = engine->kernel_context; 1422 overlay->color_key = 0x0101fe; 1423 overlay->color_key_enabled = true; 1424 overlay->brightness = -19; 1425 overlay->contrast = 75; 1426 overlay->saturation = 146; 1427 1428 i915_active_init(&overlay->last_flip, 1429 NULL, intel_overlay_last_flip_retire, 0); 1430 1431 ret = get_registers(overlay, OVERLAY_NEEDS_PHYSICAL(display)); 1432 if (ret) 1433 goto out_free; 1434 1435 memset_io(overlay->regs, 0, sizeof(struct overlay_registers)); 1436 update_polyphase_filter(overlay->regs); 1437 update_reg_attrs(overlay, overlay->regs); 1438 1439 display->overlay = overlay; 1440 drm_info(display->drm, "Initialized overlay support.\n"); 1441 return; 1442 1443 out_free: 1444 kfree(overlay); 1445 } 1446 1447 bool intel_overlay_available(struct intel_display *display) 1448 { 1449 return display->overlay; 1450 } 1451 1452 void intel_overlay_cleanup(struct intel_display *display) 1453 { 1454 struct intel_overlay *overlay; 1455 1456 overlay = fetch_and_zero(&display->overlay); 1457 if (!overlay) 1458 return; 1459 1460 /* 1461 * The bo's should be free'd by the generic code already. 1462 * Furthermore modesetting teardown happens beforehand so the 1463 * hardware should be off already. 1464 */ 1465 drm_WARN_ON(display->drm, overlay->active); 1466 1467 i915_gem_object_put(overlay->reg_bo); 1468 i915_active_fini(&overlay->last_flip); 1469 1470 kfree(overlay); 1471 } 1472 1473 #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR) 1474 1475 struct intel_overlay_snapshot { 1476 struct overlay_registers regs; 1477 unsigned long base; 1478 u32 dovsta; 1479 u32 isr; 1480 }; 1481 1482 struct intel_overlay_snapshot * 1483 intel_overlay_snapshot_capture(struct intel_display *display) 1484 { 1485 struct intel_overlay *overlay = display->overlay; 1486 struct intel_overlay_snapshot *error; 1487 1488 if (!overlay || !overlay->active) 1489 return NULL; 1490 1491 error = kmalloc(sizeof(*error), GFP_ATOMIC); 1492 if (error == NULL) 1493 return NULL; 1494 1495 error->dovsta = intel_de_read(display, DOVSTA); 1496 error->isr = intel_de_read(display, GEN2_ISR); 1497 error->base = overlay->flip_addr; 1498 1499 memcpy_fromio(&error->regs, overlay->regs, sizeof(error->regs)); 1500 1501 return error; 1502 } 1503 1504 void 1505 intel_overlay_snapshot_print(const struct intel_overlay_snapshot *error, 1506 struct drm_printer *p) 1507 { 1508 if (!error) 1509 return; 1510 1511 drm_printf(p, "Overlay, status: 0x%08x, interrupt: 0x%08x\n", 1512 error->dovsta, error->isr); 1513 drm_printf(p, " Register file at 0x%08lx:\n", error->base); 1514 1515 #define P(x) drm_printf(p, " " #x ": 0x%08x\n", error->regs.x) 1516 P(OBUF_0Y); 1517 P(OBUF_1Y); 1518 P(OBUF_0U); 1519 P(OBUF_0V); 1520 P(OBUF_1U); 1521 P(OBUF_1V); 1522 P(OSTRIDE); 1523 P(YRGB_VPH); 1524 P(UV_VPH); 1525 P(HORZ_PH); 1526 P(INIT_PHS); 1527 P(DWINPOS); 1528 P(DWINSZ); 1529 P(SWIDTH); 1530 P(SWIDTHSW); 1531 P(SHEIGHT); 1532 P(YRGBSCALE); 1533 P(UVSCALE); 1534 P(OCLRC0); 1535 P(OCLRC1); 1536 P(DCLRKV); 1537 P(DCLRKM); 1538 P(SCLRKVH); 1539 P(SCLRKVL); 1540 P(SCLRKEN); 1541 P(OCONFIG); 1542 P(OCMD); 1543 P(OSTART_0Y); 1544 P(OSTART_1Y); 1545 P(OSTART_0U); 1546 P(OSTART_0V); 1547 P(OSTART_1U); 1548 P(OSTART_1V); 1549 P(OTILEOFF_0Y); 1550 P(OTILEOFF_1Y); 1551 P(OTILEOFF_0U); 1552 P(OTILEOFF_0V); 1553 P(OTILEOFF_1U); 1554 P(OTILEOFF_1V); 1555 P(FASTHSCALE); 1556 P(UVSCALEV); 1557 #undef P 1558 } 1559 1560 #endif 1561