1 /* 2 * Copyright © 2009 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 * SOFTWARE. 22 * 23 * Authors: 24 * Daniel Vetter <daniel@ffwll.ch> 25 * 26 * Derived from Xorg ddx, xf86-video-intel, src/i830_video.c 27 */ 28 29 #include <drm/drm_fourcc.h> 30 #include <drm/i915_drm.h> 31 32 #include "gem/i915_gem_pm.h" 33 #include "gt/intel_ring.h" 34 35 #include "i915_drv.h" 36 #include "i915_reg.h" 37 #include "intel_display_types.h" 38 #include "intel_frontbuffer.h" 39 #include "intel_overlay.h" 40 41 /* Limits for overlay size. According to intel doc, the real limits are: 42 * Y width: 4095, UV width (planar): 2047, Y height: 2047, 43 * UV width (planar): * 1023. But the xorg thinks 2048 for height and width. Use 44 * the mininum of both. */ 45 #define IMAGE_MAX_WIDTH 2048 46 #define IMAGE_MAX_HEIGHT 2046 /* 2 * 1023 */ 47 /* on 830 and 845 these large limits result in the card hanging */ 48 #define IMAGE_MAX_WIDTH_LEGACY 1024 49 #define IMAGE_MAX_HEIGHT_LEGACY 1088 50 51 /* overlay register definitions */ 52 /* OCMD register */ 53 #define OCMD_TILED_SURFACE (0x1<<19) 54 #define OCMD_MIRROR_MASK (0x3<<17) 55 #define OCMD_MIRROR_MODE (0x3<<17) 56 #define OCMD_MIRROR_HORIZONTAL (0x1<<17) 57 #define OCMD_MIRROR_VERTICAL (0x2<<17) 58 #define OCMD_MIRROR_BOTH (0x3<<17) 59 #define OCMD_BYTEORDER_MASK (0x3<<14) /* zero for YUYV or FOURCC YUY2 */ 60 #define OCMD_UV_SWAP (0x1<<14) /* YVYU */ 61 #define OCMD_Y_SWAP (0x2<<14) /* UYVY or FOURCC UYVY */ 62 #define OCMD_Y_AND_UV_SWAP (0x3<<14) /* VYUY */ 63 #define OCMD_SOURCE_FORMAT_MASK (0xf<<10) 64 #define OCMD_RGB_888 (0x1<<10) /* not in i965 Intel docs */ 65 #define OCMD_RGB_555 (0x2<<10) /* not in i965 Intel docs */ 66 #define OCMD_RGB_565 (0x3<<10) /* not in i965 Intel docs */ 67 #define OCMD_YUV_422_PACKED (0x8<<10) 68 #define OCMD_YUV_411_PACKED (0x9<<10) /* not in i965 Intel docs */ 69 #define OCMD_YUV_420_PLANAR (0xc<<10) 70 #define OCMD_YUV_422_PLANAR (0xd<<10) 71 #define OCMD_YUV_410_PLANAR (0xe<<10) /* also 411 */ 72 #define OCMD_TVSYNCFLIP_PARITY (0x1<<9) 73 #define OCMD_TVSYNCFLIP_ENABLE (0x1<<7) 74 #define OCMD_BUF_TYPE_MASK (0x1<<5) 75 #define OCMD_BUF_TYPE_FRAME (0x0<<5) 76 #define OCMD_BUF_TYPE_FIELD (0x1<<5) 77 #define OCMD_TEST_MODE (0x1<<4) 78 #define OCMD_BUFFER_SELECT (0x3<<2) 79 #define OCMD_BUFFER0 (0x0<<2) 80 #define OCMD_BUFFER1 (0x1<<2) 81 #define OCMD_FIELD_SELECT (0x1<<2) 82 #define OCMD_FIELD0 (0x0<<1) 83 #define OCMD_FIELD1 (0x1<<1) 84 #define OCMD_ENABLE (0x1<<0) 85 86 /* OCONFIG register */ 87 #define OCONF_PIPE_MASK (0x1<<18) 88 #define OCONF_PIPE_A (0x0<<18) 89 #define OCONF_PIPE_B (0x1<<18) 90 #define OCONF_GAMMA2_ENABLE (0x1<<16) 91 #define OCONF_CSC_MODE_BT601 (0x0<<5) 92 #define OCONF_CSC_MODE_BT709 (0x1<<5) 93 #define OCONF_CSC_BYPASS (0x1<<4) 94 #define OCONF_CC_OUT_8BIT (0x1<<3) 95 #define OCONF_TEST_MODE (0x1<<2) 96 #define OCONF_THREE_LINE_BUFFER (0x1<<0) 97 #define OCONF_TWO_LINE_BUFFER (0x0<<0) 98 99 /* DCLRKM (dst-key) register */ 100 #define DST_KEY_ENABLE (0x1<<31) 101 #define CLK_RGB24_MASK 0x0 102 #define CLK_RGB16_MASK 0x070307 103 #define CLK_RGB15_MASK 0x070707 104 #define CLK_RGB8I_MASK 0xffffff 105 106 #define RGB16_TO_COLORKEY(c) \ 107 (((c & 0xF800) << 8) | ((c & 0x07E0) << 5) | ((c & 0x001F) << 3)) 108 #define RGB15_TO_COLORKEY(c) \ 109 (((c & 0x7c00) << 9) | ((c & 0x03E0) << 6) | ((c & 0x001F) << 3)) 110 111 /* overlay flip addr flag */ 112 #define OFC_UPDATE 0x1 113 114 /* polyphase filter coefficients */ 115 #define N_HORIZ_Y_TAPS 5 116 #define N_VERT_Y_TAPS 3 117 #define N_HORIZ_UV_TAPS 3 118 #define N_VERT_UV_TAPS 3 119 #define N_PHASES 17 120 #define MAX_TAPS 5 121 122 /* memory bufferd overlay registers */ 123 struct overlay_registers { 124 u32 OBUF_0Y; 125 u32 OBUF_1Y; 126 u32 OBUF_0U; 127 u32 OBUF_0V; 128 u32 OBUF_1U; 129 u32 OBUF_1V; 130 u32 OSTRIDE; 131 u32 YRGB_VPH; 132 u32 UV_VPH; 133 u32 HORZ_PH; 134 u32 INIT_PHS; 135 u32 DWINPOS; 136 u32 DWINSZ; 137 u32 SWIDTH; 138 u32 SWIDTHSW; 139 u32 SHEIGHT; 140 u32 YRGBSCALE; 141 u32 UVSCALE; 142 u32 OCLRC0; 143 u32 OCLRC1; 144 u32 DCLRKV; 145 u32 DCLRKM; 146 u32 SCLRKVH; 147 u32 SCLRKVL; 148 u32 SCLRKEN; 149 u32 OCONFIG; 150 u32 OCMD; 151 u32 RESERVED1; /* 0x6C */ 152 u32 OSTART_0Y; 153 u32 OSTART_1Y; 154 u32 OSTART_0U; 155 u32 OSTART_0V; 156 u32 OSTART_1U; 157 u32 OSTART_1V; 158 u32 OTILEOFF_0Y; 159 u32 OTILEOFF_1Y; 160 u32 OTILEOFF_0U; 161 u32 OTILEOFF_0V; 162 u32 OTILEOFF_1U; 163 u32 OTILEOFF_1V; 164 u32 FASTHSCALE; /* 0xA0 */ 165 u32 UVSCALEV; /* 0xA4 */ 166 u32 RESERVEDC[(0x200 - 0xA8) / 4]; /* 0xA8 - 0x1FC */ 167 u16 Y_VCOEFS[N_VERT_Y_TAPS * N_PHASES]; /* 0x200 */ 168 u16 RESERVEDD[0x100 / 2 - N_VERT_Y_TAPS * N_PHASES]; 169 u16 Y_HCOEFS[N_HORIZ_Y_TAPS * N_PHASES]; /* 0x300 */ 170 u16 RESERVEDE[0x200 / 2 - N_HORIZ_Y_TAPS * N_PHASES]; 171 u16 UV_VCOEFS[N_VERT_UV_TAPS * N_PHASES]; /* 0x500 */ 172 u16 RESERVEDF[0x100 / 2 - N_VERT_UV_TAPS * N_PHASES]; 173 u16 UV_HCOEFS[N_HORIZ_UV_TAPS * N_PHASES]; /* 0x600 */ 174 u16 RESERVEDG[0x100 / 2 - N_HORIZ_UV_TAPS * N_PHASES]; 175 }; 176 177 struct intel_overlay { 178 struct drm_i915_private *i915; 179 struct intel_context *context; 180 struct intel_crtc *crtc; 181 struct i915_vma *vma; 182 struct i915_vma *old_vma; 183 bool active; 184 bool pfit_active; 185 u32 pfit_vscale_ratio; /* shifted-point number, (1<<12) == 1.0 */ 186 u32 color_key:24; 187 u32 color_key_enabled:1; 188 u32 brightness, contrast, saturation; 189 u32 old_xscale, old_yscale; 190 /* register access */ 191 struct drm_i915_gem_object *reg_bo; 192 struct overlay_registers __iomem *regs; 193 u32 flip_addr; 194 /* flip handling */ 195 struct i915_active last_flip; 196 void (*flip_complete)(struct intel_overlay *ovl); 197 }; 198 199 static void i830_overlay_clock_gating(struct drm_i915_private *dev_priv, 200 bool enable) 201 { 202 struct pci_dev *pdev = dev_priv->drm.pdev; 203 u8 val; 204 205 /* WA_OVERLAY_CLKGATE:alm */ 206 if (enable) 207 intel_de_write(dev_priv, DSPCLK_GATE_D, 0); 208 else 209 intel_de_write(dev_priv, DSPCLK_GATE_D, 210 OVRUNIT_CLOCK_GATE_DISABLE); 211 212 /* WA_DISABLE_L2CACHE_CLOCK_GATING:alm */ 213 pci_bus_read_config_byte(pdev->bus, 214 PCI_DEVFN(0, 0), I830_CLOCK_GATE, &val); 215 if (enable) 216 val &= ~I830_L2_CACHE_CLOCK_GATE_DISABLE; 217 else 218 val |= I830_L2_CACHE_CLOCK_GATE_DISABLE; 219 pci_bus_write_config_byte(pdev->bus, 220 PCI_DEVFN(0, 0), I830_CLOCK_GATE, val); 221 } 222 223 static struct i915_request * 224 alloc_request(struct intel_overlay *overlay, void (*fn)(struct intel_overlay *)) 225 { 226 struct i915_request *rq; 227 int err; 228 229 overlay->flip_complete = fn; 230 231 rq = i915_request_create(overlay->context); 232 if (IS_ERR(rq)) 233 return rq; 234 235 err = i915_active_add_request(&overlay->last_flip, rq); 236 if (err) { 237 i915_request_add(rq); 238 return ERR_PTR(err); 239 } 240 241 return rq; 242 } 243 244 /* overlay needs to be disable in OCMD reg */ 245 static int intel_overlay_on(struct intel_overlay *overlay) 246 { 247 struct drm_i915_private *dev_priv = overlay->i915; 248 struct i915_request *rq; 249 u32 *cs; 250 251 drm_WARN_ON(&dev_priv->drm, overlay->active); 252 253 rq = alloc_request(overlay, NULL); 254 if (IS_ERR(rq)) 255 return PTR_ERR(rq); 256 257 cs = intel_ring_begin(rq, 4); 258 if (IS_ERR(cs)) { 259 i915_request_add(rq); 260 return PTR_ERR(cs); 261 } 262 263 overlay->active = true; 264 265 if (IS_I830(dev_priv)) 266 i830_overlay_clock_gating(dev_priv, false); 267 268 *cs++ = MI_OVERLAY_FLIP | MI_OVERLAY_ON; 269 *cs++ = overlay->flip_addr | OFC_UPDATE; 270 *cs++ = MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP; 271 *cs++ = MI_NOOP; 272 intel_ring_advance(rq, cs); 273 274 i915_request_add(rq); 275 276 return i915_active_wait(&overlay->last_flip); 277 } 278 279 static void intel_overlay_flip_prepare(struct intel_overlay *overlay, 280 struct i915_vma *vma) 281 { 282 enum pipe pipe = overlay->crtc->pipe; 283 struct intel_frontbuffer *from = NULL, *to = NULL; 284 285 WARN_ON(overlay->old_vma); 286 287 if (overlay->vma) 288 from = intel_frontbuffer_get(overlay->vma->obj); 289 if (vma) 290 to = intel_frontbuffer_get(vma->obj); 291 292 intel_frontbuffer_track(from, to, INTEL_FRONTBUFFER_OVERLAY(pipe)); 293 294 if (to) 295 intel_frontbuffer_put(to); 296 if (from) 297 intel_frontbuffer_put(from); 298 299 intel_frontbuffer_flip_prepare(overlay->i915, 300 INTEL_FRONTBUFFER_OVERLAY(pipe)); 301 302 overlay->old_vma = overlay->vma; 303 if (vma) 304 overlay->vma = i915_vma_get(vma); 305 else 306 overlay->vma = NULL; 307 } 308 309 /* overlay needs to be enabled in OCMD reg */ 310 static int intel_overlay_continue(struct intel_overlay *overlay, 311 struct i915_vma *vma, 312 bool load_polyphase_filter) 313 { 314 struct drm_i915_private *dev_priv = overlay->i915; 315 struct i915_request *rq; 316 u32 flip_addr = overlay->flip_addr; 317 u32 tmp, *cs; 318 319 drm_WARN_ON(&dev_priv->drm, !overlay->active); 320 321 if (load_polyphase_filter) 322 flip_addr |= OFC_UPDATE; 323 324 /* check for underruns */ 325 tmp = intel_de_read(dev_priv, DOVSTA); 326 if (tmp & (1 << 17)) 327 DRM_DEBUG("overlay underrun, DOVSTA: %x\n", tmp); 328 329 rq = alloc_request(overlay, NULL); 330 if (IS_ERR(rq)) 331 return PTR_ERR(rq); 332 333 cs = intel_ring_begin(rq, 2); 334 if (IS_ERR(cs)) { 335 i915_request_add(rq); 336 return PTR_ERR(cs); 337 } 338 339 *cs++ = MI_OVERLAY_FLIP | MI_OVERLAY_CONTINUE; 340 *cs++ = flip_addr; 341 intel_ring_advance(rq, cs); 342 343 intel_overlay_flip_prepare(overlay, vma); 344 i915_request_add(rq); 345 346 return 0; 347 } 348 349 static void intel_overlay_release_old_vma(struct intel_overlay *overlay) 350 { 351 struct i915_vma *vma; 352 353 vma = fetch_and_zero(&overlay->old_vma); 354 if (WARN_ON(!vma)) 355 return; 356 357 intel_frontbuffer_flip_complete(overlay->i915, 358 INTEL_FRONTBUFFER_OVERLAY(overlay->crtc->pipe)); 359 360 i915_gem_object_unpin_from_display_plane(vma); 361 i915_vma_put(vma); 362 } 363 364 static void 365 intel_overlay_release_old_vid_tail(struct intel_overlay *overlay) 366 { 367 intel_overlay_release_old_vma(overlay); 368 } 369 370 static void intel_overlay_off_tail(struct intel_overlay *overlay) 371 { 372 struct drm_i915_private *dev_priv = overlay->i915; 373 374 intel_overlay_release_old_vma(overlay); 375 376 overlay->crtc->overlay = NULL; 377 overlay->crtc = NULL; 378 overlay->active = false; 379 380 if (IS_I830(dev_priv)) 381 i830_overlay_clock_gating(dev_priv, true); 382 } 383 384 static void 385 intel_overlay_last_flip_retire(struct i915_active *active) 386 { 387 struct intel_overlay *overlay = 388 container_of(active, typeof(*overlay), last_flip); 389 390 if (overlay->flip_complete) 391 overlay->flip_complete(overlay); 392 } 393 394 /* overlay needs to be disabled in OCMD reg */ 395 static int intel_overlay_off(struct intel_overlay *overlay) 396 { 397 struct i915_request *rq; 398 u32 *cs, flip_addr = overlay->flip_addr; 399 400 WARN_ON(!overlay->active); 401 402 /* According to intel docs the overlay hw may hang (when switching 403 * off) without loading the filter coeffs. It is however unclear whether 404 * this applies to the disabling of the overlay or to the switching off 405 * of the hw. Do it in both cases */ 406 flip_addr |= OFC_UPDATE; 407 408 rq = alloc_request(overlay, intel_overlay_off_tail); 409 if (IS_ERR(rq)) 410 return PTR_ERR(rq); 411 412 cs = intel_ring_begin(rq, 6); 413 if (IS_ERR(cs)) { 414 i915_request_add(rq); 415 return PTR_ERR(cs); 416 } 417 418 /* wait for overlay to go idle */ 419 *cs++ = MI_OVERLAY_FLIP | MI_OVERLAY_CONTINUE; 420 *cs++ = flip_addr; 421 *cs++ = MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP; 422 423 /* turn overlay off */ 424 *cs++ = MI_OVERLAY_FLIP | MI_OVERLAY_OFF; 425 *cs++ = flip_addr; 426 *cs++ = MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP; 427 428 intel_ring_advance(rq, cs); 429 430 intel_overlay_flip_prepare(overlay, NULL); 431 i915_request_add(rq); 432 433 return i915_active_wait(&overlay->last_flip); 434 } 435 436 /* recover from an interruption due to a signal 437 * We have to be careful not to repeat work forever an make forward progess. */ 438 static int intel_overlay_recover_from_interrupt(struct intel_overlay *overlay) 439 { 440 return i915_active_wait(&overlay->last_flip); 441 } 442 443 /* Wait for pending overlay flip and release old frame. 444 * Needs to be called before the overlay register are changed 445 * via intel_overlay_(un)map_regs 446 */ 447 static int intel_overlay_release_old_vid(struct intel_overlay *overlay) 448 { 449 struct drm_i915_private *dev_priv = overlay->i915; 450 struct i915_request *rq; 451 u32 *cs; 452 453 /* 454 * Only wait if there is actually an old frame to release to 455 * guarantee forward progress. 456 */ 457 if (!overlay->old_vma) 458 return 0; 459 460 if (!(intel_de_read(dev_priv, GEN2_ISR) & I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT)) { 461 intel_overlay_release_old_vid_tail(overlay); 462 return 0; 463 } 464 465 rq = alloc_request(overlay, intel_overlay_release_old_vid_tail); 466 if (IS_ERR(rq)) 467 return PTR_ERR(rq); 468 469 cs = intel_ring_begin(rq, 2); 470 if (IS_ERR(cs)) { 471 i915_request_add(rq); 472 return PTR_ERR(cs); 473 } 474 475 *cs++ = MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP; 476 *cs++ = MI_NOOP; 477 intel_ring_advance(rq, cs); 478 479 i915_request_add(rq); 480 481 return i915_active_wait(&overlay->last_flip); 482 } 483 484 void intel_overlay_reset(struct drm_i915_private *dev_priv) 485 { 486 struct intel_overlay *overlay = dev_priv->overlay; 487 488 if (!overlay) 489 return; 490 491 overlay->old_xscale = 0; 492 overlay->old_yscale = 0; 493 overlay->crtc = NULL; 494 overlay->active = false; 495 } 496 497 static int packed_depth_bytes(u32 format) 498 { 499 switch (format & I915_OVERLAY_DEPTH_MASK) { 500 case I915_OVERLAY_YUV422: 501 return 4; 502 case I915_OVERLAY_YUV411: 503 /* return 6; not implemented */ 504 default: 505 return -EINVAL; 506 } 507 } 508 509 static int packed_width_bytes(u32 format, short width) 510 { 511 switch (format & I915_OVERLAY_DEPTH_MASK) { 512 case I915_OVERLAY_YUV422: 513 return width << 1; 514 default: 515 return -EINVAL; 516 } 517 } 518 519 static int uv_hsubsampling(u32 format) 520 { 521 switch (format & I915_OVERLAY_DEPTH_MASK) { 522 case I915_OVERLAY_YUV422: 523 case I915_OVERLAY_YUV420: 524 return 2; 525 case I915_OVERLAY_YUV411: 526 case I915_OVERLAY_YUV410: 527 return 4; 528 default: 529 return -EINVAL; 530 } 531 } 532 533 static int uv_vsubsampling(u32 format) 534 { 535 switch (format & I915_OVERLAY_DEPTH_MASK) { 536 case I915_OVERLAY_YUV420: 537 case I915_OVERLAY_YUV410: 538 return 2; 539 case I915_OVERLAY_YUV422: 540 case I915_OVERLAY_YUV411: 541 return 1; 542 default: 543 return -EINVAL; 544 } 545 } 546 547 static u32 calc_swidthsw(struct drm_i915_private *dev_priv, u32 offset, u32 width) 548 { 549 u32 sw; 550 551 if (IS_GEN(dev_priv, 2)) 552 sw = ALIGN((offset & 31) + width, 32); 553 else 554 sw = ALIGN((offset & 63) + width, 64); 555 556 if (sw == 0) 557 return 0; 558 559 return (sw - 32) >> 3; 560 } 561 562 static const u16 y_static_hcoeffs[N_PHASES][N_HORIZ_Y_TAPS] = { 563 [ 0] = { 0x3000, 0xb4a0, 0x1930, 0x1920, 0xb4a0, }, 564 [ 1] = { 0x3000, 0xb500, 0x19d0, 0x1880, 0xb440, }, 565 [ 2] = { 0x3000, 0xb540, 0x1a88, 0x2f80, 0xb3e0, }, 566 [ 3] = { 0x3000, 0xb580, 0x1b30, 0x2e20, 0xb380, }, 567 [ 4] = { 0x3000, 0xb5c0, 0x1bd8, 0x2cc0, 0xb320, }, 568 [ 5] = { 0x3020, 0xb5e0, 0x1c60, 0x2b80, 0xb2c0, }, 569 [ 6] = { 0x3020, 0xb5e0, 0x1cf8, 0x2a20, 0xb260, }, 570 [ 7] = { 0x3020, 0xb5e0, 0x1d80, 0x28e0, 0xb200, }, 571 [ 8] = { 0x3020, 0xb5c0, 0x1e08, 0x3f40, 0xb1c0, }, 572 [ 9] = { 0x3020, 0xb580, 0x1e78, 0x3ce0, 0xb160, }, 573 [10] = { 0x3040, 0xb520, 0x1ed8, 0x3aa0, 0xb120, }, 574 [11] = { 0x3040, 0xb4a0, 0x1f30, 0x3880, 0xb0e0, }, 575 [12] = { 0x3040, 0xb400, 0x1f78, 0x3680, 0xb0a0, }, 576 [13] = { 0x3020, 0xb340, 0x1fb8, 0x34a0, 0xb060, }, 577 [14] = { 0x3020, 0xb240, 0x1fe0, 0x32e0, 0xb040, }, 578 [15] = { 0x3020, 0xb140, 0x1ff8, 0x3160, 0xb020, }, 579 [16] = { 0xb000, 0x3000, 0x0800, 0x3000, 0xb000, }, 580 }; 581 582 static const u16 uv_static_hcoeffs[N_PHASES][N_HORIZ_UV_TAPS] = { 583 [ 0] = { 0x3000, 0x1800, 0x1800, }, 584 [ 1] = { 0xb000, 0x18d0, 0x2e60, }, 585 [ 2] = { 0xb000, 0x1990, 0x2ce0, }, 586 [ 3] = { 0xb020, 0x1a68, 0x2b40, }, 587 [ 4] = { 0xb040, 0x1b20, 0x29e0, }, 588 [ 5] = { 0xb060, 0x1bd8, 0x2880, }, 589 [ 6] = { 0xb080, 0x1c88, 0x3e60, }, 590 [ 7] = { 0xb0a0, 0x1d28, 0x3c00, }, 591 [ 8] = { 0xb0c0, 0x1db8, 0x39e0, }, 592 [ 9] = { 0xb0e0, 0x1e40, 0x37e0, }, 593 [10] = { 0xb100, 0x1eb8, 0x3620, }, 594 [11] = { 0xb100, 0x1f18, 0x34a0, }, 595 [12] = { 0xb100, 0x1f68, 0x3360, }, 596 [13] = { 0xb0e0, 0x1fa8, 0x3240, }, 597 [14] = { 0xb0c0, 0x1fe0, 0x3140, }, 598 [15] = { 0xb060, 0x1ff0, 0x30a0, }, 599 [16] = { 0x3000, 0x0800, 0x3000, }, 600 }; 601 602 static void update_polyphase_filter(struct overlay_registers __iomem *regs) 603 { 604 memcpy_toio(regs->Y_HCOEFS, y_static_hcoeffs, sizeof(y_static_hcoeffs)); 605 memcpy_toio(regs->UV_HCOEFS, uv_static_hcoeffs, 606 sizeof(uv_static_hcoeffs)); 607 } 608 609 static bool update_scaling_factors(struct intel_overlay *overlay, 610 struct overlay_registers __iomem *regs, 611 struct drm_intel_overlay_put_image *params) 612 { 613 /* fixed point with a 12 bit shift */ 614 u32 xscale, yscale, xscale_UV, yscale_UV; 615 #define FP_SHIFT 12 616 #define FRACT_MASK 0xfff 617 bool scale_changed = false; 618 int uv_hscale = uv_hsubsampling(params->flags); 619 int uv_vscale = uv_vsubsampling(params->flags); 620 621 if (params->dst_width > 1) 622 xscale = ((params->src_scan_width - 1) << FP_SHIFT) / 623 params->dst_width; 624 else 625 xscale = 1 << FP_SHIFT; 626 627 if (params->dst_height > 1) 628 yscale = ((params->src_scan_height - 1) << FP_SHIFT) / 629 params->dst_height; 630 else 631 yscale = 1 << FP_SHIFT; 632 633 /*if (params->format & I915_OVERLAY_YUV_PLANAR) {*/ 634 xscale_UV = xscale/uv_hscale; 635 yscale_UV = yscale/uv_vscale; 636 /* make the Y scale to UV scale ratio an exact multiply */ 637 xscale = xscale_UV * uv_hscale; 638 yscale = yscale_UV * uv_vscale; 639 /*} else { 640 xscale_UV = 0; 641 yscale_UV = 0; 642 }*/ 643 644 if (xscale != overlay->old_xscale || yscale != overlay->old_yscale) 645 scale_changed = true; 646 overlay->old_xscale = xscale; 647 overlay->old_yscale = yscale; 648 649 iowrite32(((yscale & FRACT_MASK) << 20) | 650 ((xscale >> FP_SHIFT) << 16) | 651 ((xscale & FRACT_MASK) << 3), 652 ®s->YRGBSCALE); 653 654 iowrite32(((yscale_UV & FRACT_MASK) << 20) | 655 ((xscale_UV >> FP_SHIFT) << 16) | 656 ((xscale_UV & FRACT_MASK) << 3), 657 ®s->UVSCALE); 658 659 iowrite32((((yscale >> FP_SHIFT) << 16) | 660 ((yscale_UV >> FP_SHIFT) << 0)), 661 ®s->UVSCALEV); 662 663 if (scale_changed) 664 update_polyphase_filter(regs); 665 666 return scale_changed; 667 } 668 669 static void update_colorkey(struct intel_overlay *overlay, 670 struct overlay_registers __iomem *regs) 671 { 672 const struct intel_plane_state *state = 673 to_intel_plane_state(overlay->crtc->base.primary->state); 674 u32 key = overlay->color_key; 675 u32 format = 0; 676 u32 flags = 0; 677 678 if (overlay->color_key_enabled) 679 flags |= DST_KEY_ENABLE; 680 681 if (state->uapi.visible) 682 format = state->hw.fb->format->format; 683 684 switch (format) { 685 case DRM_FORMAT_C8: 686 key = 0; 687 flags |= CLK_RGB8I_MASK; 688 break; 689 case DRM_FORMAT_XRGB1555: 690 key = RGB15_TO_COLORKEY(key); 691 flags |= CLK_RGB15_MASK; 692 break; 693 case DRM_FORMAT_RGB565: 694 key = RGB16_TO_COLORKEY(key); 695 flags |= CLK_RGB16_MASK; 696 break; 697 default: 698 flags |= CLK_RGB24_MASK; 699 break; 700 } 701 702 iowrite32(key, ®s->DCLRKV); 703 iowrite32(flags, ®s->DCLRKM); 704 } 705 706 static u32 overlay_cmd_reg(struct drm_intel_overlay_put_image *params) 707 { 708 u32 cmd = OCMD_ENABLE | OCMD_BUF_TYPE_FRAME | OCMD_BUFFER0; 709 710 if (params->flags & I915_OVERLAY_YUV_PLANAR) { 711 switch (params->flags & I915_OVERLAY_DEPTH_MASK) { 712 case I915_OVERLAY_YUV422: 713 cmd |= OCMD_YUV_422_PLANAR; 714 break; 715 case I915_OVERLAY_YUV420: 716 cmd |= OCMD_YUV_420_PLANAR; 717 break; 718 case I915_OVERLAY_YUV411: 719 case I915_OVERLAY_YUV410: 720 cmd |= OCMD_YUV_410_PLANAR; 721 break; 722 } 723 } else { /* YUV packed */ 724 switch (params->flags & I915_OVERLAY_DEPTH_MASK) { 725 case I915_OVERLAY_YUV422: 726 cmd |= OCMD_YUV_422_PACKED; 727 break; 728 case I915_OVERLAY_YUV411: 729 cmd |= OCMD_YUV_411_PACKED; 730 break; 731 } 732 733 switch (params->flags & I915_OVERLAY_SWAP_MASK) { 734 case I915_OVERLAY_NO_SWAP: 735 break; 736 case I915_OVERLAY_UV_SWAP: 737 cmd |= OCMD_UV_SWAP; 738 break; 739 case I915_OVERLAY_Y_SWAP: 740 cmd |= OCMD_Y_SWAP; 741 break; 742 case I915_OVERLAY_Y_AND_UV_SWAP: 743 cmd |= OCMD_Y_AND_UV_SWAP; 744 break; 745 } 746 } 747 748 return cmd; 749 } 750 751 static int intel_overlay_do_put_image(struct intel_overlay *overlay, 752 struct drm_i915_gem_object *new_bo, 753 struct drm_intel_overlay_put_image *params) 754 { 755 struct overlay_registers __iomem *regs = overlay->regs; 756 struct drm_i915_private *dev_priv = overlay->i915; 757 u32 swidth, swidthsw, sheight, ostride; 758 enum pipe pipe = overlay->crtc->pipe; 759 bool scale_changed = false; 760 struct i915_vma *vma; 761 int ret, tmp_width; 762 763 drm_WARN_ON(&dev_priv->drm, 764 !drm_modeset_is_locked(&dev_priv->drm.mode_config.connection_mutex)); 765 766 ret = intel_overlay_release_old_vid(overlay); 767 if (ret != 0) 768 return ret; 769 770 atomic_inc(&dev_priv->gpu_error.pending_fb_pin); 771 772 vma = i915_gem_object_pin_to_display_plane(new_bo, 773 0, NULL, PIN_MAPPABLE); 774 if (IS_ERR(vma)) { 775 ret = PTR_ERR(vma); 776 goto out_pin_section; 777 } 778 i915_gem_object_flush_frontbuffer(new_bo, ORIGIN_DIRTYFB); 779 780 if (!overlay->active) { 781 u32 oconfig; 782 783 oconfig = OCONF_CC_OUT_8BIT; 784 if (IS_GEN(dev_priv, 4)) 785 oconfig |= OCONF_CSC_MODE_BT709; 786 oconfig |= pipe == 0 ? 787 OCONF_PIPE_A : OCONF_PIPE_B; 788 iowrite32(oconfig, ®s->OCONFIG); 789 790 ret = intel_overlay_on(overlay); 791 if (ret != 0) 792 goto out_unpin; 793 } 794 795 iowrite32(params->dst_y << 16 | params->dst_x, ®s->DWINPOS); 796 iowrite32(params->dst_height << 16 | params->dst_width, ®s->DWINSZ); 797 798 if (params->flags & I915_OVERLAY_YUV_PACKED) 799 tmp_width = packed_width_bytes(params->flags, 800 params->src_width); 801 else 802 tmp_width = params->src_width; 803 804 swidth = params->src_width; 805 swidthsw = calc_swidthsw(dev_priv, params->offset_Y, tmp_width); 806 sheight = params->src_height; 807 iowrite32(i915_ggtt_offset(vma) + params->offset_Y, ®s->OBUF_0Y); 808 ostride = params->stride_Y; 809 810 if (params->flags & I915_OVERLAY_YUV_PLANAR) { 811 int uv_hscale = uv_hsubsampling(params->flags); 812 int uv_vscale = uv_vsubsampling(params->flags); 813 u32 tmp_U, tmp_V; 814 815 swidth |= (params->src_width / uv_hscale) << 16; 816 sheight |= (params->src_height / uv_vscale) << 16; 817 818 tmp_U = calc_swidthsw(dev_priv, params->offset_U, 819 params->src_width / uv_hscale); 820 tmp_V = calc_swidthsw(dev_priv, params->offset_V, 821 params->src_width / uv_hscale); 822 swidthsw |= max(tmp_U, tmp_V) << 16; 823 824 iowrite32(i915_ggtt_offset(vma) + params->offset_U, 825 ®s->OBUF_0U); 826 iowrite32(i915_ggtt_offset(vma) + params->offset_V, 827 ®s->OBUF_0V); 828 829 ostride |= params->stride_UV << 16; 830 } 831 832 iowrite32(swidth, ®s->SWIDTH); 833 iowrite32(swidthsw, ®s->SWIDTHSW); 834 iowrite32(sheight, ®s->SHEIGHT); 835 iowrite32(ostride, ®s->OSTRIDE); 836 837 scale_changed = update_scaling_factors(overlay, regs, params); 838 839 update_colorkey(overlay, regs); 840 841 iowrite32(overlay_cmd_reg(params), ®s->OCMD); 842 843 ret = intel_overlay_continue(overlay, vma, scale_changed); 844 if (ret) 845 goto out_unpin; 846 847 return 0; 848 849 out_unpin: 850 i915_gem_object_unpin_from_display_plane(vma); 851 out_pin_section: 852 atomic_dec(&dev_priv->gpu_error.pending_fb_pin); 853 854 return ret; 855 } 856 857 int intel_overlay_switch_off(struct intel_overlay *overlay) 858 { 859 struct drm_i915_private *dev_priv = overlay->i915; 860 int ret; 861 862 drm_WARN_ON(&dev_priv->drm, 863 !drm_modeset_is_locked(&dev_priv->drm.mode_config.connection_mutex)); 864 865 ret = intel_overlay_recover_from_interrupt(overlay); 866 if (ret != 0) 867 return ret; 868 869 if (!overlay->active) 870 return 0; 871 872 ret = intel_overlay_release_old_vid(overlay); 873 if (ret != 0) 874 return ret; 875 876 iowrite32(0, &overlay->regs->OCMD); 877 878 return intel_overlay_off(overlay); 879 } 880 881 static int check_overlay_possible_on_crtc(struct intel_overlay *overlay, 882 struct intel_crtc *crtc) 883 { 884 if (!crtc->active) 885 return -EINVAL; 886 887 /* can't use the overlay with double wide pipe */ 888 if (crtc->config->double_wide) 889 return -EINVAL; 890 891 return 0; 892 } 893 894 static void update_pfit_vscale_ratio(struct intel_overlay *overlay) 895 { 896 struct drm_i915_private *dev_priv = overlay->i915; 897 u32 pfit_control = intel_de_read(dev_priv, PFIT_CONTROL); 898 u32 ratio; 899 900 /* XXX: This is not the same logic as in the xorg driver, but more in 901 * line with the intel documentation for the i965 902 */ 903 if (INTEL_GEN(dev_priv) >= 4) { 904 /* on i965 use the PGM reg to read out the autoscaler values */ 905 ratio = intel_de_read(dev_priv, PFIT_PGM_RATIOS) >> PFIT_VERT_SCALE_SHIFT_965; 906 } else { 907 if (pfit_control & VERT_AUTO_SCALE) 908 ratio = intel_de_read(dev_priv, PFIT_AUTO_RATIOS); 909 else 910 ratio = intel_de_read(dev_priv, PFIT_PGM_RATIOS); 911 ratio >>= PFIT_VERT_SCALE_SHIFT; 912 } 913 914 overlay->pfit_vscale_ratio = ratio; 915 } 916 917 static int check_overlay_dst(struct intel_overlay *overlay, 918 struct drm_intel_overlay_put_image *rec) 919 { 920 const struct intel_crtc_state *pipe_config = 921 overlay->crtc->config; 922 923 if (rec->dst_x < pipe_config->pipe_src_w && 924 rec->dst_x + rec->dst_width <= pipe_config->pipe_src_w && 925 rec->dst_y < pipe_config->pipe_src_h && 926 rec->dst_y + rec->dst_height <= pipe_config->pipe_src_h) 927 return 0; 928 else 929 return -EINVAL; 930 } 931 932 static int check_overlay_scaling(struct drm_intel_overlay_put_image *rec) 933 { 934 u32 tmp; 935 936 /* downscaling limit is 8.0 */ 937 tmp = ((rec->src_scan_height << 16) / rec->dst_height) >> 16; 938 if (tmp > 7) 939 return -EINVAL; 940 941 tmp = ((rec->src_scan_width << 16) / rec->dst_width) >> 16; 942 if (tmp > 7) 943 return -EINVAL; 944 945 return 0; 946 } 947 948 static int check_overlay_src(struct drm_i915_private *dev_priv, 949 struct drm_intel_overlay_put_image *rec, 950 struct drm_i915_gem_object *new_bo) 951 { 952 int uv_hscale = uv_hsubsampling(rec->flags); 953 int uv_vscale = uv_vsubsampling(rec->flags); 954 u32 stride_mask; 955 int depth; 956 u32 tmp; 957 958 /* check src dimensions */ 959 if (IS_I845G(dev_priv) || IS_I830(dev_priv)) { 960 if (rec->src_height > IMAGE_MAX_HEIGHT_LEGACY || 961 rec->src_width > IMAGE_MAX_WIDTH_LEGACY) 962 return -EINVAL; 963 } else { 964 if (rec->src_height > IMAGE_MAX_HEIGHT || 965 rec->src_width > IMAGE_MAX_WIDTH) 966 return -EINVAL; 967 } 968 969 /* better safe than sorry, use 4 as the maximal subsampling ratio */ 970 if (rec->src_height < N_VERT_Y_TAPS*4 || 971 rec->src_width < N_HORIZ_Y_TAPS*4) 972 return -EINVAL; 973 974 /* check alignment constraints */ 975 switch (rec->flags & I915_OVERLAY_TYPE_MASK) { 976 case I915_OVERLAY_RGB: 977 /* not implemented */ 978 return -EINVAL; 979 980 case I915_OVERLAY_YUV_PACKED: 981 if (uv_vscale != 1) 982 return -EINVAL; 983 984 depth = packed_depth_bytes(rec->flags); 985 if (depth < 0) 986 return depth; 987 988 /* ignore UV planes */ 989 rec->stride_UV = 0; 990 rec->offset_U = 0; 991 rec->offset_V = 0; 992 /* check pixel alignment */ 993 if (rec->offset_Y % depth) 994 return -EINVAL; 995 break; 996 997 case I915_OVERLAY_YUV_PLANAR: 998 if (uv_vscale < 0 || uv_hscale < 0) 999 return -EINVAL; 1000 /* no offset restrictions for planar formats */ 1001 break; 1002 1003 default: 1004 return -EINVAL; 1005 } 1006 1007 if (rec->src_width % uv_hscale) 1008 return -EINVAL; 1009 1010 /* stride checking */ 1011 if (IS_I830(dev_priv) || IS_I845G(dev_priv)) 1012 stride_mask = 255; 1013 else 1014 stride_mask = 63; 1015 1016 if (rec->stride_Y & stride_mask || rec->stride_UV & stride_mask) 1017 return -EINVAL; 1018 if (IS_GEN(dev_priv, 4) && rec->stride_Y < 512) 1019 return -EINVAL; 1020 1021 tmp = (rec->flags & I915_OVERLAY_TYPE_MASK) == I915_OVERLAY_YUV_PLANAR ? 1022 4096 : 8192; 1023 if (rec->stride_Y > tmp || rec->stride_UV > 2*1024) 1024 return -EINVAL; 1025 1026 /* check buffer dimensions */ 1027 switch (rec->flags & I915_OVERLAY_TYPE_MASK) { 1028 case I915_OVERLAY_RGB: 1029 case I915_OVERLAY_YUV_PACKED: 1030 /* always 4 Y values per depth pixels */ 1031 if (packed_width_bytes(rec->flags, rec->src_width) > rec->stride_Y) 1032 return -EINVAL; 1033 1034 tmp = rec->stride_Y*rec->src_height; 1035 if (rec->offset_Y + tmp > new_bo->base.size) 1036 return -EINVAL; 1037 break; 1038 1039 case I915_OVERLAY_YUV_PLANAR: 1040 if (rec->src_width > rec->stride_Y) 1041 return -EINVAL; 1042 if (rec->src_width/uv_hscale > rec->stride_UV) 1043 return -EINVAL; 1044 1045 tmp = rec->stride_Y * rec->src_height; 1046 if (rec->offset_Y + tmp > new_bo->base.size) 1047 return -EINVAL; 1048 1049 tmp = rec->stride_UV * (rec->src_height / uv_vscale); 1050 if (rec->offset_U + tmp > new_bo->base.size || 1051 rec->offset_V + tmp > new_bo->base.size) 1052 return -EINVAL; 1053 break; 1054 } 1055 1056 return 0; 1057 } 1058 1059 int intel_overlay_put_image_ioctl(struct drm_device *dev, void *data, 1060 struct drm_file *file_priv) 1061 { 1062 struct drm_intel_overlay_put_image *params = data; 1063 struct drm_i915_private *dev_priv = to_i915(dev); 1064 struct intel_overlay *overlay; 1065 struct drm_crtc *drmmode_crtc; 1066 struct intel_crtc *crtc; 1067 struct drm_i915_gem_object *new_bo; 1068 int ret; 1069 1070 overlay = dev_priv->overlay; 1071 if (!overlay) { 1072 DRM_DEBUG("userspace bug: no overlay\n"); 1073 return -ENODEV; 1074 } 1075 1076 if (!(params->flags & I915_OVERLAY_ENABLE)) { 1077 drm_modeset_lock_all(dev); 1078 ret = intel_overlay_switch_off(overlay); 1079 drm_modeset_unlock_all(dev); 1080 1081 return ret; 1082 } 1083 1084 drmmode_crtc = drm_crtc_find(dev, file_priv, params->crtc_id); 1085 if (!drmmode_crtc) 1086 return -ENOENT; 1087 crtc = to_intel_crtc(drmmode_crtc); 1088 1089 new_bo = i915_gem_object_lookup(file_priv, params->bo_handle); 1090 if (!new_bo) 1091 return -ENOENT; 1092 1093 drm_modeset_lock_all(dev); 1094 1095 if (i915_gem_object_is_tiled(new_bo)) { 1096 DRM_DEBUG_KMS("buffer used for overlay image can not be tiled\n"); 1097 ret = -EINVAL; 1098 goto out_unlock; 1099 } 1100 1101 ret = intel_overlay_recover_from_interrupt(overlay); 1102 if (ret != 0) 1103 goto out_unlock; 1104 1105 if (overlay->crtc != crtc) { 1106 ret = intel_overlay_switch_off(overlay); 1107 if (ret != 0) 1108 goto out_unlock; 1109 1110 ret = check_overlay_possible_on_crtc(overlay, crtc); 1111 if (ret != 0) 1112 goto out_unlock; 1113 1114 overlay->crtc = crtc; 1115 crtc->overlay = overlay; 1116 1117 /* line too wide, i.e. one-line-mode */ 1118 if (crtc->config->pipe_src_w > 1024 && 1119 crtc->config->gmch_pfit.control & PFIT_ENABLE) { 1120 overlay->pfit_active = true; 1121 update_pfit_vscale_ratio(overlay); 1122 } else 1123 overlay->pfit_active = false; 1124 } 1125 1126 ret = check_overlay_dst(overlay, params); 1127 if (ret != 0) 1128 goto out_unlock; 1129 1130 if (overlay->pfit_active) { 1131 params->dst_y = (((u32)params->dst_y << 12) / 1132 overlay->pfit_vscale_ratio); 1133 /* shifting right rounds downwards, so add 1 */ 1134 params->dst_height = (((u32)params->dst_height << 12) / 1135 overlay->pfit_vscale_ratio) + 1; 1136 } 1137 1138 if (params->src_scan_height > params->src_height || 1139 params->src_scan_width > params->src_width) { 1140 ret = -EINVAL; 1141 goto out_unlock; 1142 } 1143 1144 ret = check_overlay_src(dev_priv, params, new_bo); 1145 if (ret != 0) 1146 goto out_unlock; 1147 1148 /* Check scaling after src size to prevent a divide-by-zero. */ 1149 ret = check_overlay_scaling(params); 1150 if (ret != 0) 1151 goto out_unlock; 1152 1153 ret = intel_overlay_do_put_image(overlay, new_bo, params); 1154 if (ret != 0) 1155 goto out_unlock; 1156 1157 drm_modeset_unlock_all(dev); 1158 i915_gem_object_put(new_bo); 1159 1160 return 0; 1161 1162 out_unlock: 1163 drm_modeset_unlock_all(dev); 1164 i915_gem_object_put(new_bo); 1165 1166 return ret; 1167 } 1168 1169 static void update_reg_attrs(struct intel_overlay *overlay, 1170 struct overlay_registers __iomem *regs) 1171 { 1172 iowrite32((overlay->contrast << 18) | (overlay->brightness & 0xff), 1173 ®s->OCLRC0); 1174 iowrite32(overlay->saturation, ®s->OCLRC1); 1175 } 1176 1177 static bool check_gamma_bounds(u32 gamma1, u32 gamma2) 1178 { 1179 int i; 1180 1181 if (gamma1 & 0xff000000 || gamma2 & 0xff000000) 1182 return false; 1183 1184 for (i = 0; i < 3; i++) { 1185 if (((gamma1 >> i*8) & 0xff) >= ((gamma2 >> i*8) & 0xff)) 1186 return false; 1187 } 1188 1189 return true; 1190 } 1191 1192 static bool check_gamma5_errata(u32 gamma5) 1193 { 1194 int i; 1195 1196 for (i = 0; i < 3; i++) { 1197 if (((gamma5 >> i*8) & 0xff) == 0x80) 1198 return false; 1199 } 1200 1201 return true; 1202 } 1203 1204 static int check_gamma(struct drm_intel_overlay_attrs *attrs) 1205 { 1206 if (!check_gamma_bounds(0, attrs->gamma0) || 1207 !check_gamma_bounds(attrs->gamma0, attrs->gamma1) || 1208 !check_gamma_bounds(attrs->gamma1, attrs->gamma2) || 1209 !check_gamma_bounds(attrs->gamma2, attrs->gamma3) || 1210 !check_gamma_bounds(attrs->gamma3, attrs->gamma4) || 1211 !check_gamma_bounds(attrs->gamma4, attrs->gamma5) || 1212 !check_gamma_bounds(attrs->gamma5, 0x00ffffff)) 1213 return -EINVAL; 1214 1215 if (!check_gamma5_errata(attrs->gamma5)) 1216 return -EINVAL; 1217 1218 return 0; 1219 } 1220 1221 int intel_overlay_attrs_ioctl(struct drm_device *dev, void *data, 1222 struct drm_file *file_priv) 1223 { 1224 struct drm_intel_overlay_attrs *attrs = data; 1225 struct drm_i915_private *dev_priv = to_i915(dev); 1226 struct intel_overlay *overlay; 1227 int ret; 1228 1229 overlay = dev_priv->overlay; 1230 if (!overlay) { 1231 DRM_DEBUG("userspace bug: no overlay\n"); 1232 return -ENODEV; 1233 } 1234 1235 drm_modeset_lock_all(dev); 1236 1237 ret = -EINVAL; 1238 if (!(attrs->flags & I915_OVERLAY_UPDATE_ATTRS)) { 1239 attrs->color_key = overlay->color_key; 1240 attrs->brightness = overlay->brightness; 1241 attrs->contrast = overlay->contrast; 1242 attrs->saturation = overlay->saturation; 1243 1244 if (!IS_GEN(dev_priv, 2)) { 1245 attrs->gamma0 = intel_de_read(dev_priv, OGAMC0); 1246 attrs->gamma1 = intel_de_read(dev_priv, OGAMC1); 1247 attrs->gamma2 = intel_de_read(dev_priv, OGAMC2); 1248 attrs->gamma3 = intel_de_read(dev_priv, OGAMC3); 1249 attrs->gamma4 = intel_de_read(dev_priv, OGAMC4); 1250 attrs->gamma5 = intel_de_read(dev_priv, OGAMC5); 1251 } 1252 } else { 1253 if (attrs->brightness < -128 || attrs->brightness > 127) 1254 goto out_unlock; 1255 if (attrs->contrast > 255) 1256 goto out_unlock; 1257 if (attrs->saturation > 1023) 1258 goto out_unlock; 1259 1260 overlay->color_key = attrs->color_key; 1261 overlay->brightness = attrs->brightness; 1262 overlay->contrast = attrs->contrast; 1263 overlay->saturation = attrs->saturation; 1264 1265 update_reg_attrs(overlay, overlay->regs); 1266 1267 if (attrs->flags & I915_OVERLAY_UPDATE_GAMMA) { 1268 if (IS_GEN(dev_priv, 2)) 1269 goto out_unlock; 1270 1271 if (overlay->active) { 1272 ret = -EBUSY; 1273 goto out_unlock; 1274 } 1275 1276 ret = check_gamma(attrs); 1277 if (ret) 1278 goto out_unlock; 1279 1280 intel_de_write(dev_priv, OGAMC0, attrs->gamma0); 1281 intel_de_write(dev_priv, OGAMC1, attrs->gamma1); 1282 intel_de_write(dev_priv, OGAMC2, attrs->gamma2); 1283 intel_de_write(dev_priv, OGAMC3, attrs->gamma3); 1284 intel_de_write(dev_priv, OGAMC4, attrs->gamma4); 1285 intel_de_write(dev_priv, OGAMC5, attrs->gamma5); 1286 } 1287 } 1288 overlay->color_key_enabled = (attrs->flags & I915_OVERLAY_DISABLE_DEST_COLORKEY) == 0; 1289 1290 ret = 0; 1291 out_unlock: 1292 drm_modeset_unlock_all(dev); 1293 1294 return ret; 1295 } 1296 1297 static int get_registers(struct intel_overlay *overlay, bool use_phys) 1298 { 1299 struct drm_i915_private *i915 = overlay->i915; 1300 struct drm_i915_gem_object *obj; 1301 struct i915_vma *vma; 1302 int err; 1303 1304 obj = i915_gem_object_create_stolen(i915, PAGE_SIZE); 1305 if (IS_ERR(obj)) 1306 obj = i915_gem_object_create_internal(i915, PAGE_SIZE); 1307 if (IS_ERR(obj)) 1308 return PTR_ERR(obj); 1309 1310 vma = i915_gem_object_ggtt_pin(obj, NULL, 0, 0, PIN_MAPPABLE); 1311 if (IS_ERR(vma)) { 1312 err = PTR_ERR(vma); 1313 goto err_put_bo; 1314 } 1315 1316 if (use_phys) 1317 overlay->flip_addr = sg_dma_address(obj->mm.pages->sgl); 1318 else 1319 overlay->flip_addr = i915_ggtt_offset(vma); 1320 overlay->regs = i915_vma_pin_iomap(vma); 1321 i915_vma_unpin(vma); 1322 1323 if (IS_ERR(overlay->regs)) { 1324 err = PTR_ERR(overlay->regs); 1325 goto err_put_bo; 1326 } 1327 1328 overlay->reg_bo = obj; 1329 return 0; 1330 1331 err_put_bo: 1332 i915_gem_object_put(obj); 1333 return err; 1334 } 1335 1336 void intel_overlay_setup(struct drm_i915_private *dev_priv) 1337 { 1338 struct intel_overlay *overlay; 1339 struct intel_engine_cs *engine; 1340 int ret; 1341 1342 if (!HAS_OVERLAY(dev_priv)) 1343 return; 1344 1345 engine = dev_priv->engine[RCS0]; 1346 if (!engine || !engine->kernel_context) 1347 return; 1348 1349 overlay = kzalloc(sizeof(*overlay), GFP_KERNEL); 1350 if (!overlay) 1351 return; 1352 1353 overlay->i915 = dev_priv; 1354 overlay->context = engine->kernel_context; 1355 GEM_BUG_ON(!overlay->context); 1356 1357 overlay->color_key = 0x0101fe; 1358 overlay->color_key_enabled = true; 1359 overlay->brightness = -19; 1360 overlay->contrast = 75; 1361 overlay->saturation = 146; 1362 1363 i915_active_init(&overlay->last_flip, 1364 NULL, intel_overlay_last_flip_retire); 1365 1366 ret = get_registers(overlay, OVERLAY_NEEDS_PHYSICAL(dev_priv)); 1367 if (ret) 1368 goto out_free; 1369 1370 memset_io(overlay->regs, 0, sizeof(struct overlay_registers)); 1371 update_polyphase_filter(overlay->regs); 1372 update_reg_attrs(overlay, overlay->regs); 1373 1374 dev_priv->overlay = overlay; 1375 DRM_INFO("Initialized overlay support.\n"); 1376 return; 1377 1378 out_free: 1379 kfree(overlay); 1380 } 1381 1382 void intel_overlay_cleanup(struct drm_i915_private *dev_priv) 1383 { 1384 struct intel_overlay *overlay; 1385 1386 overlay = fetch_and_zero(&dev_priv->overlay); 1387 if (!overlay) 1388 return; 1389 1390 /* 1391 * The bo's should be free'd by the generic code already. 1392 * Furthermore modesetting teardown happens beforehand so the 1393 * hardware should be off already. 1394 */ 1395 drm_WARN_ON(&dev_priv->drm, overlay->active); 1396 1397 i915_gem_object_put(overlay->reg_bo); 1398 i915_active_fini(&overlay->last_flip); 1399 1400 kfree(overlay); 1401 } 1402 1403 #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR) 1404 1405 struct intel_overlay_error_state { 1406 struct overlay_registers regs; 1407 unsigned long base; 1408 u32 dovsta; 1409 u32 isr; 1410 }; 1411 1412 struct intel_overlay_error_state * 1413 intel_overlay_capture_error_state(struct drm_i915_private *dev_priv) 1414 { 1415 struct intel_overlay *overlay = dev_priv->overlay; 1416 struct intel_overlay_error_state *error; 1417 1418 if (!overlay || !overlay->active) 1419 return NULL; 1420 1421 error = kmalloc(sizeof(*error), GFP_ATOMIC); 1422 if (error == NULL) 1423 return NULL; 1424 1425 error->dovsta = intel_de_read(dev_priv, DOVSTA); 1426 error->isr = intel_de_read(dev_priv, GEN2_ISR); 1427 error->base = overlay->flip_addr; 1428 1429 memcpy_fromio(&error->regs, overlay->regs, sizeof(error->regs)); 1430 1431 return error; 1432 } 1433 1434 void 1435 intel_overlay_print_error_state(struct drm_i915_error_state_buf *m, 1436 struct intel_overlay_error_state *error) 1437 { 1438 i915_error_printf(m, "Overlay, status: 0x%08x, interrupt: 0x%08x\n", 1439 error->dovsta, error->isr); 1440 i915_error_printf(m, " Register file at 0x%08lx:\n", 1441 error->base); 1442 1443 #define P(x) i915_error_printf(m, " " #x ": 0x%08x\n", error->regs.x) 1444 P(OBUF_0Y); 1445 P(OBUF_1Y); 1446 P(OBUF_0U); 1447 P(OBUF_0V); 1448 P(OBUF_1U); 1449 P(OBUF_1V); 1450 P(OSTRIDE); 1451 P(YRGB_VPH); 1452 P(UV_VPH); 1453 P(HORZ_PH); 1454 P(INIT_PHS); 1455 P(DWINPOS); 1456 P(DWINSZ); 1457 P(SWIDTH); 1458 P(SWIDTHSW); 1459 P(SHEIGHT); 1460 P(YRGBSCALE); 1461 P(UVSCALE); 1462 P(OCLRC0); 1463 P(OCLRC1); 1464 P(DCLRKV); 1465 P(DCLRKM); 1466 P(SCLRKVH); 1467 P(SCLRKVL); 1468 P(SCLRKEN); 1469 P(OCONFIG); 1470 P(OCMD); 1471 P(OSTART_0Y); 1472 P(OSTART_1Y); 1473 P(OSTART_0U); 1474 P(OSTART_0V); 1475 P(OSTART_1U); 1476 P(OSTART_1V); 1477 P(OTILEOFF_0Y); 1478 P(OTILEOFF_1Y); 1479 P(OTILEOFF_0U); 1480 P(OTILEOFF_0V); 1481 P(OTILEOFF_1U); 1482 P(OTILEOFF_1V); 1483 P(FASTHSCALE); 1484 P(UVSCALEV); 1485 #undef P 1486 } 1487 1488 #endif 1489