1 /* 2 * Copyright © 2009 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 * SOFTWARE. 22 * 23 * Authors: 24 * Daniel Vetter <daniel@ffwll.ch> 25 * 26 * Derived from Xorg ddx, xf86-video-intel, src/i830_video.c 27 */ 28 29 #include <drm/drm_fourcc.h> 30 31 #include "gem/i915_gem_internal.h" 32 #include "gem/i915_gem_object_frontbuffer.h" 33 #include "gem/i915_gem_pm.h" 34 35 #include "gt/intel_gpu_commands.h" 36 #include "gt/intel_ring.h" 37 38 #include "i915_drv.h" 39 #include "i915_reg.h" 40 #include "intel_color_regs.h" 41 #include "intel_de.h" 42 #include "intel_display_regs.h" 43 #include "intel_display_types.h" 44 #include "intel_frontbuffer.h" 45 #include "intel_overlay.h" 46 #include "intel_pci_config.h" 47 #include "intel_pfit_regs.h" 48 49 /* Limits for overlay size. According to intel doc, the real limits are: 50 * Y width: 4095, UV width (planar): 2047, Y height: 2047, 51 * UV width (planar): * 1023. But the xorg thinks 2048 for height and width. Use 52 * the minimum of both. 53 */ 54 #define IMAGE_MAX_WIDTH 2048 55 #define IMAGE_MAX_HEIGHT 2046 /* 2 * 1023 */ 56 /* on 830 and 845 these large limits result in the card hanging */ 57 #define IMAGE_MAX_WIDTH_LEGACY 1024 58 #define IMAGE_MAX_HEIGHT_LEGACY 1088 59 60 /* overlay register definitions */ 61 /* OCMD register */ 62 #define OCMD_TILED_SURFACE (0x1<<19) 63 #define OCMD_MIRROR_MASK (0x3<<17) 64 #define OCMD_MIRROR_MODE (0x3<<17) 65 #define OCMD_MIRROR_HORIZONTAL (0x1<<17) 66 #define OCMD_MIRROR_VERTICAL (0x2<<17) 67 #define OCMD_MIRROR_BOTH (0x3<<17) 68 #define OCMD_BYTEORDER_MASK (0x3<<14) /* zero for YUYV or FOURCC YUY2 */ 69 #define OCMD_UV_SWAP (0x1<<14) /* YVYU */ 70 #define OCMD_Y_SWAP (0x2<<14) /* UYVY or FOURCC UYVY */ 71 #define OCMD_Y_AND_UV_SWAP (0x3<<14) /* VYUY */ 72 #define OCMD_SOURCE_FORMAT_MASK (0xf<<10) 73 #define OCMD_RGB_888 (0x1<<10) /* not in i965 Intel docs */ 74 #define OCMD_RGB_555 (0x2<<10) /* not in i965 Intel docs */ 75 #define OCMD_RGB_565 (0x3<<10) /* not in i965 Intel docs */ 76 #define OCMD_YUV_422_PACKED (0x8<<10) 77 #define OCMD_YUV_411_PACKED (0x9<<10) /* not in i965 Intel docs */ 78 #define OCMD_YUV_420_PLANAR (0xc<<10) 79 #define OCMD_YUV_422_PLANAR (0xd<<10) 80 #define OCMD_YUV_410_PLANAR (0xe<<10) /* also 411 */ 81 #define OCMD_TVSYNCFLIP_PARITY (0x1<<9) 82 #define OCMD_TVSYNCFLIP_ENABLE (0x1<<7) 83 #define OCMD_BUF_TYPE_MASK (0x1<<5) 84 #define OCMD_BUF_TYPE_FRAME (0x0<<5) 85 #define OCMD_BUF_TYPE_FIELD (0x1<<5) 86 #define OCMD_TEST_MODE (0x1<<4) 87 #define OCMD_BUFFER_SELECT (0x3<<2) 88 #define OCMD_BUFFER0 (0x0<<2) 89 #define OCMD_BUFFER1 (0x1<<2) 90 #define OCMD_FIELD_SELECT (0x1<<2) 91 #define OCMD_FIELD0 (0x0<<1) 92 #define OCMD_FIELD1 (0x1<<1) 93 #define OCMD_ENABLE (0x1<<0) 94 95 /* OCONFIG register */ 96 #define OCONF_PIPE_MASK (0x1<<18) 97 #define OCONF_PIPE_A (0x0<<18) 98 #define OCONF_PIPE_B (0x1<<18) 99 #define OCONF_GAMMA2_ENABLE (0x1<<16) 100 #define OCONF_CSC_MODE_BT601 (0x0<<5) 101 #define OCONF_CSC_MODE_BT709 (0x1<<5) 102 #define OCONF_CSC_BYPASS (0x1<<4) 103 #define OCONF_CC_OUT_8BIT (0x1<<3) 104 #define OCONF_TEST_MODE (0x1<<2) 105 #define OCONF_THREE_LINE_BUFFER (0x1<<0) 106 #define OCONF_TWO_LINE_BUFFER (0x0<<0) 107 108 /* DCLRKM (dst-key) register */ 109 #define DST_KEY_ENABLE (0x1<<31) 110 #define CLK_RGB24_MASK 0x0 111 #define CLK_RGB16_MASK 0x070307 112 #define CLK_RGB15_MASK 0x070707 113 114 #define RGB30_TO_COLORKEY(c) \ 115 ((((c) & 0x3fc00000) >> 6) | (((c) & 0x000ff000) >> 4) | (((c) & 0x000003fc) >> 2)) 116 #define RGB16_TO_COLORKEY(c) \ 117 ((((c) & 0xf800) << 8) | (((c) & 0x07e0) << 5) | (((c) & 0x001f) << 3)) 118 #define RGB15_TO_COLORKEY(c) \ 119 ((((c) & 0x7c00) << 9) | (((c) & 0x03e0) << 6) | (((c) & 0x001f) << 3)) 120 #define RGB8I_TO_COLORKEY(c) \ 121 ((((c) & 0xff) << 16) | (((c) & 0xff) << 8) | (((c) & 0xff) << 0)) 122 123 /* overlay flip addr flag */ 124 #define OFC_UPDATE 0x1 125 126 /* polyphase filter coefficients */ 127 #define N_HORIZ_Y_TAPS 5 128 #define N_VERT_Y_TAPS 3 129 #define N_HORIZ_UV_TAPS 3 130 #define N_VERT_UV_TAPS 3 131 #define N_PHASES 17 132 #define MAX_TAPS 5 133 134 /* memory bufferd overlay registers */ 135 struct overlay_registers { 136 u32 OBUF_0Y; 137 u32 OBUF_1Y; 138 u32 OBUF_0U; 139 u32 OBUF_0V; 140 u32 OBUF_1U; 141 u32 OBUF_1V; 142 u32 OSTRIDE; 143 u32 YRGB_VPH; 144 u32 UV_VPH; 145 u32 HORZ_PH; 146 u32 INIT_PHS; 147 u32 DWINPOS; 148 u32 DWINSZ; 149 u32 SWIDTH; 150 u32 SWIDTHSW; 151 u32 SHEIGHT; 152 u32 YRGBSCALE; 153 u32 UVSCALE; 154 u32 OCLRC0; 155 u32 OCLRC1; 156 u32 DCLRKV; 157 u32 DCLRKM; 158 u32 SCLRKVH; 159 u32 SCLRKVL; 160 u32 SCLRKEN; 161 u32 OCONFIG; 162 u32 OCMD; 163 u32 RESERVED1; /* 0x6C */ 164 u32 OSTART_0Y; 165 u32 OSTART_1Y; 166 u32 OSTART_0U; 167 u32 OSTART_0V; 168 u32 OSTART_1U; 169 u32 OSTART_1V; 170 u32 OTILEOFF_0Y; 171 u32 OTILEOFF_1Y; 172 u32 OTILEOFF_0U; 173 u32 OTILEOFF_0V; 174 u32 OTILEOFF_1U; 175 u32 OTILEOFF_1V; 176 u32 FASTHSCALE; /* 0xA0 */ 177 u32 UVSCALEV; /* 0xA4 */ 178 u32 RESERVEDC[(0x200 - 0xA8) / 4]; /* 0xA8 - 0x1FC */ 179 u16 Y_VCOEFS[N_VERT_Y_TAPS * N_PHASES]; /* 0x200 */ 180 u16 RESERVEDD[0x100 / 2 - N_VERT_Y_TAPS * N_PHASES]; 181 u16 Y_HCOEFS[N_HORIZ_Y_TAPS * N_PHASES]; /* 0x300 */ 182 u16 RESERVEDE[0x200 / 2 - N_HORIZ_Y_TAPS * N_PHASES]; 183 u16 UV_VCOEFS[N_VERT_UV_TAPS * N_PHASES]; /* 0x500 */ 184 u16 RESERVEDF[0x100 / 2 - N_VERT_UV_TAPS * N_PHASES]; 185 u16 UV_HCOEFS[N_HORIZ_UV_TAPS * N_PHASES]; /* 0x600 */ 186 u16 RESERVEDG[0x100 / 2 - N_HORIZ_UV_TAPS * N_PHASES]; 187 }; 188 189 struct intel_overlay { 190 struct intel_display *display; 191 struct intel_context *context; 192 struct intel_crtc *crtc; 193 struct i915_vma *vma; 194 struct i915_vma *old_vma; 195 struct intel_frontbuffer *frontbuffer; 196 bool active; 197 bool pfit_active; 198 u32 pfit_vscale_ratio; /* shifted-point number, (1<<12) == 1.0 */ 199 u32 color_key:24; 200 u32 color_key_enabled:1; 201 u32 brightness, contrast, saturation; 202 u32 old_xscale, old_yscale; 203 /* register access */ 204 struct drm_i915_gem_object *reg_bo; 205 struct overlay_registers __iomem *regs; 206 u32 flip_addr; 207 /* flip handling */ 208 struct i915_active last_flip; 209 void (*flip_complete)(struct intel_overlay *ovl); 210 }; 211 212 static void i830_overlay_clock_gating(struct intel_display *display, 213 bool enable) 214 { 215 struct pci_dev *pdev = to_pci_dev(display->drm->dev); 216 u8 val; 217 218 /* WA_OVERLAY_CLKGATE:alm */ 219 if (enable) 220 intel_de_write(display, DSPCLK_GATE_D, 0); 221 else 222 intel_de_write(display, DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE); 223 224 /* WA_DISABLE_L2CACHE_CLOCK_GATING:alm */ 225 pci_bus_read_config_byte(pdev->bus, 226 PCI_DEVFN(0, 0), I830_CLOCK_GATE, &val); 227 if (enable) 228 val &= ~I830_L2_CACHE_CLOCK_GATE_DISABLE; 229 else 230 val |= I830_L2_CACHE_CLOCK_GATE_DISABLE; 231 pci_bus_write_config_byte(pdev->bus, 232 PCI_DEVFN(0, 0), I830_CLOCK_GATE, val); 233 } 234 235 static struct i915_request * 236 alloc_request(struct intel_overlay *overlay, void (*fn)(struct intel_overlay *)) 237 { 238 struct i915_request *rq; 239 int err; 240 241 overlay->flip_complete = fn; 242 243 rq = i915_request_create(overlay->context); 244 if (IS_ERR(rq)) 245 return rq; 246 247 err = i915_active_add_request(&overlay->last_flip, rq); 248 if (err) { 249 i915_request_add(rq); 250 return ERR_PTR(err); 251 } 252 253 return rq; 254 } 255 256 /* overlay needs to be disable in OCMD reg */ 257 static int intel_overlay_on(struct intel_overlay *overlay) 258 { 259 struct intel_display *display = overlay->display; 260 struct i915_request *rq; 261 u32 *cs; 262 263 drm_WARN_ON(display->drm, overlay->active); 264 265 rq = alloc_request(overlay, NULL); 266 if (IS_ERR(rq)) 267 return PTR_ERR(rq); 268 269 cs = intel_ring_begin(rq, 4); 270 if (IS_ERR(cs)) { 271 i915_request_add(rq); 272 return PTR_ERR(cs); 273 } 274 275 overlay->active = true; 276 277 if (display->platform.i830) 278 i830_overlay_clock_gating(display, false); 279 280 *cs++ = MI_OVERLAY_FLIP | MI_OVERLAY_ON; 281 *cs++ = overlay->flip_addr | OFC_UPDATE; 282 *cs++ = MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP; 283 *cs++ = MI_NOOP; 284 intel_ring_advance(rq, cs); 285 286 i915_request_add(rq); 287 288 return i915_active_wait(&overlay->last_flip); 289 } 290 291 static void intel_overlay_flip_prepare(struct intel_overlay *overlay, 292 struct i915_vma *vma) 293 { 294 struct intel_display *display = overlay->display; 295 enum pipe pipe = overlay->crtc->pipe; 296 struct intel_frontbuffer *frontbuffer = NULL; 297 298 drm_WARN_ON(display->drm, overlay->old_vma); 299 300 if (vma) 301 frontbuffer = intel_frontbuffer_get(intel_bo_to_drm_bo(vma->obj)); 302 303 intel_frontbuffer_track(overlay->frontbuffer, frontbuffer, 304 INTEL_FRONTBUFFER_OVERLAY(pipe)); 305 306 if (overlay->frontbuffer) 307 intel_frontbuffer_put(overlay->frontbuffer); 308 overlay->frontbuffer = frontbuffer; 309 310 intel_frontbuffer_flip_prepare(display, INTEL_FRONTBUFFER_OVERLAY(pipe)); 311 312 overlay->old_vma = overlay->vma; 313 if (vma) 314 overlay->vma = i915_vma_get(vma); 315 else 316 overlay->vma = NULL; 317 } 318 319 /* overlay needs to be enabled in OCMD reg */ 320 static int intel_overlay_continue(struct intel_overlay *overlay, 321 struct i915_vma *vma, 322 bool load_polyphase_filter) 323 { 324 struct intel_display *display = overlay->display; 325 struct i915_request *rq; 326 u32 flip_addr = overlay->flip_addr; 327 u32 tmp, *cs; 328 329 drm_WARN_ON(display->drm, !overlay->active); 330 331 if (load_polyphase_filter) 332 flip_addr |= OFC_UPDATE; 333 334 /* check for underruns */ 335 tmp = intel_de_read(display, DOVSTA); 336 if (tmp & (1 << 17)) 337 drm_dbg(display->drm, "overlay underrun, DOVSTA: %x\n", tmp); 338 339 rq = alloc_request(overlay, NULL); 340 if (IS_ERR(rq)) 341 return PTR_ERR(rq); 342 343 cs = intel_ring_begin(rq, 2); 344 if (IS_ERR(cs)) { 345 i915_request_add(rq); 346 return PTR_ERR(cs); 347 } 348 349 *cs++ = MI_OVERLAY_FLIP | MI_OVERLAY_CONTINUE; 350 *cs++ = flip_addr; 351 intel_ring_advance(rq, cs); 352 353 intel_overlay_flip_prepare(overlay, vma); 354 i915_request_add(rq); 355 356 return 0; 357 } 358 359 static void intel_overlay_release_old_vma(struct intel_overlay *overlay) 360 { 361 struct intel_display *display = overlay->display; 362 struct i915_vma *vma; 363 364 vma = fetch_and_zero(&overlay->old_vma); 365 if (drm_WARN_ON(display->drm, !vma)) 366 return; 367 368 intel_frontbuffer_flip_complete(display, INTEL_FRONTBUFFER_OVERLAY(overlay->crtc->pipe)); 369 370 i915_vma_unpin(vma); 371 i915_vma_put(vma); 372 } 373 374 static void 375 intel_overlay_release_old_vid_tail(struct intel_overlay *overlay) 376 { 377 intel_overlay_release_old_vma(overlay); 378 } 379 380 static void intel_overlay_off_tail(struct intel_overlay *overlay) 381 { 382 struct intel_display *display = overlay->display; 383 384 intel_overlay_release_old_vma(overlay); 385 386 overlay->crtc->overlay = NULL; 387 overlay->crtc = NULL; 388 overlay->active = false; 389 390 if (display->platform.i830) 391 i830_overlay_clock_gating(display, true); 392 } 393 394 static void intel_overlay_last_flip_retire(struct i915_active *active) 395 { 396 struct intel_overlay *overlay = 397 container_of(active, typeof(*overlay), last_flip); 398 399 if (overlay->flip_complete) 400 overlay->flip_complete(overlay); 401 } 402 403 /* overlay needs to be disabled in OCMD reg */ 404 static int intel_overlay_off(struct intel_overlay *overlay) 405 { 406 struct intel_display *display = overlay->display; 407 struct i915_request *rq; 408 u32 *cs, flip_addr = overlay->flip_addr; 409 410 drm_WARN_ON(display->drm, !overlay->active); 411 412 /* 413 * According to intel docs the overlay hw may hang (when switching 414 * off) without loading the filter coeffs. It is however unclear whether 415 * this applies to the disabling of the overlay or to the switching off 416 * of the hw. Do it in both cases. 417 */ 418 flip_addr |= OFC_UPDATE; 419 420 rq = alloc_request(overlay, intel_overlay_off_tail); 421 if (IS_ERR(rq)) 422 return PTR_ERR(rq); 423 424 cs = intel_ring_begin(rq, 6); 425 if (IS_ERR(cs)) { 426 i915_request_add(rq); 427 return PTR_ERR(cs); 428 } 429 430 /* wait for overlay to go idle */ 431 *cs++ = MI_OVERLAY_FLIP | MI_OVERLAY_CONTINUE; 432 *cs++ = flip_addr; 433 *cs++ = MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP; 434 435 /* turn overlay off */ 436 *cs++ = MI_OVERLAY_FLIP | MI_OVERLAY_OFF; 437 *cs++ = flip_addr; 438 *cs++ = MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP; 439 440 intel_ring_advance(rq, cs); 441 442 intel_overlay_flip_prepare(overlay, NULL); 443 i915_request_add(rq); 444 445 return i915_active_wait(&overlay->last_flip); 446 } 447 448 /* 449 * Recover from an interruption due to a signal. 450 * We have to be careful not to repeat work forever an make forward progress. 451 */ 452 static int intel_overlay_recover_from_interrupt(struct intel_overlay *overlay) 453 { 454 return i915_active_wait(&overlay->last_flip); 455 } 456 457 /* 458 * Wait for pending overlay flip and release old frame. 459 * Needs to be called before the overlay register are changed 460 * via intel_overlay_(un)map_regs. 461 */ 462 static int intel_overlay_release_old_vid(struct intel_overlay *overlay) 463 { 464 struct intel_display *display = overlay->display; 465 struct i915_request *rq; 466 u32 *cs; 467 468 /* 469 * Only wait if there is actually an old frame to release to 470 * guarantee forward progress. 471 */ 472 if (!overlay->old_vma) 473 return 0; 474 475 if (!(intel_de_read(display, GEN2_ISR) & I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT)) { 476 intel_overlay_release_old_vid_tail(overlay); 477 return 0; 478 } 479 480 rq = alloc_request(overlay, intel_overlay_release_old_vid_tail); 481 if (IS_ERR(rq)) 482 return PTR_ERR(rq); 483 484 cs = intel_ring_begin(rq, 2); 485 if (IS_ERR(cs)) { 486 i915_request_add(rq); 487 return PTR_ERR(cs); 488 } 489 490 *cs++ = MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP; 491 *cs++ = MI_NOOP; 492 intel_ring_advance(rq, cs); 493 494 i915_request_add(rq); 495 496 return i915_active_wait(&overlay->last_flip); 497 } 498 499 void intel_overlay_reset(struct intel_display *display) 500 { 501 struct intel_overlay *overlay = display->overlay; 502 503 if (!overlay) 504 return; 505 506 overlay->old_xscale = 0; 507 overlay->old_yscale = 0; 508 overlay->crtc = NULL; 509 overlay->active = false; 510 } 511 512 static int packed_depth_bytes(u32 format) 513 { 514 switch (format & I915_OVERLAY_DEPTH_MASK) { 515 case I915_OVERLAY_YUV422: 516 return 4; 517 case I915_OVERLAY_YUV411: 518 /* return 6; not implemented */ 519 default: 520 return -EINVAL; 521 } 522 } 523 524 static int packed_width_bytes(u32 format, short width) 525 { 526 switch (format & I915_OVERLAY_DEPTH_MASK) { 527 case I915_OVERLAY_YUV422: 528 return width << 1; 529 default: 530 return -EINVAL; 531 } 532 } 533 534 static int uv_hsubsampling(u32 format) 535 { 536 switch (format & I915_OVERLAY_DEPTH_MASK) { 537 case I915_OVERLAY_YUV422: 538 case I915_OVERLAY_YUV420: 539 return 2; 540 case I915_OVERLAY_YUV411: 541 case I915_OVERLAY_YUV410: 542 return 4; 543 default: 544 return -EINVAL; 545 } 546 } 547 548 static int uv_vsubsampling(u32 format) 549 { 550 switch (format & I915_OVERLAY_DEPTH_MASK) { 551 case I915_OVERLAY_YUV420: 552 case I915_OVERLAY_YUV410: 553 return 2; 554 case I915_OVERLAY_YUV422: 555 case I915_OVERLAY_YUV411: 556 return 1; 557 default: 558 return -EINVAL; 559 } 560 } 561 562 static u32 calc_swidthsw(struct intel_display *display, u32 offset, u32 width) 563 { 564 u32 sw; 565 566 if (DISPLAY_VER(display) == 2) 567 sw = ALIGN((offset & 31) + width, 32); 568 else 569 sw = ALIGN((offset & 63) + width, 64); 570 571 if (sw == 0) 572 return 0; 573 574 return (sw - 32) >> 3; 575 } 576 577 static const u16 y_static_hcoeffs[N_PHASES][N_HORIZ_Y_TAPS] = { 578 [ 0] = { 0x3000, 0xb4a0, 0x1930, 0x1920, 0xb4a0, }, 579 [ 1] = { 0x3000, 0xb500, 0x19d0, 0x1880, 0xb440, }, 580 [ 2] = { 0x3000, 0xb540, 0x1a88, 0x2f80, 0xb3e0, }, 581 [ 3] = { 0x3000, 0xb580, 0x1b30, 0x2e20, 0xb380, }, 582 [ 4] = { 0x3000, 0xb5c0, 0x1bd8, 0x2cc0, 0xb320, }, 583 [ 5] = { 0x3020, 0xb5e0, 0x1c60, 0x2b80, 0xb2c0, }, 584 [ 6] = { 0x3020, 0xb5e0, 0x1cf8, 0x2a20, 0xb260, }, 585 [ 7] = { 0x3020, 0xb5e0, 0x1d80, 0x28e0, 0xb200, }, 586 [ 8] = { 0x3020, 0xb5c0, 0x1e08, 0x3f40, 0xb1c0, }, 587 [ 9] = { 0x3020, 0xb580, 0x1e78, 0x3ce0, 0xb160, }, 588 [10] = { 0x3040, 0xb520, 0x1ed8, 0x3aa0, 0xb120, }, 589 [11] = { 0x3040, 0xb4a0, 0x1f30, 0x3880, 0xb0e0, }, 590 [12] = { 0x3040, 0xb400, 0x1f78, 0x3680, 0xb0a0, }, 591 [13] = { 0x3020, 0xb340, 0x1fb8, 0x34a0, 0xb060, }, 592 [14] = { 0x3020, 0xb240, 0x1fe0, 0x32e0, 0xb040, }, 593 [15] = { 0x3020, 0xb140, 0x1ff8, 0x3160, 0xb020, }, 594 [16] = { 0xb000, 0x3000, 0x0800, 0x3000, 0xb000, }, 595 }; 596 597 static const u16 uv_static_hcoeffs[N_PHASES][N_HORIZ_UV_TAPS] = { 598 [ 0] = { 0x3000, 0x1800, 0x1800, }, 599 [ 1] = { 0xb000, 0x18d0, 0x2e60, }, 600 [ 2] = { 0xb000, 0x1990, 0x2ce0, }, 601 [ 3] = { 0xb020, 0x1a68, 0x2b40, }, 602 [ 4] = { 0xb040, 0x1b20, 0x29e0, }, 603 [ 5] = { 0xb060, 0x1bd8, 0x2880, }, 604 [ 6] = { 0xb080, 0x1c88, 0x3e60, }, 605 [ 7] = { 0xb0a0, 0x1d28, 0x3c00, }, 606 [ 8] = { 0xb0c0, 0x1db8, 0x39e0, }, 607 [ 9] = { 0xb0e0, 0x1e40, 0x37e0, }, 608 [10] = { 0xb100, 0x1eb8, 0x3620, }, 609 [11] = { 0xb100, 0x1f18, 0x34a0, }, 610 [12] = { 0xb100, 0x1f68, 0x3360, }, 611 [13] = { 0xb0e0, 0x1fa8, 0x3240, }, 612 [14] = { 0xb0c0, 0x1fe0, 0x3140, }, 613 [15] = { 0xb060, 0x1ff0, 0x30a0, }, 614 [16] = { 0x3000, 0x0800, 0x3000, }, 615 }; 616 617 static void update_polyphase_filter(struct overlay_registers __iomem *regs) 618 { 619 memcpy_toio(regs->Y_HCOEFS, y_static_hcoeffs, sizeof(y_static_hcoeffs)); 620 memcpy_toio(regs->UV_HCOEFS, uv_static_hcoeffs, 621 sizeof(uv_static_hcoeffs)); 622 } 623 624 static bool update_scaling_factors(struct intel_overlay *overlay, 625 struct overlay_registers __iomem *regs, 626 struct drm_intel_overlay_put_image *params) 627 { 628 /* fixed point with a 12 bit shift */ 629 u32 xscale, yscale, xscale_UV, yscale_UV; 630 #define FP_SHIFT 12 631 #define FRACT_MASK 0xfff 632 bool scale_changed = false; 633 int uv_hscale = uv_hsubsampling(params->flags); 634 int uv_vscale = uv_vsubsampling(params->flags); 635 636 if (params->dst_width > 1) 637 xscale = ((params->src_scan_width - 1) << FP_SHIFT) / 638 params->dst_width; 639 else 640 xscale = 1 << FP_SHIFT; 641 642 if (params->dst_height > 1) 643 yscale = ((params->src_scan_height - 1) << FP_SHIFT) / 644 params->dst_height; 645 else 646 yscale = 1 << FP_SHIFT; 647 648 /*if (params->format & I915_OVERLAY_YUV_PLANAR) {*/ 649 xscale_UV = xscale/uv_hscale; 650 yscale_UV = yscale/uv_vscale; 651 /* make the Y scale to UV scale ratio an exact multiply */ 652 xscale = xscale_UV * uv_hscale; 653 yscale = yscale_UV * uv_vscale; 654 /*} else { 655 xscale_UV = 0; 656 yscale_UV = 0; 657 }*/ 658 659 if (xscale != overlay->old_xscale || yscale != overlay->old_yscale) 660 scale_changed = true; 661 overlay->old_xscale = xscale; 662 overlay->old_yscale = yscale; 663 664 iowrite32(((yscale & FRACT_MASK) << 20) | 665 ((xscale >> FP_SHIFT) << 16) | 666 ((xscale & FRACT_MASK) << 3), 667 ®s->YRGBSCALE); 668 669 iowrite32(((yscale_UV & FRACT_MASK) << 20) | 670 ((xscale_UV >> FP_SHIFT) << 16) | 671 ((xscale_UV & FRACT_MASK) << 3), 672 ®s->UVSCALE); 673 674 iowrite32((((yscale >> FP_SHIFT) << 16) | 675 ((yscale_UV >> FP_SHIFT) << 0)), 676 ®s->UVSCALEV); 677 678 if (scale_changed) 679 update_polyphase_filter(regs); 680 681 return scale_changed; 682 } 683 684 static void update_colorkey(struct intel_overlay *overlay, 685 struct overlay_registers __iomem *regs) 686 { 687 const struct intel_plane_state *state = 688 to_intel_plane_state(overlay->crtc->base.primary->state); 689 u32 key = overlay->color_key; 690 u32 format = 0; 691 u32 flags = 0; 692 693 if (overlay->color_key_enabled) 694 flags |= DST_KEY_ENABLE; 695 696 if (state->uapi.visible) 697 format = state->hw.fb->format->format; 698 699 switch (format) { 700 case DRM_FORMAT_C8: 701 key = RGB8I_TO_COLORKEY(key); 702 flags |= CLK_RGB24_MASK; 703 break; 704 case DRM_FORMAT_XRGB1555: 705 key = RGB15_TO_COLORKEY(key); 706 flags |= CLK_RGB15_MASK; 707 break; 708 case DRM_FORMAT_RGB565: 709 key = RGB16_TO_COLORKEY(key); 710 flags |= CLK_RGB16_MASK; 711 break; 712 case DRM_FORMAT_XRGB2101010: 713 case DRM_FORMAT_XBGR2101010: 714 key = RGB30_TO_COLORKEY(key); 715 flags |= CLK_RGB24_MASK; 716 break; 717 default: 718 flags |= CLK_RGB24_MASK; 719 break; 720 } 721 722 iowrite32(key, ®s->DCLRKV); 723 iowrite32(flags, ®s->DCLRKM); 724 } 725 726 static u32 overlay_cmd_reg(struct drm_intel_overlay_put_image *params) 727 { 728 u32 cmd = OCMD_ENABLE | OCMD_BUF_TYPE_FRAME | OCMD_BUFFER0; 729 730 if (params->flags & I915_OVERLAY_YUV_PLANAR) { 731 switch (params->flags & I915_OVERLAY_DEPTH_MASK) { 732 case I915_OVERLAY_YUV422: 733 cmd |= OCMD_YUV_422_PLANAR; 734 break; 735 case I915_OVERLAY_YUV420: 736 cmd |= OCMD_YUV_420_PLANAR; 737 break; 738 case I915_OVERLAY_YUV411: 739 case I915_OVERLAY_YUV410: 740 cmd |= OCMD_YUV_410_PLANAR; 741 break; 742 } 743 } else { /* YUV packed */ 744 switch (params->flags & I915_OVERLAY_DEPTH_MASK) { 745 case I915_OVERLAY_YUV422: 746 cmd |= OCMD_YUV_422_PACKED; 747 break; 748 case I915_OVERLAY_YUV411: 749 cmd |= OCMD_YUV_411_PACKED; 750 break; 751 } 752 753 switch (params->flags & I915_OVERLAY_SWAP_MASK) { 754 case I915_OVERLAY_NO_SWAP: 755 break; 756 case I915_OVERLAY_UV_SWAP: 757 cmd |= OCMD_UV_SWAP; 758 break; 759 case I915_OVERLAY_Y_SWAP: 760 cmd |= OCMD_Y_SWAP; 761 break; 762 case I915_OVERLAY_Y_AND_UV_SWAP: 763 cmd |= OCMD_Y_AND_UV_SWAP; 764 break; 765 } 766 } 767 768 return cmd; 769 } 770 771 static struct i915_vma *intel_overlay_pin_fb(struct drm_i915_gem_object *new_bo) 772 { 773 struct i915_gem_ww_ctx ww; 774 struct i915_vma *vma; 775 int ret; 776 777 i915_gem_ww_ctx_init(&ww, true); 778 retry: 779 ret = i915_gem_object_lock(new_bo, &ww); 780 if (!ret) { 781 vma = i915_gem_object_pin_to_display_plane(new_bo, &ww, 0, 0, 782 NULL, PIN_MAPPABLE); 783 ret = PTR_ERR_OR_ZERO(vma); 784 } 785 if (ret == -EDEADLK) { 786 ret = i915_gem_ww_ctx_backoff(&ww); 787 if (!ret) 788 goto retry; 789 } 790 i915_gem_ww_ctx_fini(&ww); 791 if (ret) 792 return ERR_PTR(ret); 793 794 return vma; 795 } 796 797 static int intel_overlay_do_put_image(struct intel_overlay *overlay, 798 struct drm_i915_gem_object *new_bo, 799 struct drm_intel_overlay_put_image *params) 800 { 801 struct intel_display *display = overlay->display; 802 struct overlay_registers __iomem *regs = overlay->regs; 803 u32 swidth, swidthsw, sheight, ostride; 804 enum pipe pipe = overlay->crtc->pipe; 805 bool scale_changed = false; 806 struct i915_vma *vma; 807 int ret, tmp_width; 808 809 drm_WARN_ON(display->drm, 810 !drm_modeset_is_locked(&display->drm->mode_config.connection_mutex)); 811 812 ret = intel_overlay_release_old_vid(overlay); 813 if (ret != 0) 814 return ret; 815 816 atomic_inc(&display->restore.pending_fb_pin); 817 818 vma = intel_overlay_pin_fb(new_bo); 819 if (IS_ERR(vma)) { 820 ret = PTR_ERR(vma); 821 goto out_pin_section; 822 } 823 824 i915_gem_object_flush_frontbuffer(new_bo, ORIGIN_DIRTYFB); 825 826 if (!overlay->active) { 827 const struct intel_crtc_state *crtc_state = 828 overlay->crtc->config; 829 u32 oconfig = 0; 830 831 if (crtc_state->gamma_enable && 832 crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT) 833 oconfig |= OCONF_CC_OUT_8BIT; 834 if (crtc_state->gamma_enable) 835 oconfig |= OCONF_GAMMA2_ENABLE; 836 if (DISPLAY_VER(display) == 4) 837 oconfig |= OCONF_CSC_MODE_BT709; 838 oconfig |= pipe == 0 ? 839 OCONF_PIPE_A : OCONF_PIPE_B; 840 iowrite32(oconfig, ®s->OCONFIG); 841 842 ret = intel_overlay_on(overlay); 843 if (ret != 0) 844 goto out_unpin; 845 } 846 847 iowrite32(params->dst_y << 16 | params->dst_x, ®s->DWINPOS); 848 iowrite32(params->dst_height << 16 | params->dst_width, ®s->DWINSZ); 849 850 if (params->flags & I915_OVERLAY_YUV_PACKED) 851 tmp_width = packed_width_bytes(params->flags, 852 params->src_width); 853 else 854 tmp_width = params->src_width; 855 856 swidth = params->src_width; 857 swidthsw = calc_swidthsw(display, params->offset_Y, tmp_width); 858 sheight = params->src_height; 859 iowrite32(i915_ggtt_offset(vma) + params->offset_Y, ®s->OBUF_0Y); 860 ostride = params->stride_Y; 861 862 if (params->flags & I915_OVERLAY_YUV_PLANAR) { 863 int uv_hscale = uv_hsubsampling(params->flags); 864 int uv_vscale = uv_vsubsampling(params->flags); 865 u32 tmp_U, tmp_V; 866 867 swidth |= (params->src_width / uv_hscale) << 16; 868 sheight |= (params->src_height / uv_vscale) << 16; 869 870 tmp_U = calc_swidthsw(display, params->offset_U, 871 params->src_width / uv_hscale); 872 tmp_V = calc_swidthsw(display, params->offset_V, 873 params->src_width / uv_hscale); 874 swidthsw |= max(tmp_U, tmp_V) << 16; 875 876 iowrite32(i915_ggtt_offset(vma) + params->offset_U, 877 ®s->OBUF_0U); 878 iowrite32(i915_ggtt_offset(vma) + params->offset_V, 879 ®s->OBUF_0V); 880 881 ostride |= params->stride_UV << 16; 882 } 883 884 iowrite32(swidth, ®s->SWIDTH); 885 iowrite32(swidthsw, ®s->SWIDTHSW); 886 iowrite32(sheight, ®s->SHEIGHT); 887 iowrite32(ostride, ®s->OSTRIDE); 888 889 scale_changed = update_scaling_factors(overlay, regs, params); 890 891 update_colorkey(overlay, regs); 892 893 iowrite32(overlay_cmd_reg(params), ®s->OCMD); 894 895 ret = intel_overlay_continue(overlay, vma, scale_changed); 896 if (ret) 897 goto out_unpin; 898 899 return 0; 900 901 out_unpin: 902 i915_vma_unpin(vma); 903 out_pin_section: 904 atomic_dec(&display->restore.pending_fb_pin); 905 906 return ret; 907 } 908 909 int intel_overlay_switch_off(struct intel_overlay *overlay) 910 { 911 struct intel_display *display = overlay->display; 912 int ret; 913 914 drm_WARN_ON(display->drm, 915 !drm_modeset_is_locked(&display->drm->mode_config.connection_mutex)); 916 917 ret = intel_overlay_recover_from_interrupt(overlay); 918 if (ret != 0) 919 return ret; 920 921 if (!overlay->active) 922 return 0; 923 924 ret = intel_overlay_release_old_vid(overlay); 925 if (ret != 0) 926 return ret; 927 928 iowrite32(0, &overlay->regs->OCMD); 929 930 return intel_overlay_off(overlay); 931 } 932 933 static int check_overlay_possible_on_crtc(struct intel_overlay *overlay, 934 struct intel_crtc *crtc) 935 { 936 if (!crtc->active) 937 return -EINVAL; 938 939 /* can't use the overlay with double wide pipe */ 940 if (crtc->config->double_wide) 941 return -EINVAL; 942 943 return 0; 944 } 945 946 static void update_pfit_vscale_ratio(struct intel_overlay *overlay) 947 { 948 struct intel_display *display = overlay->display; 949 u32 ratio; 950 951 /* XXX: This is not the same logic as in the xorg driver, but more in 952 * line with the intel documentation for the i965 953 */ 954 if (DISPLAY_VER(display) >= 4) { 955 u32 tmp = intel_de_read(display, PFIT_PGM_RATIOS(display)); 956 957 /* on i965 use the PGM reg to read out the autoscaler values */ 958 ratio = REG_FIELD_GET(PFIT_VERT_SCALE_MASK_965, tmp); 959 } else { 960 u32 tmp; 961 962 if (intel_de_read(display, PFIT_CONTROL(display)) & PFIT_VERT_AUTO_SCALE) 963 tmp = intel_de_read(display, PFIT_AUTO_RATIOS(display)); 964 else 965 tmp = intel_de_read(display, PFIT_PGM_RATIOS(display)); 966 967 ratio = REG_FIELD_GET(PFIT_VERT_SCALE_MASK, tmp); 968 } 969 970 overlay->pfit_vscale_ratio = ratio; 971 } 972 973 static int check_overlay_dst(struct intel_overlay *overlay, 974 struct drm_intel_overlay_put_image *rec) 975 { 976 const struct intel_crtc_state *crtc_state = 977 overlay->crtc->config; 978 struct drm_rect req, clipped; 979 980 drm_rect_init(&req, rec->dst_x, rec->dst_y, 981 rec->dst_width, rec->dst_height); 982 983 clipped = req; 984 985 if (!drm_rect_intersect(&clipped, &crtc_state->pipe_src)) 986 return -EINVAL; 987 988 if (!drm_rect_equals(&clipped, &req)) 989 return -EINVAL; 990 991 return 0; 992 } 993 994 static int check_overlay_scaling(struct drm_intel_overlay_put_image *rec) 995 { 996 u32 tmp; 997 998 /* downscaling limit is 8.0 */ 999 tmp = ((rec->src_scan_height << 16) / rec->dst_height) >> 16; 1000 if (tmp > 7) 1001 return -EINVAL; 1002 1003 tmp = ((rec->src_scan_width << 16) / rec->dst_width) >> 16; 1004 if (tmp > 7) 1005 return -EINVAL; 1006 1007 return 0; 1008 } 1009 1010 static int check_overlay_src(struct intel_display *display, 1011 struct drm_intel_overlay_put_image *rec, 1012 struct drm_i915_gem_object *new_bo) 1013 { 1014 int uv_hscale = uv_hsubsampling(rec->flags); 1015 int uv_vscale = uv_vsubsampling(rec->flags); 1016 u32 stride_mask; 1017 int depth; 1018 u32 tmp; 1019 1020 /* check src dimensions */ 1021 if (display->platform.i845g || display->platform.i830) { 1022 if (rec->src_height > IMAGE_MAX_HEIGHT_LEGACY || 1023 rec->src_width > IMAGE_MAX_WIDTH_LEGACY) 1024 return -EINVAL; 1025 } else { 1026 if (rec->src_height > IMAGE_MAX_HEIGHT || 1027 rec->src_width > IMAGE_MAX_WIDTH) 1028 return -EINVAL; 1029 } 1030 1031 /* better safe than sorry, use 4 as the maximal subsampling ratio */ 1032 if (rec->src_height < N_VERT_Y_TAPS*4 || 1033 rec->src_width < N_HORIZ_Y_TAPS*4) 1034 return -EINVAL; 1035 1036 /* check alignment constraints */ 1037 switch (rec->flags & I915_OVERLAY_TYPE_MASK) { 1038 case I915_OVERLAY_RGB: 1039 /* not implemented */ 1040 return -EINVAL; 1041 1042 case I915_OVERLAY_YUV_PACKED: 1043 if (uv_vscale != 1) 1044 return -EINVAL; 1045 1046 depth = packed_depth_bytes(rec->flags); 1047 if (depth < 0) 1048 return depth; 1049 1050 /* ignore UV planes */ 1051 rec->stride_UV = 0; 1052 rec->offset_U = 0; 1053 rec->offset_V = 0; 1054 /* check pixel alignment */ 1055 if (rec->offset_Y % depth) 1056 return -EINVAL; 1057 break; 1058 1059 case I915_OVERLAY_YUV_PLANAR: 1060 if (uv_vscale < 0 || uv_hscale < 0) 1061 return -EINVAL; 1062 /* no offset restrictions for planar formats */ 1063 break; 1064 1065 default: 1066 return -EINVAL; 1067 } 1068 1069 if (rec->src_width % uv_hscale) 1070 return -EINVAL; 1071 1072 /* stride checking */ 1073 if (display->platform.i830 || display->platform.i845g) 1074 stride_mask = 255; 1075 else 1076 stride_mask = 63; 1077 1078 if (rec->stride_Y & stride_mask || rec->stride_UV & stride_mask) 1079 return -EINVAL; 1080 if (DISPLAY_VER(display) == 4 && rec->stride_Y < 512) 1081 return -EINVAL; 1082 1083 tmp = (rec->flags & I915_OVERLAY_TYPE_MASK) == I915_OVERLAY_YUV_PLANAR ? 1084 4096 : 8192; 1085 if (rec->stride_Y > tmp || rec->stride_UV > 2*1024) 1086 return -EINVAL; 1087 1088 /* check buffer dimensions */ 1089 switch (rec->flags & I915_OVERLAY_TYPE_MASK) { 1090 case I915_OVERLAY_RGB: 1091 case I915_OVERLAY_YUV_PACKED: 1092 /* always 4 Y values per depth pixels */ 1093 if (packed_width_bytes(rec->flags, rec->src_width) > rec->stride_Y) 1094 return -EINVAL; 1095 1096 tmp = rec->stride_Y*rec->src_height; 1097 if (rec->offset_Y + tmp > new_bo->base.size) 1098 return -EINVAL; 1099 break; 1100 1101 case I915_OVERLAY_YUV_PLANAR: 1102 if (rec->src_width > rec->stride_Y) 1103 return -EINVAL; 1104 if (rec->src_width/uv_hscale > rec->stride_UV) 1105 return -EINVAL; 1106 1107 tmp = rec->stride_Y * rec->src_height; 1108 if (rec->offset_Y + tmp > new_bo->base.size) 1109 return -EINVAL; 1110 1111 tmp = rec->stride_UV * (rec->src_height / uv_vscale); 1112 if (rec->offset_U + tmp > new_bo->base.size || 1113 rec->offset_V + tmp > new_bo->base.size) 1114 return -EINVAL; 1115 break; 1116 } 1117 1118 return 0; 1119 } 1120 1121 int intel_overlay_put_image_ioctl(struct drm_device *dev, void *data, 1122 struct drm_file *file_priv) 1123 { 1124 struct intel_display *display = to_intel_display(dev); 1125 struct drm_intel_overlay_put_image *params = data; 1126 struct intel_overlay *overlay; 1127 struct drm_crtc *drmmode_crtc; 1128 struct intel_crtc *crtc; 1129 struct drm_i915_gem_object *new_bo; 1130 int ret; 1131 1132 overlay = display->overlay; 1133 if (!overlay) { 1134 drm_dbg(display->drm, "userspace bug: no overlay\n"); 1135 return -ENODEV; 1136 } 1137 1138 if (!(params->flags & I915_OVERLAY_ENABLE)) { 1139 drm_modeset_lock_all(dev); 1140 ret = intel_overlay_switch_off(overlay); 1141 drm_modeset_unlock_all(dev); 1142 1143 return ret; 1144 } 1145 1146 drmmode_crtc = drm_crtc_find(dev, file_priv, params->crtc_id); 1147 if (!drmmode_crtc) 1148 return -ENOENT; 1149 crtc = to_intel_crtc(drmmode_crtc); 1150 1151 new_bo = i915_gem_object_lookup(file_priv, params->bo_handle); 1152 if (!new_bo) 1153 return -ENOENT; 1154 1155 drm_modeset_lock_all(dev); 1156 1157 if (i915_gem_object_is_tiled(new_bo)) { 1158 drm_dbg_kms(display->drm, 1159 "buffer used for overlay image can not be tiled\n"); 1160 ret = -EINVAL; 1161 goto out_unlock; 1162 } 1163 1164 ret = intel_overlay_recover_from_interrupt(overlay); 1165 if (ret != 0) 1166 goto out_unlock; 1167 1168 if (overlay->crtc != crtc) { 1169 ret = intel_overlay_switch_off(overlay); 1170 if (ret != 0) 1171 goto out_unlock; 1172 1173 ret = check_overlay_possible_on_crtc(overlay, crtc); 1174 if (ret != 0) 1175 goto out_unlock; 1176 1177 overlay->crtc = crtc; 1178 crtc->overlay = overlay; 1179 1180 /* line too wide, i.e. one-line-mode */ 1181 if (drm_rect_width(&crtc->config->pipe_src) > 1024 && 1182 crtc->config->gmch_pfit.control & PFIT_ENABLE) { 1183 overlay->pfit_active = true; 1184 update_pfit_vscale_ratio(overlay); 1185 } else 1186 overlay->pfit_active = false; 1187 } 1188 1189 ret = check_overlay_dst(overlay, params); 1190 if (ret != 0) 1191 goto out_unlock; 1192 1193 if (overlay->pfit_active) { 1194 params->dst_y = (((u32)params->dst_y << 12) / 1195 overlay->pfit_vscale_ratio); 1196 /* shifting right rounds downwards, so add 1 */ 1197 params->dst_height = (((u32)params->dst_height << 12) / 1198 overlay->pfit_vscale_ratio) + 1; 1199 } 1200 1201 if (params->src_scan_height > params->src_height || 1202 params->src_scan_width > params->src_width) { 1203 ret = -EINVAL; 1204 goto out_unlock; 1205 } 1206 1207 ret = check_overlay_src(display, params, new_bo); 1208 if (ret != 0) 1209 goto out_unlock; 1210 1211 /* Check scaling after src size to prevent a divide-by-zero. */ 1212 ret = check_overlay_scaling(params); 1213 if (ret != 0) 1214 goto out_unlock; 1215 1216 ret = intel_overlay_do_put_image(overlay, new_bo, params); 1217 if (ret != 0) 1218 goto out_unlock; 1219 1220 drm_modeset_unlock_all(dev); 1221 i915_gem_object_put(new_bo); 1222 1223 return 0; 1224 1225 out_unlock: 1226 drm_modeset_unlock_all(dev); 1227 i915_gem_object_put(new_bo); 1228 1229 return ret; 1230 } 1231 1232 static void update_reg_attrs(struct intel_overlay *overlay, 1233 struct overlay_registers __iomem *regs) 1234 { 1235 iowrite32((overlay->contrast << 18) | (overlay->brightness & 0xff), 1236 ®s->OCLRC0); 1237 iowrite32(overlay->saturation, ®s->OCLRC1); 1238 } 1239 1240 static bool check_gamma_bounds(u32 gamma1, u32 gamma2) 1241 { 1242 int i; 1243 1244 if (gamma1 & 0xff000000 || gamma2 & 0xff000000) 1245 return false; 1246 1247 for (i = 0; i < 3; i++) { 1248 if (((gamma1 >> i*8) & 0xff) >= ((gamma2 >> i*8) & 0xff)) 1249 return false; 1250 } 1251 1252 return true; 1253 } 1254 1255 static bool check_gamma5_errata(u32 gamma5) 1256 { 1257 int i; 1258 1259 for (i = 0; i < 3; i++) { 1260 if (((gamma5 >> i*8) & 0xff) == 0x80) 1261 return false; 1262 } 1263 1264 return true; 1265 } 1266 1267 static int check_gamma(struct drm_intel_overlay_attrs *attrs) 1268 { 1269 if (!check_gamma_bounds(0, attrs->gamma0) || 1270 !check_gamma_bounds(attrs->gamma0, attrs->gamma1) || 1271 !check_gamma_bounds(attrs->gamma1, attrs->gamma2) || 1272 !check_gamma_bounds(attrs->gamma2, attrs->gamma3) || 1273 !check_gamma_bounds(attrs->gamma3, attrs->gamma4) || 1274 !check_gamma_bounds(attrs->gamma4, attrs->gamma5) || 1275 !check_gamma_bounds(attrs->gamma5, 0x00ffffff)) 1276 return -EINVAL; 1277 1278 if (!check_gamma5_errata(attrs->gamma5)) 1279 return -EINVAL; 1280 1281 return 0; 1282 } 1283 1284 int intel_overlay_attrs_ioctl(struct drm_device *dev, void *data, 1285 struct drm_file *file_priv) 1286 { 1287 struct intel_display *display = to_intel_display(dev); 1288 struct drm_intel_overlay_attrs *attrs = data; 1289 struct intel_overlay *overlay; 1290 int ret; 1291 1292 overlay = display->overlay; 1293 if (!overlay) { 1294 drm_dbg(display->drm, "userspace bug: no overlay\n"); 1295 return -ENODEV; 1296 } 1297 1298 drm_modeset_lock_all(dev); 1299 1300 ret = -EINVAL; 1301 if (!(attrs->flags & I915_OVERLAY_UPDATE_ATTRS)) { 1302 attrs->color_key = overlay->color_key; 1303 attrs->brightness = overlay->brightness; 1304 attrs->contrast = overlay->contrast; 1305 attrs->saturation = overlay->saturation; 1306 1307 if (DISPLAY_VER(display) != 2) { 1308 attrs->gamma0 = intel_de_read(display, OGAMC0); 1309 attrs->gamma1 = intel_de_read(display, OGAMC1); 1310 attrs->gamma2 = intel_de_read(display, OGAMC2); 1311 attrs->gamma3 = intel_de_read(display, OGAMC3); 1312 attrs->gamma4 = intel_de_read(display, OGAMC4); 1313 attrs->gamma5 = intel_de_read(display, OGAMC5); 1314 } 1315 } else { 1316 if (attrs->brightness < -128 || attrs->brightness > 127) 1317 goto out_unlock; 1318 if (attrs->contrast > 255) 1319 goto out_unlock; 1320 if (attrs->saturation > 1023) 1321 goto out_unlock; 1322 1323 overlay->color_key = attrs->color_key; 1324 overlay->brightness = attrs->brightness; 1325 overlay->contrast = attrs->contrast; 1326 overlay->saturation = attrs->saturation; 1327 1328 update_reg_attrs(overlay, overlay->regs); 1329 1330 if (attrs->flags & I915_OVERLAY_UPDATE_GAMMA) { 1331 if (DISPLAY_VER(display) == 2) 1332 goto out_unlock; 1333 1334 if (overlay->active) { 1335 ret = -EBUSY; 1336 goto out_unlock; 1337 } 1338 1339 ret = check_gamma(attrs); 1340 if (ret) 1341 goto out_unlock; 1342 1343 intel_de_write(display, OGAMC0, attrs->gamma0); 1344 intel_de_write(display, OGAMC1, attrs->gamma1); 1345 intel_de_write(display, OGAMC2, attrs->gamma2); 1346 intel_de_write(display, OGAMC3, attrs->gamma3); 1347 intel_de_write(display, OGAMC4, attrs->gamma4); 1348 intel_de_write(display, OGAMC5, attrs->gamma5); 1349 } 1350 } 1351 overlay->color_key_enabled = (attrs->flags & I915_OVERLAY_DISABLE_DEST_COLORKEY) == 0; 1352 1353 ret = 0; 1354 out_unlock: 1355 drm_modeset_unlock_all(dev); 1356 1357 return ret; 1358 } 1359 1360 static int get_registers(struct intel_overlay *overlay, bool use_phys) 1361 { 1362 struct intel_display *display = overlay->display; 1363 struct drm_i915_private *i915 = to_i915(display->drm); 1364 struct drm_i915_gem_object *obj = ERR_PTR(-ENODEV); 1365 struct i915_vma *vma; 1366 int err; 1367 1368 if (!display->platform.meteorlake) /* Wa_22018444074 */ 1369 obj = i915_gem_object_create_stolen(i915, PAGE_SIZE); 1370 if (IS_ERR(obj)) 1371 obj = i915_gem_object_create_internal(i915, PAGE_SIZE); 1372 if (IS_ERR(obj)) 1373 return PTR_ERR(obj); 1374 1375 vma = i915_gem_object_ggtt_pin(obj, NULL, 0, 0, PIN_MAPPABLE); 1376 if (IS_ERR(vma)) { 1377 err = PTR_ERR(vma); 1378 goto err_put_bo; 1379 } 1380 1381 if (use_phys) 1382 overlay->flip_addr = sg_dma_address(obj->mm.pages->sgl); 1383 else 1384 overlay->flip_addr = i915_ggtt_offset(vma); 1385 overlay->regs = i915_vma_pin_iomap(vma); 1386 i915_vma_unpin(vma); 1387 1388 if (IS_ERR(overlay->regs)) { 1389 err = PTR_ERR(overlay->regs); 1390 goto err_put_bo; 1391 } 1392 1393 overlay->reg_bo = obj; 1394 return 0; 1395 1396 err_put_bo: 1397 i915_gem_object_put(obj); 1398 return err; 1399 } 1400 1401 void intel_overlay_setup(struct intel_display *display) 1402 { 1403 struct drm_i915_private *dev_priv = to_i915(display->drm); 1404 struct intel_overlay *overlay; 1405 struct intel_engine_cs *engine; 1406 int ret; 1407 1408 if (!HAS_OVERLAY(display)) 1409 return; 1410 1411 engine = to_gt(dev_priv)->engine[RCS0]; 1412 if (!engine || !engine->kernel_context) 1413 return; 1414 1415 overlay = kzalloc(sizeof(*overlay), GFP_KERNEL); 1416 if (!overlay) 1417 return; 1418 1419 overlay->display = display; 1420 overlay->context = engine->kernel_context; 1421 overlay->color_key = 0x0101fe; 1422 overlay->color_key_enabled = true; 1423 overlay->brightness = -19; 1424 overlay->contrast = 75; 1425 overlay->saturation = 146; 1426 1427 i915_active_init(&overlay->last_flip, 1428 NULL, intel_overlay_last_flip_retire, 0); 1429 1430 ret = get_registers(overlay, OVERLAY_NEEDS_PHYSICAL(display)); 1431 if (ret) 1432 goto out_free; 1433 1434 memset_io(overlay->regs, 0, sizeof(struct overlay_registers)); 1435 update_polyphase_filter(overlay->regs); 1436 update_reg_attrs(overlay, overlay->regs); 1437 1438 display->overlay = overlay; 1439 drm_info(display->drm, "Initialized overlay support.\n"); 1440 return; 1441 1442 out_free: 1443 kfree(overlay); 1444 } 1445 1446 bool intel_overlay_available(struct intel_display *display) 1447 { 1448 return display->overlay; 1449 } 1450 1451 void intel_overlay_cleanup(struct intel_display *display) 1452 { 1453 struct intel_overlay *overlay; 1454 1455 overlay = fetch_and_zero(&display->overlay); 1456 if (!overlay) 1457 return; 1458 1459 /* 1460 * The bo's should be free'd by the generic code already. 1461 * Furthermore modesetting teardown happens beforehand so the 1462 * hardware should be off already. 1463 */ 1464 drm_WARN_ON(display->drm, overlay->active); 1465 1466 i915_gem_object_put(overlay->reg_bo); 1467 i915_active_fini(&overlay->last_flip); 1468 1469 kfree(overlay); 1470 } 1471 1472 #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR) 1473 1474 struct intel_overlay_snapshot { 1475 struct overlay_registers regs; 1476 unsigned long base; 1477 u32 dovsta; 1478 u32 isr; 1479 }; 1480 1481 struct intel_overlay_snapshot * 1482 intel_overlay_snapshot_capture(struct intel_display *display) 1483 { 1484 struct intel_overlay *overlay = display->overlay; 1485 struct intel_overlay_snapshot *error; 1486 1487 if (!overlay || !overlay->active) 1488 return NULL; 1489 1490 error = kmalloc(sizeof(*error), GFP_ATOMIC); 1491 if (error == NULL) 1492 return NULL; 1493 1494 error->dovsta = intel_de_read(display, DOVSTA); 1495 error->isr = intel_de_read(display, GEN2_ISR); 1496 error->base = overlay->flip_addr; 1497 1498 memcpy_fromio(&error->regs, overlay->regs, sizeof(error->regs)); 1499 1500 return error; 1501 } 1502 1503 void 1504 intel_overlay_snapshot_print(const struct intel_overlay_snapshot *error, 1505 struct drm_printer *p) 1506 { 1507 if (!error) 1508 return; 1509 1510 drm_printf(p, "Overlay, status: 0x%08x, interrupt: 0x%08x\n", 1511 error->dovsta, error->isr); 1512 drm_printf(p, " Register file at 0x%08lx:\n", error->base); 1513 1514 #define P(x) drm_printf(p, " " #x ": 0x%08x\n", error->regs.x) 1515 P(OBUF_0Y); 1516 P(OBUF_1Y); 1517 P(OBUF_0U); 1518 P(OBUF_0V); 1519 P(OBUF_1U); 1520 P(OBUF_1V); 1521 P(OSTRIDE); 1522 P(YRGB_VPH); 1523 P(UV_VPH); 1524 P(HORZ_PH); 1525 P(INIT_PHS); 1526 P(DWINPOS); 1527 P(DWINSZ); 1528 P(SWIDTH); 1529 P(SWIDTHSW); 1530 P(SHEIGHT); 1531 P(YRGBSCALE); 1532 P(UVSCALE); 1533 P(OCLRC0); 1534 P(OCLRC1); 1535 P(DCLRKV); 1536 P(DCLRKM); 1537 P(SCLRKVH); 1538 P(SCLRKVL); 1539 P(SCLRKEN); 1540 P(OCONFIG); 1541 P(OCMD); 1542 P(OSTART_0Y); 1543 P(OSTART_1Y); 1544 P(OSTART_0U); 1545 P(OSTART_0V); 1546 P(OSTART_1U); 1547 P(OSTART_1V); 1548 P(OTILEOFF_0Y); 1549 P(OTILEOFF_1Y); 1550 P(OTILEOFF_0U); 1551 P(OTILEOFF_0V); 1552 P(OTILEOFF_1U); 1553 P(OTILEOFF_1V); 1554 P(FASTHSCALE); 1555 P(UVSCALEV); 1556 #undef P 1557 } 1558 1559 #endif 1560