1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2022 Intel Corporation 4 * 5 * Read out the current hardware modeset state, and sanitize it to the current 6 * state. 7 */ 8 9 #include <drm/drm_atomic_uapi.h> 10 #include <drm/drm_atomic_state_helper.h> 11 12 #include "i915_drv.h" 13 #include "i915_reg.h" 14 #include "i9xx_wm.h" 15 #include "intel_atomic.h" 16 #include "intel_bw.h" 17 #include "intel_color.h" 18 #include "intel_crtc.h" 19 #include "intel_crtc_state_dump.h" 20 #include "intel_ddi.h" 21 #include "intel_de.h" 22 #include "intel_display.h" 23 #include "intel_display_power.h" 24 #include "intel_display_types.h" 25 #include "intel_dmc.h" 26 #include "intel_fifo_underrun.h" 27 #include "intel_modeset_setup.h" 28 #include "intel_pch_display.h" 29 #include "intel_pmdemand.h" 30 #include "intel_tc.h" 31 #include "intel_vblank.h" 32 #include "intel_wm.h" 33 #include "skl_watermark.h" 34 35 static void intel_crtc_disable_noatomic_begin(struct intel_crtc *crtc, 36 struct drm_modeset_acquire_ctx *ctx) 37 { 38 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 39 struct intel_crtc_state *crtc_state = 40 to_intel_crtc_state(crtc->base.state); 41 struct intel_plane *plane; 42 struct drm_atomic_state *state; 43 struct intel_crtc *temp_crtc; 44 enum pipe pipe = crtc->pipe; 45 46 if (!crtc_state->hw.active) 47 return; 48 49 for_each_intel_plane_on_crtc(&i915->drm, crtc, plane) { 50 const struct intel_plane_state *plane_state = 51 to_intel_plane_state(plane->base.state); 52 53 if (plane_state->uapi.visible) 54 intel_plane_disable_noatomic(crtc, plane); 55 } 56 57 state = drm_atomic_state_alloc(&i915->drm); 58 if (!state) { 59 drm_dbg_kms(&i915->drm, 60 "failed to disable [CRTC:%d:%s], out of memory", 61 crtc->base.base.id, crtc->base.name); 62 return; 63 } 64 65 state->acquire_ctx = ctx; 66 to_intel_atomic_state(state)->internal = true; 67 68 /* Everything's already locked, -EDEADLK can't happen. */ 69 for_each_intel_crtc_in_pipe_mask(&i915->drm, temp_crtc, 70 BIT(pipe) | 71 intel_crtc_joiner_secondary_pipes(crtc_state)) { 72 struct intel_crtc_state *temp_crtc_state = 73 intel_atomic_get_crtc_state(state, temp_crtc); 74 int ret; 75 76 ret = drm_atomic_add_affected_connectors(state, &temp_crtc->base); 77 78 drm_WARN_ON(&i915->drm, IS_ERR(temp_crtc_state) || ret); 79 } 80 81 i915->display.funcs.display->crtc_disable(to_intel_atomic_state(state), crtc); 82 83 drm_atomic_state_put(state); 84 85 drm_dbg_kms(&i915->drm, 86 "[CRTC:%d:%s] hw state adjusted, was enabled, now disabled\n", 87 crtc->base.base.id, crtc->base.name); 88 89 crtc->active = false; 90 crtc->base.enabled = false; 91 92 if (crtc_state->shared_dpll) 93 intel_unreference_shared_dpll_crtc(crtc, 94 crtc_state->shared_dpll, 95 &crtc_state->shared_dpll->state); 96 } 97 98 static void set_encoder_for_connector(struct intel_connector *connector, 99 struct intel_encoder *encoder) 100 { 101 struct drm_connector_state *conn_state = connector->base.state; 102 103 if (conn_state->crtc) 104 drm_connector_put(&connector->base); 105 106 if (encoder) { 107 conn_state->best_encoder = &encoder->base; 108 conn_state->crtc = encoder->base.crtc; 109 drm_connector_get(&connector->base); 110 } else { 111 conn_state->best_encoder = NULL; 112 conn_state->crtc = NULL; 113 } 114 } 115 116 static void reset_encoder_connector_state(struct intel_encoder *encoder) 117 { 118 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 119 struct intel_pmdemand_state *pmdemand_state = 120 to_intel_pmdemand_state(i915->display.pmdemand.obj.state); 121 struct intel_connector *connector; 122 struct drm_connector_list_iter conn_iter; 123 124 drm_connector_list_iter_begin(&i915->drm, &conn_iter); 125 for_each_intel_connector_iter(connector, &conn_iter) { 126 if (connector->base.encoder != &encoder->base) 127 continue; 128 129 /* Clear the corresponding bit in pmdemand active phys mask */ 130 intel_pmdemand_update_phys_mask(i915, encoder, 131 pmdemand_state, false); 132 133 set_encoder_for_connector(connector, NULL); 134 135 connector->base.dpms = DRM_MODE_DPMS_OFF; 136 connector->base.encoder = NULL; 137 } 138 drm_connector_list_iter_end(&conn_iter); 139 } 140 141 static void reset_crtc_encoder_state(struct intel_crtc *crtc) 142 { 143 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 144 struct intel_encoder *encoder; 145 146 for_each_encoder_on_crtc(&i915->drm, &crtc->base, encoder) { 147 reset_encoder_connector_state(encoder); 148 encoder->base.crtc = NULL; 149 } 150 } 151 152 static void intel_crtc_disable_noatomic_complete(struct intel_crtc *crtc) 153 { 154 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 155 struct intel_bw_state *bw_state = 156 to_intel_bw_state(i915->display.bw.obj.state); 157 struct intel_cdclk_state *cdclk_state = 158 to_intel_cdclk_state(i915->display.cdclk.obj.state); 159 struct intel_dbuf_state *dbuf_state = 160 to_intel_dbuf_state(i915->display.dbuf.obj.state); 161 struct intel_pmdemand_state *pmdemand_state = 162 to_intel_pmdemand_state(i915->display.pmdemand.obj.state); 163 struct intel_crtc_state *crtc_state = 164 to_intel_crtc_state(crtc->base.state); 165 enum pipe pipe = crtc->pipe; 166 167 __drm_atomic_helper_crtc_destroy_state(&crtc_state->uapi); 168 intel_crtc_free_hw_state(crtc_state); 169 intel_crtc_state_reset(crtc_state, crtc); 170 171 reset_crtc_encoder_state(crtc); 172 173 intel_fbc_disable(crtc); 174 intel_update_watermarks(i915); 175 176 intel_display_power_put_all_in_set(i915, &crtc->enabled_power_domains); 177 178 cdclk_state->min_cdclk[pipe] = 0; 179 cdclk_state->min_voltage_level[pipe] = 0; 180 cdclk_state->active_pipes &= ~BIT(pipe); 181 182 dbuf_state->active_pipes &= ~BIT(pipe); 183 184 bw_state->data_rate[pipe] = 0; 185 bw_state->num_active_planes[pipe] = 0; 186 187 intel_pmdemand_update_port_clock(i915, pmdemand_state, pipe, 0); 188 } 189 190 /* 191 * Return all the pipes using a transcoder in @transcoder_mask. 192 * For joiner configs return only the joiner primary. 193 */ 194 static u8 get_transcoder_pipes(struct drm_i915_private *i915, 195 u8 transcoder_mask) 196 { 197 struct intel_crtc *temp_crtc; 198 u8 pipes = 0; 199 200 for_each_intel_crtc(&i915->drm, temp_crtc) { 201 struct intel_crtc_state *temp_crtc_state = 202 to_intel_crtc_state(temp_crtc->base.state); 203 204 if (temp_crtc_state->cpu_transcoder == INVALID_TRANSCODER) 205 continue; 206 207 if (intel_crtc_is_joiner_secondary(temp_crtc_state)) 208 continue; 209 210 if (transcoder_mask & BIT(temp_crtc_state->cpu_transcoder)) 211 pipes |= BIT(temp_crtc->pipe); 212 } 213 214 return pipes; 215 } 216 217 /* 218 * Return the port sync master and slave pipes linked to @crtc. 219 * For joiner configs return only the joiner primary pipes. 220 */ 221 static void get_portsync_pipes(struct intel_crtc *crtc, 222 u8 *master_pipe_mask, u8 *slave_pipes_mask) 223 { 224 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 225 struct intel_crtc_state *crtc_state = 226 to_intel_crtc_state(crtc->base.state); 227 struct intel_crtc *master_crtc; 228 struct intel_crtc_state *master_crtc_state; 229 enum transcoder master_transcoder; 230 231 if (!is_trans_port_sync_mode(crtc_state)) { 232 *master_pipe_mask = BIT(crtc->pipe); 233 *slave_pipes_mask = 0; 234 235 return; 236 } 237 238 if (is_trans_port_sync_master(crtc_state)) 239 master_transcoder = crtc_state->cpu_transcoder; 240 else 241 master_transcoder = crtc_state->master_transcoder; 242 243 *master_pipe_mask = get_transcoder_pipes(i915, BIT(master_transcoder)); 244 drm_WARN_ON(&i915->drm, !is_power_of_2(*master_pipe_mask)); 245 246 master_crtc = intel_crtc_for_pipe(i915, ffs(*master_pipe_mask) - 1); 247 master_crtc_state = to_intel_crtc_state(master_crtc->base.state); 248 *slave_pipes_mask = get_transcoder_pipes(i915, master_crtc_state->sync_mode_slaves_mask); 249 } 250 251 static u8 get_joiner_secondary_pipes(struct drm_i915_private *i915, u8 primary_pipes_mask) 252 { 253 struct intel_crtc *primary_crtc; 254 u8 pipes = 0; 255 256 for_each_intel_crtc_in_pipe_mask(&i915->drm, primary_crtc, primary_pipes_mask) { 257 struct intel_crtc_state *primary_crtc_state = 258 to_intel_crtc_state(primary_crtc->base.state); 259 260 pipes |= intel_crtc_joiner_secondary_pipes(primary_crtc_state); 261 } 262 263 return pipes; 264 } 265 266 static void intel_crtc_disable_noatomic(struct intel_crtc *crtc, 267 struct drm_modeset_acquire_ctx *ctx) 268 { 269 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 270 u8 portsync_master_mask; 271 u8 portsync_slaves_mask; 272 u8 joiner_secondaries_mask; 273 struct intel_crtc *temp_crtc; 274 275 /* TODO: Add support for MST */ 276 get_portsync_pipes(crtc, &portsync_master_mask, &portsync_slaves_mask); 277 joiner_secondaries_mask = get_joiner_secondary_pipes(i915, 278 portsync_master_mask | 279 portsync_slaves_mask); 280 281 drm_WARN_ON(&i915->drm, 282 portsync_master_mask & portsync_slaves_mask || 283 portsync_master_mask & joiner_secondaries_mask || 284 portsync_slaves_mask & joiner_secondaries_mask); 285 286 for_each_intel_crtc_in_pipe_mask(&i915->drm, temp_crtc, joiner_secondaries_mask) 287 intel_crtc_disable_noatomic_begin(temp_crtc, ctx); 288 289 for_each_intel_crtc_in_pipe_mask(&i915->drm, temp_crtc, portsync_slaves_mask) 290 intel_crtc_disable_noatomic_begin(temp_crtc, ctx); 291 292 for_each_intel_crtc_in_pipe_mask(&i915->drm, temp_crtc, portsync_master_mask) 293 intel_crtc_disable_noatomic_begin(temp_crtc, ctx); 294 295 for_each_intel_crtc_in_pipe_mask(&i915->drm, temp_crtc, 296 joiner_secondaries_mask | 297 portsync_slaves_mask | 298 portsync_master_mask) 299 intel_crtc_disable_noatomic_complete(temp_crtc); 300 } 301 302 static void intel_modeset_update_connector_atomic_state(struct drm_i915_private *i915) 303 { 304 struct intel_connector *connector; 305 struct drm_connector_list_iter conn_iter; 306 307 drm_connector_list_iter_begin(&i915->drm, &conn_iter); 308 for_each_intel_connector_iter(connector, &conn_iter) { 309 struct drm_connector_state *conn_state = connector->base.state; 310 struct intel_encoder *encoder = 311 to_intel_encoder(connector->base.encoder); 312 313 set_encoder_for_connector(connector, encoder); 314 315 if (encoder) { 316 struct intel_crtc *crtc = 317 to_intel_crtc(encoder->base.crtc); 318 const struct intel_crtc_state *crtc_state = 319 to_intel_crtc_state(crtc->base.state); 320 321 conn_state->max_bpc = (crtc_state->pipe_bpp ?: 24) / 3; 322 } 323 } 324 drm_connector_list_iter_end(&conn_iter); 325 } 326 327 static void intel_crtc_copy_hw_to_uapi_state(struct intel_crtc_state *crtc_state) 328 { 329 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); 330 331 if (intel_crtc_is_joiner_secondary(crtc_state)) 332 return; 333 334 crtc_state->uapi.enable = crtc_state->hw.enable; 335 crtc_state->uapi.active = crtc_state->hw.active; 336 drm_WARN_ON(crtc_state->uapi.crtc->dev, 337 drm_atomic_set_mode_for_crtc(&crtc_state->uapi, &crtc_state->hw.mode) < 0); 338 339 crtc_state->uapi.adjusted_mode = crtc_state->hw.adjusted_mode; 340 crtc_state->uapi.scaling_filter = crtc_state->hw.scaling_filter; 341 342 if (DISPLAY_INFO(i915)->color.degamma_lut_size) { 343 /* assume 1:1 mapping */ 344 drm_property_replace_blob(&crtc_state->hw.degamma_lut, 345 crtc_state->pre_csc_lut); 346 drm_property_replace_blob(&crtc_state->hw.gamma_lut, 347 crtc_state->post_csc_lut); 348 } else { 349 /* 350 * ilk/snb hw may be configured for either pre_csc_lut 351 * or post_csc_lut, but we don't advertise degamma_lut as 352 * being available in the uapi since there is only one 353 * hardware LUT. Always assign the result of the readout 354 * to gamma_lut as that is the only valid source of LUTs 355 * in the uapi. 356 */ 357 drm_WARN_ON(&i915->drm, crtc_state->post_csc_lut && 358 crtc_state->pre_csc_lut); 359 360 drm_property_replace_blob(&crtc_state->hw.degamma_lut, 361 NULL); 362 drm_property_replace_blob(&crtc_state->hw.gamma_lut, 363 crtc_state->post_csc_lut ?: 364 crtc_state->pre_csc_lut); 365 } 366 367 drm_property_replace_blob(&crtc_state->uapi.degamma_lut, 368 crtc_state->hw.degamma_lut); 369 drm_property_replace_blob(&crtc_state->uapi.gamma_lut, 370 crtc_state->hw.gamma_lut); 371 drm_property_replace_blob(&crtc_state->uapi.ctm, 372 crtc_state->hw.ctm); 373 } 374 375 static void 376 intel_sanitize_plane_mapping(struct drm_i915_private *i915) 377 { 378 struct intel_crtc *crtc; 379 380 if (DISPLAY_VER(i915) >= 4) 381 return; 382 383 for_each_intel_crtc(&i915->drm, crtc) { 384 struct intel_plane *plane = 385 to_intel_plane(crtc->base.primary); 386 struct intel_crtc *plane_crtc; 387 enum pipe pipe; 388 389 if (!plane->get_hw_state(plane, &pipe)) 390 continue; 391 392 if (pipe == crtc->pipe) 393 continue; 394 395 drm_dbg_kms(&i915->drm, 396 "[PLANE:%d:%s] attached to the wrong pipe, disabling plane\n", 397 plane->base.base.id, plane->base.name); 398 399 plane_crtc = intel_crtc_for_pipe(i915, pipe); 400 intel_plane_disable_noatomic(plane_crtc, plane); 401 } 402 } 403 404 static bool intel_crtc_has_encoders(struct intel_crtc *crtc) 405 { 406 struct drm_device *dev = crtc->base.dev; 407 struct intel_encoder *encoder; 408 409 for_each_encoder_on_crtc(dev, &crtc->base, encoder) 410 return true; 411 412 return false; 413 } 414 415 static bool intel_crtc_needs_link_reset(struct intel_crtc *crtc) 416 { 417 struct drm_device *dev = crtc->base.dev; 418 struct intel_encoder *encoder; 419 420 for_each_encoder_on_crtc(dev, &crtc->base, encoder) { 421 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 422 423 if (dig_port && intel_tc_port_link_needs_reset(dig_port)) 424 return true; 425 } 426 427 return false; 428 } 429 430 static struct intel_connector *intel_encoder_find_connector(struct intel_encoder *encoder) 431 { 432 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 433 struct drm_connector_list_iter conn_iter; 434 struct intel_connector *connector; 435 struct intel_connector *found_connector = NULL; 436 437 drm_connector_list_iter_begin(&i915->drm, &conn_iter); 438 for_each_intel_connector_iter(connector, &conn_iter) { 439 if (&encoder->base == connector->base.encoder) { 440 found_connector = connector; 441 break; 442 } 443 } 444 drm_connector_list_iter_end(&conn_iter); 445 446 return found_connector; 447 } 448 449 static void intel_sanitize_fifo_underrun_reporting(const struct intel_crtc_state *crtc_state) 450 { 451 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 452 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 453 454 /* 455 * We start out with underrun reporting disabled on active 456 * pipes to avoid races. 457 * 458 * Also on gmch platforms we dont have any hardware bits to 459 * disable the underrun reporting. Which means we need to start 460 * out with underrun reporting disabled also on inactive pipes, 461 * since otherwise we'll complain about the garbage we read when 462 * e.g. coming up after runtime pm. 463 * 464 * No protection against concurrent access is required - at 465 * worst a fifo underrun happens which also sets this to false. 466 */ 467 intel_init_fifo_underrun_reporting(i915, crtc, 468 !crtc_state->hw.active && 469 !HAS_GMCH(i915)); 470 } 471 472 static bool intel_sanitize_crtc(struct intel_crtc *crtc, 473 struct drm_modeset_acquire_ctx *ctx) 474 { 475 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 476 struct intel_crtc_state *crtc_state = to_intel_crtc_state(crtc->base.state); 477 bool needs_link_reset; 478 479 if (crtc_state->hw.active) { 480 struct intel_plane *plane; 481 482 /* Disable everything but the primary plane */ 483 for_each_intel_plane_on_crtc(&i915->drm, crtc, plane) { 484 const struct intel_plane_state *plane_state = 485 to_intel_plane_state(plane->base.state); 486 487 if (plane_state->uapi.visible && 488 plane->base.type != DRM_PLANE_TYPE_PRIMARY) 489 intel_plane_disable_noatomic(crtc, plane); 490 } 491 492 /* Disable any background color/etc. set by the BIOS */ 493 intel_color_commit_noarm(crtc_state); 494 intel_color_commit_arm(crtc_state); 495 } 496 497 if (!crtc_state->hw.active || 498 intel_crtc_is_joiner_secondary(crtc_state)) 499 return false; 500 501 needs_link_reset = intel_crtc_needs_link_reset(crtc); 502 503 /* 504 * Adjust the state of the output pipe according to whether we have 505 * active connectors/encoders. 506 */ 507 if (!needs_link_reset && intel_crtc_has_encoders(crtc)) 508 return false; 509 510 intel_crtc_disable_noatomic(crtc, ctx); 511 512 /* 513 * The HPD state on other active/disconnected TC ports may be stuck in 514 * the connected state until this port is disabled and a ~10ms delay has 515 * passed, wait here for that so that sanitizing other CRTCs will see the 516 * up-to-date HPD state. 517 */ 518 if (needs_link_reset) 519 msleep(20); 520 521 return true; 522 } 523 524 static void intel_sanitize_all_crtcs(struct drm_i915_private *i915, 525 struct drm_modeset_acquire_ctx *ctx) 526 { 527 struct intel_crtc *crtc; 528 u32 crtcs_forced_off = 0; 529 530 /* 531 * An active and disconnected TypeC port prevents the HPD live state 532 * to get updated on other active/disconnected TypeC ports, so after 533 * a port gets disabled the CRTCs using other TypeC ports must be 534 * rechecked wrt. their link status. 535 */ 536 for (;;) { 537 u32 old_mask = crtcs_forced_off; 538 539 for_each_intel_crtc(&i915->drm, crtc) { 540 u32 crtc_mask = drm_crtc_mask(&crtc->base); 541 542 if (crtcs_forced_off & crtc_mask) 543 continue; 544 545 if (intel_sanitize_crtc(crtc, ctx)) 546 crtcs_forced_off |= crtc_mask; 547 } 548 if (crtcs_forced_off == old_mask) 549 break; 550 } 551 552 for_each_intel_crtc(&i915->drm, crtc) { 553 struct intel_crtc_state *crtc_state = 554 to_intel_crtc_state(crtc->base.state); 555 556 intel_crtc_state_dump(crtc_state, NULL, "setup_hw_state"); 557 } 558 } 559 560 static bool has_bogus_dpll_config(const struct intel_crtc_state *crtc_state) 561 { 562 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); 563 564 /* 565 * Some SNB BIOSen (eg. ASUS K53SV) are known to misprogram 566 * the hardware when a high res displays plugged in. DPLL P 567 * divider is zero, and the pipe timings are bonkers. We'll 568 * try to disable everything in that case. 569 * 570 * FIXME would be nice to be able to sanitize this state 571 * without several WARNs, but for now let's take the easy 572 * road. 573 */ 574 return IS_SANDYBRIDGE(i915) && 575 crtc_state->hw.active && 576 crtc_state->shared_dpll && 577 crtc_state->port_clock == 0; 578 } 579 580 static void intel_sanitize_encoder(struct intel_encoder *encoder) 581 { 582 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 583 struct intel_connector *connector; 584 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); 585 struct intel_crtc_state *crtc_state = crtc ? 586 to_intel_crtc_state(crtc->base.state) : NULL; 587 struct intel_pmdemand_state *pmdemand_state = 588 to_intel_pmdemand_state(i915->display.pmdemand.obj.state); 589 590 /* 591 * We need to check both for a crtc link (meaning that the encoder is 592 * active and trying to read from a pipe) and the pipe itself being 593 * active. 594 */ 595 bool has_active_crtc = crtc_state && 596 crtc_state->hw.active; 597 598 if (crtc_state && has_bogus_dpll_config(crtc_state)) { 599 drm_dbg_kms(&i915->drm, 600 "BIOS has misprogrammed the hardware. Disabling pipe %c\n", 601 pipe_name(crtc->pipe)); 602 has_active_crtc = false; 603 } 604 605 connector = intel_encoder_find_connector(encoder); 606 if (connector && !has_active_crtc) { 607 drm_dbg_kms(&i915->drm, 608 "[ENCODER:%d:%s] has active connectors but no active pipe!\n", 609 encoder->base.base.id, 610 encoder->base.name); 611 612 /* Clear the corresponding bit in pmdemand active phys mask */ 613 intel_pmdemand_update_phys_mask(i915, encoder, 614 pmdemand_state, false); 615 616 /* 617 * Connector is active, but has no active pipe. This is fallout 618 * from our resume register restoring. Disable the encoder 619 * manually again. 620 */ 621 if (crtc_state) { 622 struct drm_encoder *best_encoder; 623 624 drm_dbg_kms(&i915->drm, 625 "[ENCODER:%d:%s] manually disabled\n", 626 encoder->base.base.id, 627 encoder->base.name); 628 629 /* avoid oopsing in case the hooks consult best_encoder */ 630 best_encoder = connector->base.state->best_encoder; 631 connector->base.state->best_encoder = &encoder->base; 632 633 /* FIXME NULL atomic state passed! */ 634 if (encoder->disable) 635 encoder->disable(NULL, encoder, crtc_state, 636 connector->base.state); 637 if (encoder->post_disable) 638 encoder->post_disable(NULL, encoder, crtc_state, 639 connector->base.state); 640 641 connector->base.state->best_encoder = best_encoder; 642 } 643 encoder->base.crtc = NULL; 644 645 /* 646 * Inconsistent output/port/pipe state happens presumably due to 647 * a bug in one of the get_hw_state functions. Or someplace else 648 * in our code, like the register restore mess on resume. Clamp 649 * things to off as a safer default. 650 */ 651 connector->base.dpms = DRM_MODE_DPMS_OFF; 652 connector->base.encoder = NULL; 653 } 654 655 /* notify opregion of the sanitized encoder state */ 656 intel_opregion_notify_encoder(encoder, connector && has_active_crtc); 657 658 if (HAS_DDI(i915)) 659 intel_ddi_sanitize_encoder_pll_mapping(encoder); 660 } 661 662 /* FIXME read out full plane state for all planes */ 663 static void readout_plane_state(struct drm_i915_private *i915) 664 { 665 struct intel_plane *plane; 666 struct intel_crtc *crtc; 667 668 for_each_intel_plane(&i915->drm, plane) { 669 struct intel_plane_state *plane_state = 670 to_intel_plane_state(plane->base.state); 671 struct intel_crtc_state *crtc_state; 672 enum pipe pipe = PIPE_A; 673 bool visible; 674 675 visible = plane->get_hw_state(plane, &pipe); 676 677 crtc = intel_crtc_for_pipe(i915, pipe); 678 crtc_state = to_intel_crtc_state(crtc->base.state); 679 680 intel_set_plane_visible(crtc_state, plane_state, visible); 681 682 drm_dbg_kms(&i915->drm, 683 "[PLANE:%d:%s] hw state readout: %s, pipe %c\n", 684 plane->base.base.id, plane->base.name, 685 str_enabled_disabled(visible), pipe_name(pipe)); 686 } 687 688 for_each_intel_crtc(&i915->drm, crtc) { 689 struct intel_crtc_state *crtc_state = 690 to_intel_crtc_state(crtc->base.state); 691 692 intel_plane_fixup_bitmasks(crtc_state); 693 } 694 } 695 696 static void intel_modeset_readout_hw_state(struct drm_i915_private *i915) 697 { 698 struct intel_cdclk_state *cdclk_state = 699 to_intel_cdclk_state(i915->display.cdclk.obj.state); 700 struct intel_dbuf_state *dbuf_state = 701 to_intel_dbuf_state(i915->display.dbuf.obj.state); 702 struct intel_pmdemand_state *pmdemand_state = 703 to_intel_pmdemand_state(i915->display.pmdemand.obj.state); 704 enum pipe pipe; 705 struct intel_crtc *crtc; 706 struct intel_encoder *encoder; 707 struct intel_connector *connector; 708 struct drm_connector_list_iter conn_iter; 709 u8 active_pipes = 0; 710 711 for_each_intel_crtc(&i915->drm, crtc) { 712 struct intel_crtc_state *crtc_state = 713 to_intel_crtc_state(crtc->base.state); 714 715 __drm_atomic_helper_crtc_destroy_state(&crtc_state->uapi); 716 intel_crtc_free_hw_state(crtc_state); 717 intel_crtc_state_reset(crtc_state, crtc); 718 719 intel_crtc_get_pipe_config(crtc_state); 720 721 crtc_state->hw.enable = crtc_state->hw.active; 722 723 crtc->base.enabled = crtc_state->hw.enable; 724 crtc->active = crtc_state->hw.active; 725 726 if (crtc_state->hw.active) 727 active_pipes |= BIT(crtc->pipe); 728 729 drm_dbg_kms(&i915->drm, 730 "[CRTC:%d:%s] hw state readout: %s\n", 731 crtc->base.base.id, crtc->base.name, 732 str_enabled_disabled(crtc_state->hw.active)); 733 } 734 735 cdclk_state->active_pipes = active_pipes; 736 dbuf_state->active_pipes = active_pipes; 737 738 readout_plane_state(i915); 739 740 for_each_intel_encoder(&i915->drm, encoder) { 741 struct intel_crtc_state *crtc_state = NULL; 742 743 pipe = 0; 744 745 if (encoder->get_hw_state(encoder, &pipe)) { 746 crtc = intel_crtc_for_pipe(i915, pipe); 747 crtc_state = to_intel_crtc_state(crtc->base.state); 748 749 encoder->base.crtc = &crtc->base; 750 intel_encoder_get_config(encoder, crtc_state); 751 752 /* read out to secondary crtc as well for joiner */ 753 if (crtc_state->joiner_pipes) { 754 struct intel_crtc *secondary_crtc; 755 756 /* encoder should read be linked to joiner primary */ 757 WARN_ON(intel_crtc_is_joiner_secondary(crtc_state)); 758 759 for_each_intel_crtc_in_pipe_mask(&i915->drm, secondary_crtc, 760 intel_crtc_joiner_secondary_pipes(crtc_state)) { 761 struct intel_crtc_state *secondary_crtc_state; 762 763 secondary_crtc_state = to_intel_crtc_state(secondary_crtc->base.state); 764 intel_encoder_get_config(encoder, secondary_crtc_state); 765 } 766 } 767 768 intel_pmdemand_update_phys_mask(i915, encoder, 769 pmdemand_state, 770 true); 771 } else { 772 intel_pmdemand_update_phys_mask(i915, encoder, 773 pmdemand_state, 774 false); 775 776 encoder->base.crtc = NULL; 777 } 778 779 if (encoder->sync_state) 780 encoder->sync_state(encoder, crtc_state); 781 782 drm_dbg_kms(&i915->drm, 783 "[ENCODER:%d:%s] hw state readout: %s, pipe %c\n", 784 encoder->base.base.id, encoder->base.name, 785 str_enabled_disabled(encoder->base.crtc), 786 pipe_name(pipe)); 787 } 788 789 intel_dpll_readout_hw_state(i915); 790 791 drm_connector_list_iter_begin(&i915->drm, &conn_iter); 792 for_each_intel_connector_iter(connector, &conn_iter) { 793 struct intel_crtc_state *crtc_state = NULL; 794 795 if (connector->get_hw_state(connector)) { 796 struct intel_crtc *crtc; 797 798 connector->base.dpms = DRM_MODE_DPMS_ON; 799 800 encoder = intel_attached_encoder(connector); 801 connector->base.encoder = &encoder->base; 802 803 crtc = to_intel_crtc(encoder->base.crtc); 804 crtc_state = crtc ? to_intel_crtc_state(crtc->base.state) : NULL; 805 806 if (crtc_state && crtc_state->hw.active) { 807 /* 808 * This has to be done during hardware readout 809 * because anything calling .crtc_disable may 810 * rely on the connector_mask being accurate. 811 */ 812 crtc_state->uapi.connector_mask |= 813 drm_connector_mask(&connector->base); 814 crtc_state->uapi.encoder_mask |= 815 drm_encoder_mask(&encoder->base); 816 } 817 } else { 818 connector->base.dpms = DRM_MODE_DPMS_OFF; 819 connector->base.encoder = NULL; 820 } 821 822 if (connector->sync_state) 823 connector->sync_state(connector, crtc_state); 824 825 drm_dbg_kms(&i915->drm, 826 "[CONNECTOR:%d:%s] hw state readout: %s\n", 827 connector->base.base.id, connector->base.name, 828 str_enabled_disabled(connector->base.encoder)); 829 } 830 drm_connector_list_iter_end(&conn_iter); 831 832 for_each_intel_crtc(&i915->drm, crtc) { 833 struct intel_bw_state *bw_state = 834 to_intel_bw_state(i915->display.bw.obj.state); 835 struct intel_crtc_state *crtc_state = 836 to_intel_crtc_state(crtc->base.state); 837 struct intel_plane *plane; 838 int min_cdclk = 0; 839 840 if (crtc_state->hw.active) { 841 /* 842 * The initial mode needs to be set in order to keep 843 * the atomic core happy. It wants a valid mode if the 844 * crtc's enabled, so we do the above call. 845 * 846 * But we don't set all the derived state fully, hence 847 * set a flag to indicate that a full recalculation is 848 * needed on the next commit. 849 */ 850 crtc_state->inherited = true; 851 852 intel_crtc_update_active_timings(crtc_state, 853 crtc_state->vrr.enable); 854 855 intel_crtc_copy_hw_to_uapi_state(crtc_state); 856 } 857 858 for_each_intel_plane_on_crtc(&i915->drm, crtc, plane) { 859 const struct intel_plane_state *plane_state = 860 to_intel_plane_state(plane->base.state); 861 862 /* 863 * FIXME don't have the fb yet, so can't 864 * use intel_plane_data_rate() :( 865 */ 866 if (plane_state->uapi.visible) 867 crtc_state->data_rate[plane->id] = 868 4 * crtc_state->pixel_rate; 869 /* 870 * FIXME don't have the fb yet, so can't 871 * use plane->min_cdclk() :( 872 */ 873 if (plane_state->uapi.visible && plane->min_cdclk) { 874 if (crtc_state->double_wide || DISPLAY_VER(i915) >= 10) 875 crtc_state->min_cdclk[plane->id] = 876 DIV_ROUND_UP(crtc_state->pixel_rate, 2); 877 else 878 crtc_state->min_cdclk[plane->id] = 879 crtc_state->pixel_rate; 880 } 881 drm_dbg_kms(&i915->drm, 882 "[PLANE:%d:%s] min_cdclk %d kHz\n", 883 plane->base.base.id, plane->base.name, 884 crtc_state->min_cdclk[plane->id]); 885 } 886 887 if (crtc_state->hw.active) { 888 min_cdclk = intel_crtc_compute_min_cdclk(crtc_state); 889 if (drm_WARN_ON(&i915->drm, min_cdclk < 0)) 890 min_cdclk = 0; 891 } 892 893 cdclk_state->min_cdclk[crtc->pipe] = min_cdclk; 894 cdclk_state->min_voltage_level[crtc->pipe] = 895 crtc_state->min_voltage_level; 896 897 intel_pmdemand_update_port_clock(i915, pmdemand_state, pipe, 898 crtc_state->port_clock); 899 900 intel_bw_crtc_update(bw_state, crtc_state); 901 } 902 903 intel_pmdemand_init_pmdemand_params(i915, pmdemand_state); 904 } 905 906 static void 907 get_encoder_power_domains(struct drm_i915_private *i915) 908 { 909 struct intel_encoder *encoder; 910 911 for_each_intel_encoder(&i915->drm, encoder) { 912 struct intel_crtc_state *crtc_state; 913 914 if (!encoder->get_power_domains) 915 continue; 916 917 /* 918 * MST-primary and inactive encoders don't have a crtc state 919 * and neither of these require any power domain references. 920 */ 921 if (!encoder->base.crtc) 922 continue; 923 924 crtc_state = to_intel_crtc_state(encoder->base.crtc->state); 925 encoder->get_power_domains(encoder, crtc_state); 926 } 927 } 928 929 static void intel_early_display_was(struct drm_i915_private *i915) 930 { 931 /* 932 * Display WA #1185 WaDisableDARBFClkGating:glk,icl,ehl,tgl 933 * Also known as Wa_14010480278. 934 */ 935 if (IS_DISPLAY_VER(i915, 10, 12)) 936 intel_de_rmw(i915, GEN9_CLKGATE_DIS_0, 0, DARBF_GATING_DIS); 937 938 /* 939 * WaRsPkgCStateDisplayPMReq:hsw 940 * System hang if this isn't done before disabling all planes! 941 */ 942 if (IS_HASWELL(i915)) 943 intel_de_rmw(i915, CHICKEN_PAR1_1, 0, FORCE_ARB_IDLE_PLANES); 944 945 if (IS_KABYLAKE(i915) || IS_COFFEELAKE(i915) || IS_COMETLAKE(i915)) { 946 /* Display WA #1142:kbl,cfl,cml */ 947 intel_de_rmw(i915, CHICKEN_PAR1_1, 948 KBL_ARB_FILL_SPARE_22, KBL_ARB_FILL_SPARE_22); 949 intel_de_rmw(i915, CHICKEN_MISC_2, 950 KBL_ARB_FILL_SPARE_13 | KBL_ARB_FILL_SPARE_14, 951 KBL_ARB_FILL_SPARE_14); 952 } 953 } 954 955 void intel_modeset_setup_hw_state(struct drm_i915_private *i915, 956 struct drm_modeset_acquire_ctx *ctx) 957 { 958 struct intel_encoder *encoder; 959 struct intel_crtc *crtc; 960 intel_wakeref_t wakeref; 961 962 wakeref = intel_display_power_get(i915, POWER_DOMAIN_INIT); 963 964 intel_early_display_was(i915); 965 intel_modeset_readout_hw_state(i915); 966 967 /* HW state is read out, now we need to sanitize this mess. */ 968 get_encoder_power_domains(i915); 969 970 intel_pch_sanitize(i915); 971 972 /* 973 * intel_sanitize_plane_mapping() may need to do vblank 974 * waits, so we need vblank interrupts restored beforehand. 975 */ 976 for_each_intel_crtc(&i915->drm, crtc) { 977 struct intel_crtc_state *crtc_state = 978 to_intel_crtc_state(crtc->base.state); 979 980 intel_sanitize_fifo_underrun_reporting(crtc_state); 981 982 drm_crtc_vblank_reset(&crtc->base); 983 984 if (crtc_state->hw.active) { 985 intel_dmc_enable_pipe(i915, crtc->pipe); 986 intel_crtc_vblank_on(crtc_state); 987 } 988 } 989 990 intel_fbc_sanitize(&i915->display); 991 992 intel_sanitize_plane_mapping(i915); 993 994 for_each_intel_encoder(&i915->drm, encoder) 995 intel_sanitize_encoder(encoder); 996 997 /* 998 * Sanitizing CRTCs needs their connector atomic state to be 999 * up-to-date, so ensure that already here. 1000 */ 1001 intel_modeset_update_connector_atomic_state(i915); 1002 1003 intel_sanitize_all_crtcs(i915, ctx); 1004 1005 intel_dpll_sanitize_state(i915); 1006 1007 intel_wm_get_hw_state(i915); 1008 1009 for_each_intel_crtc(&i915->drm, crtc) { 1010 struct intel_crtc_state *crtc_state = 1011 to_intel_crtc_state(crtc->base.state); 1012 struct intel_power_domain_mask put_domains; 1013 1014 intel_modeset_get_crtc_power_domains(crtc_state, &put_domains); 1015 if (drm_WARN_ON(&i915->drm, !bitmap_empty(put_domains.bits, POWER_DOMAIN_NUM))) 1016 intel_modeset_put_crtc_power_domains(crtc, &put_domains); 1017 } 1018 1019 intel_display_power_put(i915, POWER_DOMAIN_INIT, wakeref); 1020 1021 intel_power_domains_sanitize_state(i915); 1022 } 1023