1 /* 2 * Copyright © 2006-2007 Intel Corporation 3 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie> 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 22 * DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: 25 * Eric Anholt <eric@anholt.net> 26 * Dave Airlie <airlied@linux.ie> 27 * Jesse Barnes <jesse.barnes@intel.com> 28 */ 29 30 #include <acpi/button.h> 31 #include <linux/acpi.h> 32 #include <linux/dmi.h> 33 #include <linux/i2c.h> 34 #include <linux/slab.h> 35 #include <linux/vga_switcheroo.h> 36 37 #include <drm/drm_atomic_helper.h> 38 #include <drm/drm_crtc.h> 39 #include <drm/drm_edid.h> 40 #include <drm/drm_probe_helper.h> 41 42 #include "i915_drv.h" 43 #include "i915_reg.h" 44 #include "intel_atomic.h" 45 #include "intel_backlight.h" 46 #include "intel_connector.h" 47 #include "intel_de.h" 48 #include "intel_display_types.h" 49 #include "intel_dpll.h" 50 #include "intel_fdi.h" 51 #include "intel_gmbus.h" 52 #include "intel_lvds.h" 53 #include "intel_lvds_regs.h" 54 #include "intel_panel.h" 55 #include "intel_pps_regs.h" 56 57 /* Private structure for the integrated LVDS support */ 58 struct intel_lvds_pps { 59 /* 100us units */ 60 int t1_t2; 61 int t3; 62 int t4; 63 int t5; 64 int tx; 65 66 int divider; 67 68 int port; 69 bool powerdown_on_reset; 70 }; 71 72 struct intel_lvds_encoder { 73 struct intel_encoder base; 74 75 bool is_dual_link; 76 i915_reg_t reg; 77 u32 a3_power; 78 79 struct intel_lvds_pps init_pps; 80 u32 init_lvds_val; 81 82 struct intel_connector *attached_connector; 83 }; 84 85 static struct intel_lvds_encoder *to_lvds_encoder(struct intel_encoder *encoder) 86 { 87 return container_of(encoder, struct intel_lvds_encoder, base); 88 } 89 90 bool intel_lvds_port_enabled(struct drm_i915_private *i915, 91 i915_reg_t lvds_reg, enum pipe *pipe) 92 { 93 u32 val; 94 95 val = intel_de_read(i915, lvds_reg); 96 97 /* asserts want to know the pipe even if the port is disabled */ 98 if (HAS_PCH_CPT(i915)) 99 *pipe = REG_FIELD_GET(LVDS_PIPE_SEL_MASK_CPT, val); 100 else 101 *pipe = REG_FIELD_GET(LVDS_PIPE_SEL_MASK, val); 102 103 return val & LVDS_PORT_EN; 104 } 105 106 static bool intel_lvds_get_hw_state(struct intel_encoder *encoder, 107 enum pipe *pipe) 108 { 109 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 110 struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(encoder); 111 intel_wakeref_t wakeref; 112 bool ret; 113 114 wakeref = intel_display_power_get_if_enabled(i915, encoder->power_domain); 115 if (!wakeref) 116 return false; 117 118 ret = intel_lvds_port_enabled(i915, lvds_encoder->reg, pipe); 119 120 intel_display_power_put(i915, encoder->power_domain, wakeref); 121 122 return ret; 123 } 124 125 static void intel_lvds_get_config(struct intel_encoder *encoder, 126 struct intel_crtc_state *crtc_state) 127 { 128 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 129 struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(encoder); 130 u32 tmp, flags = 0; 131 132 crtc_state->output_types |= BIT(INTEL_OUTPUT_LVDS); 133 134 tmp = intel_de_read(dev_priv, lvds_encoder->reg); 135 if (tmp & LVDS_HSYNC_POLARITY) 136 flags |= DRM_MODE_FLAG_NHSYNC; 137 else 138 flags |= DRM_MODE_FLAG_PHSYNC; 139 if (tmp & LVDS_VSYNC_POLARITY) 140 flags |= DRM_MODE_FLAG_NVSYNC; 141 else 142 flags |= DRM_MODE_FLAG_PVSYNC; 143 144 crtc_state->hw.adjusted_mode.flags |= flags; 145 146 if (DISPLAY_VER(dev_priv) < 5) 147 crtc_state->gmch_pfit.lvds_border_bits = 148 tmp & LVDS_BORDER_ENABLE; 149 150 /* gen2/3 store dither state in pfit control, needs to match */ 151 if (DISPLAY_VER(dev_priv) < 4) { 152 tmp = intel_de_read(dev_priv, PFIT_CONTROL(dev_priv)); 153 154 crtc_state->gmch_pfit.control |= tmp & PFIT_PANEL_8TO6_DITHER_ENABLE; 155 } 156 157 crtc_state->hw.adjusted_mode.crtc_clock = crtc_state->port_clock; 158 } 159 160 static void intel_lvds_pps_get_hw_state(struct drm_i915_private *dev_priv, 161 struct intel_lvds_pps *pps) 162 { 163 u32 val; 164 165 pps->powerdown_on_reset = intel_de_read(dev_priv, 166 PP_CONTROL(dev_priv, 0)) & PANEL_POWER_RESET; 167 168 val = intel_de_read(dev_priv, PP_ON_DELAYS(dev_priv, 0)); 169 pps->port = REG_FIELD_GET(PANEL_PORT_SELECT_MASK, val); 170 pps->t1_t2 = REG_FIELD_GET(PANEL_POWER_UP_DELAY_MASK, val); 171 pps->t5 = REG_FIELD_GET(PANEL_LIGHT_ON_DELAY_MASK, val); 172 173 val = intel_de_read(dev_priv, PP_OFF_DELAYS(dev_priv, 0)); 174 pps->t3 = REG_FIELD_GET(PANEL_POWER_DOWN_DELAY_MASK, val); 175 pps->tx = REG_FIELD_GET(PANEL_LIGHT_OFF_DELAY_MASK, val); 176 177 val = intel_de_read(dev_priv, PP_DIVISOR(dev_priv, 0)); 178 pps->divider = REG_FIELD_GET(PP_REFERENCE_DIVIDER_MASK, val); 179 val = REG_FIELD_GET(PANEL_POWER_CYCLE_DELAY_MASK, val); 180 /* 181 * Remove the BSpec specified +1 (100ms) offset that accounts for a 182 * too short power-cycle delay due to the asynchronous programming of 183 * the register. 184 */ 185 if (val) 186 val--; 187 /* Convert from 100ms to 100us units */ 188 pps->t4 = val * 1000; 189 190 if (DISPLAY_VER(dev_priv) < 5 && 191 pps->t1_t2 == 0 && pps->t5 == 0 && pps->t3 == 0 && pps->tx == 0) { 192 drm_dbg_kms(&dev_priv->drm, 193 "Panel power timings uninitialized, " 194 "setting defaults\n"); 195 /* Set T2 to 40ms and T5 to 200ms in 100 usec units */ 196 pps->t1_t2 = 40 * 10; 197 pps->t5 = 200 * 10; 198 /* Set T3 to 35ms and Tx to 200ms in 100 usec units */ 199 pps->t3 = 35 * 10; 200 pps->tx = 200 * 10; 201 } 202 203 drm_dbg(&dev_priv->drm, "LVDS PPS:t1+t2 %d t3 %d t4 %d t5 %d tx %d " 204 "divider %d port %d powerdown_on_reset %d\n", 205 pps->t1_t2, pps->t3, pps->t4, pps->t5, pps->tx, 206 pps->divider, pps->port, pps->powerdown_on_reset); 207 } 208 209 static void intel_lvds_pps_init_hw(struct drm_i915_private *dev_priv, 210 struct intel_lvds_pps *pps) 211 { 212 u32 val; 213 214 val = intel_de_read(dev_priv, PP_CONTROL(dev_priv, 0)); 215 drm_WARN_ON(&dev_priv->drm, 216 (val & PANEL_UNLOCK_MASK) != PANEL_UNLOCK_REGS); 217 if (pps->powerdown_on_reset) 218 val |= PANEL_POWER_RESET; 219 intel_de_write(dev_priv, PP_CONTROL(dev_priv, 0), val); 220 221 intel_de_write(dev_priv, PP_ON_DELAYS(dev_priv, 0), 222 REG_FIELD_PREP(PANEL_PORT_SELECT_MASK, pps->port) | 223 REG_FIELD_PREP(PANEL_POWER_UP_DELAY_MASK, pps->t1_t2) | 224 REG_FIELD_PREP(PANEL_LIGHT_ON_DELAY_MASK, pps->t5)); 225 226 intel_de_write(dev_priv, PP_OFF_DELAYS(dev_priv, 0), 227 REG_FIELD_PREP(PANEL_POWER_DOWN_DELAY_MASK, pps->t3) | 228 REG_FIELD_PREP(PANEL_LIGHT_OFF_DELAY_MASK, pps->tx)); 229 230 intel_de_write(dev_priv, PP_DIVISOR(dev_priv, 0), 231 REG_FIELD_PREP(PP_REFERENCE_DIVIDER_MASK, pps->divider) | 232 REG_FIELD_PREP(PANEL_POWER_CYCLE_DELAY_MASK, DIV_ROUND_UP(pps->t4, 1000) + 1)); 233 } 234 235 static void intel_pre_enable_lvds(struct intel_atomic_state *state, 236 struct intel_encoder *encoder, 237 const struct intel_crtc_state *crtc_state, 238 const struct drm_connector_state *conn_state) 239 { 240 struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(encoder); 241 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 242 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 243 const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; 244 enum pipe pipe = crtc->pipe; 245 u32 temp; 246 247 if (HAS_PCH_SPLIT(i915)) { 248 assert_fdi_rx_pll_disabled(i915, pipe); 249 assert_shared_dpll_disabled(i915, crtc_state->shared_dpll); 250 } else { 251 assert_pll_disabled(i915, pipe); 252 } 253 254 intel_lvds_pps_init_hw(i915, &lvds_encoder->init_pps); 255 256 temp = lvds_encoder->init_lvds_val; 257 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP; 258 259 if (HAS_PCH_CPT(i915)) { 260 temp &= ~LVDS_PIPE_SEL_MASK_CPT; 261 temp |= LVDS_PIPE_SEL_CPT(pipe); 262 } else { 263 temp &= ~LVDS_PIPE_SEL_MASK; 264 temp |= LVDS_PIPE_SEL(pipe); 265 } 266 267 /* set the corresponding LVDS_BORDER bit */ 268 temp &= ~LVDS_BORDER_ENABLE; 269 temp |= crtc_state->gmch_pfit.lvds_border_bits; 270 271 /* 272 * Set the B0-B3 data pairs corresponding to whether we're going to 273 * set the DPLLs for dual-channel mode or not. 274 */ 275 if (lvds_encoder->is_dual_link) 276 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP; 277 else 278 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP); 279 280 /* 281 * It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP) 282 * appropriately here, but we need to look more thoroughly into how 283 * panels behave in the two modes. For now, let's just maintain the 284 * value we got from the BIOS. 285 */ 286 temp &= ~LVDS_A3_POWER_MASK; 287 temp |= lvds_encoder->a3_power; 288 289 /* 290 * Set the dithering flag on LVDS as needed, note that there is no 291 * special lvds dither control bit on pch-split platforms, dithering is 292 * only controlled through the TRANSCONF reg. 293 */ 294 if (DISPLAY_VER(i915) == 4) { 295 /* 296 * Bspec wording suggests that LVDS port dithering only exists 297 * for 18bpp panels. 298 */ 299 if (crtc_state->dither && crtc_state->pipe_bpp == 18) 300 temp |= LVDS_ENABLE_DITHER; 301 else 302 temp &= ~LVDS_ENABLE_DITHER; 303 } 304 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY); 305 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC) 306 temp |= LVDS_HSYNC_POLARITY; 307 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC) 308 temp |= LVDS_VSYNC_POLARITY; 309 310 intel_de_write(i915, lvds_encoder->reg, temp); 311 } 312 313 /* 314 * Sets the power state for the panel. 315 */ 316 static void intel_enable_lvds(struct intel_atomic_state *state, 317 struct intel_encoder *encoder, 318 const struct intel_crtc_state *crtc_state, 319 const struct drm_connector_state *conn_state) 320 { 321 struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(encoder); 322 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 323 324 intel_de_rmw(dev_priv, lvds_encoder->reg, 0, LVDS_PORT_EN); 325 326 intel_de_rmw(dev_priv, PP_CONTROL(dev_priv, 0), 0, PANEL_POWER_ON); 327 intel_de_posting_read(dev_priv, lvds_encoder->reg); 328 329 if (intel_de_wait_for_set(dev_priv, PP_STATUS(dev_priv, 0), PP_ON, 5000)) 330 drm_err(&dev_priv->drm, 331 "timed out waiting for panel to power on\n"); 332 333 intel_backlight_enable(crtc_state, conn_state); 334 } 335 336 static void intel_disable_lvds(struct intel_atomic_state *state, 337 struct intel_encoder *encoder, 338 const struct intel_crtc_state *old_crtc_state, 339 const struct drm_connector_state *old_conn_state) 340 { 341 struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(encoder); 342 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 343 344 intel_de_rmw(dev_priv, PP_CONTROL(dev_priv, 0), PANEL_POWER_ON, 0); 345 if (intel_de_wait_for_clear(dev_priv, PP_STATUS(dev_priv, 0), PP_ON, 1000)) 346 drm_err(&dev_priv->drm, 347 "timed out waiting for panel to power off\n"); 348 349 intel_de_rmw(dev_priv, lvds_encoder->reg, LVDS_PORT_EN, 0); 350 intel_de_posting_read(dev_priv, lvds_encoder->reg); 351 } 352 353 static void gmch_disable_lvds(struct intel_atomic_state *state, 354 struct intel_encoder *encoder, 355 const struct intel_crtc_state *old_crtc_state, 356 const struct drm_connector_state *old_conn_state) 357 358 { 359 intel_backlight_disable(old_conn_state); 360 361 intel_disable_lvds(state, encoder, old_crtc_state, old_conn_state); 362 } 363 364 static void pch_disable_lvds(struct intel_atomic_state *state, 365 struct intel_encoder *encoder, 366 const struct intel_crtc_state *old_crtc_state, 367 const struct drm_connector_state *old_conn_state) 368 { 369 intel_backlight_disable(old_conn_state); 370 } 371 372 static void pch_post_disable_lvds(struct intel_atomic_state *state, 373 struct intel_encoder *encoder, 374 const struct intel_crtc_state *old_crtc_state, 375 const struct drm_connector_state *old_conn_state) 376 { 377 intel_disable_lvds(state, encoder, old_crtc_state, old_conn_state); 378 } 379 380 static void intel_lvds_shutdown(struct intel_encoder *encoder) 381 { 382 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 383 384 if (intel_de_wait_for_clear(dev_priv, PP_STATUS(dev_priv, 0), PP_CYCLE_DELAY_ACTIVE, 5000)) 385 drm_err(&dev_priv->drm, 386 "timed out waiting for panel power cycle delay\n"); 387 } 388 389 static enum drm_mode_status 390 intel_lvds_mode_valid(struct drm_connector *_connector, 391 struct drm_display_mode *mode) 392 { 393 struct intel_connector *connector = to_intel_connector(_connector); 394 struct drm_i915_private *i915 = to_i915(connector->base.dev); 395 const struct drm_display_mode *fixed_mode = 396 intel_panel_fixed_mode(connector, mode); 397 int max_pixclk = to_i915(connector->base.dev)->display.cdclk.max_dotclk_freq; 398 enum drm_mode_status status; 399 400 status = intel_cpu_transcoder_mode_valid(i915, mode); 401 if (status != MODE_OK) 402 return status; 403 404 status = intel_panel_mode_valid(connector, mode); 405 if (status != MODE_OK) 406 return status; 407 408 if (fixed_mode->clock > max_pixclk) 409 return MODE_CLOCK_HIGH; 410 411 return MODE_OK; 412 } 413 414 static int intel_lvds_compute_config(struct intel_encoder *encoder, 415 struct intel_crtc_state *crtc_state, 416 struct drm_connector_state *conn_state) 417 { 418 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 419 struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(encoder); 420 struct intel_connector *connector = lvds_encoder->attached_connector; 421 struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; 422 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 423 unsigned int lvds_bpp; 424 int ret; 425 426 /* Should never happen!! */ 427 if (DISPLAY_VER(i915) < 4 && crtc->pipe == 0) { 428 drm_err(&i915->drm, "Can't support LVDS on pipe A\n"); 429 return -EINVAL; 430 } 431 432 if (HAS_PCH_SPLIT(i915)) { 433 crtc_state->has_pch_encoder = true; 434 if (!intel_fdi_compute_pipe_bpp(crtc_state)) 435 return -EINVAL; 436 } 437 438 if (lvds_encoder->a3_power == LVDS_A3_POWER_UP) 439 lvds_bpp = 8*3; 440 else 441 lvds_bpp = 6*3; 442 443 /* TODO: Check crtc_state->max_link_bpp_x16 instead of bw_constrained */ 444 if (lvds_bpp != crtc_state->pipe_bpp && !crtc_state->bw_constrained) { 445 drm_dbg_kms(&i915->drm, 446 "forcing display bpp (was %d) to LVDS (%d)\n", 447 crtc_state->pipe_bpp, lvds_bpp); 448 crtc_state->pipe_bpp = lvds_bpp; 449 } 450 451 crtc_state->sink_format = INTEL_OUTPUT_FORMAT_RGB; 452 crtc_state->output_format = INTEL_OUTPUT_FORMAT_RGB; 453 454 /* 455 * We have timings from the BIOS for the panel, put them in 456 * to the adjusted mode. The CRTC will be set up for this mode, 457 * with the panel scaling set up to source from the H/VDisplay 458 * of the original mode. 459 */ 460 ret = intel_panel_compute_config(connector, adjusted_mode); 461 if (ret) 462 return ret; 463 464 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN) 465 return -EINVAL; 466 467 ret = intel_panel_fitting(crtc_state, conn_state); 468 if (ret) 469 return ret; 470 471 /* 472 * XXX: It would be nice to support lower refresh rates on the 473 * panels to reduce power consumption, and perhaps match the 474 * user's requested refresh rate. 475 */ 476 477 return 0; 478 } 479 480 /* 481 * Return the list of DDC modes if available, or the BIOS fixed mode otherwise. 482 */ 483 static int intel_lvds_get_modes(struct drm_connector *_connector) 484 { 485 struct intel_connector *connector = to_intel_connector(_connector); 486 const struct drm_edid *fixed_edid = connector->panel.fixed_edid; 487 488 /* Use panel fixed edid if we have one */ 489 if (!IS_ERR_OR_NULL(fixed_edid)) { 490 drm_edid_connector_update(&connector->base, fixed_edid); 491 492 return drm_edid_connector_add_modes(&connector->base); 493 } 494 495 return intel_panel_get_modes(connector); 496 } 497 498 static const struct drm_connector_helper_funcs intel_lvds_connector_helper_funcs = { 499 .get_modes = intel_lvds_get_modes, 500 .mode_valid = intel_lvds_mode_valid, 501 .atomic_check = intel_digital_connector_atomic_check, 502 }; 503 504 static const struct drm_connector_funcs intel_lvds_connector_funcs = { 505 .detect = intel_panel_detect, 506 .fill_modes = drm_helper_probe_single_connector_modes, 507 .atomic_get_property = intel_digital_connector_atomic_get_property, 508 .atomic_set_property = intel_digital_connector_atomic_set_property, 509 .late_register = intel_connector_register, 510 .early_unregister = intel_connector_unregister, 511 .destroy = intel_connector_destroy, 512 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 513 .atomic_duplicate_state = intel_digital_connector_duplicate_state, 514 }; 515 516 static const struct drm_encoder_funcs intel_lvds_enc_funcs = { 517 .destroy = intel_encoder_destroy, 518 }; 519 520 static int intel_no_lvds_dmi_callback(const struct dmi_system_id *id) 521 { 522 DRM_INFO("Skipping LVDS initialization for %s\n", id->ident); 523 return 1; 524 } 525 526 /* These systems claim to have LVDS, but really don't */ 527 static const struct dmi_system_id intel_no_lvds[] = { 528 { 529 .callback = intel_no_lvds_dmi_callback, 530 .ident = "Apple Mac Mini (Core series)", 531 .matches = { 532 DMI_MATCH(DMI_SYS_VENDOR, "Apple"), 533 DMI_MATCH(DMI_PRODUCT_NAME, "Macmini1,1"), 534 }, 535 }, 536 { 537 .callback = intel_no_lvds_dmi_callback, 538 .ident = "Apple Mac Mini (Core 2 series)", 539 .matches = { 540 DMI_MATCH(DMI_SYS_VENDOR, "Apple"), 541 DMI_MATCH(DMI_PRODUCT_NAME, "Macmini2,1"), 542 }, 543 }, 544 { 545 .callback = intel_no_lvds_dmi_callback, 546 .ident = "MSI IM-945GSE-A", 547 .matches = { 548 DMI_MATCH(DMI_SYS_VENDOR, "MSI"), 549 DMI_MATCH(DMI_PRODUCT_NAME, "A9830IMS"), 550 }, 551 }, 552 { 553 .callback = intel_no_lvds_dmi_callback, 554 .ident = "Dell Studio Hybrid", 555 .matches = { 556 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), 557 DMI_MATCH(DMI_PRODUCT_NAME, "Studio Hybrid 140g"), 558 }, 559 }, 560 { 561 .callback = intel_no_lvds_dmi_callback, 562 .ident = "Dell OptiPlex FX170", 563 .matches = { 564 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), 565 DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex FX170"), 566 }, 567 }, 568 { 569 .callback = intel_no_lvds_dmi_callback, 570 .ident = "AOpen Mini PC", 571 .matches = { 572 DMI_MATCH(DMI_SYS_VENDOR, "AOpen"), 573 DMI_MATCH(DMI_PRODUCT_NAME, "i965GMx-IF"), 574 }, 575 }, 576 { 577 .callback = intel_no_lvds_dmi_callback, 578 .ident = "AOpen Mini PC MP915", 579 .matches = { 580 DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"), 581 DMI_MATCH(DMI_BOARD_NAME, "i915GMx-F"), 582 }, 583 }, 584 { 585 .callback = intel_no_lvds_dmi_callback, 586 .ident = "AOpen i915GMm-HFS", 587 .matches = { 588 DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"), 589 DMI_MATCH(DMI_BOARD_NAME, "i915GMm-HFS"), 590 }, 591 }, 592 { 593 .callback = intel_no_lvds_dmi_callback, 594 .ident = "AOpen i45GMx-I", 595 .matches = { 596 DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"), 597 DMI_MATCH(DMI_BOARD_NAME, "i45GMx-I"), 598 }, 599 }, 600 { 601 .callback = intel_no_lvds_dmi_callback, 602 .ident = "Aopen i945GTt-VFA", 603 .matches = { 604 DMI_MATCH(DMI_PRODUCT_VERSION, "AO00001JW"), 605 }, 606 }, 607 { 608 .callback = intel_no_lvds_dmi_callback, 609 .ident = "Clientron U800", 610 .matches = { 611 DMI_MATCH(DMI_SYS_VENDOR, "Clientron"), 612 DMI_MATCH(DMI_PRODUCT_NAME, "U800"), 613 }, 614 }, 615 { 616 .callback = intel_no_lvds_dmi_callback, 617 .ident = "Clientron E830", 618 .matches = { 619 DMI_MATCH(DMI_SYS_VENDOR, "Clientron"), 620 DMI_MATCH(DMI_PRODUCT_NAME, "E830"), 621 }, 622 }, 623 { 624 .callback = intel_no_lvds_dmi_callback, 625 .ident = "Asus EeeBox PC EB1007", 626 .matches = { 627 DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK Computer INC."), 628 DMI_MATCH(DMI_PRODUCT_NAME, "EB1007"), 629 }, 630 }, 631 { 632 .callback = intel_no_lvds_dmi_callback, 633 .ident = "Asus AT5NM10T-I", 634 .matches = { 635 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), 636 DMI_MATCH(DMI_BOARD_NAME, "AT5NM10T-I"), 637 }, 638 }, 639 { 640 .callback = intel_no_lvds_dmi_callback, 641 .ident = "Hewlett-Packard HP t5740", 642 .matches = { 643 DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"), 644 DMI_MATCH(DMI_PRODUCT_NAME, " t5740"), 645 }, 646 }, 647 { 648 .callback = intel_no_lvds_dmi_callback, 649 .ident = "Hewlett-Packard t5745", 650 .matches = { 651 DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"), 652 DMI_MATCH(DMI_PRODUCT_NAME, "hp t5745"), 653 }, 654 }, 655 { 656 .callback = intel_no_lvds_dmi_callback, 657 .ident = "Hewlett-Packard st5747", 658 .matches = { 659 DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"), 660 DMI_MATCH(DMI_PRODUCT_NAME, "hp st5747"), 661 }, 662 }, 663 { 664 .callback = intel_no_lvds_dmi_callback, 665 .ident = "MSI Wind Box DC500", 666 .matches = { 667 DMI_MATCH(DMI_BOARD_VENDOR, "MICRO-STAR INTERNATIONAL CO., LTD"), 668 DMI_MATCH(DMI_BOARD_NAME, "MS-7469"), 669 }, 670 }, 671 { 672 .callback = intel_no_lvds_dmi_callback, 673 .ident = "Gigabyte GA-D525TUD", 674 .matches = { 675 DMI_MATCH(DMI_BOARD_VENDOR, "Gigabyte Technology Co., Ltd."), 676 DMI_MATCH(DMI_BOARD_NAME, "D525TUD"), 677 }, 678 }, 679 { 680 .callback = intel_no_lvds_dmi_callback, 681 .ident = "Supermicro X7SPA-H", 682 .matches = { 683 DMI_MATCH(DMI_SYS_VENDOR, "Supermicro"), 684 DMI_MATCH(DMI_PRODUCT_NAME, "X7SPA-H"), 685 }, 686 }, 687 { 688 .callback = intel_no_lvds_dmi_callback, 689 .ident = "Fujitsu Esprimo Q900", 690 .matches = { 691 DMI_MATCH(DMI_SYS_VENDOR, "FUJITSU"), 692 DMI_MATCH(DMI_PRODUCT_NAME, "ESPRIMO Q900"), 693 }, 694 }, 695 { 696 .callback = intel_no_lvds_dmi_callback, 697 .ident = "Intel D410PT", 698 .matches = { 699 DMI_MATCH(DMI_BOARD_VENDOR, "Intel"), 700 DMI_MATCH(DMI_BOARD_NAME, "D410PT"), 701 }, 702 }, 703 { 704 .callback = intel_no_lvds_dmi_callback, 705 .ident = "Intel D425KT", 706 .matches = { 707 DMI_MATCH(DMI_BOARD_VENDOR, "Intel"), 708 DMI_EXACT_MATCH(DMI_BOARD_NAME, "D425KT"), 709 }, 710 }, 711 { 712 .callback = intel_no_lvds_dmi_callback, 713 .ident = "Intel D510MO", 714 .matches = { 715 DMI_MATCH(DMI_BOARD_VENDOR, "Intel"), 716 DMI_EXACT_MATCH(DMI_BOARD_NAME, "D510MO"), 717 }, 718 }, 719 { 720 .callback = intel_no_lvds_dmi_callback, 721 .ident = "Intel D525MW", 722 .matches = { 723 DMI_MATCH(DMI_BOARD_VENDOR, "Intel"), 724 DMI_EXACT_MATCH(DMI_BOARD_NAME, "D525MW"), 725 }, 726 }, 727 { 728 .callback = intel_no_lvds_dmi_callback, 729 .ident = "Radiant P845", 730 .matches = { 731 DMI_MATCH(DMI_SYS_VENDOR, "Radiant Systems Inc"), 732 DMI_MATCH(DMI_PRODUCT_NAME, "P845"), 733 }, 734 }, 735 736 { } /* terminating entry */ 737 }; 738 739 static int intel_dual_link_lvds_callback(const struct dmi_system_id *id) 740 { 741 DRM_INFO("Forcing lvds to dual link mode on %s\n", id->ident); 742 return 1; 743 } 744 745 static const struct dmi_system_id intel_dual_link_lvds[] = { 746 { 747 .callback = intel_dual_link_lvds_callback, 748 .ident = "Apple MacBook Pro 15\" (2010)", 749 .matches = { 750 DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."), 751 DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro6,2"), 752 }, 753 }, 754 { 755 .callback = intel_dual_link_lvds_callback, 756 .ident = "Apple MacBook Pro 15\" (2011)", 757 .matches = { 758 DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."), 759 DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro8,2"), 760 }, 761 }, 762 { 763 .callback = intel_dual_link_lvds_callback, 764 .ident = "Apple MacBook Pro 15\" (2012)", 765 .matches = { 766 DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."), 767 DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro9,1"), 768 }, 769 }, 770 { } /* terminating entry */ 771 }; 772 773 struct intel_encoder *intel_get_lvds_encoder(struct drm_i915_private *i915) 774 { 775 struct intel_encoder *encoder; 776 777 for_each_intel_encoder(&i915->drm, encoder) { 778 if (encoder->type == INTEL_OUTPUT_LVDS) 779 return encoder; 780 } 781 782 return NULL; 783 } 784 785 bool intel_is_dual_link_lvds(struct drm_i915_private *i915) 786 { 787 struct intel_encoder *encoder = intel_get_lvds_encoder(i915); 788 789 return encoder && to_lvds_encoder(encoder)->is_dual_link; 790 } 791 792 static bool compute_is_dual_link_lvds(struct intel_lvds_encoder *lvds_encoder) 793 { 794 struct drm_i915_private *i915 = to_i915(lvds_encoder->base.base.dev); 795 struct intel_connector *connector = lvds_encoder->attached_connector; 796 const struct drm_display_mode *fixed_mode = 797 intel_panel_preferred_fixed_mode(connector); 798 unsigned int val; 799 800 /* use the module option value if specified */ 801 if (i915->display.params.lvds_channel_mode > 0) 802 return i915->display.params.lvds_channel_mode == 2; 803 804 /* single channel LVDS is limited to 112 MHz */ 805 if (fixed_mode->clock > 112999) 806 return true; 807 808 if (dmi_check_system(intel_dual_link_lvds)) 809 return true; 810 811 /* 812 * BIOS should set the proper LVDS register value at boot, but 813 * in reality, it doesn't set the value when the lid is closed; 814 * we need to check "the value to be set" in VBT when LVDS 815 * register is uninitialized. 816 */ 817 val = intel_de_read(i915, lvds_encoder->reg); 818 if (HAS_PCH_CPT(i915)) 819 val &= ~(LVDS_DETECTED | LVDS_PIPE_SEL_MASK_CPT); 820 else 821 val &= ~(LVDS_DETECTED | LVDS_PIPE_SEL_MASK); 822 if (val == 0) 823 val = connector->panel.vbt.bios_lvds_val; 824 825 return (val & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP; 826 } 827 828 static void intel_lvds_add_properties(struct drm_connector *connector) 829 { 830 intel_attach_scaling_mode_property(connector); 831 } 832 833 /** 834 * intel_lvds_init - setup LVDS connectors on this device 835 * @i915: i915 device 836 * 837 * Create the connector, register the LVDS DDC bus, and try to figure out what 838 * modes we can display on the LVDS panel (if present). 839 */ 840 void intel_lvds_init(struct drm_i915_private *i915) 841 { 842 struct intel_display *display = &i915->display; 843 struct intel_lvds_encoder *lvds_encoder; 844 struct intel_connector *connector; 845 const struct drm_edid *drm_edid; 846 struct intel_encoder *encoder; 847 i915_reg_t lvds_reg; 848 u32 lvds; 849 u8 ddc_pin; 850 851 /* Skip init on machines we know falsely report LVDS */ 852 if (dmi_check_system(intel_no_lvds)) { 853 drm_WARN(&i915->drm, !i915->display.vbt.int_lvds_support, 854 "Useless DMI match. Internal LVDS support disabled by VBT\n"); 855 return; 856 } 857 858 if (!i915->display.vbt.int_lvds_support) { 859 drm_dbg_kms(&i915->drm, 860 "Internal LVDS support disabled by VBT\n"); 861 return; 862 } 863 864 if (HAS_PCH_SPLIT(i915)) 865 lvds_reg = PCH_LVDS; 866 else 867 lvds_reg = LVDS; 868 869 lvds = intel_de_read(i915, lvds_reg); 870 871 if (HAS_PCH_SPLIT(i915)) { 872 if ((lvds & LVDS_DETECTED) == 0) 873 return; 874 } 875 876 ddc_pin = GMBUS_PIN_PANEL; 877 if (!intel_bios_is_lvds_present(display, &ddc_pin)) { 878 if ((lvds & LVDS_PORT_EN) == 0) { 879 drm_dbg_kms(&i915->drm, 880 "LVDS is not present in VBT\n"); 881 return; 882 } 883 drm_dbg_kms(&i915->drm, 884 "LVDS is not present in VBT, but enabled anyway\n"); 885 } 886 887 lvds_encoder = kzalloc(sizeof(*lvds_encoder), GFP_KERNEL); 888 if (!lvds_encoder) 889 return; 890 891 connector = intel_connector_alloc(); 892 if (!connector) { 893 kfree(lvds_encoder); 894 return; 895 } 896 897 lvds_encoder->attached_connector = connector; 898 encoder = &lvds_encoder->base; 899 900 drm_connector_init_with_ddc(&i915->drm, &connector->base, 901 &intel_lvds_connector_funcs, 902 DRM_MODE_CONNECTOR_LVDS, 903 intel_gmbus_get_adapter(i915, ddc_pin)); 904 905 drm_encoder_init(&i915->drm, &encoder->base, &intel_lvds_enc_funcs, 906 DRM_MODE_ENCODER_LVDS, "LVDS"); 907 908 encoder->enable = intel_enable_lvds; 909 encoder->pre_enable = intel_pre_enable_lvds; 910 encoder->compute_config = intel_lvds_compute_config; 911 if (HAS_PCH_SPLIT(i915)) { 912 encoder->disable = pch_disable_lvds; 913 encoder->post_disable = pch_post_disable_lvds; 914 } else { 915 encoder->disable = gmch_disable_lvds; 916 } 917 encoder->get_hw_state = intel_lvds_get_hw_state; 918 encoder->get_config = intel_lvds_get_config; 919 encoder->update_pipe = intel_backlight_update; 920 encoder->shutdown = intel_lvds_shutdown; 921 connector->get_hw_state = intel_connector_get_hw_state; 922 923 intel_connector_attach_encoder(connector, encoder); 924 925 encoder->type = INTEL_OUTPUT_LVDS; 926 encoder->power_domain = POWER_DOMAIN_PORT_OTHER; 927 encoder->port = PORT_NONE; 928 encoder->cloneable = 0; 929 if (DISPLAY_VER(i915) < 4) 930 encoder->pipe_mask = BIT(PIPE_B); 931 else 932 encoder->pipe_mask = ~0; 933 934 drm_connector_helper_add(&connector->base, &intel_lvds_connector_helper_funcs); 935 connector->base.display_info.subpixel_order = SubPixelHorizontalRGB; 936 937 lvds_encoder->reg = lvds_reg; 938 939 intel_lvds_add_properties(&connector->base); 940 941 intel_lvds_pps_get_hw_state(i915, &lvds_encoder->init_pps); 942 lvds_encoder->init_lvds_val = lvds; 943 944 /* 945 * LVDS discovery: 946 * 1) check for EDID on DDC 947 * 2) check for VBT data 948 * 3) check to see if LVDS is already on 949 * if none of the above, no panel 950 */ 951 952 /* 953 * Attempt to get the fixed panel mode from DDC. Assume that the 954 * preferred mode is the right one. 955 */ 956 mutex_lock(&i915->drm.mode_config.mutex); 957 if (vga_switcheroo_handler_flags() & VGA_SWITCHEROO_CAN_SWITCH_DDC) 958 drm_edid = drm_edid_read_switcheroo(&connector->base, connector->base.ddc); 959 else 960 drm_edid = drm_edid_read_ddc(&connector->base, connector->base.ddc); 961 if (drm_edid) { 962 if (drm_edid_connector_update(&connector->base, drm_edid) || 963 !drm_edid_connector_add_modes(&connector->base)) { 964 drm_edid_connector_update(&connector->base, NULL); 965 drm_edid_free(drm_edid); 966 drm_edid = ERR_PTR(-EINVAL); 967 } 968 } else { 969 drm_edid = ERR_PTR(-ENOENT); 970 } 971 intel_bios_init_panel_late(display, &connector->panel, NULL, 972 IS_ERR(drm_edid) ? NULL : drm_edid); 973 974 /* Try EDID first */ 975 intel_panel_add_edid_fixed_modes(connector, true); 976 977 /* Failed to get EDID, what about VBT? */ 978 if (!intel_panel_preferred_fixed_mode(connector)) 979 intel_panel_add_vbt_lfp_fixed_mode(connector); 980 981 /* 982 * If we didn't get a fixed mode from EDID or VBT, try checking 983 * if the panel is already turned on. If so, assume that 984 * whatever is currently programmed is the correct mode. 985 */ 986 if (!intel_panel_preferred_fixed_mode(connector)) 987 intel_panel_add_encoder_fixed_mode(connector, encoder); 988 989 mutex_unlock(&i915->drm.mode_config.mutex); 990 991 /* If we still don't have a mode after all that, give up. */ 992 if (!intel_panel_preferred_fixed_mode(connector)) 993 goto failed; 994 995 intel_panel_init(connector, drm_edid); 996 997 intel_backlight_setup(connector, INVALID_PIPE); 998 999 lvds_encoder->is_dual_link = compute_is_dual_link_lvds(lvds_encoder); 1000 drm_dbg_kms(&i915->drm, "detected %s-link lvds configuration\n", 1001 lvds_encoder->is_dual_link ? "dual" : "single"); 1002 1003 lvds_encoder->a3_power = lvds & LVDS_A3_POWER_MASK; 1004 1005 return; 1006 1007 failed: 1008 drm_dbg_kms(&i915->drm, "No LVDS modes found, disabling.\n"); 1009 drm_connector_cleanup(&connector->base); 1010 drm_encoder_cleanup(&encoder->base); 1011 kfree(lvds_encoder); 1012 intel_connector_free(connector); 1013 return; 1014 } 1015