1 /* 2 * Copyright © 2006-2007 Intel Corporation 3 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie> 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 22 * DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: 25 * Eric Anholt <eric@anholt.net> 26 * Dave Airlie <airlied@linux.ie> 27 * Jesse Barnes <jesse.barnes@intel.com> 28 */ 29 30 #include <acpi/button.h> 31 #include <linux/acpi.h> 32 #include <linux/dmi.h> 33 #include <linux/i2c.h> 34 #include <linux/slab.h> 35 #include <linux/vga_switcheroo.h> 36 37 #include <drm/drm_atomic_helper.h> 38 #include <drm/drm_crtc.h> 39 #include <drm/drm_edid.h> 40 #include <drm/drm_probe_helper.h> 41 42 #include "i915_drv.h" 43 #include "i915_reg.h" 44 #include "intel_atomic.h" 45 #include "intel_backlight.h" 46 #include "intel_connector.h" 47 #include "intel_de.h" 48 #include "intel_display_types.h" 49 #include "intel_dpll.h" 50 #include "intel_fdi.h" 51 #include "intel_gmbus.h" 52 #include "intel_lvds.h" 53 #include "intel_lvds_regs.h" 54 #include "intel_panel.h" 55 #include "intel_pfit.h" 56 #include "intel_pfit_regs.h" 57 #include "intel_pps_regs.h" 58 59 /* Private structure for the integrated LVDS support */ 60 struct intel_lvds_pps { 61 struct intel_pps_delays delays; 62 63 int divider; 64 65 int port; 66 bool powerdown_on_reset; 67 }; 68 69 struct intel_lvds_encoder { 70 struct intel_encoder base; 71 72 bool is_dual_link; 73 i915_reg_t reg; 74 u32 a3_power; 75 76 struct intel_lvds_pps init_pps; 77 u32 init_lvds_val; 78 79 struct intel_connector *attached_connector; 80 }; 81 82 static struct intel_lvds_encoder *to_lvds_encoder(struct intel_encoder *encoder) 83 { 84 return container_of(encoder, struct intel_lvds_encoder, base); 85 } 86 87 bool intel_lvds_port_enabled(struct drm_i915_private *i915, 88 i915_reg_t lvds_reg, enum pipe *pipe) 89 { 90 u32 val; 91 92 val = intel_de_read(i915, lvds_reg); 93 94 /* asserts want to know the pipe even if the port is disabled */ 95 if (HAS_PCH_CPT(i915)) 96 *pipe = REG_FIELD_GET(LVDS_PIPE_SEL_MASK_CPT, val); 97 else 98 *pipe = REG_FIELD_GET(LVDS_PIPE_SEL_MASK, val); 99 100 return val & LVDS_PORT_EN; 101 } 102 103 static bool intel_lvds_get_hw_state(struct intel_encoder *encoder, 104 enum pipe *pipe) 105 { 106 struct intel_display *display = to_intel_display(encoder); 107 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 108 struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(encoder); 109 intel_wakeref_t wakeref; 110 bool ret; 111 112 wakeref = intel_display_power_get_if_enabled(display, encoder->power_domain); 113 if (!wakeref) 114 return false; 115 116 ret = intel_lvds_port_enabled(i915, lvds_encoder->reg, pipe); 117 118 intel_display_power_put(display, encoder->power_domain, wakeref); 119 120 return ret; 121 } 122 123 static void intel_lvds_get_config(struct intel_encoder *encoder, 124 struct intel_crtc_state *crtc_state) 125 { 126 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 127 struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(encoder); 128 u32 tmp, flags = 0; 129 130 crtc_state->output_types |= BIT(INTEL_OUTPUT_LVDS); 131 132 tmp = intel_de_read(dev_priv, lvds_encoder->reg); 133 if (tmp & LVDS_HSYNC_POLARITY) 134 flags |= DRM_MODE_FLAG_NHSYNC; 135 else 136 flags |= DRM_MODE_FLAG_PHSYNC; 137 if (tmp & LVDS_VSYNC_POLARITY) 138 flags |= DRM_MODE_FLAG_NVSYNC; 139 else 140 flags |= DRM_MODE_FLAG_PVSYNC; 141 142 crtc_state->hw.adjusted_mode.flags |= flags; 143 144 if (DISPLAY_VER(dev_priv) < 5) 145 crtc_state->gmch_pfit.lvds_border_bits = 146 tmp & LVDS_BORDER_ENABLE; 147 148 /* gen2/3 store dither state in pfit control, needs to match */ 149 if (DISPLAY_VER(dev_priv) < 4) { 150 tmp = intel_de_read(dev_priv, PFIT_CONTROL(dev_priv)); 151 152 crtc_state->gmch_pfit.control |= tmp & PFIT_PANEL_8TO6_DITHER_ENABLE; 153 } 154 155 crtc_state->hw.adjusted_mode.crtc_clock = crtc_state->port_clock; 156 } 157 158 static void intel_lvds_pps_get_hw_state(struct drm_i915_private *dev_priv, 159 struct intel_lvds_pps *pps) 160 { 161 u32 val; 162 163 pps->powerdown_on_reset = intel_de_read(dev_priv, 164 PP_CONTROL(dev_priv, 0)) & PANEL_POWER_RESET; 165 166 val = intel_de_read(dev_priv, PP_ON_DELAYS(dev_priv, 0)); 167 pps->port = REG_FIELD_GET(PANEL_PORT_SELECT_MASK, val); 168 pps->delays.power_up = REG_FIELD_GET(PANEL_POWER_UP_DELAY_MASK, val); 169 pps->delays.backlight_on = REG_FIELD_GET(PANEL_LIGHT_ON_DELAY_MASK, val); 170 171 val = intel_de_read(dev_priv, PP_OFF_DELAYS(dev_priv, 0)); 172 pps->delays.power_down = REG_FIELD_GET(PANEL_POWER_DOWN_DELAY_MASK, val); 173 pps->delays.backlight_off = REG_FIELD_GET(PANEL_LIGHT_OFF_DELAY_MASK, val); 174 175 val = intel_de_read(dev_priv, PP_DIVISOR(dev_priv, 0)); 176 pps->divider = REG_FIELD_GET(PP_REFERENCE_DIVIDER_MASK, val); 177 val = REG_FIELD_GET(PANEL_POWER_CYCLE_DELAY_MASK, val); 178 /* 179 * Remove the BSpec specified +1 (100ms) offset that accounts for a 180 * too short power-cycle delay due to the asynchronous programming of 181 * the register. 182 */ 183 if (val) 184 val--; 185 /* Convert from 100ms to 100us units */ 186 pps->delays.power_cycle = val * 1000; 187 188 if (DISPLAY_VER(dev_priv) < 5 && 189 pps->delays.power_up == 0 && 190 pps->delays.backlight_on == 0 && 191 pps->delays.power_down == 0 && 192 pps->delays.backlight_off == 0) { 193 drm_dbg_kms(&dev_priv->drm, 194 "Panel power timings uninitialized, " 195 "setting defaults\n"); 196 /* Set T2 to 40ms and T5 to 200ms in 100 usec units */ 197 pps->delays.power_up = 40 * 10; 198 pps->delays.backlight_on = 200 * 10; 199 /* Set T3 to 35ms and Tx to 200ms in 100 usec units */ 200 pps->delays.power_down = 35 * 10; 201 pps->delays.backlight_off = 200 * 10; 202 } 203 204 drm_dbg(&dev_priv->drm, "LVDS PPS:power_up %d power_down %d power_cycle %d backlight_on %d backlight_off %d " 205 "divider %d port %d powerdown_on_reset %d\n", 206 pps->delays.power_up, pps->delays.power_down, 207 pps->delays.power_cycle, pps->delays.backlight_on, 208 pps->delays.backlight_off, pps->divider, 209 pps->port, pps->powerdown_on_reset); 210 } 211 212 static void intel_lvds_pps_init_hw(struct drm_i915_private *dev_priv, 213 struct intel_lvds_pps *pps) 214 { 215 u32 val; 216 217 val = intel_de_read(dev_priv, PP_CONTROL(dev_priv, 0)); 218 drm_WARN_ON(&dev_priv->drm, 219 (val & PANEL_UNLOCK_MASK) != PANEL_UNLOCK_REGS); 220 if (pps->powerdown_on_reset) 221 val |= PANEL_POWER_RESET; 222 intel_de_write(dev_priv, PP_CONTROL(dev_priv, 0), val); 223 224 intel_de_write(dev_priv, PP_ON_DELAYS(dev_priv, 0), 225 REG_FIELD_PREP(PANEL_PORT_SELECT_MASK, pps->port) | 226 REG_FIELD_PREP(PANEL_POWER_UP_DELAY_MASK, pps->delays.power_up) | 227 REG_FIELD_PREP(PANEL_LIGHT_ON_DELAY_MASK, pps->delays.backlight_on)); 228 229 intel_de_write(dev_priv, PP_OFF_DELAYS(dev_priv, 0), 230 REG_FIELD_PREP(PANEL_POWER_DOWN_DELAY_MASK, pps->delays.power_down) | 231 REG_FIELD_PREP(PANEL_LIGHT_OFF_DELAY_MASK, pps->delays.backlight_off)); 232 233 intel_de_write(dev_priv, PP_DIVISOR(dev_priv, 0), 234 REG_FIELD_PREP(PP_REFERENCE_DIVIDER_MASK, pps->divider) | 235 REG_FIELD_PREP(PANEL_POWER_CYCLE_DELAY_MASK, 236 DIV_ROUND_UP(pps->delays.power_cycle, 1000) + 1)); 237 } 238 239 static void intel_pre_enable_lvds(struct intel_atomic_state *state, 240 struct intel_encoder *encoder, 241 const struct intel_crtc_state *crtc_state, 242 const struct drm_connector_state *conn_state) 243 { 244 struct intel_display *display = to_intel_display(state); 245 struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(encoder); 246 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 247 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 248 const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; 249 enum pipe pipe = crtc->pipe; 250 u32 temp; 251 252 if (HAS_PCH_SPLIT(i915)) { 253 assert_fdi_rx_pll_disabled(display, pipe); 254 assert_shared_dpll_disabled(display, crtc_state->shared_dpll); 255 } else { 256 assert_pll_disabled(display, pipe); 257 } 258 259 intel_lvds_pps_init_hw(i915, &lvds_encoder->init_pps); 260 261 temp = lvds_encoder->init_lvds_val; 262 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP; 263 264 if (HAS_PCH_CPT(i915)) { 265 temp &= ~LVDS_PIPE_SEL_MASK_CPT; 266 temp |= LVDS_PIPE_SEL_CPT(pipe); 267 } else { 268 temp &= ~LVDS_PIPE_SEL_MASK; 269 temp |= LVDS_PIPE_SEL(pipe); 270 } 271 272 /* set the corresponding LVDS_BORDER bit */ 273 temp &= ~LVDS_BORDER_ENABLE; 274 temp |= crtc_state->gmch_pfit.lvds_border_bits; 275 276 /* 277 * Set the B0-B3 data pairs corresponding to whether we're going to 278 * set the DPLLs for dual-channel mode or not. 279 */ 280 if (lvds_encoder->is_dual_link) 281 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP; 282 else 283 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP); 284 285 /* 286 * It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP) 287 * appropriately here, but we need to look more thoroughly into how 288 * panels behave in the two modes. For now, let's just maintain the 289 * value we got from the BIOS. 290 */ 291 temp &= ~LVDS_A3_POWER_MASK; 292 temp |= lvds_encoder->a3_power; 293 294 /* 295 * Set the dithering flag on LVDS as needed, note that there is no 296 * special lvds dither control bit on pch-split platforms, dithering is 297 * only controlled through the TRANSCONF reg. 298 */ 299 if (DISPLAY_VER(i915) == 4) { 300 /* 301 * Bspec wording suggests that LVDS port dithering only exists 302 * for 18bpp panels. 303 */ 304 if (crtc_state->dither && crtc_state->pipe_bpp == 18) 305 temp |= LVDS_ENABLE_DITHER; 306 else 307 temp &= ~LVDS_ENABLE_DITHER; 308 } 309 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY); 310 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC) 311 temp |= LVDS_HSYNC_POLARITY; 312 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC) 313 temp |= LVDS_VSYNC_POLARITY; 314 315 intel_de_write(i915, lvds_encoder->reg, temp); 316 } 317 318 /* 319 * Sets the power state for the panel. 320 */ 321 static void intel_enable_lvds(struct intel_atomic_state *state, 322 struct intel_encoder *encoder, 323 const struct intel_crtc_state *crtc_state, 324 const struct drm_connector_state *conn_state) 325 { 326 struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(encoder); 327 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 328 329 intel_de_rmw(dev_priv, lvds_encoder->reg, 0, LVDS_PORT_EN); 330 331 intel_de_rmw(dev_priv, PP_CONTROL(dev_priv, 0), 0, PANEL_POWER_ON); 332 intel_de_posting_read(dev_priv, lvds_encoder->reg); 333 334 if (intel_de_wait_for_set(dev_priv, PP_STATUS(dev_priv, 0), PP_ON, 5000)) 335 drm_err(&dev_priv->drm, 336 "timed out waiting for panel to power on\n"); 337 338 intel_backlight_enable(crtc_state, conn_state); 339 } 340 341 static void intel_disable_lvds(struct intel_atomic_state *state, 342 struct intel_encoder *encoder, 343 const struct intel_crtc_state *old_crtc_state, 344 const struct drm_connector_state *old_conn_state) 345 { 346 struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(encoder); 347 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 348 349 intel_de_rmw(dev_priv, PP_CONTROL(dev_priv, 0), PANEL_POWER_ON, 0); 350 if (intel_de_wait_for_clear(dev_priv, PP_STATUS(dev_priv, 0), PP_ON, 1000)) 351 drm_err(&dev_priv->drm, 352 "timed out waiting for panel to power off\n"); 353 354 intel_de_rmw(dev_priv, lvds_encoder->reg, LVDS_PORT_EN, 0); 355 intel_de_posting_read(dev_priv, lvds_encoder->reg); 356 } 357 358 static void gmch_disable_lvds(struct intel_atomic_state *state, 359 struct intel_encoder *encoder, 360 const struct intel_crtc_state *old_crtc_state, 361 const struct drm_connector_state *old_conn_state) 362 363 { 364 intel_backlight_disable(old_conn_state); 365 366 intel_disable_lvds(state, encoder, old_crtc_state, old_conn_state); 367 } 368 369 static void pch_disable_lvds(struct intel_atomic_state *state, 370 struct intel_encoder *encoder, 371 const struct intel_crtc_state *old_crtc_state, 372 const struct drm_connector_state *old_conn_state) 373 { 374 intel_backlight_disable(old_conn_state); 375 } 376 377 static void pch_post_disable_lvds(struct intel_atomic_state *state, 378 struct intel_encoder *encoder, 379 const struct intel_crtc_state *old_crtc_state, 380 const struct drm_connector_state *old_conn_state) 381 { 382 intel_disable_lvds(state, encoder, old_crtc_state, old_conn_state); 383 } 384 385 static void intel_lvds_shutdown(struct intel_encoder *encoder) 386 { 387 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 388 389 if (intel_de_wait_for_clear(dev_priv, PP_STATUS(dev_priv, 0), PP_CYCLE_DELAY_ACTIVE, 5000)) 390 drm_err(&dev_priv->drm, 391 "timed out waiting for panel power cycle delay\n"); 392 } 393 394 static enum drm_mode_status 395 intel_lvds_mode_valid(struct drm_connector *_connector, 396 const struct drm_display_mode *mode) 397 { 398 struct intel_display *display = to_intel_display(_connector->dev); 399 struct intel_connector *connector = to_intel_connector(_connector); 400 const struct drm_display_mode *fixed_mode = 401 intel_panel_fixed_mode(connector, mode); 402 int max_pixclk = display->cdclk.max_dotclk_freq; 403 enum drm_mode_status status; 404 405 status = intel_cpu_transcoder_mode_valid(display, mode); 406 if (status != MODE_OK) 407 return status; 408 409 status = intel_panel_mode_valid(connector, mode); 410 if (status != MODE_OK) 411 return status; 412 413 if (fixed_mode->clock > max_pixclk) 414 return MODE_CLOCK_HIGH; 415 416 return MODE_OK; 417 } 418 419 static int intel_lvds_compute_config(struct intel_encoder *encoder, 420 struct intel_crtc_state *crtc_state, 421 struct drm_connector_state *conn_state) 422 { 423 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 424 struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(encoder); 425 struct intel_connector *connector = lvds_encoder->attached_connector; 426 struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; 427 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 428 unsigned int lvds_bpp; 429 int ret; 430 431 /* Should never happen!! */ 432 if (DISPLAY_VER(i915) < 4 && crtc->pipe == 0) { 433 drm_err(&i915->drm, "Can't support LVDS on pipe A\n"); 434 return -EINVAL; 435 } 436 437 if (HAS_PCH_SPLIT(i915)) { 438 crtc_state->has_pch_encoder = true; 439 if (!intel_fdi_compute_pipe_bpp(crtc_state)) 440 return -EINVAL; 441 } 442 443 if (lvds_encoder->a3_power == LVDS_A3_POWER_UP) 444 lvds_bpp = 8*3; 445 else 446 lvds_bpp = 6*3; 447 448 /* TODO: Check crtc_state->max_link_bpp_x16 instead of bw_constrained */ 449 if (lvds_bpp != crtc_state->pipe_bpp && !crtc_state->bw_constrained) { 450 drm_dbg_kms(&i915->drm, 451 "forcing display bpp (was %d) to LVDS (%d)\n", 452 crtc_state->pipe_bpp, lvds_bpp); 453 crtc_state->pipe_bpp = lvds_bpp; 454 } 455 456 crtc_state->sink_format = INTEL_OUTPUT_FORMAT_RGB; 457 crtc_state->output_format = INTEL_OUTPUT_FORMAT_RGB; 458 459 /* 460 * We have timings from the BIOS for the panel, put them in 461 * to the adjusted mode. The CRTC will be set up for this mode, 462 * with the panel scaling set up to source from the H/VDisplay 463 * of the original mode. 464 */ 465 ret = intel_panel_compute_config(connector, adjusted_mode); 466 if (ret) 467 return ret; 468 469 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN) 470 return -EINVAL; 471 472 ret = intel_pfit_compute_config(crtc_state, conn_state); 473 if (ret) 474 return ret; 475 476 /* 477 * XXX: It would be nice to support lower refresh rates on the 478 * panels to reduce power consumption, and perhaps match the 479 * user's requested refresh rate. 480 */ 481 482 return 0; 483 } 484 485 /* 486 * Return the list of DDC modes if available, or the BIOS fixed mode otherwise. 487 */ 488 static int intel_lvds_get_modes(struct drm_connector *_connector) 489 { 490 struct intel_connector *connector = to_intel_connector(_connector); 491 const struct drm_edid *fixed_edid = connector->panel.fixed_edid; 492 493 /* Use panel fixed edid if we have one */ 494 if (!IS_ERR_OR_NULL(fixed_edid)) { 495 drm_edid_connector_update(&connector->base, fixed_edid); 496 497 return drm_edid_connector_add_modes(&connector->base); 498 } 499 500 return intel_panel_get_modes(connector); 501 } 502 503 static const struct drm_connector_helper_funcs intel_lvds_connector_helper_funcs = { 504 .get_modes = intel_lvds_get_modes, 505 .mode_valid = intel_lvds_mode_valid, 506 .atomic_check = intel_digital_connector_atomic_check, 507 }; 508 509 static const struct drm_connector_funcs intel_lvds_connector_funcs = { 510 .detect = intel_panel_detect, 511 .fill_modes = drm_helper_probe_single_connector_modes, 512 .atomic_get_property = intel_digital_connector_atomic_get_property, 513 .atomic_set_property = intel_digital_connector_atomic_set_property, 514 .late_register = intel_connector_register, 515 .early_unregister = intel_connector_unregister, 516 .destroy = intel_connector_destroy, 517 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 518 .atomic_duplicate_state = intel_digital_connector_duplicate_state, 519 }; 520 521 static const struct drm_encoder_funcs intel_lvds_enc_funcs = { 522 .destroy = intel_encoder_destroy, 523 }; 524 525 static int intel_no_lvds_dmi_callback(const struct dmi_system_id *id) 526 { 527 DRM_INFO("Skipping LVDS initialization for %s\n", id->ident); 528 return 1; 529 } 530 531 /* These systems claim to have LVDS, but really don't */ 532 static const struct dmi_system_id intel_no_lvds[] = { 533 { 534 .callback = intel_no_lvds_dmi_callback, 535 .ident = "Apple Mac Mini (Core series)", 536 .matches = { 537 DMI_MATCH(DMI_SYS_VENDOR, "Apple"), 538 DMI_MATCH(DMI_PRODUCT_NAME, "Macmini1,1"), 539 }, 540 }, 541 { 542 .callback = intel_no_lvds_dmi_callback, 543 .ident = "Apple Mac Mini (Core 2 series)", 544 .matches = { 545 DMI_MATCH(DMI_SYS_VENDOR, "Apple"), 546 DMI_MATCH(DMI_PRODUCT_NAME, "Macmini2,1"), 547 }, 548 }, 549 { 550 .callback = intel_no_lvds_dmi_callback, 551 .ident = "MSI IM-945GSE-A", 552 .matches = { 553 DMI_MATCH(DMI_SYS_VENDOR, "MSI"), 554 DMI_MATCH(DMI_PRODUCT_NAME, "A9830IMS"), 555 }, 556 }, 557 { 558 .callback = intel_no_lvds_dmi_callback, 559 .ident = "Dell Studio Hybrid", 560 .matches = { 561 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), 562 DMI_MATCH(DMI_PRODUCT_NAME, "Studio Hybrid 140g"), 563 }, 564 }, 565 { 566 .callback = intel_no_lvds_dmi_callback, 567 .ident = "Dell OptiPlex FX170", 568 .matches = { 569 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), 570 DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex FX170"), 571 }, 572 }, 573 { 574 .callback = intel_no_lvds_dmi_callback, 575 .ident = "AOpen Mini PC", 576 .matches = { 577 DMI_MATCH(DMI_SYS_VENDOR, "AOpen"), 578 DMI_MATCH(DMI_PRODUCT_NAME, "i965GMx-IF"), 579 }, 580 }, 581 { 582 .callback = intel_no_lvds_dmi_callback, 583 .ident = "AOpen Mini PC MP915", 584 .matches = { 585 DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"), 586 DMI_MATCH(DMI_BOARD_NAME, "i915GMx-F"), 587 }, 588 }, 589 { 590 .callback = intel_no_lvds_dmi_callback, 591 .ident = "AOpen i915GMm-HFS", 592 .matches = { 593 DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"), 594 DMI_MATCH(DMI_BOARD_NAME, "i915GMm-HFS"), 595 }, 596 }, 597 { 598 .callback = intel_no_lvds_dmi_callback, 599 .ident = "AOpen i45GMx-I", 600 .matches = { 601 DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"), 602 DMI_MATCH(DMI_BOARD_NAME, "i45GMx-I"), 603 }, 604 }, 605 { 606 .callback = intel_no_lvds_dmi_callback, 607 .ident = "Aopen i945GTt-VFA", 608 .matches = { 609 DMI_MATCH(DMI_PRODUCT_VERSION, "AO00001JW"), 610 }, 611 }, 612 { 613 .callback = intel_no_lvds_dmi_callback, 614 .ident = "Clientron U800", 615 .matches = { 616 DMI_MATCH(DMI_SYS_VENDOR, "Clientron"), 617 DMI_MATCH(DMI_PRODUCT_NAME, "U800"), 618 }, 619 }, 620 { 621 .callback = intel_no_lvds_dmi_callback, 622 .ident = "Clientron E830", 623 .matches = { 624 DMI_MATCH(DMI_SYS_VENDOR, "Clientron"), 625 DMI_MATCH(DMI_PRODUCT_NAME, "E830"), 626 }, 627 }, 628 { 629 .callback = intel_no_lvds_dmi_callback, 630 .ident = "Asus EeeBox PC EB1007", 631 .matches = { 632 DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK Computer INC."), 633 DMI_MATCH(DMI_PRODUCT_NAME, "EB1007"), 634 }, 635 }, 636 { 637 .callback = intel_no_lvds_dmi_callback, 638 .ident = "Asus AT5NM10T-I", 639 .matches = { 640 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), 641 DMI_MATCH(DMI_BOARD_NAME, "AT5NM10T-I"), 642 }, 643 }, 644 { 645 .callback = intel_no_lvds_dmi_callback, 646 .ident = "Hewlett-Packard HP t5740", 647 .matches = { 648 DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"), 649 DMI_MATCH(DMI_PRODUCT_NAME, " t5740"), 650 }, 651 }, 652 { 653 .callback = intel_no_lvds_dmi_callback, 654 .ident = "Hewlett-Packard t5745", 655 .matches = { 656 DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"), 657 DMI_MATCH(DMI_PRODUCT_NAME, "hp t5745"), 658 }, 659 }, 660 { 661 .callback = intel_no_lvds_dmi_callback, 662 .ident = "Hewlett-Packard st5747", 663 .matches = { 664 DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"), 665 DMI_MATCH(DMI_PRODUCT_NAME, "hp st5747"), 666 }, 667 }, 668 { 669 .callback = intel_no_lvds_dmi_callback, 670 .ident = "MSI Wind Box DC500", 671 .matches = { 672 DMI_MATCH(DMI_BOARD_VENDOR, "MICRO-STAR INTERNATIONAL CO., LTD"), 673 DMI_MATCH(DMI_BOARD_NAME, "MS-7469"), 674 }, 675 }, 676 { 677 .callback = intel_no_lvds_dmi_callback, 678 .ident = "Gigabyte GA-D525TUD", 679 .matches = { 680 DMI_MATCH(DMI_BOARD_VENDOR, "Gigabyte Technology Co., Ltd."), 681 DMI_MATCH(DMI_BOARD_NAME, "D525TUD"), 682 }, 683 }, 684 { 685 .callback = intel_no_lvds_dmi_callback, 686 .ident = "Supermicro X7SPA-H", 687 .matches = { 688 DMI_MATCH(DMI_SYS_VENDOR, "Supermicro"), 689 DMI_MATCH(DMI_PRODUCT_NAME, "X7SPA-H"), 690 }, 691 }, 692 { 693 .callback = intel_no_lvds_dmi_callback, 694 .ident = "Fujitsu Esprimo Q900", 695 .matches = { 696 DMI_MATCH(DMI_SYS_VENDOR, "FUJITSU"), 697 DMI_MATCH(DMI_PRODUCT_NAME, "ESPRIMO Q900"), 698 }, 699 }, 700 { 701 .callback = intel_no_lvds_dmi_callback, 702 .ident = "Intel D410PT", 703 .matches = { 704 DMI_MATCH(DMI_BOARD_VENDOR, "Intel"), 705 DMI_MATCH(DMI_BOARD_NAME, "D410PT"), 706 }, 707 }, 708 { 709 .callback = intel_no_lvds_dmi_callback, 710 .ident = "Intel D425KT", 711 .matches = { 712 DMI_MATCH(DMI_BOARD_VENDOR, "Intel"), 713 DMI_EXACT_MATCH(DMI_BOARD_NAME, "D425KT"), 714 }, 715 }, 716 { 717 .callback = intel_no_lvds_dmi_callback, 718 .ident = "Intel D510MO", 719 .matches = { 720 DMI_MATCH(DMI_BOARD_VENDOR, "Intel"), 721 DMI_EXACT_MATCH(DMI_BOARD_NAME, "D510MO"), 722 }, 723 }, 724 { 725 .callback = intel_no_lvds_dmi_callback, 726 .ident = "Intel D525MW", 727 .matches = { 728 DMI_MATCH(DMI_BOARD_VENDOR, "Intel"), 729 DMI_EXACT_MATCH(DMI_BOARD_NAME, "D525MW"), 730 }, 731 }, 732 { 733 .callback = intel_no_lvds_dmi_callback, 734 .ident = "Radiant P845", 735 .matches = { 736 DMI_MATCH(DMI_SYS_VENDOR, "Radiant Systems Inc"), 737 DMI_MATCH(DMI_PRODUCT_NAME, "P845"), 738 }, 739 }, 740 741 { } /* terminating entry */ 742 }; 743 744 static int intel_dual_link_lvds_callback(const struct dmi_system_id *id) 745 { 746 DRM_INFO("Forcing lvds to dual link mode on %s\n", id->ident); 747 return 1; 748 } 749 750 static const struct dmi_system_id intel_dual_link_lvds[] = { 751 { 752 .callback = intel_dual_link_lvds_callback, 753 .ident = "Apple MacBook Pro 15\" (2010)", 754 .matches = { 755 DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."), 756 DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro6,2"), 757 }, 758 }, 759 { 760 .callback = intel_dual_link_lvds_callback, 761 .ident = "Apple MacBook Pro 15\" (2011)", 762 .matches = { 763 DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."), 764 DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro8,2"), 765 }, 766 }, 767 { 768 .callback = intel_dual_link_lvds_callback, 769 .ident = "Apple MacBook Pro 15\" (2012)", 770 .matches = { 771 DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."), 772 DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro9,1"), 773 }, 774 }, 775 { } /* terminating entry */ 776 }; 777 778 struct intel_encoder *intel_get_lvds_encoder(struct drm_i915_private *i915) 779 { 780 struct intel_encoder *encoder; 781 782 for_each_intel_encoder(&i915->drm, encoder) { 783 if (encoder->type == INTEL_OUTPUT_LVDS) 784 return encoder; 785 } 786 787 return NULL; 788 } 789 790 bool intel_is_dual_link_lvds(struct drm_i915_private *i915) 791 { 792 struct intel_encoder *encoder = intel_get_lvds_encoder(i915); 793 794 return encoder && to_lvds_encoder(encoder)->is_dual_link; 795 } 796 797 static bool compute_is_dual_link_lvds(struct intel_lvds_encoder *lvds_encoder) 798 { 799 struct drm_i915_private *i915 = to_i915(lvds_encoder->base.base.dev); 800 struct intel_connector *connector = lvds_encoder->attached_connector; 801 const struct drm_display_mode *fixed_mode = 802 intel_panel_preferred_fixed_mode(connector); 803 unsigned int val; 804 805 /* use the module option value if specified */ 806 if (i915->display.params.lvds_channel_mode > 0) 807 return i915->display.params.lvds_channel_mode == 2; 808 809 /* single channel LVDS is limited to 112 MHz */ 810 if (fixed_mode->clock > 112999) 811 return true; 812 813 if (dmi_check_system(intel_dual_link_lvds)) 814 return true; 815 816 /* 817 * BIOS should set the proper LVDS register value at boot, but 818 * in reality, it doesn't set the value when the lid is closed; 819 * we need to check "the value to be set" in VBT when LVDS 820 * register is uninitialized. 821 */ 822 val = intel_de_read(i915, lvds_encoder->reg); 823 if (HAS_PCH_CPT(i915)) 824 val &= ~(LVDS_DETECTED | LVDS_PIPE_SEL_MASK_CPT); 825 else 826 val &= ~(LVDS_DETECTED | LVDS_PIPE_SEL_MASK); 827 if (val == 0) 828 val = connector->panel.vbt.bios_lvds_val; 829 830 return (val & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP; 831 } 832 833 static void intel_lvds_add_properties(struct drm_connector *connector) 834 { 835 intel_attach_scaling_mode_property(connector); 836 } 837 838 /** 839 * intel_lvds_init - setup LVDS connectors on this device 840 * @i915: i915 device 841 * 842 * Create the connector, register the LVDS DDC bus, and try to figure out what 843 * modes we can display on the LVDS panel (if present). 844 */ 845 void intel_lvds_init(struct drm_i915_private *i915) 846 { 847 struct intel_display *display = &i915->display; 848 struct intel_lvds_encoder *lvds_encoder; 849 struct intel_connector *connector; 850 const struct drm_edid *drm_edid; 851 struct intel_encoder *encoder; 852 i915_reg_t lvds_reg; 853 u32 lvds; 854 u8 ddc_pin; 855 856 /* Skip init on machines we know falsely report LVDS */ 857 if (dmi_check_system(intel_no_lvds)) { 858 drm_WARN(&i915->drm, !i915->display.vbt.int_lvds_support, 859 "Useless DMI match. Internal LVDS support disabled by VBT\n"); 860 return; 861 } 862 863 if (!i915->display.vbt.int_lvds_support) { 864 drm_dbg_kms(&i915->drm, 865 "Internal LVDS support disabled by VBT\n"); 866 return; 867 } 868 869 if (HAS_PCH_SPLIT(i915)) 870 lvds_reg = PCH_LVDS; 871 else 872 lvds_reg = LVDS; 873 874 lvds = intel_de_read(i915, lvds_reg); 875 876 if (HAS_PCH_SPLIT(i915)) { 877 if ((lvds & LVDS_DETECTED) == 0) 878 return; 879 } 880 881 ddc_pin = GMBUS_PIN_PANEL; 882 if (!intel_bios_is_lvds_present(display, &ddc_pin)) { 883 if ((lvds & LVDS_PORT_EN) == 0) { 884 drm_dbg_kms(&i915->drm, 885 "LVDS is not present in VBT\n"); 886 return; 887 } 888 drm_dbg_kms(&i915->drm, 889 "LVDS is not present in VBT, but enabled anyway\n"); 890 } 891 892 lvds_encoder = kzalloc(sizeof(*lvds_encoder), GFP_KERNEL); 893 if (!lvds_encoder) 894 return; 895 896 connector = intel_connector_alloc(); 897 if (!connector) { 898 kfree(lvds_encoder); 899 return; 900 } 901 902 lvds_encoder->attached_connector = connector; 903 encoder = &lvds_encoder->base; 904 905 drm_connector_init_with_ddc(&i915->drm, &connector->base, 906 &intel_lvds_connector_funcs, 907 DRM_MODE_CONNECTOR_LVDS, 908 intel_gmbus_get_adapter(display, ddc_pin)); 909 910 drm_encoder_init(&i915->drm, &encoder->base, &intel_lvds_enc_funcs, 911 DRM_MODE_ENCODER_LVDS, "LVDS"); 912 913 encoder->enable = intel_enable_lvds; 914 encoder->pre_enable = intel_pre_enable_lvds; 915 encoder->compute_config = intel_lvds_compute_config; 916 if (HAS_PCH_SPLIT(i915)) { 917 encoder->disable = pch_disable_lvds; 918 encoder->post_disable = pch_post_disable_lvds; 919 } else { 920 encoder->disable = gmch_disable_lvds; 921 } 922 encoder->get_hw_state = intel_lvds_get_hw_state; 923 encoder->get_config = intel_lvds_get_config; 924 encoder->update_pipe = intel_backlight_update; 925 encoder->shutdown = intel_lvds_shutdown; 926 connector->get_hw_state = intel_connector_get_hw_state; 927 928 intel_connector_attach_encoder(connector, encoder); 929 930 encoder->type = INTEL_OUTPUT_LVDS; 931 encoder->power_domain = POWER_DOMAIN_PORT_OTHER; 932 encoder->port = PORT_NONE; 933 encoder->cloneable = 0; 934 if (DISPLAY_VER(i915) < 4) 935 encoder->pipe_mask = BIT(PIPE_B); 936 else 937 encoder->pipe_mask = ~0; 938 939 drm_connector_helper_add(&connector->base, &intel_lvds_connector_helper_funcs); 940 connector->base.display_info.subpixel_order = SubPixelHorizontalRGB; 941 942 lvds_encoder->reg = lvds_reg; 943 944 intel_lvds_add_properties(&connector->base); 945 946 intel_lvds_pps_get_hw_state(i915, &lvds_encoder->init_pps); 947 lvds_encoder->init_lvds_val = lvds; 948 949 /* 950 * LVDS discovery: 951 * 1) check for EDID on DDC 952 * 2) check for VBT data 953 * 3) check to see if LVDS is already on 954 * if none of the above, no panel 955 */ 956 957 /* 958 * Attempt to get the fixed panel mode from DDC. Assume that the 959 * preferred mode is the right one. 960 */ 961 mutex_lock(&i915->drm.mode_config.mutex); 962 if (vga_switcheroo_handler_flags() & VGA_SWITCHEROO_CAN_SWITCH_DDC) 963 drm_edid = drm_edid_read_switcheroo(&connector->base, connector->base.ddc); 964 else 965 drm_edid = drm_edid_read_ddc(&connector->base, connector->base.ddc); 966 if (drm_edid) { 967 if (drm_edid_connector_update(&connector->base, drm_edid) || 968 !drm_edid_connector_add_modes(&connector->base)) { 969 drm_edid_connector_update(&connector->base, NULL); 970 drm_edid_free(drm_edid); 971 drm_edid = ERR_PTR(-EINVAL); 972 } 973 } else { 974 drm_edid = ERR_PTR(-ENOENT); 975 } 976 intel_bios_init_panel_late(display, &connector->panel, NULL, 977 IS_ERR(drm_edid) ? NULL : drm_edid); 978 979 /* Try EDID first */ 980 intel_panel_add_edid_fixed_modes(connector, true); 981 982 /* Failed to get EDID, what about VBT? */ 983 if (!intel_panel_preferred_fixed_mode(connector)) 984 intel_panel_add_vbt_lfp_fixed_mode(connector); 985 986 /* 987 * If we didn't get a fixed mode from EDID or VBT, try checking 988 * if the panel is already turned on. If so, assume that 989 * whatever is currently programmed is the correct mode. 990 */ 991 if (!intel_panel_preferred_fixed_mode(connector)) 992 intel_panel_add_encoder_fixed_mode(connector, encoder); 993 994 mutex_unlock(&i915->drm.mode_config.mutex); 995 996 /* If we still don't have a mode after all that, give up. */ 997 if (!intel_panel_preferred_fixed_mode(connector)) 998 goto failed; 999 1000 intel_panel_init(connector, drm_edid); 1001 1002 intel_backlight_setup(connector, INVALID_PIPE); 1003 1004 lvds_encoder->is_dual_link = compute_is_dual_link_lvds(lvds_encoder); 1005 drm_dbg_kms(&i915->drm, "detected %s-link lvds configuration\n", 1006 lvds_encoder->is_dual_link ? "dual" : "single"); 1007 1008 lvds_encoder->a3_power = lvds & LVDS_A3_POWER_MASK; 1009 1010 return; 1011 1012 failed: 1013 drm_dbg_kms(&i915->drm, "No LVDS modes found, disabling.\n"); 1014 drm_connector_cleanup(&connector->base); 1015 drm_encoder_cleanup(&encoder->base); 1016 kfree(lvds_encoder); 1017 intel_connector_free(connector); 1018 return; 1019 } 1020