1 /* 2 * Copyright © 2006-2007 Intel Corporation 3 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie> 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 22 * DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: 25 * Eric Anholt <eric@anholt.net> 26 * Dave Airlie <airlied@linux.ie> 27 * Jesse Barnes <jesse.barnes@intel.com> 28 */ 29 30 #include <acpi/button.h> 31 #include <linux/acpi.h> 32 #include <linux/dmi.h> 33 #include <linux/i2c.h> 34 #include <linux/slab.h> 35 #include <linux/vga_switcheroo.h> 36 37 #include <drm/drm_atomic_helper.h> 38 #include <drm/drm_crtc.h> 39 #include <drm/drm_edid.h> 40 41 #include "i915_drv.h" 42 #include "intel_atomic.h" 43 #include "intel_backlight.h" 44 #include "intel_connector.h" 45 #include "intel_de.h" 46 #include "intel_display_types.h" 47 #include "intel_dpll.h" 48 #include "intel_fdi.h" 49 #include "intel_gmbus.h" 50 #include "intel_lvds.h" 51 #include "intel_panel.h" 52 53 /* Private structure for the integrated LVDS support */ 54 struct intel_lvds_pps { 55 /* 100us units */ 56 int t1_t2; 57 int t3; 58 int t4; 59 int t5; 60 int tx; 61 62 int divider; 63 64 int port; 65 bool powerdown_on_reset; 66 }; 67 68 struct intel_lvds_encoder { 69 struct intel_encoder base; 70 71 bool is_dual_link; 72 i915_reg_t reg; 73 u32 a3_power; 74 75 struct intel_lvds_pps init_pps; 76 u32 init_lvds_val; 77 78 struct intel_connector *attached_connector; 79 }; 80 81 static struct intel_lvds_encoder *to_lvds_encoder(struct drm_encoder *encoder) 82 { 83 return container_of(encoder, struct intel_lvds_encoder, base.base); 84 } 85 86 bool intel_lvds_port_enabled(struct drm_i915_private *dev_priv, 87 i915_reg_t lvds_reg, enum pipe *pipe) 88 { 89 u32 val; 90 91 val = intel_de_read(dev_priv, lvds_reg); 92 93 /* asserts want to know the pipe even if the port is disabled */ 94 if (HAS_PCH_CPT(dev_priv)) 95 *pipe = (val & LVDS_PIPE_SEL_MASK_CPT) >> LVDS_PIPE_SEL_SHIFT_CPT; 96 else 97 *pipe = (val & LVDS_PIPE_SEL_MASK) >> LVDS_PIPE_SEL_SHIFT; 98 99 return val & LVDS_PORT_EN; 100 } 101 102 static bool intel_lvds_get_hw_state(struct intel_encoder *encoder, 103 enum pipe *pipe) 104 { 105 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 106 struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base); 107 intel_wakeref_t wakeref; 108 bool ret; 109 110 wakeref = intel_display_power_get_if_enabled(dev_priv, 111 encoder->power_domain); 112 if (!wakeref) 113 return false; 114 115 ret = intel_lvds_port_enabled(dev_priv, lvds_encoder->reg, pipe); 116 117 intel_display_power_put(dev_priv, encoder->power_domain, wakeref); 118 119 return ret; 120 } 121 122 static void intel_lvds_get_config(struct intel_encoder *encoder, 123 struct intel_crtc_state *pipe_config) 124 { 125 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 126 struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base); 127 u32 tmp, flags = 0; 128 129 pipe_config->output_types |= BIT(INTEL_OUTPUT_LVDS); 130 131 tmp = intel_de_read(dev_priv, lvds_encoder->reg); 132 if (tmp & LVDS_HSYNC_POLARITY) 133 flags |= DRM_MODE_FLAG_NHSYNC; 134 else 135 flags |= DRM_MODE_FLAG_PHSYNC; 136 if (tmp & LVDS_VSYNC_POLARITY) 137 flags |= DRM_MODE_FLAG_NVSYNC; 138 else 139 flags |= DRM_MODE_FLAG_PVSYNC; 140 141 pipe_config->hw.adjusted_mode.flags |= flags; 142 143 if (DISPLAY_VER(dev_priv) < 5) 144 pipe_config->gmch_pfit.lvds_border_bits = 145 tmp & LVDS_BORDER_ENABLE; 146 147 /* gen2/3 store dither state in pfit control, needs to match */ 148 if (DISPLAY_VER(dev_priv) < 4) { 149 tmp = intel_de_read(dev_priv, PFIT_CONTROL); 150 151 pipe_config->gmch_pfit.control |= tmp & PANEL_8TO6_DITHER_ENABLE; 152 } 153 154 pipe_config->hw.adjusted_mode.crtc_clock = pipe_config->port_clock; 155 } 156 157 static void intel_lvds_pps_get_hw_state(struct drm_i915_private *dev_priv, 158 struct intel_lvds_pps *pps) 159 { 160 u32 val; 161 162 pps->powerdown_on_reset = intel_de_read(dev_priv, PP_CONTROL(0)) & PANEL_POWER_RESET; 163 164 val = intel_de_read(dev_priv, PP_ON_DELAYS(0)); 165 pps->port = REG_FIELD_GET(PANEL_PORT_SELECT_MASK, val); 166 pps->t1_t2 = REG_FIELD_GET(PANEL_POWER_UP_DELAY_MASK, val); 167 pps->t5 = REG_FIELD_GET(PANEL_LIGHT_ON_DELAY_MASK, val); 168 169 val = intel_de_read(dev_priv, PP_OFF_DELAYS(0)); 170 pps->t3 = REG_FIELD_GET(PANEL_POWER_DOWN_DELAY_MASK, val); 171 pps->tx = REG_FIELD_GET(PANEL_LIGHT_OFF_DELAY_MASK, val); 172 173 val = intel_de_read(dev_priv, PP_DIVISOR(0)); 174 pps->divider = REG_FIELD_GET(PP_REFERENCE_DIVIDER_MASK, val); 175 val = REG_FIELD_GET(PANEL_POWER_CYCLE_DELAY_MASK, val); 176 /* 177 * Remove the BSpec specified +1 (100ms) offset that accounts for a 178 * too short power-cycle delay due to the asynchronous programming of 179 * the register. 180 */ 181 if (val) 182 val--; 183 /* Convert from 100ms to 100us units */ 184 pps->t4 = val * 1000; 185 186 if (DISPLAY_VER(dev_priv) <= 4 && 187 pps->t1_t2 == 0 && pps->t5 == 0 && pps->t3 == 0 && pps->tx == 0) { 188 drm_dbg_kms(&dev_priv->drm, 189 "Panel power timings uninitialized, " 190 "setting defaults\n"); 191 /* Set T2 to 40ms and T5 to 200ms in 100 usec units */ 192 pps->t1_t2 = 40 * 10; 193 pps->t5 = 200 * 10; 194 /* Set T3 to 35ms and Tx to 200ms in 100 usec units */ 195 pps->t3 = 35 * 10; 196 pps->tx = 200 * 10; 197 } 198 199 drm_dbg(&dev_priv->drm, "LVDS PPS:t1+t2 %d t3 %d t4 %d t5 %d tx %d " 200 "divider %d port %d powerdown_on_reset %d\n", 201 pps->t1_t2, pps->t3, pps->t4, pps->t5, pps->tx, 202 pps->divider, pps->port, pps->powerdown_on_reset); 203 } 204 205 static void intel_lvds_pps_init_hw(struct drm_i915_private *dev_priv, 206 struct intel_lvds_pps *pps) 207 { 208 u32 val; 209 210 val = intel_de_read(dev_priv, PP_CONTROL(0)); 211 drm_WARN_ON(&dev_priv->drm, 212 (val & PANEL_UNLOCK_MASK) != PANEL_UNLOCK_REGS); 213 if (pps->powerdown_on_reset) 214 val |= PANEL_POWER_RESET; 215 intel_de_write(dev_priv, PP_CONTROL(0), val); 216 217 intel_de_write(dev_priv, PP_ON_DELAYS(0), 218 REG_FIELD_PREP(PANEL_PORT_SELECT_MASK, pps->port) | REG_FIELD_PREP(PANEL_POWER_UP_DELAY_MASK, pps->t1_t2) | REG_FIELD_PREP(PANEL_LIGHT_ON_DELAY_MASK, pps->t5)); 219 220 intel_de_write(dev_priv, PP_OFF_DELAYS(0), 221 REG_FIELD_PREP(PANEL_POWER_DOWN_DELAY_MASK, pps->t3) | REG_FIELD_PREP(PANEL_LIGHT_OFF_DELAY_MASK, pps->tx)); 222 223 intel_de_write(dev_priv, PP_DIVISOR(0), 224 REG_FIELD_PREP(PP_REFERENCE_DIVIDER_MASK, pps->divider) | REG_FIELD_PREP(PANEL_POWER_CYCLE_DELAY_MASK, DIV_ROUND_UP(pps->t4, 1000) + 1)); 225 } 226 227 static void intel_pre_enable_lvds(struct intel_atomic_state *state, 228 struct intel_encoder *encoder, 229 const struct intel_crtc_state *pipe_config, 230 const struct drm_connector_state *conn_state) 231 { 232 struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base); 233 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 234 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 235 const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode; 236 enum pipe pipe = crtc->pipe; 237 u32 temp; 238 239 if (HAS_PCH_SPLIT(dev_priv)) { 240 assert_fdi_rx_pll_disabled(dev_priv, pipe); 241 assert_shared_dpll_disabled(dev_priv, 242 pipe_config->shared_dpll); 243 } else { 244 assert_pll_disabled(dev_priv, pipe); 245 } 246 247 intel_lvds_pps_init_hw(dev_priv, &lvds_encoder->init_pps); 248 249 temp = lvds_encoder->init_lvds_val; 250 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP; 251 252 if (HAS_PCH_CPT(dev_priv)) { 253 temp &= ~LVDS_PIPE_SEL_MASK_CPT; 254 temp |= LVDS_PIPE_SEL_CPT(pipe); 255 } else { 256 temp &= ~LVDS_PIPE_SEL_MASK; 257 temp |= LVDS_PIPE_SEL(pipe); 258 } 259 260 /* set the corresponsding LVDS_BORDER bit */ 261 temp &= ~LVDS_BORDER_ENABLE; 262 temp |= pipe_config->gmch_pfit.lvds_border_bits; 263 264 /* 265 * Set the B0-B3 data pairs corresponding to whether we're going to 266 * set the DPLLs for dual-channel mode or not. 267 */ 268 if (lvds_encoder->is_dual_link) 269 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP; 270 else 271 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP); 272 273 /* 274 * It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP) 275 * appropriately here, but we need to look more thoroughly into how 276 * panels behave in the two modes. For now, let's just maintain the 277 * value we got from the BIOS. 278 */ 279 temp &= ~LVDS_A3_POWER_MASK; 280 temp |= lvds_encoder->a3_power; 281 282 /* 283 * Set the dithering flag on LVDS as needed, note that there is no 284 * special lvds dither control bit on pch-split platforms, dithering is 285 * only controlled through the PIPECONF reg. 286 */ 287 if (DISPLAY_VER(dev_priv) == 4) { 288 /* 289 * Bspec wording suggests that LVDS port dithering only exists 290 * for 18bpp panels. 291 */ 292 if (pipe_config->dither && pipe_config->pipe_bpp == 18) 293 temp |= LVDS_ENABLE_DITHER; 294 else 295 temp &= ~LVDS_ENABLE_DITHER; 296 } 297 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY); 298 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC) 299 temp |= LVDS_HSYNC_POLARITY; 300 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC) 301 temp |= LVDS_VSYNC_POLARITY; 302 303 intel_de_write(dev_priv, lvds_encoder->reg, temp); 304 } 305 306 /* 307 * Sets the power state for the panel. 308 */ 309 static void intel_enable_lvds(struct intel_atomic_state *state, 310 struct intel_encoder *encoder, 311 const struct intel_crtc_state *pipe_config, 312 const struct drm_connector_state *conn_state) 313 { 314 struct drm_device *dev = encoder->base.dev; 315 struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base); 316 struct drm_i915_private *dev_priv = to_i915(dev); 317 318 intel_de_write(dev_priv, lvds_encoder->reg, 319 intel_de_read(dev_priv, lvds_encoder->reg) | LVDS_PORT_EN); 320 321 intel_de_write(dev_priv, PP_CONTROL(0), 322 intel_de_read(dev_priv, PP_CONTROL(0)) | PANEL_POWER_ON); 323 intel_de_posting_read(dev_priv, lvds_encoder->reg); 324 325 if (intel_de_wait_for_set(dev_priv, PP_STATUS(0), PP_ON, 5000)) 326 drm_err(&dev_priv->drm, 327 "timed out waiting for panel to power on\n"); 328 329 intel_backlight_enable(pipe_config, conn_state); 330 } 331 332 static void intel_disable_lvds(struct intel_atomic_state *state, 333 struct intel_encoder *encoder, 334 const struct intel_crtc_state *old_crtc_state, 335 const struct drm_connector_state *old_conn_state) 336 { 337 struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base); 338 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 339 340 intel_de_write(dev_priv, PP_CONTROL(0), 341 intel_de_read(dev_priv, PP_CONTROL(0)) & ~PANEL_POWER_ON); 342 if (intel_de_wait_for_clear(dev_priv, PP_STATUS(0), PP_ON, 1000)) 343 drm_err(&dev_priv->drm, 344 "timed out waiting for panel to power off\n"); 345 346 intel_de_write(dev_priv, lvds_encoder->reg, 347 intel_de_read(dev_priv, lvds_encoder->reg) & ~LVDS_PORT_EN); 348 intel_de_posting_read(dev_priv, lvds_encoder->reg); 349 } 350 351 static void gmch_disable_lvds(struct intel_atomic_state *state, 352 struct intel_encoder *encoder, 353 const struct intel_crtc_state *old_crtc_state, 354 const struct drm_connector_state *old_conn_state) 355 356 { 357 intel_backlight_disable(old_conn_state); 358 359 intel_disable_lvds(state, encoder, old_crtc_state, old_conn_state); 360 } 361 362 static void pch_disable_lvds(struct intel_atomic_state *state, 363 struct intel_encoder *encoder, 364 const struct intel_crtc_state *old_crtc_state, 365 const struct drm_connector_state *old_conn_state) 366 { 367 intel_backlight_disable(old_conn_state); 368 } 369 370 static void pch_post_disable_lvds(struct intel_atomic_state *state, 371 struct intel_encoder *encoder, 372 const struct intel_crtc_state *old_crtc_state, 373 const struct drm_connector_state *old_conn_state) 374 { 375 intel_disable_lvds(state, encoder, old_crtc_state, old_conn_state); 376 } 377 378 static void intel_lvds_shutdown(struct intel_encoder *encoder) 379 { 380 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 381 382 if (intel_de_wait_for_clear(dev_priv, PP_STATUS(0), PP_CYCLE_DELAY_ACTIVE, 5000)) 383 drm_err(&dev_priv->drm, 384 "timed out waiting for panel power cycle delay\n"); 385 } 386 387 static enum drm_mode_status 388 intel_lvds_mode_valid(struct drm_connector *connector, 389 struct drm_display_mode *mode) 390 { 391 struct intel_connector *intel_connector = to_intel_connector(connector); 392 const struct drm_display_mode *fixed_mode = 393 intel_panel_fixed_mode(intel_connector, mode); 394 int max_pixclk = to_i915(connector->dev)->max_dotclk_freq; 395 enum drm_mode_status status; 396 397 if (mode->flags & DRM_MODE_FLAG_DBLSCAN) 398 return MODE_NO_DBLESCAN; 399 400 status = intel_panel_mode_valid(intel_connector, mode); 401 if (status != MODE_OK) 402 return status; 403 404 if (fixed_mode->clock > max_pixclk) 405 return MODE_CLOCK_HIGH; 406 407 return MODE_OK; 408 } 409 410 static int intel_lvds_compute_config(struct intel_encoder *intel_encoder, 411 struct intel_crtc_state *pipe_config, 412 struct drm_connector_state *conn_state) 413 { 414 struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev); 415 struct intel_lvds_encoder *lvds_encoder = 416 to_lvds_encoder(&intel_encoder->base); 417 struct intel_connector *intel_connector = 418 lvds_encoder->attached_connector; 419 struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode; 420 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 421 unsigned int lvds_bpp; 422 int ret; 423 424 /* Should never happen!! */ 425 if (DISPLAY_VER(dev_priv) < 4 && crtc->pipe == 0) { 426 drm_err(&dev_priv->drm, "Can't support LVDS on pipe A\n"); 427 return -EINVAL; 428 } 429 430 if (lvds_encoder->a3_power == LVDS_A3_POWER_UP) 431 lvds_bpp = 8*3; 432 else 433 lvds_bpp = 6*3; 434 435 if (lvds_bpp != pipe_config->pipe_bpp && !pipe_config->bw_constrained) { 436 drm_dbg_kms(&dev_priv->drm, 437 "forcing display bpp (was %d) to LVDS (%d)\n", 438 pipe_config->pipe_bpp, lvds_bpp); 439 pipe_config->pipe_bpp = lvds_bpp; 440 } 441 442 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; 443 444 /* 445 * We have timings from the BIOS for the panel, put them in 446 * to the adjusted mode. The CRTC will be set up for this mode, 447 * with the panel scaling set up to source from the H/VDisplay 448 * of the original mode. 449 */ 450 ret = intel_panel_compute_config(intel_connector, adjusted_mode); 451 if (ret) 452 return ret; 453 454 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN) 455 return -EINVAL; 456 457 if (HAS_PCH_SPLIT(dev_priv)) 458 pipe_config->has_pch_encoder = true; 459 460 ret = intel_panel_fitting(pipe_config, conn_state); 461 if (ret) 462 return ret; 463 464 /* 465 * XXX: It would be nice to support lower refresh rates on the 466 * panels to reduce power consumption, and perhaps match the 467 * user's requested refresh rate. 468 */ 469 470 return 0; 471 } 472 473 /* 474 * Return the list of DDC modes if available, or the BIOS fixed mode otherwise. 475 */ 476 static int intel_lvds_get_modes(struct drm_connector *connector) 477 { 478 struct intel_connector *intel_connector = to_intel_connector(connector); 479 480 /* use cached edid if we have one */ 481 if (!IS_ERR_OR_NULL(intel_connector->edid)) 482 return drm_add_edid_modes(connector, intel_connector->edid); 483 484 return intel_panel_get_modes(intel_connector); 485 } 486 487 static const struct drm_connector_helper_funcs intel_lvds_connector_helper_funcs = { 488 .get_modes = intel_lvds_get_modes, 489 .mode_valid = intel_lvds_mode_valid, 490 .atomic_check = intel_digital_connector_atomic_check, 491 }; 492 493 static const struct drm_connector_funcs intel_lvds_connector_funcs = { 494 .detect = intel_panel_detect, 495 .fill_modes = drm_helper_probe_single_connector_modes, 496 .atomic_get_property = intel_digital_connector_atomic_get_property, 497 .atomic_set_property = intel_digital_connector_atomic_set_property, 498 .late_register = intel_connector_register, 499 .early_unregister = intel_connector_unregister, 500 .destroy = intel_connector_destroy, 501 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 502 .atomic_duplicate_state = intel_digital_connector_duplicate_state, 503 }; 504 505 static const struct drm_encoder_funcs intel_lvds_enc_funcs = { 506 .destroy = intel_encoder_destroy, 507 }; 508 509 static int intel_no_lvds_dmi_callback(const struct dmi_system_id *id) 510 { 511 DRM_INFO("Skipping LVDS initialization for %s\n", id->ident); 512 return 1; 513 } 514 515 /* These systems claim to have LVDS, but really don't */ 516 static const struct dmi_system_id intel_no_lvds[] = { 517 { 518 .callback = intel_no_lvds_dmi_callback, 519 .ident = "Apple Mac Mini (Core series)", 520 .matches = { 521 DMI_MATCH(DMI_SYS_VENDOR, "Apple"), 522 DMI_MATCH(DMI_PRODUCT_NAME, "Macmini1,1"), 523 }, 524 }, 525 { 526 .callback = intel_no_lvds_dmi_callback, 527 .ident = "Apple Mac Mini (Core 2 series)", 528 .matches = { 529 DMI_MATCH(DMI_SYS_VENDOR, "Apple"), 530 DMI_MATCH(DMI_PRODUCT_NAME, "Macmini2,1"), 531 }, 532 }, 533 { 534 .callback = intel_no_lvds_dmi_callback, 535 .ident = "MSI IM-945GSE-A", 536 .matches = { 537 DMI_MATCH(DMI_SYS_VENDOR, "MSI"), 538 DMI_MATCH(DMI_PRODUCT_NAME, "A9830IMS"), 539 }, 540 }, 541 { 542 .callback = intel_no_lvds_dmi_callback, 543 .ident = "Dell Studio Hybrid", 544 .matches = { 545 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), 546 DMI_MATCH(DMI_PRODUCT_NAME, "Studio Hybrid 140g"), 547 }, 548 }, 549 { 550 .callback = intel_no_lvds_dmi_callback, 551 .ident = "Dell OptiPlex FX170", 552 .matches = { 553 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), 554 DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex FX170"), 555 }, 556 }, 557 { 558 .callback = intel_no_lvds_dmi_callback, 559 .ident = "AOpen Mini PC", 560 .matches = { 561 DMI_MATCH(DMI_SYS_VENDOR, "AOpen"), 562 DMI_MATCH(DMI_PRODUCT_NAME, "i965GMx-IF"), 563 }, 564 }, 565 { 566 .callback = intel_no_lvds_dmi_callback, 567 .ident = "AOpen Mini PC MP915", 568 .matches = { 569 DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"), 570 DMI_MATCH(DMI_BOARD_NAME, "i915GMx-F"), 571 }, 572 }, 573 { 574 .callback = intel_no_lvds_dmi_callback, 575 .ident = "AOpen i915GMm-HFS", 576 .matches = { 577 DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"), 578 DMI_MATCH(DMI_BOARD_NAME, "i915GMm-HFS"), 579 }, 580 }, 581 { 582 .callback = intel_no_lvds_dmi_callback, 583 .ident = "AOpen i45GMx-I", 584 .matches = { 585 DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"), 586 DMI_MATCH(DMI_BOARD_NAME, "i45GMx-I"), 587 }, 588 }, 589 { 590 .callback = intel_no_lvds_dmi_callback, 591 .ident = "Aopen i945GTt-VFA", 592 .matches = { 593 DMI_MATCH(DMI_PRODUCT_VERSION, "AO00001JW"), 594 }, 595 }, 596 { 597 .callback = intel_no_lvds_dmi_callback, 598 .ident = "Clientron U800", 599 .matches = { 600 DMI_MATCH(DMI_SYS_VENDOR, "Clientron"), 601 DMI_MATCH(DMI_PRODUCT_NAME, "U800"), 602 }, 603 }, 604 { 605 .callback = intel_no_lvds_dmi_callback, 606 .ident = "Clientron E830", 607 .matches = { 608 DMI_MATCH(DMI_SYS_VENDOR, "Clientron"), 609 DMI_MATCH(DMI_PRODUCT_NAME, "E830"), 610 }, 611 }, 612 { 613 .callback = intel_no_lvds_dmi_callback, 614 .ident = "Asus EeeBox PC EB1007", 615 .matches = { 616 DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK Computer INC."), 617 DMI_MATCH(DMI_PRODUCT_NAME, "EB1007"), 618 }, 619 }, 620 { 621 .callback = intel_no_lvds_dmi_callback, 622 .ident = "Asus AT5NM10T-I", 623 .matches = { 624 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), 625 DMI_MATCH(DMI_BOARD_NAME, "AT5NM10T-I"), 626 }, 627 }, 628 { 629 .callback = intel_no_lvds_dmi_callback, 630 .ident = "Hewlett-Packard HP t5740", 631 .matches = { 632 DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"), 633 DMI_MATCH(DMI_PRODUCT_NAME, " t5740"), 634 }, 635 }, 636 { 637 .callback = intel_no_lvds_dmi_callback, 638 .ident = "Hewlett-Packard t5745", 639 .matches = { 640 DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"), 641 DMI_MATCH(DMI_PRODUCT_NAME, "hp t5745"), 642 }, 643 }, 644 { 645 .callback = intel_no_lvds_dmi_callback, 646 .ident = "Hewlett-Packard st5747", 647 .matches = { 648 DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"), 649 DMI_MATCH(DMI_PRODUCT_NAME, "hp st5747"), 650 }, 651 }, 652 { 653 .callback = intel_no_lvds_dmi_callback, 654 .ident = "MSI Wind Box DC500", 655 .matches = { 656 DMI_MATCH(DMI_BOARD_VENDOR, "MICRO-STAR INTERNATIONAL CO., LTD"), 657 DMI_MATCH(DMI_BOARD_NAME, "MS-7469"), 658 }, 659 }, 660 { 661 .callback = intel_no_lvds_dmi_callback, 662 .ident = "Gigabyte GA-D525TUD", 663 .matches = { 664 DMI_MATCH(DMI_BOARD_VENDOR, "Gigabyte Technology Co., Ltd."), 665 DMI_MATCH(DMI_BOARD_NAME, "D525TUD"), 666 }, 667 }, 668 { 669 .callback = intel_no_lvds_dmi_callback, 670 .ident = "Supermicro X7SPA-H", 671 .matches = { 672 DMI_MATCH(DMI_SYS_VENDOR, "Supermicro"), 673 DMI_MATCH(DMI_PRODUCT_NAME, "X7SPA-H"), 674 }, 675 }, 676 { 677 .callback = intel_no_lvds_dmi_callback, 678 .ident = "Fujitsu Esprimo Q900", 679 .matches = { 680 DMI_MATCH(DMI_SYS_VENDOR, "FUJITSU"), 681 DMI_MATCH(DMI_PRODUCT_NAME, "ESPRIMO Q900"), 682 }, 683 }, 684 { 685 .callback = intel_no_lvds_dmi_callback, 686 .ident = "Intel D410PT", 687 .matches = { 688 DMI_MATCH(DMI_BOARD_VENDOR, "Intel"), 689 DMI_MATCH(DMI_BOARD_NAME, "D410PT"), 690 }, 691 }, 692 { 693 .callback = intel_no_lvds_dmi_callback, 694 .ident = "Intel D425KT", 695 .matches = { 696 DMI_MATCH(DMI_BOARD_VENDOR, "Intel"), 697 DMI_EXACT_MATCH(DMI_BOARD_NAME, "D425KT"), 698 }, 699 }, 700 { 701 .callback = intel_no_lvds_dmi_callback, 702 .ident = "Intel D510MO", 703 .matches = { 704 DMI_MATCH(DMI_BOARD_VENDOR, "Intel"), 705 DMI_EXACT_MATCH(DMI_BOARD_NAME, "D510MO"), 706 }, 707 }, 708 { 709 .callback = intel_no_lvds_dmi_callback, 710 .ident = "Intel D525MW", 711 .matches = { 712 DMI_MATCH(DMI_BOARD_VENDOR, "Intel"), 713 DMI_EXACT_MATCH(DMI_BOARD_NAME, "D525MW"), 714 }, 715 }, 716 { 717 .callback = intel_no_lvds_dmi_callback, 718 .ident = "Radiant P845", 719 .matches = { 720 DMI_MATCH(DMI_SYS_VENDOR, "Radiant Systems Inc"), 721 DMI_MATCH(DMI_PRODUCT_NAME, "P845"), 722 }, 723 }, 724 725 { } /* terminating entry */ 726 }; 727 728 static int intel_dual_link_lvds_callback(const struct dmi_system_id *id) 729 { 730 DRM_INFO("Forcing lvds to dual link mode on %s\n", id->ident); 731 return 1; 732 } 733 734 static const struct dmi_system_id intel_dual_link_lvds[] = { 735 { 736 .callback = intel_dual_link_lvds_callback, 737 .ident = "Apple MacBook Pro 15\" (2010)", 738 .matches = { 739 DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."), 740 DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro6,2"), 741 }, 742 }, 743 { 744 .callback = intel_dual_link_lvds_callback, 745 .ident = "Apple MacBook Pro 15\" (2011)", 746 .matches = { 747 DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."), 748 DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro8,2"), 749 }, 750 }, 751 { 752 .callback = intel_dual_link_lvds_callback, 753 .ident = "Apple MacBook Pro 15\" (2012)", 754 .matches = { 755 DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."), 756 DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro9,1"), 757 }, 758 }, 759 { } /* terminating entry */ 760 }; 761 762 struct intel_encoder *intel_get_lvds_encoder(struct drm_i915_private *dev_priv) 763 { 764 struct intel_encoder *encoder; 765 766 for_each_intel_encoder(&dev_priv->drm, encoder) { 767 if (encoder->type == INTEL_OUTPUT_LVDS) 768 return encoder; 769 } 770 771 return NULL; 772 } 773 774 bool intel_is_dual_link_lvds(struct drm_i915_private *dev_priv) 775 { 776 struct intel_encoder *encoder = intel_get_lvds_encoder(dev_priv); 777 778 return encoder && to_lvds_encoder(&encoder->base)->is_dual_link; 779 } 780 781 static bool compute_is_dual_link_lvds(struct intel_lvds_encoder *lvds_encoder) 782 { 783 struct drm_i915_private *dev_priv = to_i915(lvds_encoder->base.base.dev); 784 struct intel_connector *connector = lvds_encoder->attached_connector; 785 const struct drm_display_mode *fixed_mode = 786 intel_panel_preferred_fixed_mode(connector); 787 unsigned int val; 788 789 /* use the module option value if specified */ 790 if (dev_priv->params.lvds_channel_mode > 0) 791 return dev_priv->params.lvds_channel_mode == 2; 792 793 /* single channel LVDS is limited to 112 MHz */ 794 if (fixed_mode->clock > 112999) 795 return true; 796 797 if (dmi_check_system(intel_dual_link_lvds)) 798 return true; 799 800 /* 801 * BIOS should set the proper LVDS register value at boot, but 802 * in reality, it doesn't set the value when the lid is closed; 803 * we need to check "the value to be set" in VBT when LVDS 804 * register is uninitialized. 805 */ 806 val = intel_de_read(dev_priv, lvds_encoder->reg); 807 if (HAS_PCH_CPT(dev_priv)) 808 val &= ~(LVDS_DETECTED | LVDS_PIPE_SEL_MASK_CPT); 809 else 810 val &= ~(LVDS_DETECTED | LVDS_PIPE_SEL_MASK); 811 if (val == 0) 812 val = connector->panel.vbt.bios_lvds_val; 813 814 return (val & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP; 815 } 816 817 /** 818 * intel_lvds_init - setup LVDS connectors on this device 819 * @dev_priv: i915 device 820 * 821 * Create the connector, register the LVDS DDC bus, and try to figure out what 822 * modes we can display on the LVDS panel (if present). 823 */ 824 void intel_lvds_init(struct drm_i915_private *dev_priv) 825 { 826 struct drm_device *dev = &dev_priv->drm; 827 struct intel_lvds_encoder *lvds_encoder; 828 struct intel_encoder *intel_encoder; 829 struct intel_connector *intel_connector; 830 struct drm_connector *connector; 831 struct drm_encoder *encoder; 832 struct edid *edid; 833 i915_reg_t lvds_reg; 834 u32 lvds; 835 u8 pin; 836 u32 allowed_scalers; 837 838 /* Skip init on machines we know falsely report LVDS */ 839 if (dmi_check_system(intel_no_lvds)) { 840 drm_WARN(dev, !dev_priv->vbt.int_lvds_support, 841 "Useless DMI match. Internal LVDS support disabled by VBT\n"); 842 return; 843 } 844 845 if (!dev_priv->vbt.int_lvds_support) { 846 drm_dbg_kms(&dev_priv->drm, 847 "Internal LVDS support disabled by VBT\n"); 848 return; 849 } 850 851 if (HAS_PCH_SPLIT(dev_priv)) 852 lvds_reg = PCH_LVDS; 853 else 854 lvds_reg = LVDS; 855 856 lvds = intel_de_read(dev_priv, lvds_reg); 857 858 if (HAS_PCH_SPLIT(dev_priv)) { 859 if ((lvds & LVDS_DETECTED) == 0) 860 return; 861 } 862 863 pin = GMBUS_PIN_PANEL; 864 if (!intel_bios_is_lvds_present(dev_priv, &pin)) { 865 if ((lvds & LVDS_PORT_EN) == 0) { 866 drm_dbg_kms(&dev_priv->drm, 867 "LVDS is not present in VBT\n"); 868 return; 869 } 870 drm_dbg_kms(&dev_priv->drm, 871 "LVDS is not present in VBT, but enabled anyway\n"); 872 } 873 874 lvds_encoder = kzalloc(sizeof(*lvds_encoder), GFP_KERNEL); 875 if (!lvds_encoder) 876 return; 877 878 intel_connector = intel_connector_alloc(); 879 if (!intel_connector) { 880 kfree(lvds_encoder); 881 return; 882 } 883 884 lvds_encoder->attached_connector = intel_connector; 885 886 intel_encoder = &lvds_encoder->base; 887 encoder = &intel_encoder->base; 888 connector = &intel_connector->base; 889 drm_connector_init(dev, &intel_connector->base, &intel_lvds_connector_funcs, 890 DRM_MODE_CONNECTOR_LVDS); 891 892 drm_encoder_init(dev, &intel_encoder->base, &intel_lvds_enc_funcs, 893 DRM_MODE_ENCODER_LVDS, "LVDS"); 894 895 intel_encoder->enable = intel_enable_lvds; 896 intel_encoder->pre_enable = intel_pre_enable_lvds; 897 intel_encoder->compute_config = intel_lvds_compute_config; 898 if (HAS_PCH_SPLIT(dev_priv)) { 899 intel_encoder->disable = pch_disable_lvds; 900 intel_encoder->post_disable = pch_post_disable_lvds; 901 } else { 902 intel_encoder->disable = gmch_disable_lvds; 903 } 904 intel_encoder->get_hw_state = intel_lvds_get_hw_state; 905 intel_encoder->get_config = intel_lvds_get_config; 906 intel_encoder->update_pipe = intel_backlight_update; 907 intel_encoder->shutdown = intel_lvds_shutdown; 908 intel_connector->get_hw_state = intel_connector_get_hw_state; 909 910 intel_connector_attach_encoder(intel_connector, intel_encoder); 911 912 intel_encoder->type = INTEL_OUTPUT_LVDS; 913 intel_encoder->power_domain = POWER_DOMAIN_PORT_OTHER; 914 intel_encoder->port = PORT_NONE; 915 intel_encoder->cloneable = 0; 916 if (DISPLAY_VER(dev_priv) < 4) 917 intel_encoder->pipe_mask = BIT(PIPE_B); 918 else 919 intel_encoder->pipe_mask = ~0; 920 921 drm_connector_helper_add(connector, &intel_lvds_connector_helper_funcs); 922 connector->display_info.subpixel_order = SubPixelHorizontalRGB; 923 connector->interlace_allowed = false; 924 connector->doublescan_allowed = false; 925 926 lvds_encoder->reg = lvds_reg; 927 928 /* create the scaling mode property */ 929 allowed_scalers = BIT(DRM_MODE_SCALE_ASPECT); 930 allowed_scalers |= BIT(DRM_MODE_SCALE_FULLSCREEN); 931 allowed_scalers |= BIT(DRM_MODE_SCALE_CENTER); 932 drm_connector_attach_scaling_mode_property(connector, allowed_scalers); 933 connector->state->scaling_mode = DRM_MODE_SCALE_ASPECT; 934 935 intel_lvds_pps_get_hw_state(dev_priv, &lvds_encoder->init_pps); 936 lvds_encoder->init_lvds_val = lvds; 937 938 /* 939 * LVDS discovery: 940 * 1) check for EDID on DDC 941 * 2) check for VBT data 942 * 3) check to see if LVDS is already on 943 * if none of the above, no panel 944 */ 945 946 /* 947 * Attempt to get the fixed panel mode from DDC. Assume that the 948 * preferred mode is the right one. 949 */ 950 mutex_lock(&dev->mode_config.mutex); 951 if (vga_switcheroo_handler_flags() & VGA_SWITCHEROO_CAN_SWITCH_DDC) 952 edid = drm_get_edid_switcheroo(connector, 953 intel_gmbus_get_adapter(dev_priv, pin)); 954 else 955 edid = drm_get_edid(connector, 956 intel_gmbus_get_adapter(dev_priv, pin)); 957 if (edid) { 958 if (drm_add_edid_modes(connector, edid)) { 959 drm_connector_update_edid_property(connector, 960 edid); 961 } else { 962 kfree(edid); 963 edid = ERR_PTR(-EINVAL); 964 } 965 } else { 966 edid = ERR_PTR(-ENOENT); 967 } 968 intel_connector->edid = edid; 969 970 intel_bios_init_panel(dev_priv, &intel_connector->panel, NULL, 971 IS_ERR(edid) ? NULL : edid); 972 973 /* Try EDID first */ 974 intel_panel_add_edid_fixed_modes(intel_connector, 975 intel_connector->panel.vbt.drrs_type != DRRS_TYPE_NONE, 976 false); 977 978 /* Failed to get EDID, what about VBT? */ 979 if (!intel_panel_preferred_fixed_mode(intel_connector)) 980 intel_panel_add_vbt_lfp_fixed_mode(intel_connector); 981 982 /* 983 * If we didn't get a fixed mode from EDID or VBT, try checking 984 * if the panel is already turned on. If so, assume that 985 * whatever is currently programmed is the correct mode. 986 */ 987 if (!intel_panel_preferred_fixed_mode(intel_connector)) 988 intel_panel_add_encoder_fixed_mode(intel_connector, intel_encoder); 989 990 mutex_unlock(&dev->mode_config.mutex); 991 992 /* If we still don't have a mode after all that, give up. */ 993 if (!intel_panel_preferred_fixed_mode(intel_connector)) 994 goto failed; 995 996 intel_panel_init(intel_connector); 997 998 intel_backlight_setup(intel_connector, INVALID_PIPE); 999 1000 lvds_encoder->is_dual_link = compute_is_dual_link_lvds(lvds_encoder); 1001 drm_dbg_kms(&dev_priv->drm, "detected %s-link lvds configuration\n", 1002 lvds_encoder->is_dual_link ? "dual" : "single"); 1003 1004 lvds_encoder->a3_power = lvds & LVDS_A3_POWER_MASK; 1005 1006 return; 1007 1008 failed: 1009 drm_dbg_kms(&dev_priv->drm, "No LVDS modes found, disabling.\n"); 1010 drm_connector_cleanup(connector); 1011 drm_encoder_cleanup(encoder); 1012 kfree(lvds_encoder); 1013 intel_connector_free(intel_connector); 1014 return; 1015 } 1016