xref: /linux/drivers/gpu/drm/i915/display/intel_lvds.c (revision 336b78c655c84ce9ce47219185171b3912109c0a)
1 /*
2  * Copyright © 2006-2007 Intel Corporation
3  * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
4  *
5  * Permission is hereby granted, free of charge, to any person obtaining a
6  * copy of this software and associated documentation files (the "Software"),
7  * to deal in the Software without restriction, including without limitation
8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9  * and/or sell copies of the Software, and to permit persons to whom the
10  * Software is furnished to do so, subject to the following conditions:
11  *
12  * The above copyright notice and this permission notice (including the next
13  * paragraph) shall be included in all copies or substantial portions of the
14  * Software.
15  *
16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22  * DEALINGS IN THE SOFTWARE.
23  *
24  * Authors:
25  *	Eric Anholt <eric@anholt.net>
26  *      Dave Airlie <airlied@linux.ie>
27  *      Jesse Barnes <jesse.barnes@intel.com>
28  */
29 
30 #include <acpi/button.h>
31 #include <linux/acpi.h>
32 #include <linux/dmi.h>
33 #include <linux/i2c.h>
34 #include <linux/slab.h>
35 #include <linux/vga_switcheroo.h>
36 
37 #include <drm/drm_atomic_helper.h>
38 #include <drm/drm_crtc.h>
39 #include <drm/drm_edid.h>
40 
41 #include "i915_drv.h"
42 #include "i915_reg.h"
43 #include "intel_atomic.h"
44 #include "intel_backlight.h"
45 #include "intel_connector.h"
46 #include "intel_de.h"
47 #include "intel_display_types.h"
48 #include "intel_dpll.h"
49 #include "intel_fdi.h"
50 #include "intel_gmbus.h"
51 #include "intel_lvds.h"
52 #include "intel_lvds_regs.h"
53 #include "intel_panel.h"
54 
55 /* Private structure for the integrated LVDS support */
56 struct intel_lvds_pps {
57 	/* 100us units */
58 	int t1_t2;
59 	int t3;
60 	int t4;
61 	int t5;
62 	int tx;
63 
64 	int divider;
65 
66 	int port;
67 	bool powerdown_on_reset;
68 };
69 
70 struct intel_lvds_encoder {
71 	struct intel_encoder base;
72 
73 	bool is_dual_link;
74 	i915_reg_t reg;
75 	u32 a3_power;
76 
77 	struct intel_lvds_pps init_pps;
78 	u32 init_lvds_val;
79 
80 	struct intel_connector *attached_connector;
81 };
82 
83 static struct intel_lvds_encoder *to_lvds_encoder(struct intel_encoder *encoder)
84 {
85 	return container_of(encoder, struct intel_lvds_encoder, base);
86 }
87 
88 bool intel_lvds_port_enabled(struct drm_i915_private *i915,
89 			     i915_reg_t lvds_reg, enum pipe *pipe)
90 {
91 	u32 val;
92 
93 	val = intel_de_read(i915, lvds_reg);
94 
95 	/* asserts want to know the pipe even if the port is disabled */
96 	if (HAS_PCH_CPT(i915))
97 		*pipe = REG_FIELD_GET(LVDS_PIPE_SEL_MASK_CPT, val);
98 	else
99 		*pipe = REG_FIELD_GET(LVDS_PIPE_SEL_MASK, val);
100 
101 	return val & LVDS_PORT_EN;
102 }
103 
104 static bool intel_lvds_get_hw_state(struct intel_encoder *encoder,
105 				    enum pipe *pipe)
106 {
107 	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
108 	struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(encoder);
109 	intel_wakeref_t wakeref;
110 	bool ret;
111 
112 	wakeref = intel_display_power_get_if_enabled(i915, encoder->power_domain);
113 	if (!wakeref)
114 		return false;
115 
116 	ret = intel_lvds_port_enabled(i915, lvds_encoder->reg, pipe);
117 
118 	intel_display_power_put(i915, encoder->power_domain, wakeref);
119 
120 	return ret;
121 }
122 
123 static void intel_lvds_get_config(struct intel_encoder *encoder,
124 				  struct intel_crtc_state *crtc_state)
125 {
126 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
127 	struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(encoder);
128 	u32 tmp, flags = 0;
129 
130 	crtc_state->output_types |= BIT(INTEL_OUTPUT_LVDS);
131 
132 	tmp = intel_de_read(dev_priv, lvds_encoder->reg);
133 	if (tmp & LVDS_HSYNC_POLARITY)
134 		flags |= DRM_MODE_FLAG_NHSYNC;
135 	else
136 		flags |= DRM_MODE_FLAG_PHSYNC;
137 	if (tmp & LVDS_VSYNC_POLARITY)
138 		flags |= DRM_MODE_FLAG_NVSYNC;
139 	else
140 		flags |= DRM_MODE_FLAG_PVSYNC;
141 
142 	crtc_state->hw.adjusted_mode.flags |= flags;
143 
144 	if (DISPLAY_VER(dev_priv) < 5)
145 		crtc_state->gmch_pfit.lvds_border_bits =
146 			tmp & LVDS_BORDER_ENABLE;
147 
148 	/* gen2/3 store dither state in pfit control, needs to match */
149 	if (DISPLAY_VER(dev_priv) < 4) {
150 		tmp = intel_de_read(dev_priv, PFIT_CONTROL);
151 
152 		crtc_state->gmch_pfit.control |= tmp & PANEL_8TO6_DITHER_ENABLE;
153 	}
154 
155 	crtc_state->hw.adjusted_mode.crtc_clock = crtc_state->port_clock;
156 }
157 
158 static void intel_lvds_pps_get_hw_state(struct drm_i915_private *dev_priv,
159 					struct intel_lvds_pps *pps)
160 {
161 	u32 val;
162 
163 	pps->powerdown_on_reset = intel_de_read(dev_priv, PP_CONTROL(0)) & PANEL_POWER_RESET;
164 
165 	val = intel_de_read(dev_priv, PP_ON_DELAYS(0));
166 	pps->port = REG_FIELD_GET(PANEL_PORT_SELECT_MASK, val);
167 	pps->t1_t2 = REG_FIELD_GET(PANEL_POWER_UP_DELAY_MASK, val);
168 	pps->t5 = REG_FIELD_GET(PANEL_LIGHT_ON_DELAY_MASK, val);
169 
170 	val = intel_de_read(dev_priv, PP_OFF_DELAYS(0));
171 	pps->t3 = REG_FIELD_GET(PANEL_POWER_DOWN_DELAY_MASK, val);
172 	pps->tx = REG_FIELD_GET(PANEL_LIGHT_OFF_DELAY_MASK, val);
173 
174 	val = intel_de_read(dev_priv, PP_DIVISOR(0));
175 	pps->divider = REG_FIELD_GET(PP_REFERENCE_DIVIDER_MASK, val);
176 	val = REG_FIELD_GET(PANEL_POWER_CYCLE_DELAY_MASK, val);
177 	/*
178 	 * Remove the BSpec specified +1 (100ms) offset that accounts for a
179 	 * too short power-cycle delay due to the asynchronous programming of
180 	 * the register.
181 	 */
182 	if (val)
183 		val--;
184 	/* Convert from 100ms to 100us units */
185 	pps->t4 = val * 1000;
186 
187 	if (DISPLAY_VER(dev_priv) <= 4 &&
188 	    pps->t1_t2 == 0 && pps->t5 == 0 && pps->t3 == 0 && pps->tx == 0) {
189 		drm_dbg_kms(&dev_priv->drm,
190 			    "Panel power timings uninitialized, "
191 			    "setting defaults\n");
192 		/* Set T2 to 40ms and T5 to 200ms in 100 usec units */
193 		pps->t1_t2 = 40 * 10;
194 		pps->t5 = 200 * 10;
195 		/* Set T3 to 35ms and Tx to 200ms in 100 usec units */
196 		pps->t3 = 35 * 10;
197 		pps->tx = 200 * 10;
198 	}
199 
200 	drm_dbg(&dev_priv->drm, "LVDS PPS:t1+t2 %d t3 %d t4 %d t5 %d tx %d "
201 		"divider %d port %d powerdown_on_reset %d\n",
202 		pps->t1_t2, pps->t3, pps->t4, pps->t5, pps->tx,
203 		pps->divider, pps->port, pps->powerdown_on_reset);
204 }
205 
206 static void intel_lvds_pps_init_hw(struct drm_i915_private *dev_priv,
207 				   struct intel_lvds_pps *pps)
208 {
209 	u32 val;
210 
211 	val = intel_de_read(dev_priv, PP_CONTROL(0));
212 	drm_WARN_ON(&dev_priv->drm,
213 		    (val & PANEL_UNLOCK_MASK) != PANEL_UNLOCK_REGS);
214 	if (pps->powerdown_on_reset)
215 		val |= PANEL_POWER_RESET;
216 	intel_de_write(dev_priv, PP_CONTROL(0), val);
217 
218 	intel_de_write(dev_priv, PP_ON_DELAYS(0),
219 		       REG_FIELD_PREP(PANEL_PORT_SELECT_MASK, pps->port) |
220 		       REG_FIELD_PREP(PANEL_POWER_UP_DELAY_MASK, pps->t1_t2) |
221 		       REG_FIELD_PREP(PANEL_LIGHT_ON_DELAY_MASK, pps->t5));
222 
223 	intel_de_write(dev_priv, PP_OFF_DELAYS(0),
224 		       REG_FIELD_PREP(PANEL_POWER_DOWN_DELAY_MASK, pps->t3) |
225 		       REG_FIELD_PREP(PANEL_LIGHT_OFF_DELAY_MASK, pps->tx));
226 
227 	intel_de_write(dev_priv, PP_DIVISOR(0),
228 		       REG_FIELD_PREP(PP_REFERENCE_DIVIDER_MASK, pps->divider) |
229 		       REG_FIELD_PREP(PANEL_POWER_CYCLE_DELAY_MASK, DIV_ROUND_UP(pps->t4, 1000) + 1));
230 }
231 
232 static void intel_pre_enable_lvds(struct intel_atomic_state *state,
233 				  struct intel_encoder *encoder,
234 				  const struct intel_crtc_state *crtc_state,
235 				  const struct drm_connector_state *conn_state)
236 {
237 	struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(encoder);
238 	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
239 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
240 	const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
241 	enum pipe pipe = crtc->pipe;
242 	u32 temp;
243 
244 	if (HAS_PCH_SPLIT(i915)) {
245 		assert_fdi_rx_pll_disabled(i915, pipe);
246 		assert_shared_dpll_disabled(i915, crtc_state->shared_dpll);
247 	} else {
248 		assert_pll_disabled(i915, pipe);
249 	}
250 
251 	intel_lvds_pps_init_hw(i915, &lvds_encoder->init_pps);
252 
253 	temp = lvds_encoder->init_lvds_val;
254 	temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
255 
256 	if (HAS_PCH_CPT(i915)) {
257 		temp &= ~LVDS_PIPE_SEL_MASK_CPT;
258 		temp |= LVDS_PIPE_SEL_CPT(pipe);
259 	} else {
260 		temp &= ~LVDS_PIPE_SEL_MASK;
261 		temp |= LVDS_PIPE_SEL(pipe);
262 	}
263 
264 	/* set the corresponsding LVDS_BORDER bit */
265 	temp &= ~LVDS_BORDER_ENABLE;
266 	temp |= crtc_state->gmch_pfit.lvds_border_bits;
267 
268 	/*
269 	 * Set the B0-B3 data pairs corresponding to whether we're going to
270 	 * set the DPLLs for dual-channel mode or not.
271 	 */
272 	if (lvds_encoder->is_dual_link)
273 		temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
274 	else
275 		temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
276 
277 	/*
278 	 * It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
279 	 * appropriately here, but we need to look more thoroughly into how
280 	 * panels behave in the two modes. For now, let's just maintain the
281 	 * value we got from the BIOS.
282 	 */
283 	temp &= ~LVDS_A3_POWER_MASK;
284 	temp |= lvds_encoder->a3_power;
285 
286 	/*
287 	 * Set the dithering flag on LVDS as needed, note that there is no
288 	 * special lvds dither control bit on pch-split platforms, dithering is
289 	 * only controlled through the TRANSCONF reg.
290 	 */
291 	if (DISPLAY_VER(i915) == 4) {
292 		/*
293 		 * Bspec wording suggests that LVDS port dithering only exists
294 		 * for 18bpp panels.
295 		 */
296 		if (crtc_state->dither && crtc_state->pipe_bpp == 18)
297 			temp |= LVDS_ENABLE_DITHER;
298 		else
299 			temp &= ~LVDS_ENABLE_DITHER;
300 	}
301 	temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
302 	if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
303 		temp |= LVDS_HSYNC_POLARITY;
304 	if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
305 		temp |= LVDS_VSYNC_POLARITY;
306 
307 	intel_de_write(i915, lvds_encoder->reg, temp);
308 }
309 
310 /*
311  * Sets the power state for the panel.
312  */
313 static void intel_enable_lvds(struct intel_atomic_state *state,
314 			      struct intel_encoder *encoder,
315 			      const struct intel_crtc_state *crtc_state,
316 			      const struct drm_connector_state *conn_state)
317 {
318 	struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(encoder);
319 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
320 
321 	intel_de_rmw(dev_priv, lvds_encoder->reg, 0, LVDS_PORT_EN);
322 
323 	intel_de_rmw(dev_priv, PP_CONTROL(0), 0, PANEL_POWER_ON);
324 	intel_de_posting_read(dev_priv, lvds_encoder->reg);
325 
326 	if (intel_de_wait_for_set(dev_priv, PP_STATUS(0), PP_ON, 5000))
327 		drm_err(&dev_priv->drm,
328 			"timed out waiting for panel to power on\n");
329 
330 	intel_backlight_enable(crtc_state, conn_state);
331 }
332 
333 static void intel_disable_lvds(struct intel_atomic_state *state,
334 			       struct intel_encoder *encoder,
335 			       const struct intel_crtc_state *old_crtc_state,
336 			       const struct drm_connector_state *old_conn_state)
337 {
338 	struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(encoder);
339 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
340 
341 	intel_de_rmw(dev_priv, PP_CONTROL(0), PANEL_POWER_ON, 0);
342 	if (intel_de_wait_for_clear(dev_priv, PP_STATUS(0), PP_ON, 1000))
343 		drm_err(&dev_priv->drm,
344 			"timed out waiting for panel to power off\n");
345 
346 	intel_de_rmw(dev_priv, lvds_encoder->reg, LVDS_PORT_EN, 0);
347 	intel_de_posting_read(dev_priv, lvds_encoder->reg);
348 }
349 
350 static void gmch_disable_lvds(struct intel_atomic_state *state,
351 			      struct intel_encoder *encoder,
352 			      const struct intel_crtc_state *old_crtc_state,
353 			      const struct drm_connector_state *old_conn_state)
354 
355 {
356 	intel_backlight_disable(old_conn_state);
357 
358 	intel_disable_lvds(state, encoder, old_crtc_state, old_conn_state);
359 }
360 
361 static void pch_disable_lvds(struct intel_atomic_state *state,
362 			     struct intel_encoder *encoder,
363 			     const struct intel_crtc_state *old_crtc_state,
364 			     const struct drm_connector_state *old_conn_state)
365 {
366 	intel_backlight_disable(old_conn_state);
367 }
368 
369 static void pch_post_disable_lvds(struct intel_atomic_state *state,
370 				  struct intel_encoder *encoder,
371 				  const struct intel_crtc_state *old_crtc_state,
372 				  const struct drm_connector_state *old_conn_state)
373 {
374 	intel_disable_lvds(state, encoder, old_crtc_state, old_conn_state);
375 }
376 
377 static void intel_lvds_shutdown(struct intel_encoder *encoder)
378 {
379 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
380 
381 	if (intel_de_wait_for_clear(dev_priv, PP_STATUS(0), PP_CYCLE_DELAY_ACTIVE, 5000))
382 		drm_err(&dev_priv->drm,
383 			"timed out waiting for panel power cycle delay\n");
384 }
385 
386 static enum drm_mode_status
387 intel_lvds_mode_valid(struct drm_connector *_connector,
388 		      struct drm_display_mode *mode)
389 {
390 	struct intel_connector *connector = to_intel_connector(_connector);
391 	const struct drm_display_mode *fixed_mode =
392 		intel_panel_fixed_mode(connector, mode);
393 	int max_pixclk = to_i915(connector->base.dev)->max_dotclk_freq;
394 	enum drm_mode_status status;
395 
396 	if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
397 		return MODE_NO_DBLESCAN;
398 
399 	status = intel_panel_mode_valid(connector, mode);
400 	if (status != MODE_OK)
401 		return status;
402 
403 	if (fixed_mode->clock > max_pixclk)
404 		return MODE_CLOCK_HIGH;
405 
406 	return MODE_OK;
407 }
408 
409 static int intel_lvds_compute_config(struct intel_encoder *encoder,
410 				     struct intel_crtc_state *crtc_state,
411 				     struct drm_connector_state *conn_state)
412 {
413 	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
414 	struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(encoder);
415 	struct intel_connector *connector = lvds_encoder->attached_connector;
416 	struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
417 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
418 	unsigned int lvds_bpp;
419 	int ret;
420 
421 	/* Should never happen!! */
422 	if (DISPLAY_VER(i915) < 4 && crtc->pipe == 0) {
423 		drm_err(&i915->drm, "Can't support LVDS on pipe A\n");
424 		return -EINVAL;
425 	}
426 
427 	if (lvds_encoder->a3_power == LVDS_A3_POWER_UP)
428 		lvds_bpp = 8*3;
429 	else
430 		lvds_bpp = 6*3;
431 
432 	if (lvds_bpp != crtc_state->pipe_bpp && !crtc_state->bw_constrained) {
433 		drm_dbg_kms(&i915->drm,
434 			    "forcing display bpp (was %d) to LVDS (%d)\n",
435 			    crtc_state->pipe_bpp, lvds_bpp);
436 		crtc_state->pipe_bpp = lvds_bpp;
437 	}
438 
439 	crtc_state->output_format = INTEL_OUTPUT_FORMAT_RGB;
440 
441 	/*
442 	 * We have timings from the BIOS for the panel, put them in
443 	 * to the adjusted mode.  The CRTC will be set up for this mode,
444 	 * with the panel scaling set up to source from the H/VDisplay
445 	 * of the original mode.
446 	 */
447 	ret = intel_panel_compute_config(connector, adjusted_mode);
448 	if (ret)
449 		return ret;
450 
451 	if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
452 		return -EINVAL;
453 
454 	if (HAS_PCH_SPLIT(i915))
455 		crtc_state->has_pch_encoder = true;
456 
457 	ret = intel_panel_fitting(crtc_state, conn_state);
458 	if (ret)
459 		return ret;
460 
461 	/*
462 	 * XXX: It would be nice to support lower refresh rates on the
463 	 * panels to reduce power consumption, and perhaps match the
464 	 * user's requested refresh rate.
465 	 */
466 
467 	return 0;
468 }
469 
470 /*
471  * Return the list of DDC modes if available, or the BIOS fixed mode otherwise.
472  */
473 static int intel_lvds_get_modes(struct drm_connector *_connector)
474 {
475 	struct intel_connector *connector = to_intel_connector(_connector);
476 	const struct drm_edid *fixed_edid = connector->panel.fixed_edid;
477 
478 	/* Use panel fixed edid if we have one */
479 	if (!IS_ERR_OR_NULL(fixed_edid)) {
480 		drm_edid_connector_update(&connector->base, fixed_edid);
481 
482 		return drm_edid_connector_add_modes(&connector->base);
483 	}
484 
485 	return intel_panel_get_modes(connector);
486 }
487 
488 static const struct drm_connector_helper_funcs intel_lvds_connector_helper_funcs = {
489 	.get_modes = intel_lvds_get_modes,
490 	.mode_valid = intel_lvds_mode_valid,
491 	.atomic_check = intel_digital_connector_atomic_check,
492 };
493 
494 static const struct drm_connector_funcs intel_lvds_connector_funcs = {
495 	.detect = intel_panel_detect,
496 	.fill_modes = drm_helper_probe_single_connector_modes,
497 	.atomic_get_property = intel_digital_connector_atomic_get_property,
498 	.atomic_set_property = intel_digital_connector_atomic_set_property,
499 	.late_register = intel_connector_register,
500 	.early_unregister = intel_connector_unregister,
501 	.destroy = intel_connector_destroy,
502 	.atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
503 	.atomic_duplicate_state = intel_digital_connector_duplicate_state,
504 };
505 
506 static const struct drm_encoder_funcs intel_lvds_enc_funcs = {
507 	.destroy = intel_encoder_destroy,
508 };
509 
510 static int intel_no_lvds_dmi_callback(const struct dmi_system_id *id)
511 {
512 	DRM_INFO("Skipping LVDS initialization for %s\n", id->ident);
513 	return 1;
514 }
515 
516 /* These systems claim to have LVDS, but really don't */
517 static const struct dmi_system_id intel_no_lvds[] = {
518 	{
519 		.callback = intel_no_lvds_dmi_callback,
520 		.ident = "Apple Mac Mini (Core series)",
521 		.matches = {
522 			DMI_MATCH(DMI_SYS_VENDOR, "Apple"),
523 			DMI_MATCH(DMI_PRODUCT_NAME, "Macmini1,1"),
524 		},
525 	},
526 	{
527 		.callback = intel_no_lvds_dmi_callback,
528 		.ident = "Apple Mac Mini (Core 2 series)",
529 		.matches = {
530 			DMI_MATCH(DMI_SYS_VENDOR, "Apple"),
531 			DMI_MATCH(DMI_PRODUCT_NAME, "Macmini2,1"),
532 		},
533 	},
534 	{
535 		.callback = intel_no_lvds_dmi_callback,
536 		.ident = "MSI IM-945GSE-A",
537 		.matches = {
538 			DMI_MATCH(DMI_SYS_VENDOR, "MSI"),
539 			DMI_MATCH(DMI_PRODUCT_NAME, "A9830IMS"),
540 		},
541 	},
542 	{
543 		.callback = intel_no_lvds_dmi_callback,
544 		.ident = "Dell Studio Hybrid",
545 		.matches = {
546 			DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
547 			DMI_MATCH(DMI_PRODUCT_NAME, "Studio Hybrid 140g"),
548 		},
549 	},
550 	{
551 		.callback = intel_no_lvds_dmi_callback,
552 		.ident = "Dell OptiPlex FX170",
553 		.matches = {
554 			DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
555 			DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex FX170"),
556 		},
557 	},
558 	{
559 		.callback = intel_no_lvds_dmi_callback,
560 		.ident = "AOpen Mini PC",
561 		.matches = {
562 			DMI_MATCH(DMI_SYS_VENDOR, "AOpen"),
563 			DMI_MATCH(DMI_PRODUCT_NAME, "i965GMx-IF"),
564 		},
565 	},
566 	{
567 		.callback = intel_no_lvds_dmi_callback,
568 		.ident = "AOpen Mini PC MP915",
569 		.matches = {
570 			DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"),
571 			DMI_MATCH(DMI_BOARD_NAME, "i915GMx-F"),
572 		},
573 	},
574 	{
575 		.callback = intel_no_lvds_dmi_callback,
576 		.ident = "AOpen i915GMm-HFS",
577 		.matches = {
578 			DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"),
579 			DMI_MATCH(DMI_BOARD_NAME, "i915GMm-HFS"),
580 		},
581 	},
582 	{
583 		.callback = intel_no_lvds_dmi_callback,
584 		.ident = "AOpen i45GMx-I",
585 		.matches = {
586 			DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"),
587 			DMI_MATCH(DMI_BOARD_NAME, "i45GMx-I"),
588 		},
589 	},
590 	{
591 		.callback = intel_no_lvds_dmi_callback,
592 		.ident = "Aopen i945GTt-VFA",
593 		.matches = {
594 			DMI_MATCH(DMI_PRODUCT_VERSION, "AO00001JW"),
595 		},
596 	},
597 	{
598 		.callback = intel_no_lvds_dmi_callback,
599 		.ident = "Clientron U800",
600 		.matches = {
601 			DMI_MATCH(DMI_SYS_VENDOR, "Clientron"),
602 			DMI_MATCH(DMI_PRODUCT_NAME, "U800"),
603 		},
604 	},
605 	{
606 		.callback = intel_no_lvds_dmi_callback,
607 		.ident = "Clientron E830",
608 		.matches = {
609 			DMI_MATCH(DMI_SYS_VENDOR, "Clientron"),
610 			DMI_MATCH(DMI_PRODUCT_NAME, "E830"),
611 		},
612 	},
613 	{
614 		.callback = intel_no_lvds_dmi_callback,
615 		.ident = "Asus EeeBox PC EB1007",
616 		.matches = {
617 			DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK Computer INC."),
618 			DMI_MATCH(DMI_PRODUCT_NAME, "EB1007"),
619 		},
620 	},
621 	{
622 		.callback = intel_no_lvds_dmi_callback,
623 		.ident = "Asus AT5NM10T-I",
624 		.matches = {
625 			DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
626 			DMI_MATCH(DMI_BOARD_NAME, "AT5NM10T-I"),
627 		},
628 	},
629 	{
630 		.callback = intel_no_lvds_dmi_callback,
631 		.ident = "Hewlett-Packard HP t5740",
632 		.matches = {
633 			DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"),
634 			DMI_MATCH(DMI_PRODUCT_NAME, " t5740"),
635 		},
636 	},
637 	{
638 		.callback = intel_no_lvds_dmi_callback,
639 		.ident = "Hewlett-Packard t5745",
640 		.matches = {
641 			DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"),
642 			DMI_MATCH(DMI_PRODUCT_NAME, "hp t5745"),
643 		},
644 	},
645 	{
646 		.callback = intel_no_lvds_dmi_callback,
647 		.ident = "Hewlett-Packard st5747",
648 		.matches = {
649 			DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"),
650 			DMI_MATCH(DMI_PRODUCT_NAME, "hp st5747"),
651 		},
652 	},
653 	{
654 		.callback = intel_no_lvds_dmi_callback,
655 		.ident = "MSI Wind Box DC500",
656 		.matches = {
657 			DMI_MATCH(DMI_BOARD_VENDOR, "MICRO-STAR INTERNATIONAL CO., LTD"),
658 			DMI_MATCH(DMI_BOARD_NAME, "MS-7469"),
659 		},
660 	},
661 	{
662 		.callback = intel_no_lvds_dmi_callback,
663 		.ident = "Gigabyte GA-D525TUD",
664 		.matches = {
665 			DMI_MATCH(DMI_BOARD_VENDOR, "Gigabyte Technology Co., Ltd."),
666 			DMI_MATCH(DMI_BOARD_NAME, "D525TUD"),
667 		},
668 	},
669 	{
670 		.callback = intel_no_lvds_dmi_callback,
671 		.ident = "Supermicro X7SPA-H",
672 		.matches = {
673 			DMI_MATCH(DMI_SYS_VENDOR, "Supermicro"),
674 			DMI_MATCH(DMI_PRODUCT_NAME, "X7SPA-H"),
675 		},
676 	},
677 	{
678 		.callback = intel_no_lvds_dmi_callback,
679 		.ident = "Fujitsu Esprimo Q900",
680 		.matches = {
681 			DMI_MATCH(DMI_SYS_VENDOR, "FUJITSU"),
682 			DMI_MATCH(DMI_PRODUCT_NAME, "ESPRIMO Q900"),
683 		},
684 	},
685 	{
686 		.callback = intel_no_lvds_dmi_callback,
687 		.ident = "Intel D410PT",
688 		.matches = {
689 			DMI_MATCH(DMI_BOARD_VENDOR, "Intel"),
690 			DMI_MATCH(DMI_BOARD_NAME, "D410PT"),
691 		},
692 	},
693 	{
694 		.callback = intel_no_lvds_dmi_callback,
695 		.ident = "Intel D425KT",
696 		.matches = {
697 			DMI_MATCH(DMI_BOARD_VENDOR, "Intel"),
698 			DMI_EXACT_MATCH(DMI_BOARD_NAME, "D425KT"),
699 		},
700 	},
701 	{
702 		.callback = intel_no_lvds_dmi_callback,
703 		.ident = "Intel D510MO",
704 		.matches = {
705 			DMI_MATCH(DMI_BOARD_VENDOR, "Intel"),
706 			DMI_EXACT_MATCH(DMI_BOARD_NAME, "D510MO"),
707 		},
708 	},
709 	{
710 		.callback = intel_no_lvds_dmi_callback,
711 		.ident = "Intel D525MW",
712 		.matches = {
713 			DMI_MATCH(DMI_BOARD_VENDOR, "Intel"),
714 			DMI_EXACT_MATCH(DMI_BOARD_NAME, "D525MW"),
715 		},
716 	},
717 	{
718 		.callback = intel_no_lvds_dmi_callback,
719 		.ident = "Radiant P845",
720 		.matches = {
721 			DMI_MATCH(DMI_SYS_VENDOR, "Radiant Systems Inc"),
722 			DMI_MATCH(DMI_PRODUCT_NAME, "P845"),
723 		},
724 	},
725 
726 	{ }	/* terminating entry */
727 };
728 
729 static int intel_dual_link_lvds_callback(const struct dmi_system_id *id)
730 {
731 	DRM_INFO("Forcing lvds to dual link mode on %s\n", id->ident);
732 	return 1;
733 }
734 
735 static const struct dmi_system_id intel_dual_link_lvds[] = {
736 	{
737 		.callback = intel_dual_link_lvds_callback,
738 		.ident = "Apple MacBook Pro 15\" (2010)",
739 		.matches = {
740 			DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."),
741 			DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro6,2"),
742 		},
743 	},
744 	{
745 		.callback = intel_dual_link_lvds_callback,
746 		.ident = "Apple MacBook Pro 15\" (2011)",
747 		.matches = {
748 			DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."),
749 			DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro8,2"),
750 		},
751 	},
752 	{
753 		.callback = intel_dual_link_lvds_callback,
754 		.ident = "Apple MacBook Pro 15\" (2012)",
755 		.matches = {
756 			DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."),
757 			DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro9,1"),
758 		},
759 	},
760 	{ }	/* terminating entry */
761 };
762 
763 struct intel_encoder *intel_get_lvds_encoder(struct drm_i915_private *i915)
764 {
765 	struct intel_encoder *encoder;
766 
767 	for_each_intel_encoder(&i915->drm, encoder) {
768 		if (encoder->type == INTEL_OUTPUT_LVDS)
769 			return encoder;
770 	}
771 
772 	return NULL;
773 }
774 
775 bool intel_is_dual_link_lvds(struct drm_i915_private *i915)
776 {
777 	struct intel_encoder *encoder = intel_get_lvds_encoder(i915);
778 
779 	return encoder && to_lvds_encoder(encoder)->is_dual_link;
780 }
781 
782 static bool compute_is_dual_link_lvds(struct intel_lvds_encoder *lvds_encoder)
783 {
784 	struct drm_i915_private *i915 = to_i915(lvds_encoder->base.base.dev);
785 	struct intel_connector *connector = lvds_encoder->attached_connector;
786 	const struct drm_display_mode *fixed_mode =
787 		intel_panel_preferred_fixed_mode(connector);
788 	unsigned int val;
789 
790 	/* use the module option value if specified */
791 	if (i915->params.lvds_channel_mode > 0)
792 		return i915->params.lvds_channel_mode == 2;
793 
794 	/* single channel LVDS is limited to 112 MHz */
795 	if (fixed_mode->clock > 112999)
796 		return true;
797 
798 	if (dmi_check_system(intel_dual_link_lvds))
799 		return true;
800 
801 	/*
802 	 * BIOS should set the proper LVDS register value at boot, but
803 	 * in reality, it doesn't set the value when the lid is closed;
804 	 * we need to check "the value to be set" in VBT when LVDS
805 	 * register is uninitialized.
806 	 */
807 	val = intel_de_read(i915, lvds_encoder->reg);
808 	if (HAS_PCH_CPT(i915))
809 		val &= ~(LVDS_DETECTED | LVDS_PIPE_SEL_MASK_CPT);
810 	else
811 		val &= ~(LVDS_DETECTED | LVDS_PIPE_SEL_MASK);
812 	if (val == 0)
813 		val = connector->panel.vbt.bios_lvds_val;
814 
815 	return (val & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP;
816 }
817 
818 static void intel_lvds_add_properties(struct drm_connector *connector)
819 {
820 	intel_attach_scaling_mode_property(connector);
821 }
822 
823 /**
824  * intel_lvds_init - setup LVDS connectors on this device
825  * @i915: i915 device
826  *
827  * Create the connector, register the LVDS DDC bus, and try to figure out what
828  * modes we can display on the LVDS panel (if present).
829  */
830 void intel_lvds_init(struct drm_i915_private *i915)
831 {
832 	struct intel_lvds_encoder *lvds_encoder;
833 	struct intel_connector *connector;
834 	const struct drm_edid *drm_edid;
835 	struct intel_encoder *encoder;
836 	i915_reg_t lvds_reg;
837 	u32 lvds;
838 	u8 pin;
839 
840 	/* Skip init on machines we know falsely report LVDS */
841 	if (dmi_check_system(intel_no_lvds)) {
842 		drm_WARN(&i915->drm, !i915->display.vbt.int_lvds_support,
843 			 "Useless DMI match. Internal LVDS support disabled by VBT\n");
844 		return;
845 	}
846 
847 	if (!i915->display.vbt.int_lvds_support) {
848 		drm_dbg_kms(&i915->drm,
849 			    "Internal LVDS support disabled by VBT\n");
850 		return;
851 	}
852 
853 	if (HAS_PCH_SPLIT(i915))
854 		lvds_reg = PCH_LVDS;
855 	else
856 		lvds_reg = LVDS;
857 
858 	lvds = intel_de_read(i915, lvds_reg);
859 
860 	if (HAS_PCH_SPLIT(i915)) {
861 		if ((lvds & LVDS_DETECTED) == 0)
862 			return;
863 	}
864 
865 	pin = GMBUS_PIN_PANEL;
866 	if (!intel_bios_is_lvds_present(i915, &pin)) {
867 		if ((lvds & LVDS_PORT_EN) == 0) {
868 			drm_dbg_kms(&i915->drm,
869 				    "LVDS is not present in VBT\n");
870 			return;
871 		}
872 		drm_dbg_kms(&i915->drm,
873 			    "LVDS is not present in VBT, but enabled anyway\n");
874 	}
875 
876 	lvds_encoder = kzalloc(sizeof(*lvds_encoder), GFP_KERNEL);
877 	if (!lvds_encoder)
878 		return;
879 
880 	connector = intel_connector_alloc();
881 	if (!connector) {
882 		kfree(lvds_encoder);
883 		return;
884 	}
885 
886 	lvds_encoder->attached_connector = connector;
887 	encoder = &lvds_encoder->base;
888 
889 	drm_connector_init(&i915->drm, &connector->base, &intel_lvds_connector_funcs,
890 			   DRM_MODE_CONNECTOR_LVDS);
891 
892 	drm_encoder_init(&i915->drm, &encoder->base, &intel_lvds_enc_funcs,
893 			 DRM_MODE_ENCODER_LVDS, "LVDS");
894 
895 	encoder->enable = intel_enable_lvds;
896 	encoder->pre_enable = intel_pre_enable_lvds;
897 	encoder->compute_config = intel_lvds_compute_config;
898 	if (HAS_PCH_SPLIT(i915)) {
899 		encoder->disable = pch_disable_lvds;
900 		encoder->post_disable = pch_post_disable_lvds;
901 	} else {
902 		encoder->disable = gmch_disable_lvds;
903 	}
904 	encoder->get_hw_state = intel_lvds_get_hw_state;
905 	encoder->get_config = intel_lvds_get_config;
906 	encoder->update_pipe = intel_backlight_update;
907 	encoder->shutdown = intel_lvds_shutdown;
908 	connector->get_hw_state = intel_connector_get_hw_state;
909 
910 	intel_connector_attach_encoder(connector, encoder);
911 
912 	encoder->type = INTEL_OUTPUT_LVDS;
913 	encoder->power_domain = POWER_DOMAIN_PORT_OTHER;
914 	encoder->port = PORT_NONE;
915 	encoder->cloneable = 0;
916 	if (DISPLAY_VER(i915) < 4)
917 		encoder->pipe_mask = BIT(PIPE_B);
918 	else
919 		encoder->pipe_mask = ~0;
920 
921 	drm_connector_helper_add(&connector->base, &intel_lvds_connector_helper_funcs);
922 	connector->base.display_info.subpixel_order = SubPixelHorizontalRGB;
923 
924 	lvds_encoder->reg = lvds_reg;
925 
926 	intel_lvds_add_properties(&connector->base);
927 
928 	intel_lvds_pps_get_hw_state(i915, &lvds_encoder->init_pps);
929 	lvds_encoder->init_lvds_val = lvds;
930 
931 	/*
932 	 * LVDS discovery:
933 	 * 1) check for EDID on DDC
934 	 * 2) check for VBT data
935 	 * 3) check to see if LVDS is already on
936 	 *    if none of the above, no panel
937 	 */
938 
939 	/*
940 	 * Attempt to get the fixed panel mode from DDC.  Assume that the
941 	 * preferred mode is the right one.
942 	 */
943 	mutex_lock(&i915->drm.mode_config.mutex);
944 	if (vga_switcheroo_handler_flags() & VGA_SWITCHEROO_CAN_SWITCH_DDC) {
945 		const struct edid *edid;
946 
947 		/* FIXME: Make drm_get_edid_switcheroo() return drm_edid */
948 		edid = drm_get_edid_switcheroo(&connector->base,
949 					       intel_gmbus_get_adapter(i915, pin));
950 		if (edid) {
951 			drm_edid = drm_edid_alloc(edid, (edid->extensions + 1) * EDID_LENGTH);
952 			kfree(edid);
953 		} else {
954 			drm_edid = NULL;
955 		}
956 	} else {
957 		drm_edid = drm_edid_read_ddc(&connector->base,
958 					     intel_gmbus_get_adapter(i915, pin));
959 	}
960 	if (drm_edid) {
961 		if (drm_edid_connector_update(&connector->base, drm_edid) ||
962 		    !drm_edid_connector_add_modes(&connector->base)) {
963 			drm_edid_connector_update(&connector->base, NULL);
964 			drm_edid_free(drm_edid);
965 			drm_edid = ERR_PTR(-EINVAL);
966 		}
967 	} else {
968 		drm_edid = ERR_PTR(-ENOENT);
969 	}
970 	intel_bios_init_panel_late(i915, &connector->panel, NULL,
971 				   IS_ERR(drm_edid) ? NULL : drm_edid);
972 
973 	/* Try EDID first */
974 	intel_panel_add_edid_fixed_modes(connector, true);
975 
976 	/* Failed to get EDID, what about VBT? */
977 	if (!intel_panel_preferred_fixed_mode(connector))
978 		intel_panel_add_vbt_lfp_fixed_mode(connector);
979 
980 	/*
981 	 * If we didn't get a fixed mode from EDID or VBT, try checking
982 	 * if the panel is already turned on.  If so, assume that
983 	 * whatever is currently programmed is the correct mode.
984 	 */
985 	if (!intel_panel_preferred_fixed_mode(connector))
986 		intel_panel_add_encoder_fixed_mode(connector, encoder);
987 
988 	mutex_unlock(&i915->drm.mode_config.mutex);
989 
990 	/* If we still don't have a mode after all that, give up. */
991 	if (!intel_panel_preferred_fixed_mode(connector))
992 		goto failed;
993 
994 	intel_panel_init(connector, drm_edid);
995 
996 	intel_backlight_setup(connector, INVALID_PIPE);
997 
998 	lvds_encoder->is_dual_link = compute_is_dual_link_lvds(lvds_encoder);
999 	drm_dbg_kms(&i915->drm, "detected %s-link lvds configuration\n",
1000 		    lvds_encoder->is_dual_link ? "dual" : "single");
1001 
1002 	lvds_encoder->a3_power = lvds & LVDS_A3_POWER_MASK;
1003 
1004 	return;
1005 
1006 failed:
1007 	drm_dbg_kms(&i915->drm, "No LVDS modes found, disabling.\n");
1008 	drm_connector_cleanup(&connector->base);
1009 	drm_encoder_cleanup(&encoder->base);
1010 	kfree(lvds_encoder);
1011 	intel_connector_free(connector);
1012 	return;
1013 }
1014