1 /* SPDX-License-Identifier: MIT 2 * 3 * Copyright © 2025 Intel Corporation 4 */ 5 6 #ifndef __INTEL_LT_PHY_REGS_H__ 7 #define __INTEL_LT_PHY_REGS_H__ 8 9 #define XE3PLPD_MSGBUS_TIMEOUT_FAST_US 500 10 #define XE3PLPD_MACCLK_TURNON_LATENCY_MS 1 11 #define XE3PLPD_MACCLK_TURNON_LATENCY_US 21 12 #define XE3PLPD_MACCLK_TURNOFF_LATENCY_US 1 13 #define XE3PLPD_RATE_CALIB_DONE_LATENCY_US 50 14 #define XE3PLPD_RESET_START_LATENCY_US 10 15 #define XE3PLPD_PWRDN_TO_RDY_LATENCY_US 4 16 #define XE3PLPD_RESET_END_LATENCY_US 200 17 18 /* LT Phy MAC Register */ 19 #define LT_PHY_MAC_VDR _MMIO(0xC00) 20 #define LT_PHY_PCLKIN_GATE REG_BIT8(0) 21 22 /* LT Phy Pipe Spec Registers */ 23 #define LT_PHY_TXY_CTL8(idx) (0x408 + (0x200 * (idx))) 24 #define LT_PHY_TX_SWING_LEVEL_MASK REG_GENMASK8(7, 4) 25 #define LT_PHY_TX_SWING_LEVEL(val) REG_FIELD_PREP8(LT_PHY_TX_SWING_LEVEL_MASK, val) 26 #define LT_PHY_TX_SWING_MASK REG_BIT8(3) 27 #define LT_PHY_TX_SWING(val) REG_FIELD_PREP8(LT_PHY_TX_SWING_MASK, val) 28 29 #define LT_PHY_TXY_CTL2(idx) (0x402 + (0x200 * (idx))) 30 #define LT_PHY_TXY_CTL3(idx) (0x403 + (0x200 * (idx))) 31 #define LT_PHY_TXY_CTL4(idx) (0x404 + (0x200 * (idx))) 32 #define LT_PHY_TX_CURSOR_MASK REG_GENMASK8(5, 0) 33 #define LT_PHY_TX_CURSOR(val) REG_FIELD_PREP8(LT_PHY_TX_CURSOR_MASK, val) 34 35 #define LT_PHY_TXY_CTL10(idx) (0x40A + (0x200 * (idx))) 36 #define LT_PHY_TXY_CTL10_MAC(idx) _MMIO(LT_PHY_TXY_CTL10(idx)) 37 #define LT_PHY_TX_LANE_ENABLE REG_BIT8(0) 38 39 /* LT Phy Vendor Register */ 40 #define LT_PHY_VDR_0_CONFIG 0xC02 41 #define LT_PHY_VDR_DP_PLL_ENABLE REG_BIT(7) 42 #define LT_PHY_VDR_1_CONFIG 0xC03 43 #define LT_PHY_VDR_RATE_ENCODING_MASK REG_GENMASK8(6, 3) 44 #define LT_PHY_VDR_MODE_ENCODING_MASK REG_GENMASK8(2, 0) 45 #define LT_PHY_VDR_2_CONFIG 0xCC3 46 47 #define LT_PHY_VDR_X_ADDR_MSB(idx) (0xC04 + 0x6 * (idx)) 48 #define LT_PHY_VDR_X_ADDR_LSB(idx) (0xC05 + 0x6 * (idx)) 49 50 #define LT_PHY_VDR_X_DATAY(idx, y) ((0xC06 + (3 - (y))) + 0x6 * (idx)) 51 52 #define LT_PHY_RATE_UPDATE 0xCC4 53 #define LT_PHY_RATE_CONTROL_VDR_UPDATE REG_BIT8(0) 54 55 #define _XE3PLPD_PORT_BUF_CTL5(idx) _MMIO(_PICK_EVEN_2RANGES(idx, PORT_TC1, \ 56 _XELPDP_PORT_BUF_CTL1_LN0_A, \ 57 _XELPDP_PORT_BUF_CTL1_LN0_B, \ 58 _XELPDP_PORT_BUF_CTL1_LN0_USBC1, \ 59 _XELPDP_PORT_BUF_CTL1_LN0_USBC2) \ 60 + 0x34) 61 #define XE3PLPD_PORT_BUF_CTL5(port) _XE3PLPD_PORT_BUF_CTL5(__xe2lpd_port_idx(port)) 62 #define XE3PLPD_MACCLK_RESET_0 REG_BIT(11) 63 #define XE3PLPD_MACCLK_RATE_MASK REG_GENMASK(4, 0) 64 #define XE3PLPD_MACCLK_RATE_DEF REG_FIELD_PREP(XE3PLPD_MACCLK_RATE_MASK, 0x1F) 65 66 #define _XE3PLPD_PORT_P2M_MSGBUS_STATUS_P2P(idx, lane) _MMIO(_PICK_EVEN_2RANGES(idx, PORT_TC1, \ 67 _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_A, \ 68 _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_B, \ 69 _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_USBC1, \ 70 _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_USBC2) \ 71 + 0x60 + (lane) * 0x4) 72 #define XE3PLPD_PORT_P2M_MSGBUS_STATUS_P2P(port, lane) _XE3PLPD_PORT_P2M_MSGBUS_STATUS_P2P(__xe2lpd_port_idx(port), \ 73 lane) 74 #define XE3LPD_PORT_P2M_ADDR_MASK REG_GENMASK(11, 0) 75 #endif /* __INTEL_LT_PHY_REGS_H__ */ 76